1 // SPDX-License-Identifier: GPL-2.0-or-later
3 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
4 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
5 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
6 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
8 Based on the original rt2800pci.c and rt2800usb.c.
9 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
10 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
11 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
12 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
13 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
14 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
15 <http://rt2x00.serialmonkey.com>
21 Abstract: rt2800 generic device routines.
24 #include <linux/crc-ccitt.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/slab.h>
30 #include "rt2800lib.h"
33 static bool modparam_watchdog;
34 module_param_named(watchdog, modparam_watchdog, bool, S_IRUGO);
35 MODULE_PARM_DESC(watchdog, "Enable watchdog to detect tx/rx hangs and reset hardware if detected");
39 * All access to the CSR registers will go through the methods
40 * rt2800_register_read and rt2800_register_write.
41 * BBP and RF register require indirect register access,
42 * and use the CSR registers BBPCSR and RFCSR to achieve this.
43 * These indirect registers work with busy bits,
44 * and we will try maximal REGISTER_BUSY_COUNT times to access
45 * the register while taking a REGISTER_BUSY_DELAY us delay
46 * between each attampt. When the busy bit is still set at that time,
47 * the access attempt is considered to have failed,
48 * and we will print an error.
49 * The _lock versions must be used if you already hold the csr_mutex
51 #define WAIT_FOR_BBP(__dev, __reg) \
52 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
53 #define WAIT_FOR_RFCSR(__dev, __reg) \
54 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
55 #define WAIT_FOR_RFCSR_MT7620(__dev, __reg) \
56 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY_MT7620, \
58 #define WAIT_FOR_RF(__dev, __reg) \
59 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
60 #define WAIT_FOR_MCU(__dev, __reg) \
61 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
62 H2M_MAILBOX_CSR_OWNER, (__reg))
64 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
66 /* check for rt2872 on SoC */
67 if (!rt2x00_is_soc(rt2x00dev) ||
68 !rt2x00_rt(rt2x00dev, RT2872))
71 /* we know for sure that these rf chipsets are used on rt305x boards */
72 if (rt2x00_rf(rt2x00dev, RF3020) ||
73 rt2x00_rf(rt2x00dev, RF3021) ||
74 rt2x00_rf(rt2x00dev, RF3022))
77 rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n");
81 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
82 const unsigned int word, const u8 value)
86 mutex_lock(&rt2x00dev->csr_mutex);
89 * Wait until the BBP becomes available, afterwards we
90 * can safely write the new data into the register.
92 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
94 rt2x00_set_field32(®, BBP_CSR_CFG_VALUE, value);
95 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word);
96 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1);
97 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 0);
98 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1);
100 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
103 mutex_unlock(&rt2x00dev->csr_mutex);
106 static u8 rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, const unsigned int word)
111 mutex_lock(&rt2x00dev->csr_mutex);
114 * Wait until the BBP becomes available, afterwards we
115 * can safely write the read request into the register.
116 * After the data has been written, we wait until hardware
117 * returns the correct value, if at any time the register
118 * doesn't become available in time, reg will be 0xffffffff
119 * which means we return 0xff to the caller.
121 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
123 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word);
124 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1);
125 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 1);
126 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1);
128 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
130 WAIT_FOR_BBP(rt2x00dev, ®);
133 value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
135 mutex_unlock(&rt2x00dev->csr_mutex);
140 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
141 const unsigned int word, const u8 value)
145 mutex_lock(&rt2x00dev->csr_mutex);
148 * Wait until the RFCSR becomes available, afterwards we
149 * can safely write the new data into the register.
151 switch (rt2x00dev->chip.rt) {
153 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®)) {
155 rt2x00_set_field32(®, RF_CSR_CFG_DATA_MT7620, value);
156 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM_MT7620,
158 rt2x00_set_field32(®, RF_CSR_CFG_WRITE_MT7620, 1);
159 rt2x00_set_field32(®, RF_CSR_CFG_BUSY_MT7620, 1);
161 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
166 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) {
168 rt2x00_set_field32(®, RF_CSR_CFG_DATA, value);
169 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word);
170 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 1);
171 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1);
173 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
178 mutex_unlock(&rt2x00dev->csr_mutex);
181 static void rt2800_rfcsr_write_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
182 const unsigned int reg, const u8 value)
184 rt2800_rfcsr_write(rt2x00dev, (reg | (bank << 6)), value);
187 static void rt2800_rfcsr_write_chanreg(struct rt2x00_dev *rt2x00dev,
188 const unsigned int reg, const u8 value)
190 rt2800_rfcsr_write_bank(rt2x00dev, 4, reg, value);
191 rt2800_rfcsr_write_bank(rt2x00dev, 6, reg, value);
194 static void rt2800_rfcsr_write_dccal(struct rt2x00_dev *rt2x00dev,
195 const unsigned int reg, const u8 value)
197 rt2800_rfcsr_write_bank(rt2x00dev, 5, reg, value);
198 rt2800_rfcsr_write_bank(rt2x00dev, 7, reg, value);
201 static u8 rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
202 const unsigned int word)
207 mutex_lock(&rt2x00dev->csr_mutex);
210 * Wait until the RFCSR becomes available, afterwards we
211 * can safely write the read request into the register.
212 * After the data has been written, we wait until hardware
213 * returns the correct value, if at any time the register
214 * doesn't become available in time, reg will be 0xffffffff
215 * which means we return 0xff to the caller.
217 switch (rt2x00dev->chip.rt) {
219 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®)) {
221 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM_MT7620,
223 rt2x00_set_field32(®, RF_CSR_CFG_WRITE_MT7620, 0);
224 rt2x00_set_field32(®, RF_CSR_CFG_BUSY_MT7620, 1);
226 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
228 WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®);
231 value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA_MT7620);
235 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) {
237 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word);
238 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 0);
239 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1);
241 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
243 WAIT_FOR_RFCSR(rt2x00dev, ®);
246 value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
250 mutex_unlock(&rt2x00dev->csr_mutex);
255 static u8 rt2800_rfcsr_read_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
256 const unsigned int reg)
258 return rt2800_rfcsr_read(rt2x00dev, (reg | (bank << 6)));
261 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
262 const unsigned int word, const u32 value)
266 mutex_lock(&rt2x00dev->csr_mutex);
269 * Wait until the RF becomes available, afterwards we
270 * can safely write the new data into the register.
272 if (WAIT_FOR_RF(rt2x00dev, ®)) {
274 rt2x00_set_field32(®, RF_CSR_CFG0_REG_VALUE_BW, value);
275 rt2x00_set_field32(®, RF_CSR_CFG0_STANDBYMODE, 0);
276 rt2x00_set_field32(®, RF_CSR_CFG0_SEL, 0);
277 rt2x00_set_field32(®, RF_CSR_CFG0_BUSY, 1);
279 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
280 rt2x00_rf_write(rt2x00dev, word, value);
283 mutex_unlock(&rt2x00dev->csr_mutex);
286 static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = {
287 [EEPROM_CHIP_ID] = 0x0000,
288 [EEPROM_VERSION] = 0x0001,
289 [EEPROM_MAC_ADDR_0] = 0x0002,
290 [EEPROM_MAC_ADDR_1] = 0x0003,
291 [EEPROM_MAC_ADDR_2] = 0x0004,
292 [EEPROM_NIC_CONF0] = 0x001a,
293 [EEPROM_NIC_CONF1] = 0x001b,
294 [EEPROM_FREQ] = 0x001d,
295 [EEPROM_LED_AG_CONF] = 0x001e,
296 [EEPROM_LED_ACT_CONF] = 0x001f,
297 [EEPROM_LED_POLARITY] = 0x0020,
298 [EEPROM_NIC_CONF2] = 0x0021,
299 [EEPROM_LNA] = 0x0022,
300 [EEPROM_RSSI_BG] = 0x0023,
301 [EEPROM_RSSI_BG2] = 0x0024,
302 [EEPROM_TXMIXER_GAIN_BG] = 0x0024, /* overlaps with RSSI_BG2 */
303 [EEPROM_RSSI_A] = 0x0025,
304 [EEPROM_RSSI_A2] = 0x0026,
305 [EEPROM_TXMIXER_GAIN_A] = 0x0026, /* overlaps with RSSI_A2 */
306 [EEPROM_EIRP_MAX_TX_POWER] = 0x0027,
307 [EEPROM_TXPOWER_DELTA] = 0x0028,
308 [EEPROM_TXPOWER_BG1] = 0x0029,
309 [EEPROM_TXPOWER_BG2] = 0x0030,
310 [EEPROM_TSSI_BOUND_BG1] = 0x0037,
311 [EEPROM_TSSI_BOUND_BG2] = 0x0038,
312 [EEPROM_TSSI_BOUND_BG3] = 0x0039,
313 [EEPROM_TSSI_BOUND_BG4] = 0x003a,
314 [EEPROM_TSSI_BOUND_BG5] = 0x003b,
315 [EEPROM_TXPOWER_A1] = 0x003c,
316 [EEPROM_TXPOWER_A2] = 0x0053,
317 [EEPROM_TXPOWER_INIT] = 0x0068,
318 [EEPROM_TSSI_BOUND_A1] = 0x006a,
319 [EEPROM_TSSI_BOUND_A2] = 0x006b,
320 [EEPROM_TSSI_BOUND_A3] = 0x006c,
321 [EEPROM_TSSI_BOUND_A4] = 0x006d,
322 [EEPROM_TSSI_BOUND_A5] = 0x006e,
323 [EEPROM_TXPOWER_BYRATE] = 0x006f,
324 [EEPROM_BBP_START] = 0x0078,
327 static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = {
328 [EEPROM_CHIP_ID] = 0x0000,
329 [EEPROM_VERSION] = 0x0001,
330 [EEPROM_MAC_ADDR_0] = 0x0002,
331 [EEPROM_MAC_ADDR_1] = 0x0003,
332 [EEPROM_MAC_ADDR_2] = 0x0004,
333 [EEPROM_NIC_CONF0] = 0x001a,
334 [EEPROM_NIC_CONF1] = 0x001b,
335 [EEPROM_NIC_CONF2] = 0x001c,
336 [EEPROM_EIRP_MAX_TX_POWER] = 0x0020,
337 [EEPROM_FREQ] = 0x0022,
338 [EEPROM_LED_AG_CONF] = 0x0023,
339 [EEPROM_LED_ACT_CONF] = 0x0024,
340 [EEPROM_LED_POLARITY] = 0x0025,
341 [EEPROM_LNA] = 0x0026,
342 [EEPROM_EXT_LNA2] = 0x0027,
343 [EEPROM_RSSI_BG] = 0x0028,
344 [EEPROM_RSSI_BG2] = 0x0029,
345 [EEPROM_RSSI_A] = 0x002a,
346 [EEPROM_RSSI_A2] = 0x002b,
347 [EEPROM_TXPOWER_BG1] = 0x0030,
348 [EEPROM_TXPOWER_BG2] = 0x0037,
349 [EEPROM_EXT_TXPOWER_BG3] = 0x003e,
350 [EEPROM_TSSI_BOUND_BG1] = 0x0045,
351 [EEPROM_TSSI_BOUND_BG2] = 0x0046,
352 [EEPROM_TSSI_BOUND_BG3] = 0x0047,
353 [EEPROM_TSSI_BOUND_BG4] = 0x0048,
354 [EEPROM_TSSI_BOUND_BG5] = 0x0049,
355 [EEPROM_TXPOWER_A1] = 0x004b,
356 [EEPROM_TXPOWER_A2] = 0x0065,
357 [EEPROM_EXT_TXPOWER_A3] = 0x007f,
358 [EEPROM_TSSI_BOUND_A1] = 0x009a,
359 [EEPROM_TSSI_BOUND_A2] = 0x009b,
360 [EEPROM_TSSI_BOUND_A3] = 0x009c,
361 [EEPROM_TSSI_BOUND_A4] = 0x009d,
362 [EEPROM_TSSI_BOUND_A5] = 0x009e,
363 [EEPROM_TXPOWER_BYRATE] = 0x00a0,
366 static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev,
367 const enum rt2800_eeprom_word word)
369 const unsigned int *map;
372 if (WARN_ONCE(word >= EEPROM_WORD_COUNT,
373 "%s: invalid EEPROM word %d\n",
374 wiphy_name(rt2x00dev->hw->wiphy), word))
377 if (rt2x00_rt(rt2x00dev, RT3593) ||
378 rt2x00_rt(rt2x00dev, RT3883))
379 map = rt2800_eeprom_map_ext;
381 map = rt2800_eeprom_map;
385 /* Index 0 is valid only for EEPROM_CHIP_ID.
386 * Otherwise it means that the offset of the
387 * given word is not initialized in the map,
388 * or that the field is not usable on the
391 WARN_ONCE(word != EEPROM_CHIP_ID && index == 0,
392 "%s: invalid access of EEPROM word %d\n",
393 wiphy_name(rt2x00dev->hw->wiphy), word);
398 static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev,
399 const enum rt2800_eeprom_word word)
403 index = rt2800_eeprom_word_index(rt2x00dev, word);
404 return rt2x00_eeprom_addr(rt2x00dev, index);
407 static u16 rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev,
408 const enum rt2800_eeprom_word word)
412 index = rt2800_eeprom_word_index(rt2x00dev, word);
413 return rt2x00_eeprom_read(rt2x00dev, index);
416 static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev,
417 const enum rt2800_eeprom_word word, u16 data)
421 index = rt2800_eeprom_word_index(rt2x00dev, word);
422 rt2x00_eeprom_write(rt2x00dev, index, data);
425 static u16 rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev,
426 const enum rt2800_eeprom_word array,
431 index = rt2800_eeprom_word_index(rt2x00dev, array);
432 return rt2x00_eeprom_read(rt2x00dev, index + offset);
435 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
440 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
441 rt2x00_set_field32(®, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
442 rt2x00_set_field32(®, FRC_WL_ANT_SET, 1);
443 rt2x00_set_field32(®, WLAN_CLK_EN, 0);
444 rt2x00_set_field32(®, WLAN_EN, 1);
445 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
447 udelay(REGISTER_BUSY_DELAY);
452 * Check PLL_LD & XTAL_RDY.
454 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
455 reg = rt2800_register_read(rt2x00dev, CMB_CTRL);
456 if (rt2x00_get_field32(reg, PLL_LD) &&
457 rt2x00_get_field32(reg, XTAL_RDY))
459 udelay(REGISTER_BUSY_DELAY);
462 if (i >= REGISTER_BUSY_COUNT) {
467 rt2800_register_write(rt2x00dev, 0x58, 0x018);
468 udelay(REGISTER_BUSY_DELAY);
469 rt2800_register_write(rt2x00dev, 0x58, 0x418);
470 udelay(REGISTER_BUSY_DELAY);
471 rt2800_register_write(rt2x00dev, 0x58, 0x618);
472 udelay(REGISTER_BUSY_DELAY);
478 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
479 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 0);
480 rt2x00_set_field32(®, WLAN_CLK_EN, 1);
481 rt2x00_set_field32(®, WLAN_RESET, 1);
482 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
484 rt2x00_set_field32(®, WLAN_RESET, 0);
485 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
487 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
488 } while (count != 0);
493 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
494 const u8 command, const u8 token,
495 const u8 arg0, const u8 arg1)
500 * SOC devices don't support MCU requests.
502 if (rt2x00_is_soc(rt2x00dev))
505 mutex_lock(&rt2x00dev->csr_mutex);
508 * Wait until the MCU becomes available, afterwards we
509 * can safely write the new data into the register.
511 if (WAIT_FOR_MCU(rt2x00dev, ®)) {
512 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1);
513 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token);
514 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0);
515 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1);
516 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
519 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command);
520 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
523 mutex_unlock(&rt2x00dev->csr_mutex);
525 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
527 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
532 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
533 reg = rt2800_register_read(rt2x00dev, MAC_CSR0);
534 if (reg && reg != ~0)
539 rt2x00_err(rt2x00dev, "Unstable hardware\n");
542 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
544 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
550 * Some devices are really slow to respond here. Wait a whole second
553 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
554 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
555 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
556 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
562 rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg);
565 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
567 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
571 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
572 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
573 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
574 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
575 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
576 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
577 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
579 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
581 void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev,
582 unsigned short *txwi_size,
583 unsigned short *rxwi_size)
585 switch (rt2x00dev->chip.rt) {
588 *txwi_size = TXWI_DESC_SIZE_4WORDS;
589 *rxwi_size = RXWI_DESC_SIZE_5WORDS;
594 *txwi_size = TXWI_DESC_SIZE_5WORDS;
595 *rxwi_size = RXWI_DESC_SIZE_6WORDS;
599 *txwi_size = TXWI_DESC_SIZE_4WORDS;
600 *rxwi_size = RXWI_DESC_SIZE_4WORDS;
604 EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size);
606 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
612 * The last 2 bytes in the firmware array are the crc checksum itself,
613 * this means that we should never pass those 2 bytes to the crc
616 fw_crc = (data[len - 2] << 8 | data[len - 1]);
619 * Use the crc ccitt algorithm.
620 * This will return the same value as the legacy driver which
621 * used bit ordering reversion on the both the firmware bytes
622 * before input input as well as on the final output.
623 * Obviously using crc ccitt directly is much more efficient.
625 crc = crc_ccitt(~0, data, len - 2);
628 * There is a small difference between the crc-itu-t + bitrev and
629 * the crc-ccitt crc calculation. In the latter method the 2 bytes
630 * will be swapped, use swab16 to convert the crc to the correct
635 return fw_crc == crc;
638 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
639 const u8 *data, const size_t len)
646 * PCI(e) & SOC devices require firmware with a length
647 * of 8kb. USB devices require firmware files with a length
648 * of 4kb. Certain USB chipsets however require different firmware,
649 * which Ralink only provides attached to the original firmware
650 * file. Thus for USB devices, firmware files have a length
651 * which is a multiple of 4kb. The firmware for rt3290 chip also
652 * have a length which is a multiple of 4kb.
654 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
661 * Validate the firmware length
663 if (len != fw_len && (!multiple || (len % fw_len) != 0))
664 return FW_BAD_LENGTH;
667 * Check if the chipset requires one of the upper parts
670 if (rt2x00_is_usb(rt2x00dev) &&
671 !rt2x00_rt(rt2x00dev, RT2860) &&
672 !rt2x00_rt(rt2x00dev, RT2872) &&
673 !rt2x00_rt(rt2x00dev, RT3070) &&
674 ((len / fw_len) == 1))
675 return FW_BAD_VERSION;
678 * 8kb firmware files must be checked as if it were
679 * 2 separate firmware files.
681 while (offset < len) {
682 if (!rt2800_check_firmware_crc(data + offset, fw_len))
690 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
692 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
693 const u8 *data, const size_t len)
699 if (rt2x00_rt(rt2x00dev, RT3290)) {
700 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
706 * If driver doesn't wake up firmware here,
707 * rt2800_load_firmware will hang forever when interface is up again.
709 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
712 * Wait for stable hardware.
714 if (rt2800_wait_csr_ready(rt2x00dev))
717 if (rt2x00_is_pci(rt2x00dev)) {
718 if (rt2x00_rt(rt2x00dev, RT3290) ||
719 rt2x00_rt(rt2x00dev, RT3572) ||
720 rt2x00_rt(rt2x00dev, RT5390) ||
721 rt2x00_rt(rt2x00dev, RT5392)) {
722 reg = rt2800_register_read(rt2x00dev, AUX_CTRL);
723 rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1);
724 rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1);
725 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
727 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
730 rt2800_disable_wpdma(rt2x00dev);
733 * Write firmware to the device.
735 rt2800_drv_write_firmware(rt2x00dev, data, len);
738 * Wait for device to stabilize.
740 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
741 reg = rt2800_register_read(rt2x00dev, PBF_SYS_CTRL);
742 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
747 if (i == REGISTER_BUSY_COUNT) {
748 rt2x00_err(rt2x00dev, "PBF system register not ready\n");
753 * Disable DMA, will be reenabled later when enabling
756 rt2800_disable_wpdma(rt2x00dev);
759 * Initialize firmware.
761 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
762 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
763 if (rt2x00_is_usb(rt2x00dev)) {
764 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
765 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
771 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
773 void rt2800_write_tx_data(struct queue_entry *entry,
774 struct txentry_desc *txdesc)
776 __le32 *txwi = rt2800_drv_get_txwi(entry);
781 * Initialize TX Info descriptor
783 word = rt2x00_desc_read(txwi, 0);
784 rt2x00_set_field32(&word, TXWI_W0_FRAG,
785 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
786 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
787 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
788 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
789 rt2x00_set_field32(&word, TXWI_W0_TS,
790 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
791 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
792 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
793 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
794 txdesc->u.ht.mpdu_density);
795 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
796 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
797 rt2x00_set_field32(&word, TXWI_W0_BW,
798 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
799 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
800 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
801 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
802 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
803 rt2x00_desc_write(txwi, 0, word);
805 word = rt2x00_desc_read(txwi, 1);
806 rt2x00_set_field32(&word, TXWI_W1_ACK,
807 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
808 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
809 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
810 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
811 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
812 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
813 txdesc->key_idx : txdesc->u.ht.wcid);
814 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
816 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
817 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
818 rt2x00_desc_write(txwi, 1, word);
821 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
822 * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
823 * When TXD_W3_WIV is set to 1 it will use the IV data
824 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
825 * crypto entry in the registers should be used to encrypt the frame.
827 * Nulify all remaining words as well, we don't know how to program them.
829 for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++)
830 _rt2x00_desc_write(txwi, i, 0);
832 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
834 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
836 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
837 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
838 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
844 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
845 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG);
846 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
847 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
848 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
849 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
851 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A);
852 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
853 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
854 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
855 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
859 * Convert the value from the descriptor into the RSSI value
860 * If the value in the descriptor is 0, it is considered invalid
861 * and the default (extremely low) rssi value is assumed
863 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
864 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
865 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
868 * mac80211 only accepts a single RSSI value. Calculating the
869 * average doesn't deliver a fair answer either since -60:-60 would
870 * be considered equally good as -50:-70 while the second is the one
871 * which gives less energy...
873 rssi0 = max(rssi0, rssi1);
874 return (int)max(rssi0, rssi2);
877 void rt2800_process_rxwi(struct queue_entry *entry,
878 struct rxdone_entry_desc *rxdesc)
880 __le32 *rxwi = (__le32 *) entry->skb->data;
883 word = rt2x00_desc_read(rxwi, 0);
885 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
886 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
888 word = rt2x00_desc_read(rxwi, 1);
890 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
891 rxdesc->enc_flags |= RX_ENC_FLAG_SHORT_GI;
893 if (rt2x00_get_field32(word, RXWI_W1_BW))
894 rxdesc->bw = RATE_INFO_BW_40;
897 * Detect RX rate, always use MCS as signal type.
899 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
900 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
901 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
904 * Mask of 0x8 bit to remove the short preamble flag.
906 if (rxdesc->rate_mode == RATE_MODE_CCK)
907 rxdesc->signal &= ~0x8;
909 word = rt2x00_desc_read(rxwi, 2);
912 * Convert descriptor AGC value to RSSI value.
914 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
916 * Remove RXWI descriptor from start of the buffer.
918 skb_pull(entry->skb, entry->queue->winfo_size);
920 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
922 static void rt2800_rate_from_status(struct skb_frame_desc *skbdesc,
923 u32 status, enum nl80211_band band)
926 u8 idx = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
928 switch (rt2x00_get_field32(status, TX_STA_FIFO_PHYMODE)) {
929 case RATE_MODE_HT_GREENFIELD:
930 flags |= IEEE80211_TX_RC_GREEN_FIELD;
932 case RATE_MODE_HT_MIX:
933 flags |= IEEE80211_TX_RC_MCS;
936 if (band == NL80211_BAND_2GHZ)
945 if (rt2x00_get_field32(status, TX_STA_FIFO_BW))
946 flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
948 if (rt2x00_get_field32(status, TX_STA_FIFO_SGI))
949 flags |= IEEE80211_TX_RC_SHORT_GI;
951 skbdesc->tx_rate_idx = idx;
952 skbdesc->tx_rate_flags = flags;
955 static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg)
960 int tx_wcid, tx_ack, tx_pid, is_agg;
963 * This frames has returned with an IO error,
964 * so the status report is not intended for this
967 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags))
970 wcid = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
971 ack = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
972 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
973 is_agg = rt2x00_get_field32(reg, TX_STA_FIFO_TX_AGGRE);
976 * Validate if this TX status report is intended for
977 * this entry by comparing the WCID/ACK/PID fields.
979 txwi = rt2800_drv_get_txwi(entry);
981 word = rt2x00_desc_read(txwi, 1);
982 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
983 tx_ack = rt2x00_get_field32(word, TXWI_W1_ACK);
984 tx_pid = rt2x00_get_field32(word, TXWI_W1_PACKETID);
986 if (wcid != tx_wcid || ack != tx_ack || (!is_agg && pid != tx_pid)) {
987 rt2x00_dbg(entry->queue->rt2x00dev,
988 "TX status report missed for queue %d entry %d\n",
989 entry->queue->qid, entry->entry_idx);
996 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi,
999 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1000 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1001 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1002 struct txdone_entry_desc txdesc;
1005 int aggr, ampdu, wcid, ack_req;
1008 * Obtain the status about this packet.
1011 word = rt2x00_desc_read(txwi, 0);
1013 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
1014 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
1016 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
1017 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
1018 wcid = rt2x00_get_field32(status, TX_STA_FIFO_WCID);
1019 ack_req = rt2x00_get_field32(status, TX_STA_FIFO_TX_ACK_REQUIRED);
1022 * If a frame was meant to be sent as a single non-aggregated MPDU
1023 * but ended up in an aggregate the used tx rate doesn't correlate
1024 * with the one specified in the TXWI as the whole aggregate is sent
1025 * with the same rate.
1027 * For example: two frames are sent to rt2x00, the first one sets
1028 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
1029 * and requests MCS15. If the hw aggregates both frames into one
1030 * AMDPU the tx status for both frames will contain MCS7 although
1031 * the frame was sent successfully.
1033 * Hence, replace the requested rate with the real tx rate to not
1034 * confuse the rate control algortihm by providing clearly wrong
1037 * FIXME: if we do not find matching entry, we tell that frame was
1038 * posted without any retries. We need to find a way to fix that
1039 * and provide retry count.
1041 if (unlikely((aggr == 1 && ampdu == 0 && real_mcs != mcs)) || !match) {
1042 rt2800_rate_from_status(skbdesc, status, rt2x00dev->curr_band);
1046 if (aggr == 1 || ampdu == 1)
1047 __set_bit(TXDONE_AMPDU, &txdesc.flags);
1050 __set_bit(TXDONE_NO_ACK_REQ, &txdesc.flags);
1053 * Ralink has a retry mechanism using a global fallback
1054 * table. We setup this fallback table to try the immediate
1055 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
1056 * always contains the MCS used for the last transmission, be
1057 * it successful or not.
1059 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
1061 * Transmission succeeded. The number of retries is
1064 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1065 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
1068 * Transmission failed. The number of retries is
1069 * always 7 in this case (for a total number of 8
1072 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1073 txdesc.retry = rt2x00dev->long_retry;
1077 * the frame was retried at least once
1078 * -> hw used fallback rates
1081 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
1084 /* RCU assures non-null sta will not be freed by mac80211. */
1086 if (likely(wcid >= WCID_START && wcid <= WCID_END))
1087 skbdesc->sta = drv_data->wcid_to_sta[wcid - WCID_START];
1089 skbdesc->sta = NULL;
1090 rt2x00lib_txdone_nomatch(entry, &txdesc);
1093 rt2x00lib_txdone(entry, &txdesc);
1096 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
1098 void rt2800_txdone(struct rt2x00_dev *rt2x00dev, unsigned int quota)
1100 struct data_queue *queue;
1101 struct queue_entry *entry;
1106 while (quota-- > 0 && kfifo_get(&rt2x00dev->txstatus_fifo, ®)) {
1108 * TX_STA_FIFO_PID_QUEUE is a 2-bit field, thus qid is
1109 * guaranteed to be one of the TX QIDs .
1111 qid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE);
1112 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
1114 if (unlikely(rt2x00queue_empty(queue))) {
1115 rt2x00_dbg(rt2x00dev, "Got TX status for an empty queue %u, dropping\n",
1120 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1122 if (unlikely(test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) ||
1123 !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))) {
1124 rt2x00_warn(rt2x00dev, "Data pending for entry %u in queue %u\n",
1125 entry->entry_idx, qid);
1129 match = rt2800_txdone_entry_check(entry, reg);
1130 rt2800_txdone_entry(entry, reg, rt2800_drv_get_txwi(entry), match);
1133 EXPORT_SYMBOL_GPL(rt2800_txdone);
1135 static inline bool rt2800_entry_txstatus_timeout(struct rt2x00_dev *rt2x00dev,
1136 struct queue_entry *entry)
1141 if (!test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))
1144 if (test_bit(DEVICE_STATE_FLUSHING, &rt2x00dev->flags))
1145 tout = msecs_to_jiffies(50);
1147 tout = msecs_to_jiffies(2000);
1149 ret = time_after(jiffies, entry->last_action + tout);
1151 rt2x00_dbg(entry->queue->rt2x00dev,
1152 "TX status timeout for entry %d in queue %d\n",
1153 entry->entry_idx, entry->queue->qid);
1157 bool rt2800_txstatus_timeout(struct rt2x00_dev *rt2x00dev)
1159 struct data_queue *queue;
1160 struct queue_entry *entry;
1162 tx_queue_for_each(rt2x00dev, queue) {
1163 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1164 if (rt2800_entry_txstatus_timeout(rt2x00dev, entry))
1170 EXPORT_SYMBOL_GPL(rt2800_txstatus_timeout);
1173 * test if there is an entry in any TX queue for which DMA is done
1174 * but the TX status has not been returned yet
1176 bool rt2800_txstatus_pending(struct rt2x00_dev *rt2x00dev)
1178 struct data_queue *queue;
1180 tx_queue_for_each(rt2x00dev, queue) {
1181 if (rt2x00queue_get_entry(queue, Q_INDEX_DMA_DONE) !=
1182 rt2x00queue_get_entry(queue, Q_INDEX_DONE))
1187 EXPORT_SYMBOL_GPL(rt2800_txstatus_pending);
1189 void rt2800_txdone_nostatus(struct rt2x00_dev *rt2x00dev)
1191 struct data_queue *queue;
1192 struct queue_entry *entry;
1195 * Process any trailing TX status reports for IO failures,
1196 * we loop until we find the first non-IO error entry. This
1197 * can either be a frame which is free, is being uploaded,
1198 * or has completed the upload but didn't have an entry
1199 * in the TX_STAT_FIFO register yet.
1201 tx_queue_for_each(rt2x00dev, queue) {
1202 while (!rt2x00queue_empty(queue)) {
1203 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1205 if (test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) ||
1206 !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))
1209 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags) ||
1210 rt2800_entry_txstatus_timeout(rt2x00dev, entry))
1211 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE);
1217 EXPORT_SYMBOL_GPL(rt2800_txdone_nostatus);
1219 static int rt2800_check_hung(struct data_queue *queue)
1221 unsigned int cur_idx = rt2800_drv_get_dma_done(queue);
1223 if (queue->wd_idx != cur_idx)
1224 queue->wd_count = 0;
1228 return queue->wd_count > 16;
1231 void rt2800_watchdog(struct rt2x00_dev *rt2x00dev)
1233 struct data_queue *queue;
1234 bool hung_tx = false;
1235 bool hung_rx = false;
1237 if (test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags))
1240 queue_for_each(rt2x00dev, queue) {
1241 switch (queue->qid) {
1247 if (rt2x00queue_empty(queue))
1249 hung_tx = rt2800_check_hung(queue);
1252 /* For station mode we should reactive at least
1253 * beacons. TODO: need to find good way detect
1254 * RX hung for AP mode.
1256 if (rt2x00dev->intf_sta_count == 0)
1258 hung_rx = rt2800_check_hung(queue);
1266 rt2x00_warn(rt2x00dev, "Watchdog TX hung detected\n");
1269 rt2x00_warn(rt2x00dev, "Watchdog RX hung detected\n");
1271 if (hung_tx || hung_rx)
1272 ieee80211_restart_hw(rt2x00dev->hw);
1274 EXPORT_SYMBOL_GPL(rt2800_watchdog);
1276 static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev,
1279 return HW_BEACON_BASE(index);
1282 static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev,
1285 return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index));
1288 static void rt2800_update_beacons_setup(struct rt2x00_dev *rt2x00dev)
1290 struct data_queue *queue = rt2x00dev->bcn;
1291 struct queue_entry *entry;
1297 * Setup offsets of all active beacons in BCN_OFFSET{0,1} registers.
1299 for (i = 0; i < queue->limit; i++) {
1300 entry = &queue->entries[i];
1301 if (!test_bit(ENTRY_BCN_ENABLED, &entry->flags))
1303 off = rt2800_get_beacon_offset(rt2x00dev, entry->entry_idx);
1304 reg |= off << (8 * bcn_num);
1308 rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg);
1309 rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32));
1312 * H/W sends up to MAC_BSSID_DW1_BSS_BCN_NUM + 1 consecutive beacons.
1314 bssid_dw1 = rt2800_register_read(rt2x00dev, MAC_BSSID_DW1);
1315 rt2x00_set_field32(&bssid_dw1, MAC_BSSID_DW1_BSS_BCN_NUM,
1316 bcn_num > 0 ? bcn_num - 1 : 0);
1317 rt2800_register_write(rt2x00dev, MAC_BSSID_DW1, bssid_dw1);
1320 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
1322 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1323 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1324 unsigned int beacon_base;
1325 unsigned int padding_len;
1327 const int txwi_desc_size = entry->queue->winfo_size;
1330 * Disable beaconing while we are reloading the beacon data,
1331 * otherwise we might be sending out invalid data.
1333 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1335 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0);
1336 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1339 * Add space for the TXWI in front of the skb.
1341 memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size);
1344 * Register descriptor details in skb frame descriptor.
1346 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
1347 skbdesc->desc = entry->skb->data;
1348 skbdesc->desc_len = txwi_desc_size;
1351 * Add the TXWI for the beacon to the skb.
1353 rt2800_write_tx_data(entry, txdesc);
1356 * Dump beacon to userspace through debugfs.
1358 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry);
1361 * Write entire beacon with TXWI and padding to register.
1363 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
1364 if (padding_len && skb_pad(entry->skb, padding_len)) {
1365 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
1366 /* skb freed by skb_pad() on failure */
1368 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1372 beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx);
1374 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
1375 entry->skb->len + padding_len);
1376 __set_bit(ENTRY_BCN_ENABLED, &entry->flags);
1379 * Change global beacons settings.
1381 rt2800_update_beacons_setup(rt2x00dev);
1384 * Restore beaconing state.
1386 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1389 * Clean up beacon skb.
1391 dev_kfree_skb_any(entry->skb);
1394 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
1396 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
1400 const int txwi_desc_size = rt2x00dev->bcn->winfo_size;
1401 unsigned int beacon_base;
1403 beacon_base = rt2800_hw_beacon_base(rt2x00dev, index);
1406 * For the Beacon base registers we only need to clear
1407 * the whole TXWI which (when set to 0) will invalidate
1408 * the entire beacon.
1410 for (i = 0; i < txwi_desc_size; i += sizeof(__le32))
1411 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
1414 void rt2800_clear_beacon(struct queue_entry *entry)
1416 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1420 * Disable beaconing while we are reloading the beacon data,
1421 * otherwise we might be sending out invalid data.
1423 orig_reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1425 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0);
1426 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1431 rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx);
1432 __clear_bit(ENTRY_BCN_ENABLED, &entry->flags);
1435 * Change global beacons settings.
1437 rt2800_update_beacons_setup(rt2x00dev);
1439 * Restore beaconing state.
1441 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1443 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
1445 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1446 const struct rt2x00debug rt2800_rt2x00debug = {
1447 .owner = THIS_MODULE,
1449 .read = rt2800_register_read,
1450 .write = rt2800_register_write,
1451 .flags = RT2X00DEBUGFS_OFFSET,
1452 .word_base = CSR_REG_BASE,
1453 .word_size = sizeof(u32),
1454 .word_count = CSR_REG_SIZE / sizeof(u32),
1457 /* NOTE: The local EEPROM access functions can't
1458 * be used here, use the generic versions instead.
1460 .read = rt2x00_eeprom_read,
1461 .write = rt2x00_eeprom_write,
1462 .word_base = EEPROM_BASE,
1463 .word_size = sizeof(u16),
1464 .word_count = EEPROM_SIZE / sizeof(u16),
1467 .read = rt2800_bbp_read,
1468 .write = rt2800_bbp_write,
1469 .word_base = BBP_BASE,
1470 .word_size = sizeof(u8),
1471 .word_count = BBP_SIZE / sizeof(u8),
1474 .read = rt2x00_rf_read,
1475 .write = rt2800_rf_write,
1476 .word_base = RF_BASE,
1477 .word_size = sizeof(u32),
1478 .word_count = RF_SIZE / sizeof(u32),
1481 .read = rt2800_rfcsr_read,
1482 .write = rt2800_rfcsr_write,
1483 .word_base = RFCSR_BASE,
1484 .word_size = sizeof(u8),
1485 .word_count = RFCSR_SIZE / sizeof(u8),
1488 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
1489 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1491 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
1495 if (rt2x00_rt(rt2x00dev, RT3290)) {
1496 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
1497 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
1499 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
1500 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
1503 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
1505 #ifdef CONFIG_RT2X00_LIB_LEDS
1506 static void rt2800_brightness_set(struct led_classdev *led_cdev,
1507 enum led_brightness brightness)
1509 struct rt2x00_led *led =
1510 container_of(led_cdev, struct rt2x00_led, led_dev);
1511 unsigned int enabled = brightness != LED_OFF;
1512 unsigned int bg_mode =
1513 (enabled && led->rt2x00dev->curr_band == NL80211_BAND_2GHZ);
1514 unsigned int polarity =
1515 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1516 EEPROM_FREQ_LED_POLARITY);
1517 unsigned int ledmode =
1518 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1519 EEPROM_FREQ_LED_MODE);
1522 /* Check for SoC (SOC devices don't support MCU requests) */
1523 if (rt2x00_is_soc(led->rt2x00dev)) {
1524 reg = rt2800_register_read(led->rt2x00dev, LED_CFG);
1526 /* Set LED Polarity */
1527 rt2x00_set_field32(®, LED_CFG_LED_POLAR, polarity);
1530 if (led->type == LED_TYPE_RADIO) {
1531 rt2x00_set_field32(®, LED_CFG_G_LED_MODE,
1533 } else if (led->type == LED_TYPE_ASSOC) {
1534 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE,
1536 } else if (led->type == LED_TYPE_QUALITY) {
1537 rt2x00_set_field32(®, LED_CFG_R_LED_MODE,
1541 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
1544 if (led->type == LED_TYPE_RADIO) {
1545 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1546 enabled ? 0x20 : 0);
1547 } else if (led->type == LED_TYPE_ASSOC) {
1548 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1549 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
1550 } else if (led->type == LED_TYPE_QUALITY) {
1552 * The brightness is divided into 6 levels (0 - 5),
1553 * The specs tell us the following levels:
1554 * 0, 1 ,3, 7, 15, 31
1555 * to determine the level in a simple way we can simply
1556 * work with bitshifting:
1559 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
1560 (1 << brightness / (LED_FULL / 6)) - 1,
1566 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
1567 struct rt2x00_led *led, enum led_type type)
1569 led->rt2x00dev = rt2x00dev;
1571 led->led_dev.brightness_set = rt2800_brightness_set;
1572 led->flags = LED_INITIALIZED;
1574 #endif /* CONFIG_RT2X00_LIB_LEDS */
1577 * Configuration handlers.
1579 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1583 struct mac_wcid_entry wcid_entry;
1586 offset = MAC_WCID_ENTRY(wcid);
1588 memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1590 memcpy(wcid_entry.mac, address, ETH_ALEN);
1592 rt2800_register_multiwrite(rt2x00dev, offset,
1593 &wcid_entry, sizeof(wcid_entry));
1596 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1599 offset = MAC_WCID_ATTR_ENTRY(wcid);
1600 rt2800_register_write(rt2x00dev, offset, 0);
1603 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1604 int wcid, u32 bssidx)
1606 u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1610 * The BSS Idx numbers is split in a main value of 3 bits,
1611 * and a extended field for adding one additional bit to the value.
1613 reg = rt2800_register_read(rt2x00dev, offset);
1614 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1615 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1616 (bssidx & 0x8) >> 3);
1617 rt2800_register_write(rt2x00dev, offset, reg);
1620 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1621 struct rt2x00lib_crypto *crypto,
1622 struct ieee80211_key_conf *key)
1624 struct mac_iveiv_entry iveiv_entry;
1628 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1630 if (crypto->cmd == SET_KEY) {
1631 reg = rt2800_register_read(rt2x00dev, offset);
1632 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB,
1633 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1635 * Both the cipher as the BSS Idx numbers are split in a main
1636 * value of 3 bits, and a extended field for adding one additional
1639 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER,
1640 (crypto->cipher & 0x7));
1641 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1642 (crypto->cipher & 0x8) >> 3);
1643 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1644 rt2800_register_write(rt2x00dev, offset, reg);
1646 /* Delete the cipher without touching the bssidx */
1647 reg = rt2800_register_read(rt2x00dev, offset);
1648 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1649 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1650 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1651 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1652 rt2800_register_write(rt2x00dev, offset, reg);
1655 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1657 rt2800_register_multiread(rt2x00dev, offset,
1658 &iveiv_entry, sizeof(iveiv_entry));
1659 if ((crypto->cipher == CIPHER_TKIP) ||
1660 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1661 (crypto->cipher == CIPHER_AES))
1662 iveiv_entry.iv[3] |= 0x20;
1663 iveiv_entry.iv[3] |= key->keyidx << 6;
1664 rt2800_register_multiwrite(rt2x00dev, offset,
1665 &iveiv_entry, sizeof(iveiv_entry));
1668 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1669 struct rt2x00lib_crypto *crypto,
1670 struct ieee80211_key_conf *key)
1672 struct hw_key_entry key_entry;
1673 struct rt2x00_field32 field;
1677 if (crypto->cmd == SET_KEY) {
1678 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1680 memcpy(key_entry.key, crypto->key,
1681 sizeof(key_entry.key));
1682 memcpy(key_entry.tx_mic, crypto->tx_mic,
1683 sizeof(key_entry.tx_mic));
1684 memcpy(key_entry.rx_mic, crypto->rx_mic,
1685 sizeof(key_entry.rx_mic));
1687 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1688 rt2800_register_multiwrite(rt2x00dev, offset,
1689 &key_entry, sizeof(key_entry));
1693 * The cipher types are stored over multiple registers
1694 * starting with SHARED_KEY_MODE_BASE each word will have
1695 * 32 bits and contains the cipher types for 2 bssidx each.
1696 * Using the correct defines correctly will cause overhead,
1697 * so just calculate the correct offset.
1699 field.bit_offset = 4 * (key->hw_key_idx % 8);
1700 field.bit_mask = 0x7 << field.bit_offset;
1702 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1704 reg = rt2800_register_read(rt2x00dev, offset);
1705 rt2x00_set_field32(®, field,
1706 (crypto->cmd == SET_KEY) * crypto->cipher);
1707 rt2800_register_write(rt2x00dev, offset, reg);
1710 * Update WCID information
1712 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1713 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1715 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1719 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1721 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1722 struct rt2x00lib_crypto *crypto,
1723 struct ieee80211_key_conf *key)
1725 struct hw_key_entry key_entry;
1728 if (crypto->cmd == SET_KEY) {
1730 * Allow key configuration only for STAs that are
1733 if (crypto->wcid > WCID_END)
1735 key->hw_key_idx = crypto->wcid;
1737 memcpy(key_entry.key, crypto->key,
1738 sizeof(key_entry.key));
1739 memcpy(key_entry.tx_mic, crypto->tx_mic,
1740 sizeof(key_entry.tx_mic));
1741 memcpy(key_entry.rx_mic, crypto->rx_mic,
1742 sizeof(key_entry.rx_mic));
1744 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1745 rt2800_register_multiwrite(rt2x00dev, offset,
1746 &key_entry, sizeof(key_entry));
1750 * Update WCID information
1752 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1756 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1758 static void rt2800_set_max_psdu_len(struct rt2x00_dev *rt2x00dev)
1762 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1764 for (i = 0; i < 3; i++)
1765 if (drv_data->ampdu_factor_cnt[i] > 0)
1768 max_psdu = min(drv_data->max_psdu, i);
1770 reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG);
1771 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, max_psdu);
1772 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1775 int rt2800_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1776 struct ieee80211_sta *sta)
1778 struct rt2x00_dev *rt2x00dev = hw->priv;
1779 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1780 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1784 * Limit global maximum TX AMPDU length to smallest value of all
1785 * connected stations. In AP mode this can be suboptimal, but we
1786 * do not have a choice if some connected STA is not capable to
1787 * receive the same amount of data like the others.
1789 if (sta->ht_cap.ht_supported) {
1790 drv_data->ampdu_factor_cnt[sta->ht_cap.ampdu_factor & 3]++;
1791 rt2800_set_max_psdu_len(rt2x00dev);
1795 * Search for the first free WCID entry and return the corresponding
1798 wcid = find_first_zero_bit(drv_data->sta_ids, STA_IDS_SIZE) + WCID_START;
1801 * Store selected wcid even if it is invalid so that we can
1802 * later decide if the STA is uploaded into the hw.
1804 sta_priv->wcid = wcid;
1807 * No space left in the device, however, we can still communicate
1808 * with the STA -> No error.
1810 if (wcid > WCID_END)
1813 __set_bit(wcid - WCID_START, drv_data->sta_ids);
1814 drv_data->wcid_to_sta[wcid - WCID_START] = sta;
1817 * Clean up WCID attributes and write STA address to the device.
1819 rt2800_delete_wcid_attr(rt2x00dev, wcid);
1820 rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1821 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1822 rt2x00lib_get_bssidx(rt2x00dev, vif));
1825 EXPORT_SYMBOL_GPL(rt2800_sta_add);
1827 int rt2800_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1828 struct ieee80211_sta *sta)
1830 struct rt2x00_dev *rt2x00dev = hw->priv;
1831 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1832 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1833 int wcid = sta_priv->wcid;
1835 if (sta->ht_cap.ht_supported) {
1836 drv_data->ampdu_factor_cnt[sta->ht_cap.ampdu_factor & 3]--;
1837 rt2800_set_max_psdu_len(rt2x00dev);
1840 if (wcid > WCID_END)
1843 * Remove WCID entry, no need to clean the attributes as they will
1844 * get renewed when the WCID is reused.
1846 rt2800_config_wcid(rt2x00dev, NULL, wcid);
1847 drv_data->wcid_to_sta[wcid - WCID_START] = NULL;
1848 __clear_bit(wcid - WCID_START, drv_data->sta_ids);
1852 EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1854 void rt2800_pre_reset_hw(struct rt2x00_dev *rt2x00dev)
1856 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1857 struct data_queue *queue = rt2x00dev->bcn;
1858 struct queue_entry *entry;
1861 for (wcid = WCID_START; wcid < WCID_END; wcid++) {
1862 drv_data->wcid_to_sta[wcid - WCID_START] = NULL;
1863 __clear_bit(wcid - WCID_START, drv_data->sta_ids);
1866 for (i = 0; i < queue->limit; i++) {
1867 entry = &queue->entries[i];
1868 clear_bit(ENTRY_BCN_ASSIGNED, &entry->flags);
1871 EXPORT_SYMBOL_GPL(rt2800_pre_reset_hw);
1873 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1874 const unsigned int filter_flags)
1879 * Start configuration steps.
1880 * Note that the version error will always be dropped
1881 * and broadcast frames will always be accepted since
1882 * there is no filter for it at this time.
1884 reg = rt2800_register_read(rt2x00dev, RX_FILTER_CFG);
1885 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CRC_ERROR,
1886 !(filter_flags & FIF_FCSFAIL));
1887 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PHY_ERROR,
1888 !(filter_flags & FIF_PLCPFAIL));
1889 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_TO_ME,
1890 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags));
1891 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1892 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1893 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_MULTICAST,
1894 !(filter_flags & FIF_ALLMULTI));
1895 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BROADCAST, 0);
1896 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1897 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END_ACK,
1898 !(filter_flags & FIF_CONTROL));
1899 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END,
1900 !(filter_flags & FIF_CONTROL));
1901 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_ACK,
1902 !(filter_flags & FIF_CONTROL));
1903 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CTS,
1904 !(filter_flags & FIF_CONTROL));
1905 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_RTS,
1906 !(filter_flags & FIF_CONTROL));
1907 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PSPOLL,
1908 !(filter_flags & FIF_PSPOLL));
1909 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BA, 0);
1910 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BAR,
1911 !(filter_flags & FIF_CONTROL));
1912 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CNTL,
1913 !(filter_flags & FIF_CONTROL));
1914 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1916 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1918 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1919 struct rt2x00intf_conf *conf, const unsigned int flags)
1922 bool update_bssid = false;
1924 if (flags & CONFIG_UPDATE_TYPE) {
1926 * Enable synchronisation.
1928 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1929 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1930 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1932 if (conf->sync == TSF_SYNC_AP_NONE) {
1934 * Tune beacon queue transmit parameters for AP mode
1936 reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG);
1937 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1938 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1939 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1940 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1941 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1943 reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG);
1944 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1945 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1946 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1947 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1948 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1952 if (flags & CONFIG_UPDATE_MAC) {
1953 if (flags & CONFIG_UPDATE_TYPE &&
1954 conf->sync == TSF_SYNC_AP_NONE) {
1956 * The BSSID register has to be set to our own mac
1957 * address in AP mode.
1959 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1960 update_bssid = true;
1963 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1964 reg = le32_to_cpu(conf->mac[1]);
1965 rt2x00_set_field32(®, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1966 conf->mac[1] = cpu_to_le32(reg);
1969 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1970 conf->mac, sizeof(conf->mac));
1973 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1974 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1975 reg = le32_to_cpu(conf->bssid[1]);
1976 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1977 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
1978 conf->bssid[1] = cpu_to_le32(reg);
1981 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1982 conf->bssid, sizeof(conf->bssid));
1985 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1987 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1988 struct rt2x00lib_erp *erp)
1990 bool any_sta_nongf = !!(erp->ht_opmode &
1991 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1992 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1993 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1994 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1997 /* default protection rate for HT20: OFDM 24M */
1998 mm20_rate = gf20_rate = 0x4004;
2000 /* default protection rate for HT40: duplicate OFDM 24M */
2001 mm40_rate = gf40_rate = 0x4084;
2003 switch (protection) {
2004 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
2006 * All STAs in this BSS are HT20/40 but there might be
2007 * STAs not supporting greenfield mode.
2008 * => Disable protection for HT transmissions.
2010 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
2013 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2015 * All STAs in this BSS are HT20 or HT20/40 but there
2016 * might be STAs not supporting greenfield mode.
2017 * => Protect all HT40 transmissions.
2019 mm20_mode = gf20_mode = 0;
2020 mm40_mode = gf40_mode = 1;
2023 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
2025 * Nonmember protection:
2026 * According to 802.11n we _should_ protect all
2027 * HT transmissions (but we don't have to).
2029 * But if cts_protection is enabled we _shall_ protect
2030 * all HT transmissions using a CCK rate.
2032 * And if any station is non GF we _shall_ protect
2035 * We decide to protect everything
2036 * -> fall through to mixed mode.
2038 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2040 * Legacy STAs are present
2041 * => Protect all HT transmissions.
2043 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 1;
2046 * If erp protection is needed we have to protect HT
2047 * transmissions with CCK 11M long preamble.
2049 if (erp->cts_protection) {
2050 /* don't duplicate RTS/CTS in CCK mode */
2051 mm20_rate = mm40_rate = 0x0003;
2052 gf20_rate = gf40_rate = 0x0003;
2057 /* check for STAs not supporting greenfield mode */
2059 gf20_mode = gf40_mode = 1;
2061 /* Update HT protection config */
2062 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
2063 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
2064 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
2065 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2067 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
2068 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
2069 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
2070 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2072 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
2073 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
2074 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
2075 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2077 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
2078 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
2079 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
2080 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2083 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
2088 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2089 reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG);
2090 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE,
2091 !!erp->short_preamble);
2092 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2095 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2096 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
2097 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL,
2098 erp->cts_protection ? 2 : 0);
2099 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2102 if (changed & BSS_CHANGED_BASIC_RATES) {
2103 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
2104 0xff0 | erp->basic_rates);
2105 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
2108 if (changed & BSS_CHANGED_ERP_SLOT) {
2109 reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG);
2110 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME,
2112 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
2114 reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG);
2115 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, erp->eifs);
2116 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
2119 if (changed & BSS_CHANGED_BEACON_INT) {
2120 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
2121 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL,
2122 erp->beacon_int * 16);
2123 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2126 if (changed & BSS_CHANGED_HT)
2127 rt2800_config_ht_opmode(rt2x00dev, erp);
2129 EXPORT_SYMBOL_GPL(rt2800_config_erp);
2131 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
2135 u8 led_ctrl, led_g_mode, led_r_mode;
2137 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
2138 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) {
2139 rt2x00_set_field32(®, GPIO_SWITCH_0, 1);
2140 rt2x00_set_field32(®, GPIO_SWITCH_1, 1);
2142 rt2x00_set_field32(®, GPIO_SWITCH_0, 0);
2143 rt2x00_set_field32(®, GPIO_SWITCH_1, 0);
2145 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
2147 reg = rt2800_register_read(rt2x00dev, LED_CFG);
2148 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
2149 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
2150 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
2151 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
2152 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
2153 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
2154 if (led_ctrl == 0 || led_ctrl > 0x40) {
2155 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, led_g_mode);
2156 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, led_r_mode);
2157 rt2800_register_write(rt2x00dev, LED_CFG, reg);
2159 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
2160 (led_g_mode << 2) | led_r_mode, 1);
2165 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
2169 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
2170 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
2172 if (rt2x00_is_pci(rt2x00dev)) {
2173 reg = rt2800_register_read(rt2x00dev, E2PROM_CSR);
2174 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, eesk_pin);
2175 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
2176 } else if (rt2x00_is_usb(rt2x00dev))
2177 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
2180 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
2181 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0);
2182 rt2x00_set_field32(®, GPIO_CTRL_VAL3, gpio_bit3);
2183 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
2186 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
2192 r1 = rt2800_bbp_read(rt2x00dev, 1);
2193 r3 = rt2800_bbp_read(rt2x00dev, 3);
2195 if (rt2x00_rt(rt2x00dev, RT3572) &&
2196 rt2x00_has_cap_bt_coexist(rt2x00dev))
2197 rt2800_config_3572bt_ant(rt2x00dev);
2200 * Configure the TX antenna.
2202 switch (ant->tx_chain_num) {
2204 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
2207 if (rt2x00_rt(rt2x00dev, RT3572) &&
2208 rt2x00_has_cap_bt_coexist(rt2x00dev))
2209 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
2211 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
2214 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
2219 * Configure the RX antenna.
2221 switch (ant->rx_chain_num) {
2223 if (rt2x00_rt(rt2x00dev, RT3070) ||
2224 rt2x00_rt(rt2x00dev, RT3090) ||
2225 rt2x00_rt(rt2x00dev, RT3352) ||
2226 rt2x00_rt(rt2x00dev, RT3390)) {
2227 eeprom = rt2800_eeprom_read(rt2x00dev,
2229 if (rt2x00_get_field16(eeprom,
2230 EEPROM_NIC_CONF1_ANT_DIVERSITY))
2231 rt2800_set_ant_diversity(rt2x00dev,
2232 rt2x00dev->default_ant.rx);
2234 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
2237 if (rt2x00_rt(rt2x00dev, RT3572) &&
2238 rt2x00_has_cap_bt_coexist(rt2x00dev)) {
2239 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
2240 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
2241 rt2x00dev->curr_band == NL80211_BAND_5GHZ);
2242 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
2244 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
2248 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
2252 rt2800_bbp_write(rt2x00dev, 3, r3);
2253 rt2800_bbp_write(rt2x00dev, 1, r1);
2255 if (rt2x00_rt(rt2x00dev, RT3593) ||
2256 rt2x00_rt(rt2x00dev, RT3883)) {
2257 if (ant->rx_chain_num == 1)
2258 rt2800_bbp_write(rt2x00dev, 86, 0x00);
2260 rt2800_bbp_write(rt2x00dev, 86, 0x46);
2263 EXPORT_SYMBOL_GPL(rt2800_config_ant);
2265 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
2266 struct rt2x00lib_conf *libconf)
2271 if (libconf->rf.channel <= 14) {
2272 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
2273 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
2274 } else if (libconf->rf.channel <= 64) {
2275 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
2276 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
2277 } else if (libconf->rf.channel <= 128) {
2278 if (rt2x00_rt(rt2x00dev, RT3593) ||
2279 rt2x00_rt(rt2x00dev, RT3883)) {
2280 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
2281 lna_gain = rt2x00_get_field16(eeprom,
2282 EEPROM_EXT_LNA2_A1);
2284 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
2285 lna_gain = rt2x00_get_field16(eeprom,
2286 EEPROM_RSSI_BG2_LNA_A1);
2289 if (rt2x00_rt(rt2x00dev, RT3593) ||
2290 rt2x00_rt(rt2x00dev, RT3883)) {
2291 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
2292 lna_gain = rt2x00_get_field16(eeprom,
2293 EEPROM_EXT_LNA2_A2);
2295 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
2296 lna_gain = rt2x00_get_field16(eeprom,
2297 EEPROM_RSSI_A2_LNA_A2);
2301 rt2x00dev->lna_gain = lna_gain;
2304 static inline bool rt2800_clk_is_20mhz(struct rt2x00_dev *rt2x00dev)
2306 return clk_get_rate(rt2x00dev->clk) == 20000000;
2309 #define FREQ_OFFSET_BOUND 0x5f
2311 static void rt2800_freq_cal_mode1(struct rt2x00_dev *rt2x00dev)
2313 u8 freq_offset, prev_freq_offset;
2314 u8 rfcsr, prev_rfcsr;
2316 freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE);
2317 freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND);
2319 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
2322 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset);
2323 if (rfcsr == prev_rfcsr)
2326 if (rt2x00_is_usb(rt2x00dev)) {
2327 rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff,
2328 freq_offset, prev_rfcsr);
2332 prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE);
2333 while (prev_freq_offset != freq_offset) {
2334 if (prev_freq_offset < freq_offset)
2339 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset);
2340 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2342 usleep_range(1000, 1500);
2346 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
2347 struct ieee80211_conf *conf,
2348 struct rf_channel *rf,
2349 struct channel_info *info)
2351 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
2353 if (rt2x00dev->default_ant.tx_chain_num == 1)
2354 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
2356 if (rt2x00dev->default_ant.rx_chain_num == 1) {
2357 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
2358 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
2359 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
2360 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
2362 if (rf->channel > 14) {
2364 * When TX power is below 0, we should increase it by 7 to
2365 * make it a positive value (Minimum value is -7).
2366 * However this means that values between 0 and 7 have
2367 * double meaning, and we should set a 7DBm boost flag.
2369 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
2370 (info->default_power1 >= 0));
2372 if (info->default_power1 < 0)
2373 info->default_power1 += 7;
2375 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
2377 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
2378 (info->default_power2 >= 0));
2380 if (info->default_power2 < 0)
2381 info->default_power2 += 7;
2383 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
2385 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
2386 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
2389 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
2391 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2392 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2393 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2394 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2398 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2399 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2400 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
2401 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2405 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2406 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2407 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2408 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2411 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
2412 struct ieee80211_conf *conf,
2413 struct rf_channel *rf,
2414 struct channel_info *info)
2416 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2417 u8 rfcsr, calib_tx, calib_rx;
2419 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2421 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
2422 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
2423 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2425 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2426 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2427 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2429 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2430 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
2431 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2433 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
2434 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
2435 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2437 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2438 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2439 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2440 rt2x00dev->default_ant.rx_chain_num <= 1);
2441 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
2442 rt2x00dev->default_ant.rx_chain_num <= 2);
2443 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2444 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2445 rt2x00dev->default_ant.tx_chain_num <= 1);
2446 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
2447 rt2x00dev->default_ant.tx_chain_num <= 2);
2448 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2450 rfcsr = rt2800_rfcsr_read(rt2x00dev, 23);
2451 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2452 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2454 if (rt2x00_rt(rt2x00dev, RT3390)) {
2455 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
2456 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
2458 if (conf_is_ht40(conf)) {
2459 calib_tx = drv_data->calibration_bw40;
2460 calib_rx = drv_data->calibration_bw40;
2462 calib_tx = drv_data->calibration_bw20;
2463 calib_rx = drv_data->calibration_bw20;
2467 rfcsr = rt2800_rfcsr_read(rt2x00dev, 24);
2468 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
2469 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
2471 rfcsr = rt2800_rfcsr_read(rt2x00dev, 31);
2472 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
2473 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2475 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2476 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2477 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2479 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2480 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2481 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2483 usleep_range(1000, 1500);
2485 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2486 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2489 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
2490 struct ieee80211_conf *conf,
2491 struct rf_channel *rf,
2492 struct channel_info *info)
2494 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2498 if (rf->channel <= 14) {
2499 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2500 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2502 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2503 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2506 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2507 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
2509 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2510 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2511 if (rf->channel <= 14)
2512 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
2514 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
2515 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2517 rfcsr = rt2800_rfcsr_read(rt2x00dev, 5);
2518 if (rf->channel <= 14)
2519 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
2521 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
2522 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
2524 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2525 if (rf->channel <= 14) {
2526 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
2527 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2528 info->default_power1);
2530 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
2531 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2532 (info->default_power1 & 0x3) |
2533 ((info->default_power1 & 0xC) << 1));
2535 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2537 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
2538 if (rf->channel <= 14) {
2539 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
2540 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2541 info->default_power2);
2543 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
2544 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2545 (info->default_power2 & 0x3) |
2546 ((info->default_power2 & 0xC) << 1));
2548 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2550 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2551 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2552 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2553 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2554 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2555 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2556 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2557 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
2558 if (rf->channel <= 14) {
2559 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2560 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2562 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2563 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2565 switch (rt2x00dev->default_ant.tx_chain_num) {
2567 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2570 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2574 switch (rt2x00dev->default_ant.rx_chain_num) {
2576 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2579 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2583 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2585 rfcsr = rt2800_rfcsr_read(rt2x00dev, 23);
2586 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2587 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2589 if (conf_is_ht40(conf)) {
2590 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
2591 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
2593 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
2594 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
2597 if (rf->channel <= 14) {
2598 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
2599 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
2600 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2601 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
2602 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2604 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2605 drv_data->txmixer_gain_24g);
2606 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2607 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2608 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
2609 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
2610 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
2611 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2612 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2613 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
2615 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2616 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
2617 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
2618 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
2619 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
2620 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2621 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2622 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2623 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
2624 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
2626 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2627 drv_data->txmixer_gain_5g);
2628 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2629 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2630 if (rf->channel <= 64) {
2631 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
2632 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
2633 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2634 } else if (rf->channel <= 128) {
2635 rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
2636 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
2637 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2639 rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
2640 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
2641 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2643 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
2644 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
2645 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
2648 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
2649 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0);
2650 if (rf->channel <= 14)
2651 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1);
2653 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 0);
2654 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
2656 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2657 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2658 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2661 static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev,
2662 struct ieee80211_conf *conf,
2663 struct rf_channel *rf,
2664 struct channel_info *info)
2666 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2671 const bool txbf_enabled = false; /* TODO */
2673 /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */
2674 bbp = rt2800_bbp_read(rt2x00dev, 109);
2675 rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0);
2676 rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0);
2677 rt2800_bbp_write(rt2x00dev, 109, bbp);
2679 bbp = rt2800_bbp_read(rt2x00dev, 110);
2680 rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0);
2681 rt2800_bbp_write(rt2x00dev, 110, bbp);
2683 if (rf->channel <= 14) {
2684 /* Restore BBP 25 & 26 for 2.4 GHz */
2685 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2686 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2688 /* Hard code BBP 25 & 26 for 5GHz */
2690 /* Enable IQ Phase correction */
2691 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2692 /* Setup IQ Phase correction value */
2693 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2696 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2697 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf);
2699 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
2700 rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3));
2701 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2703 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
2704 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1);
2705 if (rf->channel <= 14)
2706 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1);
2708 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2);
2709 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2711 rfcsr = rt2800_rfcsr_read(rt2x00dev, 53);
2712 if (rf->channel <= 14) {
2714 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2715 info->default_power1 & 0x1f);
2717 if (rt2x00_is_usb(rt2x00dev))
2720 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2721 ((info->default_power1 & 0x18) << 1) |
2722 (info->default_power1 & 7));
2724 rt2800_rfcsr_write(rt2x00dev, 53, rfcsr);
2726 rfcsr = rt2800_rfcsr_read(rt2x00dev, 55);
2727 if (rf->channel <= 14) {
2729 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2730 info->default_power2 & 0x1f);
2732 if (rt2x00_is_usb(rt2x00dev))
2735 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2736 ((info->default_power2 & 0x18) << 1) |
2737 (info->default_power2 & 7));
2739 rt2800_rfcsr_write(rt2x00dev, 55, rfcsr);
2741 rfcsr = rt2800_rfcsr_read(rt2x00dev, 54);
2742 if (rf->channel <= 14) {
2744 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2745 info->default_power3 & 0x1f);
2747 if (rt2x00_is_usb(rt2x00dev))
2750 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2751 ((info->default_power3 & 0x18) << 1) |
2752 (info->default_power3 & 7));
2754 rt2800_rfcsr_write(rt2x00dev, 54, rfcsr);
2756 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2757 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2758 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2759 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2760 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2761 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2762 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2763 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2764 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2766 switch (rt2x00dev->default_ant.tx_chain_num) {
2768 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2771 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2774 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2778 switch (rt2x00dev->default_ant.rx_chain_num) {
2780 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2783 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2786 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2789 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2791 rt2800_freq_cal_mode1(rt2x00dev);
2793 if (conf_is_ht40(conf)) {
2794 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40,
2796 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40,
2799 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20,
2801 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20,
2805 /* NOTE: the reference driver does not writes the new value
2808 rfcsr = rt2800_rfcsr_read(rt2x00dev, 32);
2809 rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc);
2811 if (rf->channel <= 14)
2815 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2817 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2818 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m);
2819 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m);
2820 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2822 /* Band selection */
2823 rfcsr = rt2800_rfcsr_read(rt2x00dev, 36);
2824 if (rf->channel <= 14)
2825 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
2827 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
2828 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
2830 rfcsr = rt2800_rfcsr_read(rt2x00dev, 34);
2831 if (rf->channel <= 14)
2835 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
2837 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2838 if (rf->channel <= 14)
2842 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2844 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2845 if (rf->channel >= 1 && rf->channel <= 14)
2846 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2847 else if (rf->channel >= 36 && rf->channel <= 64)
2848 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2849 else if (rf->channel >= 100 && rf->channel <= 128)
2850 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2852 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2853 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2855 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2856 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
2857 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2859 rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
2861 if (rf->channel <= 14) {
2862 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
2863 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
2865 rt2800_rfcsr_write(rt2x00dev, 10, 0xd8);
2866 rt2800_rfcsr_write(rt2x00dev, 13, 0x23);
2869 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
2870 rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1);
2871 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2873 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
2874 if (rf->channel <= 14) {
2875 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5);
2876 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3);
2878 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4);
2879 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2);
2881 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2883 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
2884 if (rf->channel <= 14)
2885 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3);
2887 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2);
2890 rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1);
2892 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2894 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
2895 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0);
2896 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2898 rfcsr = rt2800_rfcsr_read(rt2x00dev, 57);
2899 if (rf->channel <= 14)
2900 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b);
2902 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f);
2903 rt2800_rfcsr_write(rt2x00dev, 57, rfcsr);
2905 if (rf->channel <= 14) {
2906 rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
2907 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
2909 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
2910 rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
2913 /* Initiate VCO calibration */
2914 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
2915 if (rf->channel <= 14) {
2916 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2918 rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1);
2919 rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1);
2920 rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1);
2921 rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1);
2922 rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1);
2923 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2925 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2927 if (rf->channel >= 1 && rf->channel <= 14) {
2930 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2931 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2933 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
2934 } else if (rf->channel >= 36 && rf->channel <= 64) {
2937 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2938 rt2800_rfcsr_write(rt2x00dev, 39, 0x36);
2940 rt2800_rfcsr_write(rt2x00dev, 45, 0xeb);
2941 } else if (rf->channel >= 100 && rf->channel <= 128) {
2944 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2945 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2947 rt2800_rfcsr_write(rt2x00dev, 45, 0xb3);
2951 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2952 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2954 rt2800_rfcsr_write(rt2x00dev, 45, 0x9b);
2958 static void rt2800_config_channel_rf3853(struct rt2x00_dev *rt2x00dev,
2959 struct ieee80211_conf *conf,
2960 struct rf_channel *rf,
2961 struct channel_info *info)
2965 u8 pwr1, pwr2, pwr3;
2967 const bool txbf_enabled = false; /* TODO */
2969 /* TODO: add band selection */
2971 if (rf->channel <= 14)
2972 rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
2973 else if (rf->channel < 132)
2974 rt2800_rfcsr_write(rt2x00dev, 6, 0x80);
2976 rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
2978 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2979 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2981 if (rf->channel <= 14)
2982 rt2800_rfcsr_write(rt2x00dev, 11, 0x46);
2984 rt2800_rfcsr_write(rt2x00dev, 11, 0x48);
2986 if (rf->channel <= 14)
2987 rt2800_rfcsr_write(rt2x00dev, 12, 0x1a);
2989 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
2991 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
2993 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2994 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2995 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2996 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2997 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2998 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2999 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
3000 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3001 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
3003 switch (rt2x00dev->default_ant.tx_chain_num) {
3005 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
3008 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3011 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
3015 switch (rt2x00dev->default_ant.rx_chain_num) {
3017 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
3020 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3023 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
3026 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3028 rt2800_freq_cal_mode1(rt2x00dev);
3030 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
3031 if (!conf_is_ht40(conf))
3035 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3037 if (rf->channel <= 14)
3038 rt2800_rfcsr_write(rt2x00dev, 31, 0xa0);
3040 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3042 if (conf_is_ht40(conf))
3043 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3045 rt2800_rfcsr_write(rt2x00dev, 32, 0xd8);
3047 if (rf->channel <= 14)
3048 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
3050 rt2800_rfcsr_write(rt2x00dev, 34, 0x20);
3052 /* loopback RF_BS */
3053 rfcsr = rt2800_rfcsr_read(rt2x00dev, 36);
3054 if (rf->channel <= 14)
3055 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
3057 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
3058 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
3060 if (rf->channel <= 14)
3062 else if (rf->channel < 100)
3064 else if (rf->channel < 132)
3072 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3074 if (rf->channel <= 14)
3075 rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
3077 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
3079 if (rf->channel <= 14)
3081 else if (rf->channel < 100)
3083 else if (rf->channel < 132)
3087 rt2800_rfcsr_write(rt2x00dev, 45, rfcsr);
3089 if (rf->channel <= 14)
3097 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3099 rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
3101 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
3102 if (rf->channel <= 14)
3103 rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
3105 rt2800_rfcsr_write(rt2x00dev, 51, 0x51);
3107 rfcsr = rt2800_rfcsr_read(rt2x00dev, 52);
3108 if (rf->channel <= 14)
3109 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
3111 rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
3113 if (rf->channel <= 14) {
3114 pwr1 = info->default_power1 & 0x1f;
3115 pwr2 = info->default_power2 & 0x1f;
3116 pwr3 = info->default_power3 & 0x1f;
3118 pwr1 = 0x48 | ((info->default_power1 & 0x18) << 1) |
3119 (info->default_power1 & 0x7);
3120 pwr2 = 0x48 | ((info->default_power2 & 0x18) << 1) |
3121 (info->default_power2 & 0x7);
3122 pwr3 = 0x48 | ((info->default_power3 & 0x18) << 1) |
3123 (info->default_power3 & 0x7);
3126 rt2800_rfcsr_write(rt2x00dev, 53, pwr1);
3127 rt2800_rfcsr_write(rt2x00dev, 54, pwr2);
3128 rt2800_rfcsr_write(rt2x00dev, 55, pwr3);
3130 rt2x00_dbg(rt2x00dev, "Channel:%d, pwr1:%02x, pwr2:%02x, pwr3:%02x\n",
3131 rf->channel, pwr1, pwr2, pwr3);
3133 bbp = (info->default_power1 >> 5) |
3134 ((info->default_power2 & 0xe0) >> 1);
3135 rt2800_bbp_write(rt2x00dev, 109, bbp);
3137 bbp = rt2800_bbp_read(rt2x00dev, 110);
3139 bbp |= (info->default_power3 & 0xe0) >> 1;
3140 rt2800_bbp_write(rt2x00dev, 110, bbp);
3142 rfcsr = rt2800_rfcsr_read(rt2x00dev, 57);
3143 if (rf->channel <= 14)
3144 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
3146 rt2800_rfcsr_write(rt2x00dev, 57, 0x3e);
3148 /* Enable RF tuning */
3149 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
3150 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3151 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3155 bbp = rt2800_bbp_read(rt2x00dev, 49);
3156 /* clear update flag */
3157 rt2800_bbp_write(rt2x00dev, 49, bbp & 0xfe);
3158 rt2800_bbp_write(rt2x00dev, 49, bbp);
3160 /* TODO: add calibration for TxBF */
3163 #define POWER_BOUND 0x27
3164 #define POWER_BOUND_5G 0x2b
3166 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
3167 struct ieee80211_conf *conf,
3168 struct rf_channel *rf,
3169 struct channel_info *info)
3173 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
3174 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
3175 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
3176 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
3177 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
3179 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
3180 if (info->default_power1 > POWER_BOUND)
3181 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
3183 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
3184 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3186 rt2800_freq_cal_mode1(rt2x00dev);
3188 if (rf->channel <= 14) {
3189 if (rf->channel == 6)
3190 rt2800_bbp_write(rt2x00dev, 68, 0x0c);
3192 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
3194 if (rf->channel >= 1 && rf->channel <= 6)
3195 rt2800_bbp_write(rt2x00dev, 59, 0x0f);
3196 else if (rf->channel >= 7 && rf->channel <= 11)
3197 rt2800_bbp_write(rt2x00dev, 59, 0x0e);
3198 else if (rf->channel >= 12 && rf->channel <= 14)
3199 rt2800_bbp_write(rt2x00dev, 59, 0x0d);
3203 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
3204 struct ieee80211_conf *conf,
3205 struct rf_channel *rf,
3206 struct channel_info *info)
3210 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
3211 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
3213 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
3214 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
3215 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
3217 if (info->default_power1 > POWER_BOUND)
3218 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
3220 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
3222 if (info->default_power2 > POWER_BOUND)
3223 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
3225 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
3227 rt2800_freq_cal_mode1(rt2x00dev);
3229 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3230 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
3231 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
3233 if ( rt2x00dev->default_ant.tx_chain_num == 2 )
3234 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3236 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
3238 if ( rt2x00dev->default_ant.rx_chain_num == 2 )
3239 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3241 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
3243 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
3244 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
3246 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3248 rt2800_rfcsr_write(rt2x00dev, 31, 80);
3251 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
3252 struct ieee80211_conf *conf,
3253 struct rf_channel *rf,
3254 struct channel_info *info)
3257 int idx = rf->channel-1;
3259 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
3260 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
3261 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
3262 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
3263 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
3265 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
3266 if (info->default_power1 > POWER_BOUND)
3267 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
3269 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
3270 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3272 if (rt2x00_rt(rt2x00dev, RT5392)) {
3273 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
3274 if (info->default_power2 > POWER_BOUND)
3275 rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
3277 rt2x00_set_field8(&rfcsr, RFCSR50_TX,
3278 info->default_power2);
3279 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
3282 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3283 if (rt2x00_rt(rt2x00dev, RT5392)) {
3284 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3285 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3287 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3288 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
3289 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
3290 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
3291 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3293 rt2800_freq_cal_mode1(rt2x00dev);
3295 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
3296 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
3297 /* r55/r59 value array of channel 1~14 */
3298 static const char r55_bt_rev[] = {0x83, 0x83,
3299 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
3300 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
3301 static const char r59_bt_rev[] = {0x0e, 0x0e,
3302 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
3303 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
3305 rt2800_rfcsr_write(rt2x00dev, 55,
3307 rt2800_rfcsr_write(rt2x00dev, 59,
3310 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
3311 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
3312 0x88, 0x88, 0x86, 0x85, 0x84};
3314 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
3317 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
3318 static const char r55_nonbt_rev[] = {0x23, 0x23,
3319 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
3320 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
3321 static const char r59_nonbt_rev[] = {0x07, 0x07,
3322 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
3323 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
3325 rt2800_rfcsr_write(rt2x00dev, 55,
3326 r55_nonbt_rev[idx]);
3327 rt2800_rfcsr_write(rt2x00dev, 59,
3328 r59_nonbt_rev[idx]);
3329 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
3330 rt2x00_rt(rt2x00dev, RT5392) ||
3331 rt2x00_rt(rt2x00dev, RT6352)) {
3332 static const char r59_non_bt[] = {0x8f, 0x8f,
3333 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
3334 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
3336 rt2800_rfcsr_write(rt2x00dev, 59,
3338 } else if (rt2x00_rt(rt2x00dev, RT5350)) {
3339 static const char r59_non_bt[] = {0x0b, 0x0b,
3340 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0a,
3341 0x0a, 0x09, 0x08, 0x07, 0x07, 0x06};
3343 rt2800_rfcsr_write(rt2x00dev, 59,
3349 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
3350 struct ieee80211_conf *conf,
3351 struct rf_channel *rf,
3352 struct channel_info *info)
3359 const bool is_11b = false;
3360 const bool is_type_ep = false;
3362 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
3363 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL,
3364 (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
3365 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3367 /* Order of values on rf_channel entry: N, K, mod, R */
3368 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
3370 rfcsr = rt2800_rfcsr_read(rt2x00dev, 9);
3371 rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
3372 rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
3373 rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
3374 rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
3376 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
3377 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
3378 rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
3379 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
3381 if (rf->channel <= 14) {
3382 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
3383 /* FIXME: RF11 owerwrite ? */
3384 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
3385 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
3386 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
3387 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
3388 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
3389 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3390 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
3391 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
3392 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3393 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
3394 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
3395 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
3396 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
3397 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
3398 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
3399 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
3400 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
3401 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
3402 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3403 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
3404 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
3405 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
3406 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
3407 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
3408 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
3409 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3410 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
3411 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
3413 /* TODO RF27 <- tssi */
3415 rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
3416 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
3417 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
3421 rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
3422 rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
3424 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
3426 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
3430 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
3432 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
3435 power_bound = POWER_BOUND;
3438 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
3439 /* FIMXE: RF11 overwrite */
3440 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
3441 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
3442 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
3443 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3444 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
3445 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3446 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
3447 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
3448 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
3449 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
3450 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
3451 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
3452 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
3453 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
3455 /* TODO RF27 <- tssi */
3457 if (rf->channel >= 36 && rf->channel <= 64) {
3459 rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
3460 rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
3461 rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
3462 rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
3463 if (rf->channel <= 50)
3464 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
3465 else if (rf->channel >= 52)
3466 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
3467 rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
3468 rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
3469 rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
3470 rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
3471 rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
3472 rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
3473 rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
3474 if (rf->channel <= 50) {
3475 rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
3476 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
3477 } else if (rf->channel >= 52) {
3478 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
3479 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
3482 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
3483 rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
3484 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
3486 } else if (rf->channel >= 100 && rf->channel <= 165) {
3488 rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
3489 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
3490 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
3491 if (rf->channel <= 153) {
3492 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
3493 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
3494 } else if (rf->channel >= 155) {
3495 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
3496 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
3498 if (rf->channel <= 138) {
3499 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
3500 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
3501 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
3502 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
3503 } else if (rf->channel >= 140) {
3504 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
3505 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
3506 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
3507 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
3509 if (rf->channel <= 124)
3510 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
3511 else if (rf->channel >= 126)
3512 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
3513 if (rf->channel <= 138)
3514 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
3515 else if (rf->channel >= 140)
3516 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
3517 rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
3518 if (rf->channel <= 138)
3519 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
3520 else if (rf->channel >= 140)
3521 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
3522 if (rf->channel <= 128)
3523 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
3524 else if (rf->channel >= 130)
3525 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
3526 if (rf->channel <= 116)
3527 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
3528 else if (rf->channel >= 118)
3529 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
3530 if (rf->channel <= 138)
3531 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
3532 else if (rf->channel >= 140)
3533 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
3534 if (rf->channel <= 116)
3535 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
3536 else if (rf->channel >= 118)
3537 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
3540 power_bound = POWER_BOUND_5G;
3544 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
3545 if (info->default_power1 > power_bound)
3546 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
3548 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
3550 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
3551 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3553 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
3554 if (info->default_power2 > power_bound)
3555 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
3557 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
3559 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
3560 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
3562 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3563 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3564 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
3566 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
3567 rt2x00dev->default_ant.tx_chain_num >= 1);
3568 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
3569 rt2x00dev->default_ant.tx_chain_num == 2);
3570 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
3572 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
3573 rt2x00dev->default_ant.rx_chain_num >= 1);
3574 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
3575 rt2x00dev->default_ant.rx_chain_num == 2);
3576 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
3578 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3579 rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
3581 if (conf_is_ht40(conf))
3582 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
3584 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
3587 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3588 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3591 /* TODO proper frequency adjustment */
3592 rt2800_freq_cal_mode1(rt2x00dev);
3594 /* TODO merge with others */
3595 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
3596 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3597 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3600 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3601 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3602 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3604 rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
3605 rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
3606 rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
3607 rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
3609 /* GLRT band configuration */
3610 rt2800_bbp_write(rt2x00dev, 195, 128);
3611 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
3612 rt2800_bbp_write(rt2x00dev, 195, 129);
3613 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
3614 rt2800_bbp_write(rt2x00dev, 195, 130);
3615 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
3616 rt2800_bbp_write(rt2x00dev, 195, 131);
3617 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
3618 rt2800_bbp_write(rt2x00dev, 195, 133);
3619 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
3620 rt2800_bbp_write(rt2x00dev, 195, 124);
3621 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
3624 static void rt2800_config_channel_rf7620(struct rt2x00_dev *rt2x00dev,
3625 struct ieee80211_conf *conf,
3626 struct rf_channel *rf,
3627 struct channel_info *info)
3629 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
3630 u8 rx_agc_fc, tx_agc_fc;
3633 /* Frequeny plan setting */
3634 /* Rdiv setting (set 0x03 if Xtal==20)
3637 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
3638 rt2x00_set_field8(&rfcsr, RFCSR13_RDIV_MT7620,
3639 rt2800_clk_is_20mhz(rt2x00dev) ? 3 : 0);
3640 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
3643 * R20[7:0] in rf->rf1
3646 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
3647 rfcsr = (rf->rf1 & 0x00ff);
3648 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
3650 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
3651 rt2x00_set_field8(&rfcsr, RFCSR21_BIT1, 0);
3652 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3654 /* K setting (always 0)
3655 * R16[3:0] (RF PLL freq selection)
3657 rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
3658 rt2x00_set_field8(&rfcsr, RFCSR16_RF_PLL_FREQ_SEL_MT7620, 0);
3659 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
3661 /* D setting (always 0)
3662 * R22[2:0] (D=15, R22[2:0]=<111>)
3664 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
3665 rt2x00_set_field8(&rfcsr, RFCSR22_FREQPLAN_D_MT7620, 0);
3666 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3669 * Ksd: R17<7:0> in rf->rf2
3670 * R18<7:0> in rf->rf3
3671 * R19<1:0> in rf->rf4
3673 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
3675 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3677 rfcsr = rt2800_rfcsr_read(rt2x00dev, 18);
3679 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
3681 rfcsr = rt2800_rfcsr_read(rt2x00dev, 19);
3682 rt2x00_set_field8(&rfcsr, RFCSR19_K, rf->rf4);
3683 rt2800_rfcsr_write(rt2x00dev, 19, rfcsr);
3685 /* Default: XO=20MHz , SDM mode */
3686 rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
3687 rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80);
3688 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
3690 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
3691 rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1);
3692 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3694 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3695 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_EN_MT7620,
3696 rt2x00dev->default_ant.tx_chain_num != 1);
3697 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3699 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
3700 rt2x00_set_field8(&rfcsr, RFCSR2_TX2_EN_MT7620,
3701 rt2x00dev->default_ant.tx_chain_num != 1);
3702 rt2x00_set_field8(&rfcsr, RFCSR2_RX2_EN_MT7620,
3703 rt2x00dev->default_ant.rx_chain_num != 1);
3704 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3706 rfcsr = rt2800_rfcsr_read(rt2x00dev, 42);
3707 rt2x00_set_field8(&rfcsr, RFCSR42_TX2_EN_MT7620,
3708 rt2x00dev->default_ant.tx_chain_num != 1);
3709 rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
3711 /* RF for DC Cal BW */
3712 if (conf_is_ht40(conf)) {
3713 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
3714 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
3715 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
3716 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
3717 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
3719 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x20);
3720 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x20);
3721 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x00);
3722 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x20);
3723 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20);
3726 if (conf_is_ht40(conf)) {
3727 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08);
3728 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08);
3730 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28);
3731 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28);
3734 rfcsr = rt2800_rfcsr_read(rt2x00dev, 28);
3735 rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40,
3736 conf_is_ht40(conf) && (rf->channel == 11));
3737 rt2800_rfcsr_write(rt2x00dev, 28, rfcsr);
3739 if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) {
3740 if (conf_is_ht40(conf)) {
3741 rx_agc_fc = drv_data->rx_calibration_bw40;
3742 tx_agc_fc = drv_data->tx_calibration_bw40;
3744 rx_agc_fc = drv_data->rx_calibration_bw20;
3745 tx_agc_fc = drv_data->tx_calibration_bw20;
3747 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
3750 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rfcsr);
3751 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
3754 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rfcsr);
3755 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 6);
3758 rt2800_rfcsr_write_bank(rt2x00dev, 7, 6, rfcsr);
3759 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 7);
3762 rt2800_rfcsr_write_bank(rt2x00dev, 7, 7, rfcsr);
3764 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
3767 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rfcsr);
3768 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
3771 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rfcsr);
3772 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 58);
3775 rt2800_rfcsr_write_bank(rt2x00dev, 7, 58, rfcsr);
3776 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 59);
3779 rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr);
3783 static void rt2800_config_alc(struct rt2x00_dev *rt2x00dev,
3784 struct ieee80211_channel *chan,
3786 u16 eeprom, target_power, max_power;
3787 u32 mac_sys_ctrl, mac_status;
3792 /* hardware unit is 0.5dBm, limited to 23.5dBm */
3794 if (power_level > 0x2f)
3797 max_power = chan->max_power * 2;
3798 if (max_power > 0x2f)
3801 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_0);
3802 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_0, power_level);
3803 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_1, power_level);
3804 rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_0, max_power);
3805 rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_1, max_power);
3807 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
3808 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_INTERNAL_TX_ALC)) {
3809 /* init base power by eeprom target power */
3810 target_power = rt2800_eeprom_read(rt2x00dev,
3811 EEPROM_TXPOWER_INIT);
3812 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_0, target_power);
3813 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_1, target_power);
3815 rt2800_register_write(rt2x00dev, TX_ALC_CFG_0, reg);
3817 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1);
3818 rt2x00_set_field32(®, TX_ALC_CFG_1_TX_TEMP_COMP, 0);
3819 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
3821 /* Save MAC SYS CTRL registers */
3822 mac_sys_ctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
3824 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
3825 /* Check MAC Tx/Rx idle */
3826 for (i = 0; i < 10000; i++) {
3827 mac_status = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
3828 if (mac_status & 0x3)
3829 usleep_range(50, 200);
3835 rt2x00_warn(rt2x00dev, "Wait MAC Status to MAX !!!\n");
3837 if (chan->center_freq > 2457) {
3838 bbp = rt2800_bbp_read(rt2x00dev, 30);
3840 rt2800_bbp_write(rt2x00dev, 30, bbp);
3841 rt2800_rfcsr_write(rt2x00dev, 39, 0);
3842 if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
3843 rt2800_rfcsr_write(rt2x00dev, 42, 0xfb);
3845 rt2800_rfcsr_write(rt2x00dev, 42, 0x7b);
3847 bbp = rt2800_bbp_read(rt2x00dev, 30);
3849 rt2800_bbp_write(rt2x00dev, 30, bbp);
3850 rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
3851 if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
3852 rt2800_rfcsr_write(rt2x00dev, 42, 0xdb);
3854 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
3856 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl);
3858 rt2800_vco_calibration(rt2x00dev);
3861 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
3862 const unsigned int word,
3867 for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
3868 reg = rt2800_bbp_read(rt2x00dev, 27);
3869 rt2x00_set_field8(®, BBP27_RX_CHAIN_SEL, chain);
3870 rt2800_bbp_write(rt2x00dev, 27, reg);
3872 rt2800_bbp_write(rt2x00dev, word, value);
3876 static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
3881 rt2800_bbp_write(rt2x00dev, 158, 0x2c);
3883 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
3884 else if (channel >= 36 && channel <= 64)
3885 cal = rt2x00_eeprom_byte(rt2x00dev,
3886 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G);
3887 else if (channel >= 100 && channel <= 138)
3888 cal = rt2x00_eeprom_byte(rt2x00dev,
3889 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G);
3890 else if (channel >= 140 && channel <= 165)
3891 cal = rt2x00_eeprom_byte(rt2x00dev,
3892 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G);
3895 rt2800_bbp_write(rt2x00dev, 159, cal);
3898 rt2800_bbp_write(rt2x00dev, 158, 0x2d);
3900 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
3901 else if (channel >= 36 && channel <= 64)
3902 cal = rt2x00_eeprom_byte(rt2x00dev,
3903 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G);
3904 else if (channel >= 100 && channel <= 138)
3905 cal = rt2x00_eeprom_byte(rt2x00dev,
3906 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G);
3907 else if (channel >= 140 && channel <= 165)
3908 cal = rt2x00_eeprom_byte(rt2x00dev,
3909 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G);
3912 rt2800_bbp_write(rt2x00dev, 159, cal);
3915 rt2800_bbp_write(rt2x00dev, 158, 0x4a);
3917 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
3918 else if (channel >= 36 && channel <= 64)
3919 cal = rt2x00_eeprom_byte(rt2x00dev,
3920 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G);
3921 else if (channel >= 100 && channel <= 138)
3922 cal = rt2x00_eeprom_byte(rt2x00dev,
3923 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G);
3924 else if (channel >= 140 && channel <= 165)
3925 cal = rt2x00_eeprom_byte(rt2x00dev,
3926 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G);
3929 rt2800_bbp_write(rt2x00dev, 159, cal);
3932 rt2800_bbp_write(rt2x00dev, 158, 0x4b);
3934 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
3935 else if (channel >= 36 && channel <= 64)
3936 cal = rt2x00_eeprom_byte(rt2x00dev,
3937 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G);
3938 else if (channel >= 100 && channel <= 138)
3939 cal = rt2x00_eeprom_byte(rt2x00dev,
3940 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G);
3941 else if (channel >= 140 && channel <= 165)
3942 cal = rt2x00_eeprom_byte(rt2x00dev,
3943 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G);
3946 rt2800_bbp_write(rt2x00dev, 159, cal);
3948 /* FIXME: possible RX0, RX1 callibration ? */
3950 /* RF IQ compensation control */
3951 rt2800_bbp_write(rt2x00dev, 158, 0x04);
3952 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
3953 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3955 /* RF IQ imbalance compensation control */
3956 rt2800_bbp_write(rt2x00dev, 158, 0x03);
3957 cal = rt2x00_eeprom_byte(rt2x00dev,
3958 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
3959 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3962 static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev,
3963 unsigned int channel,
3966 if (rt2x00_rt(rt2x00dev, RT3593) ||
3967 rt2x00_rt(rt2x00dev, RT3883))
3968 txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC);
3971 return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER);
3973 if (rt2x00_rt(rt2x00dev, RT3593) ||
3974 rt2x00_rt(rt2x00dev, RT3883))
3975 return clamp_t(char, txpower, MIN_A_TXPOWER_3593,
3976 MAX_A_TXPOWER_3593);
3978 return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER);
3981 static void rt3883_bbp_adjust(struct rt2x00_dev *rt2x00dev,
3982 struct rf_channel *rf)
3986 bbp = (rf->channel > 14) ? 0x48 : 0x38;
3987 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, bbp);
3989 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3991 if (rf->channel <= 14) {
3992 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3994 /* Disable CCK packet detection */
3995 rt2800_bbp_write(rt2x00dev, 70, 0x00);
3998 rt2800_bbp_write(rt2x00dev, 73, 0x10);
4000 if (rf->channel > 14) {
4001 rt2800_bbp_write(rt2x00dev, 62, 0x1d);
4002 rt2800_bbp_write(rt2x00dev, 63, 0x1d);
4003 rt2800_bbp_write(rt2x00dev, 64, 0x1d);
4005 rt2800_bbp_write(rt2x00dev, 62, 0x2d);
4006 rt2800_bbp_write(rt2x00dev, 63, 0x2d);
4007 rt2800_bbp_write(rt2x00dev, 64, 0x2d);
4011 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
4012 struct ieee80211_conf *conf,
4013 struct rf_channel *rf,
4014 struct channel_info *info)
4020 info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
4021 info->default_power1);
4022 info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
4023 info->default_power2);
4024 if (rt2x00dev->default_ant.tx_chain_num > 2)
4025 info->default_power3 =
4026 rt2800_txpower_to_dev(rt2x00dev, rf->channel,
4027 info->default_power3);
4029 switch (rt2x00dev->chip.rt) {
4031 rt3883_bbp_adjust(rt2x00dev, rf);
4035 switch (rt2x00dev->chip.rf) {
4041 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
4044 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
4047 rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info);
4050 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
4053 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
4056 rt2800_config_channel_rf3853(rt2x00dev, conf, rf, info);
4066 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
4069 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
4072 rt2800_config_channel_rf7620(rt2x00dev, conf, rf, info);
4075 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
4078 if (rt2x00_rf(rt2x00dev, RF3070) ||
4079 rt2x00_rf(rt2x00dev, RF3290) ||
4080 rt2x00_rf(rt2x00dev, RF3322) ||
4081 rt2x00_rf(rt2x00dev, RF5350) ||
4082 rt2x00_rf(rt2x00dev, RF5360) ||
4083 rt2x00_rf(rt2x00dev, RF5362) ||
4084 rt2x00_rf(rt2x00dev, RF5370) ||
4085 rt2x00_rf(rt2x00dev, RF5372) ||
4086 rt2x00_rf(rt2x00dev, RF5390) ||
4087 rt2x00_rf(rt2x00dev, RF5392)) {
4088 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
4089 if (rt2x00_rf(rt2x00dev, RF3322)) {
4090 rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_TX_H20M,
4091 conf_is_ht40(conf));
4092 rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_RX_H20M,
4093 conf_is_ht40(conf));
4095 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M,
4096 conf_is_ht40(conf));
4097 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M,
4098 conf_is_ht40(conf));
4100 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
4102 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
4103 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
4104 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
4108 * Change BBP settings
4111 if (rt2x00_rt(rt2x00dev, RT3352)) {
4112 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4113 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4114 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4116 rt2800_bbp_write(rt2x00dev, 27, 0x0);
4117 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
4118 rt2800_bbp_write(rt2x00dev, 27, 0x20);
4119 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
4120 rt2800_bbp_write(rt2x00dev, 86, 0x38);
4121 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
4122 } else if (rt2x00_rt(rt2x00dev, RT3593)) {
4123 if (rf->channel > 14) {
4124 /* Disable CCK Packet detection on 5GHz */
4125 rt2800_bbp_write(rt2x00dev, 70, 0x00);
4127 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4130 if (conf_is_ht40(conf))
4131 rt2800_bbp_write(rt2x00dev, 105, 0x04);
4133 rt2800_bbp_write(rt2x00dev, 105, 0x34);
4135 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4136 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4137 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4138 rt2800_bbp_write(rt2x00dev, 77, 0x98);
4139 } else if (rt2x00_rt(rt2x00dev, RT3883)) {
4140 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4141 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4142 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4144 if (rt2x00dev->default_ant.rx_chain_num > 1)
4145 rt2800_bbp_write(rt2x00dev, 86, 0x46);
4147 rt2800_bbp_write(rt2x00dev, 86, 0);
4149 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4150 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4151 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4152 rt2800_bbp_write(rt2x00dev, 86, 0);
4155 if (rf->channel <= 14) {
4156 if (!rt2x00_rt(rt2x00dev, RT5390) &&
4157 !rt2x00_rt(rt2x00dev, RT5392) &&
4158 !rt2x00_rt(rt2x00dev, RT6352)) {
4159 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
4160 rt2800_bbp_write(rt2x00dev, 82, 0x62);
4161 rt2800_bbp_write(rt2x00dev, 82, 0x62);
4162 rt2800_bbp_write(rt2x00dev, 75, 0x46);
4164 if (rt2x00_rt(rt2x00dev, RT3593))
4165 rt2800_bbp_write(rt2x00dev, 82, 0x62);
4167 rt2800_bbp_write(rt2x00dev, 82, 0x84);
4168 rt2800_bbp_write(rt2x00dev, 75, 0x50);
4170 if (rt2x00_rt(rt2x00dev, RT3593) ||
4171 rt2x00_rt(rt2x00dev, RT3883))
4172 rt2800_bbp_write(rt2x00dev, 83, 0x8a);
4176 if (rt2x00_rt(rt2x00dev, RT3572))
4177 rt2800_bbp_write(rt2x00dev, 82, 0x94);
4178 else if (rt2x00_rt(rt2x00dev, RT3593) ||
4179 rt2x00_rt(rt2x00dev, RT3883))
4180 rt2800_bbp_write(rt2x00dev, 82, 0x82);
4181 else if (!rt2x00_rt(rt2x00dev, RT6352))
4182 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
4184 if (rt2x00_rt(rt2x00dev, RT3593) ||
4185 rt2x00_rt(rt2x00dev, RT3883))
4186 rt2800_bbp_write(rt2x00dev, 83, 0x9a);
4188 if (rt2x00_has_cap_external_lna_a(rt2x00dev))
4189 rt2800_bbp_write(rt2x00dev, 75, 0x46);
4191 rt2800_bbp_write(rt2x00dev, 75, 0x50);
4194 reg = rt2800_register_read(rt2x00dev, TX_BAND_CFG);
4195 rt2x00_set_field32(®, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
4196 rt2x00_set_field32(®, TX_BAND_CFG_A, rf->channel > 14);
4197 rt2x00_set_field32(®, TX_BAND_CFG_BG, rf->channel <= 14);
4198 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
4200 if (rt2x00_rt(rt2x00dev, RT3572))
4201 rt2800_rfcsr_write(rt2x00dev, 8, 0);
4203 if (rt2x00_rt(rt2x00dev, RT6352)) {
4204 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
4205 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFRX_EN, 1);
4210 switch (rt2x00dev->default_ant.tx_chain_num) {
4212 /* Turn on tertiary PAs */
4213 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN,
4215 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN,
4219 /* Turn on secondary PAs */
4220 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
4222 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
4226 /* Turn on primary PAs */
4227 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN,
4229 if (rt2x00_has_cap_bt_coexist(rt2x00dev))
4230 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
4232 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
4237 switch (rt2x00dev->default_ant.rx_chain_num) {
4239 /* Turn on tertiary LNAs */
4240 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN,
4242 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN,
4246 /* Turn on secondary LNAs */
4247 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN,
4249 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN,
4253 /* Turn on primary LNAs */
4254 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN,
4256 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN,
4261 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
4262 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
4264 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4266 if (rt2x00_rt(rt2x00dev, RT3572)) {
4267 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
4270 if (rf->channel <= 14)
4271 reg = 0x1c + (2 * rt2x00dev->lna_gain);
4273 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
4275 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
4278 if (rt2x00_rt(rt2x00dev, RT3593)) {
4279 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
4281 /* Band selection */
4282 if (rt2x00_is_usb(rt2x00dev) ||
4283 rt2x00_is_pcie(rt2x00dev)) {
4284 /* GPIO #8 controls all paths */
4285 rt2x00_set_field32(®, GPIO_CTRL_DIR8, 0);
4286 if (rf->channel <= 14)
4287 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 1);
4289 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 0);
4292 /* LNA PE control. */
4293 if (rt2x00_is_usb(rt2x00dev)) {
4294 /* GPIO #4 controls PE0 and PE1,
4295 * GPIO #7 controls PE2
4297 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0);
4298 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0);
4300 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1);
4301 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1);
4302 } else if (rt2x00_is_pcie(rt2x00dev)) {
4303 /* GPIO #4 controls PE0, PE1 and PE2 */
4304 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0);
4305 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1);
4308 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
4311 if (rf->channel <= 14)
4312 reg = 0x1c + 2 * rt2x00dev->lna_gain;
4314 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
4316 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
4318 usleep_range(1000, 1500);
4321 if (rt2x00_rt(rt2x00dev, RT3883)) {
4322 if (!conf_is_ht40(conf))
4323 rt2800_bbp_write(rt2x00dev, 105, 0x34);
4325 rt2800_bbp_write(rt2x00dev, 105, 0x04);
4328 if (rf->channel <= 14)
4329 reg = 0x2e + rt2x00dev->lna_gain;
4331 reg = 0x20 + ((rt2x00dev->lna_gain * 5) / 3);
4333 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
4335 usleep_range(1000, 1500);
4338 if (rt2x00_rt(rt2x00dev, RT5592) || rt2x00_rt(rt2x00dev, RT6352)) {
4340 if (!conf_is_ht40(conf)) {
4341 if (rt2x00_rt(rt2x00dev, RT6352) &&
4342 rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
4348 rt2800_bbp_write(rt2x00dev, 195, 141);
4349 rt2800_bbp_write(rt2x00dev, 196, reg);
4352 * Despite the vendor driver using different values here for
4353 * RT6352 chip, we use 0x1c for now. This may have to be changed
4354 * once TSSI got implemented.
4356 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2*rt2x00dev->lna_gain;
4357 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
4359 rt2800_iq_calibrate(rt2x00dev, rf->channel);
4362 bbp = rt2800_bbp_read(rt2x00dev, 4);
4363 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
4364 rt2800_bbp_write(rt2x00dev, 4, bbp);
4366 bbp = rt2800_bbp_read(rt2x00dev, 3);
4367 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
4368 rt2800_bbp_write(rt2x00dev, 3, bbp);
4370 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
4371 if (conf_is_ht40(conf)) {
4372 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
4373 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4374 rt2800_bbp_write(rt2x00dev, 73, 0x16);
4376 rt2800_bbp_write(rt2x00dev, 69, 0x16);
4377 rt2800_bbp_write(rt2x00dev, 70, 0x08);
4378 rt2800_bbp_write(rt2x00dev, 73, 0x11);
4382 usleep_range(1000, 1500);
4385 * Clear channel statistic counters
4387 reg = rt2800_register_read(rt2x00dev, CH_IDLE_STA);
4388 reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA);
4389 reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC);
4394 if (rt2x00_rt(rt2x00dev, RT3352) ||
4395 rt2x00_rt(rt2x00dev, RT5350)) {
4396 bbp = rt2800_bbp_read(rt2x00dev, 49);
4397 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
4398 rt2800_bbp_write(rt2x00dev, 49, bbp);
4402 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
4411 * First check if temperature compensation is supported.
4413 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
4414 if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC))
4418 * Read TSSI boundaries for temperature compensation from
4421 * Array idx 0 1 2 3 4 5 6 7 8
4422 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
4423 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
4425 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
4426 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1);
4427 tssi_bounds[0] = rt2x00_get_field16(eeprom,
4428 EEPROM_TSSI_BOUND_BG1_MINUS4);
4429 tssi_bounds[1] = rt2x00_get_field16(eeprom,
4430 EEPROM_TSSI_BOUND_BG1_MINUS3);
4432 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2);
4433 tssi_bounds[2] = rt2x00_get_field16(eeprom,
4434 EEPROM_TSSI_BOUND_BG2_MINUS2);
4435 tssi_bounds[3] = rt2x00_get_field16(eeprom,
4436 EEPROM_TSSI_BOUND_BG2_MINUS1);
4438 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3);
4439 tssi_bounds[4] = rt2x00_get_field16(eeprom,
4440 EEPROM_TSSI_BOUND_BG3_REF);
4441 tssi_bounds[5] = rt2x00_get_field16(eeprom,
4442 EEPROM_TSSI_BOUND_BG3_PLUS1);
4444 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4);
4445 tssi_bounds[6] = rt2x00_get_field16(eeprom,
4446 EEPROM_TSSI_BOUND_BG4_PLUS2);
4447 tssi_bounds[7] = rt2x00_get_field16(eeprom,
4448 EEPROM_TSSI_BOUND_BG4_PLUS3);
4450 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5);
4451 tssi_bounds[8] = rt2x00_get_field16(eeprom,
4452 EEPROM_TSSI_BOUND_BG5_PLUS4);
4454 step = rt2x00_get_field16(eeprom,
4455 EEPROM_TSSI_BOUND_BG5_AGC_STEP);
4457 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1);
4458 tssi_bounds[0] = rt2x00_get_field16(eeprom,
4459 EEPROM_TSSI_BOUND_A1_MINUS4);
4460 tssi_bounds[1] = rt2x00_get_field16(eeprom,
4461 EEPROM_TSSI_BOUND_A1_MINUS3);
4463 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2);
4464 tssi_bounds[2] = rt2x00_get_field16(eeprom,
4465 EEPROM_TSSI_BOUND_A2_MINUS2);
4466 tssi_bounds[3] = rt2x00_get_field16(eeprom,
4467 EEPROM_TSSI_BOUND_A2_MINUS1);
4469 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3);
4470 tssi_bounds[4] = rt2x00_get_field16(eeprom,
4471 EEPROM_TSSI_BOUND_A3_REF);
4472 tssi_bounds[5] = rt2x00_get_field16(eeprom,
4473 EEPROM_TSSI_BOUND_A3_PLUS1);
4475 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4);
4476 tssi_bounds[6] = rt2x00_get_field16(eeprom,
4477 EEPROM_TSSI_BOUND_A4_PLUS2);
4478 tssi_bounds[7] = rt2x00_get_field16(eeprom,
4479 EEPROM_TSSI_BOUND_A4_PLUS3);
4481 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5);
4482 tssi_bounds[8] = rt2x00_get_field16(eeprom,
4483 EEPROM_TSSI_BOUND_A5_PLUS4);
4485 step = rt2x00_get_field16(eeprom,
4486 EEPROM_TSSI_BOUND_A5_AGC_STEP);
4490 * Check if temperature compensation is supported.
4492 if (tssi_bounds[4] == 0xff || step == 0xff)
4496 * Read current TSSI (BBP 49).
4498 current_tssi = rt2800_bbp_read(rt2x00dev, 49);
4501 * Compare TSSI value (BBP49) with the compensation boundaries
4502 * from the EEPROM and increase or decrease tx power.
4504 for (i = 0; i <= 3; i++) {
4505 if (current_tssi > tssi_bounds[i])
4510 for (i = 8; i >= 5; i--) {
4511 if (current_tssi < tssi_bounds[i])
4516 return (i - 4) * step;
4519 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
4520 enum nl80211_band band)
4527 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA);
4530 * HT40 compensation not required.
4532 if (eeprom == 0xffff ||
4533 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4536 if (band == NL80211_BAND_2GHZ) {
4537 comp_en = rt2x00_get_field16(eeprom,
4538 EEPROM_TXPOWER_DELTA_ENABLE_2G);
4540 comp_type = rt2x00_get_field16(eeprom,
4541 EEPROM_TXPOWER_DELTA_TYPE_2G);
4542 comp_value = rt2x00_get_field16(eeprom,
4543 EEPROM_TXPOWER_DELTA_VALUE_2G);
4545 comp_value = -comp_value;
4548 comp_en = rt2x00_get_field16(eeprom,
4549 EEPROM_TXPOWER_DELTA_ENABLE_5G);
4551 comp_type = rt2x00_get_field16(eeprom,
4552 EEPROM_TXPOWER_DELTA_TYPE_5G);
4553 comp_value = rt2x00_get_field16(eeprom,
4554 EEPROM_TXPOWER_DELTA_VALUE_5G);
4556 comp_value = -comp_value;
4563 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
4564 int power_level, int max_power)
4568 if (rt2x00_has_cap_power_limit(rt2x00dev))
4572 * XXX: We don't know the maximum transmit power of our hardware since
4573 * the EEPROM doesn't expose it. We only know that we are calibrated
4576 * Hence, we assume the regulatory limit that cfg80211 calulated for
4577 * the current channel is our maximum and if we are requested to lower
4578 * the value we just reduce our tx power accordingly.
4580 delta = power_level - max_power;
4581 return min(delta, 0);
4584 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
4585 enum nl80211_band band, int power_level,
4586 u8 txpower, int delta)
4591 u8 eirp_txpower_criterion;
4594 if (rt2x00_rt(rt2x00dev, RT3593))
4595 return min_t(u8, txpower, 0xc);
4597 if (rt2x00_rt(rt2x00dev, RT3883))
4598 return min_t(u8, txpower, 0xf);
4600 if (rt2x00_has_cap_power_limit(rt2x00dev)) {
4602 * Check if eirp txpower exceed txpower_limit.
4603 * We use OFDM 6M as criterion and its eirp txpower
4604 * is stored at EEPROM_EIRP_MAX_TX_POWER.
4605 * .11b data rate need add additional 4dbm
4606 * when calculating eirp txpower.
4608 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
4609 EEPROM_TXPOWER_BYRATE,
4611 criterion = rt2x00_get_field16(eeprom,
4612 EEPROM_TXPOWER_BYRATE_RATE0);
4614 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER);
4616 if (band == NL80211_BAND_2GHZ)
4617 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
4618 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
4620 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
4621 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
4623 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
4624 (is_rate_b ? 4 : 0) + delta;
4626 reg_limit = (eirp_txpower > power_level) ?
4627 (eirp_txpower - power_level) : 0;
4631 txpower = max(0, txpower + delta - reg_limit);
4632 return min_t(u8, txpower, 0xc);
4647 TX_PWR_CFG_0_EXT_IDX,
4648 TX_PWR_CFG_1_EXT_IDX,
4649 TX_PWR_CFG_2_EXT_IDX,
4650 TX_PWR_CFG_3_EXT_IDX,
4651 TX_PWR_CFG_4_EXT_IDX,
4652 TX_PWR_CFG_IDX_COUNT,
4655 static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev,
4656 struct ieee80211_channel *chan,
4661 u32 regs[TX_PWR_CFG_IDX_COUNT];
4662 unsigned int offset;
4663 enum nl80211_band band = chan->band;
4667 memset(regs, '\0', sizeof(regs));
4669 /* TODO: adapt TX power reduction from the rt28xx code */
4671 /* calculate temperature compensation delta */
4672 delta = rt2800_get_gain_calibration_delta(rt2x00dev);
4674 if (band == NL80211_BAND_5GHZ)
4679 if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4682 /* read the next four txpower values */
4683 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4687 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4688 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
4690 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX],
4691 TX_PWR_CFG_0_CCK1_CH0, txpower);
4692 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX],
4693 TX_PWR_CFG_0_CCK1_CH1, txpower);
4694 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX],
4695 TX_PWR_CFG_0_EXT_CCK1_CH2, txpower);
4697 /* CCK 5.5MBS,11MBS */
4698 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4699 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
4701 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX],
4702 TX_PWR_CFG_0_CCK5_CH0, txpower);
4703 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX],
4704 TX_PWR_CFG_0_CCK5_CH1, txpower);
4705 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX],
4706 TX_PWR_CFG_0_EXT_CCK5_CH2, txpower);
4708 /* OFDM 6MBS,9MBS */
4709 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4710 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4712 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX],
4713 TX_PWR_CFG_0_OFDM6_CH0, txpower);
4714 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX],
4715 TX_PWR_CFG_0_OFDM6_CH1, txpower);
4716 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX],
4717 TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower);
4719 /* OFDM 12MBS,18MBS */
4720 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4721 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4723 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX],
4724 TX_PWR_CFG_0_OFDM12_CH0, txpower);
4725 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX],
4726 TX_PWR_CFG_0_OFDM12_CH1, txpower);
4727 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX],
4728 TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower);
4730 /* read the next four txpower values */
4731 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4734 /* OFDM 24MBS,36MBS */
4735 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4736 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4738 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX],
4739 TX_PWR_CFG_1_OFDM24_CH0, txpower);
4740 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX],
4741 TX_PWR_CFG_1_OFDM24_CH1, txpower);
4742 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX],
4743 TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower);
4746 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4747 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4749 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX],
4750 TX_PWR_CFG_1_OFDM48_CH0, txpower);
4751 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX],
4752 TX_PWR_CFG_1_OFDM48_CH1, txpower);
4753 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX],
4754 TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower);
4757 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4758 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4760 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX],
4761 TX_PWR_CFG_7_OFDM54_CH0, txpower);
4762 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX],
4763 TX_PWR_CFG_7_OFDM54_CH1, txpower);
4764 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX],
4765 TX_PWR_CFG_7_OFDM54_CH2, txpower);
4767 /* read the next four txpower values */
4768 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4772 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4773 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4775 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX],
4776 TX_PWR_CFG_1_MCS0_CH0, txpower);
4777 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX],
4778 TX_PWR_CFG_1_MCS0_CH1, txpower);
4779 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX],
4780 TX_PWR_CFG_1_EXT_MCS0_CH2, txpower);
4783 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4784 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4786 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX],
4787 TX_PWR_CFG_1_MCS2_CH0, txpower);
4788 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX],
4789 TX_PWR_CFG_1_MCS2_CH1, txpower);
4790 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX],
4791 TX_PWR_CFG_1_EXT_MCS2_CH2, txpower);
4794 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4795 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4797 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX],
4798 TX_PWR_CFG_2_MCS4_CH0, txpower);
4799 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX],
4800 TX_PWR_CFG_2_MCS4_CH1, txpower);
4801 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX],
4802 TX_PWR_CFG_2_EXT_MCS4_CH2, txpower);
4805 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4806 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4808 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX],
4809 TX_PWR_CFG_2_MCS6_CH0, txpower);
4810 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX],
4811 TX_PWR_CFG_2_MCS6_CH1, txpower);
4812 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX],
4813 TX_PWR_CFG_2_EXT_MCS6_CH2, txpower);
4815 /* read the next four txpower values */
4816 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4820 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4821 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4823 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX],
4824 TX_PWR_CFG_7_MCS7_CH0, txpower);
4825 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX],
4826 TX_PWR_CFG_7_MCS7_CH1, txpower);
4827 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX],
4828 TX_PWR_CFG_7_MCS7_CH2, txpower);
4831 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4832 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4834 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX],
4835 TX_PWR_CFG_2_MCS8_CH0, txpower);
4836 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX],
4837 TX_PWR_CFG_2_MCS8_CH1, txpower);
4838 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX],
4839 TX_PWR_CFG_2_EXT_MCS8_CH2, txpower);
4842 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4843 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4845 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX],
4846 TX_PWR_CFG_2_MCS10_CH0, txpower);
4847 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX],
4848 TX_PWR_CFG_2_MCS10_CH1, txpower);
4849 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX],
4850 TX_PWR_CFG_2_EXT_MCS10_CH2, txpower);
4853 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4854 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4856 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX],
4857 TX_PWR_CFG_3_MCS12_CH0, txpower);
4858 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX],
4859 TX_PWR_CFG_3_MCS12_CH1, txpower);
4860 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX],
4861 TX_PWR_CFG_3_EXT_MCS12_CH2, txpower);
4863 /* read the next four txpower values */
4864 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4868 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4869 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4871 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX],
4872 TX_PWR_CFG_3_MCS14_CH0, txpower);
4873 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX],
4874 TX_PWR_CFG_3_MCS14_CH1, txpower);
4875 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX],
4876 TX_PWR_CFG_3_EXT_MCS14_CH2, txpower);
4879 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4880 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4882 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX],
4883 TX_PWR_CFG_8_MCS15_CH0, txpower);
4884 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX],
4885 TX_PWR_CFG_8_MCS15_CH1, txpower);
4886 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX],
4887 TX_PWR_CFG_8_MCS15_CH2, txpower);
4890 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4891 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4893 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX],
4894 TX_PWR_CFG_5_MCS16_CH0, txpower);
4895 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX],
4896 TX_PWR_CFG_5_MCS16_CH1, txpower);
4897 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX],
4898 TX_PWR_CFG_5_MCS16_CH2, txpower);
4901 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4902 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4904 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX],
4905 TX_PWR_CFG_5_MCS18_CH0, txpower);
4906 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX],
4907 TX_PWR_CFG_5_MCS18_CH1, txpower);
4908 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX],
4909 TX_PWR_CFG_5_MCS18_CH2, txpower);
4911 /* read the next four txpower values */
4912 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4916 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4917 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4919 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX],
4920 TX_PWR_CFG_6_MCS20_CH0, txpower);
4921 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX],
4922 TX_PWR_CFG_6_MCS20_CH1, txpower);
4923 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX],
4924 TX_PWR_CFG_6_MCS20_CH2, txpower);
4927 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4928 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4930 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX],
4931 TX_PWR_CFG_6_MCS22_CH0, txpower);
4932 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX],
4933 TX_PWR_CFG_6_MCS22_CH1, txpower);
4934 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX],
4935 TX_PWR_CFG_6_MCS22_CH2, txpower);
4938 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4939 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4941 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX],
4942 TX_PWR_CFG_8_MCS23_CH0, txpower);
4943 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX],
4944 TX_PWR_CFG_8_MCS23_CH1, txpower);
4945 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX],
4946 TX_PWR_CFG_8_MCS23_CH2, txpower);
4948 /* read the next four txpower values */
4949 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4953 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4954 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4956 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX],
4957 TX_PWR_CFG_3_STBC0_CH0, txpower);
4958 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX],
4959 TX_PWR_CFG_3_STBC0_CH1, txpower);
4960 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX],
4961 TX_PWR_CFG_3_EXT_STBC0_CH2, txpower);
4964 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4965 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4967 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX],
4968 TX_PWR_CFG_3_STBC2_CH0, txpower);
4969 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX],
4970 TX_PWR_CFG_3_STBC2_CH1, txpower);
4971 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX],
4972 TX_PWR_CFG_3_EXT_STBC2_CH2, txpower);
4975 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4976 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4978 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower);
4979 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower);
4980 rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0,
4984 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4985 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4987 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower);
4988 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower);
4989 rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2,
4992 /* read the next four txpower values */
4993 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4997 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4998 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5000 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX],
5001 TX_PWR_CFG_9_STBC7_CH0, txpower);
5002 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX],
5003 TX_PWR_CFG_9_STBC7_CH1, txpower);
5004 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX],
5005 TX_PWR_CFG_9_STBC7_CH2, txpower);
5007 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]);
5008 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]);
5009 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]);
5010 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]);
5011 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]);
5012 rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]);
5013 rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]);
5014 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]);
5015 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]);
5016 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]);
5018 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT,
5019 regs[TX_PWR_CFG_0_EXT_IDX]);
5020 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT,
5021 regs[TX_PWR_CFG_1_EXT_IDX]);
5022 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT,
5023 regs[TX_PWR_CFG_2_EXT_IDX]);
5024 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT,
5025 regs[TX_PWR_CFG_3_EXT_IDX]);
5026 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT,
5027 regs[TX_PWR_CFG_4_EXT_IDX]);
5029 for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++)
5030 rt2x00_dbg(rt2x00dev,
5031 "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n",
5032 (band == NL80211_BAND_5GHZ) ? '5' : '2',
5033 (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ?
5035 (i > TX_PWR_CFG_9_IDX) ?
5036 (i - TX_PWR_CFG_9_IDX - 1) : i,
5037 (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "",
5038 (unsigned long) regs[i]);
5041 static void rt2800_config_txpower_rt6352(struct rt2x00_dev *rt2x00dev,
5042 struct ieee80211_channel *chan,
5049 enum nl80211_band band = chan->band;
5052 /* Warn user if bw_comp is set in EEPROM */
5053 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
5056 rt2x00_warn(rt2x00dev, "ignoring EEPROM HT40 power delta: %d\n",
5059 /* populate TX_PWR_CFG_0 up to TX_PWR_CFG_4 from EEPROM for HT20, limit
5060 * value to 0x3f and replace 0x20 by 0x21 as this is what the vendor
5061 * driver does as well, though it looks kinda wrong.
5062 * Maybe some misunderstanding of what a signed 8-bit value is? Maybe
5063 * the hardware has a problem handling 0x20, and as the code initially
5064 * used a fixed offset between HT20 and HT40 rates they had to work-
5065 * around that issue and most likely just forgot about it later on.
5066 * Maybe we should use rt2800_get_txpower_bw_comp() here as well,
5067 * however, the corresponding EEPROM value is not respected by the
5068 * vendor driver, so maybe this is rather being taken care of the
5069 * TXALC and the driver doesn't need to handle it...?
5070 * Though this is all very awkward, just do as they did, as that's what
5071 * board vendors expected when they populated the EEPROM...
5073 for (i = 0; i < 5; i++) {
5074 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
5075 EEPROM_TXPOWER_BYRATE,
5086 t = (eeprom & 0x3f00) >> 8;
5092 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
5093 EEPROM_TXPOWER_BYRATE,
5102 t = (eeprom & 0x3f00) >> 8;
5107 data |= (eeprom << 16);
5109 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) {
5111 if (data != 0xffffffff)
5112 rt2800_register_write(rt2x00dev,
5113 TX_PWR_CFG_0 + (i * 4),
5117 if (gdata != 0xffffffff)
5118 rt2800_register_write(rt2x00dev,
5119 TX_PWR_CFG_0 + (i * 4),
5124 /* Aparently Ralink ran out of space in the BYRATE calibration section
5125 * of the EERPOM which is copied to the corresponding TX_PWR_CFG_x
5126 * registers. As recent 2T chips use 8-bit instead of 4-bit values for
5127 * power-offsets more space would be needed. Ralink decided to keep the
5128 * EEPROM layout untouched and rather have some shared values covering
5129 * multiple bitrates.
5130 * Populate the registers not covered by the EEPROM in the same way the
5131 * vendor driver does.
5134 /* For OFDM 54MBS use value from OFDM 48MBS */
5136 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_1);
5137 t = rt2x00_get_field32(reg, TX_PWR_CFG_1B_48MBS);
5138 rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_54MBS, t);
5140 /* For MCS 7 use value from MCS 6 */
5141 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_2);
5142 t = rt2x00_get_field32(reg, TX_PWR_CFG_2B_MCS6_MCS7);
5143 rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_MCS7, t);
5144 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, pwreg);
5146 /* For MCS 15 use value from MCS 14 */
5148 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_3);
5149 t = rt2x00_get_field32(reg, TX_PWR_CFG_3B_MCS14);
5150 rt2x00_set_field32(&pwreg, TX_PWR_CFG_8B_MCS15, t);
5151 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, pwreg);
5153 /* For STBC MCS 7 use value from STBC MCS 6 */
5155 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_4);
5156 t = rt2x00_get_field32(reg, TX_PWR_CFG_4B_STBC_MCS6);
5157 rt2x00_set_field32(&pwreg, TX_PWR_CFG_9B_STBC_MCS7, t);
5158 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, pwreg);
5160 rt2800_config_alc(rt2x00dev, chan, power_level);
5162 /* TODO: temperature compensation code! */
5166 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
5167 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
5168 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
5169 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
5170 * Reference per rate transmit power values are located in the EEPROM at
5171 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
5172 * current conditions (i.e. band, bandwidth, temperature, user settings).
5174 static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev,
5175 struct ieee80211_channel *chan,
5181 int i, is_rate_b, delta, power_ctrl;
5182 enum nl80211_band band = chan->band;
5185 * Calculate HT40 compensation. For 40MHz we need to add or subtract
5186 * value read from EEPROM (different for 2GHz and for 5GHz).
5188 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
5191 * Calculate temperature compensation. Depends on measurement of current
5192 * TSSI (Transmitter Signal Strength Indication) we know TX power (due
5193 * to temperature or maybe other factors) is smaller or bigger than
5194 * expected. We adjust it, based on TSSI reference and boundaries values
5195 * provided in EEPROM.
5197 switch (rt2x00dev->chip.rt) {
5205 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
5208 /* TODO: temperature compensation code for other chips. */
5213 * Decrease power according to user settings, on devices with unknown
5214 * maximum tx power. For other devices we take user power_level into
5215 * consideration on rt2800_compensate_txpower().
5217 delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
5221 * BBP_R1 controls TX power for all rates, it allow to set the following
5222 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
5224 * TODO: we do not use +6 dBm option to do not increase power beyond
5225 * regulatory limit, however this could be utilized for devices with
5226 * CAPABILITY_POWER_LIMIT.
5231 } else if (delta <= -6) {
5237 r1 = rt2800_bbp_read(rt2x00dev, 1);
5238 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
5239 rt2800_bbp_write(rt2x00dev, 1, r1);
5241 offset = TX_PWR_CFG_0;
5243 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
5244 /* just to be safe */
5245 if (offset > TX_PWR_CFG_4)
5248 reg = rt2800_register_read(rt2x00dev, offset);
5250 /* read the next four txpower values */
5251 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
5252 EEPROM_TXPOWER_BYRATE,
5255 is_rate_b = i ? 0 : 1;
5257 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
5258 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
5259 * TX_PWR_CFG_4: unknown
5261 txpower = rt2x00_get_field16(eeprom,
5262 EEPROM_TXPOWER_BYRATE_RATE0);
5263 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5264 power_level, txpower, delta);
5265 rt2x00_set_field32(®, TX_PWR_CFG_RATE0, txpower);
5268 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
5269 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
5270 * TX_PWR_CFG_4: unknown
5272 txpower = rt2x00_get_field16(eeprom,
5273 EEPROM_TXPOWER_BYRATE_RATE1);
5274 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5275 power_level, txpower, delta);
5276 rt2x00_set_field32(®, TX_PWR_CFG_RATE1, txpower);
5279 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
5280 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
5281 * TX_PWR_CFG_4: unknown
5283 txpower = rt2x00_get_field16(eeprom,
5284 EEPROM_TXPOWER_BYRATE_RATE2);
5285 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5286 power_level, txpower, delta);
5287 rt2x00_set_field32(®, TX_PWR_CFG_RATE2, txpower);
5290 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
5291 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
5292 * TX_PWR_CFG_4: unknown
5294 txpower = rt2x00_get_field16(eeprom,
5295 EEPROM_TXPOWER_BYRATE_RATE3);
5296 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5297 power_level, txpower, delta);
5298 rt2x00_set_field32(®, TX_PWR_CFG_RATE3, txpower);
5300 /* read the next four txpower values */
5301 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
5302 EEPROM_TXPOWER_BYRATE,
5307 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
5308 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
5309 * TX_PWR_CFG_4: unknown
5311 txpower = rt2x00_get_field16(eeprom,
5312 EEPROM_TXPOWER_BYRATE_RATE0);
5313 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5314 power_level, txpower, delta);
5315 rt2x00_set_field32(®, TX_PWR_CFG_RATE4, txpower);
5318 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
5319 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
5320 * TX_PWR_CFG_4: unknown
5322 txpower = rt2x00_get_field16(eeprom,
5323 EEPROM_TXPOWER_BYRATE_RATE1);
5324 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5325 power_level, txpower, delta);
5326 rt2x00_set_field32(®, TX_PWR_CFG_RATE5, txpower);
5329 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
5330 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
5331 * TX_PWR_CFG_4: unknown
5333 txpower = rt2x00_get_field16(eeprom,
5334 EEPROM_TXPOWER_BYRATE_RATE2);
5335 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5336 power_level, txpower, delta);
5337 rt2x00_set_field32(®, TX_PWR_CFG_RATE6, txpower);
5340 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
5341 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
5342 * TX_PWR_CFG_4: unknown
5344 txpower = rt2x00_get_field16(eeprom,
5345 EEPROM_TXPOWER_BYRATE_RATE3);
5346 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5347 power_level, txpower, delta);
5348 rt2x00_set_field32(®, TX_PWR_CFG_RATE7, txpower);
5350 rt2800_register_write(rt2x00dev, offset, reg);
5352 /* next TX_PWR_CFG register */
5357 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
5358 struct ieee80211_channel *chan,
5361 if (rt2x00_rt(rt2x00dev, RT3593) ||
5362 rt2x00_rt(rt2x00dev, RT3883))
5363 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
5364 else if (rt2x00_rt(rt2x00dev, RT6352))
5365 rt2800_config_txpower_rt6352(rt2x00dev, chan, power_level);
5367 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level);
5370 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
5372 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
5373 rt2x00dev->tx_power);
5375 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
5377 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
5381 unsigned long min_sleep = 0;
5384 * A voltage-controlled oscillator(VCO) is an electronic oscillator
5385 * designed to be controlled in oscillation frequency by a voltage
5386 * input. Maybe the temperature will affect the frequency of
5387 * oscillation to be shifted. The VCO calibration will be called
5388 * periodically to adjust the frequency to be precision.
5391 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
5392 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
5393 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
5395 switch (rt2x00dev->chip.rf) {
5402 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
5403 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
5404 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
5418 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
5419 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
5420 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
5424 rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
5425 rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
5426 rfcsr = rt2800_rfcsr_read(rt2x00dev, 4);
5427 rt2x00_set_field8(&rfcsr, RFCSR4_VCOCAL_EN, 1);
5428 rt2800_rfcsr_write(rt2x00dev, 4, rfcsr);
5432 WARN_ONCE(1, "Not supported RF chipset %x for VCO recalibration",
5433 rt2x00dev->chip.rf);
5438 usleep_range(min_sleep, min_sleep * 2);
5440 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
5441 if (rt2x00dev->rf_channel <= 14) {
5442 switch (rt2x00dev->default_ant.tx_chain_num) {
5444 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
5447 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
5451 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
5455 switch (rt2x00dev->default_ant.tx_chain_num) {
5457 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
5460 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
5464 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
5468 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
5470 if (rt2x00_rt(rt2x00dev, RT6352)) {
5471 if (rt2x00dev->default_ant.rx_chain_num == 1) {
5472 rt2800_bbp_write(rt2x00dev, 91, 0x07);
5473 rt2800_bbp_write(rt2x00dev, 95, 0x1A);
5474 rt2800_bbp_write(rt2x00dev, 195, 128);
5475 rt2800_bbp_write(rt2x00dev, 196, 0xA0);
5476 rt2800_bbp_write(rt2x00dev, 195, 170);
5477 rt2800_bbp_write(rt2x00dev, 196, 0x12);
5478 rt2800_bbp_write(rt2x00dev, 195, 171);
5479 rt2800_bbp_write(rt2x00dev, 196, 0x10);
5481 rt2800_bbp_write(rt2x00dev, 91, 0x06);
5482 rt2800_bbp_write(rt2x00dev, 95, 0x9A);
5483 rt2800_bbp_write(rt2x00dev, 195, 128);
5484 rt2800_bbp_write(rt2x00dev, 196, 0xE0);
5485 rt2800_bbp_write(rt2x00dev, 195, 170);
5486 rt2800_bbp_write(rt2x00dev, 196, 0x30);
5487 rt2800_bbp_write(rt2x00dev, 195, 171);
5488 rt2800_bbp_write(rt2x00dev, 196, 0x30);
5491 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
5492 rt2800_bbp_write(rt2x00dev, 75, 0x68);
5493 rt2800_bbp_write(rt2x00dev, 76, 0x4C);
5494 rt2800_bbp_write(rt2x00dev, 79, 0x1C);
5495 rt2800_bbp_write(rt2x00dev, 80, 0x0C);
5496 rt2800_bbp_write(rt2x00dev, 82, 0xB6);
5499 /* On 11A, We should delay and wait RF/BBP to be stable
5500 * and the appropriate time should be 1000 micro seconds
5501 * 2005/06/05 - On 11G, we also need this delay time.
5502 * Otherwise it's difficult to pass the WHQL.
5504 usleep_range(1000, 1500);
5507 EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
5509 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
5510 struct rt2x00lib_conf *libconf)
5514 reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG);
5515 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT,
5516 libconf->conf->short_frame_max_tx_count);
5517 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT,
5518 libconf->conf->long_frame_max_tx_count);
5519 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
5522 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
5523 struct rt2x00lib_conf *libconf)
5525 enum dev_state state =
5526 (libconf->conf->flags & IEEE80211_CONF_PS) ?
5527 STATE_SLEEP : STATE_AWAKE;
5530 if (state == STATE_SLEEP) {
5531 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
5533 reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG);
5534 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
5535 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
5536 libconf->conf->listen_interval - 1);
5537 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 1);
5538 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5540 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
5542 reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG);
5543 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
5544 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
5545 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 0);
5546 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5548 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
5552 void rt2800_config(struct rt2x00_dev *rt2x00dev,
5553 struct rt2x00lib_conf *libconf,
5554 const unsigned int flags)
5556 /* Always recalculate LNA gain before changing configuration */
5557 rt2800_config_lna_gain(rt2x00dev, libconf);
5559 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
5560 rt2800_config_channel(rt2x00dev, libconf->conf,
5561 &libconf->rf, &libconf->channel);
5562 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
5563 libconf->conf->power_level);
5565 if (flags & IEEE80211_CONF_CHANGE_POWER)
5566 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
5567 libconf->conf->power_level);
5568 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
5569 rt2800_config_retry_limit(rt2x00dev, libconf);
5570 if (flags & IEEE80211_CONF_CHANGE_PS)
5571 rt2800_config_ps(rt2x00dev, libconf);
5573 EXPORT_SYMBOL_GPL(rt2800_config);
5578 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
5583 * Update FCS error count from register.
5585 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0);
5586 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
5588 EXPORT_SYMBOL_GPL(rt2800_link_stats);
5590 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
5594 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
5595 if (rt2x00_rt(rt2x00dev, RT3070) ||
5596 rt2x00_rt(rt2x00dev, RT3071) ||
5597 rt2x00_rt(rt2x00dev, RT3090) ||
5598 rt2x00_rt(rt2x00dev, RT3290) ||
5599 rt2x00_rt(rt2x00dev, RT3390) ||
5600 rt2x00_rt(rt2x00dev, RT3572) ||
5601 rt2x00_rt(rt2x00dev, RT3593) ||
5602 rt2x00_rt(rt2x00dev, RT5390) ||
5603 rt2x00_rt(rt2x00dev, RT5392) ||
5604 rt2x00_rt(rt2x00dev, RT5592) ||
5605 rt2x00_rt(rt2x00dev, RT6352))
5606 vgc = 0x1c + (2 * rt2x00dev->lna_gain);
5608 vgc = 0x2e + rt2x00dev->lna_gain;
5609 } else { /* 5GHZ band */
5610 if (rt2x00_rt(rt2x00dev, RT3593) ||
5611 rt2x00_rt(rt2x00dev, RT3883))
5612 vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3;
5613 else if (rt2x00_rt(rt2x00dev, RT5592))
5614 vgc = 0x24 + (2 * rt2x00dev->lna_gain);
5616 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
5617 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
5619 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
5626 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
5627 struct link_qual *qual, u8 vgc_level)
5629 if (qual->vgc_level != vgc_level) {
5630 if (rt2x00_rt(rt2x00dev, RT3572) ||
5631 rt2x00_rt(rt2x00dev, RT3593) ||
5632 rt2x00_rt(rt2x00dev, RT3883)) {
5633 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66,
5635 } else if (rt2x00_rt(rt2x00dev, RT5592)) {
5636 rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
5637 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
5639 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
5642 qual->vgc_level = vgc_level;
5643 qual->vgc_level_reg = vgc_level;
5647 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
5649 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
5651 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
5653 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
5658 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
5661 /* When RSSI is better than a certain threshold, increase VGC
5662 * with a chip specific value in order to improve the balance
5663 * between sensibility and noise isolation.
5666 vgc = rt2800_get_default_vgc(rt2x00dev);
5668 switch (rt2x00dev->chip.rt) {
5671 if (qual->rssi > -65) {
5672 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ)
5680 if (qual->rssi > -65)
5685 if (qual->rssi > -65)
5690 if (qual->rssi > -80)
5695 rt2800_set_vgc(rt2x00dev, qual, vgc);
5697 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
5700 * Initialization functions.
5702 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
5704 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5710 rt2800_disable_wpdma(rt2x00dev);
5712 ret = rt2800_drv_init_registers(rt2x00dev);
5716 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
5717 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
5719 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
5721 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
5722 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
5723 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0);
5724 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, 0);
5725 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0);
5726 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0);
5727 rt2x00_set_field32(®, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
5728 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
5730 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
5732 reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG);
5733 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 9);
5734 rt2x00_set_field32(®, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
5735 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
5737 if (rt2x00_rt(rt2x00dev, RT3290)) {
5738 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
5739 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
5740 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 1);
5741 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
5744 reg = rt2800_register_read(rt2x00dev, CMB_CTRL);
5745 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
5746 rt2x00_set_field32(®, LDO0_EN, 1);
5747 rt2x00_set_field32(®, LDO_BGSEL, 3);
5748 rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
5751 reg = rt2800_register_read(rt2x00dev, OSC_CTRL);
5752 rt2x00_set_field32(®, OSC_ROSC_EN, 1);
5753 rt2x00_set_field32(®, OSC_CAL_REQ, 1);
5754 rt2x00_set_field32(®, OSC_REF_CYCLE, 0x27);
5755 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
5757 reg = rt2800_register_read(rt2x00dev, COEX_CFG0);
5758 rt2x00_set_field32(®, COEX_CFG_ANT, 0x5e);
5759 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
5761 reg = rt2800_register_read(rt2x00dev, COEX_CFG2);
5762 rt2x00_set_field32(®, BT_COEX_CFG1, 0x00);
5763 rt2x00_set_field32(®, BT_COEX_CFG0, 0x17);
5764 rt2x00_set_field32(®, WL_COEX_CFG1, 0x93);
5765 rt2x00_set_field32(®, WL_COEX_CFG0, 0x7f);
5766 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
5768 reg = rt2800_register_read(rt2x00dev, PLL_CTRL);
5769 rt2x00_set_field32(®, PLL_CONTROL, 1);
5770 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
5773 if (rt2x00_rt(rt2x00dev, RT3071) ||
5774 rt2x00_rt(rt2x00dev, RT3090) ||
5775 rt2x00_rt(rt2x00dev, RT3290) ||
5776 rt2x00_rt(rt2x00dev, RT3390)) {
5778 if (rt2x00_rt(rt2x00dev, RT3290))
5779 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
5782 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
5785 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5786 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5787 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
5788 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
5789 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
5790 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
5791 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5794 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5797 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5799 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
5800 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5802 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
5803 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5804 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
5806 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5807 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5809 } else if (rt2800_is_305x_soc(rt2x00dev)) {
5810 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5811 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5812 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
5813 } else if (rt2x00_rt(rt2x00dev, RT3352)) {
5814 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
5815 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5816 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5817 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
5818 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5819 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5820 } else if (rt2x00_rt(rt2x00dev, RT3593)) {
5821 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
5822 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5823 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) {
5824 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
5825 if (rt2x00_get_field16(eeprom,
5826 EEPROM_NIC_CONF1_DAC_TEST))
5827 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5830 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5833 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5836 } else if (rt2x00_rt(rt2x00dev, RT3883)) {
5837 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
5838 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5839 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00040000);
5840 rt2800_register_write(rt2x00dev, TX_TXBF_CFG_0, 0x8000fc21);
5841 rt2800_register_write(rt2x00dev, TX_TXBF_CFG_3, 0x00009c40);
5842 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
5843 rt2x00_rt(rt2x00dev, RT5392) ||
5844 rt2x00_rt(rt2x00dev, RT6352)) {
5845 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5846 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5847 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5848 } else if (rt2x00_rt(rt2x00dev, RT5592)) {
5849 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5850 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5851 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5852 } else if (rt2x00_rt(rt2x00dev, RT5350)) {
5853 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5854 } else if (rt2x00_rt(rt2x00dev, RT6352)) {
5855 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401);
5856 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0000);
5857 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5858 rt2800_register_write(rt2x00dev, MIMO_PS_CFG, 0x00000002);
5859 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x00150F0F);
5860 rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x00000000);
5861 rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0);
5862 rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0);
5863 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C);
5864 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C);
5865 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
5867 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT,
5869 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1);
5870 rt2x00_set_field32(®, TX_ALC_CFG_1_ROS_BUSY_EN, 0);
5871 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
5873 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
5874 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5877 reg = rt2800_register_read(rt2x00dev, TX_LINK_CFG);
5878 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
5879 rt2x00_set_field32(®, TX_LINK_CFG_MFB_ENABLE, 0);
5880 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
5881 rt2x00_set_field32(®, TX_LINK_CFG_TX_MRQ_EN, 0);
5882 rt2x00_set_field32(®, TX_LINK_CFG_TX_RDG_EN, 0);
5883 rt2x00_set_field32(®, TX_LINK_CFG_TX_CF_ACK_EN, 1);
5884 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB, 0);
5885 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFS, 0);
5886 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
5888 reg = rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG);
5889 rt2x00_set_field32(®, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
5890 rt2x00_set_field32(®, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
5891 rt2x00_set_field32(®, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
5892 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
5894 reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG);
5895 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
5896 if (rt2x00_is_usb(rt2x00dev)) {
5897 drv_data->max_psdu = 3;
5898 } else if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
5899 rt2x00_rt(rt2x00dev, RT2883) ||
5900 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E)) {
5901 drv_data->max_psdu = 2;
5903 drv_data->max_psdu = 1;
5905 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, drv_data->max_psdu);
5906 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_PSDU, 10);
5907 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_MPDU, 10);
5908 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
5910 reg = rt2800_register_read(rt2x00dev, LED_CFG);
5911 rt2x00_set_field32(®, LED_CFG_ON_PERIOD, 70);
5912 rt2x00_set_field32(®, LED_CFG_OFF_PERIOD, 30);
5913 rt2x00_set_field32(®, LED_CFG_SLOW_BLINK_PERIOD, 3);
5914 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 3);
5915 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 3);
5916 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 3);
5917 rt2x00_set_field32(®, LED_CFG_LED_POLAR, 1);
5918 rt2800_register_write(rt2x00dev, LED_CFG, reg);
5920 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
5922 reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG);
5923 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 2);
5924 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 2);
5925 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_THRE, 2000);
5926 rt2x00_set_field32(®, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
5927 rt2x00_set_field32(®, TX_RTY_CFG_AGG_RTY_MODE, 0);
5928 rt2x00_set_field32(®, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
5929 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
5931 reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG);
5932 rt2x00_set_field32(®, AUTO_RSP_CFG_AUTORESPONDER, 1);
5933 rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
5934 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MMODE, 1);
5935 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MREF, 0);
5936 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 0);
5937 rt2x00_set_field32(®, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
5938 rt2x00_set_field32(®, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
5939 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
5941 reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG);
5942 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_RATE, 3);
5943 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_CTRL, 0);
5944 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
5945 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
5946 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5947 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5948 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5949 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5950 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
5951 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, 1);
5952 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
5954 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
5955 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_RATE, 3);
5956 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 0);
5957 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
5958 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
5959 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5960 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5961 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5962 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5963 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
5964 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, 1);
5965 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
5967 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
5968 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
5969 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, 1);
5970 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
5971 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 0);
5972 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5973 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5974 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5975 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5976 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
5977 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, 0);
5978 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
5980 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
5981 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
5982 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, 1);
5983 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
5984 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 0);
5985 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5986 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5987 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
5988 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5989 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
5990 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, 0);
5991 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
5993 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
5994 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
5995 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, 1);
5996 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
5997 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 0);
5998 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5999 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
6000 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
6001 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
6002 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
6003 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, 0);
6004 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
6006 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
6007 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
6008 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, 1);
6009 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
6010 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 0);
6011 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
6012 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
6013 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
6014 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
6015 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
6016 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, 0);
6017 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
6019 if (rt2x00_is_usb(rt2x00dev)) {
6020 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
6022 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
6023 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
6024 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
6025 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
6026 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
6027 rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
6028 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
6029 rt2x00_set_field32(®, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
6030 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
6031 rt2x00_set_field32(®, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
6032 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
6036 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
6037 * although it is reserved.
6039 reg = rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG);
6040 rt2x00_set_field32(®, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
6041 rt2x00_set_field32(®, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
6042 rt2x00_set_field32(®, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
6043 rt2x00_set_field32(®, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
6044 rt2x00_set_field32(®, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
6045 rt2x00_set_field32(®, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
6046 rt2x00_set_field32(®, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
6047 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
6048 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
6049 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CWMIN, 0);
6050 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
6052 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
6053 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
6055 if (rt2x00_rt(rt2x00dev, RT3883)) {
6056 rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_0, 0x12111008);
6057 rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_1, 0x16151413);
6060 reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG);
6061 rt2x00_set_field32(®, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 7);
6062 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES,
6063 IEEE80211_MAX_RTS_THRESHOLD);
6064 rt2x00_set_field32(®, TX_RTS_CFG_RTS_FBK_EN, 1);
6065 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
6067 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
6070 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
6071 * time should be set to 16. However, the original Ralink driver uses
6072 * 16 for both and indeed using a value of 10 for CCK SIFS results in
6073 * connection problems with 11g + CTS protection. Hence, use the same
6074 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
6076 reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG);
6077 rt2x00_set_field32(®, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
6078 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
6079 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
6080 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, 314);
6081 rt2x00_set_field32(®, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
6082 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
6084 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
6087 * ASIC will keep garbage value after boot, clear encryption keys.
6089 for (i = 0; i < 4; i++)
6090 rt2800_register_write(rt2x00dev, SHARED_KEY_MODE_ENTRY(i), 0);
6092 for (i = 0; i < 256; i++) {
6093 rt2800_config_wcid(rt2x00dev, NULL, i);
6094 rt2800_delete_wcid_attr(rt2x00dev, i);
6098 * Clear encryption initialization vectors on start, but keep them
6099 * for watchdog reset. Otherwise we will have wrong IVs and not be
6100 * able to keep connections after reset.
6102 if (!test_bit(DEVICE_STATE_RESET, &rt2x00dev->flags))
6103 for (i = 0; i < 256; i++)
6104 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
6109 for (i = 0; i < 8; i++)
6110 rt2800_clear_beacon_register(rt2x00dev, i);
6112 if (rt2x00_is_usb(rt2x00dev)) {
6113 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
6114 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 30);
6115 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
6116 } else if (rt2x00_is_pcie(rt2x00dev)) {
6117 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
6118 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 125);
6119 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
6122 reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG0);
6123 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS0FBK, 0);
6124 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS1FBK, 0);
6125 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS2FBK, 1);
6126 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS3FBK, 2);
6127 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS4FBK, 3);
6128 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS5FBK, 4);
6129 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS6FBK, 5);
6130 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS7FBK, 6);
6131 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
6133 reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG1);
6134 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS8FBK, 8);
6135 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS9FBK, 8);
6136 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS10FBK, 9);
6137 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS11FBK, 10);
6138 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS12FBK, 11);
6139 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS13FBK, 12);
6140 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS14FBK, 13);
6141 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS15FBK, 14);
6142 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
6144 reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG0);
6145 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS0FBK, 8);
6146 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS1FBK, 8);
6147 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS2FBK, 9);
6148 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS3FBK, 10);
6149 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS4FBK, 11);
6150 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS5FBK, 12);
6151 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS6FBK, 13);
6152 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS7FBK, 14);
6153 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
6155 reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG1);
6156 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS0FBK, 0);
6157 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS1FBK, 0);
6158 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS2FBK, 1);
6159 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS3FBK, 2);
6160 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
6163 * Do not force the BA window size, we use the TXWI to set it
6165 reg = rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE);
6166 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
6167 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
6168 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
6171 * We must clear the error counters.
6172 * These registers are cleared on read,
6173 * so we may pass a useless variable to store the value.
6175 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0);
6176 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT1);
6177 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT2);
6178 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT0);
6179 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT1);
6180 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT2);
6183 * Setup leadtime for pre tbtt interrupt to 6ms
6185 reg = rt2800_register_read(rt2x00dev, INT_TIMER_CFG);
6186 rt2x00_set_field32(®, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
6187 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
6190 * Set up channel statistics timer
6192 reg = rt2800_register_read(rt2x00dev, CH_TIME_CFG);
6193 rt2x00_set_field32(®, CH_TIME_CFG_EIFS_BUSY, 1);
6194 rt2x00_set_field32(®, CH_TIME_CFG_NAV_BUSY, 1);
6195 rt2x00_set_field32(®, CH_TIME_CFG_RX_BUSY, 1);
6196 rt2x00_set_field32(®, CH_TIME_CFG_TX_BUSY, 1);
6197 rt2x00_set_field32(®, CH_TIME_CFG_TMR_EN, 1);
6198 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
6203 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
6208 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
6209 reg = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
6210 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
6213 udelay(REGISTER_BUSY_DELAY);
6216 rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n");
6220 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
6226 * BBP was enabled after firmware was loaded,
6227 * but we need to reactivate it now.
6229 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
6230 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
6233 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
6234 value = rt2800_bbp_read(rt2x00dev, 0);
6235 if ((value != 0xff) && (value != 0x00))
6237 udelay(REGISTER_BUSY_DELAY);
6240 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
6244 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
6248 value = rt2800_bbp_read(rt2x00dev, 4);
6249 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
6250 rt2800_bbp_write(rt2x00dev, 4, value);
6253 static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
6255 rt2800_bbp_write(rt2x00dev, 142, 1);
6256 rt2800_bbp_write(rt2x00dev, 143, 57);
6259 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
6261 static const u8 glrt_table[] = {
6262 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
6263 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
6264 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
6265 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
6266 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
6267 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
6268 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
6269 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
6270 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */
6274 for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
6275 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
6276 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
6280 static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev)
6282 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
6283 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6284 rt2800_bbp_write(rt2x00dev, 68, 0x0B);
6285 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6286 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6287 rt2800_bbp_write(rt2x00dev, 73, 0x10);
6288 rt2800_bbp_write(rt2x00dev, 81, 0x37);
6289 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6290 rt2800_bbp_write(rt2x00dev, 83, 0x6A);
6291 rt2800_bbp_write(rt2x00dev, 84, 0x99);
6292 rt2800_bbp_write(rt2x00dev, 86, 0x00);
6293 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6294 rt2800_bbp_write(rt2x00dev, 92, 0x00);
6295 rt2800_bbp_write(rt2x00dev, 103, 0x00);
6296 rt2800_bbp_write(rt2x00dev, 105, 0x05);
6297 rt2800_bbp_write(rt2x00dev, 106, 0x35);
6300 static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev)
6305 value = rt2800_bbp_read(rt2x00dev, 138);
6306 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
6307 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
6309 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
6311 rt2800_bbp_write(rt2x00dev, 138, value);
6314 static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev)
6316 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6318 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6319 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6321 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6322 rt2800_bbp_write(rt2x00dev, 73, 0x10);
6324 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6326 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
6327 rt2800_bbp_write(rt2x00dev, 80, 0x08);
6329 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6331 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6333 rt2800_bbp_write(rt2x00dev, 84, 0x99);
6335 rt2800_bbp_write(rt2x00dev, 86, 0x00);
6337 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6339 rt2800_bbp_write(rt2x00dev, 92, 0x00);
6341 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6343 rt2800_bbp_write(rt2x00dev, 105, 0x01);
6345 rt2800_bbp_write(rt2x00dev, 106, 0x35);
6348 static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev)
6350 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6351 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6353 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
6354 rt2800_bbp_write(rt2x00dev, 69, 0x16);
6355 rt2800_bbp_write(rt2x00dev, 73, 0x12);
6357 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6358 rt2800_bbp_write(rt2x00dev, 73, 0x10);
6361 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6363 rt2800_bbp_write(rt2x00dev, 81, 0x37);
6365 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6367 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6369 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
6370 rt2800_bbp_write(rt2x00dev, 84, 0x19);
6372 rt2800_bbp_write(rt2x00dev, 84, 0x99);
6374 rt2800_bbp_write(rt2x00dev, 86, 0x00);
6376 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6378 rt2800_bbp_write(rt2x00dev, 92, 0x00);
6380 rt2800_bbp_write(rt2x00dev, 103, 0x00);
6382 rt2800_bbp_write(rt2x00dev, 105, 0x05);
6384 rt2800_bbp_write(rt2x00dev, 106, 0x35);
6387 static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev)
6389 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6390 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6392 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6393 rt2800_bbp_write(rt2x00dev, 73, 0x10);
6395 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6397 rt2800_bbp_write(rt2x00dev, 79, 0x13);
6398 rt2800_bbp_write(rt2x00dev, 80, 0x05);
6399 rt2800_bbp_write(rt2x00dev, 81, 0x33);
6401 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6403 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6405 rt2800_bbp_write(rt2x00dev, 84, 0x99);
6407 rt2800_bbp_write(rt2x00dev, 86, 0x00);
6409 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6411 rt2800_bbp_write(rt2x00dev, 92, 0x00);
6413 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
6414 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
6415 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E))
6416 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6418 rt2800_bbp_write(rt2x00dev, 103, 0x00);
6420 rt2800_bbp_write(rt2x00dev, 105, 0x05);
6422 rt2800_bbp_write(rt2x00dev, 106, 0x35);
6424 if (rt2x00_rt(rt2x00dev, RT3071) ||
6425 rt2x00_rt(rt2x00dev, RT3090))
6426 rt2800_disable_unused_dac_adc(rt2x00dev);
6429 static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev)
6433 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6435 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6437 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6438 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6440 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6442 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6443 rt2800_bbp_write(rt2x00dev, 73, 0x13);
6444 rt2800_bbp_write(rt2x00dev, 75, 0x46);
6445 rt2800_bbp_write(rt2x00dev, 76, 0x28);
6447 rt2800_bbp_write(rt2x00dev, 77, 0x58);
6449 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6451 rt2800_bbp_write(rt2x00dev, 74, 0x0b);
6452 rt2800_bbp_write(rt2x00dev, 79, 0x18);
6453 rt2800_bbp_write(rt2x00dev, 80, 0x09);
6454 rt2800_bbp_write(rt2x00dev, 81, 0x33);
6456 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6458 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
6460 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
6462 rt2800_bbp_write(rt2x00dev, 86, 0x38);
6464 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6466 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6468 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6470 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6472 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
6474 rt2800_bbp_write(rt2x00dev, 106, 0x03);
6476 rt2800_bbp_write(rt2x00dev, 128, 0x12);
6478 rt2800_bbp_write(rt2x00dev, 67, 0x24);
6479 rt2800_bbp_write(rt2x00dev, 143, 0x04);
6480 rt2800_bbp_write(rt2x00dev, 142, 0x99);
6481 rt2800_bbp_write(rt2x00dev, 150, 0x30);
6482 rt2800_bbp_write(rt2x00dev, 151, 0x2e);
6483 rt2800_bbp_write(rt2x00dev, 152, 0x20);
6484 rt2800_bbp_write(rt2x00dev, 153, 0x34);
6485 rt2800_bbp_write(rt2x00dev, 154, 0x40);
6486 rt2800_bbp_write(rt2x00dev, 155, 0x3b);
6487 rt2800_bbp_write(rt2x00dev, 253, 0x04);
6489 value = rt2800_bbp_read(rt2x00dev, 47);
6490 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
6491 rt2800_bbp_write(rt2x00dev, 47, value);
6493 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
6494 value = rt2800_bbp_read(rt2x00dev, 3);
6495 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
6496 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
6497 rt2800_bbp_write(rt2x00dev, 3, value);
6500 static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev)
6502 rt2800_bbp_write(rt2x00dev, 3, 0x00);
6503 rt2800_bbp_write(rt2x00dev, 4, 0x50);
6505 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6507 rt2800_bbp_write(rt2x00dev, 47, 0x48);
6509 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6510 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6512 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6514 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6515 rt2800_bbp_write(rt2x00dev, 73, 0x13);
6516 rt2800_bbp_write(rt2x00dev, 75, 0x46);
6517 rt2800_bbp_write(rt2x00dev, 76, 0x28);
6519 rt2800_bbp_write(rt2x00dev, 77, 0x59);
6521 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6523 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
6524 rt2800_bbp_write(rt2x00dev, 80, 0x08);
6525 rt2800_bbp_write(rt2x00dev, 81, 0x37);
6527 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6529 if (rt2x00_rt(rt2x00dev, RT5350)) {
6530 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
6531 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
6533 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6534 rt2800_bbp_write(rt2x00dev, 84, 0x99);
6537 rt2800_bbp_write(rt2x00dev, 86, 0x38);
6539 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6541 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6543 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6545 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6547 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6549 if (rt2x00_rt(rt2x00dev, RT5350)) {
6550 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
6551 rt2800_bbp_write(rt2x00dev, 106, 0x03);
6553 rt2800_bbp_write(rt2x00dev, 105, 0x34);
6554 rt2800_bbp_write(rt2x00dev, 106, 0x05);
6557 rt2800_bbp_write(rt2x00dev, 120, 0x50);
6559 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
6561 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
6562 /* Set ITxBF timeout to 0x9c40=1000msec */
6563 rt2800_bbp_write(rt2x00dev, 179, 0x02);
6564 rt2800_bbp_write(rt2x00dev, 180, 0x00);
6565 rt2800_bbp_write(rt2x00dev, 182, 0x40);
6566 rt2800_bbp_write(rt2x00dev, 180, 0x01);
6567 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
6568 rt2800_bbp_write(rt2x00dev, 179, 0x00);
6569 /* Reprogram the inband interface to put right values in RXWI */
6570 rt2800_bbp_write(rt2x00dev, 142, 0x04);
6571 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
6572 rt2800_bbp_write(rt2x00dev, 142, 0x06);
6573 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
6574 rt2800_bbp_write(rt2x00dev, 142, 0x07);
6575 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
6576 rt2800_bbp_write(rt2x00dev, 142, 0x08);
6577 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
6579 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
6581 if (rt2x00_rt(rt2x00dev, RT5350)) {
6582 /* Antenna Software OFDM */
6583 rt2800_bbp_write(rt2x00dev, 150, 0x40);
6584 /* Antenna Software CCK */
6585 rt2800_bbp_write(rt2x00dev, 151, 0x30);
6586 rt2800_bbp_write(rt2x00dev, 152, 0xa3);
6587 /* Clear previously selected antenna */
6588 rt2800_bbp_write(rt2x00dev, 154, 0);
6592 static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev)
6594 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6595 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6597 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6598 rt2800_bbp_write(rt2x00dev, 73, 0x10);
6600 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6602 rt2800_bbp_write(rt2x00dev, 79, 0x13);
6603 rt2800_bbp_write(rt2x00dev, 80, 0x05);
6604 rt2800_bbp_write(rt2x00dev, 81, 0x33);
6606 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6608 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6610 rt2800_bbp_write(rt2x00dev, 84, 0x99);
6612 rt2800_bbp_write(rt2x00dev, 86, 0x00);
6614 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6616 rt2800_bbp_write(rt2x00dev, 92, 0x00);
6618 if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
6619 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6621 rt2800_bbp_write(rt2x00dev, 103, 0x00);
6623 rt2800_bbp_write(rt2x00dev, 105, 0x05);
6625 rt2800_bbp_write(rt2x00dev, 106, 0x35);
6627 rt2800_disable_unused_dac_adc(rt2x00dev);
6630 static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev)
6632 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6634 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6635 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6637 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6638 rt2800_bbp_write(rt2x00dev, 73, 0x10);
6640 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6642 rt2800_bbp_write(rt2x00dev, 79, 0x13);
6643 rt2800_bbp_write(rt2x00dev, 80, 0x05);
6644 rt2800_bbp_write(rt2x00dev, 81, 0x33);
6646 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6648 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6650 rt2800_bbp_write(rt2x00dev, 84, 0x99);
6652 rt2800_bbp_write(rt2x00dev, 86, 0x00);
6654 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6656 rt2800_bbp_write(rt2x00dev, 92, 0x00);
6658 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6660 rt2800_bbp_write(rt2x00dev, 105, 0x05);
6662 rt2800_bbp_write(rt2x00dev, 106, 0x35);
6664 rt2800_disable_unused_dac_adc(rt2x00dev);
6667 static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev)
6669 rt2800_init_bbp_early(rt2x00dev);
6671 rt2800_bbp_write(rt2x00dev, 79, 0x13);
6672 rt2800_bbp_write(rt2x00dev, 80, 0x05);
6673 rt2800_bbp_write(rt2x00dev, 81, 0x33);
6674 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
6676 rt2800_bbp_write(rt2x00dev, 84, 0x19);
6678 /* Enable DC filter */
6679 if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E))
6680 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6683 static void rt2800_init_bbp_3883(struct rt2x00_dev *rt2x00dev)
6685 rt2800_init_bbp_early(rt2x00dev);
6687 rt2800_bbp_write(rt2x00dev, 4, 0x50);
6688 rt2800_bbp_write(rt2x00dev, 47, 0x48);
6690 rt2800_bbp_write(rt2x00dev, 86, 0x46);
6691 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6693 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6695 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6696 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6697 rt2800_bbp_write(rt2x00dev, 105, 0x34);
6698 rt2800_bbp_write(rt2x00dev, 106, 0x12);
6699 rt2800_bbp_write(rt2x00dev, 120, 0x50);
6700 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
6701 rt2800_bbp_write(rt2x00dev, 163, 0x9d);
6703 /* Set ITxBF timeout to 0x9C40=1000msec */
6704 rt2800_bbp_write(rt2x00dev, 179, 0x02);
6705 rt2800_bbp_write(rt2x00dev, 180, 0x00);
6706 rt2800_bbp_write(rt2x00dev, 182, 0x40);
6707 rt2800_bbp_write(rt2x00dev, 180, 0x01);
6708 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
6710 rt2800_bbp_write(rt2x00dev, 179, 0x00);
6712 /* Reprogram the inband interface to put right values in RXWI */
6713 rt2800_bbp_write(rt2x00dev, 142, 0x04);
6714 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
6715 rt2800_bbp_write(rt2x00dev, 142, 0x06);
6716 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
6717 rt2800_bbp_write(rt2x00dev, 142, 0x07);
6718 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
6719 rt2800_bbp_write(rt2x00dev, 142, 0x08);
6720 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
6721 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
6724 static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev)
6730 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6732 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6734 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6735 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6737 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6739 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6740 rt2800_bbp_write(rt2x00dev, 73, 0x13);
6741 rt2800_bbp_write(rt2x00dev, 75, 0x46);
6742 rt2800_bbp_write(rt2x00dev, 76, 0x28);
6744 rt2800_bbp_write(rt2x00dev, 77, 0x59);
6746 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6748 rt2800_bbp_write(rt2x00dev, 79, 0x13);
6749 rt2800_bbp_write(rt2x00dev, 80, 0x05);
6750 rt2800_bbp_write(rt2x00dev, 81, 0x33);
6752 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6754 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
6756 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
6758 rt2800_bbp_write(rt2x00dev, 86, 0x38);
6760 if (rt2x00_rt(rt2x00dev, RT5392))
6761 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6763 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6765 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6767 if (rt2x00_rt(rt2x00dev, RT5392)) {
6768 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
6769 rt2800_bbp_write(rt2x00dev, 98, 0x12);
6772 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6774 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6776 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
6778 if (rt2x00_rt(rt2x00dev, RT5390))
6779 rt2800_bbp_write(rt2x00dev, 106, 0x03);
6780 else if (rt2x00_rt(rt2x00dev, RT5392))
6781 rt2800_bbp_write(rt2x00dev, 106, 0x12);
6785 rt2800_bbp_write(rt2x00dev, 128, 0x12);
6787 if (rt2x00_rt(rt2x00dev, RT5392)) {
6788 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
6789 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
6792 rt2800_disable_unused_dac_adc(rt2x00dev);
6794 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
6795 div_mode = rt2x00_get_field16(eeprom,
6796 EEPROM_NIC_CONF1_ANT_DIVERSITY);
6797 ant = (div_mode == 3) ? 1 : 0;
6799 /* check if this is a Bluetooth combo card */
6800 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
6803 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
6804 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0);
6805 rt2x00_set_field32(®, GPIO_CTRL_DIR6, 0);
6806 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 0);
6807 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 0);
6809 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 1);
6811 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 1);
6812 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
6815 /* These chips have hardware RX antenna diversity */
6816 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) ||
6817 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) {
6818 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
6819 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
6820 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
6823 value = rt2800_bbp_read(rt2x00dev, 152);
6825 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
6827 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
6828 rt2800_bbp_write(rt2x00dev, 152, value);
6830 rt2800_init_freq_calibration(rt2x00dev);
6833 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
6839 rt2800_init_bbp_early(rt2x00dev);
6841 value = rt2800_bbp_read(rt2x00dev, 105);
6842 rt2x00_set_field8(&value, BBP105_MLD,
6843 rt2x00dev->default_ant.rx_chain_num == 2);
6844 rt2800_bbp_write(rt2x00dev, 105, value);
6846 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6848 rt2800_bbp_write(rt2x00dev, 20, 0x06);
6849 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6850 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
6851 rt2800_bbp_write(rt2x00dev, 68, 0xDD);
6852 rt2800_bbp_write(rt2x00dev, 69, 0x1A);
6853 rt2800_bbp_write(rt2x00dev, 70, 0x05);
6854 rt2800_bbp_write(rt2x00dev, 73, 0x13);
6855 rt2800_bbp_write(rt2x00dev, 74, 0x0F);
6856 rt2800_bbp_write(rt2x00dev, 75, 0x4F);
6857 rt2800_bbp_write(rt2x00dev, 76, 0x28);
6858 rt2800_bbp_write(rt2x00dev, 77, 0x59);
6859 rt2800_bbp_write(rt2x00dev, 84, 0x9A);
6860 rt2800_bbp_write(rt2x00dev, 86, 0x38);
6861 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6862 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6863 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6864 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
6865 rt2800_bbp_write(rt2x00dev, 98, 0x12);
6866 rt2800_bbp_write(rt2x00dev, 103, 0xC0);
6867 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6868 /* FIXME BBP105 owerwrite */
6869 rt2800_bbp_write(rt2x00dev, 105, 0x3C);
6870 rt2800_bbp_write(rt2x00dev, 106, 0x35);
6871 rt2800_bbp_write(rt2x00dev, 128, 0x12);
6872 rt2800_bbp_write(rt2x00dev, 134, 0xD0);
6873 rt2800_bbp_write(rt2x00dev, 135, 0xF6);
6874 rt2800_bbp_write(rt2x00dev, 137, 0x0F);
6876 /* Initialize GLRT (Generalized Likehood Radio Test) */
6877 rt2800_init_bbp_5592_glrt(rt2x00dev);
6879 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6881 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
6882 div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
6883 ant = (div_mode == 3) ? 1 : 0;
6884 value = rt2800_bbp_read(rt2x00dev, 152);
6887 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
6889 /* Auxiliary antenna */
6890 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
6892 rt2800_bbp_write(rt2x00dev, 152, value);
6894 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
6895 value = rt2800_bbp_read(rt2x00dev, 254);
6896 rt2x00_set_field8(&value, BBP254_BIT7, 1);
6897 rt2800_bbp_write(rt2x00dev, 254, value);
6900 rt2800_init_freq_calibration(rt2x00dev);
6902 rt2800_bbp_write(rt2x00dev, 84, 0x19);
6903 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
6904 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6907 static void rt2800_bbp_glrt_write(struct rt2x00_dev *rt2x00dev,
6908 const u8 reg, const u8 value)
6910 rt2800_bbp_write(rt2x00dev, 195, reg);
6911 rt2800_bbp_write(rt2x00dev, 196, value);
6914 static void rt2800_bbp_dcoc_write(struct rt2x00_dev *rt2x00dev,
6915 const u8 reg, const u8 value)
6917 rt2800_bbp_write(rt2x00dev, 158, reg);
6918 rt2800_bbp_write(rt2x00dev, 159, value);
6921 static u8 rt2800_bbp_dcoc_read(struct rt2x00_dev *rt2x00dev, const u8 reg)
6923 rt2800_bbp_write(rt2x00dev, 158, reg);
6924 return rt2800_bbp_read(rt2x00dev, 159);
6927 static void rt2800_init_bbp_6352(struct rt2x00_dev *rt2x00dev)
6931 /* Apply Maximum Likelihood Detection (MLD) for 2 stream case */
6932 bbp = rt2800_bbp_read(rt2x00dev, 105);
6933 rt2x00_set_field8(&bbp, BBP105_MLD,
6934 rt2x00dev->default_ant.rx_chain_num == 2);
6935 rt2800_bbp_write(rt2x00dev, 105, bbp);
6937 /* Avoid data loss and CRC errors */
6938 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6940 /* Fix I/Q swap issue */
6941 bbp = rt2800_bbp_read(rt2x00dev, 1);
6943 rt2800_bbp_write(rt2x00dev, 1, bbp);
6945 /* BBP for G band */
6946 rt2800_bbp_write(rt2x00dev, 3, 0x08);
6947 rt2800_bbp_write(rt2x00dev, 4, 0x00); /* rt2800_bbp4_mac_if_ctrl? */
6948 rt2800_bbp_write(rt2x00dev, 6, 0x08);
6949 rt2800_bbp_write(rt2x00dev, 14, 0x09);
6950 rt2800_bbp_write(rt2x00dev, 15, 0xFF);
6951 rt2800_bbp_write(rt2x00dev, 16, 0x01);
6952 rt2800_bbp_write(rt2x00dev, 20, 0x06);
6953 rt2800_bbp_write(rt2x00dev, 21, 0x00);
6954 rt2800_bbp_write(rt2x00dev, 22, 0x00);
6955 rt2800_bbp_write(rt2x00dev, 27, 0x00);
6956 rt2800_bbp_write(rt2x00dev, 28, 0x00);
6957 rt2800_bbp_write(rt2x00dev, 30, 0x00);
6958 rt2800_bbp_write(rt2x00dev, 31, 0x48);
6959 rt2800_bbp_write(rt2x00dev, 47, 0x40);
6960 rt2800_bbp_write(rt2x00dev, 62, 0x00);
6961 rt2800_bbp_write(rt2x00dev, 63, 0x00);
6962 rt2800_bbp_write(rt2x00dev, 64, 0x00);
6963 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
6964 rt2800_bbp_write(rt2x00dev, 66, 0x1C);
6965 rt2800_bbp_write(rt2x00dev, 67, 0x20);
6966 rt2800_bbp_write(rt2x00dev, 68, 0xDD);
6967 rt2800_bbp_write(rt2x00dev, 69, 0x10);
6968 rt2800_bbp_write(rt2x00dev, 70, 0x05);
6969 rt2800_bbp_write(rt2x00dev, 73, 0x18);
6970 rt2800_bbp_write(rt2x00dev, 74, 0x0F);
6971 rt2800_bbp_write(rt2x00dev, 75, 0x60);
6972 rt2800_bbp_write(rt2x00dev, 76, 0x44);
6973 rt2800_bbp_write(rt2x00dev, 77, 0x59);
6974 rt2800_bbp_write(rt2x00dev, 78, 0x1E);
6975 rt2800_bbp_write(rt2x00dev, 79, 0x1C);
6976 rt2800_bbp_write(rt2x00dev, 80, 0x0C);
6977 rt2800_bbp_write(rt2x00dev, 81, 0x3A);
6978 rt2800_bbp_write(rt2x00dev, 82, 0xB6);
6979 rt2800_bbp_write(rt2x00dev, 83, 0x9A);
6980 rt2800_bbp_write(rt2x00dev, 84, 0x9A);
6981 rt2800_bbp_write(rt2x00dev, 86, 0x38);
6982 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6983 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6984 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6985 rt2800_bbp_write(rt2x00dev, 95, 0x9A);
6986 rt2800_bbp_write(rt2x00dev, 96, 0x00);
6987 rt2800_bbp_write(rt2x00dev, 103, 0xC0);
6988 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6989 /* FIXME BBP105 owerwrite */
6990 rt2800_bbp_write(rt2x00dev, 105, 0x3C);
6991 rt2800_bbp_write(rt2x00dev, 106, 0x12);
6992 rt2800_bbp_write(rt2x00dev, 109, 0x00);
6993 rt2800_bbp_write(rt2x00dev, 134, 0x10);
6994 rt2800_bbp_write(rt2x00dev, 135, 0xA6);
6995 rt2800_bbp_write(rt2x00dev, 137, 0x04);
6996 rt2800_bbp_write(rt2x00dev, 142, 0x30);
6997 rt2800_bbp_write(rt2x00dev, 143, 0xF7);
6998 rt2800_bbp_write(rt2x00dev, 160, 0xEC);
6999 rt2800_bbp_write(rt2x00dev, 161, 0xC4);
7000 rt2800_bbp_write(rt2x00dev, 162, 0x77);
7001 rt2800_bbp_write(rt2x00dev, 163, 0xF9);
7002 rt2800_bbp_write(rt2x00dev, 164, 0x00);
7003 rt2800_bbp_write(rt2x00dev, 165, 0x00);
7004 rt2800_bbp_write(rt2x00dev, 186, 0x00);
7005 rt2800_bbp_write(rt2x00dev, 187, 0x00);
7006 rt2800_bbp_write(rt2x00dev, 188, 0x00);
7007 rt2800_bbp_write(rt2x00dev, 186, 0x00);
7008 rt2800_bbp_write(rt2x00dev, 187, 0x01);
7009 rt2800_bbp_write(rt2x00dev, 188, 0x00);
7010 rt2800_bbp_write(rt2x00dev, 189, 0x00);
7012 rt2800_bbp_write(rt2x00dev, 91, 0x06);
7013 rt2800_bbp_write(rt2x00dev, 92, 0x04);
7014 rt2800_bbp_write(rt2x00dev, 93, 0x54);
7015 rt2800_bbp_write(rt2x00dev, 99, 0x50);
7016 rt2800_bbp_write(rt2x00dev, 148, 0x84);
7017 rt2800_bbp_write(rt2x00dev, 167, 0x80);
7018 rt2800_bbp_write(rt2x00dev, 178, 0xFF);
7019 rt2800_bbp_write(rt2x00dev, 106, 0x13);
7021 /* BBP for G band GLRT function (BBP_128 ~ BBP_221) */
7022 rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00);
7023 rt2800_bbp_glrt_write(rt2x00dev, 1, 0x14);
7024 rt2800_bbp_glrt_write(rt2x00dev, 2, 0x20);
7025 rt2800_bbp_glrt_write(rt2x00dev, 3, 0x0A);
7026 rt2800_bbp_glrt_write(rt2x00dev, 10, 0x16);
7027 rt2800_bbp_glrt_write(rt2x00dev, 11, 0x06);
7028 rt2800_bbp_glrt_write(rt2x00dev, 12, 0x02);
7029 rt2800_bbp_glrt_write(rt2x00dev, 13, 0x07);
7030 rt2800_bbp_glrt_write(rt2x00dev, 14, 0x05);
7031 rt2800_bbp_glrt_write(rt2x00dev, 15, 0x09);
7032 rt2800_bbp_glrt_write(rt2x00dev, 16, 0x20);
7033 rt2800_bbp_glrt_write(rt2x00dev, 17, 0x08);
7034 rt2800_bbp_glrt_write(rt2x00dev, 18, 0x4A);
7035 rt2800_bbp_glrt_write(rt2x00dev, 19, 0x00);
7036 rt2800_bbp_glrt_write(rt2x00dev, 20, 0x00);
7037 rt2800_bbp_glrt_write(rt2x00dev, 128, 0xE0);
7038 rt2800_bbp_glrt_write(rt2x00dev, 129, 0x1F);
7039 rt2800_bbp_glrt_write(rt2x00dev, 130, 0x4F);
7040 rt2800_bbp_glrt_write(rt2x00dev, 131, 0x32);
7041 rt2800_bbp_glrt_write(rt2x00dev, 132, 0x08);
7042 rt2800_bbp_glrt_write(rt2x00dev, 133, 0x28);
7043 rt2800_bbp_glrt_write(rt2x00dev, 134, 0x19);
7044 rt2800_bbp_glrt_write(rt2x00dev, 135, 0x0A);
7045 rt2800_bbp_glrt_write(rt2x00dev, 138, 0x16);
7046 rt2800_bbp_glrt_write(rt2x00dev, 139, 0x10);
7047 rt2800_bbp_glrt_write(rt2x00dev, 140, 0x10);
7048 rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1A);
7049 rt2800_bbp_glrt_write(rt2x00dev, 142, 0x36);
7050 rt2800_bbp_glrt_write(rt2x00dev, 143, 0x2C);
7051 rt2800_bbp_glrt_write(rt2x00dev, 144, 0x26);
7052 rt2800_bbp_glrt_write(rt2x00dev, 145, 0x24);
7053 rt2800_bbp_glrt_write(rt2x00dev, 146, 0x42);
7054 rt2800_bbp_glrt_write(rt2x00dev, 147, 0x40);
7055 rt2800_bbp_glrt_write(rt2x00dev, 148, 0x30);
7056 rt2800_bbp_glrt_write(rt2x00dev, 149, 0x29);
7057 rt2800_bbp_glrt_write(rt2x00dev, 150, 0x4C);
7058 rt2800_bbp_glrt_write(rt2x00dev, 151, 0x46);
7059 rt2800_bbp_glrt_write(rt2x00dev, 152, 0x3D);
7060 rt2800_bbp_glrt_write(rt2x00dev, 153, 0x40);
7061 rt2800_bbp_glrt_write(rt2x00dev, 154, 0x3E);
7062 rt2800_bbp_glrt_write(rt2x00dev, 155, 0x38);
7063 rt2800_bbp_glrt_write(rt2x00dev, 156, 0x3D);
7064 rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2F);
7065 rt2800_bbp_glrt_write(rt2x00dev, 158, 0x3C);
7066 rt2800_bbp_glrt_write(rt2x00dev, 159, 0x34);
7067 rt2800_bbp_glrt_write(rt2x00dev, 160, 0x2C);
7068 rt2800_bbp_glrt_write(rt2x00dev, 161, 0x2F);
7069 rt2800_bbp_glrt_write(rt2x00dev, 162, 0x3C);
7070 rt2800_bbp_glrt_write(rt2x00dev, 163, 0x35);
7071 rt2800_bbp_glrt_write(rt2x00dev, 164, 0x2E);
7072 rt2800_bbp_glrt_write(rt2x00dev, 165, 0x2F);
7073 rt2800_bbp_glrt_write(rt2x00dev, 166, 0x49);
7074 rt2800_bbp_glrt_write(rt2x00dev, 167, 0x41);
7075 rt2800_bbp_glrt_write(rt2x00dev, 168, 0x36);
7076 rt2800_bbp_glrt_write(rt2x00dev, 169, 0x39);
7077 rt2800_bbp_glrt_write(rt2x00dev, 170, 0x30);
7078 rt2800_bbp_glrt_write(rt2x00dev, 171, 0x30);
7079 rt2800_bbp_glrt_write(rt2x00dev, 172, 0x0E);
7080 rt2800_bbp_glrt_write(rt2x00dev, 173, 0x0D);
7081 rt2800_bbp_glrt_write(rt2x00dev, 174, 0x28);
7082 rt2800_bbp_glrt_write(rt2x00dev, 175, 0x21);
7083 rt2800_bbp_glrt_write(rt2x00dev, 176, 0x1C);
7084 rt2800_bbp_glrt_write(rt2x00dev, 177, 0x16);
7085 rt2800_bbp_glrt_write(rt2x00dev, 178, 0x50);
7086 rt2800_bbp_glrt_write(rt2x00dev, 179, 0x4A);
7087 rt2800_bbp_glrt_write(rt2x00dev, 180, 0x43);
7088 rt2800_bbp_glrt_write(rt2x00dev, 181, 0x50);
7089 rt2800_bbp_glrt_write(rt2x00dev, 182, 0x10);
7090 rt2800_bbp_glrt_write(rt2x00dev, 183, 0x10);
7091 rt2800_bbp_glrt_write(rt2x00dev, 184, 0x10);
7092 rt2800_bbp_glrt_write(rt2x00dev, 185, 0x10);
7093 rt2800_bbp_glrt_write(rt2x00dev, 200, 0x7D);
7094 rt2800_bbp_glrt_write(rt2x00dev, 201, 0x14);
7095 rt2800_bbp_glrt_write(rt2x00dev, 202, 0x32);
7096 rt2800_bbp_glrt_write(rt2x00dev, 203, 0x2C);
7097 rt2800_bbp_glrt_write(rt2x00dev, 204, 0x36);
7098 rt2800_bbp_glrt_write(rt2x00dev, 205, 0x4C);
7099 rt2800_bbp_glrt_write(rt2x00dev, 206, 0x43);
7100 rt2800_bbp_glrt_write(rt2x00dev, 207, 0x2C);
7101 rt2800_bbp_glrt_write(rt2x00dev, 208, 0x2E);
7102 rt2800_bbp_glrt_write(rt2x00dev, 209, 0x36);
7103 rt2800_bbp_glrt_write(rt2x00dev, 210, 0x30);
7104 rt2800_bbp_glrt_write(rt2x00dev, 211, 0x6E);
7106 /* BBP for G band DCOC function */
7107 rt2800_bbp_dcoc_write(rt2x00dev, 140, 0x0C);
7108 rt2800_bbp_dcoc_write(rt2x00dev, 141, 0x00);
7109 rt2800_bbp_dcoc_write(rt2x00dev, 142, 0x10);
7110 rt2800_bbp_dcoc_write(rt2x00dev, 143, 0x10);
7111 rt2800_bbp_dcoc_write(rt2x00dev, 144, 0x10);
7112 rt2800_bbp_dcoc_write(rt2x00dev, 145, 0x10);
7113 rt2800_bbp_dcoc_write(rt2x00dev, 146, 0x08);
7114 rt2800_bbp_dcoc_write(rt2x00dev, 147, 0x40);
7115 rt2800_bbp_dcoc_write(rt2x00dev, 148, 0x04);
7116 rt2800_bbp_dcoc_write(rt2x00dev, 149, 0x04);
7117 rt2800_bbp_dcoc_write(rt2x00dev, 150, 0x08);
7118 rt2800_bbp_dcoc_write(rt2x00dev, 151, 0x08);
7119 rt2800_bbp_dcoc_write(rt2x00dev, 152, 0x03);
7120 rt2800_bbp_dcoc_write(rt2x00dev, 153, 0x03);
7121 rt2800_bbp_dcoc_write(rt2x00dev, 154, 0x03);
7122 rt2800_bbp_dcoc_write(rt2x00dev, 155, 0x02);
7123 rt2800_bbp_dcoc_write(rt2x00dev, 156, 0x40);
7124 rt2800_bbp_dcoc_write(rt2x00dev, 157, 0x40);
7125 rt2800_bbp_dcoc_write(rt2x00dev, 158, 0x64);
7126 rt2800_bbp_dcoc_write(rt2x00dev, 159, 0x64);
7128 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7131 static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
7138 if (rt2800_is_305x_soc(rt2x00dev))
7139 rt2800_init_bbp_305x_soc(rt2x00dev);
7141 switch (rt2x00dev->chip.rt) {
7145 rt2800_init_bbp_28xx(rt2x00dev);
7150 rt2800_init_bbp_30xx(rt2x00dev);
7153 rt2800_init_bbp_3290(rt2x00dev);
7157 rt2800_init_bbp_3352(rt2x00dev);
7160 rt2800_init_bbp_3390(rt2x00dev);
7163 rt2800_init_bbp_3572(rt2x00dev);
7166 rt2800_init_bbp_3593(rt2x00dev);
7169 rt2800_init_bbp_3883(rt2x00dev);
7173 rt2800_init_bbp_53xx(rt2x00dev);
7176 rt2800_init_bbp_5592(rt2x00dev);
7179 rt2800_init_bbp_6352(rt2x00dev);
7183 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
7184 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
7185 EEPROM_BBP_START, i);
7187 if (eeprom != 0xffff && eeprom != 0x0000) {
7188 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
7189 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
7190 rt2800_bbp_write(rt2x00dev, reg_id, value);
7195 static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev)
7199 reg = rt2800_register_read(rt2x00dev, OPT_14_CSR);
7200 rt2x00_set_field32(®, OPT_14_CSR_BIT0, 1);
7201 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
7204 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40,
7213 u8 rfcsr24 = (bw40) ? 0x27 : 0x07;
7215 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
7217 bbp = rt2800_bbp_read(rt2x00dev, 4);
7218 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
7219 rt2800_bbp_write(rt2x00dev, 4, bbp);
7221 rfcsr = rt2800_rfcsr_read(rt2x00dev, 31);
7222 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
7223 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
7225 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
7226 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
7227 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
7230 * Set power & frequency of passband test tone
7232 rt2800_bbp_write(rt2x00dev, 24, 0);
7234 for (i = 0; i < 100; i++) {
7235 rt2800_bbp_write(rt2x00dev, 25, 0x90);
7238 passband = rt2800_bbp_read(rt2x00dev, 55);
7244 * Set power & frequency of stopband test tone
7246 rt2800_bbp_write(rt2x00dev, 24, 0x06);
7248 for (i = 0; i < 100; i++) {
7249 rt2800_bbp_write(rt2x00dev, 25, 0x90);
7252 stopband = rt2800_bbp_read(rt2x00dev, 55);
7254 if ((passband - stopband) <= filter_target) {
7256 overtuned += ((passband - stopband) == filter_target);
7260 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
7263 rfcsr24 -= !!overtuned;
7265 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
7269 static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev,
7270 const unsigned int rf_reg)
7274 rfcsr = rt2800_rfcsr_read(rt2x00dev, rf_reg);
7275 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1);
7276 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
7278 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0);
7279 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
7282 static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev)
7284 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7290 * TODO: sync filter_tgt values with vendor driver
7292 if (rt2x00_rt(rt2x00dev, RT3070)) {
7293 filter_tgt_bw20 = 0x16;
7294 filter_tgt_bw40 = 0x19;
7296 filter_tgt_bw20 = 0x13;
7297 filter_tgt_bw40 = 0x15;
7300 drv_data->calibration_bw20 =
7301 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20);
7302 drv_data->calibration_bw40 =
7303 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40);
7306 * Save BBP 25 & 26 values for later use in channel switching (for 3052)
7308 drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25);
7309 drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26);
7312 * Set back to initial state
7314 rt2800_bbp_write(rt2x00dev, 24, 0);
7316 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
7317 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
7318 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
7321 * Set BBP back to BW20
7323 bbp = rt2800_bbp_read(rt2x00dev, 4);
7324 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
7325 rt2800_bbp_write(rt2x00dev, 4, bbp);
7328 static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev)
7330 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7331 u8 min_gain, rfcsr, bbp;
7334 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
7336 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
7337 if (rt2x00_rt(rt2x00dev, RT3070) ||
7338 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
7339 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
7340 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
7341 if (!rt2x00_has_cap_external_lna_bg(rt2x00dev))
7342 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
7345 min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
7346 if (drv_data->txmixer_gain_24g >= min_gain) {
7347 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
7348 drv_data->txmixer_gain_24g);
7351 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
7353 if (rt2x00_rt(rt2x00dev, RT3090)) {
7354 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
7355 bbp = rt2800_bbp_read(rt2x00dev, 138);
7356 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
7357 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
7358 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
7359 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
7360 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
7361 rt2800_bbp_write(rt2x00dev, 138, bbp);
7364 if (rt2x00_rt(rt2x00dev, RT3070)) {
7365 rfcsr = rt2800_rfcsr_read(rt2x00dev, 27);
7366 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
7367 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
7369 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
7370 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
7371 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
7372 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
7373 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
7374 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
7375 rt2x00_rt(rt2x00dev, RT3090) ||
7376 rt2x00_rt(rt2x00dev, RT3390)) {
7377 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
7378 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
7379 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
7380 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
7381 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
7382 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
7383 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
7385 rfcsr = rt2800_rfcsr_read(rt2x00dev, 15);
7386 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
7387 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
7389 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
7390 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
7391 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
7393 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
7394 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
7395 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
7399 static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev)
7401 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7405 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
7406 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0);
7407 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
7409 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
7410 tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g,
7411 RFCSR17_TXMIXER_GAIN);
7412 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain);
7413 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
7415 rfcsr = rt2800_rfcsr_read(rt2x00dev, 38);
7416 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
7417 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
7419 rfcsr = rt2800_rfcsr_read(rt2x00dev, 39);
7420 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
7421 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
7423 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
7424 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
7425 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
7426 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
7428 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
7429 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
7430 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
7432 /* TODO: enable stream mode */
7435 static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
7440 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
7441 reg = rt2800_bbp_read(rt2x00dev, 138);
7442 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
7443 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
7444 rt2x00_set_field8(®, BBP138_RX_ADC1, 0);
7445 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
7446 rt2x00_set_field8(®, BBP138_TX_DAC1, 1);
7447 rt2800_bbp_write(rt2x00dev, 138, reg);
7449 reg = rt2800_rfcsr_read(rt2x00dev, 38);
7450 rt2x00_set_field8(®, RFCSR38_RX_LO1_EN, 0);
7451 rt2800_rfcsr_write(rt2x00dev, 38, reg);
7453 reg = rt2800_rfcsr_read(rt2x00dev, 39);
7454 rt2x00_set_field8(®, RFCSR39_RX_LO2_EN, 0);
7455 rt2800_rfcsr_write(rt2x00dev, 39, reg);
7457 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7459 reg = rt2800_rfcsr_read(rt2x00dev, 30);
7460 rt2x00_set_field8(®, RFCSR30_RX_VCM, 2);
7461 rt2800_rfcsr_write(rt2x00dev, 30, reg);
7464 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
7466 rt2800_rf_init_calibration(rt2x00dev, 30);
7468 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
7469 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
7470 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
7471 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
7472 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
7473 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
7474 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
7475 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
7476 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
7477 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
7478 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
7479 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
7480 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
7481 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
7482 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
7483 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
7484 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
7485 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
7486 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
7487 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
7488 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
7489 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
7490 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7491 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
7492 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
7493 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
7494 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
7495 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
7496 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
7497 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
7498 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
7499 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
7502 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
7508 /* XXX vendor driver do this only for 3070 */
7509 rt2800_rf_init_calibration(rt2x00dev, 30);
7511 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
7512 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
7513 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
7514 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
7515 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
7516 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
7517 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
7518 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
7519 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
7520 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
7521 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
7522 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
7523 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
7524 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
7525 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
7526 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
7527 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
7528 rt2800_rfcsr_write(rt2x00dev, 25, 0x03);
7529 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
7531 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
7532 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7533 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1);
7534 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3);
7535 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7536 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
7537 rt2x00_rt(rt2x00dev, RT3090)) {
7538 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
7540 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
7541 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
7542 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
7544 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7545 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1);
7546 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
7547 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
7548 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
7549 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
7550 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3);
7552 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0);
7554 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7556 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
7557 rt2x00_set_field32(®, GPIO_SWITCH_5, 0);
7558 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
7561 rt2800_rx_filter_calibration(rt2x00dev);
7563 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
7564 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
7565 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
7566 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7568 rt2800_led_open_drain_enable(rt2x00dev);
7569 rt2800_normal_mode_setup_3xxx(rt2x00dev);
7572 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
7576 rt2800_rf_init_calibration(rt2x00dev, 2);
7578 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
7579 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
7580 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
7581 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
7582 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
7583 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
7584 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7585 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
7586 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
7587 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
7588 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
7589 rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
7590 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7591 rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
7592 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
7593 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
7594 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
7595 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7596 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7597 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7598 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
7599 rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
7600 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
7601 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
7602 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
7603 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
7604 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
7605 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
7606 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
7607 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
7608 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
7609 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
7610 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
7611 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
7612 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
7613 rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
7614 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
7615 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
7616 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
7617 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
7618 rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
7619 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
7620 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
7621 rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
7622 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
7623 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
7625 rfcsr = rt2800_rfcsr_read(rt2x00dev, 29);
7626 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
7627 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
7629 rt2800_led_open_drain_enable(rt2x00dev);
7630 rt2800_normal_mode_setup_3xxx(rt2x00dev);
7633 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
7635 int tx0_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX0,
7636 &rt2x00dev->cap_flags);
7637 int tx1_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX1,
7638 &rt2x00dev->cap_flags);
7641 rt2800_rf_init_calibration(rt2x00dev, 30);
7643 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
7644 rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
7645 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
7646 rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
7647 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
7648 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
7649 rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
7650 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7651 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
7652 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7653 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
7654 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
7655 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
7656 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
7657 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
7658 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7659 rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
7660 rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
7661 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
7662 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
7663 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
7664 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7665 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
7666 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
7667 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
7668 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
7669 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7670 rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
7671 rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
7672 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7673 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7674 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7675 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
7678 rt2x00_set_field8(&rfcsr, RFCSR34_TX0_EXT_PA, 1);
7680 rt2x00_set_field8(&rfcsr, RFCSR34_TX1_EXT_PA, 1);
7681 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
7682 rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
7683 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
7684 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
7685 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
7686 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
7687 rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
7690 rt2x00_set_field8(&rfcsr, RFCSR41_BIT1, 1);
7691 rt2x00_set_field8(&rfcsr, RFCSR41_BIT4, 1);
7693 rt2800_rfcsr_write(rt2x00dev, 41, rfcsr);
7696 rt2x00_set_field8(&rfcsr, RFCSR42_BIT1, 1);
7697 rt2x00_set_field8(&rfcsr, RFCSR42_BIT4, 1);
7699 rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
7700 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
7701 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
7702 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
7703 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
7704 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
7705 rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
7706 rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
7709 rt2x00_set_field8(&rfcsr, RFCSR50_TX0_EXT_PA, 1);
7711 rt2x00_set_field8(&rfcsr, RFCSR50_TX1_EXT_PA, 1);
7712 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
7713 rt2800_rfcsr_write(rt2x00dev, 51, (tx0_ext_pa ? 0x52 : 0x7f));
7714 rt2800_rfcsr_write(rt2x00dev, 52, (tx0_ext_pa ? 0xc0 : 0x00));
7715 rt2800_rfcsr_write(rt2x00dev, 53, (tx0_ext_pa ? 0xd2 : 0x52));
7716 rt2800_rfcsr_write(rt2x00dev, 54, (tx0_ext_pa ? 0xc0 : 0x1b));
7717 rt2800_rfcsr_write(rt2x00dev, 55, (tx1_ext_pa ? 0x52 : 0x7f));
7718 rt2800_rfcsr_write(rt2x00dev, 56, (tx1_ext_pa ? 0xc0 : 0x00));
7719 rt2800_rfcsr_write(rt2x00dev, 57, (tx0_ext_pa ? 0x49 : 0x52));
7720 rt2800_rfcsr_write(rt2x00dev, 58, (tx1_ext_pa ? 0xc0 : 0x1b));
7721 rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
7722 rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
7723 rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
7724 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
7725 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
7727 rt2800_rx_filter_calibration(rt2x00dev);
7728 rt2800_led_open_drain_enable(rt2x00dev);
7729 rt2800_normal_mode_setup_3xxx(rt2x00dev);
7732 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
7736 rt2800_rf_init_calibration(rt2x00dev, 30);
7738 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
7739 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
7740 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
7741 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
7742 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
7743 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
7744 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
7745 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
7746 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
7747 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
7748 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
7749 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
7750 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
7751 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
7752 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
7753 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
7754 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
7755 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
7756 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
7757 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
7758 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
7759 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
7760 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7761 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
7762 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
7763 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
7764 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
7765 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
7766 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
7767 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
7768 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
7769 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
7771 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
7772 rt2x00_set_field32(®, GPIO_SWITCH_5, 0);
7773 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
7775 rt2800_rx_filter_calibration(rt2x00dev);
7777 if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
7778 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7780 rt2800_led_open_drain_enable(rt2x00dev);
7781 rt2800_normal_mode_setup_3xxx(rt2x00dev);
7784 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
7789 rt2800_rf_init_calibration(rt2x00dev, 30);
7791 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
7792 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
7793 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
7794 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
7795 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
7796 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
7797 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
7798 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
7799 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
7800 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
7801 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
7802 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
7803 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
7804 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
7805 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
7806 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
7807 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
7808 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
7809 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
7810 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
7811 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
7812 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7813 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
7814 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
7815 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
7816 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
7817 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
7818 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
7819 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
7820 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
7821 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
7823 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
7824 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
7825 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
7827 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7828 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3);
7829 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1);
7830 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7832 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7833 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0);
7834 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1);
7835 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7837 rt2800_rx_filter_calibration(rt2x00dev);
7838 rt2800_led_open_drain_enable(rt2x00dev);
7839 rt2800_normal_mode_setup_3xxx(rt2x00dev);
7842 static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev)
7845 bool txbf_enabled = false; /* FIXME */
7847 bbp = rt2800_bbp_read(rt2x00dev, 105);
7848 if (rt2x00dev->default_ant.rx_chain_num == 1)
7849 rt2x00_set_field8(&bbp, BBP105_MLD, 0);
7851 rt2x00_set_field8(&bbp, BBP105_MLD, 1);
7852 rt2800_bbp_write(rt2x00dev, 105, bbp);
7854 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7856 rt2800_bbp_write(rt2x00dev, 92, 0x02);
7857 rt2800_bbp_write(rt2x00dev, 82, 0x82);
7858 rt2800_bbp_write(rt2x00dev, 106, 0x05);
7859 rt2800_bbp_write(rt2x00dev, 104, 0x92);
7860 rt2800_bbp_write(rt2x00dev, 88, 0x90);
7861 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
7862 rt2800_bbp_write(rt2x00dev, 47, 0x48);
7863 rt2800_bbp_write(rt2x00dev, 120, 0x50);
7866 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
7868 rt2800_bbp_write(rt2x00dev, 163, 0x9d);
7871 rt2800_bbp_write(rt2x00dev, 142, 6);
7872 rt2800_bbp_write(rt2x00dev, 143, 160);
7873 rt2800_bbp_write(rt2x00dev, 142, 7);
7874 rt2800_bbp_write(rt2x00dev, 143, 161);
7875 rt2800_bbp_write(rt2x00dev, 142, 8);
7876 rt2800_bbp_write(rt2x00dev, 143, 162);
7878 /* ADC/DAC control */
7879 rt2800_bbp_write(rt2x00dev, 31, 0x08);
7881 /* RX AGC energy lower bound in log2 */
7882 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
7884 /* FIXME: BBP 105 owerwrite? */
7885 rt2800_bbp_write(rt2x00dev, 105, 0x04);
7889 static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev)
7891 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7895 /* Disable GPIO #4 and #7 function for LAN PE control */
7896 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
7897 rt2x00_set_field32(®, GPIO_SWITCH_4, 0);
7898 rt2x00_set_field32(®, GPIO_SWITCH_7, 0);
7899 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
7901 /* Initialize default register values */
7902 rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
7903 rt2800_rfcsr_write(rt2x00dev, 3, 0x80);
7904 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
7905 rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
7906 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
7907 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7908 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
7909 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
7910 rt2800_rfcsr_write(rt2x00dev, 12, 0x4e);
7911 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
7912 rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
7913 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7914 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7915 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7916 rt2800_rfcsr_write(rt2x00dev, 32, 0x78);
7917 rt2800_rfcsr_write(rt2x00dev, 33, 0x3b);
7918 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
7919 rt2800_rfcsr_write(rt2x00dev, 35, 0xe0);
7920 rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
7921 rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
7922 rt2800_rfcsr_write(rt2x00dev, 44, 0xd3);
7923 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
7924 rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
7925 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
7926 rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
7927 rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
7928 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
7929 rt2800_rfcsr_write(rt2x00dev, 53, 0x18);
7930 rt2800_rfcsr_write(rt2x00dev, 54, 0x18);
7931 rt2800_rfcsr_write(rt2x00dev, 55, 0x18);
7932 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
7933 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
7935 /* Initiate calibration */
7936 /* TODO: use rt2800_rf_init_calibration ? */
7937 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
7938 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
7939 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
7941 rt2800_freq_cal_mode1(rt2x00dev);
7943 rfcsr = rt2800_rfcsr_read(rt2x00dev, 18);
7944 rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1);
7945 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
7947 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7948 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3);
7949 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1);
7950 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7951 usleep_range(1000, 1500);
7952 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7953 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0);
7954 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7956 /* Set initial values for RX filter calibration */
7957 drv_data->calibration_bw20 = 0x1f;
7958 drv_data->calibration_bw40 = 0x2f;
7960 /* Save BBP 25 & 26 values for later use in channel switching */
7961 drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25);
7962 drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26);
7964 rt2800_led_open_drain_enable(rt2x00dev);
7965 rt2800_normal_mode_setup_3593(rt2x00dev);
7967 rt3593_post_bbp_init(rt2x00dev);
7969 /* TODO: enable stream mode support */
7972 static void rt2800_init_rfcsr_5350(struct rt2x00_dev *rt2x00dev)
7974 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
7975 rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
7976 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
7977 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
7978 rt2800_rfcsr_write(rt2x00dev, 4, 0x49);
7979 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
7980 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
7981 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7982 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
7983 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7984 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
7985 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
7986 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
7987 if (rt2800_clk_is_20mhz(rt2x00dev))
7988 rt2800_rfcsr_write(rt2x00dev, 13, 0x1f);
7990 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
7991 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
7992 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7993 rt2800_rfcsr_write(rt2x00dev, 16, 0xc0);
7994 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
7995 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
7996 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
7997 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
7998 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7999 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
8000 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
8001 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
8002 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
8003 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
8004 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8005 rt2800_rfcsr_write(rt2x00dev, 29, 0xd0);
8006 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
8007 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
8008 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
8009 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
8010 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
8011 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
8012 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8013 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
8014 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
8015 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
8016 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
8017 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
8018 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
8019 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
8020 rt2800_rfcsr_write(rt2x00dev, 44, 0x0c);
8021 rt2800_rfcsr_write(rt2x00dev, 45, 0xa6);
8022 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
8023 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
8024 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
8025 rt2800_rfcsr_write(rt2x00dev, 49, 0x80);
8026 rt2800_rfcsr_write(rt2x00dev, 50, 0x00);
8027 rt2800_rfcsr_write(rt2x00dev, 51, 0x00);
8028 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
8029 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
8030 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
8031 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
8032 rt2800_rfcsr_write(rt2x00dev, 56, 0x82);
8033 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
8034 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
8035 rt2800_rfcsr_write(rt2x00dev, 59, 0x0b);
8036 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
8037 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
8038 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
8039 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
8042 static void rt2800_init_rfcsr_3883(struct rt2x00_dev *rt2x00dev)
8046 /* TODO: get the actual ECO value from the SoC */
8047 const unsigned int eco = 5;
8049 rt2800_rf_init_calibration(rt2x00dev, 2);
8051 rt2800_rfcsr_write(rt2x00dev, 0, 0xe0);
8052 rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
8053 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
8054 rt2800_rfcsr_write(rt2x00dev, 3, 0x20);
8055 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
8056 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
8057 rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
8058 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8059 rt2800_rfcsr_write(rt2x00dev, 8, 0x5b);
8060 rt2800_rfcsr_write(rt2x00dev, 9, 0x08);
8061 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
8062 rt2800_rfcsr_write(rt2x00dev, 11, 0x48);
8063 rt2800_rfcsr_write(rt2x00dev, 12, 0x1a);
8064 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
8065 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8066 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8067 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
8069 /* RFCSR 17 will be initialized later based on the
8070 * frequency offset stored in the EEPROM
8073 rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
8074 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
8075 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
8076 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
8077 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
8078 rt2800_rfcsr_write(rt2x00dev, 23, 0xc0);
8079 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
8080 rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
8081 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
8082 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
8083 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8084 rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
8085 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
8086 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
8087 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
8088 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
8089 rt2800_rfcsr_write(rt2x00dev, 34, 0x20);
8090 rt2800_rfcsr_write(rt2x00dev, 35, 0x00);
8091 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8092 rt2800_rfcsr_write(rt2x00dev, 37, 0x00);
8093 rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
8094 rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
8095 rt2800_rfcsr_write(rt2x00dev, 40, 0x00);
8096 rt2800_rfcsr_write(rt2x00dev, 41, 0x00);
8097 rt2800_rfcsr_write(rt2x00dev, 42, 0x00);
8098 rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
8099 rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
8100 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
8101 rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
8102 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
8103 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
8104 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
8105 rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
8106 rt2800_rfcsr_write(rt2x00dev, 51, 0x51);
8107 rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
8108 rt2800_rfcsr_write(rt2x00dev, 53, 0x76);
8109 rt2800_rfcsr_write(rt2x00dev, 54, 0x76);
8110 rt2800_rfcsr_write(rt2x00dev, 55, 0x76);
8111 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
8112 rt2800_rfcsr_write(rt2x00dev, 57, 0x3e);
8113 rt2800_rfcsr_write(rt2x00dev, 58, 0x00);
8114 rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
8115 rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
8116 rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
8117 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
8118 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
8120 /* TODO: rx filter calibration? */
8122 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
8124 rt2800_bbp_write(rt2x00dev, 163, 0x9d);
8126 rt2800_bbp_write(rt2x00dev, 105, 0x05);
8128 rt2800_bbp_write(rt2x00dev, 179, 0x02);
8129 rt2800_bbp_write(rt2x00dev, 180, 0x00);
8130 rt2800_bbp_write(rt2x00dev, 182, 0x40);
8131 rt2800_bbp_write(rt2x00dev, 180, 0x01);
8132 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
8134 rt2800_bbp_write(rt2x00dev, 179, 0x00);
8136 rt2800_bbp_write(rt2x00dev, 142, 0x04);
8137 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
8138 rt2800_bbp_write(rt2x00dev, 142, 0x06);
8139 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
8140 rt2800_bbp_write(rt2x00dev, 142, 0x07);
8141 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
8142 rt2800_bbp_write(rt2x00dev, 142, 0x08);
8143 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
8144 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
8147 rt2800_rfcsr_write(rt2x00dev, 32, 0xd8);
8148 rt2800_rfcsr_write(rt2x00dev, 33, 0x32);
8151 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
8152 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_BP, 0);
8153 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
8154 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
8156 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
8157 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
8159 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
8160 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
8161 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
8163 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
8165 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
8167 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
8169 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
8171 rfcsr = rt2800_rfcsr_read(rt2x00dev, 46);
8173 rt2800_rfcsr_write(rt2x00dev, 46, rfcsr);
8175 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
8177 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
8180 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
8182 rt2800_rf_init_calibration(rt2x00dev, 2);
8184 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
8185 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
8186 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
8187 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
8188 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8189 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
8191 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
8192 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8193 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
8194 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
8195 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
8196 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
8197 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8198 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8199 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
8200 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
8201 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
8203 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
8204 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
8205 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
8206 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
8207 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
8208 if (rt2x00_is_usb(rt2x00dev) &&
8209 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8210 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
8212 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
8213 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
8214 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
8215 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8216 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
8218 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
8219 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
8220 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
8221 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
8222 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
8223 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
8224 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8225 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
8226 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
8227 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
8229 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
8230 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
8231 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
8232 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
8233 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
8234 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
8235 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8236 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
8238 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
8239 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
8240 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
8241 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
8243 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
8244 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8245 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
8247 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
8248 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
8249 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
8250 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8251 rt2800_rfcsr_write(rt2x00dev, 56, 0x42);
8253 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
8254 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
8255 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
8256 rt2800_rfcsr_write(rt2x00dev, 59, 0x8f);
8258 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
8259 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
8260 if (rt2x00_is_usb(rt2x00dev))
8261 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
8263 rt2800_rfcsr_write(rt2x00dev, 61, 0xd5);
8265 if (rt2x00_is_usb(rt2x00dev))
8266 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
8268 rt2800_rfcsr_write(rt2x00dev, 61, 0xb5);
8270 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
8271 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
8273 rt2800_normal_mode_setup_5xxx(rt2x00dev);
8275 rt2800_led_open_drain_enable(rt2x00dev);
8278 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
8280 rt2800_rf_init_calibration(rt2x00dev, 2);
8282 rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
8283 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
8284 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
8285 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
8286 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8287 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
8288 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
8289 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
8290 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
8291 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8292 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8293 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
8294 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
8295 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
8296 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
8297 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
8298 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
8299 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
8300 rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
8301 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
8302 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
8303 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
8304 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8305 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
8306 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
8307 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
8308 rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
8309 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
8310 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
8311 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
8312 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8313 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
8314 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
8315 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
8316 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
8317 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
8318 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
8319 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
8320 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
8321 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
8322 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
8323 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
8324 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
8325 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
8326 rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
8327 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
8328 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
8329 rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
8330 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
8331 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
8332 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
8333 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
8334 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
8335 rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
8336 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
8337 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
8338 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
8339 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
8341 rt2800_normal_mode_setup_5xxx(rt2x00dev);
8343 rt2800_led_open_drain_enable(rt2x00dev);
8346 static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
8348 rt2800_rf_init_calibration(rt2x00dev, 30);
8350 rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
8351 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
8352 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
8353 rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
8354 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8355 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8356 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8357 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
8358 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
8359 rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
8360 rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
8361 rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
8362 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
8363 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8364 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
8365 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
8366 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
8367 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
8368 rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
8369 rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
8370 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
8372 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
8375 rt2800_freq_cal_mode1(rt2x00dev);
8377 /* Enable DC filter */
8378 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
8379 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
8381 rt2800_normal_mode_setup_5xxx(rt2x00dev);
8383 if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
8384 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
8386 rt2800_led_open_drain_enable(rt2x00dev);
8389 static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,
8390 bool set_bw, bool is_ht40)
8394 bbp_val = rt2800_bbp_read(rt2x00dev, 21);
8396 rt2800_bbp_write(rt2x00dev, 21, bbp_val);
8397 usleep_range(100, 200);
8400 bbp_val = rt2800_bbp_read(rt2x00dev, 4);
8401 rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, 2 * is_ht40);
8402 rt2800_bbp_write(rt2x00dev, 4, bbp_val);
8403 usleep_range(100, 200);
8406 bbp_val = rt2800_bbp_read(rt2x00dev, 21);
8408 rt2800_bbp_write(rt2x00dev, 21, bbp_val);
8409 usleep_range(100, 200);
8412 static int rt2800_rf_lp_config(struct rt2x00_dev *rt2x00dev, bool btxcal)
8417 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
8419 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x02);
8421 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x06);
8423 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
8425 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rf_val);
8428 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xC1);
8429 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x20);
8430 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02);
8431 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
8434 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val);
8435 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
8438 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val);
8439 rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, 0x31);
8441 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xF1);
8442 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x18);
8443 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02);
8444 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
8447 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val);
8448 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
8451 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val);
8457 static char rt2800_lp_tx_filter_bw_cal(struct rt2x00_dev *rt2x00dev)
8463 rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x82);
8467 usleep_range(500, 2000);
8468 bbp_val = rt2800_bbp_read(rt2x00dev, 159);
8469 if (bbp_val == 0x02 || cnt == 20)
8475 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 0x39);
8476 cal_val = bbp_val & 0x7F;
8477 if (cal_val >= 0x40)
8483 static void rt2800_bw_filter_calibration(struct rt2x00_dev *rt2x00dev,
8486 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
8487 u8 tx_agc_fc = 0, rx_agc_fc = 0, cmm_agc_fc;
8489 u8 tx_filter_target_20m = 0x09, tx_filter_target_40m = 0x02;
8490 u8 rx_filter_target_20m = 0x27, rx_filter_target_40m = 0x31;
8491 int loop = 0, is_ht40, cnt;
8493 char cal_r32_init, cal_r32_val, cal_diff;
8494 u8 saverfb5r00, saverfb5r01, saverfb5r03, saverfb5r04, saverfb5r05;
8495 u8 saverfb5r06, saverfb5r07;
8496 u8 saverfb5r08, saverfb5r17, saverfb5r18, saverfb5r19, saverfb5r20;
8497 u8 saverfb5r37, saverfb5r38, saverfb5r39, saverfb5r40, saverfb5r41;
8498 u8 saverfb5r42, saverfb5r43, saverfb5r44, saverfb5r45, saverfb5r46;
8499 u8 saverfb5r58, saverfb5r59;
8500 u8 savebbp159r0, savebbp159r2, savebbpr23;
8501 u32 MAC_RF_CONTROL0, MAC_RF_BYPASS0;
8503 /* Save MAC registers */
8504 MAC_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
8505 MAC_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
8507 /* save BBP registers */
8508 savebbpr23 = rt2800_bbp_read(rt2x00dev, 23);
8510 savebbp159r0 = rt2800_bbp_dcoc_read(rt2x00dev, 0);
8511 savebbp159r2 = rt2800_bbp_dcoc_read(rt2x00dev, 2);
8513 /* Save RF registers */
8514 saverfb5r00 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
8515 saverfb5r01 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
8516 saverfb5r03 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
8517 saverfb5r04 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
8518 saverfb5r05 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 5);
8519 saverfb5r06 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
8520 saverfb5r07 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
8521 saverfb5r08 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8);
8522 saverfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
8523 saverfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
8524 saverfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
8525 saverfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
8527 saverfb5r37 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 37);
8528 saverfb5r38 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 38);
8529 saverfb5r39 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 39);
8530 saverfb5r40 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 40);
8531 saverfb5r41 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 41);
8532 saverfb5r42 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 42);
8533 saverfb5r43 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 43);
8534 saverfb5r44 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 44);
8535 saverfb5r45 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 45);
8536 saverfb5r46 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 46);
8538 saverfb5r58 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
8539 saverfb5r59 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
8541 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
8543 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val);
8545 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
8547 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rf_val);
8551 usleep_range(500, 2000);
8552 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
8553 if (((rf_val & 0x1) == 0x00) || (cnt == 40))
8558 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
8561 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val);
8564 bbp_val = rt2800_bbp_read(rt2x00dev, 23);
8567 rt2800_bbp_write(rt2x00dev, 23, bbp_val);
8575 filter_target = tx_filter_target_20m;
8577 filter_target = rx_filter_target_20m;
8582 filter_target = tx_filter_target_40m;
8584 filter_target = rx_filter_target_40m;
8587 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8);
8592 rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, rf_val);
8594 rt2800_bbp_core_soft_reset(rt2x00dev, true, is_ht40);
8596 rt2800_rf_lp_config(rt2x00dev, btxcal);
8599 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
8601 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val);
8602 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
8604 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val);
8607 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
8609 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val);
8610 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
8612 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val);
8615 usleep_range(1000, 2000);
8617 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2);
8619 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val);
8621 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40);
8623 cal_r32_init = rt2800_lp_tx_filter_bw_cal(rt2x00dev);
8625 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2);
8627 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val);
8630 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
8632 rf_val |= tx_agc_fc;
8633 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val);
8634 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
8636 rf_val |= tx_agc_fc;
8637 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val);
8639 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
8641 rf_val |= rx_agc_fc;
8642 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val);
8643 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
8645 rf_val |= rx_agc_fc;
8646 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val);
8649 usleep_range(500, 1000);
8651 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40);
8653 cal_r32_val = rt2800_lp_tx_filter_bw_cal(rt2x00dev);
8655 cal_diff = cal_r32_init - cal_r32_val;
8658 cmm_agc_fc = tx_agc_fc;
8660 cmm_agc_fc = rx_agc_fc;
8662 if (((cal_diff > filter_target) && (cmm_agc_fc == 0)) ||
8663 ((cal_diff < filter_target) && (cmm_agc_fc == 0x3f))) {
8668 } else if ((cal_diff <= filter_target) && (cmm_agc_fc < 0x3f)) {
8678 drv_data->tx_calibration_bw20 = tx_agc_fc;
8680 drv_data->tx_calibration_bw40 = tx_agc_fc;
8683 drv_data->rx_calibration_bw20 = rx_agc_fc;
8685 drv_data->rx_calibration_bw40 = rx_agc_fc;
8689 } while (loop <= 1);
8691 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, saverfb5r00);
8692 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, saverfb5r01);
8693 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, saverfb5r03);
8694 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r04);
8695 rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, saverfb5r05);
8696 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, saverfb5r06);
8697 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, saverfb5r07);
8698 rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, saverfb5r08);
8699 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17);
8700 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18);
8701 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19);
8702 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20);
8704 rt2800_rfcsr_write_bank(rt2x00dev, 5, 37, saverfb5r37);
8705 rt2800_rfcsr_write_bank(rt2x00dev, 5, 38, saverfb5r38);
8706 rt2800_rfcsr_write_bank(rt2x00dev, 5, 39, saverfb5r39);
8707 rt2800_rfcsr_write_bank(rt2x00dev, 5, 40, saverfb5r40);
8708 rt2800_rfcsr_write_bank(rt2x00dev, 5, 41, saverfb5r41);
8709 rt2800_rfcsr_write_bank(rt2x00dev, 5, 42, saverfb5r42);
8710 rt2800_rfcsr_write_bank(rt2x00dev, 5, 43, saverfb5r43);
8711 rt2800_rfcsr_write_bank(rt2x00dev, 5, 44, saverfb5r44);
8712 rt2800_rfcsr_write_bank(rt2x00dev, 5, 45, saverfb5r45);
8713 rt2800_rfcsr_write_bank(rt2x00dev, 5, 46, saverfb5r46);
8715 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, saverfb5r58);
8716 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, saverfb5r59);
8718 rt2800_bbp_write(rt2x00dev, 23, savebbpr23);
8720 rt2800_bbp_dcoc_write(rt2x00dev, 0, savebbp159r0);
8721 rt2800_bbp_dcoc_write(rt2x00dev, 2, savebbp159r2);
8723 bbp_val = rt2800_bbp_read(rt2x00dev, 4);
8724 rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH,
8725 2 * test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags));
8726 rt2800_bbp_write(rt2x00dev, 4, bbp_val);
8728 rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0);
8729 rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0);
8732 static void rt2800_init_rfcsr_6352(struct rt2x00_dev *rt2x00dev)
8734 /* Initialize RF central register to default value */
8735 rt2800_rfcsr_write(rt2x00dev, 0, 0x02);
8736 rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
8737 rt2800_rfcsr_write(rt2x00dev, 2, 0x33);
8738 rt2800_rfcsr_write(rt2x00dev, 3, 0xFF);
8739 rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
8740 rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
8741 rt2800_rfcsr_write(rt2x00dev, 6, 0x00);
8742 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8743 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
8744 rt2800_rfcsr_write(rt2x00dev, 9, 0x00);
8745 rt2800_rfcsr_write(rt2x00dev, 10, 0x00);
8746 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
8747 rt2800_rfcsr_write(rt2x00dev, 12, rt2x00dev->freq_offset);
8748 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
8749 rt2800_rfcsr_write(rt2x00dev, 14, 0x40);
8750 rt2800_rfcsr_write(rt2x00dev, 15, 0x22);
8751 rt2800_rfcsr_write(rt2x00dev, 16, 0x4C);
8752 rt2800_rfcsr_write(rt2x00dev, 17, 0x00);
8753 rt2800_rfcsr_write(rt2x00dev, 18, 0x00);
8754 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
8755 rt2800_rfcsr_write(rt2x00dev, 20, 0xA0);
8756 rt2800_rfcsr_write(rt2x00dev, 21, 0x12);
8757 rt2800_rfcsr_write(rt2x00dev, 22, 0x07);
8758 rt2800_rfcsr_write(rt2x00dev, 23, 0x13);
8759 rt2800_rfcsr_write(rt2x00dev, 24, 0xFE);
8760 rt2800_rfcsr_write(rt2x00dev, 25, 0x24);
8761 rt2800_rfcsr_write(rt2x00dev, 26, 0x7A);
8762 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
8763 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8764 rt2800_rfcsr_write(rt2x00dev, 29, 0x05);
8765 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
8766 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
8767 rt2800_rfcsr_write(rt2x00dev, 32, 0x00);
8768 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
8769 rt2800_rfcsr_write(rt2x00dev, 34, 0x00);
8770 rt2800_rfcsr_write(rt2x00dev, 35, 0x00);
8771 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8772 rt2800_rfcsr_write(rt2x00dev, 37, 0x00);
8773 rt2800_rfcsr_write(rt2x00dev, 38, 0x00);
8774 rt2800_rfcsr_write(rt2x00dev, 39, 0x00);
8775 rt2800_rfcsr_write(rt2x00dev, 40, 0x00);
8776 rt2800_rfcsr_write(rt2x00dev, 41, 0xD0);
8777 rt2800_rfcsr_write(rt2x00dev, 42, 0x5B);
8778 rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
8780 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
8781 if (rt2800_clk_is_20mhz(rt2x00dev))
8782 rt2800_rfcsr_write(rt2x00dev, 13, 0x03);
8784 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
8785 rt2800_rfcsr_write(rt2x00dev, 14, 0x7C);
8786 rt2800_rfcsr_write(rt2x00dev, 16, 0x80);
8787 rt2800_rfcsr_write(rt2x00dev, 17, 0x99);
8788 rt2800_rfcsr_write(rt2x00dev, 18, 0x99);
8789 rt2800_rfcsr_write(rt2x00dev, 19, 0x09);
8790 rt2800_rfcsr_write(rt2x00dev, 20, 0x50);
8791 rt2800_rfcsr_write(rt2x00dev, 21, 0xB0);
8792 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
8793 rt2800_rfcsr_write(rt2x00dev, 23, 0x06);
8794 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
8795 rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
8796 rt2800_rfcsr_write(rt2x00dev, 26, 0x5D);
8797 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
8798 rt2800_rfcsr_write(rt2x00dev, 28, 0x61);
8799 rt2800_rfcsr_write(rt2x00dev, 29, 0xB5);
8800 rt2800_rfcsr_write(rt2x00dev, 43, 0x02);
8802 rt2800_rfcsr_write(rt2x00dev, 28, 0x62);
8803 rt2800_rfcsr_write(rt2x00dev, 29, 0xAD);
8804 rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
8806 /* Initialize RF channel register to default value */
8807 rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03);
8808 rt2800_rfcsr_write_chanreg(rt2x00dev, 1, 0x00);
8809 rt2800_rfcsr_write_chanreg(rt2x00dev, 2, 0x00);
8810 rt2800_rfcsr_write_chanreg(rt2x00dev, 3, 0x00);
8811 rt2800_rfcsr_write_chanreg(rt2x00dev, 4, 0x00);
8812 rt2800_rfcsr_write_chanreg(rt2x00dev, 5, 0x08);
8813 rt2800_rfcsr_write_chanreg(rt2x00dev, 6, 0x00);
8814 rt2800_rfcsr_write_chanreg(rt2x00dev, 7, 0x51);
8815 rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x53);
8816 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x16);
8817 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x61);
8818 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
8819 rt2800_rfcsr_write_chanreg(rt2x00dev, 12, 0x22);
8820 rt2800_rfcsr_write_chanreg(rt2x00dev, 13, 0x3D);
8821 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
8822 rt2800_rfcsr_write_chanreg(rt2x00dev, 15, 0x13);
8823 rt2800_rfcsr_write_chanreg(rt2x00dev, 16, 0x22);
8824 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x27);
8825 rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02);
8826 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
8827 rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x01);
8828 rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x52);
8829 rt2800_rfcsr_write_chanreg(rt2x00dev, 22, 0x80);
8830 rt2800_rfcsr_write_chanreg(rt2x00dev, 23, 0xB3);
8831 rt2800_rfcsr_write_chanreg(rt2x00dev, 24, 0x00);
8832 rt2800_rfcsr_write_chanreg(rt2x00dev, 25, 0x00);
8833 rt2800_rfcsr_write_chanreg(rt2x00dev, 26, 0x00);
8834 rt2800_rfcsr_write_chanreg(rt2x00dev, 27, 0x00);
8835 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x5C);
8836 rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0x6B);
8837 rt2800_rfcsr_write_chanreg(rt2x00dev, 30, 0x6B);
8838 rt2800_rfcsr_write_chanreg(rt2x00dev, 31, 0x31);
8839 rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x5D);
8840 rt2800_rfcsr_write_chanreg(rt2x00dev, 33, 0x00);
8841 rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xE6);
8842 rt2800_rfcsr_write_chanreg(rt2x00dev, 35, 0x55);
8843 rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x00);
8844 rt2800_rfcsr_write_chanreg(rt2x00dev, 37, 0xBB);
8845 rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB3);
8846 rt2800_rfcsr_write_chanreg(rt2x00dev, 39, 0xB3);
8847 rt2800_rfcsr_write_chanreg(rt2x00dev, 40, 0x03);
8848 rt2800_rfcsr_write_chanreg(rt2x00dev, 41, 0x00);
8849 rt2800_rfcsr_write_chanreg(rt2x00dev, 42, 0x00);
8850 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xB3);
8851 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xD3);
8852 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
8853 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x07);
8854 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x68);
8855 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xEF);
8856 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1C);
8857 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x07);
8858 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xA8);
8859 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0x85);
8860 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x10);
8861 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x07);
8862 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6A);
8863 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0x85);
8864 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x10);
8865 rt2800_rfcsr_write_chanreg(rt2x00dev, 62, 0x1C);
8866 rt2800_rfcsr_write_chanreg(rt2x00dev, 63, 0x00);
8868 rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5);
8870 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);
8871 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);
8872 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33);
8873 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E);
8874 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
8875 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4);
8876 rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02);
8877 rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12);
8878 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C);
8879 rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB);
8880 rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D);
8881 rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6);
8882 rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08);
8883 rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4);
8884 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
8885 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);
8886 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
8887 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
8888 rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67);
8889 rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69);
8890 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF);
8891 rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27);
8892 rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20);
8893 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
8894 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);
8895 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);
8896 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
8897 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
8898 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
8899 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
8901 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
8902 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
8903 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
8904 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);
8905 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
8906 rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);
8907 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
8908 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
8909 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
8911 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
8912 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
8913 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
8914 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
8915 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
8916 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
8918 /* Initialize RF channel register for DRQFN */
8919 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
8920 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);
8921 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);
8922 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);
8923 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);
8924 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);
8925 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);
8926 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);
8928 /* Initialize RF DC calibration register to default value */
8929 rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47);
8930 rt2800_rfcsr_write_dccal(rt2x00dev, 1, 0x00);
8931 rt2800_rfcsr_write_dccal(rt2x00dev, 2, 0x00);
8932 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x00);
8933 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x00);
8934 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
8935 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
8936 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
8937 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
8938 rt2800_rfcsr_write_dccal(rt2x00dev, 9, 0x00);
8939 rt2800_rfcsr_write_dccal(rt2x00dev, 10, 0x07);
8940 rt2800_rfcsr_write_dccal(rt2x00dev, 11, 0x01);
8941 rt2800_rfcsr_write_dccal(rt2x00dev, 12, 0x07);
8942 rt2800_rfcsr_write_dccal(rt2x00dev, 13, 0x07);
8943 rt2800_rfcsr_write_dccal(rt2x00dev, 14, 0x07);
8944 rt2800_rfcsr_write_dccal(rt2x00dev, 15, 0x20);
8945 rt2800_rfcsr_write_dccal(rt2x00dev, 16, 0x22);
8946 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x00);
8947 rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0x00);
8948 rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x00);
8949 rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00);
8950 rt2800_rfcsr_write_dccal(rt2x00dev, 21, 0xF1);
8951 rt2800_rfcsr_write_dccal(rt2x00dev, 22, 0x11);
8952 rt2800_rfcsr_write_dccal(rt2x00dev, 23, 0x02);
8953 rt2800_rfcsr_write_dccal(rt2x00dev, 24, 0x41);
8954 rt2800_rfcsr_write_dccal(rt2x00dev, 25, 0x20);
8955 rt2800_rfcsr_write_dccal(rt2x00dev, 26, 0x00);
8956 rt2800_rfcsr_write_dccal(rt2x00dev, 27, 0xD7);
8957 rt2800_rfcsr_write_dccal(rt2x00dev, 28, 0xA2);
8958 rt2800_rfcsr_write_dccal(rt2x00dev, 29, 0x20);
8959 rt2800_rfcsr_write_dccal(rt2x00dev, 30, 0x49);
8960 rt2800_rfcsr_write_dccal(rt2x00dev, 31, 0x20);
8961 rt2800_rfcsr_write_dccal(rt2x00dev, 32, 0x04);
8962 rt2800_rfcsr_write_dccal(rt2x00dev, 33, 0xF1);
8963 rt2800_rfcsr_write_dccal(rt2x00dev, 34, 0xA1);
8964 rt2800_rfcsr_write_dccal(rt2x00dev, 35, 0x01);
8965 rt2800_rfcsr_write_dccal(rt2x00dev, 41, 0x00);
8966 rt2800_rfcsr_write_dccal(rt2x00dev, 42, 0x00);
8967 rt2800_rfcsr_write_dccal(rt2x00dev, 43, 0x00);
8968 rt2800_rfcsr_write_dccal(rt2x00dev, 44, 0x00);
8969 rt2800_rfcsr_write_dccal(rt2x00dev, 45, 0x00);
8970 rt2800_rfcsr_write_dccal(rt2x00dev, 46, 0x00);
8971 rt2800_rfcsr_write_dccal(rt2x00dev, 47, 0x3E);
8972 rt2800_rfcsr_write_dccal(rt2x00dev, 48, 0x3D);
8973 rt2800_rfcsr_write_dccal(rt2x00dev, 49, 0x3E);
8974 rt2800_rfcsr_write_dccal(rt2x00dev, 50, 0x3D);
8975 rt2800_rfcsr_write_dccal(rt2x00dev, 51, 0x3E);
8976 rt2800_rfcsr_write_dccal(rt2x00dev, 52, 0x3D);
8977 rt2800_rfcsr_write_dccal(rt2x00dev, 53, 0x00);
8978 rt2800_rfcsr_write_dccal(rt2x00dev, 54, 0x00);
8979 rt2800_rfcsr_write_dccal(rt2x00dev, 55, 0x00);
8980 rt2800_rfcsr_write_dccal(rt2x00dev, 56, 0x00);
8981 rt2800_rfcsr_write_dccal(rt2x00dev, 57, 0x00);
8982 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
8983 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
8984 rt2800_rfcsr_write_dccal(rt2x00dev, 60, 0x0A);
8985 rt2800_rfcsr_write_dccal(rt2x00dev, 61, 0x00);
8986 rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00);
8987 rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00);
8989 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08);
8990 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04);
8991 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20);
8993 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
8994 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
8996 rt2800_bw_filter_calibration(rt2x00dev, true);
8997 rt2800_bw_filter_calibration(rt2x00dev, false);
9000 static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
9002 if (rt2800_is_305x_soc(rt2x00dev)) {
9003 rt2800_init_rfcsr_305x_soc(rt2x00dev);
9007 switch (rt2x00dev->chip.rt) {
9011 rt2800_init_rfcsr_30xx(rt2x00dev);
9014 rt2800_init_rfcsr_3290(rt2x00dev);
9017 rt2800_init_rfcsr_3352(rt2x00dev);
9020 rt2800_init_rfcsr_3390(rt2x00dev);
9023 rt2800_init_rfcsr_3883(rt2x00dev);
9026 rt2800_init_rfcsr_3572(rt2x00dev);
9029 rt2800_init_rfcsr_3593(rt2x00dev);
9032 rt2800_init_rfcsr_5350(rt2x00dev);
9035 rt2800_init_rfcsr_5390(rt2x00dev);
9038 rt2800_init_rfcsr_5392(rt2x00dev);
9041 rt2800_init_rfcsr_5592(rt2x00dev);
9044 rt2800_init_rfcsr_6352(rt2x00dev);
9049 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
9055 * Initialize MAC registers.
9057 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
9058 rt2800_init_registers(rt2x00dev)))
9062 * Wait BBP/RF to wake up.
9064 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev)))
9068 * Send signal during boot time to initialize firmware.
9070 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
9071 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
9072 if (rt2x00_is_usb(rt2x00dev))
9073 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
9074 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
9078 * Make sure BBP is up and running.
9080 if (unlikely(rt2800_wait_bbp_ready(rt2x00dev)))
9084 * Initialize BBP/RF registers.
9086 rt2800_init_bbp(rt2x00dev);
9087 rt2800_init_rfcsr(rt2x00dev);
9089 if (rt2x00_is_usb(rt2x00dev) &&
9090 (rt2x00_rt(rt2x00dev, RT3070) ||
9091 rt2x00_rt(rt2x00dev, RT3071) ||
9092 rt2x00_rt(rt2x00dev, RT3572))) {
9094 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
9101 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
9102 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1);
9103 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0);
9104 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
9108 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
9109 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
9110 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
9111 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9112 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
9114 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
9115 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1);
9116 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1);
9117 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
9120 * Initialize LED control
9122 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF);
9123 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
9124 word & 0xff, (word >> 8) & 0xff);
9126 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF);
9127 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
9128 word & 0xff, (word >> 8) & 0xff);
9130 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY);
9131 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
9132 word & 0xff, (word >> 8) & 0xff);
9136 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
9138 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
9142 rt2800_disable_wpdma(rt2x00dev);
9144 /* Wait for DMA, ignore error */
9145 rt2800_wait_wpdma_ready(rt2x00dev);
9147 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
9148 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 0);
9149 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0);
9150 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
9152 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
9154 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
9159 if (rt2x00_rt(rt2x00dev, RT3290))
9160 efuse_ctrl_reg = EFUSE_CTRL_3290;
9162 efuse_ctrl_reg = EFUSE_CTRL;
9164 reg = rt2800_register_read(rt2x00dev, efuse_ctrl_reg);
9165 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
9167 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
9169 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
9173 u16 efuse_data0_reg;
9174 u16 efuse_data1_reg;
9175 u16 efuse_data2_reg;
9176 u16 efuse_data3_reg;
9178 if (rt2x00_rt(rt2x00dev, RT3290)) {
9179 efuse_ctrl_reg = EFUSE_CTRL_3290;
9180 efuse_data0_reg = EFUSE_DATA0_3290;
9181 efuse_data1_reg = EFUSE_DATA1_3290;
9182 efuse_data2_reg = EFUSE_DATA2_3290;
9183 efuse_data3_reg = EFUSE_DATA3_3290;
9185 efuse_ctrl_reg = EFUSE_CTRL;
9186 efuse_data0_reg = EFUSE_DATA0;
9187 efuse_data1_reg = EFUSE_DATA1;
9188 efuse_data2_reg = EFUSE_DATA2;
9189 efuse_data3_reg = EFUSE_DATA3;
9191 mutex_lock(&rt2x00dev->csr_mutex);
9193 reg = rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg);
9194 rt2x00_set_field32(®, EFUSE_CTRL_ADDRESS_IN, i);
9195 rt2x00_set_field32(®, EFUSE_CTRL_MODE, 0);
9196 rt2x00_set_field32(®, EFUSE_CTRL_KICK, 1);
9197 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
9199 /* Wait until the EEPROM has been loaded */
9200 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, ®);
9201 /* Apparently the data is read from end to start */
9202 reg = rt2800_register_read_lock(rt2x00dev, efuse_data3_reg);
9203 /* The returned value is in CPU order, but eeprom is le */
9204 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
9205 reg = rt2800_register_read_lock(rt2x00dev, efuse_data2_reg);
9206 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
9207 reg = rt2800_register_read_lock(rt2x00dev, efuse_data1_reg);
9208 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
9209 reg = rt2800_register_read_lock(rt2x00dev, efuse_data0_reg);
9210 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
9212 mutex_unlock(&rt2x00dev->csr_mutex);
9215 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
9219 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
9220 rt2800_efuse_read(rt2x00dev, i);
9224 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
9226 static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev)
9230 if (rt2x00_rt(rt2x00dev, RT3593) ||
9231 rt2x00_rt(rt2x00dev, RT3883))
9234 word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG);
9235 if ((word & 0x00ff) != 0x00ff)
9236 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
9241 static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev)
9245 if (rt2x00_rt(rt2x00dev, RT3593) ||
9246 rt2x00_rt(rt2x00dev, RT3883))
9249 word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A);
9250 if ((word & 0x00ff) != 0x00ff)
9251 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
9256 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
9258 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
9261 u8 default_lna_gain;
9267 retval = rt2800_read_eeprom(rt2x00dev);
9272 * Start validation of the data that has been read.
9274 mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
9275 rt2x00lib_set_mac_address(rt2x00dev, mac);
9277 word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
9278 if (word == 0xffff) {
9279 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
9280 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
9281 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
9282 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
9283 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
9284 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
9285 rt2x00_rt(rt2x00dev, RT2872)) {
9287 * There is a max of 2 RX streams for RT28x0 series
9289 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
9290 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
9291 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
9294 word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
9295 if (word == 0xffff) {
9296 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
9297 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
9298 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
9299 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
9300 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
9301 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
9302 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
9303 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
9304 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
9305 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
9306 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
9307 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
9308 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
9309 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
9310 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
9311 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
9312 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
9315 word = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
9316 if ((word & 0x00ff) == 0x00ff) {
9317 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
9318 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
9319 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
9321 if ((word & 0xff00) == 0xff00) {
9322 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
9323 LED_MODE_TXRX_ACTIVITY);
9324 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
9325 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
9326 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
9327 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
9328 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
9329 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
9333 * During the LNA validation we are going to use
9334 * lna0 as correct value. Note that EEPROM_LNA
9335 * is never validated.
9337 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
9338 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
9340 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG);
9341 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
9342 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
9343 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
9344 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
9345 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
9347 drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev);
9349 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
9350 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
9351 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
9352 if (!rt2x00_rt(rt2x00dev, RT3593) &&
9353 !rt2x00_rt(rt2x00dev, RT3883)) {
9354 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
9355 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
9356 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
9359 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
9361 drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev);
9363 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A);
9364 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
9365 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
9366 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
9367 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
9368 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
9370 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
9371 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
9372 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
9373 if (!rt2x00_rt(rt2x00dev, RT3593) &&
9374 !rt2x00_rt(rt2x00dev, RT3883)) {
9375 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
9376 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
9377 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
9380 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
9382 if (rt2x00_rt(rt2x00dev, RT3593) ||
9383 rt2x00_rt(rt2x00dev, RT3883)) {
9384 word = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
9385 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 ||
9386 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff)
9387 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
9389 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 ||
9390 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff)
9391 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
9393 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word);
9399 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
9406 * Read EEPROM word for configuration.
9408 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
9411 * Identify RF chipset by EEPROM value
9412 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
9413 * RT53xx: defined in "EEPROM_CHIP_ID" field
9415 if (rt2x00_rt(rt2x00dev, RT3290) ||
9416 rt2x00_rt(rt2x00dev, RT5390) ||
9417 rt2x00_rt(rt2x00dev, RT5392) ||
9418 rt2x00_rt(rt2x00dev, RT6352))
9419 rf = rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID);
9420 else if (rt2x00_rt(rt2x00dev, RT3352))
9422 else if (rt2x00_rt(rt2x00dev, RT3883))
9424 else if (rt2x00_rt(rt2x00dev, RT5350))
9427 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
9456 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
9461 rt2x00_set_rf(rt2x00dev, rf);
9464 * Identify default antenna configuration.
9466 rt2x00dev->default_ant.tx_chain_num =
9467 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
9468 rt2x00dev->default_ant.rx_chain_num =
9469 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
9471 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
9473 if (rt2x00_rt(rt2x00dev, RT3070) ||
9474 rt2x00_rt(rt2x00dev, RT3090) ||
9475 rt2x00_rt(rt2x00dev, RT3352) ||
9476 rt2x00_rt(rt2x00dev, RT3390)) {
9477 value = rt2x00_get_field16(eeprom,
9478 EEPROM_NIC_CONF1_ANT_DIVERSITY);
9483 rt2x00dev->default_ant.tx = ANTENNA_A;
9484 rt2x00dev->default_ant.rx = ANTENNA_A;
9487 rt2x00dev->default_ant.tx = ANTENNA_A;
9488 rt2x00dev->default_ant.rx = ANTENNA_B;
9492 rt2x00dev->default_ant.tx = ANTENNA_A;
9493 rt2x00dev->default_ant.rx = ANTENNA_A;
9496 /* These chips have hardware RX antenna diversity */
9497 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) ||
9498 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) {
9499 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
9500 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
9504 * Determine external LNA informations.
9506 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
9507 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
9508 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
9509 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
9512 * Detect if this device has an hardware controlled radio.
9514 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
9515 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
9518 * Detect if this device has Bluetooth co-existence.
9520 if (!rt2x00_rt(rt2x00dev, RT3352) &&
9521 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
9522 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
9525 * Read frequency offset and RF programming sequence.
9527 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
9528 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
9531 * Store led settings, for correct led behaviour.
9533 #ifdef CONFIG_RT2X00_LIB_LEDS
9534 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
9535 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
9536 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
9538 rt2x00dev->led_mcu_reg = eeprom;
9539 #endif /* CONFIG_RT2X00_LIB_LEDS */
9542 * Check if support EIRP tx power limit feature.
9544 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER);
9546 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
9547 EIRP_MAX_TX_POWER_LIMIT)
9548 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
9551 * Detect if device uses internal or external PA
9553 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
9555 if (rt2x00_rt(rt2x00dev, RT3352)) {
9556 if (rt2x00_get_field16(eeprom,
9557 EEPROM_NIC_CONF1_EXTERNAL_TX0_PA_3352))
9558 __set_bit(CAPABILITY_EXTERNAL_PA_TX0,
9559 &rt2x00dev->cap_flags);
9560 if (rt2x00_get_field16(eeprom,
9561 EEPROM_NIC_CONF1_EXTERNAL_TX1_PA_3352))
9562 __set_bit(CAPABILITY_EXTERNAL_PA_TX1,
9563 &rt2x00dev->cap_flags);
9570 * RF value list for rt28xx
9571 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
9573 static const struct rf_channel rf_vals[] = {
9574 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
9575 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
9576 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
9577 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
9578 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
9579 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
9580 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
9581 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
9582 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
9583 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
9584 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
9585 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
9586 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
9587 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
9589 /* 802.11 UNI / HyperLan 2 */
9590 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
9591 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
9592 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
9593 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
9594 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
9595 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
9596 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
9597 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
9598 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
9599 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
9600 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
9601 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
9603 /* 802.11 HyperLan 2 */
9604 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
9605 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
9606 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
9607 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
9608 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
9609 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
9610 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
9611 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
9612 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
9613 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
9614 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
9615 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
9616 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
9617 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
9618 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
9619 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
9622 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
9623 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
9624 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
9625 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
9626 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
9627 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
9628 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
9629 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
9630 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
9631 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
9632 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
9635 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
9636 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
9637 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
9638 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
9639 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
9640 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
9641 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
9645 * RF value list for rt3xxx
9646 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052 & RF3053)
9648 static const struct rf_channel rf_vals_3x[] = {
9664 /* 802.11 UNI / HyperLan 2 */
9678 /* 802.11 HyperLan 2 */
9711 * RF value list for rt3xxx with Xtal20MHz
9712 * Supports: 2.4 GHz (all) (RF3322)
9714 static const struct rf_channel rf_vals_3x_xtal20[] = {
9724 {10, 0xEB, 2, 0x14},
9725 {11, 0xEC, 2, 0x14},
9726 {12, 0xED, 2, 0x14},
9727 {13, 0xEE, 2, 0x14},
9728 {14, 0xF0, 2, 0x18},
9731 static const struct rf_channel rf_vals_3853[] = {
9791 static const struct rf_channel rf_vals_5592_xtal20[] = {
9792 /* Channel, N, K, mod, R */
9802 {10, 491, 4, 10, 3},
9803 {11, 492, 4, 10, 3},
9804 {12, 493, 4, 10, 3},
9805 {13, 494, 4, 10, 3},
9806 {14, 496, 8, 10, 3},
9807 {36, 172, 8, 12, 1},
9808 {38, 173, 0, 12, 1},
9809 {40, 173, 4, 12, 1},
9810 {42, 173, 8, 12, 1},
9811 {44, 174, 0, 12, 1},
9812 {46, 174, 4, 12, 1},
9813 {48, 174, 8, 12, 1},
9814 {50, 175, 0, 12, 1},
9815 {52, 175, 4, 12, 1},
9816 {54, 175, 8, 12, 1},
9817 {56, 176, 0, 12, 1},
9818 {58, 176, 4, 12, 1},
9819 {60, 176, 8, 12, 1},
9820 {62, 177, 0, 12, 1},
9821 {64, 177, 4, 12, 1},
9822 {100, 183, 4, 12, 1},
9823 {102, 183, 8, 12, 1},
9824 {104, 184, 0, 12, 1},
9825 {106, 184, 4, 12, 1},
9826 {108, 184, 8, 12, 1},
9827 {110, 185, 0, 12, 1},
9828 {112, 185, 4, 12, 1},
9829 {114, 185, 8, 12, 1},
9830 {116, 186, 0, 12, 1},
9831 {118, 186, 4, 12, 1},
9832 {120, 186, 8, 12, 1},
9833 {122, 187, 0, 12, 1},
9834 {124, 187, 4, 12, 1},
9835 {126, 187, 8, 12, 1},
9836 {128, 188, 0, 12, 1},
9837 {130, 188, 4, 12, 1},
9838 {132, 188, 8, 12, 1},
9839 {134, 189, 0, 12, 1},
9840 {136, 189, 4, 12, 1},
9841 {138, 189, 8, 12, 1},
9842 {140, 190, 0, 12, 1},
9843 {149, 191, 6, 12, 1},
9844 {151, 191, 10, 12, 1},
9845 {153, 192, 2, 12, 1},
9846 {155, 192, 6, 12, 1},
9847 {157, 192, 10, 12, 1},
9848 {159, 193, 2, 12, 1},
9849 {161, 193, 6, 12, 1},
9850 {165, 194, 2, 12, 1},
9851 {184, 164, 0, 12, 1},
9852 {188, 164, 4, 12, 1},
9853 {192, 165, 8, 12, 1},
9854 {196, 166, 0, 12, 1},
9857 static const struct rf_channel rf_vals_5592_xtal40[] = {
9858 /* Channel, N, K, mod, R */
9868 {10, 245, 7, 10, 3},
9869 {11, 246, 2, 10, 3},
9870 {12, 246, 7, 10, 3},
9871 {13, 247, 2, 10, 3},
9872 {14, 248, 4, 10, 3},
9876 {42, 86, 10, 12, 1},
9882 {54, 87, 10, 12, 1},
9888 {100, 91, 8, 12, 1},
9889 {102, 91, 10, 12, 1},
9890 {104, 92, 0, 12, 1},
9891 {106, 92, 2, 12, 1},
9892 {108, 92, 4, 12, 1},
9893 {110, 92, 6, 12, 1},
9894 {112, 92, 8, 12, 1},
9895 {114, 92, 10, 12, 1},
9896 {116, 93, 0, 12, 1},
9897 {118, 93, 2, 12, 1},
9898 {120, 93, 4, 12, 1},
9899 {122, 93, 6, 12, 1},
9900 {124, 93, 8, 12, 1},
9901 {126, 93, 10, 12, 1},
9902 {128, 94, 0, 12, 1},
9903 {130, 94, 2, 12, 1},
9904 {132, 94, 4, 12, 1},
9905 {134, 94, 6, 12, 1},
9906 {136, 94, 8, 12, 1},
9907 {138, 94, 10, 12, 1},
9908 {140, 95, 0, 12, 1},
9909 {149, 95, 9, 12, 1},
9910 {151, 95, 11, 12, 1},
9911 {153, 96, 1, 12, 1},
9912 {155, 96, 3, 12, 1},
9913 {157, 96, 5, 12, 1},
9914 {159, 96, 7, 12, 1},
9915 {161, 96, 9, 12, 1},
9916 {165, 97, 1, 12, 1},
9917 {184, 82, 0, 12, 1},
9918 {188, 82, 4, 12, 1},
9919 {192, 82, 8, 12, 1},
9920 {196, 83, 0, 12, 1},
9923 static const struct rf_channel rf_vals_7620[] = {
9924 {1, 0x50, 0x99, 0x99, 1},
9925 {2, 0x50, 0x44, 0x44, 2},
9926 {3, 0x50, 0xEE, 0xEE, 2},
9927 {4, 0x50, 0x99, 0x99, 3},
9928 {5, 0x51, 0x44, 0x44, 0},
9929 {6, 0x51, 0xEE, 0xEE, 0},
9930 {7, 0x51, 0x99, 0x99, 1},
9931 {8, 0x51, 0x44, 0x44, 2},
9932 {9, 0x51, 0xEE, 0xEE, 2},
9933 {10, 0x51, 0x99, 0x99, 3},
9934 {11, 0x52, 0x44, 0x44, 0},
9935 {12, 0x52, 0xEE, 0xEE, 0},
9936 {13, 0x52, 0x99, 0x99, 1},
9937 {14, 0x52, 0x33, 0x33, 3},
9940 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
9942 struct hw_mode_spec *spec = &rt2x00dev->spec;
9943 struct channel_info *info;
9944 char *default_power1;
9945 char *default_power2;
9946 char *default_power3;
9947 unsigned int i, tx_chains, rx_chains;
9951 * Disable powersaving as default.
9953 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
9956 * Change default retry settings to values corresponding more closely
9957 * to rate[0].count setting of minstrel rate control algorithm.
9959 rt2x00dev->hw->wiphy->retry_short = 2;
9960 rt2x00dev->hw->wiphy->retry_long = 2;
9963 * Initialize all hw fields.
9965 ieee80211_hw_set(rt2x00dev->hw, REPORTS_TX_ACK_STATUS);
9966 ieee80211_hw_set(rt2x00dev->hw, AMPDU_AGGREGATION);
9967 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK);
9968 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM);
9969 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS);
9972 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
9973 * unless we are capable of sending the buffered frames out after the
9974 * DTIM transmission using rt2x00lib_beacondone. This will send out
9975 * multicast and broadcast traffic immediately instead of buffering it
9976 * infinitly and thus dropping it after some time.
9978 if (!rt2x00_is_usb(rt2x00dev))
9979 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING);
9981 /* Set MFP if HW crypto is disabled. */
9982 if (rt2800_hwcrypt_disabled(rt2x00dev))
9983 ieee80211_hw_set(rt2x00dev->hw, MFP_CAPABLE);
9985 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
9986 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
9987 rt2800_eeprom_addr(rt2x00dev,
9988 EEPROM_MAC_ADDR_0));
9991 * As rt2800 has a global fallback table we cannot specify
9992 * more then one tx rate per frame but since the hw will
9993 * try several rates (based on the fallback table) we should
9994 * initialize max_report_rates to the maximum number of rates
9995 * we are going to try. Otherwise mac80211 will truncate our
9996 * reported tx rates and the rc algortihm will end up with
9999 rt2x00dev->hw->max_rates = 1;
10000 rt2x00dev->hw->max_report_rates = 7;
10001 rt2x00dev->hw->max_rate_tries = 1;
10004 * Initialize hw_mode information.
10006 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
10008 switch (rt2x00dev->chip.rf) {
10011 spec->num_channels = 14;
10012 spec->channels = rf_vals;
10017 spec->num_channels = ARRAY_SIZE(rf_vals);
10018 spec->channels = rf_vals;
10036 spec->num_channels = 14;
10037 if (rt2800_clk_is_20mhz(rt2x00dev))
10038 spec->channels = rf_vals_3x_xtal20;
10040 spec->channels = rf_vals_3x;
10044 spec->num_channels = ARRAY_SIZE(rf_vals_7620);
10045 spec->channels = rf_vals_7620;
10050 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
10051 spec->channels = rf_vals_3x;
10055 spec->num_channels = ARRAY_SIZE(rf_vals_3853);
10056 spec->channels = rf_vals_3853;
10060 reg = rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX);
10061 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
10062 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
10063 spec->channels = rf_vals_5592_xtal40;
10065 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
10066 spec->channels = rf_vals_5592_xtal20;
10071 if (WARN_ON_ONCE(!spec->channels))
10074 spec->supported_bands = SUPPORT_BAND_2GHZ;
10075 if (spec->num_channels > 14)
10076 spec->supported_bands |= SUPPORT_BAND_5GHZ;
10079 * Initialize HT information.
10081 if (!rt2x00_rf(rt2x00dev, RF2020))
10082 spec->ht.ht_supported = true;
10084 spec->ht.ht_supported = false;
10087 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
10088 IEEE80211_HT_CAP_GRN_FLD |
10089 IEEE80211_HT_CAP_SGI_20 |
10090 IEEE80211_HT_CAP_SGI_40;
10092 tx_chains = rt2x00dev->default_ant.tx_chain_num;
10093 rx_chains = rt2x00dev->default_ant.rx_chain_num;
10095 if (tx_chains >= 2)
10096 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
10098 spec->ht.cap |= rx_chains << IEEE80211_HT_CAP_RX_STBC_SHIFT;
10100 spec->ht.ampdu_factor = (rx_chains > 1) ? 3 : 2;
10101 spec->ht.ampdu_density = 4;
10102 spec->ht.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
10103 if (tx_chains != rx_chains) {
10104 spec->ht.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
10105 spec->ht.mcs.tx_params |=
10106 (tx_chains - 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
10109 switch (rx_chains) {
10111 spec->ht.mcs.rx_mask[2] = 0xff;
10114 spec->ht.mcs.rx_mask[1] = 0xff;
10117 spec->ht.mcs.rx_mask[0] = 0xff;
10118 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
10123 * Create channel information array
10125 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
10129 spec->channels_info = info;
10131 default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
10132 default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
10134 if (rt2x00dev->default_ant.tx_chain_num > 2)
10135 default_power3 = rt2800_eeprom_addr(rt2x00dev,
10136 EEPROM_EXT_TXPOWER_BG3);
10138 default_power3 = NULL;
10140 for (i = 0; i < 14; i++) {
10141 info[i].default_power1 = default_power1[i];
10142 info[i].default_power2 = default_power2[i];
10143 if (default_power3)
10144 info[i].default_power3 = default_power3[i];
10147 if (spec->num_channels > 14) {
10148 default_power1 = rt2800_eeprom_addr(rt2x00dev,
10149 EEPROM_TXPOWER_A1);
10150 default_power2 = rt2800_eeprom_addr(rt2x00dev,
10151 EEPROM_TXPOWER_A2);
10153 if (rt2x00dev->default_ant.tx_chain_num > 2)
10155 rt2800_eeprom_addr(rt2x00dev,
10156 EEPROM_EXT_TXPOWER_A3);
10158 default_power3 = NULL;
10160 for (i = 14; i < spec->num_channels; i++) {
10161 info[i].default_power1 = default_power1[i - 14];
10162 info[i].default_power2 = default_power2[i - 14];
10163 if (default_power3)
10164 info[i].default_power3 = default_power3[i - 14];
10168 switch (rt2x00dev->chip.rf) {
10188 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
10195 static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
10201 if (rt2x00_rt(rt2x00dev, RT3290))
10202 reg = rt2800_register_read(rt2x00dev, MAC_CSR0_3290);
10204 reg = rt2800_register_read(rt2x00dev, MAC_CSR0);
10206 rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET);
10207 rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION);
10228 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n",
10233 if (rt == RT5390 && rt2x00_is_soc(rt2x00dev))
10236 rt2x00_set_rt(rt2x00dev, rt, rev);
10241 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
10246 retval = rt2800_probe_rt(rt2x00dev);
10251 * Allocate eeprom data.
10253 retval = rt2800_validate_eeprom(rt2x00dev);
10257 retval = rt2800_init_eeprom(rt2x00dev);
10262 * Enable rfkill polling by setting GPIO direction of the
10263 * rfkill switch GPIO pin correctly.
10265 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
10266 rt2x00_set_field32(®, GPIO_CTRL_DIR2, 1);
10267 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
10270 * Initialize hw specifications.
10272 retval = rt2800_probe_hw_mode(rt2x00dev);
10277 * Set device capabilities.
10279 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
10280 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
10281 if (!rt2x00_is_usb(rt2x00dev))
10282 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
10285 * Set device requirements.
10287 if (!rt2x00_is_soc(rt2x00dev))
10288 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
10289 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
10290 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
10291 if (!rt2800_hwcrypt_disabled(rt2x00dev))
10292 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
10293 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
10294 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
10295 if (rt2x00_is_usb(rt2x00dev))
10296 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
10298 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
10299 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
10302 if (modparam_watchdog) {
10303 __set_bit(CAPABILITY_RESTART_HW, &rt2x00dev->cap_flags);
10304 rt2x00dev->link.watchdog_interval = msecs_to_jiffies(100);
10306 rt2x00dev->link.watchdog_disabled = true;
10310 * Set the rssi offset.
10312 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
10316 EXPORT_SYMBOL_GPL(rt2800_probe_hw);
10319 * IEEE80211 stack callback functions.
10321 void rt2800_get_key_seq(struct ieee80211_hw *hw,
10322 struct ieee80211_key_conf *key,
10323 struct ieee80211_key_seq *seq)
10325 struct rt2x00_dev *rt2x00dev = hw->priv;
10326 struct mac_iveiv_entry iveiv_entry;
10329 if (key->cipher != WLAN_CIPHER_SUITE_TKIP)
10332 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
10333 rt2800_register_multiread(rt2x00dev, offset,
10334 &iveiv_entry, sizeof(iveiv_entry));
10336 memcpy(&seq->tkip.iv16, &iveiv_entry.iv[0], 2);
10337 memcpy(&seq->tkip.iv32, &iveiv_entry.iv[4], 4);
10339 EXPORT_SYMBOL_GPL(rt2800_get_key_seq);
10341 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
10343 struct rt2x00_dev *rt2x00dev = hw->priv;
10345 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
10347 reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG);
10348 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, value);
10349 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
10351 reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG);
10352 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, enabled);
10353 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
10355 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
10356 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, enabled);
10357 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
10359 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
10360 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, enabled);
10361 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
10363 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
10364 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, enabled);
10365 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
10367 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
10368 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, enabled);
10369 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
10371 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
10372 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, enabled);
10373 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
10377 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
10379 int rt2800_conf_tx(struct ieee80211_hw *hw,
10380 struct ieee80211_vif *vif, u16 queue_idx,
10381 const struct ieee80211_tx_queue_params *params)
10383 struct rt2x00_dev *rt2x00dev = hw->priv;
10384 struct data_queue *queue;
10385 struct rt2x00_field32 field;
10391 * First pass the configuration through rt2x00lib, that will
10392 * update the queue settings and validate the input. After that
10393 * we are free to update the registers based on the value
10394 * in the queue parameter.
10396 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
10401 * We only need to perform additional register initialization
10404 if (queue_idx >= 4)
10407 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
10409 /* Update WMM TXOP register */
10410 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
10411 field.bit_offset = (queue_idx & 1) * 16;
10412 field.bit_mask = 0xffff << field.bit_offset;
10414 reg = rt2800_register_read(rt2x00dev, offset);
10415 rt2x00_set_field32(®, field, queue->txop);
10416 rt2800_register_write(rt2x00dev, offset, reg);
10418 /* Update WMM registers */
10419 field.bit_offset = queue_idx * 4;
10420 field.bit_mask = 0xf << field.bit_offset;
10422 reg = rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG);
10423 rt2x00_set_field32(®, field, queue->aifs);
10424 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
10426 reg = rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG);
10427 rt2x00_set_field32(®, field, queue->cw_min);
10428 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
10430 reg = rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG);
10431 rt2x00_set_field32(®, field, queue->cw_max);
10432 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
10434 /* Update EDCA registers */
10435 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
10437 reg = rt2800_register_read(rt2x00dev, offset);
10438 rt2x00_set_field32(®, EDCA_AC0_CFG_TX_OP, queue->txop);
10439 rt2x00_set_field32(®, EDCA_AC0_CFG_AIFSN, queue->aifs);
10440 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMIN, queue->cw_min);
10441 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMAX, queue->cw_max);
10442 rt2800_register_write(rt2x00dev, offset, reg);
10446 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
10448 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
10450 struct rt2x00_dev *rt2x00dev = hw->priv;
10454 reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW1);
10455 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
10456 reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW0);
10457 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
10461 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
10463 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
10464 struct ieee80211_ampdu_params *params)
10466 struct ieee80211_sta *sta = params->sta;
10467 enum ieee80211_ampdu_mlme_action action = params->action;
10468 u16 tid = params->tid;
10469 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
10473 * Don't allow aggregation for stations the hardware isn't aware
10474 * of because tx status reports for frames to an unknown station
10475 * always contain wcid=WCID_END+1 and thus we can't distinguish
10476 * between multiple stations which leads to unwanted situations
10477 * when the hw reorders frames due to aggregation.
10479 if (sta_priv->wcid > WCID_END)
10483 case IEEE80211_AMPDU_RX_START:
10484 case IEEE80211_AMPDU_RX_STOP:
10486 * The hw itself takes care of setting up BlockAck mechanisms.
10487 * So, we only have to allow mac80211 to nagotiate a BlockAck
10488 * agreement. Once that is done, the hw will BlockAck incoming
10489 * AMPDUs without further setup.
10492 case IEEE80211_AMPDU_TX_START:
10493 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
10495 case IEEE80211_AMPDU_TX_STOP_CONT:
10496 case IEEE80211_AMPDU_TX_STOP_FLUSH:
10497 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
10498 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
10500 case IEEE80211_AMPDU_TX_OPERATIONAL:
10503 rt2x00_warn((struct rt2x00_dev *)hw->priv,
10504 "Unknown AMPDU action\n");
10509 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
10511 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
10512 struct survey_info *survey)
10514 struct rt2x00_dev *rt2x00dev = hw->priv;
10515 struct ieee80211_conf *conf = &hw->conf;
10516 u32 idle, busy, busy_ext;
10521 survey->channel = conf->chandef.chan;
10523 idle = rt2800_register_read(rt2x00dev, CH_IDLE_STA);
10524 busy = rt2800_register_read(rt2x00dev, CH_BUSY_STA);
10525 busy_ext = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC);
10527 if (idle || busy) {
10528 survey->filled = SURVEY_INFO_TIME |
10529 SURVEY_INFO_TIME_BUSY |
10530 SURVEY_INFO_TIME_EXT_BUSY;
10532 survey->time = (idle + busy) / 1000;
10533 survey->time_busy = busy / 1000;
10534 survey->time_ext_busy = busy_ext / 1000;
10537 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
10538 survey->filled |= SURVEY_INFO_IN_USE;
10543 EXPORT_SYMBOL_GPL(rt2800_get_survey);
10545 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
10546 MODULE_VERSION(DRV_VERSION);
10547 MODULE_DESCRIPTION("Ralink RT2800 library");
10548 MODULE_LICENSE("GPL");