2 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/delay.h>
19 #include "mt76x2_eeprom.h"
20 #include "mt76x2_mcu.h"
22 struct mt76x2_reg_pair {
28 mt76x2_wait_for_mac(struct mt76x2_dev *dev)
32 for (i = 0; i < 500; i++) {
33 switch (mt76_rr(dev, MT_MAC_CSR0)) {
40 usleep_range(5000, 10000);
47 wait_for_wpdma(struct mt76x2_dev *dev)
49 return mt76_poll(dev, MT_WPDMA_GLO_CFG,
50 MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
51 MT_WPDMA_GLO_CFG_RX_DMA_BUSY,
56 mt76x2_mac_pbf_init(struct mt76x2_dev *dev)
60 val = MT_PBF_SYS_CTRL_MCU_RESET |
61 MT_PBF_SYS_CTRL_DMA_RESET |
62 MT_PBF_SYS_CTRL_MAC_RESET |
63 MT_PBF_SYS_CTRL_PBF_RESET |
64 MT_PBF_SYS_CTRL_ASY_RESET;
66 mt76_set(dev, MT_PBF_SYS_CTRL, val);
67 mt76_clear(dev, MT_PBF_SYS_CTRL, val);
69 mt76_wr(dev, MT_PBF_TX_MAX_PCNT, 0xefef3f1f);
70 mt76_wr(dev, MT_PBF_RX_MAX_PCNT, 0xfebf);
74 mt76x2_write_reg_pairs(struct mt76x2_dev *dev,
75 const struct mt76x2_reg_pair *data, int len)
78 mt76_wr(dev, data->reg, data->value);
85 mt76_write_mac_initvals(struct mt76x2_dev *dev)
87 #define DEFAULT_PROT_CFG \
88 (FIELD_PREP(MT_PROT_CFG_RATE, 0x2004) | \
89 FIELD_PREP(MT_PROT_CFG_NAV, 1) | \
90 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f) | \
91 MT_PROT_CFG_RTS_THRESH)
93 #define DEFAULT_PROT_CFG_20 \
94 (FIELD_PREP(MT_PROT_CFG_RATE, 0x2004) | \
95 FIELD_PREP(MT_PROT_CFG_CTRL, 1) | \
96 FIELD_PREP(MT_PROT_CFG_NAV, 1) | \
97 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x17))
99 #define DEFAULT_PROT_CFG_40 \
100 (FIELD_PREP(MT_PROT_CFG_RATE, 0x2084) | \
101 FIELD_PREP(MT_PROT_CFG_CTRL, 1) | \
102 FIELD_PREP(MT_PROT_CFG_NAV, 1) | \
103 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f))
105 static const struct mt76x2_reg_pair vals[] = {
106 /* Copied from MediaTek reference source */
107 { MT_PBF_SYS_CTRL, 0x00080c00 },
108 { MT_PBF_CFG, 0x1efebcff },
109 { MT_FCE_PSE_CTRL, 0x00000001 },
110 { MT_MAC_SYS_CTRL, 0x0000000c },
111 { MT_MAX_LEN_CFG, 0x003e3f00 },
112 { MT_AMPDU_MAX_LEN_20M1S, 0xaaa99887 },
113 { MT_AMPDU_MAX_LEN_20M2S, 0x000000aa },
114 { MT_XIFS_TIME_CFG, 0x33a40d0a },
115 { MT_BKOFF_SLOT_CFG, 0x00000209 },
116 { MT_TBTT_SYNC_CFG, 0x00422010 },
117 { MT_PWR_PIN_CFG, 0x00000000 },
118 { 0x1238, 0x001700c8 },
119 { MT_TX_SW_CFG0, 0x00101001 },
120 { MT_TX_SW_CFG1, 0x00010000 },
121 { MT_TX_SW_CFG2, 0x00000000 },
122 { MT_TXOP_CTRL_CFG, 0x0400583f },
123 { MT_TX_RTS_CFG, 0x00100020 },
124 { MT_TX_TIMEOUT_CFG, 0x000a2290 },
125 { MT_TX_RETRY_CFG, 0x47f01f0f },
126 { MT_EXP_ACK_TIME, 0x002c00dc },
127 { MT_TX_PROT_CFG6, 0xe3f42004 },
128 { MT_TX_PROT_CFG7, 0xe3f42084 },
129 { MT_TX_PROT_CFG8, 0xe3f42104 },
130 { MT_PIFS_TX_CFG, 0x00060fff },
131 { MT_RX_FILTR_CFG, 0x00015f97 },
132 { MT_LEGACY_BASIC_RATE, 0x0000017f },
133 { MT_HT_BASIC_RATE, 0x00004003 },
134 { MT_PN_PAD_MODE, 0x00000003 },
135 { MT_TXOP_HLDR_ET, 0x00000002 },
136 { 0xa44, 0x00000000 },
137 { MT_HEADER_TRANS_CTRL_REG, 0x00000000 },
138 { MT_TSO_CTRL, 0x00000000 },
139 { MT_AUX_CLK_CFG, 0x00000000 },
140 { MT_DACCLK_EN_DLY_CFG, 0x00000000 },
141 { MT_TX_ALC_CFG_4, 0x00000000 },
142 { MT_TX_ALC_VGA3, 0x00000000 },
143 { MT_TX_PWR_CFG_0, 0x3a3a3a3a },
144 { MT_TX_PWR_CFG_1, 0x3a3a3a3a },
145 { MT_TX_PWR_CFG_2, 0x3a3a3a3a },
146 { MT_TX_PWR_CFG_3, 0x3a3a3a3a },
147 { MT_TX_PWR_CFG_4, 0x3a3a3a3a },
148 { MT_TX_PWR_CFG_7, 0x3a3a3a3a },
149 { MT_TX_PWR_CFG_8, 0x0000003a },
150 { MT_TX_PWR_CFG_9, 0x0000003a },
151 { MT_EFUSE_CTRL, 0x0000d000 },
152 { MT_PAUSE_ENABLE_CONTROL1, 0x0000000a },
153 { MT_FCE_WLAN_FLOW_CONTROL1, 0x60401c18 },
154 { MT_WPDMA_DELAY_INT_CFG, 0x94ff0000 },
155 { MT_TX_SW_CFG3, 0x00000004 },
156 { MT_HT_FBK_TO_LEGACY, 0x00001818 },
157 { MT_VHT_HT_FBK_CFG1, 0xedcba980 },
158 { MT_PROT_AUTO_TX_CFG, 0x00830083 },
159 { MT_HT_CTRL_CFG, 0x000001ff },
161 struct mt76x2_reg_pair prot_vals[] = {
162 { MT_CCK_PROT_CFG, DEFAULT_PROT_CFG },
163 { MT_OFDM_PROT_CFG, DEFAULT_PROT_CFG },
164 { MT_MM20_PROT_CFG, DEFAULT_PROT_CFG_20 },
165 { MT_MM40_PROT_CFG, DEFAULT_PROT_CFG_40 },
166 { MT_GF20_PROT_CFG, DEFAULT_PROT_CFG_20 },
167 { MT_GF40_PROT_CFG, DEFAULT_PROT_CFG_40 },
170 mt76x2_write_reg_pairs(dev, vals, ARRAY_SIZE(vals));
171 mt76x2_write_reg_pairs(dev, prot_vals, ARRAY_SIZE(prot_vals));
175 mt76x2_fixup_xtal(struct mt76x2_dev *dev)
180 eep_val = mt76x2_eeprom_get(dev, MT_EE_XTAL_TRIM_2);
182 offset = eep_val & 0x7f;
183 if ((eep_val & 0xff) == 0xff)
185 else if (eep_val & 0x80)
189 if (eep_val == 0x00 || eep_val == 0xff) {
190 eep_val = mt76x2_eeprom_get(dev, MT_EE_XTAL_TRIM_1);
193 if (eep_val == 0x00 || eep_val == 0xff)
198 mt76_rmw_field(dev, MT_XO_CTRL5, MT_XO_CTRL5_C2_VAL, eep_val + offset);
199 mt76_set(dev, MT_XO_CTRL6, MT_XO_CTRL6_C2_CTRL);
201 eep_val = mt76x2_eeprom_get(dev, MT_EE_NIC_CONF_2);
202 switch (FIELD_GET(MT_EE_NIC_CONF_2_XTAL_OPTION, eep_val)) {
204 mt76_wr(dev, MT_XO_CTRL7, 0x5c1fee80);
207 mt76_wr(dev, MT_XO_CTRL7, 0x5c1feed0);
215 mt76x2_init_beacon_offsets(struct mt76x2_dev *dev)
217 u16 base = MT_BEACON_BASE;
221 for (i = 0; i < 16; i++) {
222 u16 addr = dev->beacon_offsets[i];
224 regs[i / 4] |= ((addr - base) / 64) << (8 * (i % 4));
227 for (i = 0; i < 4; i++)
228 mt76_wr(dev, MT_BCN_OFFSET(i), regs[i]);
231 int mt76x2_mac_reset(struct mt76x2_dev *dev, bool hard)
233 static const u8 null_addr[ETH_ALEN] = {};
234 const u8 *macaddr = dev->mt76.macaddr;
238 if (!mt76x2_wait_for_mac(dev))
241 val = mt76_rr(dev, MT_WPDMA_GLO_CFG);
243 val &= ~(MT_WPDMA_GLO_CFG_TX_DMA_EN |
244 MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
245 MT_WPDMA_GLO_CFG_RX_DMA_EN |
246 MT_WPDMA_GLO_CFG_RX_DMA_BUSY |
247 MT_WPDMA_GLO_CFG_DMA_BURST_SIZE);
248 val |= FIELD_PREP(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3);
250 mt76_wr(dev, MT_WPDMA_GLO_CFG, val);
252 mt76x2_mac_pbf_init(dev);
253 mt76_write_mac_initvals(dev);
254 mt76x2_fixup_xtal(dev);
256 mt76_clear(dev, MT_MAC_SYS_CTRL,
257 MT_MAC_SYS_CTRL_RESET_CSR |
258 MT_MAC_SYS_CTRL_RESET_BBP);
261 mt76_clear(dev, MT_COEXCFG0, MT_COEXCFG0_COEX_EN);
263 mt76_set(dev, MT_EXT_CCA_CFG, 0x0000f000);
264 mt76_clear(dev, MT_TX_ALC_CFG_4, BIT(31));
266 mt76_wr(dev, MT_RF_BYPASS_0, 0x06000000);
267 mt76_wr(dev, MT_RF_SETTING_0, 0x08800000);
268 usleep_range(5000, 10000);
269 mt76_wr(dev, MT_RF_BYPASS_0, 0x00000000);
271 mt76_wr(dev, MT_MCU_CLOCK_CTL, 0x1401);
272 mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN);
274 mt76_wr(dev, MT_MAC_ADDR_DW0, get_unaligned_le32(macaddr));
275 mt76_wr(dev, MT_MAC_ADDR_DW1, get_unaligned_le16(macaddr + 4));
277 mt76_wr(dev, MT_MAC_BSSID_DW0, get_unaligned_le32(macaddr));
278 mt76_wr(dev, MT_MAC_BSSID_DW1, get_unaligned_le16(macaddr + 4) |
279 FIELD_PREP(MT_MAC_BSSID_DW1_MBSS_MODE, 3) | /* 8 beacons */
280 MT_MAC_BSSID_DW1_MBSS_LOCAL_BIT);
282 /* Fire a pre-TBTT interrupt 8 ms before TBTT */
283 mt76_rmw_field(dev, MT_INT_TIMER_CFG, MT_INT_TIMER_CFG_PRE_TBTT,
285 mt76_rmw_field(dev, MT_INT_TIMER_CFG, MT_INT_TIMER_CFG_GP_TIMER,
287 mt76_wr(dev, MT_INT_TIMER_EN, 0);
289 mt76_wr(dev, MT_BCN_BYPASS_MASK, 0xffff);
293 for (i = 0; i < 256 / 32; i++)
294 mt76_wr(dev, MT_WCID_DROP_BASE + i * 4, 0);
296 for (i = 0; i < 256; i++)
297 mt76x2_mac_wcid_setup(dev, i, 0, NULL);
299 for (i = 0; i < 16; i++)
300 for (k = 0; k < 4; k++)
301 mt76x2_mac_shared_key_setup(dev, i, k, NULL);
303 for (i = 0; i < 8; i++) {
304 mt76x2_mac_set_bssid(dev, i, null_addr);
305 mt76x2_mac_set_beacon(dev, i, NULL);
308 for (i = 0; i < 16; i++)
309 mt76_rr(dev, MT_TX_STAT_FIFO);
311 mt76_wr(dev, MT_CH_TIME_CFG,
312 MT_CH_TIME_CFG_TIMER_EN |
313 MT_CH_TIME_CFG_TX_AS_BUSY |
314 MT_CH_TIME_CFG_RX_AS_BUSY |
315 MT_CH_TIME_CFG_NAV_AS_BUSY |
316 MT_CH_TIME_CFG_EIFS_AS_BUSY |
317 FIELD_PREP(MT_CH_TIME_CFG_CH_TIMER_CLR, 1));
319 mt76x2_init_beacon_offsets(dev);
321 mt76x2_set_tx_ackto(dev);
326 int mt76x2_mac_start(struct mt76x2_dev *dev)
330 for (i = 0; i < 16; i++)
331 mt76_rr(dev, MT_TX_AGG_CNT(i));
333 for (i = 0; i < 16; i++)
334 mt76_rr(dev, MT_TX_STAT_FIFO);
336 memset(dev->aggr_stats, 0, sizeof(dev->aggr_stats));
338 mt76_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX);
340 usleep_range(50, 100);
342 mt76_set(dev, MT_WPDMA_GLO_CFG,
343 MT_WPDMA_GLO_CFG_TX_DMA_EN |
344 MT_WPDMA_GLO_CFG_RX_DMA_EN);
346 mt76_clear(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE);
348 mt76_wr(dev, MT_RX_FILTR_CFG, dev->rxfilter);
350 mt76_wr(dev, MT_MAC_SYS_CTRL,
351 MT_MAC_SYS_CTRL_ENABLE_TX |
352 MT_MAC_SYS_CTRL_ENABLE_RX);
354 mt76x2_irq_enable(dev, MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL |
360 void mt76x2_mac_stop(struct mt76x2_dev *dev, bool force)
362 bool stopped = false;
366 mt76_wr(dev, MT_MAC_SYS_CTRL, 0);
368 rts_cfg = mt76_rr(dev, MT_TX_RTS_CFG);
369 mt76_wr(dev, MT_TX_RTS_CFG, rts_cfg & ~MT_TX_RTS_CFG_RETRY_LIMIT);
371 /* Wait for MAC to become idle */
372 for (i = 0; i < 300; i++) {
373 if (mt76_rr(dev, MT_MAC_STATUS) &
374 (MT_MAC_STATUS_RX | MT_MAC_STATUS_TX))
377 if (mt76_rr(dev, MT_BBP(IBI, 12)))
384 if (force && !stopped) {
385 mt76_set(dev, MT_BBP(CORE, 4), BIT(1));
386 mt76_clear(dev, MT_BBP(CORE, 4), BIT(1));
388 mt76_set(dev, MT_BBP(CORE, 4), BIT(0));
389 mt76_clear(dev, MT_BBP(CORE, 4), BIT(0));
392 mt76_wr(dev, MT_TX_RTS_CFG, rts_cfg);
395 void mt76x2_mac_resume(struct mt76x2_dev *dev)
397 mt76_wr(dev, MT_MAC_SYS_CTRL,
398 MT_MAC_SYS_CTRL_ENABLE_TX |
399 MT_MAC_SYS_CTRL_ENABLE_RX);
403 mt76x2_power_on_rf_patch(struct mt76x2_dev *dev)
405 mt76_set(dev, 0x10130, BIT(0) | BIT(16));
408 mt76_clear(dev, 0x1001c, 0xff);
409 mt76_set(dev, 0x1001c, 0x30);
411 mt76_wr(dev, 0x10014, 0x484f);
414 mt76_set(dev, 0x10130, BIT(17));
417 mt76_clear(dev, 0x10130, BIT(16));
420 mt76_set(dev, 0x1014c, BIT(19) | BIT(20));
424 mt76x2_power_on_rf(struct mt76x2_dev *dev, int unit)
426 int shift = unit ? 8 : 0;
429 mt76_set(dev, 0x10130, BIT(0) << shift);
432 /* Enable RFDIG LDO/AFE/ABB/ADDA */
433 mt76_set(dev, 0x10130, (BIT(1) | BIT(3) | BIT(4) | BIT(5)) << shift);
436 /* Switch RFDIG power to internal LDO */
437 mt76_clear(dev, 0x10130, BIT(2) << shift);
440 mt76x2_power_on_rf_patch(dev);
442 mt76_set(dev, 0x530, 0xf);
446 mt76x2_power_on(struct mt76x2_dev *dev)
450 /* Turn on WL MTCMOS */
451 mt76_set(dev, MT_WLAN_MTC_CTRL, MT_WLAN_MTC_CTRL_MTCMOS_PWR_UP);
453 val = MT_WLAN_MTC_CTRL_STATE_UP |
454 MT_WLAN_MTC_CTRL_PWR_ACK |
455 MT_WLAN_MTC_CTRL_PWR_ACK_S;
457 mt76_poll(dev, MT_WLAN_MTC_CTRL, val, val, 1000);
459 mt76_clear(dev, MT_WLAN_MTC_CTRL, 0x7f << 16);
462 mt76_clear(dev, MT_WLAN_MTC_CTRL, 0xf << 24);
465 mt76_set(dev, MT_WLAN_MTC_CTRL, 0xf << 24);
466 mt76_clear(dev, MT_WLAN_MTC_CTRL, 0xfff);
468 /* Turn on AD/DA power down */
469 mt76_clear(dev, 0x11204, BIT(3));
471 /* WLAN function enable */
472 mt76_set(dev, 0x10080, BIT(0));
474 /* Release BBP software reset */
475 mt76_clear(dev, 0x10064, BIT(18));
477 mt76x2_power_on_rf(dev, 0);
478 mt76x2_power_on_rf(dev, 1);
481 void mt76x2_set_tx_ackto(struct mt76x2_dev *dev)
483 u8 ackto, sifs, slottime = dev->slottime;
485 slottime += 3 * dev->coverage_class;
487 sifs = mt76_get_field(dev, MT_XIFS_TIME_CFG,
488 MT_XIFS_TIME_CFG_OFDM_SIFS);
490 ackto = slottime + sifs;
491 mt76_rmw_field(dev, MT_TX_TIMEOUT_CFG,
492 MT_TX_TIMEOUT_CFG_ACKTO, ackto);
496 mt76x2_set_wlan_state(struct mt76x2_dev *dev, bool enable)
498 u32 val = mt76_rr(dev, MT_WLAN_FUN_CTRL);
501 val |= (MT_WLAN_FUN_CTRL_WLAN_EN |
502 MT_WLAN_FUN_CTRL_WLAN_CLK_EN);
504 val &= ~(MT_WLAN_FUN_CTRL_WLAN_EN |
505 MT_WLAN_FUN_CTRL_WLAN_CLK_EN);
507 mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
512 mt76x2_reset_wlan(struct mt76x2_dev *dev, bool enable)
516 val = mt76_rr(dev, MT_WLAN_FUN_CTRL);
518 val &= ~MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL;
520 if (val & MT_WLAN_FUN_CTRL_WLAN_EN) {
521 val |= MT_WLAN_FUN_CTRL_WLAN_RESET_RF;
522 mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
525 val &= ~MT_WLAN_FUN_CTRL_WLAN_RESET_RF;
528 mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
531 mt76x2_set_wlan_state(dev, enable);
534 int mt76x2_init_hardware(struct mt76x2_dev *dev)
536 static const u16 beacon_offsets[16] = {
537 /* 1024 byte per beacon */
547 /* BSS idx 8-15 not used for beacons */
560 dev->beacon_offsets = beacon_offsets;
561 tasklet_init(&dev->pre_tbtt_tasklet, mt76x2_pre_tbtt_tasklet,
562 (unsigned long) dev);
564 dev->chainmask = 0x202;
565 dev->global_wcid.idx = 255;
566 dev->global_wcid.hw_key_idx = -1;
569 val = mt76_rr(dev, MT_WPDMA_GLO_CFG);
570 val &= MT_WPDMA_GLO_CFG_DMA_BURST_SIZE |
571 MT_WPDMA_GLO_CFG_BIG_ENDIAN |
572 MT_WPDMA_GLO_CFG_HDR_SEG_LEN;
573 val |= MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE;
574 mt76_wr(dev, MT_WPDMA_GLO_CFG, val);
576 mt76x2_reset_wlan(dev, true);
577 mt76x2_power_on(dev);
579 ret = mt76x2_eeprom_init(dev);
583 ret = mt76x2_mac_reset(dev, true);
587 dev->rxfilter = mt76_rr(dev, MT_RX_FILTR_CFG);
589 ret = mt76x2_dma_init(dev);
593 set_bit(MT76_STATE_INITIALIZED, &dev->mt76.state);
594 ret = mt76x2_mac_start(dev);
598 ret = mt76x2_mcu_init(dev);
602 mt76x2_mac_stop(dev, false);
607 void mt76x2_stop_hardware(struct mt76x2_dev *dev)
609 cancel_delayed_work_sync(&dev->cal_work);
610 cancel_delayed_work_sync(&dev->mac_work);
611 mt76x2_mcu_set_radio_state(dev, false);
612 mt76x2_mac_stop(dev, false);
615 void mt76x2_cleanup(struct mt76x2_dev *dev)
617 tasklet_disable(&dev->dfs_pd.dfs_tasklet);
618 tasklet_disable(&dev->pre_tbtt_tasklet);
619 mt76x2_stop_hardware(dev);
620 mt76x2_dma_cleanup(dev);
621 mt76x2_mcu_cleanup(dev);
624 struct mt76x2_dev *mt76x2_alloc_device(struct device *pdev)
626 static const struct mt76_driver_ops drv_ops = {
627 .txwi_size = sizeof(struct mt76x2_txwi),
628 .update_survey = mt76x2_update_channel,
629 .tx_prepare_skb = mt76x2_tx_prepare_skb,
630 .tx_complete_skb = mt76x2_tx_complete_skb,
631 .rx_skb = mt76x2_queue_rx_skb,
632 .rx_poll_complete = mt76x2_rx_poll_complete,
633 .sta_ps = mt76x2_sta_ps,
635 struct ieee80211_hw *hw;
636 struct mt76x2_dev *dev;
638 hw = ieee80211_alloc_hw(sizeof(*dev), &mt76x2_ops);
643 dev->mt76.dev = pdev;
645 dev->mt76.drv = &drv_ops;
646 mutex_init(&dev->mutex);
647 spin_lock_init(&dev->irq_lock);
652 static void mt76x2_regd_notifier(struct wiphy *wiphy,
653 struct regulatory_request *request)
655 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
656 struct mt76x2_dev *dev = hw->priv;
658 mt76x2_dfs_set_domain(dev, request->dfs_region);
661 #define CCK_RATE(_idx, _rate) { \
663 .flags = IEEE80211_RATE_SHORT_PREAMBLE, \
664 .hw_value = (MT_PHY_TYPE_CCK << 8) | _idx, \
665 .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (8 + _idx), \
668 #define OFDM_RATE(_idx, _rate) { \
670 .hw_value = (MT_PHY_TYPE_OFDM << 8) | _idx, \
671 .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | _idx, \
674 static struct ieee80211_rate mt76x2_rates[] = {
689 static const struct ieee80211_iface_limit if_limits[] = {
692 .types = BIT(NL80211_IFTYPE_ADHOC)
695 .types = BIT(NL80211_IFTYPE_STATION) |
696 #ifdef CONFIG_MAC80211_MESH
697 BIT(NL80211_IFTYPE_MESH_POINT) |
699 BIT(NL80211_IFTYPE_AP)
703 static const struct ieee80211_iface_combination if_comb[] = {
706 .n_limits = ARRAY_SIZE(if_limits),
708 .num_different_channels = 1,
709 .beacon_int_infra_match = true,
710 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) |
711 BIT(NL80211_CHAN_WIDTH_20) |
712 BIT(NL80211_CHAN_WIDTH_40) |
713 BIT(NL80211_CHAN_WIDTH_80),
717 static void mt76x2_led_set_config(struct mt76_dev *mt76, u8 delay_on,
720 struct mt76x2_dev *dev = container_of(mt76, struct mt76x2_dev,
724 val = MT_LED_STATUS_DURATION(0xff) |
725 MT_LED_STATUS_OFF(delay_off) |
726 MT_LED_STATUS_ON(delay_on);
728 mt76_wr(dev, MT_LED_S0(mt76->led_pin), val);
729 mt76_wr(dev, MT_LED_S1(mt76->led_pin), val);
731 val = MT_LED_CTRL_REPLAY(mt76->led_pin) |
732 MT_LED_CTRL_KICK(mt76->led_pin);
734 val |= MT_LED_CTRL_POLARITY(mt76->led_pin);
735 mt76_wr(dev, MT_LED_CTRL, val);
738 static int mt76x2_led_set_blink(struct led_classdev *led_cdev,
739 unsigned long *delay_on,
740 unsigned long *delay_off)
742 struct mt76_dev *mt76 = container_of(led_cdev, struct mt76_dev,
744 u8 delta_on, delta_off;
746 delta_off = max_t(u8, *delay_off / 10, 1);
747 delta_on = max_t(u8, *delay_on / 10, 1);
749 mt76x2_led_set_config(mt76, delta_on, delta_off);
753 static void mt76x2_led_set_brightness(struct led_classdev *led_cdev,
754 enum led_brightness brightness)
756 struct mt76_dev *mt76 = container_of(led_cdev, struct mt76_dev,
760 mt76x2_led_set_config(mt76, 0, 0xff);
762 mt76x2_led_set_config(mt76, 0xff, 0);
766 mt76x2_init_txpower(struct mt76x2_dev *dev,
767 struct ieee80211_supported_band *sband)
769 struct ieee80211_channel *chan;
770 struct mt76x2_tx_power_info txp;
771 struct mt76_rate_power t = {};
775 for (i = 0; i < sband->n_channels; i++) {
776 chan = &sband->channels[i];
778 mt76x2_get_power_info(dev, &txp, chan);
780 target_power = max_t(int, (txp.chain[0].target_power +
782 (txp.chain[1].target_power +
783 txp.chain[1].delta));
785 mt76x2_get_rate_power(dev, &t, chan);
787 chan->max_power = mt76x2_get_max_rate_power(&t) +
789 chan->max_power /= 2;
791 /* convert to combined output power on 2x2 devices */
792 chan->max_power += 3;
796 int mt76x2_register_device(struct mt76x2_dev *dev)
798 struct ieee80211_hw *hw = mt76_hw(dev);
799 struct wiphy *wiphy = hw->wiphy;
804 fifo_size = roundup_pow_of_two(32 * sizeof(struct mt76x2_tx_status));
805 status_fifo = devm_kzalloc(dev->mt76.dev, fifo_size, GFP_KERNEL);
809 kfifo_init(&dev->txstatus_fifo, status_fifo, fifo_size);
811 ret = mt76x2_init_hardware(dev);
817 hw->max_report_rates = 7;
818 hw->max_rate_tries = 1;
819 hw->extra_tx_headroom = 2;
821 hw->sta_data_size = sizeof(struct mt76x2_sta);
822 hw->vif_data_size = sizeof(struct mt76x2_vif);
824 for (i = 0; i < ARRAY_SIZE(dev->macaddr_list); i++) {
825 u8 *addr = dev->macaddr_list[i].addr;
827 memcpy(addr, dev->mt76.macaddr, ETH_ALEN);
833 addr[0] ^= ((i - 1) << 2);
835 wiphy->addresses = dev->macaddr_list;
836 wiphy->n_addresses = ARRAY_SIZE(dev->macaddr_list);
838 wiphy->iface_combinations = if_comb;
839 wiphy->n_iface_combinations = ARRAY_SIZE(if_comb);
841 wiphy->reg_notifier = mt76x2_regd_notifier;
843 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS);
845 ieee80211_hw_set(hw, SUPPORTS_HT_CCK_RATES);
846 ieee80211_hw_set(hw, SUPPORTS_REORDERING_BUFFER);
848 INIT_DELAYED_WORK(&dev->cal_work, mt76x2_phy_calibrate);
849 INIT_DELAYED_WORK(&dev->mac_work, mt76x2_mac_work);
851 dev->mt76.sband_2g.sband.ht_cap.cap |= IEEE80211_HT_CAP_LDPC_CODING;
852 dev->mt76.sband_5g.sband.ht_cap.cap |= IEEE80211_HT_CAP_LDPC_CODING;
854 mt76x2_dfs_init_detector(dev);
856 /* init led callbacks */
857 dev->mt76.led_cdev.brightness_set = mt76x2_led_set_brightness;
858 dev->mt76.led_cdev.blink_set = mt76x2_led_set_blink;
860 ret = mt76_register_device(&dev->mt76, true, mt76x2_rates,
861 ARRAY_SIZE(mt76x2_rates));
865 mt76x2_init_debugfs(dev);
866 mt76x2_init_txpower(dev, &dev->mt76.sband_2g.sband);
867 mt76x2_init_txpower(dev, &dev->mt76.sband_5g.sband);
872 mt76x2_stop_hardware(dev);