2 * Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 static void mt76x2u_mac_reset_counters(struct mt76x02_dev *dev)
22 mt76_rr(dev, MT_RX_STAT_0);
23 mt76_rr(dev, MT_RX_STAT_1);
24 mt76_rr(dev, MT_RX_STAT_2);
25 mt76_rr(dev, MT_TX_STA_0);
26 mt76_rr(dev, MT_TX_STA_1);
27 mt76_rr(dev, MT_TX_STA_2);
30 static void mt76x2u_mac_fixup_xtal(struct mt76x02_dev *dev)
35 eep_val = mt76x02_eeprom_get(dev, MT_EE_XTAL_TRIM_2);
37 offset = eep_val & 0x7f;
38 if ((eep_val & 0xff) == 0xff)
40 else if (eep_val & 0x80)
44 if (eep_val == 0x00 || eep_val == 0xff) {
45 eep_val = mt76x02_eeprom_get(dev, MT_EE_XTAL_TRIM_1);
48 if (eep_val == 0x00 || eep_val == 0xff)
53 mt76_rmw_field(dev, MT_VEND_ADDR(CFG, MT_XO_CTRL5),
54 MT_XO_CTRL5_C2_VAL, eep_val + offset);
55 mt76_set(dev, MT_VEND_ADDR(CFG, MT_XO_CTRL6), MT_XO_CTRL6_C2_CTRL);
57 mt76_wr(dev, 0x504, 0x06000000);
58 mt76_wr(dev, 0x50c, 0x08800000);
60 mt76_wr(dev, 0x504, 0x0);
62 /* decrease SIFS from 16us to 13us */
63 mt76_rmw_field(dev, MT_XIFS_TIME_CFG,
64 MT_XIFS_TIME_CFG_OFDM_SIFS, 0xd);
65 mt76_rmw_field(dev, MT_BKOFF_SLOT_CFG, MT_BKOFF_SLOT_CFG_CC_DELAY, 1);
68 mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN);
70 eep_val = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_2);
71 switch (FIELD_GET(MT_EE_NIC_CONF_2_XTAL_OPTION, eep_val)) {
73 mt76_wr(dev, MT_XO_CTRL7, 0x5c1fee80);
76 mt76_wr(dev, MT_XO_CTRL7, 0x5c1feed0);
83 int mt76x2u_mac_reset(struct mt76x02_dev *dev)
85 mt76_wr(dev, MT_WPDMA_GLO_CFG, BIT(4) | BIT(5));
88 mt76_wr(dev, MT_PBF_TX_MAX_PCNT, 0xefef3f1f);
89 mt76_wr(dev, MT_PBF_RX_MAX_PCNT, 0xfebf);
91 mt76_write_mac_initvals(dev);
93 mt76_wr(dev, MT_TX_LINK_CFG, 0x1020);
94 mt76_wr(dev, MT_AUTO_RSP_CFG, 0x13);
95 mt76_wr(dev, MT_MAX_LEN_CFG, 0x2f00);
96 mt76_wr(dev, MT_TX_RTS_CFG, 0x92b20);
98 mt76_wr(dev, MT_WMM_AIFSN, 0x2273);
99 mt76_wr(dev, MT_WMM_CWMIN, 0x2344);
100 mt76_wr(dev, MT_WMM_CWMAX, 0x34aa);
102 mt76_clear(dev, MT_MAC_SYS_CTRL,
103 MT_MAC_SYS_CTRL_RESET_CSR |
104 MT_MAC_SYS_CTRL_RESET_BBP);
107 mt76_clear(dev, MT_COEXCFG0, MT_COEXCFG0_COEX_EN);
109 mt76_set(dev, MT_EXT_CCA_CFG, 0xf000);
110 mt76_clear(dev, MT_TX_ALC_CFG_4, BIT(31));
112 mt76x2u_mac_fixup_xtal(dev);
117 int mt76x2u_mac_start(struct mt76x02_dev *dev)
119 mt76x2u_mac_reset_counters(dev);
121 mt76_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX);
122 mt76x02_wait_for_wpdma(&dev->mt76, 1000);
123 usleep_range(50, 100);
125 mt76_wr(dev, MT_RX_FILTR_CFG, dev->mt76.rxfilter);
127 mt76_wr(dev, MT_MAC_SYS_CTRL,
128 MT_MAC_SYS_CTRL_ENABLE_TX |
129 MT_MAC_SYS_CTRL_ENABLE_RX);
134 int mt76x2u_mac_stop(struct mt76x02_dev *dev)
136 int i, count = 0, val;
137 bool stopped = false;
140 if (test_bit(MT76_REMOVED, &dev->mt76.state))
143 rts_cfg = mt76_rr(dev, MT_TX_RTS_CFG);
144 mt76_wr(dev, MT_TX_RTS_CFG, rts_cfg & ~MT_TX_RTS_CFG_RETRY_LIMIT);
146 mt76_clear(dev, MT_TXOP_CTRL_CFG, BIT(20));
147 mt76_clear(dev, MT_TXOP_HLDR_ET, BIT(1));
149 /* wait tx dma to stop */
150 for (i = 0; i < 2000; i++) {
151 val = mt76_rr(dev, MT_VEND_ADDR(CFG, MT_USB_U3DMA_CFG));
152 if (!(val & MT_USB_DMA_CFG_TX_BUSY) && i > 10)
154 usleep_range(50, 100);
157 /* page count on TxQ */
158 for (i = 0; i < 200; i++) {
159 if (!(mt76_rr(dev, 0x0438) & 0xffffffff) &&
160 !(mt76_rr(dev, 0x0a30) & 0x000000ff) &&
161 !(mt76_rr(dev, 0x0a34) & 0xff00ff00))
163 usleep_range(10, 20);
167 mt76_clear(dev, MT_MAC_SYS_CTRL,
168 MT_MAC_SYS_CTRL_ENABLE_RX |
169 MT_MAC_SYS_CTRL_ENABLE_TX);
171 /* Wait for MAC to become idle */
172 for (i = 0; i < 1000; i++) {
173 if (!(mt76_rr(dev, MT_MAC_STATUS) & MT_MAC_STATUS_TX) &&
174 !mt76_rr(dev, MT_BBP(IBI, 12))) {
178 usleep_range(10, 20);
182 mt76_set(dev, MT_BBP(CORE, 4), BIT(1));
183 mt76_clear(dev, MT_BBP(CORE, 4), BIT(1));
185 mt76_set(dev, MT_BBP(CORE, 4), BIT(0));
186 mt76_clear(dev, MT_BBP(CORE, 4), BIT(0));
189 /* page count on RxQ */
190 for (i = 0; i < 200; i++) {
191 if (!(mt76_rr(dev, 0x0430) & 0x00ff0000) &&
192 !(mt76_rr(dev, 0x0a30) & 0xffffffff) &&
193 !(mt76_rr(dev, 0x0a34) & 0xffffffff) &&
199 if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_RX, 0, 2000))
200 dev_warn(dev->mt76.dev, "MAC RX failed to stop\n");
202 /* wait rx dma to stop */
203 for (i = 0; i < 2000; i++) {
204 val = mt76_rr(dev, MT_VEND_ADDR(CFG, MT_USB_U3DMA_CFG));
205 if (!(val & MT_USB_DMA_CFG_RX_BUSY) && i > 10)
207 usleep_range(50, 100);
210 mt76_wr(dev, MT_TX_RTS_CFG, rts_cfg);
215 void mt76x2u_mac_resume(struct mt76x02_dev *dev)
217 mt76_wr(dev, MT_MAC_SYS_CTRL,
218 MT_MAC_SYS_CTRL_ENABLE_TX |
219 MT_MAC_SYS_CTRL_ENABLE_RX);
220 mt76_set(dev, MT_TXOP_CTRL_CFG, BIT(20));
221 mt76_set(dev, MT_TXOP_HLDR_ET, BIT(1));