2 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
3 * Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 #include "../mt76x02_phy.h"
24 mt76x2_adjust_high_lna_gain(struct mt76x02_dev *dev, int reg, s8 offset)
28 gain = FIELD_GET(MT_BBP_AGC_LNA_HIGH_GAIN, mt76_rr(dev, MT_BBP(AGC, reg)));
30 mt76_rmw_field(dev, MT_BBP(AGC, reg), MT_BBP_AGC_LNA_HIGH_GAIN, gain);
34 mt76x2_adjust_agc_gain(struct mt76x02_dev *dev, int reg, s8 offset)
38 gain = FIELD_GET(MT_BBP_AGC_GAIN, mt76_rr(dev, MT_BBP(AGC, reg)));
40 mt76_rmw_field(dev, MT_BBP(AGC, reg), MT_BBP_AGC_GAIN, gain);
43 void mt76x2_apply_gain_adj(struct mt76x02_dev *dev)
45 s8 *gain_adj = dev->cal.rx.high_gain;
47 mt76x2_adjust_high_lna_gain(dev, 4, gain_adj[0]);
48 mt76x2_adjust_high_lna_gain(dev, 5, gain_adj[1]);
50 mt76x2_adjust_agc_gain(dev, 8, gain_adj[0]);
51 mt76x2_adjust_agc_gain(dev, 9, gain_adj[1]);
53 EXPORT_SYMBOL_GPL(mt76x2_apply_gain_adj);
55 void mt76x2_phy_set_txpower_regs(struct mt76x02_dev *dev,
56 enum nl80211_band band)
61 if (band == NL80211_BAND_2GHZ) {
62 pa_mode[0] = 0x010055ff;
63 pa_mode[1] = 0x00550055;
65 mt76_wr(dev, MT_TX_ALC_CFG_2, 0x35160a00);
66 mt76_wr(dev, MT_TX_ALC_CFG_3, 0x35160a06);
68 if (mt76x02_ext_pa_enabled(dev, band)) {
69 mt76_wr(dev, MT_RF_PA_MODE_ADJ0, 0x0000ec00);
70 mt76_wr(dev, MT_RF_PA_MODE_ADJ1, 0x0000ec00);
72 mt76_wr(dev, MT_RF_PA_MODE_ADJ0, 0xf4000200);
73 mt76_wr(dev, MT_RF_PA_MODE_ADJ1, 0xfa000200);
76 pa_mode[0] = 0x0000ffff;
77 pa_mode[1] = 0x00ff00ff;
79 if (mt76x02_ext_pa_enabled(dev, band)) {
80 mt76_wr(dev, MT_TX_ALC_CFG_2, 0x2f0f0400);
81 mt76_wr(dev, MT_TX_ALC_CFG_3, 0x2f0f0476);
83 mt76_wr(dev, MT_TX_ALC_CFG_2, 0x1b0f0400);
84 mt76_wr(dev, MT_TX_ALC_CFG_3, 0x1b0f0476);
87 if (mt76x02_ext_pa_enabled(dev, band))
88 pa_mode_adj = 0x04000000;
92 mt76_wr(dev, MT_RF_PA_MODE_ADJ0, pa_mode_adj);
93 mt76_wr(dev, MT_RF_PA_MODE_ADJ1, pa_mode_adj);
96 mt76_wr(dev, MT_BB_PA_MODE_CFG0, pa_mode[0]);
97 mt76_wr(dev, MT_BB_PA_MODE_CFG1, pa_mode[1]);
98 mt76_wr(dev, MT_RF_PA_MODE_CFG0, pa_mode[0]);
99 mt76_wr(dev, MT_RF_PA_MODE_CFG1, pa_mode[1]);
101 if (mt76x02_ext_pa_enabled(dev, band)) {
104 if (band == NL80211_BAND_2GHZ)
109 mt76_wr(dev, MT_TX0_RF_GAIN_CORR, val);
110 mt76_wr(dev, MT_TX1_RF_GAIN_CORR, val);
111 mt76_wr(dev, MT_TX_ALC_CFG_4, 0x00001818);
113 if (band == NL80211_BAND_2GHZ) {
114 u32 val = 0x0f3c3c3c;
116 mt76_wr(dev, MT_TX0_RF_GAIN_CORR, val);
117 mt76_wr(dev, MT_TX1_RF_GAIN_CORR, val);
118 mt76_wr(dev, MT_TX_ALC_CFG_4, 0x00000606);
120 mt76_wr(dev, MT_TX0_RF_GAIN_CORR, 0x383c023c);
121 mt76_wr(dev, MT_TX1_RF_GAIN_CORR, 0x24282e28);
122 mt76_wr(dev, MT_TX_ALC_CFG_4, 0);
126 EXPORT_SYMBOL_GPL(mt76x2_phy_set_txpower_regs);
129 mt76x2_get_min_rate_power(struct mt76_rate_power *r)
134 for (i = 0; i < sizeof(r->all); i++) {
139 ret = min(ret, r->all[i]);
147 void mt76x2_phy_set_txpower(struct mt76x02_dev *dev)
149 enum nl80211_chan_width width = dev->mt76.chandef.width;
150 struct ieee80211_channel *chan = dev->mt76.chandef.chan;
151 struct mt76x2_tx_power_info txp;
152 int txp_0, txp_1, delta = 0;
153 struct mt76_rate_power t = {};
154 int base_power, gain;
156 mt76x2_get_power_info(dev, &txp, chan);
158 if (width == NL80211_CHAN_WIDTH_40)
159 delta = txp.delta_bw40;
160 else if (width == NL80211_CHAN_WIDTH_80)
161 delta = txp.delta_bw80;
163 mt76x2_get_rate_power(dev, &t, chan);
164 mt76x02_add_rate_power_offset(&t, txp.chain[0].target_power);
165 mt76x02_limit_rate_power(&t, dev->mt76.txpower_conf);
166 dev->mt76.txpower_cur = mt76x02_get_max_rate_power(&t);
168 base_power = mt76x2_get_min_rate_power(&t);
169 delta += base_power - txp.chain[0].target_power;
170 txp_0 = txp.chain[0].target_power + txp.chain[0].delta + delta;
171 txp_1 = txp.chain[1].target_power + txp.chain[1].delta + delta;
173 gain = min(txp_0, txp_1);
178 } else if (gain > 0x2f) {
179 base_power -= gain - 0x2f;
184 mt76x02_add_rate_power_offset(&t, -base_power);
185 dev->target_power = txp.chain[0].target_power;
186 dev->target_power_delta[0] = txp_0 - txp.chain[0].target_power;
187 dev->target_power_delta[1] = txp_1 - txp.chain[0].target_power;
188 dev->mt76.rate_power = t;
190 mt76x02_phy_set_txpower(dev, txp_0, txp_1);
192 EXPORT_SYMBOL_GPL(mt76x2_phy_set_txpower);
194 void mt76x2_configure_tx_delay(struct mt76x02_dev *dev,
195 enum nl80211_band band, u8 bw)
199 if (mt76x02_ext_pa_enabled(dev, band)) {
200 cfg0 = bw ? 0x000b0c01 : 0x00101101;
203 cfg0 = bw ? 0x000b0b01 : 0x00101001;
206 mt76_wr(dev, MT_TX_SW_CFG0, cfg0);
207 mt76_wr(dev, MT_TX_SW_CFG1, cfg1);
209 mt76_rmw_field(dev, MT_XIFS_TIME_CFG, MT_XIFS_TIME_CFG_OFDM_SIFS, 15);
211 EXPORT_SYMBOL_GPL(mt76x2_configure_tx_delay);
213 void mt76x2_phy_tssi_compensate(struct mt76x02_dev *dev)
215 struct ieee80211_channel *chan = dev->mt76.chandef.chan;
216 struct mt76x2_tx_power_info txp;
217 struct mt76x2_tssi_comp t = {};
219 if (!dev->cal.tssi_cal_done)
222 if (!dev->cal.tssi_comp_pending) {
225 mt76x2_mcu_tssi_comp(dev, &t);
226 dev->cal.tssi_comp_pending = true;
228 if (mt76_rr(dev, MT_BBP(CORE, 34)) & BIT(4))
231 dev->cal.tssi_comp_pending = false;
232 mt76x2_get_power_info(dev, &txp, chan);
234 if (mt76x02_ext_pa_enabled(dev, chan->band))
238 t.slope0 = txp.chain[0].tssi_slope;
239 t.offset0 = txp.chain[0].tssi_offset;
240 t.slope1 = txp.chain[1].tssi_slope;
241 t.offset1 = txp.chain[1].tssi_offset;
242 mt76x2_mcu_tssi_comp(dev, &t);
244 if (t.pa_mode || dev->cal.dpd_cal_done || dev->ed_tx_blocked)
247 usleep_range(10000, 20000);
248 mt76x02_mcu_calibrate(dev, MCU_CAL_DPD, chan->hw_value);
249 dev->cal.dpd_cal_done = true;
252 EXPORT_SYMBOL_GPL(mt76x2_phy_tssi_compensate);
255 mt76x2_phy_set_gain_val(struct mt76x02_dev *dev)
260 gain_val[0] = dev->cal.agc_gain_cur[0] - dev->cal.agc_gain_adjust;
261 gain_val[1] = dev->cal.agc_gain_cur[1] - dev->cal.agc_gain_adjust;
264 if (!mt76x2_has_ext_lna(dev) &&
265 dev->mt76.chandef.width >= NL80211_CHAN_WIDTH_40)
268 if (mt76x2_has_ext_lna(dev) &&
269 dev->mt76.chandef.chan->band == NL80211_BAND_2GHZ &&
270 dev->mt76.chandef.width < NL80211_CHAN_WIDTH_40)
275 mt76_wr(dev, MT_BBP(AGC, 8),
276 val | FIELD_PREP(MT_BBP_AGC_GAIN, gain_val[0]));
277 mt76_wr(dev, MT_BBP(AGC, 9),
278 val | FIELD_PREP(MT_BBP_AGC_GAIN, gain_val[1]));
280 if (dev->mt76.chandef.chan->flags & IEEE80211_CHAN_RADAR)
281 mt76x02_phy_dfs_adjust_agc(dev);
284 void mt76x2_phy_update_channel_gain(struct mt76x02_dev *dev)
286 u8 *gain = dev->cal.agc_gain_init;
287 u8 low_gain_delta, gain_delta;
293 dev->cal.avg_rssi_all = mt76_get_min_avg_rssi(&dev->mt76);
294 if (!dev->cal.avg_rssi_all)
295 dev->cal.avg_rssi_all = -75;
297 low_gain = (dev->cal.avg_rssi_all > mt76x02_get_rssi_gain_thresh(dev)) +
298 (dev->cal.avg_rssi_all > mt76x02_get_low_rssi_gain_thresh(dev));
300 gain_change = dev->cal.low_gain < 0 ||
301 (dev->cal.low_gain & 2) ^ (low_gain & 2);
302 dev->cal.low_gain = low_gain;
305 if (mt76x02_phy_adjust_vga_gain(dev))
306 mt76x2_phy_set_gain_val(dev);
310 if (dev->mt76.chandef.width == NL80211_CHAN_WIDTH_80) {
311 mt76_wr(dev, MT_BBP(RXO, 14), 0x00560211);
312 val = mt76_rr(dev, MT_BBP(AGC, 26)) & ~0xf;
317 mt76_wr(dev, MT_BBP(AGC, 26), val);
319 mt76_wr(dev, MT_BBP(RXO, 14), 0x00560423);
322 if (mt76x2_has_ext_lna(dev))
328 if (dev->mt76.chandef.chan->band == NL80211_BAND_2GHZ)
330 else if (low_gain == 2)
331 agc_35 = agc_37 = 0x08080808;
332 else if (dev->mt76.chandef.width == NL80211_CHAN_WIDTH_80)
338 mt76_wr(dev, MT_BBP(RXO, 18), 0xf000a990);
339 mt76_wr(dev, MT_BBP(AGC, 35), 0x08080808);
340 mt76_wr(dev, MT_BBP(AGC, 37), 0x08080808);
341 gain_delta = low_gain_delta;
342 dev->cal.agc_gain_adjust = 0;
344 mt76_wr(dev, MT_BBP(RXO, 18), 0xf000a991);
346 dev->cal.agc_gain_adjust = low_gain_delta;
349 mt76_wr(dev, MT_BBP(AGC, 35), agc_35);
350 mt76_wr(dev, MT_BBP(AGC, 37), agc_37);
352 dev->cal.agc_gain_cur[0] = gain[0] - gain_delta;
353 dev->cal.agc_gain_cur[1] = gain[1] - gain_delta;
354 mt76x2_phy_set_gain_val(dev);
356 /* clear false CCA counters */
357 mt76_rr(dev, MT_RX_STAT_1);
359 EXPORT_SYMBOL_GPL(mt76x2_phy_update_channel_gain);