Merge tag 'efi-urgent' of git://git.kernel.org/pub/scm/linux/kernel/git/mfleming...
[sfrench/cifs-2.6.git] / drivers / net / wireless / iwlwifi / pcie / tx.c
1 /******************************************************************************
2  *
3  * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
4  * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
5  *
6  * Portions of this file are derived from the ipw3945 project, as well
7  * as portions of the ieee80211 subsystem header files.
8  *
9  * This program is free software; you can redistribute it and/or modify it
10  * under the terms of version 2 of the GNU General Public License as
11  * published by the Free Software Foundation.
12  *
13  * This program is distributed in the hope that it will be useful, but WITHOUT
14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
16  * more details.
17  *
18  * You should have received a copy of the GNU General Public License along with
19  * this program; if not, write to the Free Software Foundation, Inc.,
20  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21  *
22  * The full GNU General Public License is included in this distribution in the
23  * file called LICENSE.
24  *
25  * Contact Information:
26  *  Intel Linux Wireless <ilw@linux.intel.com>
27  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28  *
29  *****************************************************************************/
30 #include <linux/etherdevice.h>
31 #include <linux/slab.h>
32 #include <linux/sched.h>
33
34 #include "iwl-debug.h"
35 #include "iwl-csr.h"
36 #include "iwl-prph.h"
37 #include "iwl-io.h"
38 #include "iwl-scd.h"
39 #include "iwl-op-mode.h"
40 #include "internal.h"
41 /* FIXME: need to abstract out TX command (once we know what it looks like) */
42 #include "dvm/commands.h"
43
44 #define IWL_TX_CRC_SIZE 4
45 #define IWL_TX_DELIMITER_SIZE 4
46
47 /*************** DMA-QUEUE-GENERAL-FUNCTIONS  *****
48  * DMA services
49  *
50  * Theory of operation
51  *
52  * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
53  * of buffer descriptors, each of which points to one or more data buffers for
54  * the device to read from or fill.  Driver and device exchange status of each
55  * queue via "read" and "write" pointers.  Driver keeps minimum of 2 empty
56  * entries in each circular buffer, to protect against confusing empty and full
57  * queue states.
58  *
59  * The device reads or writes the data in the queues via the device's several
60  * DMA/FIFO channels.  Each queue is mapped to a single DMA channel.
61  *
62  * For Tx queue, there are low mark and high mark limits. If, after queuing
63  * the packet for Tx, free space become < low mark, Tx queue stopped. When
64  * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
65  * Tx queue resumed.
66  *
67  ***************************************************/
68 static int iwl_queue_space(const struct iwl_queue *q)
69 {
70         unsigned int max;
71         unsigned int used;
72
73         /*
74          * To avoid ambiguity between empty and completely full queues, there
75          * should always be less than TFD_QUEUE_SIZE_MAX elements in the queue.
76          * If q->n_window is smaller than TFD_QUEUE_SIZE_MAX, there is no need
77          * to reserve any queue entries for this purpose.
78          */
79         if (q->n_window < TFD_QUEUE_SIZE_MAX)
80                 max = q->n_window;
81         else
82                 max = TFD_QUEUE_SIZE_MAX - 1;
83
84         /*
85          * TFD_QUEUE_SIZE_MAX is a power of 2, so the following is equivalent to
86          * modulo by TFD_QUEUE_SIZE_MAX and is well defined.
87          */
88         used = (q->write_ptr - q->read_ptr) & (TFD_QUEUE_SIZE_MAX - 1);
89
90         if (WARN_ON(used > max))
91                 return 0;
92
93         return max - used;
94 }
95
96 /*
97  * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
98  */
99 static int iwl_queue_init(struct iwl_queue *q, int slots_num, u32 id)
100 {
101         q->n_window = slots_num;
102         q->id = id;
103
104         /* slots_num must be power-of-two size, otherwise
105          * get_cmd_index is broken. */
106         if (WARN_ON(!is_power_of_2(slots_num)))
107                 return -EINVAL;
108
109         q->low_mark = q->n_window / 4;
110         if (q->low_mark < 4)
111                 q->low_mark = 4;
112
113         q->high_mark = q->n_window / 8;
114         if (q->high_mark < 2)
115                 q->high_mark = 2;
116
117         q->write_ptr = 0;
118         q->read_ptr = 0;
119
120         return 0;
121 }
122
123 static int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
124                                   struct iwl_dma_ptr *ptr, size_t size)
125 {
126         if (WARN_ON(ptr->addr))
127                 return -EINVAL;
128
129         ptr->addr = dma_alloc_coherent(trans->dev, size,
130                                        &ptr->dma, GFP_KERNEL);
131         if (!ptr->addr)
132                 return -ENOMEM;
133         ptr->size = size;
134         return 0;
135 }
136
137 static void iwl_pcie_free_dma_ptr(struct iwl_trans *trans,
138                                   struct iwl_dma_ptr *ptr)
139 {
140         if (unlikely(!ptr->addr))
141                 return;
142
143         dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
144         memset(ptr, 0, sizeof(*ptr));
145 }
146
147 static void iwl_pcie_txq_stuck_timer(unsigned long data)
148 {
149         struct iwl_txq *txq = (void *)data;
150         struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
151         struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
152         u32 scd_sram_addr = trans_pcie->scd_base_addr +
153                                 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
154         u8 buf[16];
155         int i;
156
157         spin_lock(&txq->lock);
158         /* check if triggered erroneously */
159         if (txq->q.read_ptr == txq->q.write_ptr) {
160                 spin_unlock(&txq->lock);
161                 return;
162         }
163         spin_unlock(&txq->lock);
164
165         IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id,
166                 jiffies_to_msecs(txq->wd_timeout));
167         IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
168                 txq->q.read_ptr, txq->q.write_ptr);
169
170         iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
171
172         iwl_print_hex_error(trans, buf, sizeof(buf));
173
174         for (i = 0; i < FH_TCSR_CHNL_NUM; i++)
175                 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", i,
176                         iwl_read_direct32(trans, FH_TX_TRB_REG(i)));
177
178         for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
179                 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(i));
180                 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
181                 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
182                 u32 tbl_dw =
183                         iwl_trans_read_mem32(trans,
184                                              trans_pcie->scd_base_addr +
185                                              SCD_TRANS_TBL_OFFSET_QUEUE(i));
186
187                 if (i & 0x1)
188                         tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
189                 else
190                         tbl_dw = tbl_dw & 0x0000FFFF;
191
192                 IWL_ERR(trans,
193                         "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
194                         i, active ? "" : "in", fifo, tbl_dw,
195                         iwl_read_prph(trans, SCD_QUEUE_RDPTR(i)) &
196                                 (TFD_QUEUE_SIZE_MAX - 1),
197                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(i)));
198         }
199
200         iwl_force_nmi(trans);
201 }
202
203 /*
204  * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
205  */
206 static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
207                                              struct iwl_txq *txq, u16 byte_cnt)
208 {
209         struct iwlagn_scd_bc_tbl *scd_bc_tbl;
210         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
211         int write_ptr = txq->q.write_ptr;
212         int txq_id = txq->q.id;
213         u8 sec_ctl = 0;
214         u8 sta_id = 0;
215         u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
216         __le16 bc_ent;
217         struct iwl_tx_cmd *tx_cmd =
218                 (void *) txq->entries[txq->q.write_ptr].cmd->payload;
219
220         scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
221
222         WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
223
224         sta_id = tx_cmd->sta_id;
225         sec_ctl = tx_cmd->sec_ctl;
226
227         switch (sec_ctl & TX_CMD_SEC_MSK) {
228         case TX_CMD_SEC_CCM:
229                 len += IEEE80211_CCMP_MIC_LEN;
230                 break;
231         case TX_CMD_SEC_TKIP:
232                 len += IEEE80211_TKIP_ICV_LEN;
233                 break;
234         case TX_CMD_SEC_WEP:
235                 len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN;
236                 break;
237         }
238
239         if (trans_pcie->bc_table_dword)
240                 len = DIV_ROUND_UP(len, 4);
241
242         bc_ent = cpu_to_le16(len | (sta_id << 12));
243
244         scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
245
246         if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
247                 scd_bc_tbl[txq_id].
248                         tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
249 }
250
251 static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
252                                             struct iwl_txq *txq)
253 {
254         struct iwl_trans_pcie *trans_pcie =
255                 IWL_TRANS_GET_PCIE_TRANS(trans);
256         struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
257         int txq_id = txq->q.id;
258         int read_ptr = txq->q.read_ptr;
259         u8 sta_id = 0;
260         __le16 bc_ent;
261         struct iwl_tx_cmd *tx_cmd =
262                 (void *)txq->entries[txq->q.read_ptr].cmd->payload;
263
264         WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
265
266         if (txq_id != trans_pcie->cmd_queue)
267                 sta_id = tx_cmd->sta_id;
268
269         bc_ent = cpu_to_le16(1 | (sta_id << 12));
270         scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
271
272         if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
273                 scd_bc_tbl[txq_id].
274                         tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
275 }
276
277 /*
278  * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware
279  */
280 static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans,
281                                     struct iwl_txq *txq)
282 {
283         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
284         u32 reg = 0;
285         int txq_id = txq->q.id;
286
287         lockdep_assert_held(&txq->lock);
288
289         /*
290          * explicitly wake up the NIC if:
291          * 1. shadow registers aren't enabled
292          * 2. NIC is woken up for CMD regardless of shadow outside this function
293          * 3. there is a chance that the NIC is asleep
294          */
295         if (!trans->cfg->base_params->shadow_reg_enable &&
296             txq_id != trans_pcie->cmd_queue &&
297             test_bit(STATUS_TPOWER_PMI, &trans->status)) {
298                 /*
299                  * wake up nic if it's powered down ...
300                  * uCode will wake up, and interrupt us again, so next
301                  * time we'll skip this part.
302                  */
303                 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
304
305                 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
306                         IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
307                                        txq_id, reg);
308                         iwl_set_bit(trans, CSR_GP_CNTRL,
309                                     CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
310                         txq->need_update = true;
311                         return;
312                 }
313         }
314
315         /*
316          * if not in power-save mode, uCode will never sleep when we're
317          * trying to tx (during RFKILL, we're not trying to tx).
318          */
319         IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->q.write_ptr);
320         iwl_write32(trans, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8));
321 }
322
323 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans)
324 {
325         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
326         int i;
327
328         for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
329                 struct iwl_txq *txq = &trans_pcie->txq[i];
330
331                 spin_lock_bh(&txq->lock);
332                 if (trans_pcie->txq[i].need_update) {
333                         iwl_pcie_txq_inc_wr_ptr(trans, txq);
334                         trans_pcie->txq[i].need_update = false;
335                 }
336                 spin_unlock_bh(&txq->lock);
337         }
338 }
339
340 static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
341 {
342         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
343
344         dma_addr_t addr = get_unaligned_le32(&tb->lo);
345         if (sizeof(dma_addr_t) > sizeof(u32))
346                 addr |=
347                 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
348
349         return addr;
350 }
351
352 static inline void iwl_pcie_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
353                                        dma_addr_t addr, u16 len)
354 {
355         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
356         u16 hi_n_len = len << 4;
357
358         put_unaligned_le32(addr, &tb->lo);
359         if (sizeof(dma_addr_t) > sizeof(u32))
360                 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
361
362         tb->hi_n_len = cpu_to_le16(hi_n_len);
363
364         tfd->num_tbs = idx + 1;
365 }
366
367 static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_tfd *tfd)
368 {
369         return tfd->num_tbs & 0x1f;
370 }
371
372 static void iwl_pcie_tfd_unmap(struct iwl_trans *trans,
373                                struct iwl_cmd_meta *meta,
374                                struct iwl_tfd *tfd)
375 {
376         int i;
377         int num_tbs;
378
379         /* Sanity check on number of chunks */
380         num_tbs = iwl_pcie_tfd_get_num_tbs(tfd);
381
382         if (num_tbs >= IWL_NUM_OF_TBS) {
383                 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
384                 /* @todo issue fatal error, it is quite serious situation */
385                 return;
386         }
387
388         /* first TB is never freed - it's the scratchbuf data */
389
390         for (i = 1; i < num_tbs; i++)
391                 dma_unmap_single(trans->dev, iwl_pcie_tfd_tb_get_addr(tfd, i),
392                                  iwl_pcie_tfd_tb_get_len(tfd, i),
393                                  DMA_TO_DEVICE);
394
395         tfd->num_tbs = 0;
396 }
397
398 /*
399  * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
400  * @trans - transport private data
401  * @txq - tx queue
402  * @dma_dir - the direction of the DMA mapping
403  *
404  * Does NOT advance any TFD circular buffer read/write indexes
405  * Does NOT free the TFD itself (which is within circular buffer)
406  */
407 static void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq)
408 {
409         struct iwl_tfd *tfd_tmp = txq->tfds;
410
411         /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and
412          * idx is bounded by n_window
413          */
414         int rd_ptr = txq->q.read_ptr;
415         int idx = get_cmd_index(&txq->q, rd_ptr);
416
417         lockdep_assert_held(&txq->lock);
418
419         /* We have only q->n_window txq->entries, but we use
420          * TFD_QUEUE_SIZE_MAX tfds
421          */
422         iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, &tfd_tmp[rd_ptr]);
423
424         /* free SKB */
425         if (txq->entries) {
426                 struct sk_buff *skb;
427
428                 skb = txq->entries[idx].skb;
429
430                 /* Can be called from irqs-disabled context
431                  * If skb is not NULL, it means that the whole queue is being
432                  * freed and that the queue is not empty - free the skb
433                  */
434                 if (skb) {
435                         iwl_op_mode_free_skb(trans->op_mode, skb);
436                         txq->entries[idx].skb = NULL;
437                 }
438         }
439 }
440
441 static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq,
442                                   dma_addr_t addr, u16 len, bool reset)
443 {
444         struct iwl_queue *q;
445         struct iwl_tfd *tfd, *tfd_tmp;
446         u32 num_tbs;
447
448         q = &txq->q;
449         tfd_tmp = txq->tfds;
450         tfd = &tfd_tmp[q->write_ptr];
451
452         if (reset)
453                 memset(tfd, 0, sizeof(*tfd));
454
455         num_tbs = iwl_pcie_tfd_get_num_tbs(tfd);
456
457         /* Each TFD can point to a maximum 20 Tx buffers */
458         if (num_tbs >= IWL_NUM_OF_TBS) {
459                 IWL_ERR(trans, "Error can not send more than %d chunks\n",
460                         IWL_NUM_OF_TBS);
461                 return -EINVAL;
462         }
463
464         if (WARN(addr & ~IWL_TX_DMA_MASK,
465                  "Unaligned address = %llx\n", (unsigned long long)addr))
466                 return -EINVAL;
467
468         iwl_pcie_tfd_set_tb(tfd, num_tbs, addr, len);
469
470         return 0;
471 }
472
473 static int iwl_pcie_txq_alloc(struct iwl_trans *trans,
474                                struct iwl_txq *txq, int slots_num,
475                                u32 txq_id)
476 {
477         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
478         size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
479         size_t scratchbuf_sz;
480         int i;
481
482         if (WARN_ON(txq->entries || txq->tfds))
483                 return -EINVAL;
484
485         setup_timer(&txq->stuck_timer, iwl_pcie_txq_stuck_timer,
486                     (unsigned long)txq);
487         txq->trans_pcie = trans_pcie;
488
489         txq->q.n_window = slots_num;
490
491         txq->entries = kcalloc(slots_num,
492                                sizeof(struct iwl_pcie_txq_entry),
493                                GFP_KERNEL);
494
495         if (!txq->entries)
496                 goto error;
497
498         if (txq_id == trans_pcie->cmd_queue)
499                 for (i = 0; i < slots_num; i++) {
500                         txq->entries[i].cmd =
501                                 kmalloc(sizeof(struct iwl_device_cmd),
502                                         GFP_KERNEL);
503                         if (!txq->entries[i].cmd)
504                                 goto error;
505                 }
506
507         /* Circular buffer of transmit frame descriptors (TFDs),
508          * shared with device */
509         txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
510                                        &txq->q.dma_addr, GFP_KERNEL);
511         if (!txq->tfds)
512                 goto error;
513
514         BUILD_BUG_ON(IWL_HCMD_SCRATCHBUF_SIZE != sizeof(*txq->scratchbufs));
515         BUILD_BUG_ON(offsetof(struct iwl_pcie_txq_scratch_buf, scratch) !=
516                         sizeof(struct iwl_cmd_header) +
517                         offsetof(struct iwl_tx_cmd, scratch));
518
519         scratchbuf_sz = sizeof(*txq->scratchbufs) * slots_num;
520
521         txq->scratchbufs = dma_alloc_coherent(trans->dev, scratchbuf_sz,
522                                               &txq->scratchbufs_dma,
523                                               GFP_KERNEL);
524         if (!txq->scratchbufs)
525                 goto err_free_tfds;
526
527         txq->q.id = txq_id;
528
529         return 0;
530 err_free_tfds:
531         dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->q.dma_addr);
532 error:
533         if (txq->entries && txq_id == trans_pcie->cmd_queue)
534                 for (i = 0; i < slots_num; i++)
535                         kfree(txq->entries[i].cmd);
536         kfree(txq->entries);
537         txq->entries = NULL;
538
539         return -ENOMEM;
540
541 }
542
543 static int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq,
544                               int slots_num, u32 txq_id)
545 {
546         int ret;
547
548         txq->need_update = false;
549
550         /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
551          * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
552         BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
553
554         /* Initialize queue's high/low-water marks, and head/tail indexes */
555         ret = iwl_queue_init(&txq->q, slots_num, txq_id);
556         if (ret)
557                 return ret;
558
559         spin_lock_init(&txq->lock);
560
561         /*
562          * Tell nic where to find circular buffer of Tx Frame Descriptors for
563          * given Tx queue, and enable the DMA channel used for that queue.
564          * Circular buffer (TFD queue in DRAM) physical base address */
565         iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
566                            txq->q.dma_addr >> 8);
567
568         return 0;
569 }
570
571 /*
572  * iwl_pcie_txq_unmap -  Unmap any remaining DMA mappings and free skb's
573  */
574 static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id)
575 {
576         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
577         struct iwl_txq *txq = &trans_pcie->txq[txq_id];
578         struct iwl_queue *q = &txq->q;
579
580         spin_lock_bh(&txq->lock);
581         while (q->write_ptr != q->read_ptr) {
582                 IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n",
583                                    txq_id, q->read_ptr);
584                 iwl_pcie_txq_free_tfd(trans, txq);
585                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr);
586         }
587         txq->active = false;
588         spin_unlock_bh(&txq->lock);
589
590         /* just in case - this queue may have been stopped */
591         iwl_wake_queue(trans, txq);
592 }
593
594 /*
595  * iwl_pcie_txq_free - Deallocate DMA queue.
596  * @txq: Transmit queue to deallocate.
597  *
598  * Empty queue by removing and destroying all BD's.
599  * Free all buffers.
600  * 0-fill, but do not free "txq" descriptor structure.
601  */
602 static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id)
603 {
604         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
605         struct iwl_txq *txq = &trans_pcie->txq[txq_id];
606         struct device *dev = trans->dev;
607         int i;
608
609         if (WARN_ON(!txq))
610                 return;
611
612         iwl_pcie_txq_unmap(trans, txq_id);
613
614         /* De-alloc array of command/tx buffers */
615         if (txq_id == trans_pcie->cmd_queue)
616                 for (i = 0; i < txq->q.n_window; i++) {
617                         kzfree(txq->entries[i].cmd);
618                         kzfree(txq->entries[i].free_buf);
619                 }
620
621         /* De-alloc circular buffer of TFDs */
622         if (txq->tfds) {
623                 dma_free_coherent(dev,
624                                   sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX,
625                                   txq->tfds, txq->q.dma_addr);
626                 txq->q.dma_addr = 0;
627                 txq->tfds = NULL;
628
629                 dma_free_coherent(dev,
630                                   sizeof(*txq->scratchbufs) * txq->q.n_window,
631                                   txq->scratchbufs, txq->scratchbufs_dma);
632         }
633
634         kfree(txq->entries);
635         txq->entries = NULL;
636
637         del_timer_sync(&txq->stuck_timer);
638
639         /* 0-fill queue descriptor structure */
640         memset(txq, 0, sizeof(*txq));
641 }
642
643 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
644 {
645         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
646         int nq = trans->cfg->base_params->num_of_queues;
647         int chan;
648         u32 reg_val;
649         int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) -
650                                 SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32);
651
652         /* make sure all queue are not stopped/used */
653         memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
654         memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
655
656         trans_pcie->scd_base_addr =
657                 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
658
659         WARN_ON(scd_base_addr != 0 &&
660                 scd_base_addr != trans_pcie->scd_base_addr);
661
662         /* reset context data, TX status and translation data */
663         iwl_trans_write_mem(trans, trans_pcie->scd_base_addr +
664                                    SCD_CONTEXT_MEM_LOWER_BOUND,
665                             NULL, clear_dwords);
666
667         iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
668                        trans_pcie->scd_bc_tbls.dma >> 10);
669
670         /* The chain extension of the SCD doesn't work well. This feature is
671          * enabled by default by the HW, so we need to disable it manually.
672          */
673         if (trans->cfg->base_params->scd_chain_ext_wa)
674                 iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
675
676         iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue,
677                                 trans_pcie->cmd_fifo,
678                                 trans_pcie->cmd_q_wdg_timeout);
679
680         /* Activate all Tx DMA/FIFO channels */
681         iwl_scd_activate_fifos(trans);
682
683         /* Enable DMA channel */
684         for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++)
685                 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
686                                    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
687                                    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
688
689         /* Update FH chicken bits */
690         reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
691         iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
692                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
693
694         /* Enable L1-Active */
695         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
696                 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
697                                     APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
698 }
699
700 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans)
701 {
702         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
703         int txq_id;
704
705         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
706              txq_id++) {
707                 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
708
709                 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
710                                    txq->q.dma_addr >> 8);
711                 iwl_pcie_txq_unmap(trans, txq_id);
712                 txq->q.read_ptr = 0;
713                 txq->q.write_ptr = 0;
714         }
715
716         /* Tell NIC where to find the "keep warm" buffer */
717         iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
718                            trans_pcie->kw.dma >> 4);
719
720         /*
721          * Send 0 as the scd_base_addr since the device may have be reset
722          * while we were in WoWLAN in which case SCD_SRAM_BASE_ADDR will
723          * contain garbage.
724          */
725         iwl_pcie_tx_start(trans, 0);
726 }
727
728 /*
729  * iwl_pcie_tx_stop - Stop all Tx DMA channels
730  */
731 int iwl_pcie_tx_stop(struct iwl_trans *trans)
732 {
733         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
734         int ch, txq_id, ret;
735
736         /* Turn off all Tx DMA fifos */
737         spin_lock(&trans_pcie->irq_lock);
738
739         iwl_scd_deactivate_fifos(trans);
740
741         /* Stop each Tx DMA channel, and wait for it to be idle */
742         for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
743                 iwl_write_direct32(trans,
744                                    FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
745                 ret = iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG,
746                         FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 1000);
747                 if (ret < 0)
748                         IWL_ERR(trans,
749                                 "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
750                                 ch,
751                                 iwl_read_direct32(trans,
752                                                   FH_TSSR_TX_STATUS_REG));
753         }
754         spin_unlock(&trans_pcie->irq_lock);
755
756         /*
757          * This function can be called before the op_mode disabled the
758          * queues. This happens when we have an rfkill interrupt.
759          * Since we stop Tx altogether - mark the queues as stopped.
760          */
761         memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
762         memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
763
764         /* This can happen: start_hw, stop_device */
765         if (!trans_pcie->txq)
766                 return 0;
767
768         /* Unmap DMA from host system and free skb's */
769         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
770              txq_id++)
771                 iwl_pcie_txq_unmap(trans, txq_id);
772
773         return 0;
774 }
775
776 /*
777  * iwl_trans_tx_free - Free TXQ Context
778  *
779  * Destroy all TX DMA queues and structures
780  */
781 void iwl_pcie_tx_free(struct iwl_trans *trans)
782 {
783         int txq_id;
784         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
785
786         /* Tx queues */
787         if (trans_pcie->txq) {
788                 for (txq_id = 0;
789                      txq_id < trans->cfg->base_params->num_of_queues; txq_id++)
790                         iwl_pcie_txq_free(trans, txq_id);
791         }
792
793         kfree(trans_pcie->txq);
794         trans_pcie->txq = NULL;
795
796         iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw);
797
798         iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
799 }
800
801 /*
802  * iwl_pcie_tx_alloc - allocate TX context
803  * Allocate all Tx DMA structures and initialize them
804  */
805 static int iwl_pcie_tx_alloc(struct iwl_trans *trans)
806 {
807         int ret;
808         int txq_id, slots_num;
809         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
810
811         u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues *
812                         sizeof(struct iwlagn_scd_bc_tbl);
813
814         /*It is not allowed to alloc twice, so warn when this happens.
815          * We cannot rely on the previous allocation, so free and fail */
816         if (WARN_ON(trans_pcie->txq)) {
817                 ret = -EINVAL;
818                 goto error;
819         }
820
821         ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
822                                    scd_bc_tbls_size);
823         if (ret) {
824                 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
825                 goto error;
826         }
827
828         /* Alloc keep-warm buffer */
829         ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
830         if (ret) {
831                 IWL_ERR(trans, "Keep Warm allocation failed\n");
832                 goto error;
833         }
834
835         trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues,
836                                   sizeof(struct iwl_txq), GFP_KERNEL);
837         if (!trans_pcie->txq) {
838                 IWL_ERR(trans, "Not enough memory for txq\n");
839                 ret = -ENOMEM;
840                 goto error;
841         }
842
843         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
844         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
845              txq_id++) {
846                 slots_num = (txq_id == trans_pcie->cmd_queue) ?
847                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
848                 ret = iwl_pcie_txq_alloc(trans, &trans_pcie->txq[txq_id],
849                                           slots_num, txq_id);
850                 if (ret) {
851                         IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
852                         goto error;
853                 }
854         }
855
856         return 0;
857
858 error:
859         iwl_pcie_tx_free(trans);
860
861         return ret;
862 }
863 int iwl_pcie_tx_init(struct iwl_trans *trans)
864 {
865         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
866         int ret;
867         int txq_id, slots_num;
868         bool alloc = false;
869
870         if (!trans_pcie->txq) {
871                 ret = iwl_pcie_tx_alloc(trans);
872                 if (ret)
873                         goto error;
874                 alloc = true;
875         }
876
877         spin_lock(&trans_pcie->irq_lock);
878
879         /* Turn off all Tx DMA fifos */
880         iwl_scd_deactivate_fifos(trans);
881
882         /* Tell NIC where to find the "keep warm" buffer */
883         iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
884                            trans_pcie->kw.dma >> 4);
885
886         spin_unlock(&trans_pcie->irq_lock);
887
888         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
889         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
890              txq_id++) {
891                 slots_num = (txq_id == trans_pcie->cmd_queue) ?
892                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
893                 ret = iwl_pcie_txq_init(trans, &trans_pcie->txq[txq_id],
894                                          slots_num, txq_id);
895                 if (ret) {
896                         IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
897                         goto error;
898                 }
899         }
900
901         if (trans->cfg->base_params->num_of_queues > 20)
902                 iwl_set_bits_prph(trans, SCD_GP_CTRL,
903                                   SCD_GP_CTRL_ENABLE_31_QUEUES);
904
905         return 0;
906 error:
907         /*Upon error, free only if we allocated something */
908         if (alloc)
909                 iwl_pcie_tx_free(trans);
910         return ret;
911 }
912
913 static inline void iwl_pcie_txq_progress(struct iwl_txq *txq)
914 {
915         if (!txq->wd_timeout)
916                 return;
917
918         /*
919          * if empty delete timer, otherwise move timer forward
920          * since we're making progress on this queue
921          */
922         if (txq->q.read_ptr == txq->q.write_ptr)
923                 del_timer(&txq->stuck_timer);
924         else
925                 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
926 }
927
928 /* Frees buffers until index _not_ inclusive */
929 void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
930                             struct sk_buff_head *skbs)
931 {
932         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
933         struct iwl_txq *txq = &trans_pcie->txq[txq_id];
934         int tfd_num = ssn & (TFD_QUEUE_SIZE_MAX - 1);
935         struct iwl_queue *q = &txq->q;
936         int last_to_free;
937
938         /* This function is not meant to release cmd queue*/
939         if (WARN_ON(txq_id == trans_pcie->cmd_queue))
940                 return;
941
942         spin_lock_bh(&txq->lock);
943
944         if (!txq->active) {
945                 IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n",
946                                     txq_id, ssn);
947                 goto out;
948         }
949
950         if (txq->q.read_ptr == tfd_num)
951                 goto out;
952
953         IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
954                            txq_id, txq->q.read_ptr, tfd_num, ssn);
955
956         /*Since we free until index _not_ inclusive, the one before index is
957          * the last we will free. This one must be used */
958         last_to_free = iwl_queue_dec_wrap(tfd_num);
959
960         if (!iwl_queue_used(q, last_to_free)) {
961                 IWL_ERR(trans,
962                         "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",
963                         __func__, txq_id, last_to_free, TFD_QUEUE_SIZE_MAX,
964                         q->write_ptr, q->read_ptr);
965                 goto out;
966         }
967
968         if (WARN_ON(!skb_queue_empty(skbs)))
969                 goto out;
970
971         for (;
972              q->read_ptr != tfd_num;
973              q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) {
974
975                 if (WARN_ON_ONCE(txq->entries[txq->q.read_ptr].skb == NULL))
976                         continue;
977
978                 __skb_queue_tail(skbs, txq->entries[txq->q.read_ptr].skb);
979
980                 txq->entries[txq->q.read_ptr].skb = NULL;
981
982                 iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq);
983
984                 iwl_pcie_txq_free_tfd(trans, txq);
985         }
986
987         iwl_pcie_txq_progress(txq);
988
989         if (iwl_queue_space(&txq->q) > txq->q.low_mark)
990                 iwl_wake_queue(trans, txq);
991
992         if (q->read_ptr == q->write_ptr) {
993                 IWL_DEBUG_RPM(trans, "Q %d - last tx reclaimed\n", q->id);
994                 iwl_trans_pcie_unref(trans);
995         }
996
997 out:
998         spin_unlock_bh(&txq->lock);
999 }
1000
1001 static int iwl_pcie_set_cmd_in_flight(struct iwl_trans *trans,
1002                                       const struct iwl_host_cmd *cmd)
1003 {
1004         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1005         int ret;
1006
1007         lockdep_assert_held(&trans_pcie->reg_lock);
1008
1009         if (!(cmd->flags & CMD_SEND_IN_IDLE) &&
1010             !trans_pcie->ref_cmd_in_flight) {
1011                 trans_pcie->ref_cmd_in_flight = true;
1012                 IWL_DEBUG_RPM(trans, "set ref_cmd_in_flight - ref\n");
1013                 iwl_trans_pcie_ref(trans);
1014         }
1015
1016         if (trans_pcie->cmd_in_flight)
1017                 return 0;
1018
1019         trans_pcie->cmd_in_flight = true;
1020
1021         /*
1022          * wake up the NIC to make sure that the firmware will see the host
1023          * command - we will let the NIC sleep once all the host commands
1024          * returned. This needs to be done only on NICs that have
1025          * apmg_wake_up_wa set.
1026          */
1027         if (trans->cfg->base_params->apmg_wake_up_wa) {
1028                 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1029                                          CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1030                 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1031                         udelay(2);
1032
1033                 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1034                                    CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1035                                    (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1036                                     CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP),
1037                                    15000);
1038                 if (ret < 0) {
1039                         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1040                                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1041                         trans_pcie->cmd_in_flight = false;
1042                         IWL_ERR(trans, "Failed to wake NIC for hcmd\n");
1043                         return -EIO;
1044                 }
1045         }
1046
1047         return 0;
1048 }
1049
1050 static int iwl_pcie_clear_cmd_in_flight(struct iwl_trans *trans)
1051 {
1052         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1053
1054         lockdep_assert_held(&trans_pcie->reg_lock);
1055
1056         if (trans_pcie->ref_cmd_in_flight) {
1057                 trans_pcie->ref_cmd_in_flight = false;
1058                 IWL_DEBUG_RPM(trans, "clear ref_cmd_in_flight - unref\n");
1059                 iwl_trans_pcie_unref(trans);
1060         }
1061
1062         if (WARN_ON(!trans_pcie->cmd_in_flight))
1063                 return 0;
1064
1065         trans_pcie->cmd_in_flight = false;
1066
1067         if (trans->cfg->base_params->apmg_wake_up_wa)
1068                 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1069                                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1070
1071         return 0;
1072 }
1073
1074 /*
1075  * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd
1076  *
1077  * When FW advances 'R' index, all entries between old and new 'R' index
1078  * need to be reclaimed. As result, some free space forms.  If there is
1079  * enough free space (> low mark), wake the stack that feeds us.
1080  */
1081 static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx)
1082 {
1083         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1084         struct iwl_txq *txq = &trans_pcie->txq[txq_id];
1085         struct iwl_queue *q = &txq->q;
1086         unsigned long flags;
1087         int nfreed = 0;
1088
1089         lockdep_assert_held(&txq->lock);
1090
1091         if ((idx >= TFD_QUEUE_SIZE_MAX) || (!iwl_queue_used(q, idx))) {
1092                 IWL_ERR(trans,
1093                         "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
1094                         __func__, txq_id, idx, TFD_QUEUE_SIZE_MAX,
1095                         q->write_ptr, q->read_ptr);
1096                 return;
1097         }
1098
1099         for (idx = iwl_queue_inc_wrap(idx); q->read_ptr != idx;
1100              q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) {
1101
1102                 if (nfreed++ > 0) {
1103                         IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n",
1104                                 idx, q->write_ptr, q->read_ptr);
1105                         iwl_force_nmi(trans);
1106                 }
1107         }
1108
1109         if (q->read_ptr == q->write_ptr) {
1110                 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1111                 iwl_pcie_clear_cmd_in_flight(trans);
1112                 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1113         }
1114
1115         iwl_pcie_txq_progress(txq);
1116 }
1117
1118 static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid,
1119                                  u16 txq_id)
1120 {
1121         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1122         u32 tbl_dw_addr;
1123         u32 tbl_dw;
1124         u16 scd_q2ratid;
1125
1126         scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
1127
1128         tbl_dw_addr = trans_pcie->scd_base_addr +
1129                         SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
1130
1131         tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr);
1132
1133         if (txq_id & 0x1)
1134                 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1135         else
1136                 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1137
1138         iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw);
1139
1140         return 0;
1141 }
1142
1143 /* Receiver address (actually, Rx station's index into station table),
1144  * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */
1145 #define BUILD_RAxTID(sta_id, tid)       (((sta_id) << 4) + (tid))
1146
1147 void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn,
1148                                const struct iwl_trans_txq_scd_cfg *cfg,
1149                                unsigned int wdg_timeout)
1150 {
1151         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1152         struct iwl_txq *txq = &trans_pcie->txq[txq_id];
1153         int fifo = -1;
1154
1155         if (test_and_set_bit(txq_id, trans_pcie->queue_used))
1156                 WARN_ONCE(1, "queue %d already used - expect issues", txq_id);
1157
1158         txq->wd_timeout = msecs_to_jiffies(wdg_timeout);
1159
1160         if (cfg) {
1161                 fifo = cfg->fifo;
1162
1163                 /* Disable the scheduler prior configuring the cmd queue */
1164                 if (txq_id == trans_pcie->cmd_queue &&
1165                     trans_pcie->scd_set_active)
1166                         iwl_scd_enable_set_active(trans, 0);
1167
1168                 /* Stop this Tx queue before configuring it */
1169                 iwl_scd_txq_set_inactive(trans, txq_id);
1170
1171                 /* Set this queue as a chain-building queue unless it is CMD */
1172                 if (txq_id != trans_pcie->cmd_queue)
1173                         iwl_scd_txq_set_chain(trans, txq_id);
1174
1175                 if (cfg->aggregate) {
1176                         u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid);
1177
1178                         /* Map receiver-address / traffic-ID to this queue */
1179                         iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id);
1180
1181                         /* enable aggregations for the queue */
1182                         iwl_scd_txq_enable_agg(trans, txq_id);
1183                         txq->ampdu = true;
1184                 } else {
1185                         /*
1186                          * disable aggregations for the queue, this will also
1187                          * make the ra_tid mapping configuration irrelevant
1188                          * since it is now a non-AGG queue.
1189                          */
1190                         iwl_scd_txq_disable_agg(trans, txq_id);
1191
1192                         ssn = txq->q.read_ptr;
1193                 }
1194         }
1195
1196         /* Place first TFD at index corresponding to start sequence number.
1197          * Assumes that ssn_idx is valid (!= 0xFFF) */
1198         txq->q.read_ptr = (ssn & 0xff);
1199         txq->q.write_ptr = (ssn & 0xff);
1200         iwl_write_direct32(trans, HBUS_TARG_WRPTR,
1201                            (ssn & 0xff) | (txq_id << 8));
1202
1203         if (cfg) {
1204                 u8 frame_limit = cfg->frame_limit;
1205
1206                 iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);
1207
1208                 /* Set up Tx window size and frame limit for this queue */
1209                 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
1210                                 SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0);
1211                 iwl_trans_write_mem32(trans,
1212                         trans_pcie->scd_base_addr +
1213                         SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1214                         ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1215                                         SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1216                         ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1217                                         SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1218
1219                 /* Set up status area in SRAM, map to Tx DMA/FIFO, activate */
1220                 iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
1221                                (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1222                                (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) |
1223                                (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
1224                                SCD_QUEUE_STTS_REG_MSK);
1225
1226                 /* enable the scheduler for this queue (only) */
1227                 if (txq_id == trans_pcie->cmd_queue &&
1228                     trans_pcie->scd_set_active)
1229                         iwl_scd_enable_set_active(trans, BIT(txq_id));
1230
1231                 IWL_DEBUG_TX_QUEUES(trans,
1232                                     "Activate queue %d on FIFO %d WrPtr: %d\n",
1233                                     txq_id, fifo, ssn & 0xff);
1234         } else {
1235                 IWL_DEBUG_TX_QUEUES(trans,
1236                                     "Activate queue %d WrPtr: %d\n",
1237                                     txq_id, ssn & 0xff);
1238         }
1239
1240         txq->active = true;
1241 }
1242
1243 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id,
1244                                 bool configure_scd)
1245 {
1246         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1247         u32 stts_addr = trans_pcie->scd_base_addr +
1248                         SCD_TX_STTS_QUEUE_OFFSET(txq_id);
1249         static const u32 zero_val[4] = {};
1250
1251         /*
1252          * Upon HW Rfkill - we stop the device, and then stop the queues
1253          * in the op_mode. Just for the sake of the simplicity of the op_mode,
1254          * allow the op_mode to call txq_disable after it already called
1255          * stop_device.
1256          */
1257         if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) {
1258                 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status),
1259                           "queue %d not used", txq_id);
1260                 return;
1261         }
1262
1263         if (configure_scd) {
1264                 iwl_scd_txq_set_inactive(trans, txq_id);
1265
1266                 iwl_trans_write_mem(trans, stts_addr, (void *)zero_val,
1267                                     ARRAY_SIZE(zero_val));
1268         }
1269
1270         iwl_pcie_txq_unmap(trans, txq_id);
1271         trans_pcie->txq[txq_id].ampdu = false;
1272
1273         IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id);
1274 }
1275
1276 /*************** HOST COMMAND QUEUE FUNCTIONS   *****/
1277
1278 /*
1279  * iwl_pcie_enqueue_hcmd - enqueue a uCode command
1280  * @priv: device private data point
1281  * @cmd: a pointer to the ucode command structure
1282  *
1283  * The function returns < 0 values to indicate the operation
1284  * failed. On success, it returns the index (>= 0) of command in the
1285  * command queue.
1286  */
1287 static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
1288                                  struct iwl_host_cmd *cmd)
1289 {
1290         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1291         struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1292         struct iwl_queue *q = &txq->q;
1293         struct iwl_device_cmd *out_cmd;
1294         struct iwl_cmd_meta *out_meta;
1295         unsigned long flags;
1296         void *dup_buf = NULL;
1297         dma_addr_t phys_addr;
1298         int idx;
1299         u16 copy_size, cmd_size, scratch_size;
1300         bool had_nocopy = false;
1301         int i, ret;
1302         u32 cmd_pos;
1303         const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD];
1304         u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD];
1305
1306         copy_size = sizeof(out_cmd->hdr);
1307         cmd_size = sizeof(out_cmd->hdr);
1308
1309         /* need one for the header if the first is NOCOPY */
1310         BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1);
1311
1312         for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1313                 cmddata[i] = cmd->data[i];
1314                 cmdlen[i] = cmd->len[i];
1315
1316                 if (!cmd->len[i])
1317                         continue;
1318
1319                 /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */
1320                 if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) {
1321                         int copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size;
1322
1323                         if (copy > cmdlen[i])
1324                                 copy = cmdlen[i];
1325                         cmdlen[i] -= copy;
1326                         cmddata[i] += copy;
1327                         copy_size += copy;
1328                 }
1329
1330                 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
1331                         had_nocopy = true;
1332                         if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) {
1333                                 idx = -EINVAL;
1334                                 goto free_dup_buf;
1335                         }
1336                 } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) {
1337                         /*
1338                          * This is also a chunk that isn't copied
1339                          * to the static buffer so set had_nocopy.
1340                          */
1341                         had_nocopy = true;
1342
1343                         /* only allowed once */
1344                         if (WARN_ON(dup_buf)) {
1345                                 idx = -EINVAL;
1346                                 goto free_dup_buf;
1347                         }
1348
1349                         dup_buf = kmemdup(cmddata[i], cmdlen[i],
1350                                           GFP_ATOMIC);
1351                         if (!dup_buf)
1352                                 return -ENOMEM;
1353                 } else {
1354                         /* NOCOPY must not be followed by normal! */
1355                         if (WARN_ON(had_nocopy)) {
1356                                 idx = -EINVAL;
1357                                 goto free_dup_buf;
1358                         }
1359                         copy_size += cmdlen[i];
1360                 }
1361                 cmd_size += cmd->len[i];
1362         }
1363
1364         /*
1365          * If any of the command structures end up being larger than
1366          * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
1367          * allocated into separate TFDs, then we will need to
1368          * increase the size of the buffers.
1369          */
1370         if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE,
1371                  "Command %s (%#x) is too large (%d bytes)\n",
1372                  get_cmd_string(trans_pcie, cmd->id), cmd->id, copy_size)) {
1373                 idx = -EINVAL;
1374                 goto free_dup_buf;
1375         }
1376
1377         spin_lock_bh(&txq->lock);
1378
1379         if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
1380                 spin_unlock_bh(&txq->lock);
1381
1382                 IWL_ERR(trans, "No space in command queue\n");
1383                 iwl_op_mode_cmd_queue_full(trans->op_mode);
1384                 idx = -ENOSPC;
1385                 goto free_dup_buf;
1386         }
1387
1388         idx = get_cmd_index(q, q->write_ptr);
1389         out_cmd = txq->entries[idx].cmd;
1390         out_meta = &txq->entries[idx].meta;
1391
1392         memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
1393         if (cmd->flags & CMD_WANT_SKB)
1394                 out_meta->source = cmd;
1395
1396         /* set up the header */
1397
1398         out_cmd->hdr.cmd = cmd->id;
1399         out_cmd->hdr.flags = 0;
1400         out_cmd->hdr.sequence =
1401                 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1402                                          INDEX_TO_SEQ(q->write_ptr));
1403
1404         /* and copy the data that needs to be copied */
1405         cmd_pos = offsetof(struct iwl_device_cmd, payload);
1406         copy_size = sizeof(out_cmd->hdr);
1407         for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1408                 int copy;
1409
1410                 if (!cmd->len[i])
1411                         continue;
1412
1413                 /* copy everything if not nocopy/dup */
1414                 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1415                                            IWL_HCMD_DFL_DUP))) {
1416                         copy = cmd->len[i];
1417
1418                         memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1419                         cmd_pos += copy;
1420                         copy_size += copy;
1421                         continue;
1422                 }
1423
1424                 /*
1425                  * Otherwise we need at least IWL_HCMD_SCRATCHBUF_SIZE copied
1426                  * in total (for the scratchbuf handling), but copy up to what
1427                  * we can fit into the payload for debug dump purposes.
1428                  */
1429                 copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]);
1430
1431                 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1432                 cmd_pos += copy;
1433
1434                 /* However, treat copy_size the proper way, we need it below */
1435                 if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) {
1436                         copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size;
1437
1438                         if (copy > cmd->len[i])
1439                                 copy = cmd->len[i];
1440                         copy_size += copy;
1441                 }
1442         }
1443
1444         IWL_DEBUG_HC(trans,
1445                      "Sending command %s (#%x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
1446                      get_cmd_string(trans_pcie, out_cmd->hdr.cmd),
1447                      out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
1448                      cmd_size, q->write_ptr, idx, trans_pcie->cmd_queue);
1449
1450         /* start the TFD with the scratchbuf */
1451         scratch_size = min_t(int, copy_size, IWL_HCMD_SCRATCHBUF_SIZE);
1452         memcpy(&txq->scratchbufs[q->write_ptr], &out_cmd->hdr, scratch_size);
1453         iwl_pcie_txq_build_tfd(trans, txq,
1454                                iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr),
1455                                scratch_size, true);
1456
1457         /* map first command fragment, if any remains */
1458         if (copy_size > scratch_size) {
1459                 phys_addr = dma_map_single(trans->dev,
1460                                            ((u8 *)&out_cmd->hdr) + scratch_size,
1461                                            copy_size - scratch_size,
1462                                            DMA_TO_DEVICE);
1463                 if (dma_mapping_error(trans->dev, phys_addr)) {
1464                         iwl_pcie_tfd_unmap(trans, out_meta,
1465                                            &txq->tfds[q->write_ptr]);
1466                         idx = -ENOMEM;
1467                         goto out;
1468                 }
1469
1470                 iwl_pcie_txq_build_tfd(trans, txq, phys_addr,
1471                                        copy_size - scratch_size, false);
1472         }
1473
1474         /* map the remaining (adjusted) nocopy/dup fragments */
1475         for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1476                 const void *data = cmddata[i];
1477
1478                 if (!cmdlen[i])
1479                         continue;
1480                 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1481                                            IWL_HCMD_DFL_DUP)))
1482                         continue;
1483                 if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP)
1484                         data = dup_buf;
1485                 phys_addr = dma_map_single(trans->dev, (void *)data,
1486                                            cmdlen[i], DMA_TO_DEVICE);
1487                 if (dma_mapping_error(trans->dev, phys_addr)) {
1488                         iwl_pcie_tfd_unmap(trans, out_meta,
1489                                            &txq->tfds[q->write_ptr]);
1490                         idx = -ENOMEM;
1491                         goto out;
1492                 }
1493
1494                 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false);
1495         }
1496
1497         out_meta->flags = cmd->flags;
1498         if (WARN_ON_ONCE(txq->entries[idx].free_buf))
1499                 kzfree(txq->entries[idx].free_buf);
1500         txq->entries[idx].free_buf = dup_buf;
1501
1502         trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr);
1503
1504         /* start timer if queue currently empty */
1505         if (q->read_ptr == q->write_ptr && txq->wd_timeout)
1506                 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
1507
1508         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1509         ret = iwl_pcie_set_cmd_in_flight(trans, cmd);
1510         if (ret < 0) {
1511                 idx = ret;
1512                 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1513                 goto out;
1514         }
1515
1516         /* Increment and update queue's write index */
1517         q->write_ptr = iwl_queue_inc_wrap(q->write_ptr);
1518         iwl_pcie_txq_inc_wr_ptr(trans, txq);
1519
1520         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1521
1522  out:
1523         spin_unlock_bh(&txq->lock);
1524  free_dup_buf:
1525         if (idx < 0)
1526                 kfree(dup_buf);
1527         return idx;
1528 }
1529
1530 /*
1531  * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them
1532  * @rxb: Rx buffer to reclaim
1533  * @handler_status: return value of the handler of the command
1534  *      (put in setup_rx_handlers)
1535  *
1536  * If an Rx buffer has an async callback associated with it the callback
1537  * will be executed.  The attached skb (if present) will only be freed
1538  * if the callback returns 1
1539  */
1540 void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
1541                             struct iwl_rx_cmd_buffer *rxb, int handler_status)
1542 {
1543         struct iwl_rx_packet *pkt = rxb_addr(rxb);
1544         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1545         int txq_id = SEQ_TO_QUEUE(sequence);
1546         int index = SEQ_TO_INDEX(sequence);
1547         int cmd_index;
1548         struct iwl_device_cmd *cmd;
1549         struct iwl_cmd_meta *meta;
1550         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1551         struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1552
1553         /* If a Tx command is being handled and it isn't in the actual
1554          * command queue then there a command routing bug has been introduced
1555          * in the queue management code. */
1556         if (WARN(txq_id != trans_pcie->cmd_queue,
1557                  "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
1558                  txq_id, trans_pcie->cmd_queue, sequence,
1559                  trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr,
1560                  trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) {
1561                 iwl_print_hex_error(trans, pkt, 32);
1562                 return;
1563         }
1564
1565         spin_lock_bh(&txq->lock);
1566
1567         cmd_index = get_cmd_index(&txq->q, index);
1568         cmd = txq->entries[cmd_index].cmd;
1569         meta = &txq->entries[cmd_index].meta;
1570
1571         iwl_pcie_tfd_unmap(trans, meta, &txq->tfds[index]);
1572
1573         /* Input error checking is done when commands are added to queue. */
1574         if (meta->flags & CMD_WANT_SKB) {
1575                 struct page *p = rxb_steal_page(rxb);
1576
1577                 meta->source->resp_pkt = pkt;
1578                 meta->source->_rx_page_addr = (unsigned long)page_address(p);
1579                 meta->source->_rx_page_order = trans_pcie->rx_page_order;
1580                 meta->source->handler_status = handler_status;
1581         }
1582
1583         iwl_pcie_cmdq_reclaim(trans, txq_id, index);
1584
1585         if (!(meta->flags & CMD_ASYNC)) {
1586                 if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) {
1587                         IWL_WARN(trans,
1588                                  "HCMD_ACTIVE already clear for command %s\n",
1589                                  get_cmd_string(trans_pcie, cmd->hdr.cmd));
1590                 }
1591                 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1592                 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1593                                get_cmd_string(trans_pcie, cmd->hdr.cmd));
1594                 wake_up(&trans_pcie->wait_command_queue);
1595         }
1596
1597         meta->flags = 0;
1598
1599         spin_unlock_bh(&txq->lock);
1600 }
1601
1602 #define HOST_COMPLETE_TIMEOUT   (2 * HZ)
1603
1604 static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans,
1605                                     struct iwl_host_cmd *cmd)
1606 {
1607         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1608         int ret;
1609
1610         /* An asynchronous command can not expect an SKB to be set. */
1611         if (WARN_ON(cmd->flags & CMD_WANT_SKB))
1612                 return -EINVAL;
1613
1614         ret = iwl_pcie_enqueue_hcmd(trans, cmd);
1615         if (ret < 0) {
1616                 IWL_ERR(trans,
1617                         "Error sending %s: enqueue_hcmd failed: %d\n",
1618                         get_cmd_string(trans_pcie, cmd->id), ret);
1619                 return ret;
1620         }
1621         return 0;
1622 }
1623
1624 static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans,
1625                                    struct iwl_host_cmd *cmd)
1626 {
1627         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1628         int cmd_idx;
1629         int ret;
1630
1631         IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n",
1632                        get_cmd_string(trans_pcie, cmd->id));
1633
1634         if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE,
1635                                   &trans->status),
1636                  "Command %s: a command is already active!\n",
1637                  get_cmd_string(trans_pcie, cmd->id)))
1638                 return -EIO;
1639
1640         IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n",
1641                        get_cmd_string(trans_pcie, cmd->id));
1642
1643         cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd);
1644         if (cmd_idx < 0) {
1645                 ret = cmd_idx;
1646                 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1647                 IWL_ERR(trans,
1648                         "Error sending %s: enqueue_hcmd failed: %d\n",
1649                         get_cmd_string(trans_pcie, cmd->id), ret);
1650                 return ret;
1651         }
1652
1653         ret = wait_event_timeout(trans_pcie->wait_command_queue,
1654                                  !test_bit(STATUS_SYNC_HCMD_ACTIVE,
1655                                            &trans->status),
1656                                  HOST_COMPLETE_TIMEOUT);
1657         if (!ret) {
1658                 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1659                 struct iwl_queue *q = &txq->q;
1660
1661                 IWL_ERR(trans, "Error sending %s: time out after %dms.\n",
1662                         get_cmd_string(trans_pcie, cmd->id),
1663                         jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
1664
1665                 IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n",
1666                         q->read_ptr, q->write_ptr);
1667
1668                 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1669                 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1670                                get_cmd_string(trans_pcie, cmd->id));
1671                 ret = -ETIMEDOUT;
1672
1673                 iwl_force_nmi(trans);
1674                 iwl_trans_fw_error(trans);
1675
1676                 goto cancel;
1677         }
1678
1679         if (test_bit(STATUS_FW_ERROR, &trans->status)) {
1680                 IWL_ERR(trans, "FW error in SYNC CMD %s\n",
1681                         get_cmd_string(trans_pcie, cmd->id));
1682                 dump_stack();
1683                 ret = -EIO;
1684                 goto cancel;
1685         }
1686
1687         if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1688             test_bit(STATUS_RFKILL, &trans->status)) {
1689                 IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n");
1690                 ret = -ERFKILL;
1691                 goto cancel;
1692         }
1693
1694         if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) {
1695                 IWL_ERR(trans, "Error: Response NULL in '%s'\n",
1696                         get_cmd_string(trans_pcie, cmd->id));
1697                 ret = -EIO;
1698                 goto cancel;
1699         }
1700
1701         return 0;
1702
1703 cancel:
1704         if (cmd->flags & CMD_WANT_SKB) {
1705                 /*
1706                  * Cancel the CMD_WANT_SKB flag for the cmd in the
1707                  * TX cmd queue. Otherwise in case the cmd comes
1708                  * in later, it will possibly set an invalid
1709                  * address (cmd->meta.source).
1710                  */
1711                 trans_pcie->txq[trans_pcie->cmd_queue].
1712                         entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB;
1713         }
1714
1715         if (cmd->resp_pkt) {
1716                 iwl_free_resp(cmd);
1717                 cmd->resp_pkt = NULL;
1718         }
1719
1720         return ret;
1721 }
1722
1723 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
1724 {
1725         if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1726             test_bit(STATUS_RFKILL, &trans->status)) {
1727                 IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n",
1728                                   cmd->id);
1729                 return -ERFKILL;
1730         }
1731
1732         if (cmd->flags & CMD_ASYNC)
1733                 return iwl_pcie_send_hcmd_async(trans, cmd);
1734
1735         /* We still can fail on RFKILL that can be asserted while we wait */
1736         return iwl_pcie_send_hcmd_sync(trans, cmd);
1737 }
1738
1739 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1740                       struct iwl_device_cmd *dev_cmd, int txq_id)
1741 {
1742         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1743         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1744         struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload;
1745         struct iwl_cmd_meta *out_meta;
1746         struct iwl_txq *txq;
1747         struct iwl_queue *q;
1748         dma_addr_t tb0_phys, tb1_phys, scratch_phys;
1749         void *tb1_addr;
1750         u16 len, tb1_len, tb2_len;
1751         bool wait_write_ptr;
1752         __le16 fc = hdr->frame_control;
1753         u8 hdr_len = ieee80211_hdrlen(fc);
1754         u16 wifi_seq;
1755
1756         txq = &trans_pcie->txq[txq_id];
1757         q = &txq->q;
1758
1759         if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used),
1760                       "TX on unused queue %d\n", txq_id))
1761                 return -EINVAL;
1762
1763         spin_lock(&txq->lock);
1764
1765         /* In AGG mode, the index in the ring must correspond to the WiFi
1766          * sequence number. This is a HW requirements to help the SCD to parse
1767          * the BA.
1768          * Check here that the packets are in the right place on the ring.
1769          */
1770         wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
1771         WARN_ONCE(txq->ampdu &&
1772                   (wifi_seq & 0xff) != q->write_ptr,
1773                   "Q: %d WiFi Seq %d tfdNum %d",
1774                   txq_id, wifi_seq, q->write_ptr);
1775
1776         /* Set up driver data for this TFD */
1777         txq->entries[q->write_ptr].skb = skb;
1778         txq->entries[q->write_ptr].cmd = dev_cmd;
1779
1780         dev_cmd->hdr.sequence =
1781                 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1782                             INDEX_TO_SEQ(q->write_ptr)));
1783
1784         tb0_phys = iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr);
1785         scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) +
1786                        offsetof(struct iwl_tx_cmd, scratch);
1787
1788         tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1789         tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1790
1791         /* Set up first empty entry in queue's array of Tx/cmd buffers */
1792         out_meta = &txq->entries[q->write_ptr].meta;
1793
1794         /*
1795          * The second TB (tb1) points to the remainder of the TX command
1796          * and the 802.11 header - dword aligned size
1797          * (This calculation modifies the TX command, so do it before the
1798          * setup of the first TB)
1799          */
1800         len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) +
1801               hdr_len - IWL_HCMD_SCRATCHBUF_SIZE;
1802         tb1_len = ALIGN(len, 4);
1803
1804         /* Tell NIC about any 2-byte padding after MAC header */
1805         if (tb1_len != len)
1806                 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1807
1808         /* The first TB points to the scratchbuf data - min_copy bytes */
1809         memcpy(&txq->scratchbufs[q->write_ptr], &dev_cmd->hdr,
1810                IWL_HCMD_SCRATCHBUF_SIZE);
1811         iwl_pcie_txq_build_tfd(trans, txq, tb0_phys,
1812                                IWL_HCMD_SCRATCHBUF_SIZE, true);
1813
1814         /* there must be data left over for TB1 or this code must be changed */
1815         BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_HCMD_SCRATCHBUF_SIZE);
1816
1817         /* map the data for TB1 */
1818         tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_HCMD_SCRATCHBUF_SIZE;
1819         tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE);
1820         if (unlikely(dma_mapping_error(trans->dev, tb1_phys)))
1821                 goto out_err;
1822         iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false);
1823
1824         /*
1825          * Set up TFD's third entry to point directly to remainder
1826          * of skb, if any (802.11 null frames have no payload).
1827          */
1828         tb2_len = skb->len - hdr_len;
1829         if (tb2_len > 0) {
1830                 dma_addr_t tb2_phys = dma_map_single(trans->dev,
1831                                                      skb->data + hdr_len,
1832                                                      tb2_len, DMA_TO_DEVICE);
1833                 if (unlikely(dma_mapping_error(trans->dev, tb2_phys))) {
1834                         iwl_pcie_tfd_unmap(trans, out_meta,
1835                                            &txq->tfds[q->write_ptr]);
1836                         goto out_err;
1837                 }
1838                 iwl_pcie_txq_build_tfd(trans, txq, tb2_phys, tb2_len, false);
1839         }
1840
1841         /* Set up entry for this TFD in Tx byte-count array */
1842         iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1843
1844         trace_iwlwifi_dev_tx(trans->dev, skb,
1845                              &txq->tfds[txq->q.write_ptr],
1846                              sizeof(struct iwl_tfd),
1847                              &dev_cmd->hdr, IWL_HCMD_SCRATCHBUF_SIZE + tb1_len,
1848                              skb->data + hdr_len, tb2_len);
1849         trace_iwlwifi_dev_tx_data(trans->dev, skb,
1850                                   skb->data + hdr_len, tb2_len);
1851
1852         wait_write_ptr = ieee80211_has_morefrags(fc);
1853
1854         /* start timer if queue currently empty */
1855         if (q->read_ptr == q->write_ptr) {
1856                 if (txq->wd_timeout)
1857                         mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
1858                 IWL_DEBUG_RPM(trans, "Q: %d first tx - take ref\n", q->id);
1859                 iwl_trans_pcie_ref(trans);
1860         }
1861
1862         /* Tell device the write index *just past* this latest filled TFD */
1863         q->write_ptr = iwl_queue_inc_wrap(q->write_ptr);
1864         if (!wait_write_ptr)
1865                 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1866
1867         /*
1868          * At this point the frame is "transmitted" successfully
1869          * and we will get a TX status notification eventually.
1870          */
1871         if (iwl_queue_space(q) < q->high_mark) {
1872                 if (wait_write_ptr)
1873                         iwl_pcie_txq_inc_wr_ptr(trans, txq);
1874                 else
1875                         iwl_stop_queue(trans, txq);
1876         }
1877         spin_unlock(&txq->lock);
1878         return 0;
1879 out_err:
1880         spin_unlock(&txq->lock);
1881         return -1;
1882 }