drivers/net/wireless/ipw2200.c

   1 /******************************************************************************
   2
   3   Copyright(c) 2003 - 2006 Intel Corporation. All rights reserved.
   4
   5   802.11 status code portion of this file from ethereal-0.10.6:
   6     Copyright 2000, Axis Communications AB
   7     Ethereal - Network traffic analyzer
   8     By Gerald Combs <gerald@ethereal.com>
   9     Copyright 1998 Gerald Combs
  10
  11   This program is free software; you can redistribute it and/or modify it
  12   under the terms of version 2 of the GNU General Public License as
  13   published by the Free Software Foundation.
  14
  15   This program is distributed in the hope that it will be useful, but WITHOUT
  16   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  18   more details.
  19
  20   You should have received a copy of the GNU General Public License along with
  21   this program; if not, write to the Free Software Foundation, Inc., 59
  22   Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  23
  24   The full GNU General Public License is included in this distribution in the
  25   file called LICENSE.
  26
  27   Contact Information:
  28   James P. Ketrenos <ipw2100-admin@linux.intel.com>
  29   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  30
  31 ******************************************************************************/
  32
  33 #include "ipw2200.h"
  34 #include <linux/version.h>
  35
  36
  37 #ifndef KBUILD_EXTMOD
  38 #define VK "k"
  39 #else
  40 #define VK
  41 #endif
  42
  43 #ifdef CONFIG_IPW2200_DEBUG
  44 #define VD "d"
  45 #else
  46 #define VD
  47 #endif
  48
  49 #ifdef CONFIG_IPW2200_MONITOR
  50 #define VM "m"
  51 #else
  52 #define VM
  53 #endif
  54
  55 #ifdef CONFIG_IPW2200_PROMISCUOUS
  56 #define VP "p"
  57 #else
  58 #define VP
  59 #endif
  60
  61 #ifdef CONFIG_IPW2200_RADIOTAP
  62 #define VR "r"
  63 #else
  64 #define VR
  65 #endif
  66
  67 #ifdef CONFIG_IPW2200_QOS
  68 #define VQ "q"
  69 #else
  70 #define VQ
  71 #endif
  72
  73 #define IPW2200_VERSION "1.2.2" VK VD VM VP VR VQ
  74 #define DRV_DESCRIPTION "Intel(R) PRO/Wireless 2200/2915 Network Driver"
  75 #define DRV_COPYRIGHT   "Copyright(c) 2003-2006 Intel Corporation"
  76 #define DRV_VERSION     IPW2200_VERSION
  77
  78 #define ETH_P_80211_STATS (ETH_P_80211_RAW + 1)
  79
  80 MODULE_DESCRIPTION(DRV_DESCRIPTION);
  81 MODULE_VERSION(DRV_VERSION);
  82 MODULE_AUTHOR(DRV_COPYRIGHT);
  83 MODULE_LICENSE("GPL");
  84
  85 static int cmdlog = 0;
  86 static int debug = 0;
  87 static int channel = 0;
  88 static int mode = 0;
  89
  90 static u32 ipw_debug_level;
  91 static int associate = 1;
  92 static int auto_create = 1;
  93 static int led = 0;
  94 static int disable = 0;
  95 static int bt_coexist = 0;
  96 static int hwcrypto = 0;
  97 static int roaming = 1;
  98 static const char ipw_modes[] = {
  99         'a', 'b', 'g', '?'
 100 };
 101 static int antenna = CFG_SYS_ANTENNA_BOTH;
 102
 103 #ifdef CONFIG_IPW2200_PROMISCUOUS
 104 static int rtap_iface = 0;     /* def: 0 -- do not create rtap interface */
 105 #endif
 106
 107
 108 #ifdef CONFIG_IPW2200_QOS
 109 static int qos_enable = 0;
 110 static int qos_burst_enable = 0;
 111 static int qos_no_ack_mask = 0;
 112 static int burst_duration_CCK = 0;
 113 static int burst_duration_OFDM = 0;
 114
 115 static struct ieee80211_qos_parameters def_qos_parameters_OFDM = {
 116         {QOS_TX0_CW_MIN_OFDM, QOS_TX1_CW_MIN_OFDM, QOS_TX2_CW_MIN_OFDM,
 117          QOS_TX3_CW_MIN_OFDM},
 118         {QOS_TX0_CW_MAX_OFDM, QOS_TX1_CW_MAX_OFDM, QOS_TX2_CW_MAX_OFDM,
 119          QOS_TX3_CW_MAX_OFDM},
 120         {QOS_TX0_AIFS, QOS_TX1_AIFS, QOS_TX2_AIFS, QOS_TX3_AIFS},
 121         {QOS_TX0_ACM, QOS_TX1_ACM, QOS_TX2_ACM, QOS_TX3_ACM},
 122         {QOS_TX0_TXOP_LIMIT_OFDM, QOS_TX1_TXOP_LIMIT_OFDM,
 123          QOS_TX2_TXOP_LIMIT_OFDM, QOS_TX3_TXOP_LIMIT_OFDM}
 124 };
 125
 126 static struct ieee80211_qos_parameters def_qos_parameters_CCK = {
 127         {QOS_TX0_CW_MIN_CCK, QOS_TX1_CW_MIN_CCK, QOS_TX2_CW_MIN_CCK,
 128          QOS_TX3_CW_MIN_CCK},
 129         {QOS_TX0_CW_MAX_CCK, QOS_TX1_CW_MAX_CCK, QOS_TX2_CW_MAX_CCK,
 130          QOS_TX3_CW_MAX_CCK},
 131         {QOS_TX0_AIFS, QOS_TX1_AIFS, QOS_TX2_AIFS, QOS_TX3_AIFS},
 132         {QOS_TX0_ACM, QOS_TX1_ACM, QOS_TX2_ACM, QOS_TX3_ACM},
 133         {QOS_TX0_TXOP_LIMIT_CCK, QOS_TX1_TXOP_LIMIT_CCK, QOS_TX2_TXOP_LIMIT_CCK,
 134          QOS_TX3_TXOP_LIMIT_CCK}
 135 };
 136
 137 static struct ieee80211_qos_parameters def_parameters_OFDM = {
 138         {DEF_TX0_CW_MIN_OFDM, DEF_TX1_CW_MIN_OFDM, DEF_TX2_CW_MIN_OFDM,
 139          DEF_TX3_CW_MIN_OFDM},
 140         {DEF_TX0_CW_MAX_OFDM, DEF_TX1_CW_MAX_OFDM, DEF_TX2_CW_MAX_OFDM,
 141          DEF_TX3_CW_MAX_OFDM},
 142         {DEF_TX0_AIFS, DEF_TX1_AIFS, DEF_TX2_AIFS, DEF_TX3_AIFS},
 143         {DEF_TX0_ACM, DEF_TX1_ACM, DEF_TX2_ACM, DEF_TX3_ACM},
 144         {DEF_TX0_TXOP_LIMIT_OFDM, DEF_TX1_TXOP_LIMIT_OFDM,
 145          DEF_TX2_TXOP_LIMIT_OFDM, DEF_TX3_TXOP_LIMIT_OFDM}
 146 };
 147
 148 static struct ieee80211_qos_parameters def_parameters_CCK = {
 149         {DEF_TX0_CW_MIN_CCK, DEF_TX1_CW_MIN_CCK, DEF_TX2_CW_MIN_CCK,
 150          DEF_TX3_CW_MIN_CCK},
 151         {DEF_TX0_CW_MAX_CCK, DEF_TX1_CW_MAX_CCK, DEF_TX2_CW_MAX_CCK,
 152          DEF_TX3_CW_MAX_CCK},
 153         {DEF_TX0_AIFS, DEF_TX1_AIFS, DEF_TX2_AIFS, DEF_TX3_AIFS},
 154         {DEF_TX0_ACM, DEF_TX1_ACM, DEF_TX2_ACM, DEF_TX3_ACM},
 155         {DEF_TX0_TXOP_LIMIT_CCK, DEF_TX1_TXOP_LIMIT_CCK, DEF_TX2_TXOP_LIMIT_CCK,
 156          DEF_TX3_TXOP_LIMIT_CCK}
 157 };
 158
 159 static u8 qos_oui[QOS_OUI_LEN] = { 0x00, 0x50, 0xF2 };
 160
 161 static int from_priority_to_tx_queue[] = {
 162         IPW_TX_QUEUE_1, IPW_TX_QUEUE_2, IPW_TX_QUEUE_2, IPW_TX_QUEUE_1,
 163         IPW_TX_QUEUE_3, IPW_TX_QUEUE_3, IPW_TX_QUEUE_4, IPW_TX_QUEUE_4
 164 };
 165
 166 static u32 ipw_qos_get_burst_duration(struct ipw_priv *priv);
 167
 168 static int ipw_send_qos_params_command(struct ipw_priv *priv, struct ieee80211_qos_parameters
 169                                        *qos_param);
 170 static int ipw_send_qos_info_command(struct ipw_priv *priv, struct ieee80211_qos_information_element
 171                                      *qos_param);
 172 #endif                          /* CONFIG_IPW2200_QOS */
 173
 174 static struct iw_statistics *ipw_get_wireless_stats(struct net_device *dev);
 175 static void ipw_remove_current_network(struct ipw_priv *priv);
 176 static void ipw_rx(struct ipw_priv *priv);
 177 static int ipw_queue_tx_reclaim(struct ipw_priv *priv,
 178                                 struct clx2_tx_queue *txq, int qindex);
 179 static int ipw_queue_reset(struct ipw_priv *priv);
 180
 181 static int ipw_queue_tx_hcmd(struct ipw_priv *priv, int hcmd, void *buf,
 182                              int len, int sync);
 183
 184 static void ipw_tx_queue_free(struct ipw_priv *);
 185
 186 static struct ipw_rx_queue *ipw_rx_queue_alloc(struct ipw_priv *);
 187 static void ipw_rx_queue_free(struct ipw_priv *, struct ipw_rx_queue *);
 188 static void ipw_rx_queue_replenish(void *);
 189 static int ipw_up(struct ipw_priv *);
 190 static void ipw_bg_up(struct work_struct *work);
 191 static void ipw_down(struct ipw_priv *);
 192 static void ipw_bg_down(struct work_struct *work);
 193 static int ipw_config(struct ipw_priv *);
 194 static int init_supported_rates(struct ipw_priv *priv,
 195                                 struct ipw_supported_rates *prates);
 196 static void ipw_set_hwcrypto_keys(struct ipw_priv *);
 197 static void ipw_send_wep_keys(struct ipw_priv *, int);
 198
 199 static int snprint_line(char *buf, size_t count,
 200                         const u8 * data, u32 len, u32 ofs)
 201 {
 202         int out, i, j, l;
 203         char c;
 204
 205         out = snprintf(buf, count, "%08X", ofs);
 206
 207         for (l = 0, i = 0; i < 2; i++) {
 208                 out += snprintf(buf + out, count - out, " ");
 209                 for (j = 0; j < 8 && l < len; j++, l++)
 210                         out += snprintf(buf + out, count - out, "%02X ",
 211                                         data[(i * 8 + j)]);
 212                 for (; j < 8; j++)
 213                         out += snprintf(buf + out, count - out, "   ");
 214         }
 215
 216         out += snprintf(buf + out, count - out, " ");
 217         for (l = 0, i = 0; i < 2; i++) {
 218                 out += snprintf(buf + out, count - out, " ");
 219                 for (j = 0; j < 8 && l < len; j++, l++) {
 220                         c = data[(i * 8 + j)];
 221                         if (!isascii(c) || !isprint(c))
 222                                 c = '.';
 223
 224                         out += snprintf(buf + out, count - out, "%c", c);
 225                 }
 226
 227                 for (; j < 8; j++)
 228                         out += snprintf(buf + out, count - out, " ");
 229         }
 230
 231         return out;
 232 }
 233
 234 static void printk_buf(int level, const u8 * data, u32 len)
 235 {
 236         char line[81];
 237         u32 ofs = 0;
 238         if (!(ipw_debug_level & level))
 239                 return;
 240
 241         while (len) {
 242                 snprint_line(line, sizeof(line), &data[ofs],
 243                              min(len, 16U), ofs);
 244                 printk(KERN_DEBUG "%s\n", line);
 245                 ofs += 16;
 246                 len -= min(len, 16U);
 247         }
 248 }
 249
 250 static int snprintk_buf(u8 * output, size_t size, const u8 * data, size_t len)
 251 {
 252         size_t out = size;
 253         u32 ofs = 0;
 254         int total = 0;
 255
 256         while (size && len) {
 257                 out = snprint_line(output, size, &data[ofs],
 258                                    min_t(size_t, len, 16U), ofs);
 259
 260                 ofs += 16;
 261                 output += out;
 262                 size -= out;
 263                 len -= min_t(size_t, len, 16U);
 264                 total += out;
 265         }
 266         return total;
 267 }
 268
 269 /* alias for 32-bit indirect read (for SRAM/reg above 4K), with debug wrapper */
 270 static u32 _ipw_read_reg32(struct ipw_priv *priv, u32 reg);
 271 #define ipw_read_reg32(a, b) _ipw_read_reg32(a, b)
 272
 273 /* alias for 8-bit indirect read (for SRAM/reg above 4K), with debug wrapper */
 274 static u8 _ipw_read_reg8(struct ipw_priv *ipw, u32 reg);
 275 #define ipw_read_reg8(a, b) _ipw_read_reg8(a, b)
 276
 277 /* 8-bit indirect write (for SRAM/reg above 4K), with debug wrapper */
 278 static void _ipw_write_reg8(struct ipw_priv *priv, u32 reg, u8 value);
 279 static inline void ipw_write_reg8(struct ipw_priv *a, u32 b, u8 c)
 280 {
 281         IPW_DEBUG_IO("%s %d: write_indirect8(0x%08X, 0x%08X)\n", __FILE__,
 282                      __LINE__, (u32) (b), (u32) (c));
 283         _ipw_write_reg8(a, b, c);
 284 }
 285
 286 /* 16-bit indirect write (for SRAM/reg above 4K), with debug wrapper */
 287 static void _ipw_write_reg16(struct ipw_priv *priv, u32 reg, u16 value);
 288 static inline void ipw_write_reg16(struct ipw_priv *a, u32 b, u16 c)
 289 {
 290         IPW_DEBUG_IO("%s %d: write_indirect16(0x%08X, 0x%08X)\n", __FILE__,
 291                      __LINE__, (u32) (b), (u32) (c));
 292         _ipw_write_reg16(a, b, c);
 293 }
 294
 295 /* 32-bit indirect write (for SRAM/reg above 4K), with debug wrapper */
 296 static void _ipw_write_reg32(struct ipw_priv *priv, u32 reg, u32 value);
 297 static inline void ipw_write_reg32(struct ipw_priv *a, u32 b, u32 c)
 298 {
 299         IPW_DEBUG_IO("%s %d: write_indirect32(0x%08X, 0x%08X)\n", __FILE__,
 300                      __LINE__, (u32) (b), (u32) (c));
 301         _ipw_write_reg32(a, b, c);
 302 }
 303
 304 /* 8-bit direct write (low 4K) */
 305 #define _ipw_write8(ipw, ofs, val) writeb((val), (ipw)->hw_base + (ofs))
 306
 307 /* 8-bit direct write (for low 4K of SRAM/regs), with debug wrapper */
 308 #define ipw_write8(ipw, ofs, val) \
 309  IPW_DEBUG_IO("%s %d: write_direct8(0x%08X, 0x%08X)\n", __FILE__, __LINE__, (u32)(ofs), (u32)(val)); \
 310  _ipw_write8(ipw, ofs, val)
 311
 312 /* 16-bit direct write (low 4K) */
 313 #define _ipw_write16(ipw, ofs, val) writew((val), (ipw)->hw_base + (ofs))
 314
 315 /* 16-bit direct write (for low 4K of SRAM/regs), with debug wrapper */
 316 #define ipw_write16(ipw, ofs, val) \
 317  IPW_DEBUG_IO("%s %d: write_direct16(0x%08X, 0x%08X)\n", __FILE__, __LINE__, (u32)(ofs), (u32)(val)); \
 318  _ipw_write16(ipw, ofs, val)
 319
 320 /* 32-bit direct write (low 4K) */
 321 #define _ipw_write32(ipw, ofs, val) writel((val), (ipw)->hw_base + (ofs))
 322
 323 /* 32-bit direct write (for low 4K of SRAM/regs), with debug wrapper */
 324 #define ipw_write32(ipw, ofs, val) \
 325  IPW_DEBUG_IO("%s %d: write_direct32(0x%08X, 0x%08X)\n", __FILE__, __LINE__, (u32)(ofs), (u32)(val)); \
 326  _ipw_write32(ipw, ofs, val)
 327
 328 /* 8-bit direct read (low 4K) */
 329 #define _ipw_read8(ipw, ofs) readb((ipw)->hw_base + (ofs))
 330
 331 /* 8-bit direct read (low 4K), with debug wrapper */
 332 static inline u8 __ipw_read8(char *f, u32 l, struct ipw_priv *ipw, u32 ofs)
 333 {
 334         IPW_DEBUG_IO("%s %d: read_direct8(0x%08X)\n", f, l, (u32) (ofs));
 335         return _ipw_read8(ipw, ofs);
 336 }
 337
 338 /* alias to 8-bit direct read (low 4K of SRAM/regs), with debug wrapper */
 339 #define ipw_read8(ipw, ofs) __ipw_read8(__FILE__, __LINE__, ipw, ofs)
 340
 341 /* 16-bit direct read (low 4K) */
 342 #define _ipw_read16(ipw, ofs) readw((ipw)->hw_base + (ofs))
 343
 344 /* 16-bit direct read (low 4K), with debug wrapper */
 345 static inline u16 __ipw_read16(char *f, u32 l, struct ipw_priv *ipw, u32 ofs)
 346 {
 347         IPW_DEBUG_IO("%s %d: read_direct16(0x%08X)\n", f, l, (u32) (ofs));
 348         return _ipw_read16(ipw, ofs);
 349 }
 350
 351 /* alias to 16-bit direct read (low 4K of SRAM/regs), with debug wrapper */
 352 #define ipw_read16(ipw, ofs) __ipw_read16(__FILE__, __LINE__, ipw, ofs)
 353
 354 /* 32-bit direct read (low 4K) */
 355 #define _ipw_read32(ipw, ofs) readl((ipw)->hw_base + (ofs))
 356
 357 /* 32-bit direct read (low 4K), with debug wrapper */
 358 static inline u32 __ipw_read32(char *f, u32 l, struct ipw_priv *ipw, u32 ofs)
 359 {
 360         IPW_DEBUG_IO("%s %d: read_direct32(0x%08X)\n", f, l, (u32) (ofs));
 361         return _ipw_read32(ipw, ofs);
 362 }
 363
 364 /* alias to 32-bit direct read (low 4K of SRAM/regs), with debug wrapper */
 365 #define ipw_read32(ipw, ofs) __ipw_read32(__FILE__, __LINE__, ipw, ofs)
 366
 367 /* multi-byte read (above 4K), with debug wrapper */
 368 static void _ipw_read_indirect(struct ipw_priv *, u32, u8 *, int);
 369 static inline void __ipw_read_indirect(const char *f, int l,
 370                                        struct ipw_priv *a, u32 b, u8 * c, int d)
 371 {
 372         IPW_DEBUG_IO("%s %d: read_indirect(0x%08X) %d bytes\n", f, l, (u32) (b),
 373                      d);
 374         _ipw_read_indirect(a, b, c, d);
 375 }
 376
 377 /* alias to multi-byte read (SRAM/regs above 4K), with debug wrapper */
 378 #define ipw_read_indirect(a, b, c, d) __ipw_read_indirect(__FILE__, __LINE__, a, b, c, d)
 379
 380 /* alias to multi-byte read (SRAM/regs above 4K), with debug wrapper */
 381 static void _ipw_write_indirect(struct ipw_priv *priv, u32 addr, u8 * data,
 382                                 int num);
 383 #define ipw_write_indirect(a, b, c, d) \
 384         IPW_DEBUG_IO("%s %d: write_indirect(0x%08X) %d bytes\n", __FILE__, __LINE__, (u32)(b), d); \
 385         _ipw_write_indirect(a, b, c, d)
 386
 387 /* 32-bit indirect write (above 4K) */
 388 static void _ipw_write_reg32(struct ipw_priv *priv, u32 reg, u32 value)
 389 {
 390         IPW_DEBUG_IO(" %p : reg = 0x%8X : value = 0x%8X\n", priv, reg, value);
 391         _ipw_write32(priv, IPW_INDIRECT_ADDR, reg);
 392         _ipw_write32(priv, IPW_INDIRECT_DATA, value);
 393 }
 394
 395 /* 8-bit indirect write (above 4K) */
 396 static void _ipw_write_reg8(struct ipw_priv *priv, u32 reg, u8 value)
 397 {
 398         u32 aligned_addr = reg & IPW_INDIRECT_ADDR_MASK;        /* dword align */
 399         u32 dif_len = reg - aligned_addr;
 400
 401         IPW_DEBUG_IO(" reg = 0x%8X : value = 0x%8X\n", reg, value);
 402         _ipw_write32(priv, IPW_INDIRECT_ADDR, aligned_addr);
 403         _ipw_write8(priv, IPW_INDIRECT_DATA + dif_len, value);
 404 }
 405
 406 /* 16-bit indirect write (above 4K) */
 407 static void _ipw_write_reg16(struct ipw_priv *priv, u32 reg, u16 value)
 408 {
 409         u32 aligned_addr = reg & IPW_INDIRECT_ADDR_MASK;        /* dword align */
 410         u32 dif_len = (reg - aligned_addr) & (~0x1ul);
 411
 412         IPW_DEBUG_IO(" reg = 0x%8X : value = 0x%8X\n", reg, value);
 413         _ipw_write32(priv, IPW_INDIRECT_ADDR, aligned_addr);
 414         _ipw_write16(priv, IPW_INDIRECT_DATA + dif_len, value);
 415 }
 416
 417 /* 8-bit indirect read (above 4K) */
 418 static u8 _ipw_read_reg8(struct ipw_priv *priv, u32 reg)
 419 {
 420         u32 word;
 421         _ipw_write32(priv, IPW_INDIRECT_ADDR, reg & IPW_INDIRECT_ADDR_MASK);
 422         IPW_DEBUG_IO(" reg = 0x%8X : \n", reg);
 423         word = _ipw_read32(priv, IPW_INDIRECT_DATA);
 424         return (word >> ((reg & 0x3) * 8)) & 0xff;
 425 }
 426
 427 /* 32-bit indirect read (above 4K) */
 428 static u32 _ipw_read_reg32(struct ipw_priv *priv, u32 reg)
 429 {
 430         u32 value;
 431
 432         IPW_DEBUG_IO("%p : reg = 0x%08x\n", priv, reg);
 433
 434         _ipw_write32(priv, IPW_INDIRECT_ADDR, reg);
 435         value = _ipw_read32(priv, IPW_INDIRECT_DATA);
 436         IPW_DEBUG_IO(" reg = 0x%4X : value = 0x%4x \n", reg, value);
 437         return value;
 438 }
 439
 440 /* General purpose, no alignment requirement, iterative (multi-byte) read, */
 441 /*    for area above 1st 4K of SRAM/reg space */
 442 static void _ipw_read_indirect(struct ipw_priv *priv, u32 addr, u8 * buf,
 443                                int num)
 444 {
 445         u32 aligned_addr = addr & IPW_INDIRECT_ADDR_MASK;       /* dword align */
 446         u32 dif_len = addr - aligned_addr;
 447         u32 i;
 448
 449         IPW_DEBUG_IO("addr = %i, buf = %p, num = %i\n", addr, buf, num);
 450
 451         if (num <= 0) {
 452                 return;
 453         }
 454
 455         /* Read the first dword (or portion) byte by byte */
 456         if (unlikely(dif_len)) {
 457                 _ipw_write32(priv, IPW_INDIRECT_ADDR, aligned_addr);
 458                 /* Start reading at aligned_addr + dif_len */
 459                 for (i = dif_len; ((i < 4) && (num > 0)); i++, num--)
 460                         *buf++ = _ipw_read8(priv, IPW_INDIRECT_DATA + i);
 461                 aligned_addr += 4;
 462         }
 463
 464         /* Read all of the middle dwords as dwords, with auto-increment */
 465         _ipw_write32(priv, IPW_AUTOINC_ADDR, aligned_addr);
 466         for (; num >= 4; buf += 4, aligned_addr += 4, num -= 4)
 467                 *(u32 *) buf = _ipw_read32(priv, IPW_AUTOINC_DATA);
 468
 469         /* Read the last dword (or portion) byte by byte */
 470         if (unlikely(num)) {
 471                 _ipw_write32(priv, IPW_INDIRECT_ADDR, aligned_addr);
 472                 for (i = 0; num > 0; i++, num--)
 473                         *buf++ = ipw_read8(priv, IPW_INDIRECT_DATA + i);
 474         }
 475 }
 476
 477 /* General purpose, no alignment requirement, iterative (multi-byte) write, */
 478 /*    for area above 1st 4K of SRAM/reg space */
 479 static void _ipw_write_indirect(struct ipw_priv *priv, u32 addr, u8 * buf,
 480                                 int num)
 481 {
 482         u32 aligned_addr = addr & IPW_INDIRECT_ADDR_MASK;       /* dword align */
 483         u32 dif_len = addr - aligned_addr;
 484         u32 i;
 485
 486         IPW_DEBUG_IO("addr = %i, buf = %p, num = %i\n", addr, buf, num);
 487
 488         if (num <= 0) {
 489                 return;
 490         }
 491
 492         /* Write the first dword (or portion) byte by byte */
 493         if (unlikely(dif_len)) {
 494                 _ipw_write32(priv, IPW_INDIRECT_ADDR, aligned_addr);
 495                 /* Start writing at aligned_addr + dif_len */
 496                 for (i = dif_len; ((i < 4) && (num > 0)); i++, num--, buf++)
 497                         _ipw_write8(priv, IPW_INDIRECT_DATA + i, *buf);
 498                 aligned_addr += 4;
 499         }
 500
 501         /* Write all of the middle dwords as dwords, with auto-increment */
 502         _ipw_write32(priv, IPW_AUTOINC_ADDR, aligned_addr);
 503         for (; num >= 4; buf += 4, aligned_addr += 4, num -= 4)
 504                 _ipw_write32(priv, IPW_AUTOINC_DATA, *(u32 *) buf);
 505
 506         /* Write the last dword (or portion) byte by byte */
 507         if (unlikely(num)) {
 508                 _ipw_write32(priv, IPW_INDIRECT_ADDR, aligned_addr);
 509                 for (i = 0; num > 0; i++, num--, buf++)
 510                         _ipw_write8(priv, IPW_INDIRECT_DATA + i, *buf);
 511         }
 512 }
 513
 514 /* General purpose, no alignment requirement, iterative (multi-byte) write, */
 515 /*    for 1st 4K of SRAM/regs space */
 516 static void ipw_write_direct(struct ipw_priv *priv, u32 addr, void *buf,
 517                              int num)
 518 {
 519         memcpy_toio((priv->hw_base + addr), buf, num);
 520 }
 521
 522 /* Set bit(s) in low 4K of SRAM/regs */
 523 static inline void ipw_set_bit(struct ipw_priv *priv, u32 reg, u32 mask)
 524 {
 525         ipw_write32(priv, reg, ipw_read32(priv, reg) | mask);
 526 }
 527
 528 /* Clear bit(s) in low 4K of SRAM/regs */
 529 static inline void ipw_clear_bit(struct ipw_priv *priv, u32 reg, u32 mask)
 530 {
 531         ipw_write32(priv, reg, ipw_read32(priv, reg) & ~mask);
 532 }
 533
 534 static inline void __ipw_enable_interrupts(struct ipw_priv *priv)
 535 {
 536         if (priv->status & STATUS_INT_ENABLED)
 537                 return;
 538         priv->status |= STATUS_INT_ENABLED;
 539         ipw_write32(priv, IPW_INTA_MASK_R, IPW_INTA_MASK_ALL);
 540 }
 541
 542 static inline void __ipw_disable_interrupts(struct ipw_priv *priv)
 543 {
 544         if (!(priv->status & STATUS_INT_ENABLED))
 545                 return;
 546         priv->status &= ~STATUS_INT_ENABLED;
 547         ipw_write32(priv, IPW_INTA_MASK_R, ~IPW_INTA_MASK_ALL);
 548 }
 549
 550 static inline void ipw_enable_interrupts(struct ipw_priv *priv)
 551 {
 552         unsigned long flags;
 553
 554         spin_lock_irqsave(&priv->irq_lock, flags);
 555         __ipw_enable_interrupts(priv);
 556         spin_unlock_irqrestore(&priv->irq_lock, flags);
 557 }
 558
 559 static inline void ipw_disable_interrupts(struct ipw_priv *priv)
 560 {
 561         unsigned long flags;
 562
 563         spin_lock_irqsave(&priv->irq_lock, flags);
 564         __ipw_disable_interrupts(priv);
 565         spin_unlock_irqrestore(&priv->irq_lock, flags);
 566 }
 567
 568 static char *ipw_error_desc(u32 val)
 569 {
 570         switch (val) {
 571         case IPW_FW_ERROR_OK:
 572                 return "ERROR_OK";
 573         case IPW_FW_ERROR_FAIL:
 574                 return "ERROR_FAIL";
 575         case IPW_FW_ERROR_MEMORY_UNDERFLOW:
 576                 return "MEMORY_UNDERFLOW";
 577         case IPW_FW_ERROR_MEMORY_OVERFLOW:
 578                 return "MEMORY_OVERFLOW";
 579         case IPW_FW_ERROR_BAD_PARAM:
 580                 return "BAD_PARAM";
 581         case IPW_FW_ERROR_BAD_CHECKSUM:
 582                 return "BAD_CHECKSUM";
 583         case IPW_FW_ERROR_NMI_INTERRUPT:
 584                 return "NMI_INTERRUPT";
 585         case IPW_FW_ERROR_BAD_DATABASE:
 586                 return "BAD_DATABASE";
 587         case IPW_FW_ERROR_ALLOC_FAIL:
 588                 return "ALLOC_FAIL";
 589         case IPW_FW_ERROR_DMA_UNDERRUN:
 590                 return "DMA_UNDERRUN";
 591         case IPW_FW_ERROR_DMA_STATUS:
 592                 return "DMA_STATUS";
 593         case IPW_FW_ERROR_DINO_ERROR:
 594                 return "DINO_ERROR";
 595         case IPW_FW_ERROR_EEPROM_ERROR:
 596                 return "EEPROM_ERROR";
 597         case IPW_FW_ERROR_SYSASSERT:
 598                 return "SYSASSERT";
 599         case IPW_FW_ERROR_FATAL_ERROR:
 600                 return "FATAL_ERROR";
 601         default:
 602                 return "UNKNOWN_ERROR";
 603         }
 604 }
 605
 606 static void ipw_dump_error_log(struct ipw_priv *priv,
 607                                struct ipw_fw_error *error)
 608 {
 609         u32 i;
 610
 611         if (!error) {
 612                 IPW_ERROR("Error allocating and capturing error log.  "
 613                           "Nothing to dump.\n");
 614                 return;
 615         }
 616
 617         IPW_ERROR("Start IPW Error Log Dump:\n");
 618         IPW_ERROR("Status: 0x%08X, Config: %08X\n",
 619                   error->status, error->config);
 620
 621         for (i = 0; i < error->elem_len; i++)
 622                 IPW_ERROR("%s %i 0x%08x  0x%08x  0x%08x  0x%08x  0x%08x\n",
 623                           ipw_error_desc(error->elem[i].desc),
 624                           error->elem[i].time,
 625                           error->elem[i].blink1,
 626                           error->elem[i].blink2,
 627                           error->elem[i].link1,
 628                           error->elem[i].link2, error->elem[i].data);
 629         for (i = 0; i < error->log_len; i++)
 630                 IPW_ERROR("%i\t0x%08x\t%i\n",
 631                           error->log[i].time,
 632                           error->log[i].data, error->log[i].event);
 633 }
 634
 635 static inline int ipw_is_init(struct ipw_priv *priv)
 636 {
 637         return (priv->status & STATUS_INIT) ? 1 : 0;
 638 }
 639
 640 static int ipw_get_ordinal(struct ipw_priv *priv, u32 ord, void *val, u32 * len)
 641 {
 642         u32 addr, field_info, field_len, field_count, total_len;
 643
 644         IPW_DEBUG_ORD("ordinal = %i\n", ord);
 645
 646         if (!priv || !val || !len) {
 647                 IPW_DEBUG_ORD("Invalid argument\n");
 648                 return -EINVAL;
 649         }
 650
 651         /* verify device ordinal tables have been initialized */
 652         if (!priv->table0_addr || !priv->table1_addr || !priv->table2_addr) {
 653                 IPW_DEBUG_ORD("Access ordinals before initialization\n");
 654                 return -EINVAL;
 655         }
 656
 657         switch (IPW_ORD_TABLE_ID_MASK & ord) {
 658         case IPW_ORD_TABLE_0_MASK:
 659                 /*
 660                  * TABLE 0: Direct access to a table of 32 bit values
 661                  *
 662                  * This is a very simple table with the data directly
 663                  * read from the table
 664                  */
 665
 666                 /* remove the table id from the ordinal */
 667                 ord &= IPW_ORD_TABLE_VALUE_MASK;
 668
 669                 /* boundary check */
 670                 if (ord > priv->table0_len) {
 671                         IPW_DEBUG_ORD("ordinal value (%i) longer then "
 672                                       "max (%i)\n", ord, priv->table0_len);
 673                         return -EINVAL;
 674                 }
 675
 676                 /* verify we have enough room to store the value */
 677                 if (*len < sizeof(u32)) {
 678                         IPW_DEBUG_ORD("ordinal buffer length too small, "
 679                                       "need %zd\n", sizeof(u32));
 680                         return -EINVAL;
 681                 }
 682
 683                 IPW_DEBUG_ORD("Reading TABLE0[%i] from offset 0x%08x\n",
 684                               ord, priv->table0_addr + (ord << 2));
 685
 686                 *len = sizeof(u32);
 687                 ord <<= 2;
 688                 *((u32 *) val) = ipw_read32(priv, priv->table0_addr + ord);
 689                 break;
 690
 691         case IPW_ORD_TABLE_1_MASK:
 692                 /*
 693                  * TABLE 1: Indirect access to a table of 32 bit values
 694                  *
 695                  * This is a fairly large table of u32 values each
 696                  * representing starting addr for the data (which is
 697                  * also a u32)
 698                  */
 699
 700                 /* remove the table id from the ordinal */
 701                 ord &= IPW_ORD_TABLE_VALUE_MASK;
 702
 703                 /* boundary check */
 704                 if (ord > priv->table1_len) {
 705                         IPW_DEBUG_ORD("ordinal value too long\n");
 706                         return -EINVAL;
 707                 }
 708
 709                 /* verify we have enough room to store the value */
 710                 if (*len < sizeof(u32)) {
 711                         IPW_DEBUG_ORD("ordinal buffer length too small, "
 712                                       "need %zd\n", sizeof(u32));
 713                         return -EINVAL;
 714                 }
 715
 716                 *((u32 *) val) =
 717                     ipw_read_reg32(priv, (priv->table1_addr + (ord << 2)));
 718                 *len = sizeof(u32);
 719                 break;
 720
 721         case IPW_ORD_TABLE_2_MASK:
 722                 /*
 723                  * TABLE 2: Indirect access to a table of variable sized values
 724                  *
 725                  * This table consist of six values, each containing
 726                  *     - dword containing the starting offset of the data
 727                  *     - dword containing the lengh in the first 16bits
 728                  *       and the count in the second 16bits
 729                  */
 730
 731                 /* remove the table id from the ordinal */
 732                 ord &= IPW_ORD_TABLE_VALUE_MASK;
 733
 734                 /* boundary check */
 735                 if (ord > priv->table2_len) {
 736                         IPW_DEBUG_ORD("ordinal value too long\n");
 737                         return -EINVAL;
 738                 }
 739
 740                 /* get the address of statistic */
 741                 addr = ipw_read_reg32(priv, priv->table2_addr + (ord << 3));
 742
 743                 /* get the second DW of statistics ;
 744                  * two 16-bit words - first is length, second is count */
 745                 field_info =
 746                     ipw_read_reg32(priv,
 747                                    priv->table2_addr + (ord << 3) +
 748                                    sizeof(u32));
 749
 750                 /* get each entry length */
 751                 field_len = *((u16 *) & field_info);
 752
 753                 /* get number of entries */
 754                 field_count = *(((u16 *) & field_info) + 1);
 755
 756                 /* abort if not enought memory */
 757                 total_len = field_len * field_count;
 758                 if (total_len > *len) {
 759                         *len = total_len;
 760                         return -EINVAL;
 761                 }
 762
 763                 *len = total_len;
 764                 if (!total_len)
 765                         return 0;
 766
 767                 IPW_DEBUG_ORD("addr = 0x%08x, total_len = %i, "
 768                               "field_info = 0x%08x\n",
 769                               addr, total_len, field_info);
 770                 ipw_read_indirect(priv, addr, val, total_len);
 771                 break;
 772
 773         default:
 774                 IPW_DEBUG_ORD("Invalid ordinal!\n");
 775                 return -EINVAL;
 776
 777         }
 778
 779         return 0;
 780 }
 781
 782 static void ipw_init_ordinals(struct ipw_priv *priv)
 783 {
 784         priv->table0_addr = IPW_ORDINALS_TABLE_LOWER;
 785         priv->table0_len = ipw_read32(priv, priv->table0_addr);
 786
 787         IPW_DEBUG_ORD("table 0 offset at 0x%08x, len = %i\n",
 788                       priv->table0_addr, priv->table0_len);
 789
 790         priv->table1_addr = ipw_read32(priv, IPW_ORDINALS_TABLE_1);
 791         priv->table1_len = ipw_read_reg32(priv, priv->table1_addr);
 792
 793         IPW_DEBUG_ORD("table 1 offset at 0x%08x, len = %i\n",
 794                       priv->table1_addr, priv->table1_len);
 795
 796         priv->table2_addr = ipw_read32(priv, IPW_ORDINALS_TABLE_2);
 797         priv->table2_len = ipw_read_reg32(priv, priv->table2_addr);
 798         priv->table2_len &= 0x0000ffff; /* use first two bytes */
 799
 800         IPW_DEBUG_ORD("table 2 offset at 0x%08x, len = %i\n",
 801                       priv->table2_addr, priv->table2_len);
 802
 803 }
 804
 805 static u32 ipw_register_toggle(u32 reg)
 806 {
 807         reg &= ~IPW_START_STANDBY;
 808         if (reg & IPW_GATE_ODMA)
 809                 reg &= ~IPW_GATE_ODMA;
 810         if (reg & IPW_GATE_IDMA)
 811                 reg &= ~IPW_GATE_IDMA;
 812         if (reg & IPW_GATE_ADMA)
 813                 reg &= ~IPW_GATE_ADMA;
 814         return reg;
 815 }
 816
 817 /*
 818  * LED behavior:
 819  * - On radio ON, turn on any LEDs that require to be on during start
 820  * - On initialization, start unassociated blink
 821  * - On association, disable unassociated blink
 822  * - On disassociation, start unassociated blink
 823  * - On radio OFF, turn off any LEDs started during radio on
 824  *
 825  */
 826 #define LD_TIME_LINK_ON msecs_to_jiffies(300)
 827 #define LD_TIME_LINK_OFF msecs_to_jiffies(2700)
 828 #define LD_TIME_ACT_ON msecs_to_jiffies(250)
 829
 830 static void ipw_led_link_on(struct ipw_priv *priv)
 831 {
 832         unsigned long flags;
 833         u32 led;
 834
 835         /* If configured to not use LEDs, or nic_type is 1,
 836          * then we don't toggle a LINK led */
 837         if (priv->config & CFG_NO_LED || priv->nic_type == EEPROM_NIC_TYPE_1)
 838                 return;
 839
 840         spin_lock_irqsave(&priv->lock, flags);
 841
 842         if (!(priv->status & STATUS_RF_KILL_MASK) &&
 843             !(priv->status & STATUS_LED_LINK_ON)) {
 844                 IPW_DEBUG_LED("Link LED On\n");
 845                 led = ipw_read_reg32(priv, IPW_EVENT_REG);
 846                 led |= priv->led_association_on;
 847
 848                 led = ipw_register_toggle(led);
 849
 850                 IPW_DEBUG_LED("Reg: 0x%08X\n", led);
 851                 ipw_write_reg32(priv, IPW_EVENT_REG, led);
 852
 853                 priv->status |= STATUS_LED_LINK_ON;
 854
 855                 /* If we aren't associated, schedule turning the LED off */
 856                 if (!(priv->status & STATUS_ASSOCIATED))
 857                         queue_delayed_work(priv->workqueue,
 858                                            &priv->led_link_off,
 859                                            LD_TIME_LINK_ON);
 860         }
 861
 862         spin_unlock_irqrestore(&priv->lock, flags);
 863 }
 864
 865 static void ipw_bg_led_link_on(struct work_struct *work)
 866 {
 867         struct ipw_priv *priv =
 868                 container_of(work, struct ipw_priv, led_link_on.work);
 869         mutex_lock(&priv->mutex);
 870         ipw_led_link_on(priv);
 871         mutex_unlock(&priv->mutex);
 872 }
 873
 874 static void ipw_led_link_off(struct ipw_priv *priv)
 875 {
 876         unsigned long flags;
 877         u32 led;
 878
 879         /* If configured not to use LEDs, or nic type is 1,
 880          * then we don't goggle the LINK led. */
 881         if (priv->config & CFG_NO_LED || priv->nic_type == EEPROM_NIC_TYPE_1)
 882                 return;
 883
 884         spin_lock_irqsave(&priv->lock, flags);
 885
 886         if (priv->status & STATUS_LED_LINK_ON) {
 887                 led = ipw_read_reg32(priv, IPW_EVENT_REG);
 888                 led &= priv->led_association_off;
 889                 led = ipw_register_toggle(led);
 890
 891                 IPW_DEBUG_LED("Reg: 0x%08X\n", led);
 892                 ipw_write_reg32(priv, IPW_EVENT_REG, led);
 893
 894                 IPW_DEBUG_LED("Link LED Off\n");
 895
 896                 priv->status &= ~STATUS_LED_LINK_ON;
 897
 898                 /* If we aren't associated and the radio is on, schedule
 899                  * turning the LED on (blink while unassociated) */
 900                 if (!(priv->status & STATUS_RF_KILL_MASK) &&
 901                     !(priv->status & STATUS_ASSOCIATED))
 902                         queue_delayed_work(priv->workqueue, &priv->led_link_on,
 903                                            LD_TIME_LINK_OFF);
 904
 905         }
 906
 907         spin_unlock_irqrestore(&priv->lock, flags);
 908 }
 909
 910 static void ipw_bg_led_link_off(struct work_struct *work)
 911 {
 912         struct ipw_priv *priv =
 913                 container_of(work, struct ipw_priv, led_link_off.work);
 914         mutex_lock(&priv->mutex);
 915         ipw_led_link_off(priv);
 916         mutex_unlock(&priv->mutex);
 917 }
 918
 919 static void __ipw_led_activity_on(struct ipw_priv *priv)
 920 {
 921         u32 led;
 922
 923         if (priv->config & CFG_NO_LED)
 924                 return;
 925
 926         if (priv->status & STATUS_RF_KILL_MASK)
 927                 return;
 928
 929         if (!(priv->status & STATUS_LED_ACT_ON)) {
 930                 led = ipw_read_reg32(priv, IPW_EVENT_REG);
 931                 led |= priv->led_activity_on;
 932
 933                 led = ipw_register_toggle(led);
 934
 935                 IPW_DEBUG_LED("Reg: 0x%08X\n", led);
 936                 ipw_write_reg32(priv, IPW_EVENT_REG, led);
 937
 938                 IPW_DEBUG_LED("Activity LED On\n");
 939
 940                 priv->status |= STATUS_LED_ACT_ON;
 941
 942                 cancel_delayed_work(&priv->led_act_off);
 943                 queue_delayed_work(priv->workqueue, &priv->led_act_off,
 944                                    LD_TIME_ACT_ON);
 945         } else {
 946                 /* Reschedule LED off for full time period */
 947                 cancel_delayed_work(&priv->led_act_off);
 948                 queue_delayed_work(priv->workqueue, &priv->led_act_off,
 949                                    LD_TIME_ACT_ON);
 950         }
 951 }
 952
 953 #if 0
 954 void ipw_led_activity_on(struct ipw_priv *priv)
 955 {
 956         unsigned long flags;
 957         spin_lock_irqsave(&priv->lock, flags);
 958         __ipw_led_activity_on(priv);
 959         spin_unlock_irqrestore(&priv->lock, flags);
 960 }
 961 #endif  /*  0  */
 962
 963 static void ipw_led_activity_off(struct ipw_priv *priv)
 964 {
 965         unsigned long flags;
 966         u32 led;
 967
 968         if (priv->config & CFG_NO_LED)
 969                 return;
 970
 971         spin_lock_irqsave(&priv->lock, flags);
 972
 973         if (priv->status & STATUS_LED_ACT_ON) {
 974                 led = ipw_read_reg32(priv, IPW_EVENT_REG);
 975                 led &= priv->led_activity_off;
 976
 977                 led = ipw_register_toggle(led);
 978
 979                 IPW_DEBUG_LED("Reg: 0x%08X\n", led);
 980                 ipw_write_reg32(priv, IPW_EVENT_REG, led);
 981
 982                 IPW_DEBUG_LED("Activity LED Off\n");
 983
 984                 priv->status &= ~STATUS_LED_ACT_ON;
 985         }
 986
 987         spin_unlock_irqrestore(&priv->lock, flags);
 988 }
 989
 990 static void ipw_bg_led_activity_off(struct work_struct *work)
 991 {
 992         struct ipw_priv *priv =
 993                 container_of(work, struct ipw_priv, led_act_off.work);
 994         mutex_lock(&priv->mutex);
 995         ipw_led_activity_off(priv);
 996         mutex_unlock(&priv->mutex);
 997 }
 998
 999 static void ipw_led_band_on(struct ipw_priv *priv)
1000 {
1001         unsigned long flags;
1002         u32 led;
1003
1004         /* Only nic type 1 supports mode LEDs */
1005         if (priv->config & CFG_NO_LED ||
1006             priv->nic_type != EEPROM_NIC_TYPE_1 || !priv->assoc_network)
1007                 return;
1008
1009         spin_lock_irqsave(&priv->lock, flags);
1010
1011         led = ipw_read_reg32(priv, IPW_EVENT_REG);
1012         if (priv->assoc_network->mode == IEEE_A) {
1013                 led |= priv->led_ofdm_on;
1014                 led &= priv->led_association_off;
1015                 IPW_DEBUG_LED("Mode LED On: 802.11a\n");
1016         } else if (priv->assoc_network->mode == IEEE_G) {
1017                 led |= priv->led_ofdm_on;
1018                 led |= priv->led_association_on;
1019                 IPW_DEBUG_LED("Mode LED On: 802.11g\n");
1020         } else {
1021                 led &= priv->led_ofdm_off;
1022                 led |= priv->led_association_on;
1023                 IPW_DEBUG_LED("Mode LED On: 802.11b\n");
1024         }
1025
1026         led = ipw_register_toggle(led);
1027
1028         IPW_DEBUG_LED("Reg: 0x%08X\n", led);
1029         ipw_write_reg32(priv, IPW_EVENT_REG, led);
1030
1031         spin_unlock_irqrestore(&priv->lock, flags);
1032 }
1033
1034 static void ipw_led_band_off(struct ipw_priv *priv)
1035 {
1036         unsigned long flags;
1037         u32 led;
1038
1039         /* Only nic type 1 supports mode LEDs */
1040         if (priv->config & CFG_NO_LED || priv->nic_type != EEPROM_NIC_TYPE_1)
1041                 return;
1042
1043         spin_lock_irqsave(&priv->lock, flags);
1044
1045         led = ipw_read_reg32(priv, IPW_EVENT_REG);
1046         led &= priv->led_ofdm_off;
1047         led &= priv->led_association_off;
1048
1049         led = ipw_register_toggle(led);
1050
1051         IPW_DEBUG_LED("Reg: 0x%08X\n", led);
1052         ipw_write_reg32(priv, IPW_EVENT_REG, led);
1053
1054         spin_unlock_irqrestore(&priv->lock, flags);
1055 }
1056
1057 static void ipw_led_radio_on(struct ipw_priv *priv)
1058 {
1059         ipw_led_link_on(priv);
1060 }
1061
1062 static void ipw_led_radio_off(struct ipw_priv *priv)
1063 {
1064         ipw_led_activity_off(priv);
1065         ipw_led_link_off(priv);
1066 }
1067
1068 static void ipw_led_link_up(struct ipw_priv *priv)
1069 {
1070         /* Set the Link Led on for all nic types */
1071         ipw_led_link_on(priv);
1072 }
1073
1074 static void ipw_led_link_down(struct ipw_priv *priv)
1075 {
1076         ipw_led_activity_off(priv);
1077         ipw_led_link_off(priv);
1078
1079         if (priv->status & STATUS_RF_KILL_MASK)
1080                 ipw_led_radio_off(priv);
1081 }
1082
1083 static void ipw_led_init(struct ipw_priv *priv)
1084 {
1085         priv->nic_type = priv->eeprom[EEPROM_NIC_TYPE];
1086
1087         /* Set the default PINs for the link and activity leds */
1088         priv->led_activity_on = IPW_ACTIVITY_LED;
1089         priv->led_activity_off = ~(IPW_ACTIVITY_LED);
1090
1091         priv->led_association_on = IPW_ASSOCIATED_LED;
1092         priv->led_association_off = ~(IPW_ASSOCIATED_LED);
1093
1094         /* Set the default PINs for the OFDM leds */
1095         priv->led_ofdm_on = IPW_OFDM_LED;
1096         priv->led_ofdm_off = ~(IPW_OFDM_LED);
1097
1098         switch (priv->nic_type) {
1099         case EEPROM_NIC_TYPE_1:
1100                 /* In this NIC type, the LEDs are reversed.... */
1101                 priv->led_activity_on = IPW_ASSOCIATED_LED;
1102                 priv->led_activity_off = ~(IPW_ASSOCIATED_LED);
1103                 priv->led_association_on = IPW_ACTIVITY_LED;
1104                 priv->led_association_off = ~(IPW_ACTIVITY_LED);
1105
1106                 if (!(priv->config & CFG_NO_LED))
1107                         ipw_led_band_on(priv);
1108
1109                 /* And we don't blink link LEDs for this nic, so
1110                  * just return here */
1111                 return;
1112
1113         case EEPROM_NIC_TYPE_3:
1114         case EEPROM_NIC_TYPE_2:
1115         case EEPROM_NIC_TYPE_4:
1116         case EEPROM_NIC_TYPE_0:
1117                 break;
1118
1119         default:
1120                 IPW_DEBUG_INFO("Unknown NIC type from EEPROM: %d\n",
1121                                priv->nic_type);
1122                 priv->nic_type = EEPROM_NIC_TYPE_0;
1123                 break;
1124         }
1125
1126         if (!(priv->config & CFG_NO_LED)) {
1127                 if (priv->status & STATUS_ASSOCIATED)
1128                         ipw_led_link_on(priv);
1129                 else
1130                         ipw_led_link_off(priv);
1131         }
1132 }
1133
1134 static void ipw_led_shutdown(struct ipw_priv *priv)
1135 {
1136         ipw_led_activity_off(priv);
1137         ipw_led_link_off(priv);
1138         ipw_led_band_off(priv);
1139         cancel_delayed_work(&priv->led_link_on);
1140         cancel_delayed_work(&priv->led_link_off);
1141         cancel_delayed_work(&priv->led_act_off);
1142 }
1143
1144 /*
1145  * The following adds a new attribute to the sysfs representation
1146  * of this device driver (i.e. a new file in /sys/bus/pci/drivers/ipw/)
1147  * used for controling the debug level.
1148  *
1149  * See the level definitions in ipw for details.
1150  */
1151 static ssize_t show_debug_level(struct device_driver *d, char *buf)
1152 {
1153         return sprintf(buf, "0x%08X\n", ipw_debug_level);
1154 }
1155
1156 static ssize_t store_debug_level(struct device_driver *d, const char *buf,
1157                                  size_t count)
1158 {
1159         char *p = (char *)buf;
1160         u32 val;
1161
1162         if (p[1] == 'x' || p[1] == 'X' || p[0] == 'x' || p[0] == 'X') {
1163                 p++;
1164                 if (p[0] == 'x' || p[0] == 'X')
1165                         p++;
1166                 val = simple_strtoul(p, &p, 16);
1167         } else
1168                 val = simple_strtoul(p, &p, 10);
1169         if (p == buf)
1170                 printk(KERN_INFO DRV_NAME
1171                        ": %s is not in hex or decimal form.\n", buf);
1172         else
1173                 ipw_debug_level = val;
1174
1175         return strnlen(buf, count);
1176 }
1177
1178 static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO,
1179                    show_debug_level, store_debug_level);
1180
1181 static inline u32 ipw_get_event_log_len(struct ipw_priv *priv)
1182 {
1183         /* length = 1st dword in log */
1184         return ipw_read_reg32(priv, ipw_read32(priv, IPW_EVENT_LOG));
1185 }
1186
1187 static void ipw_capture_event_log(struct ipw_priv *priv,
1188                                   u32 log_len, struct ipw_event *log)
1189 {
1190         u32 base;
1191
1192         if (log_len) {
1193                 base = ipw_read32(priv, IPW_EVENT_LOG);
1194                 ipw_read_indirect(priv, base + sizeof(base) + sizeof(u32),
1195                                   (u8 *) log, sizeof(*log) * log_len);
1196         }
1197 }
1198
1199 static struct ipw_fw_error *ipw_alloc_error_log(struct ipw_priv *priv)
1200 {
1201         struct ipw_fw_error *error;
1202         u32 log_len = ipw_get_event_log_len(priv);
1203         u32 base = ipw_read32(priv, IPW_ERROR_LOG);
1204         u32 elem_len = ipw_read_reg32(priv, base);
1205
1206         error = kmalloc(sizeof(*error) +
1207                         sizeof(*error->elem) * elem_len +
1208                         sizeof(*error->log) * log_len, GFP_ATOMIC);
1209         if (!error) {
1210                 IPW_ERROR("Memory allocation for firmware error log "
1211                           "failed.\n");
1212                 return NULL;
1213         }
1214         error->jiffies = jiffies;
1215         error->status = priv->status;
1216         error->config = priv->config;
1217         error->elem_len = elem_len;
1218         error->log_len = log_len;
1219         error->elem = (struct ipw_error_elem *)error->payload;
1220         error->log = (struct ipw_event *)(error->elem + elem_len);
1221
1222         ipw_capture_event_log(priv, log_len, error->log);
1223
1224         if (elem_len)
1225                 ipw_read_indirect(priv, base + sizeof(base), (u8 *) error->elem,
1226                                   sizeof(*error->elem) * elem_len);
1227
1228         return error;
1229 }
1230
1231 static ssize_t show_event_log(struct device *d,
1232                               struct device_attribute *attr, char *buf)
1233 {
1234         struct ipw_priv *priv = dev_get_drvdata(d);
1235         u32 log_len = ipw_get_event_log_len(priv);
1236         u32 log_size;
1237         struct ipw_event *log;
1238         u32 len = 0, i;
1239
1240         /* not using min() because of its strict type checking */
1241         log_size = PAGE_SIZE / sizeof(*log) > log_len ?
1242                         sizeof(*log) * log_len : PAGE_SIZE;
1243         log = kzalloc(log_size, GFP_KERNEL);
1244         if (!log) {
1245                 IPW_ERROR("Unable to allocate memory for log\n");
1246                 return 0;
1247         }
1248         log_len = log_size / sizeof(*log);
1249         ipw_capture_event_log(priv, log_len, log);
1250
1251         len += snprintf(buf + len, PAGE_SIZE - len, "%08X", log_len);
1252         for (i = 0; i < log_len; i++)
1253                 len += snprintf(buf + len, PAGE_SIZE - len,
1254                                 "\n%08X%08X%08X",
1255                                 log[i].time, log[i].event, log[i].data);
1256         len += snprintf(buf + len, PAGE_SIZE - len, "\n");
1257         kfree(log);
1258         return len;
1259 }
1260
1261 static DEVICE_ATTR(event_log, S_IRUGO, show_event_log, NULL);
1262
1263 static ssize_t show_error(struct device *d,
1264                           struct device_attribute *attr, char *buf)
1265 {
1266         struct ipw_priv *priv = dev_get_drvdata(d);
1267         u32 len = 0, i;
1268         if (!priv->error)
1269                 return 0;
1270         len += snprintf(buf + len, PAGE_SIZE - len,
1271                         "%08lX%08X%08X%08X",
1272                         priv->error->jiffies,
1273                         priv->error->status,
1274                         priv->error->config, priv->error->elem_len);
1275         for (i = 0; i < priv->error->elem_len; i++)
1276                 len += snprintf(buf + len, PAGE_SIZE - len,
1277                                 "\n%08X%08X%08X%08X%08X%08X%08X",
1278                                 priv->error->elem[i].time,
1279                                 priv->error->elem[i].desc,
1280                                 priv->error->elem[i].blink1,
1281                                 priv->error->elem[i].blink2,
1282                                 priv->error->elem[i].link1,
1283                                 priv->error->elem[i].link2,
1284                                 priv->error->elem[i].data);
1285
1286         len += snprintf(buf + len, PAGE_SIZE - len,
1287                         "\n%08X", priv->error->log_len);
1288         for (i = 0; i < priv->error->log_len; i++)
1289                 len += snprintf(buf + len, PAGE_SIZE - len,
1290                                 "\n%08X%08X%08X",
1291                                 priv->error->log[i].time,
1292                                 priv->error->log[i].event,
1293                                 priv->error->log[i].data);
1294         len += snprintf(buf + len, PAGE_SIZE - len, "\n");
1295         return len;
1296 }
1297
1298 static ssize_t clear_error(struct device *d,
1299                            struct device_attribute *attr,
1300                            const char *buf, size_t count)
1301 {
1302         struct ipw_priv *priv = dev_get_drvdata(d);
1303
1304         kfree(priv->error);
1305         priv->error = NULL;
1306         return count;
1307 }
1308
1309 static DEVICE_ATTR(error, S_IRUGO | S_IWUSR, show_error, clear_error);
1310
1311 static ssize_t show_cmd_log(struct device *d,
1312                             struct device_attribute *attr, char *buf)
1313 {
1314         struct ipw_priv *priv = dev_get_drvdata(d);
1315         u32 len = 0, i;
1316         if (!priv->cmdlog)
1317                 return 0;
1318         for (i = (priv->cmdlog_pos + 1) % priv->cmdlog_len;
1319              (i != priv->cmdlog_pos) && (PAGE_SIZE - len);
1320              i = (i + 1) % priv->cmdlog_len) {
1321                 len +=
1322                     snprintf(buf + len, PAGE_SIZE - len,
1323                              "\n%08lX%08X%08X%08X\n", priv->cmdlog[i].jiffies,
1324                              priv->cmdlog[i].retcode, priv->cmdlog[i].cmd.cmd,
1325                              priv->cmdlog[i].cmd.len);
1326                 len +=
1327                     snprintk_buf(buf + len, PAGE_SIZE - len,
1328                                  (u8 *) priv->cmdlog[i].cmd.param,
1329                                  priv->cmdlog[i].cmd.len);
1330                 len += snprintf(buf + len, PAGE_SIZE - len, "\n");
1331         }
1332         len += snprintf(buf + len, PAGE_SIZE - len, "\n");
1333         return len;
1334 }
1335
1336 static DEVICE_ATTR(cmd_log, S_IRUGO, show_cmd_log, NULL);
1337
1338 #ifdef CONFIG_IPW2200_PROMISCUOUS
1339 static void ipw_prom_free(struct ipw_priv *priv);
1340 static int ipw_prom_alloc(struct ipw_priv *priv);
1341 static ssize_t store_rtap_iface(struct device *d,
1342                          struct device_attribute *attr,
1343                          const char *buf, size_t count)
1344 {
1345         struct ipw_priv *priv = dev_get_drvdata(d);
1346         int rc = 0;
1347
1348         if (count < 1)
1349                 return -EINVAL;
1350
1351         switch (buf[0]) {
1352         case '0':
1353                 if (!rtap_iface)
1354                         return count;
1355
1356                 if (netif_running(priv->prom_net_dev)) {
1357                         IPW_WARNING("Interface is up.  Cannot unregister.\n");
1358                         return count;
1359                 }
1360
1361                 ipw_prom_free(priv);
1362                 rtap_iface = 0;
1363                 break;
1364
1365         case '1':
1366                 if (rtap_iface)
1367                         return count;
1368
1369                 rc = ipw_prom_alloc(priv);
1370                 if (!rc)
1371                         rtap_iface = 1;
1372                 break;
1373
1374         default:
1375                 return -EINVAL;
1376         }
1377
1378         if (rc) {
1379                 IPW_ERROR("Failed to register promiscuous network "
1380                           "device (error %d).\n", rc);
1381         }
1382
1383         return count;
1384 }
1385
1386 static ssize_t show_rtap_iface(struct device *d,
1387                         struct device_attribute *attr,
1388                         char *buf)
1389 {
1390         struct ipw_priv *priv = dev_get_drvdata(d);
1391         if (rtap_iface)
1392                 return sprintf(buf, "%s", priv->prom_net_dev->name);
1393         else {
1394                 buf[0] = '-';
1395                 buf[1] = '1';
1396                 buf[2] = '\0';
1397                 return 3;
1398         }
1399 }
1400
1401 static DEVICE_ATTR(rtap_iface, S_IWUSR | S_IRUSR, show_rtap_iface,
1402                    store_rtap_iface);
1403
1404 static ssize_t store_rtap_filter(struct device *d,
1405                          struct device_attribute *attr,
1406                          const char *buf, size_t count)
1407 {
1408         struct ipw_priv *priv = dev_get_drvdata(d);
1409
1410         if (!priv->prom_priv) {
1411                 IPW_ERROR("Attempting to set filter without "
1412                           "rtap_iface enabled.\n");
1413                 return -EPERM;
1414         }
1415
1416         priv->prom_priv->filter = simple_strtol(buf, NULL, 0);
1417
1418         IPW_DEBUG_INFO("Setting rtap filter to " BIT_FMT16 "\n",
1419                        BIT_ARG16(priv->prom_priv->filter));
1420
1421         return count;
1422 }
1423
1424 static ssize_t show_rtap_filter(struct device *d,
1425                         struct device_attribute *attr,
1426                         char *buf)
1427 {
1428         struct ipw_priv *priv = dev_get_drvdata(d);
1429         return sprintf(buf, "0x%04X",
1430                        priv->prom_priv ? priv->prom_priv->filter : 0);
1431 }
1432
1433 static DEVICE_ATTR(rtap_filter, S_IWUSR | S_IRUSR, show_rtap_filter,
1434                    store_rtap_filter);
1435 #endif
1436
1437 static ssize_t show_scan_age(struct device *d, struct device_attribute *attr,
1438                              char *buf)
1439 {
1440         struct ipw_priv *priv = dev_get_drvdata(d);
1441         return sprintf(buf, "%d\n", priv->ieee->scan_age);
1442 }
1443
1444 static ssize_t store_scan_age(struct device *d, struct device_attribute *attr,
1445                               const char *buf, size_t count)
1446 {
1447         struct ipw_priv *priv = dev_get_drvdata(d);
1448         struct net_device *dev = priv->net_dev;
1449         char buffer[] = "00000000";
1450         unsigned long len =
1451             (sizeof(buffer) - 1) > count ? count : sizeof(buffer) - 1;
1452         unsigned long val;
1453         char *p = buffer;
1454
1455         IPW_DEBUG_INFO("enter\n");
1456
1457         strncpy(buffer, buf, len);
1458         buffer[len] = 0;
1459
1460         if (p[1] == 'x' || p[1] == 'X' || p[0] == 'x' || p[0] == 'X') {
1461                 p++;
1462                 if (p[0] == 'x' || p[0] == 'X')
1463                         p++;
1464                 val = simple_strtoul(p, &p, 16);
1465         } else
1466                 val = simple_strtoul(p, &p, 10);
1467         if (p == buffer) {
1468                 IPW_DEBUG_INFO("%s: user supplied invalid value.\n", dev->name);
1469         } else {
1470                 priv->ieee->scan_age = val;
1471                 IPW_DEBUG_INFO("set scan_age = %u\n", priv->ieee->scan_age);
1472         }
1473
1474         IPW_DEBUG_INFO("exit\n");
1475         return len;
1476 }
1477
1478 static DEVICE_ATTR(scan_age, S_IWUSR | S_IRUGO, show_scan_age, store_scan_age);
1479
1480 static ssize_t show_led(struct device *d, struct device_attribute *attr,
1481                         char *buf)
1482 {
1483         struct ipw_priv *priv = dev_get_drvdata(d);
1484         return sprintf(buf, "%d\n", (priv->config & CFG_NO_LED) ? 0 : 1);
1485 }
1486
1487 static ssize_t store_led(struct device *d, struct device_attribute *attr,
1488                          const char *buf, size_t count)
1489 {
1490         struct ipw_priv *priv = dev_get_drvdata(d);
1491
1492         IPW_DEBUG_INFO("enter\n");
1493
1494         if (count == 0)
1495                 return 0;
1496
1497         if (*buf == 0) {
1498                 IPW_DEBUG_LED("Disabling LED control.\n");
1499                 priv->config |= CFG_NO_LED;
1500                 ipw_led_shutdown(priv);
1501         } else {
1502                 IPW_DEBUG_LED("Enabling LED control.\n");
1503                 priv->config &= ~CFG_NO_LED;
1504                 ipw_led_init(priv);
1505         }
1506
1507         IPW_DEBUG_INFO("exit\n");
1508         return count;
1509 }
1510
1511 static DEVICE_ATTR(led, S_IWUSR | S_IRUGO, show_led, store_led);
1512
1513 static ssize_t show_status(struct device *d,
1514                            struct device_attribute *attr, char *buf)
1515 {
1516         struct ipw_priv *p = d->driver_data;
1517         return sprintf(buf, "0x%08x\n", (int)p->status);
1518 }
1519
1520 static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
1521
1522 static ssize_t show_cfg(struct device *d, struct device_attribute *attr,
1523                         char *buf)
1524 {
1525         struct ipw_priv *p = d->driver_data;
1526         return sprintf(buf, "0x%08x\n", (int)p->config);
1527 }
1528
1529 static DEVICE_ATTR(cfg, S_IRUGO, show_cfg, NULL);
1530
1531 static ssize_t show_nic_type(struct device *d,
1532                              struct device_attribute *attr, char *buf)
1533 {
1534         struct ipw_priv *priv = d->driver_data;
1535         return sprintf(buf, "TYPE: %d\n", priv->nic_type);
1536 }
1537
1538 static DEVICE_ATTR(nic_type, S_IRUGO, show_nic_type, NULL);
1539
1540 static ssize_t show_ucode_version(struct device *d,
1541                                   struct device_attribute *attr, char *buf)
1542 {
1543         u32 len = sizeof(u32), tmp = 0;
1544         struct ipw_priv *p = d->driver_data;
1545
1546         if (ipw_get_ordinal(p, IPW_ORD_STAT_UCODE_VERSION, &tmp, &len))
1547                 return 0;
1548
1549         return sprintf(buf, "0x%08x\n", tmp);
1550 }
1551
1552 static DEVICE_ATTR(ucode_version, S_IWUSR | S_IRUGO, show_ucode_version, NULL);
1553
1554 static ssize_t show_rtc(struct device *d, struct device_attribute *attr,
1555                         char *buf)
1556 {
1557         u32 len = sizeof(u32), tmp = 0;
1558         struct ipw_priv *p = d->driver_data;
1559
1560         if (ipw_get_ordinal(p, IPW_ORD_STAT_RTC, &tmp, &len))
1561                 return 0;
1562
1563         return sprintf(buf, "0x%08x\n", tmp);
1564 }
1565
1566 static DEVICE_ATTR(rtc, S_IWUSR | S_IRUGO, show_rtc, NULL);
1567
1568 /*
1569  * Add a device attribute to view/control the delay between eeprom
1570  * operations.
1571  */
1572 static ssize_t show_eeprom_delay(struct device *d,
1573                                  struct device_attribute *attr, char *buf)
1574 {
1575         int n = ((struct ipw_priv *)d->driver_data)->eeprom_delay;
1576         return sprintf(buf, "%i\n", n);
1577 }
1578 static ssize_t store_eeprom_delay(struct device *d,
1579                                   struct device_attribute *attr,
1580                                   const char *buf, size_t count)
1581 {
1582         struct ipw_priv *p = d->driver_data;
1583         sscanf(buf, "%i", &p->eeprom_delay);
1584         return strnlen(buf, count);
1585 }
1586
1587 static DEVICE_ATTR(eeprom_delay, S_IWUSR | S_IRUGO,
1588                    show_eeprom_delay, store_eeprom_delay);
1589
1590 static ssize_t show_command_event_reg(struct device *d,
1591                                       struct device_attribute *attr, char *buf)
1592 {
1593         u32 reg = 0;
1594         struct ipw_priv *p = d->driver_data;
1595
1596         reg = ipw_read_reg32(p, IPW_INTERNAL_CMD_EVENT);
1597         return sprintf(buf, "0x%08x\n", reg);
1598 }
1599 static ssize_t store_command_event_reg(struct device *d,
1600                                        struct device_attribute *attr,
1601                                        const char *buf, size_t count)
1602 {
1603         u32 reg;
1604         struct ipw_priv *p = d->driver_data;
1605
1606         sscanf(buf, "%x", &reg);
1607         ipw_write_reg32(p, IPW_INTERNAL_CMD_EVENT, reg);
1608         return strnlen(buf, count);
1609 }
1610
1611 static DEVICE_ATTR(command_event_reg, S_IWUSR | S_IRUGO,
1612                    show_command_event_reg, store_command_event_reg);
1613
1614 static ssize_t show_mem_gpio_reg(struct device *d,
1615                                  struct device_attribute *attr, char *buf)
1616 {
1617         u32 reg = 0;
1618         struct ipw_priv *p = d->driver_data;
1619
1620         reg = ipw_read_reg32(p, 0x301100);
1621         return sprintf(buf, "0x%08x\n", reg);
1622 }
1623 static ssize_t store_mem_gpio_reg(struct device *d,
1624                                   struct device_attribute *attr,
1625                                   const char *buf, size_t count)
1626 {
1627         u32 reg;
1628         struct ipw_priv *p = d->driver_data;
1629
1630         sscanf(buf, "%x", &reg);
1631         ipw_write_reg32(p, 0x301100, reg);
1632         return strnlen(buf, count);
1633 }
1634
1635 static DEVICE_ATTR(mem_gpio_reg, S_IWUSR | S_IRUGO,
1636                    show_mem_gpio_reg, store_mem_gpio_reg);
1637
1638 static ssize_t show_indirect_dword(struct device *d,
1639                                    struct device_attribute *attr, char *buf)
1640 {
1641         u32 reg = 0;
1642         struct ipw_priv *priv = d->driver_data;
1643
1644         if (priv->status & STATUS_INDIRECT_DWORD)
1645                 reg = ipw_read_reg32(priv, priv->indirect_dword);
1646         else
1647                 reg = 0;
1648
1649         return sprintf(buf, "0x%08x\n", reg);
1650 }
1651 static ssize_t store_indirect_dword(struct device *d,
1652                                     struct device_attribute *attr,
1653                                     const char *buf, size_t count)
1654 {
1655         struct ipw_priv *priv = d->driver_data;
1656
1657         sscanf(buf, "%x", &priv->indirect_dword);
1658         priv->status |= STATUS_INDIRECT_DWORD;
1659         return strnlen(buf, count);
1660 }
1661
1662 static DEVICE_ATTR(indirect_dword, S_IWUSR | S_IRUGO,
1663                    show_indirect_dword, store_indirect_dword);
1664
1665 static ssize_t show_indirect_byte(struct device *d,
1666                                   struct device_attribute *attr, char *buf)
1667 {
1668         u8 reg = 0;
1669         struct ipw_priv *priv = d->driver_data;
1670
1671         if (priv->status & STATUS_INDIRECT_BYTE)
1672                 reg = ipw_read_reg8(priv, priv->indirect_byte);
1673         else
1674                 reg = 0;
1675
1676         return sprintf(buf, "0x%02x\n", reg);
1677 }
1678 static ssize_t store_indirect_byte(struct device *d,
1679                                    struct device_attribute *attr,
1680                                    const char *buf, size_t count)
1681 {
1682         struct ipw_priv *priv = d->driver_data;
1683
1684         sscanf(buf, "%x", &priv->indirect_byte);
1685         priv->status |= STATUS_INDIRECT_BYTE;
1686         return strnlen(buf, count);
1687 }
1688
1689 static DEVICE_ATTR(indirect_byte, S_IWUSR | S_IRUGO,
1690                    show_indirect_byte, store_indirect_byte);
1691
1692 static ssize_t show_direct_dword(struct device *d,
1693                                  struct device_attribute *attr, char *buf)
1694 {
1695         u32 reg = 0;
1696         struct ipw_priv *priv = d->driver_data;
1697
1698         if (priv->status & STATUS_DIRECT_DWORD)
1699                 reg = ipw_read32(priv, priv->direct_dword);
1700         else
1701                 reg = 0;
1702
1703         return sprintf(buf, "0x%08x\n", reg);
1704 }
1705 static ssize_t store_direct_dword(struct device *d,
1706                                   struct device_attribute *attr,
1707                                   const char *buf, size_t count)
1708 {
1709         struct ipw_priv *priv = d->driver_data;
1710
1711         sscanf(buf, "%x", &priv->direct_dword);
1712         priv->status |= STATUS_DIRECT_DWORD;
1713         return strnlen(buf, count);
1714 }
1715
1716 static DEVICE_ATTR(direct_dword, S_IWUSR | S_IRUGO,
1717                    show_direct_dword, store_direct_dword);
1718
1719 static int rf_kill_active(struct ipw_priv *priv)
1720 {
1721         if (0 == (ipw_read32(priv, 0x30) & 0x10000))
1722                 priv->status |= STATUS_RF_KILL_HW;
1723         else
1724                 priv->status &= ~STATUS_RF_KILL_HW;
1725
1726         return (priv->status & STATUS_RF_KILL_HW) ? 1 : 0;
1727 }
1728
1729 static ssize_t show_rf_kill(struct device *d, struct device_attribute *attr,
1730                             char *buf)
1731 {
1732         /* 0 - RF kill not enabled
1733            1 - SW based RF kill active (sysfs)
1734            2 - HW based RF kill active
1735            3 - Both HW and SW baed RF kill active */
1736         struct ipw_priv *priv = d->driver_data;
1737         int val = ((priv->status & STATUS_RF_KILL_SW) ? 0x1 : 0x0) |
1738             (rf_kill_active(priv) ? 0x2 : 0x0);
1739         return sprintf(buf, "%i\n", val);
1740 }
1741
1742 static int ipw_radio_kill_sw(struct ipw_priv *priv, int disable_radio)
1743 {
1744         if ((disable_radio ? 1 : 0) ==
1745             ((priv->status & STATUS_RF_KILL_SW) ? 1 : 0))
1746                 return 0;
1747
1748         IPW_DEBUG_RF_KILL("Manual SW RF Kill set to: RADIO  %s\n",
1749                           disable_radio ? "OFF" : "ON");
1750
1751         if (disable_radio) {
1752                 priv->status |= STATUS_RF_KILL_SW;
1753
1754                 if (priv->workqueue) {
1755                         cancel_delayed_work(&priv->request_scan);
1756                         cancel_delayed_work(&priv->scan_event);
1757                 }
1758                 queue_work(priv->workqueue, &priv->down);
1759         } else {
1760                 priv->status &= ~STATUS_RF_KILL_SW;
1761                 if (rf_kill_active(priv)) {
1762                         IPW_DEBUG_RF_KILL("Can not turn radio back on - "
1763                                           "disabled by HW switch\n");
1764                         /* Make sure the RF_KILL check timer is running */
1765                         cancel_delayed_work(&priv->rf_kill);
1766                         queue_delayed_work(priv->workqueue, &priv->rf_kill,
1767                                            round_jiffies_relative(2 * HZ));
1768                 } else
1769                         queue_work(priv->workqueue, &priv->up);
1770         }
1771
1772         return 1;
1773 }
1774
1775 static ssize_t store_rf_kill(struct device *d, struct device_attribute *attr,
1776                              const char *buf, size_t count)
1777 {
1778         struct ipw_priv *priv = d->driver_data;
1779
1780         ipw_radio_kill_sw(priv, buf[0] == '1');
1781
1782         return count;
1783 }
1784
1785 static DEVICE_ATTR(rf_kill, S_IWUSR | S_IRUGO, show_rf_kill, store_rf_kill);
1786
1787 static ssize_t show_speed_scan(struct device *d, struct device_attribute *attr,
1788                                char *buf)
1789 {
1790         struct ipw_priv *priv = (struct ipw_priv *)d->driver_data;
1791         int pos = 0, len = 0;
1792         if (priv->config & CFG_SPEED_SCAN) {
1793                 while (priv->speed_scan[pos] != 0)
1794                         len += sprintf(&buf[len], "%d ",
1795                                        priv->speed_scan[pos++]);
1796                 return len + sprintf(&buf[len], "\n");
1797         }
1798
1799         return sprintf(buf, "0\n");
1800 }
1801
1802 static ssize_t store_speed_scan(struct device *d, struct device_attribute *attr,
1803                                 const char *buf, size_t count)
1804 {
1805         struct ipw_priv *priv = (struct ipw_priv *)d->driver_data;
1806         int channel, pos = 0;
1807         const char *p = buf;
1808
1809         /* list of space separated channels to scan, optionally ending with 0 */
1810         while ((channel = simple_strtol(p, NULL, 0))) {
1811                 if (pos == MAX_SPEED_SCAN - 1) {
1812                         priv->speed_scan[pos] = 0;
1813                         break;
1814                 }
1815
1816                 if (ieee80211_is_valid_channel(priv->ieee, channel))
1817                         priv->speed_scan[pos++] = channel;
1818                 else
1819                         IPW_WARNING("Skipping invalid channel request: %d\n",
1820                                     channel);
1821                 p = strchr(p, ' ');
1822                 if (!p)
1823                         break;
1824                 while (*p == ' ' || *p == '\t')
1825                         p++;
1826         }
1827
1828         if (pos == 0)
1829                 priv->config &= ~CFG_SPEED_SCAN;
1830         else {
1831                 priv->speed_scan_pos = 0;
1832                 priv->config |= CFG_SPEED_SCAN;
1833         }
1834
1835         return count;
1836 }
1837
1838 static DEVICE_ATTR(speed_scan, S_IWUSR | S_IRUGO, show_speed_scan,
1839                    store_speed_scan);
1840
1841 static ssize_t show_net_stats(struct device *d, struct device_attribute *attr,
1842                               char *buf)
1843 {
1844         struct ipw_priv *priv = (struct ipw_priv *)d->driver_data;
1845         return sprintf(buf, "%c\n", (priv->config & CFG_NET_STATS) ? '1' : '0');
1846 }
1847
1848 static ssize_t store_net_stats(struct device *d, struct device_attribute *attr,
1849                                const char *buf, size_t count)
1850 {
1851         struct ipw_priv *priv = (struct ipw_priv *)d->driver_data;
1852         if (buf[0] == '1')
1853                 priv->config |= CFG_NET_STATS;
1854         else
1855                 priv->config &= ~CFG_NET_STATS;
1856
1857         return count;
1858 }
1859
1860 static DEVICE_ATTR(net_stats, S_IWUSR | S_IRUGO,
1861                    show_net_stats, store_net_stats);
1862
1863 static ssize_t show_channels(struct device *d,
1864                              struct device_attribute *attr,
1865                              char *buf)
1866 {
1867         struct ipw_priv *priv = dev_get_drvdata(d);
1868         const struct ieee80211_geo *geo = ieee80211_get_geo(priv->ieee);
1869         int len = 0, i;
1870
1871         len = sprintf(&buf[len],
1872                       "Displaying %d channels in 2.4Ghz band "
1873                       "(802.11bg):\n", geo->bg_channels);
1874
1875         for (i = 0; i < geo->bg_channels; i++) {
1876                 len += sprintf(&buf[len], "%d: BSS%s%s, %s, Band %s.\n",
1877                                geo->bg[i].channel,
1878                                geo->bg[i].flags & IEEE80211_CH_RADAR_DETECT ?
1879                                " (radar spectrum)" : "",
1880                                ((geo->bg[i].flags & IEEE80211_CH_NO_IBSS) ||
1881                                 (geo->bg[i].flags & IEEE80211_CH_RADAR_DETECT))
1882                                ? "" : ", IBSS",
1883                                geo->bg[i].flags & IEEE80211_CH_PASSIVE_ONLY ?
1884                                "passive only" : "active/passive",
1885                                geo->bg[i].flags & IEEE80211_CH_B_ONLY ?
1886                                "B" : "B/G");
1887         }
1888
1889         len += sprintf(&buf[len],
1890                        "Displaying %d channels in 5.2Ghz band "
1891                        "(802.11a):\n", geo->a_channels);
1892         for (i = 0; i < geo->a_channels; i++) {
1893                 len += sprintf(&buf[len], "%d: BSS%s%s, %s.\n",
1894                                geo->a[i].channel,
1895                                geo->a[i].flags & IEEE80211_CH_RADAR_DETECT ?
1896                                " (radar spectrum)" : "",
1897                                ((geo->a[i].flags & IEEE80211_CH_NO_IBSS) ||
1898                                 (geo->a[i].flags & IEEE80211_CH_RADAR_DETECT))
1899                                ? "" : ", IBSS",
1900                                geo->a[i].flags & IEEE80211_CH_PASSIVE_ONLY ?
1901                                "passive only" : "active/passive");
1902         }
1903
1904         return len;
1905 }
1906
1907 static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
1908
1909 static void notify_wx_assoc_event(struct ipw_priv *priv)
1910 {
1911         union iwreq_data wrqu;
1912         wrqu.ap_addr.sa_family = ARPHRD_ETHER;
1913         if (priv->status & STATUS_ASSOCIATED)
1914                 memcpy(wrqu.ap_addr.sa_data, priv->bssid, ETH_ALEN);
1915         else
1916                 memset(wrqu.ap_addr.sa_data, 0, ETH_ALEN);
1917         wireless_send_event(priv->net_dev, SIOCGIWAP, &wrqu, NULL);
1918 }
1919
1920 static void ipw_irq_tasklet(struct ipw_priv *priv)
1921 {
1922         u32 inta, inta_mask, handled = 0;
1923         unsigned long flags;
1924         int rc = 0;
1925
1926         spin_lock_irqsave(&priv->irq_lock, flags);
1927
1928         inta = ipw_read32(priv, IPW_INTA_RW);
1929         inta_mask = ipw_read32(priv, IPW_INTA_MASK_R);
1930         inta &= (IPW_INTA_MASK_ALL & inta_mask);
1931
1932         /* Add any cached INTA values that need to be handled */
1933         inta |= priv->isr_inta;
1934
1935         spin_unlock_irqrestore(&priv->irq_lock, flags);
1936
1937         spin_lock_irqsave(&priv->lock, flags);
1938
1939         /* handle all the justifications for the interrupt */
1940         if (inta & IPW_INTA_BIT_RX_TRANSFER) {
1941                 ipw_rx(priv);
1942                 handled |= IPW_INTA_BIT_RX_TRANSFER;
1943         }
1944
1945         if (inta & IPW_INTA_BIT_TX_CMD_QUEUE) {
1946                 IPW_DEBUG_HC("Command completed.\n");
1947                 rc = ipw_queue_tx_reclaim(priv, &priv->txq_cmd, -1);
1948                 priv->status &= ~STATUS_HCMD_ACTIVE;
1949                 wake_up_interruptible(&priv->wait_command_queue);
1950                 handled |= IPW_INTA_BIT_TX_CMD_QUEUE;
1951         }
1952
1953         if (inta & IPW_INTA_BIT_TX_QUEUE_1) {
1954                 IPW_DEBUG_TX("TX_QUEUE_1\n");
1955                 rc = ipw_queue_tx_reclaim(priv, &priv->txq[0], 0);
1956                 handled |= IPW_INTA_BIT_TX_QUEUE_1;
1957         }
1958
1959         if (inta & IPW_INTA_BIT_TX_QUEUE_2) {
1960                 IPW_DEBUG_TX("TX_QUEUE_2\n");
1961                 rc = ipw_queue_tx_reclaim(priv, &priv->txq[1], 1);
1962                 handled |= IPW_INTA_BIT_TX_QUEUE_2;
1963         }
1964
1965         if (inta & IPW_INTA_BIT_TX_QUEUE_3) {
1966                 IPW_DEBUG_TX("TX_QUEUE_3\n");
1967                 rc = ipw_queue_tx_reclaim(priv, &priv->txq[2], 2);
1968                 handled |= IPW_INTA_BIT_TX_QUEUE_3;
1969         }
1970
1971         if (inta & IPW_INTA_BIT_TX_QUEUE_4) {
1972                 IPW_DEBUG_TX("TX_QUEUE_4\n");
1973                 rc = ipw_queue_tx_reclaim(priv, &priv->txq[3], 3);
1974                 handled |= IPW_INTA_BIT_TX_QUEUE_4;
1975         }
1976
1977         if (inta & IPW_INTA_BIT_STATUS_CHANGE) {
1978                 IPW_WARNING("STATUS_CHANGE\n");
1979                 handled |= IPW_INTA_BIT_STATUS_CHANGE;
1980         }
1981
1982         if (inta & IPW_INTA_BIT_BEACON_PERIOD_EXPIRED) {
1983                 IPW_WARNING("TX_PERIOD_EXPIRED\n");
1984                 handled |= IPW_INTA_BIT_BEACON_PERIOD_EXPIRED;
1985         }
1986
1987         if (inta & IPW_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE) {
1988                 IPW_WARNING("HOST_CMD_DONE\n");
1989                 handled |= IPW_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE;
1990         }
1991
1992         if (inta & IPW_INTA_BIT_FW_INITIALIZATION_DONE) {
1993                 IPW_WARNING("FW_INITIALIZATION_DONE\n");
1994                 handled |= IPW_INTA_BIT_FW_INITIALIZATION_DONE;
1995         }
1996
1997         if (inta & IPW_INTA_BIT_FW_CARD_DISABLE_PHY_OFF_DONE) {
1998                 IPW_WARNING("PHY_OFF_DONE\n");
1999                 handled |= IPW_INTA_BIT_FW_CARD_DISABLE_PHY_OFF_DONE;
2000         }
2001
2002         if (inta & IPW_INTA_BIT_RF_KILL_DONE) {
2003                 IPW_DEBUG_RF_KILL("RF_KILL_DONE\n");
2004                 priv->status |= STATUS_RF_KILL_HW;
2005                 wake_up_interruptible(&priv->wait_command_queue);
2006                 priv->status &= ~(STATUS_ASSOCIATED | STATUS_ASSOCIATING);
2007                 cancel_delayed_work(&priv->request_scan);
2008                 cancel_delayed_work(&priv->scan_event);
2009                 schedule_work(&priv->link_down);
2010                 queue_delayed_work(priv->workqueue, &priv->rf_kill, 2 * HZ);
2011                 handled |= IPW_INTA_BIT_RF_KILL_DONE;
2012         }
2013
2014         if (inta & IPW_INTA_BIT_FATAL_ERROR) {
2015                 IPW_WARNING("Firmware error detected.  Restarting.\n");
2016                 if (priv->error) {
2017                         IPW_DEBUG_FW("Sysfs 'error' log already exists.\n");
2018                         if (ipw_debug_level & IPW_DL_FW_ERRORS) {
2019                                 struct ipw_fw_error *error =
2020                                     ipw_alloc_error_log(priv);
2021                                 ipw_dump_error_log(priv, error);
2022                                 kfree(error);
2023                         }
2024                 } else {
2025                         priv->error = ipw_alloc_error_log(priv);
2026                         if (priv->error)
2027                                 IPW_DEBUG_FW("Sysfs 'error' log captured.\n");
2028                         else
2029                                 IPW_DEBUG_FW("Error allocating sysfs 'error' "
2030                                              "log.\n");
2031                         if (ipw_debug_level & IPW_DL_FW_ERRORS)
2032                                 ipw_dump_error_log(priv, priv->error);
2033                 }
2034
2035                 /* XXX: If hardware encryption is for WPA/WPA2,
2036                  * we have to notify the supplicant. */
2037                 if (priv->ieee->sec.encrypt) {
2038                         priv->status &= ~STATUS_ASSOCIATED;
2039                         notify_wx_assoc_event(priv);
2040                 }
2041
2042                 /* Keep the restart process from trying to send host
2043                  * commands by clearing the INIT status bit */
2044                 priv->status &= ~STATUS_INIT;
2045
2046                 /* Cancel currently queued command. */
2047                 priv->status &= ~STATUS_HCMD_ACTIVE;
2048                 wake_up_interruptible(&priv->wait_command_queue);
2049
2050                 queue_work(priv->workqueue, &priv->adapter_restart);
2051                 handled |= IPW_INTA_BIT_FATAL_ERROR;
2052         }
2053
2054         if (inta & IPW_INTA_BIT_PARITY_ERROR) {
2055                 IPW_ERROR("Parity error\n");
2056                 handled |= IPW_INTA_BIT_PARITY_ERROR;
2057         }
2058
2059         if (handled != inta) {
2060                 IPW_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
2061         }
2062
2063         spin_unlock_irqrestore(&priv->lock, flags);
2064
2065         /* enable all interrupts */
2066         ipw_enable_interrupts(priv);
2067 }
2068
2069 #define IPW_CMD(x) case IPW_CMD_ ## x : return #x
2070 static char *get_cmd_string(u8 cmd)
2071 {
2072         switch (cmd) {
2073                 IPW_CMD(HOST_COMPLETE);
2074                 IPW_CMD(POWER_DOWN);
2075                 IPW_CMD(SYSTEM_CONFIG);
2076                 IPW_CMD(MULTICAST_ADDRESS);
2077                 IPW_CMD(SSID);
2078                 IPW_CMD(ADAPTER_ADDRESS);
2079                 IPW_CMD(PORT_TYPE);
2080                 IPW_CMD(RTS_THRESHOLD);
2081                 IPW_CMD(FRAG_THRESHOLD);
2082                 IPW_CMD(POWER_MODE);
2083                 IPW_CMD(WEP_KEY);
2084                 IPW_CMD(TGI_TX_KEY);
2085                 IPW_CMD(SCAN_REQUEST);
2086                 IPW_CMD(SCAN_REQUEST_EXT);
2087                 IPW_CMD(ASSOCIATE);
2088                 IPW_CMD(SUPPORTED_RATES);
2089                 IPW_CMD(SCAN_ABORT);
2090                 IPW_CMD(TX_FLUSH);
2091                 IPW_CMD(QOS_PARAMETERS);
2092                 IPW_CMD(DINO_CONFIG);
2093                 IPW_CMD(RSN_CAPABILITIES);
2094                 IPW_CMD(RX_KEY);
2095                 IPW_CMD(CARD_DISABLE);
2096                 IPW_CMD(SEED_NUMBER);
2097                 IPW_CMD(TX_POWER);
2098                 IPW_CMD(COUNTRY_INFO);
2099                 IPW_CMD(AIRONET_INFO);
2100                 IPW_CMD(AP_TX_POWER);
2101                 IPW_CMD(CCKM_INFO);
2102                 IPW_CMD(CCX_VER_INFO);
2103                 IPW_CMD(SET_CALIBRATION);
2104                 IPW_CMD(SENSITIVITY_CALIB);
2105                 IPW_CMD(RETRY_LIMIT);
2106                 IPW_CMD(IPW_PRE_POWER_DOWN);
2107                 IPW_CMD(VAP_BEACON_TEMPLATE);
2108                 IPW_CMD(VAP_DTIM_PERIOD);
2109                 IPW_CMD(EXT_SUPPORTED_RATES);
2110                 IPW_CMD(VAP_LOCAL_TX_PWR_CONSTRAINT);
2111                 IPW_CMD(VAP_QUIET_INTERVALS);
2112                 IPW_CMD(VAP_CHANNEL_SWITCH);
2113                 IPW_CMD(VAP_MANDATORY_CHANNELS);
2114                 IPW_CMD(VAP_CELL_PWR_LIMIT);
2115                 IPW_CMD(VAP_CF_PARAM_SET);
2116                 IPW_CMD(VAP_SET_BEACONING_STATE);
2117                 IPW_CMD(MEASUREMENT);
2118                 IPW_CMD(POWER_CAPABILITY);
2119                 IPW_CMD(SUPPORTED_CHANNELS);
2120                 IPW_CMD(TPC_REPORT);
2121                 IPW_CMD(WME_INFO);
2122                 IPW_CMD(PRODUCTION_COMMAND);
2123         default:
2124                 return "UNKNOWN";
2125         }
2126 }
2127
2128 #define HOST_COMPLETE_TIMEOUT HZ
2129
2130 static int __ipw_send_cmd(struct ipw_priv *priv, struct host_cmd *cmd)
2131 {
2132         int rc = 0;
2133         unsigned long flags;
2134
2135         spin_lock_irqsave(&priv->lock, flags);
2136         if (priv->status & STATUS_HCMD_ACTIVE) {
2137                 IPW_ERROR("Failed to send %s: Already sending a command.\n",
2138                           get_cmd_string(cmd->cmd));
2139                 spin_unlock_irqrestore(&priv->lock, flags);
2140                 return -EAGAIN;
2141         }
2142
2143         priv->status |= STATUS_HCMD_ACTIVE;
2144
2145         if (priv->cmdlog) {
2146                 priv->cmdlog[priv->cmdlog_pos].jiffies = jiffies;
2147                 priv->cmdlog[priv->cmdlog_pos].cmd.cmd = cmd->cmd;
2148                 priv->cmdlog[priv->cmdlog_pos].cmd.len = cmd->len;
2149                 memcpy(priv->cmdlog[priv->cmdlog_pos].cmd.param, cmd->param,
2150                        cmd->len);
2151                 priv->cmdlog[priv->cmdlog_pos].retcode = -1;
2152         }
2153
2154         IPW_DEBUG_HC("%s command (#%d) %d bytes: 0x%08X\n",
2155                      get_cmd_string(cmd->cmd), cmd->cmd, cmd->len,
2156                      priv->status);
2157
2158 #ifndef DEBUG_CMD_WEP_KEY
2159         if (cmd->cmd == IPW_CMD_WEP_KEY)
2160                 IPW_DEBUG_HC("WEP_KEY command masked out for secure.\n");
2161         else
2162 #endif
2163                 printk_buf(IPW_DL_HOST_COMMAND, (u8 *) cmd->param, cmd->len);
2164
2165         rc = ipw_queue_tx_hcmd(priv, cmd->cmd, cmd->param, cmd->len, 0);
2166         if (rc) {
2167                 priv->status &= ~STATUS_HCMD_ACTIVE;
2168                 IPW_ERROR("Failed to send %s: Reason %d\n",
2169                           get_cmd_string(cmd->cmd), rc);
2170                 spin_unlock_irqrestore(&priv->lock, flags);
2171                 goto exit;
2172         }
2173         spin_unlock_irqrestore(&priv->lock, flags);
2174
2175         rc = wait_event_interruptible_timeout(priv->wait_command_queue,
2176                                               !(priv->
2177                                                 status & STATUS_HCMD_ACTIVE),
2178                                               HOST_COMPLETE_TIMEOUT);
2179         if (rc == 0) {
2180                 spin_lock_irqsave(&priv->lock, flags);
2181                 if (priv->status & STATUS_HCMD_ACTIVE) {
2182                         IPW_ERROR("Failed to send %s: Command timed out.\n",
2183                                   get_cmd_string(cmd->cmd));
2184                         priv->status &= ~STATUS_HCMD_ACTIVE;
2185                         spin_unlock_irqrestore(&priv->lock, flags);
2186                         rc = -EIO;
2187                         goto exit;
2188                 }
2189                 spin_unlock_irqrestore(&priv->lock, flags);
2190         } else
2191                 rc = 0;
2192
2193         if (priv->status & STATUS_RF_KILL_HW) {
2194                 IPW_ERROR("Failed to send %s: Aborted due to RF kill switch.\n",
2195                           get_cmd_string(cmd->cmd));
2196                 rc = -EIO;
2197                 goto exit;
2198         }
2199
2200       exit:
2201         if (priv->cmdlog) {
2202                 priv->cmdlog[priv->cmdlog_pos++].retcode = rc;
2203                 priv->cmdlog_pos %= priv->cmdlog_len;
2204         }
2205         return rc;
2206 }
2207
2208 static int ipw_send_cmd_simple(struct ipw_priv *priv, u8 command)
2209 {
2210         struct host_cmd cmd = {
2211                 .cmd = command,
2212         };
2213
2214         return __ipw_send_cmd(priv, &cmd);
2215 }
2216
2217 static int ipw_send_cmd_pdu(struct ipw_priv *priv, u8 command, u8 len,
2218                             void *data)
2219 {
2220         struct host_cmd cmd = {
2221                 .cmd = command,
2222                 .len = len,
2223                 .param = data,
2224         };
2225
2226         return __ipw_send_cmd(priv, &cmd);
2227 }
2228
2229 static int ipw_send_host_complete(struct ipw_priv *priv)
2230 {
2231         if (!priv) {
2232                 IPW_ERROR("Invalid args\n");
2233                 return -1;
2234         }
2235
2236         return ipw_send_cmd_simple(priv, IPW_CMD_HOST_COMPLETE);
2237 }
2238
2239 static int ipw_send_system_config(struct ipw_priv *priv)
2240 {
2241         return ipw_send_cmd_pdu(priv, IPW_CMD_SYSTEM_CONFIG,
2242                                 sizeof(priv->sys_config),
2243                                 &priv->sys_config);
2244 }
2245
2246 static int ipw_send_ssid(struct ipw_priv *priv, u8 * ssid, int len)
2247 {
2248         if (!priv || !ssid) {
2249                 IPW_ERROR("Invalid args\n");
2250                 return -1;
2251         }
2252
2253         return ipw_send_cmd_pdu(priv, IPW_CMD_SSID, min(len, IW_ESSID_MAX_SIZE),
2254                                 ssid);
2255 }
2256
2257 static int ipw_send_adapter_address(struct ipw_priv *priv, u8 * mac)
2258 {
2259         if (!priv || !mac) {
2260                 IPW_ERROR("Invalid args\n");
2261                 return -1;
2262         }
2263
2264         IPW_DEBUG_INFO("%s: Setting MAC to %s\n",
2265                        priv->net_dev->name, print_mac(mac, mac));
2266
2267         return ipw_send_cmd_pdu(priv, IPW_CMD_ADAPTER_ADDRESS, ETH_ALEN, mac);
2268 }
2269
2270 /*
2271  * NOTE: This must be executed from our workqueue as it results in udelay
2272  * being called which may corrupt the keyboard if executed on default
2273  * workqueue
2274  */
2275 static void ipw_adapter_restart(void *adapter)
2276 {
2277         struct ipw_priv *priv = adapter;
2278
2279         if (priv->status & STATUS_RF_KILL_MASK)
2280                 return;
2281
2282         ipw_down(priv);
2283
2284         if (priv->assoc_network &&
2285             (priv->assoc_network->capability & WLAN_CAPABILITY_IBSS))
2286                 ipw_remove_current_network(priv);
2287
2288         if (ipw_up(priv)) {
2289                 IPW_ERROR("Failed to up device\n");
2290                 return;
2291         }
2292 }
2293
2294 static void ipw_bg_adapter_restart(struct work_struct *work)
2295 {
2296         struct ipw_priv *priv =
2297                 container_of(work, struct ipw_priv, adapter_restart);
2298         mutex_lock(&priv->mutex);
2299         ipw_adapter_restart(priv);
2300         mutex_unlock(&priv->mutex);
2301 }
2302
2303 #define IPW_SCAN_CHECK_WATCHDOG (5 * HZ)
2304
2305 static void ipw_scan_check(void *data)
2306 {
2307         struct ipw_priv *priv = data;
2308         if (priv->status & (STATUS_SCANNING | STATUS_SCAN_ABORTING)) {
2309                 IPW_DEBUG_SCAN("Scan completion watchdog resetting "
2310                                "adapter after (%dms).\n",
2311                                jiffies_to_msecs(IPW_SCAN_CHECK_WATCHDOG));
2312                 queue_work(priv->workqueue, &priv->adapter_restart);
2313         }
2314 }
2315
2316 static void ipw_bg_scan_check(struct work_struct *work)
2317 {
2318         struct ipw_priv *priv =
2319                 container_of(work, struct ipw_priv, scan_check.work);
2320         mutex_lock(&priv->mutex);
2321         ipw_scan_check(priv);
2322         mutex_unlock(&priv->mutex);
2323 }
2324
2325 static int ipw_send_scan_request_ext(struct ipw_priv *priv,
2326                                      struct ipw_scan_request_ext *request)
2327 {
2328         return ipw_send_cmd_pdu(priv, IPW_CMD_SCAN_REQUEST_EXT,
2329                                 sizeof(*request), request);
2330 }
2331
2332 static int ipw_send_scan_abort(struct ipw_priv *priv)
2333 {
2334         if (!priv) {
2335                 IPW_ERROR("Invalid args\n");
2336                 return -1;
2337         }
2338
2339         return ipw_send_cmd_simple(priv, IPW_CMD_SCAN_ABORT);
2340 }
2341
2342 static int ipw_set_sensitivity(struct ipw_priv *priv, u16 sens)
2343 {
2344         struct ipw_sensitivity_calib calib = {
2345                 .beacon_rssi_raw = cpu_to_le16(sens),
2346         };
2347
2348         return ipw_send_cmd_pdu(priv, IPW_CMD_SENSITIVITY_CALIB, sizeof(calib),
2349                                 &calib);
2350 }
2351
2352 static int ipw_send_associate(struct ipw_priv *priv,
2353                               struct ipw_associate *associate)
2354 {
2355         if (!priv || !associate) {
2356                 IPW_ERROR("Invalid args\n");
2357                 return -1;
2358         }
2359
2360         return ipw_send_cmd_pdu(priv, IPW_CMD_ASSOCIATE, sizeof(*associate),
2361                                 associate);
2362 }
2363
2364 static int ipw_send_supported_rates(struct ipw_priv *priv,
2365                                     struct ipw_supported_rates *rates)
2366 {
2367         if (!priv || !rates) {
2368                 IPW_ERROR("Invalid args\n");
2369                 return -1;
2370         }
2371
2372         return ipw_send_cmd_pdu(priv, IPW_CMD_SUPPORTED_RATES, sizeof(*rates),
2373                                 rates);
2374 }
2375
2376 static int ipw_set_random_seed(struct ipw_priv *priv)
2377 {
2378         u32 val;
2379
2380         if (!priv) {
2381                 IPW_ERROR("Invalid args\n");
2382                 return -1;
2383         }
2384
2385         get_random_bytes(&val, sizeof(val));
2386
2387         return ipw_send_cmd_pdu(priv, IPW_CMD_SEED_NUMBER, sizeof(val), &val);
2388 }
2389
2390 static int ipw_send_card_disable(struct ipw_priv *priv, u32 phy_off)
2391 {
2392         __le32 v = cpu_to_le32(phy_off);
2393         if (!priv) {
2394                 IPW_ERROR("Invalid args\n");
2395                 return -1;
2396         }
2397
2398         return ipw_send_cmd_pdu(priv, IPW_CMD_CARD_DISABLE, sizeof(v), &v);
2399 }
2400
2401 static int ipw_send_tx_power(struct ipw_priv *priv, struct ipw_tx_power *power)
2402 {
2403         if (!priv || !power) {
2404                 IPW_ERROR("Invalid args\n");
2405                 return -1;
2406         }
2407
2408         return ipw_send_cmd_pdu(priv, IPW_CMD_TX_POWER, sizeof(*power), power);
2409 }
2410
2411 static int ipw_set_tx_power(struct ipw_priv *priv)
2412 {
2413         const struct ieee80211_geo *geo = ieee80211_get_geo(priv->ieee);
2414         struct ipw_tx_power tx_power;
2415         s8 max_power;
2416         int i;
2417
2418         memset(&tx_power, 0, sizeof(tx_power));
2419
2420         /* configure device for 'G' band */
2421         tx_power.ieee_mode = IPW_G_MODE;
2422         tx_power.num_channels = geo->bg_channels;
2423         for (i = 0; i < geo->bg_channels; i++) {
2424                 max_power = geo->bg[i].max_power;
2425                 tx_power.channels_tx_power[i].channel_number =
2426                     geo->bg[i].channel;
2427                 tx_power.channels_tx_power[i].tx_power = max_power ?
2428                     min(max_power, priv->tx_power) : priv->tx_power;
2429         }
2430         if (ipw_send_tx_power(priv, &tx_power))
2431                 return -EIO;
2432
2433         /* configure device to also handle 'B' band */
2434         tx_power.ieee_mode = IPW_B_MODE;
2435         if (ipw_send_tx_power(priv, &tx_power))
2436                 return -EIO;
2437
2438         /* configure device to also handle 'A' band */
2439         if (priv->ieee->abg_true) {
2440                 tx_power.ieee_mode = IPW_A_MODE;
2441                 tx_power.num_channels = geo->a_channels;
2442                 for (i = 0; i < tx_power.num_channels; i++) {
2443                         max_power = geo->a[i].max_power;
2444                         tx_power.channels_tx_power[i].channel_number =
2445                             geo->a[i].channel;
2446                         tx_power.channels_tx_power[i].tx_power = max_power ?
2447                             min(max_power, priv->tx_power) : priv->tx_power;
2448                 }
2449                 if (ipw_send_tx_power(priv, &tx_power))
2450                         return -EIO;
2451         }
2452         return 0;
2453 }
2454
2455 static int ipw_send_rts_threshold(struct ipw_priv *priv, u16 rts)
2456 {
2457         struct ipw_rts_threshold rts_threshold = {
2458                 .rts_threshold = cpu_to_le16(rts),
2459         };
2460
2461         if (!priv) {
2462                 IPW_ERROR("Invalid args\n");
2463                 return -1;
2464         }
2465
2466         return ipw_send_cmd_pdu(priv, IPW_CMD_RTS_THRESHOLD,
2467                                 sizeof(rts_threshold), &rts_threshold);
2468 }
2469
2470 static int ipw_send_frag_threshold(struct ipw_priv *priv, u16 frag)
2471 {
2472         struct ipw_frag_threshold frag_threshold = {
2473                 .frag_threshold = cpu_to_le16(frag),
2474         };
2475
2476         if (!priv) {
2477                 IPW_ERROR("Invalid args\n");
2478                 return -1;
2479         }
2480
2481         return ipw_send_cmd_pdu(priv, IPW_CMD_FRAG_THRESHOLD,
2482                                 sizeof(frag_threshold), &frag_threshold);
2483 }
2484
2485 static int ipw_send_power_mode(struct ipw_priv *priv, u32 mode)
2486 {
2487         __le32 param;
2488
2489         if (!priv) {
2490                 IPW_ERROR("Invalid args\n");
2491                 return -1;
2492         }
2493
2494         /* If on battery, set to 3, if AC set to CAM, else user
2495          * level */
2496         switch (mode) {
2497         case IPW_POWER_BATTERY:
2498                 param = cpu_to_le32(IPW_POWER_INDEX_3);
2499                 break;
2500         case IPW_POWER_AC:
2501                 param = cpu_to_le32(IPW_POWER_MODE_CAM);
2502                 break;
2503         default:
2504                 param = cpu_to_le32(mode);
2505                 break;
2506         }
2507
2508         return ipw_send_cmd_pdu(priv, IPW_CMD_POWER_MODE, sizeof(param),
2509                                 &param);
2510 }
2511
2512 static int ipw_send_retry_limit(struct ipw_priv *priv, u8 slimit, u8 llimit)
2513 {
2514         struct ipw_retry_limit retry_limit = {
2515                 .short_retry_limit = slimit,
2516                 .long_retry_limit = llimit
2517         };
2518
2519         if (!priv) {
2520                 IPW_ERROR("Invalid args\n");
2521                 return -1;
2522         }
2523
2524         return ipw_send_cmd_pdu(priv, IPW_CMD_RETRY_LIMIT, sizeof(retry_limit),
2525                                 &retry_limit);
2526 }
2527
2528 /*
2529  * The IPW device contains a Microwire compatible EEPROM that stores
2530  * various data like the MAC address.  Usually the firmware has exclusive
2531  * access to the eeprom, but during device initialization (before the
2532  * device driver has sent the HostComplete command to the firmware) the
2533  * device driver has read access to the EEPROM by way of indirect addressing
2534  * through a couple of memory mapped registers.
2535  *
2536  * The following is a simplified implementation for pulling data out of the
2537  * the eeprom, along with some helper functions to find information in
2538  * the per device private data's copy of the eeprom.
2539  *
2540  * NOTE: To better understand how these functions work (i.e what is a chip
2541  *       select and why do have to keep driving the eeprom clock?), read
2542  *       just about any data sheet for a Microwire compatible EEPROM.
2543  */
2544
2545 /* write a 32 bit value into the indirect accessor register */
2546 static inline void eeprom_write_reg(struct ipw_priv *p, u32 data)
2547 {
2548         ipw_write_reg32(p, FW_MEM_REG_EEPROM_ACCESS, data);
2549
2550         /* the eeprom requires some time to complete the operation */
2551         udelay(p->eeprom_delay);
2552
2553         return;
2554 }
2555
2556 /* perform a chip select operation */
2557 static void eeprom_cs(struct ipw_priv *priv)
2558 {
2559         eeprom_write_reg(priv, 0);
2560         eeprom_write_reg(priv, EEPROM_BIT_CS);
2561         eeprom_write_reg(priv, EEPROM_BIT_CS | EEPROM_BIT_SK);
2562         eeprom_write_reg(priv, EEPROM_BIT_CS);
2563 }
2564
2565 /* perform a chip select operation */
2566 static void eeprom_disable_cs(struct ipw_priv *priv)
2567 {
2568         eeprom_write_reg(priv, EEPROM_BIT_CS);
2569         eeprom_write_reg(priv, 0);
2570         eeprom_write_reg(priv, EEPROM_BIT_SK);
2571 }
2572
2573 /* push a single bit down to the eeprom */
2574 static inline void eeprom_write_bit(struct ipw_priv *p, u8 bit)
2575 {
2576         int d = (bit ? EEPROM_BIT_DI : 0);
2577         eeprom_write_reg(p, EEPROM_BIT_CS | d);
2578         eeprom_write_reg(p, EEPROM_BIT_CS | d | EEPROM_BIT_SK);
2579 }
2580
2581 /* push an opcode followed by an address down to the eeprom */
2582 static void eeprom_op(struct ipw_priv *priv, u8 op, u8 addr)
2583 {
2584         int i;
2585
2586         eeprom_cs(priv);
2587         eeprom_write_bit(priv, 1);
2588         eeprom_write_bit(priv, op & 2);
2589         eeprom_write_bit(priv, op & 1);
2590         for (i = 7; i >= 0; i--) {
2591                 eeprom_write_bit(priv, addr & (1 << i));
2592         }
2593 }
2594
2595 /* pull 16 bits off the eeprom, one bit at a time */
2596 static u16 eeprom_read_u16(struct ipw_priv *priv, u8 addr)
2597 {
2598         int i;
2599         u16 r = 0;
2600
2601         /* Send READ Opcode */
2602         eeprom_op(priv, EEPROM_CMD_READ, addr);
2603
2604         /* Send dummy bit */
2605         eeprom_write_reg(priv, EEPROM_BIT_CS);
2606
2607         /* Read the byte off the eeprom one bit at a time */
2608         for (i = 0; i < 16; i++) {
2609                 u32 data = 0;
2610                 eeprom_write_reg(priv, EEPROM_BIT_CS | EEPROM_BIT_SK);
2611                 eeprom_write_reg(priv, EEPROM_BIT_CS);
2612                 data = ipw_read_reg32(priv, FW_MEM_REG_EEPROM_ACCESS);
2613                 r = (r << 1) | ((data & EEPROM_BIT_DO) ? 1 : 0);
2614         }
2615
2616         /* Send another dummy bit */
2617         eeprom_write_reg(priv, 0);
2618         eeprom_disable_cs(priv);
2619
2620         return r;
2621 }
2622
2623 /* helper function for pulling the mac address out of the private */
2624 /* data's copy of the eeprom data                                 */
2625 static void eeprom_parse_mac(struct ipw_priv *priv, u8 * mac)
2626 {
2627         memcpy(mac, &priv->eeprom[EEPROM_MAC_ADDRESS], 6);
2628 }
2629
2630 /*
2631  * Either the device driver (i.e. the host) or the firmware can
2632  * load eeprom data into the designated region in SRAM.  If neither
2633  * happens then the FW will shutdown with a fatal error.
2634  *
2635  * In order to signal the FW to load the EEPROM, the EEPROM_LOAD_DISABLE
2636  * bit needs region of shared SRAM needs to be non-zero.
2637  */
2638 static void ipw_eeprom_init_sram(struct ipw_priv *priv)
2639 {
2640         int i;
2641         __le16 *eeprom = (__le16 *) priv->eeprom;
2642
2643         IPW_DEBUG_TRACE(">>\n");
2644
2645         /* read entire contents of eeprom into private buffer */
2646         for (i = 0; i < 128; i++)
2647                 eeprom[i] = cpu_to_le16(eeprom_read_u16(priv, (u8) i));
2648
2649         /*
2650            If the data looks correct, then copy it to our private
2651            copy.  Otherwise let the firmware know to perform the operation
2652            on its own.
2653          */
2654         if (priv->eeprom[EEPROM_VERSION] != 0) {
2655                 IPW_DEBUG_INFO("Writing EEPROM data into SRAM\n");
2656
2657                 /* write the eeprom data to sram */
2658                 for (i = 0; i < IPW_EEPROM_IMAGE_SIZE; i++)
2659                         ipw_write8(priv, IPW_EEPROM_DATA + i, priv->eeprom[i]);
2660
2661                 /* Do not load eeprom data on fatal error or suspend */
2662                 ipw_write32(priv, IPW_EEPROM_LOAD_DISABLE, 0);
2663         } else {
2664                 IPW_DEBUG_INFO("Enabling FW initializationg of SRAM\n");
2665
2666                 /* Load eeprom data on fatal error or suspend */
2667                 ipw_write32(priv, IPW_EEPROM_LOAD_DISABLE, 1);
2668         }
2669
2670         IPW_DEBUG_TRACE("<<\n");
2671 }
2672
2673 static void ipw_zero_memory(struct ipw_priv *priv, u32 start, u32 count)
2674 {
2675         count >>= 2;
2676         if (!count)
2677                 return;
2678         _ipw_write32(priv, IPW_AUTOINC_ADDR, start);
2679         while (count--)
2680                 _ipw_write32(priv, IPW_AUTOINC_DATA, 0);
2681 }
2682
2683 static inline void ipw_fw_dma_reset_command_blocks(struct ipw_priv *priv)
2684 {
2685         ipw_zero_memory(priv, IPW_SHARED_SRAM_DMA_CONTROL,
2686                         CB_NUMBER_OF_ELEMENTS_SMALL *
2687                         sizeof(struct command_block));
2688 }
2689
2690 static int ipw_fw_dma_enable(struct ipw_priv *priv)
2691 {                               /* start dma engine but no transfers yet */
2692
2693         IPW_DEBUG_FW(">> : \n");
2694
2695         /* Start the dma */
2696         ipw_fw_dma_reset_command_blocks(priv);
2697
2698         /* Write CB base address */
2699         ipw_write_reg32(priv, IPW_DMA_I_CB_BASE, IPW_SHARED_SRAM_DMA_CONTROL);
2700
2701         IPW_DEBUG_FW("<< : \n");
2702         return 0;
2703 }
2704
2705 static void ipw_fw_dma_abort(struct ipw_priv *priv)
2706 {
2707         u32 control = 0;
2708
2709         IPW_DEBUG_FW(">> :\n");
2710
2711         /* set the Stop and Abort bit */
2712         control = DMA_CONTROL_SMALL_CB_CONST_VALUE | DMA_CB_STOP_AND_ABORT;
2713         ipw_write_reg32(priv, IPW_DMA_I_DMA_CONTROL, control);
2714         priv->sram_desc.last_cb_index = 0;
2715
2716         IPW_DEBUG_FW("<< \n");
2717 }
2718
2719 static int ipw_fw_dma_write_command_block(struct ipw_priv *priv, int index,
2720                                           struct command_block *cb)
2721 {
2722         u32 address =
2723             IPW_SHARED_SRAM_DMA_CONTROL +
2724             (sizeof(struct command_block) * index);
2725         IPW_DEBUG_FW(">> :\n");
2726
2727         ipw_write_indirect(priv, address, (u8 *) cb,
2728                            (int)sizeof(struct command_block));
2729
2730         IPW_DEBUG_FW("<< :\n");
2731         return 0;
2732
2733 }
2734
2735 static int ipw_fw_dma_kick(struct ipw_priv *priv)
2736 {
2737         u32 control = 0;
2738         u32 index = 0;
2739
2740         IPW_DEBUG_FW(">> :\n");
2741
2742         for (index = 0; index < priv->sram_desc.last_cb_index; index++)
2743                 ipw_fw_dma_write_command_block(priv, index,
2744                                                &priv->sram_desc.cb_list[index]);
2745
2746         /* Enable the DMA in the CSR register */
2747         ipw_clear_bit(priv, IPW_RESET_REG,
2748                       IPW_RESET_REG_MASTER_DISABLED |
2749                       IPW_RESET_REG_STOP_MASTER);
2750
2751         /* Set the Start bit. */
2752         control = DMA_CONTROL_SMALL_CB_CONST_VALUE | DMA_CB_START;
2753         ipw_write_reg32(priv, IPW_DMA_I_DMA_CONTROL, control);
2754
2755         IPW_DEBUG_FW("<< :\n");
2756         return 0;
2757 }
2758
2759 static void ipw_fw_dma_dump_command_block(struct ipw_priv *priv)
2760 {
2761         u32 address;
2762         u32 register_value = 0;
2763         u32 cb_fields_address = 0;
2764
2765         IPW_DEBUG_FW(">> :\n");
2766         address = ipw_read_reg32(priv, IPW_DMA_I_CURRENT_CB);
2767         IPW_DEBUG_FW_INFO("Current CB is 0x%x \n", address);
2768
2769         /* Read the DMA Controlor register */
2770         register_value = ipw_read_reg32(priv, IPW_DMA_I_DMA_CONTROL);
2771         IPW_DEBUG_FW_INFO("IPW_DMA_I_DMA_CONTROL is 0x%x \n", register_value);
2772
2773         /* Print the CB values */
2774         cb_fields_address = address;
2775         register_value = ipw_read_reg32(priv, cb_fields_address);
2776         IPW_DEBUG_FW_INFO("Current CB ControlField is 0x%x \n", register_value);
2777
2778         cb_fields_address += sizeof(u32);
2779         register_value = ipw_read_reg32(priv, cb_fields_address);
2780         IPW_DEBUG_FW_INFO("Current CB Source Field is 0x%x \n", register_value);
2781
2782         cb_fields_address += sizeof(u32);
2783         register_value = ipw_read_reg32(priv, cb_fields_address);
2784         IPW_DEBUG_FW_INFO("Current CB Destination Field is 0x%x \n",
2785                           register_value);
2786
2787         cb_fields_address += sizeof(u32);
2788         register_value = ipw_read_reg32(priv, cb_fields_address);
2789         IPW_DEBUG_FW_INFO("Current CB Status Field is 0x%x \n", register_value);
2790
2791         IPW_DEBUG_FW(">> :\n");
2792 }
2793
2794 static int ipw_fw_dma_command_block_index(struct ipw_priv *priv)
2795 {
2796         u32 current_cb_address = 0;
2797         u32 current_cb_index = 0;
2798
2799         IPW_DEBUG_FW("<< :\n");
2800         current_cb_address = ipw_read_reg32(priv, IPW_DMA_I_CURRENT_CB);
2801
2802         current_cb_index = (current_cb_address - IPW_SHARED_SRAM_DMA_CONTROL) /
2803             sizeof(struct command_block);
2804
2805         IPW_DEBUG_FW_INFO("Current CB index 0x%x address = 0x%X \n",
2806                           current_cb_index, current_cb_address);
2807
2808         IPW_DEBUG_FW(">> :\n");
2809         return current_cb_index;
2810
2811 }
2812
2813 static int ipw_fw_dma_add_command_block(struct ipw_priv *priv,
2814                                         u32 src_address,
2815                                         u32 dest_address,
2816                                         u32 length,
2817                                         int interrupt_enabled, int is_last)
2818 {
2819
2820         u32 control = CB_VALID | CB_SRC_LE | CB_DEST_LE | CB_SRC_AUTOINC |
2821             CB_SRC_IO_GATED | CB_DEST_AUTOINC | CB_SRC_SIZE_LONG |
2822             CB_DEST_SIZE_LONG;
2823         struct command_block *cb;
2824         u32 last_cb_element = 0;
2825
2826         IPW_DEBUG_FW_INFO("src_address=0x%x dest_address=0x%x length=0x%x\n",
2827                           src_address, dest_address, length);
2828
2829         if (priv->sram_desc.last_cb_index >= CB_NUMBER_OF_ELEMENTS_SMALL)
2830                 return -1;
2831
2832         last_cb_element = priv->sram_desc.last_cb_index;
2833         cb = &priv->sram_desc.cb_list[last_cb_element];
2834         priv->sram_desc.last_cb_index++;
2835
2836         /* Calculate the new CB control word */
2837         if (interrupt_enabled)
2838                 control |= CB_INT_ENABLED;
2839
2840         if (is_last)
2841                 control |= CB_LAST_VALID;
2842
2843         control |= length;
2844
2845         /* Calculate the CB Element's checksum value */
2846         cb->status = control ^ src_address ^ dest_address;
2847
2848         /* Copy the Source and Destination addresses */
2849         cb->dest_addr = dest_address;
2850         cb->source_addr = src_address;
2851
2852         /* Copy the Control Word last */
2853         cb->control = control;
2854
2855         return 0;
2856 }
2857
2858 static int ipw_fw_dma_add_buffer(struct ipw_priv *priv,
2859                                  u32 src_phys, u32 dest_address, u32 length)
2860 {
2861         u32 bytes_left = length;
2862         u32 src_offset = 0;
2863         u32 dest_offset = 0;
2864         int status = 0;
2865         IPW_DEBUG_FW(">> \n");
2866         IPW_DEBUG_FW_INFO("src_phys=0x%x dest_address=0x%x length=0x%x\n",
2867                           src_phys, dest_address, length);
2868         while (bytes_left > CB_MAX_LENGTH) {
2869                 status = ipw_fw_dma_add_command_block(priv,
2870                                                       src_phys + src_offset,
2871                                                       dest_address +
2872                                                       dest_offset,
2873                                                       CB_MAX_LENGTH, 0, 0);
2874                 if (status) {
2875                         IPW_DEBUG_FW_INFO(": Failed\n");
2876                         return -1;
2877                 } else
2878                         IPW_DEBUG_FW_INFO(": Added new cb\n");
2879
2880                 src_offset += CB_MAX_LENGTH;
2881                 dest_offset += CB_MAX_LENGTH;
2882                 bytes_left -= CB_MAX_LENGTH;
2883         }
2884
2885         /* add the buffer tail */
2886         if (bytes_left > 0) {
2887                 status =
2888                     ipw_fw_dma_add_command_block(priv, src_phys + src_offset,
2889                                                  dest_address + dest_offset,
2890                                                  bytes_left, 0, 0);
2891                 if (status) {
2892                         IPW_DEBUG_FW_INFO(": Failed on the buffer tail\n");
2893                         return -1;
2894                 } else
2895                         IPW_DEBUG_FW_INFO
2896                             (": Adding new cb - the buffer tail\n");
2897         }
2898
2899         IPW_DEBUG_FW("<< \n");
2900         return 0;
2901 }
2902
2903 static int ipw_fw_dma_wait(struct ipw_priv *priv)
2904 {
2905         u32 current_index = 0, previous_index;
2906         u32 watchdog = 0;
2907
2908         IPW_DEBUG_FW(">> : \n");
2909
2910         current_index = ipw_fw_dma_command_block_index(priv);
2911         IPW_DEBUG_FW_INFO("sram_desc.last_cb_index:0x%08X\n",
2912                           (int)priv->sram_desc.last_cb_index);
2913
2914         while (current_index < priv->sram_desc.last_cb_index) {
2915                 udelay(50);
2916                 previous_index = current_index;
2917                 current_index = ipw_fw_dma_command_block_index(priv);
2918
2919                 if (previous_index < current_index) {
2920                         watchdog = 0;
2921                         continue;
2922                 }
2923                 if (++watchdog > 400) {
2924                         IPW_DEBUG_FW_INFO("Timeout\n");
2925                         ipw_fw_dma_dump_command_block(priv);
2926                         ipw_fw_dma_abort(priv);
2927                         return -1;
2928                 }
2929         }
2930
2931         ipw_fw_dma_abort(priv);
2932
2933         /*Disable the DMA in the CSR register */
2934         ipw_set_bit(priv, IPW_RESET_REG,
2935                     IPW_RESET_REG_MASTER_DISABLED | IPW_RESET_REG_STOP_MASTER);
2936
2937         IPW_DEBUG_FW("<< dmaWaitSync \n");
2938         return 0;
2939 }
2940
2941 static void ipw_remove_current_network(struct ipw_priv *priv)
2942 {
2943         struct list_head *element, *safe;
2944         struct ieee80211_network *network = NULL;
2945         unsigned long flags;
2946
2947         spin_lock_irqsave(&priv->ieee->lock, flags);
2948         list_for_each_safe(element, safe, &priv->ieee->network_list) {
2949                 network = list_entry(element, struct ieee80211_network, list);
2950                 if (!memcmp(network->bssid, priv->bssid, ETH_ALEN)) {
2951                         list_del(element);
2952                         list_add_tail(&network->list,
2953                                       &priv->ieee->network_free_list);
2954                 }
2955         }
2956         spin_unlock_irqrestore(&priv->ieee->lock, flags);
2957 }
2958
2959 /**
2960  * Check that card is still alive.
2961  * Reads debug register from domain0.
2962  * If card is present, pre-defined value should
2963  * be found there.
2964  *
2965  * @param priv
2966  * @return 1 if card is present, 0 otherwise
2967  */
2968 static inline int ipw_alive(struct ipw_priv *priv)
2969 {
2970         return ipw_read32(priv, 0x90) == 0xd55555d5;
2971 }
2972
2973 /* timeout in msec, attempted in 10-msec quanta */
2974 static int ipw_poll_bit(struct ipw_priv *priv, u32 addr, u32 mask,
2975                                int timeout)
2976 {
2977         int i = 0;
2978
2979         do {
2980                 if ((ipw_read32(priv, addr) & mask) == mask)
2981                         return i;
2982                 mdelay(10);
2983                 i += 10;
2984         } while (i < timeout);
2985
2986         return -ETIME;
2987 }
2988
2989 /* These functions load the firmware and micro code for the operation of
2990  * the ipw hardware.  It assumes the buffer has all the bits for the
2991  * image and the caller is handling the memory allocation and clean up.
2992  */
2993
2994 static int ipw_stop_master(struct ipw_priv *priv)
2995 {
2996         int rc;
2997
2998         IPW_DEBUG_TRACE(">> \n");
2999         /* stop master. typical delay - 0 */
3000         ipw_set_bit(priv, IPW_RESET_REG, IPW_RESET_REG_STOP_MASTER);
3001
3002         /* timeout is in msec, polled in 10-msec quanta */
3003         rc = ipw_poll_bit(priv, IPW_RESET_REG,
3004                           IPW_RESET_REG_MASTER_DISABLED, 100);
3005         if (rc < 0) {
3006                 IPW_ERROR("wait for stop master failed after 100ms\n");
3007                 return -1;
3008         }
3009
3010         IPW_DEBUG_INFO("stop master %dms\n", rc);
3011
3012         return rc;
3013 }
3014
3015 static void ipw_arc_release(struct ipw_priv *priv)
3016 {
3017         IPW_DEBUG_TRACE(">> \n");
3018         mdelay(5);
3019
3020         ipw_clear_bit(priv, IPW_RESET_REG, CBD_RESET_REG_PRINCETON_RESET);
3021
3022         /* no one knows timing, for safety add some delay */
3023         mdelay(5);
3024 }
3025
3026 struct fw_chunk {
3027         __le32 address;
3028         __le32 length;
3029 };
3030
3031 static int ipw_load_ucode(struct ipw_priv *priv, u8 * data, size_t len)
3032 {
3033         int rc = 0, i, addr;
3034         u8 cr = 0;
3035         __le16 *image;
3036
3037         image = (__le16 *) data;
3038
3039         IPW_DEBUG_TRACE(">> \n");
3040
3041         rc = ipw_stop_master(priv);
3042
3043         if (rc < 0)
3044                 return rc;
3045
3046         for (addr = IPW_SHARED_LOWER_BOUND;
3047              addr < IPW_REGISTER_DOMAIN1_END; addr += 4) {
3048                 ipw_write32(priv, addr, 0);
3049         }
3050
3051         /* no ucode (yet) */
3052         memset(&priv->dino_alive, 0, sizeof(priv->dino_alive));
3053         /* destroy DMA queues */
3054         /* reset sequence */
3055
3056         ipw_write_reg32(priv, IPW_MEM_HALT_AND_RESET, IPW_BIT_HALT_RESET_ON);
3057         ipw_arc_release(priv);
3058         ipw_write_reg32(priv, IPW_MEM_HALT_AND_RESET, IPW_BIT_HALT_RESET_OFF);
3059         mdelay(1);
3060
3061         /* reset PHY */
3062         ipw_write_reg32(priv, IPW_INTERNAL_CMD_EVENT, IPW_BASEBAND_POWER_DOWN);
3063         mdelay(1);
3064
3065         ipw_write_reg32(priv, IPW_INTERNAL_CMD_EVENT, 0);
3066         mdelay(1);
3067
3068         /* enable ucode store */
3069         ipw_write_reg8(priv, IPW_BASEBAND_CONTROL_STATUS, 0x0);
3070         ipw_write_reg8(priv, IPW_BASEBAND_CONTROL_STATUS, DINO_ENABLE_CS);
3071         mdelay(1);
3072
3073         /* write ucode */
3074         /**
3075          * @bug
3076          * Do NOT set indirect address register once and then
3077          * store data to indirect data register in the loop.
3078          * It seems very reasonable, but in this case DINO do not
3079          * accept ucode. It is essential to set address each time.
3080          */
3081         /* load new ipw uCode */
3082         for (i = 0; i < len / 2; i++)
3083                 ipw_write_reg16(priv, IPW_BASEBAND_CONTROL_STORE,
3084                                 le16_to_cpu(image[i]));
3085
3086         /* enable DINO */
3087         ipw_write_reg8(priv, IPW_BASEBAND_CONTROL_STATUS, 0);
3088         ipw_write_reg8(priv, IPW_BASEBAND_CONTROL_STATUS, DINO_ENABLE_SYSTEM);
3089
3090         /* this is where the igx / win driver deveates from the VAP driver. */
3091
3092         /* wait for alive response */
3093         for (i = 0; i < 100; i++) {
3094                 /* poll for incoming data */
3095                 cr = ipw_read_reg8(priv, IPW_BASEBAND_CONTROL_STATUS);
3096                 if (cr & DINO_RXFIFO_DATA)
3097                         break;
3098                 mdelay(1);
3099         }
3100
3101         if (cr & DINO_RXFIFO_DATA) {
3102                 /* alive_command_responce size is NOT multiple of 4 */
3103                 __le32 response_buffer[(sizeof(priv->dino_alive) + 3) / 4];
3104
3105                 for (i = 0; i < ARRAY_SIZE(response_buffer); i++)
3106                         response_buffer[i] =
3107                             cpu_to_le32(ipw_read_reg32(priv,
3108                                                        IPW_BASEBAND_RX_FIFO_READ));
3109                 memcpy(&priv->dino_alive, response_buffer,
3110                        sizeof(priv->dino_alive));
3111                 if (priv->dino_alive.alive_command == 1
3112                     && priv->dino_alive.ucode_valid == 1) {
3113                         rc = 0;
3114                         IPW_DEBUG_INFO
3115                             ("Microcode OK, rev. %d (0x%x) dev. %d (0x%x) "
3116                              "of %02d/%02d/%02d %02d:%02d\n",
3117                              priv->dino_alive.software_revision,
3118                              priv->dino_alive.software_revision,
3119                              priv->dino_alive.device_identifier,
3120                              priv->dino_alive.device_identifier,
3121                              priv->dino_alive.time_stamp[0],
3122                              priv->dino_alive.time_stamp[1],
3123                              priv->dino_alive.time_stamp[2],
3124                              priv->dino_alive.time_stamp[3],
3125                              priv->dino_alive.time_stamp[4]);
3126                 } else {
3127                         IPW_DEBUG_INFO("Microcode is not alive\n");
3128                         rc = -EINVAL;
3129                 }
3130         } else {
3131                 IPW_DEBUG_INFO("No alive response from DINO\n");
3132                 rc = -ETIME;
3133         }
3134
3135         /* disable DINO, otherwise for some reason
3136            firmware have problem getting alive resp. */
3137         ipw_write_reg8(priv, IPW_BASEBAND_CONTROL_STATUS, 0);
3138
3139         return rc;
3140 }
3141
3142 static int ipw_load_firmware(struct ipw_priv *priv, u8 * data, size_t len)
3143 {
3144         int rc = -1;
3145         int offset = 0;
3146         struct fw_chunk *chunk;
3147         dma_addr_t shared_phys;
3148         u8 *shared_virt;
3149
3150         IPW_DEBUG_TRACE("<< : \n");
3151         shared_virt = pci_alloc_consistent(priv->pci_dev, len, &shared_phys);
3152
3153         if (!shared_virt)
3154                 return -ENOMEM;
3155
3156         memmove(shared_virt, data, len);
3157
3158         /* Start the Dma */
3159         rc = ipw_fw_dma_enable(priv);
3160
3161         if (priv->sram_desc.last_cb_index > 0) {
3162                 /* the DMA is already ready this would be a bug. */
3163                 BUG();
3164                 goto out;
3165         }
3166
3167         do {
3168                 chunk = (struct fw_chunk *)(data + offset);
3169                 offset += sizeof(struct fw_chunk);
3170                 /* build DMA packet and queue up for sending */
3171                 /* dma to chunk->address, the chunk->length bytes from data +
3172                  * offeset*/
3173                 /* Dma loading */
3174                 rc = ipw_fw_dma_add_buffer(priv, shared_phys + offset,
3175                                            le32_to_cpu(chunk->address),
3176                                            le32_to_cpu(chunk->length));
3177                 if (rc) {
3178                         IPW_DEBUG_INFO("dmaAddBuffer Failed\n");
3179                         goto out;
3180                 }
3181
3182                 offset += le32_to_cpu(chunk->length);
3183         } while (offset < len);
3184
3185         /* Run the DMA and wait for the answer */
3186         rc = ipw_fw_dma_kick(priv);
3187         if (rc) {
3188                 IPW_ERROR("dmaKick Failed\n");
3189                 goto out;
3190         }
3191
3192         rc = ipw_fw_dma_wait(priv);
3193         if (rc) {
3194                 IPW_ERROR("dmaWaitSync Failed\n");
3195                 goto out;
3196         }
3197       out:
3198         pci_free_consistent(priv->pci_dev, len, shared_virt, shared_phys);
3199         return rc;
3200 }
3201
3202 /* stop nic */
3203 static int ipw_stop_nic(struct ipw_priv *priv)
3204 {
3205         int rc = 0;
3206
3207         /* stop */
3208         ipw_write32(priv, IPW_RESET_REG, IPW_RESET_REG_STOP_MASTER);
3209
3210         rc = ipw_poll_bit(priv, IPW_RESET_REG,
3211                           IPW_RESET_REG_MASTER_DISABLED, 500);
3212         if (rc < 0) {
3213                 IPW_ERROR("wait for reg master disabled failed after 500ms\n");
3214                 return rc;
3215         }
3216
3217         ipw_set_bit(priv, IPW_RESET_REG, CBD_RESET_REG_PRINCETON_RESET);
3218
3219         return rc;
3220 }
3221
3222 static void ipw_start_nic(struct ipw_priv *priv)
3223 {
3224         IPW_DEBUG_TRACE(">>\n");
3225
3226         /* prvHwStartNic  release ARC */
3227         ipw_clear_bit(priv, IPW_RESET_REG,
3228                       IPW_RESET_REG_MASTER_DISABLED |
3229                       IPW_RESET_REG_STOP_MASTER |
3230                       CBD_RESET_REG_PRINCETON_RESET);
3231
3232         /* enable power management */
3233         ipw_set_bit(priv, IPW_GP_CNTRL_RW,
3234                     IPW_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY);
3235
3236         IPW_DEBUG_TRACE("<<\n");
3237 }
3238
3239 static int ipw_init_nic(struct ipw_priv *priv)
3240 {
3241         int rc;
3242
3243         IPW_DEBUG_TRACE(">>\n");
3244         /* reset */
3245         /*prvHwInitNic */
3246         /* set "initialization complete" bit to move adapter to D0 state */
3247         ipw_set_bit(priv, IPW_GP_CNTRL_RW, IPW_GP_CNTRL_BIT_INIT_DONE);
3248
3249         /* low-level PLL activation */
3250         ipw_write32(priv, IPW_READ_INT_REGISTER,
3251                     IPW_BIT_INT_HOST_SRAM_READ_INT_REGISTER);
3252
3253         /* wait for clock stabilization */
3254         rc = ipw_poll_bit(priv, IPW_GP_CNTRL_RW,
3255                           IPW_GP_CNTRL_BIT_CLOCK_READY, 250);
3256         if (rc < 0)
3257                 IPW_DEBUG_INFO("FAILED wait for clock stablization\n");
3258
3259         /* assert SW reset */
3260         ipw_set_bit(priv, IPW_RESET_REG, IPW_RESET_REG_SW_RESET);
3261
3262         udelay(10);
3263
3264         /* set "initialization complete" bit to move adapter to D0 state */
3265         ipw_set_bit(priv, IPW_GP_CNTRL_RW, IPW_GP_CNTRL_BIT_INIT_DONE);
3266
3267         IPW_DEBUG_TRACE(">>\n");
3268         return 0;
3269 }
3270
3271 /* Call this function from process context, it will sleep in request_firmware.
3272  * Probe is an ok place to call this from.
3273  */
3274 static int ipw_reset_nic(struct ipw_priv *priv)
3275 {
3276         int rc = 0;
3277         unsigned long flags;
3278
3279         IPW_DEBUG_TRACE(">>\n");
3280
3281         rc = ipw_init_nic(priv);
3282
3283         spin_lock_irqsave(&priv->lock, flags);
3284         /* Clear the 'host command active' bit... */
3285         priv->status &= ~STATUS_HCMD_ACTIVE;
3286         wake_up_interruptible(&priv->wait_command_queue);
3287         priv->status &= ~(STATUS_SCANNING | STATUS_SCAN_ABORTING);
3288         wake_up_interruptible(&priv->wait_state);
3289         spin_unlock_irqrestore(&priv->lock, flags);
3290
3291         IPW_DEBUG_TRACE("<<\n");
3292         return rc;
3293 }
3294
3295
3296 struct ipw_fw {
3297         __le32 ver;
3298         __le32 boot_size;
3299         __le32 ucode_size;
3300         __le32 fw_size;
3301         u8 data[0];
3302 };
3303
3304 static int ipw_get_fw(struct ipw_priv *priv,
3305                       const struct firmware **raw, const char *name)
3306 {
3307         struct ipw_fw *fw;
3308         int rc;
3309
3310         /* ask firmware_class module to get the boot firmware off disk */
3311         rc = request_firmware(raw, name, &priv->pci_dev->dev);
3312         if (rc < 0) {
3313                 IPW_ERROR("%s request_firmware failed: Reason %d\n", name, rc);
3314                 return rc;
3315         }
3316
3317         if ((*raw)->size < sizeof(*fw)) {
3318                 IPW_ERROR("%s is too small (%zd)\n", name, (*raw)->size);
3319                 return -EINVAL;
3320         }
3321
3322         fw = (void *)(*raw)->data;
3323
3324         if ((*raw)->size < sizeof(*fw) + le32_to_cpu(fw->boot_size) +
3325             le32_to_cpu(fw->ucode_size) + le32_to_cpu(fw->fw_size)) {
3326                 IPW_ERROR("%s is too small or corrupt (%zd)\n",
3327                           name, (*raw)->size);
3328                 return -EINVAL;
3329         }
3330
3331         IPW_DEBUG_INFO("Read firmware '%s' image v%d.%d (%zd bytes)\n",
3332                        name,
3333                        le32_to_cpu(fw->ver) >> 16,
3334                        le32_to_cpu(fw->ver) & 0xff,
3335                        (*raw)->size - sizeof(*fw));
3336         return 0;
3337 }
3338
3339 #define IPW_RX_BUF_SIZE (3000)
3340
3341 static void ipw_rx_queue_reset(struct ipw_priv *priv,
3342                                       struct ipw_rx_queue *rxq)
3343 {
3344         unsigned long flags;
3345         int i;
3346
3347         spin_lock_irqsave(&rxq->lock, flags);
3348
3349         INIT_LIST_HEAD(&rxq->rx_free);
3350         INIT_LIST_HEAD(&rxq->rx_used);
3351
3352         /* Fill the rx_used queue with _all_ of the Rx buffers */
3353         for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
3354                 /* In the reset function, these buffers may have been allocated
3355                  * to an SKB, so we need to unmap and free potential storage */
3356                 if (rxq->pool[i].skb != NULL) {
3357                         pci_unmap_single(priv->pci_dev, rxq->pool[i].dma_addr,
3358                                          IPW_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3359                         dev_kfree_skb(rxq->pool[i].skb);
3360                         rxq->pool[i].skb = NULL;
3361                 }
3362                 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
3363         }
3364
3365         /* Set us so that we have processed and used all buffers, but have
3366          * not restocked the Rx queue with fresh buffers */
3367         rxq->read = rxq->write = 0;
3368         rxq->free_count = 0;
3369         spin_unlock_irqrestore(&rxq->lock, flags);
3370 }
3371
3372 #ifdef CONFIG_PM
3373 static int fw_loaded = 0;
3374 static const struct firmware *raw = NULL;
3375
3376 static void free_firmware(void)
3377 {
3378         if (fw_loaded) {
3379                 release_firmware(raw);
3380                 raw = NULL;
3381                 fw_loaded = 0;
3382         }
3383 }
3384 #else
3385 #define free_firmware() do {} while (0)
3386 #endif
3387
3388 static int ipw_load(struct ipw_priv *priv)
3389 {
3390 #ifndef CONFIG_PM
3391         const struct firmware *raw = NULL;
3392 #endif
3393         struct ipw_fw *fw;
3394         u8 *boot_img, *ucode_img, *fw_img;
3395         u8 *name = NULL;
3396         int rc = 0, retries = 3;
3397
3398         switch (priv->ieee->iw_mode) {
3399         case IW_MODE_ADHOC:
3400                 name = "ipw2200-ibss.fw";
3401                 break;
3402 #ifdef CONFIG_IPW2200_MONITOR
3403         case IW_MODE_MONITOR:
3404                 name = "ipw2200-sniffer.fw";
3405                 break;
3406 #endif
3407         case IW_MODE_INFRA:
3408                 name = "ipw2200-bss.fw";
3409                 break;
3410         }
3411
3412         if (!name) {
3413                 rc = -EINVAL;
3414                 goto error;
3415         }
3416
3417 #ifdef CONFIG_PM
3418         if (!fw_loaded) {
3419 #endif
3420                 rc = ipw_get_fw(priv, &raw, name);
3421                 if (rc < 0)
3422                         goto error;
3423 #ifdef CONFIG_PM
3424         }
3425 #endif
3426
3427         fw = (void *)raw->data;
3428         boot_img = &fw->data[0];
3429         ucode_img = &fw->data[le32_to_cpu(fw->boot_size)];
3430         fw_img = &fw->data[le32_to_cpu(fw->boot_size) +
3431                            le32_to_cpu(fw->ucode_size)];
3432
3433         if (rc < 0)
3434                 goto error;
3435
3436         if (!priv->rxq)
3437                 priv->rxq = ipw_rx_queue_alloc(priv);
3438         else
3439                 ipw_rx_queue_reset(priv, priv->rxq);
3440         if (!priv->rxq) {
3441                 IPW_ERROR("Unable to initialize Rx queue\n");
3442                 goto error;
3443         }
3444
3445       retry:
3446         /* Ensure interrupts are disabled */
3447         ipw_write32(priv, IPW_INTA_MASK_R, ~IPW_INTA_MASK_ALL);
3448         priv->status &= ~STATUS_INT_ENABLED;
3449
3450         /* ack pending interrupts */
3451         ipw_write32(priv, IPW_INTA_RW, IPW_INTA_MASK_ALL);
3452
3453         ipw_stop_nic(priv);
3454
3455         rc = ipw_reset_nic(priv);
3456         if (rc < 0) {
3457                 IPW_ERROR("Unable to reset NIC\n");
3458                 goto error;
3459         }
3460
3461         ipw_zero_memory(priv, IPW_NIC_SRAM_LOWER_BOUND,
3462                         IPW_NIC_SRAM_UPPER_BOUND - IPW_NIC_SRAM_LOWER_BOUND);
3463
3464         /* DMA the initial boot firmware into the device */
3465         rc = ipw_load_firmware(priv, boot_img, le32_to_cpu(fw->boot_size));
3466         if (rc < 0) {
3467                 IPW_ERROR("Unable to load boot firmware: %d\n", rc);
3468                 goto error;
3469         }
3470
3471         /* kick start the device */
3472         ipw_start_nic(priv);
3473
3474         /* wait for the device to finish its initial startup sequence */
3475         rc = ipw_poll_bit(priv, IPW_INTA_RW,
3476                           IPW_INTA_BIT_FW_INITIALIZATION_DONE, 500);
3477         if (rc < 0) {
3478                 IPW_ERROR("device failed to boot initial fw image\n");
3479                 goto error;
3480         }
3481         IPW_DEBUG_INFO("initial device response after %dms\n", rc);
3482
3483         /* ack fw init done interrupt */
3484         ipw_write32(priv, IPW_INTA_RW, IPW_INTA_BIT_FW_INITIALIZATION_DONE);
3485
3486         /* DMA the ucode into the device */
3487         rc = ipw_load_ucode(priv, ucode_img, le32_to_cpu(fw->ucode_size));
3488         if (rc < 0) {
3489                 IPW_ERROR("Unable to load ucode: %d\n", rc);
3490                 goto error;
3491         }
3492
3493         /* stop nic */
3494         ipw_stop_nic(priv);
3495
3496         /* DMA bss firmware into the device */
3497         rc = ipw_load_firmware(priv, fw_img, le32_to_cpu(fw->fw_size));
3498         if (rc < 0) {
3499                 IPW_ERROR("Unable to load firmware: %d\n", rc);
3500                 goto error;
3501         }
3502 #ifdef CONFIG_PM
3503         fw_loaded = 1;
3504 #endif
3505
3506         ipw_write32(priv, IPW_EEPROM_LOAD_DISABLE, 0);
3507
3508         rc = ipw_queue_reset(priv);
3509         if (rc < 0) {
3510                 IPW_ERROR("Unable to initialize queues\n");
3511                 goto error;
3512         }
3513
3514         /* Ensure interrupts are disabled */
3515         ipw_write32(priv, IPW_INTA_MASK_R, ~IPW_INTA_MASK_ALL);
3516         /* ack pending interrupts */
3517         ipw_write32(priv, IPW_INTA_RW, IPW_INTA_MASK_ALL);
3518
3519         /* kick start the device */
3520         ipw_start_nic(priv);
3521
3522         if (ipw_read32(priv, IPW_INTA_RW) & IPW_INTA_BIT_PARITY_ERROR) {
3523                 if (retries > 0) {
3524                         IPW_WARNING("Parity error.  Retrying init.\n");
3525                         retries--;
3526                         goto retry;
3527                 }
3528
3529                 IPW_ERROR("TODO: Handle parity error -- schedule restart?\n");
3530                 rc = -EIO;
3531                 goto error;
3532         }
3533
3534         /* wait for the device */
3535         rc = ipw_poll_bit(priv, IPW_INTA_RW,
3536                           IPW_INTA_BIT_FW_INITIALIZATION_DONE, 500);
3537         if (rc < 0) {
3538                 IPW_ERROR("device failed to start within 500ms\n");
3539                 goto error;
3540         }
3541         IPW_DEBUG_INFO("device response after %dms\n", rc);
3542
3543         /* ack fw init done interrupt */
3544         ipw_write32(priv, IPW_INTA_RW, IPW_INTA_BIT_FW_INITIALIZATION_DONE);
3545
3546         /* read eeprom data and initialize the eeprom region of sram */
3547         priv->eeprom_delay = 1;
3548         ipw_eeprom_init_sram(priv);
3549
3550         /* enable interrupts */
3551         ipw_enable_interrupts(priv);
3552
3553         /* Ensure our queue has valid packets */
3554         ipw_rx_queue_replenish(priv);
3555
3556         ipw_write32(priv, IPW_RX_READ_INDEX, priv->rxq->read);
3557
3558         /* ack pending interrupts */
3559         ipw_write32(priv, IPW_INTA_RW, IPW_INTA_MASK_ALL);
3560
3561 #ifndef CONFIG_PM
3562         release_firmware(raw);
3563 #endif
3564         return 0;
3565
3566       error:
3567         if (priv->rxq) {
3568                 ipw_rx_queue_free(priv, priv->rxq);
3569                 priv->rxq = NULL;
3570         }
3571         ipw_tx_queue_free(priv);
3572         if (raw)
3573                 release_firmware(raw);
3574 #ifdef CONFIG_PM
3575         fw_loaded = 0;
3576         raw = NULL;
3577 #endif
3578
3579         return rc;
3580 }
3581
3582 /**
3583  * DMA services
3584  *
3585  * Theory of operation
3586  *
3587  * A queue is a circular buffers with 'Read' and 'Write' pointers.
3588  * 2 empty entries always kept in the buffer to protect from overflow.
3589  *
3590  * For Tx queue, there are low mark and high mark limits. If, after queuing
3591  * the packet for Tx, free space become < low mark, Tx queue stopped. When
3592  * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
3593  * Tx queue resumed.
3594  *
3595  * The IPW operates with six queues, one receive queue in the device's
3596  * sram, one transmit queue for sending commands to the device firmware,
3597  * and four transmit queues for data.
3598  *
3599  * The four transmit queues allow for performing quality of service (qos)
3600  * transmissions as per the 802.11 protocol.  Currently Linux does not
3601  * provide a mechanism to the user for utilizing prioritized queues, so
3602  * we only utilize the first data transmit queue (queue1).
3603  */
3604
3605 /**
3606  * Driver allocates buffers of this size for Rx
3607  */
3608
3609 /**
3610  * ipw_rx_queue_space - Return number of free slots available in queue.
3611  */
3612 static int ipw_rx_queue_space(const struct ipw_rx_queue *q)
3613 {
3614         int s = q->read - q->write;
3615         if (s <= 0)
3616                 s += RX_QUEUE_SIZE;
3617         /* keep some buffer to not confuse full and empty queue */
3618         s -= 2;
3619         if (s < 0)
3620                 s = 0;
3621         return s;
3622 }
3623
3624 static inline int ipw_tx_queue_space(const struct clx2_queue *q)
3625 {
3626         int s = q->last_used - q->first_empty;
3627         if (s <= 0)
3628                 s += q->n_bd;
3629         s -= 2;                 /* keep some reserve to not confuse empty and full situations */
3630         if (s < 0)
3631                 s = 0;
3632         return s;
3633 }
3634
3635 static inline int ipw_queue_inc_wrap(int index, int n_bd)
3636 {
3637         return (++index == n_bd) ? 0 : index;
3638 }
3639
3640 /**
3641  * Initialize common DMA queue structure
3642  *
3643  * @param q                queue to init
3644  * @param count            Number of BD's to allocate. Should be power of 2
3645  * @param read_register    Address for 'read' register
3646  *                         (not offset within BAR, full address)
3647  * @param write_register   Address for 'write' register
3648  *                         (not offset within BAR, full address)
3649  * @param base_register    Address for 'base' register
3650  *                         (not offset within BAR, full address)
3651  * @param size             Address for 'size' register
3652  *                         (not offset within BAR, full address)
3653  */
3654 static void ipw_queue_init(struct ipw_priv *priv, struct clx2_queue *q,
3655                            int count, u32 read, u32 write, u32 base, u32 size)
3656 {
3657         q->n_bd = count;
3658
3659         q->low_mark = q->n_bd / 4;
3660         if (q->low_mark < 4)
3661                 q->low_mark = 4;
3662
3663         q->high_mark = q->n_bd / 8;
3664         if (q->high_mark < 2)
3665                 q->high_mark = 2;
3666
3667         q->first_empty = q->last_used = 0;
3668         q->reg_r = read;
3669         q->reg_w = write;
3670
3671         ipw_write32(priv, base, q->dma_addr);
3672         ipw_write32(priv, size, count);
3673         ipw_write32(priv, read, 0);
3674         ipw_write32(priv, write, 0);
3675
3676         _ipw_read32(priv, 0x90);
3677 }
3678
3679 static int ipw_queue_tx_init(struct ipw_priv *priv,
3680                              struct clx2_tx_queue *q,
3681                              int count, u32 read, u32 write, u32 base, u32 size)
3682 {
3683         struct pci_dev *dev = priv->pci_dev;
3684
3685         q->txb = kmalloc(sizeof(q->txb[0]) * count, GFP_KERNEL);
3686         if (!q->txb) {
3687                 IPW_ERROR("vmalloc for auxilary BD structures failed\n");
3688                 return -ENOMEM;
3689         }
3690
3691         q->bd =
3692             pci_alloc_consistent(dev, sizeof(q->bd[0]) * count, &q->q.dma_addr);
3693         if (!q->bd) {
3694                 IPW_ERROR("pci_alloc_consistent(%zd) failed\n",
3695                           sizeof(q->bd[0]) * count);
3696                 kfree(q->txb);
3697                 q->txb = NULL;
3698                 return -ENOMEM;
3699         }
3700
3701         ipw_queue_init(priv, &q->q, count, read, write, base, size);
3702         return 0;
3703 }
3704
3705 /**
3706  * Free one TFD, those at index [txq->q.last_used].
3707  * Do NOT advance any indexes
3708  *
3709  * @param dev
3710  * @param txq
3711  */
3712 static void ipw_queue_tx_free_tfd(struct ipw_priv *priv,
3713                                   struct clx2_tx_queue *txq)
3714 {
3715         struct tfd_frame *bd = &txq->bd[txq->q.last_used];
3716         struct pci_dev *dev = priv->pci_dev;
3717         int i;
3718
3719         /* classify bd */
3720         if (bd->control_flags.message_type == TX_HOST_COMMAND_TYPE)
3721                 /* nothing to cleanup after for host commands */
3722                 return;
3723
3724         /* sanity check */
3725         if (le32_to_cpu(bd->u.data.num_chunks) > NUM_TFD_CHUNKS) {
3726                 IPW_ERROR("Too many chunks: %i\n",
3727                           le32_to_cpu(bd->u.data.num_chunks));
3728                 /** @todo issue