Merge branch 'upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/linville...
[sfrench/cifs-2.6.git] / drivers / net / wireless / ipw2200.c
1 /******************************************************************************
2
3   Copyright(c) 2003 - 2006 Intel Corporation. All rights reserved.
4
5   802.11 status code portion of this file from ethereal-0.10.6:
6     Copyright 2000, Axis Communications AB
7     Ethereal - Network traffic analyzer
8     By Gerald Combs <gerald@ethereal.com>
9     Copyright 1998 Gerald Combs
10
11   This program is free software; you can redistribute it and/or modify it
12   under the terms of version 2 of the GNU General Public License as
13   published by the Free Software Foundation.
14
15   This program is distributed in the hope that it will be useful, but WITHOUT
16   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
18   more details.
19
20   You should have received a copy of the GNU General Public License along with
21   this program; if not, write to the Free Software Foundation, Inc., 59
22   Temple Place - Suite 330, Boston, MA  02111-1307, USA.
23
24   The full GNU General Public License is included in this distribution in the
25   file called LICENSE.
26
27   Contact Information:
28   James P. Ketrenos <ipw2100-admin@linux.intel.com>
29   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30
31 ******************************************************************************/
32
33 #include "ipw2200.h"
34 #include <linux/version.h>
35
36 #define IPW2200_VERSION "git-1.1.1"
37 #define DRV_DESCRIPTION "Intel(R) PRO/Wireless 2200/2915 Network Driver"
38 #define DRV_COPYRIGHT   "Copyright(c) 2003-2006 Intel Corporation"
39 #define DRV_VERSION     IPW2200_VERSION
40
41 #define ETH_P_80211_STATS (ETH_P_80211_RAW + 1)
42
43 MODULE_DESCRIPTION(DRV_DESCRIPTION);
44 MODULE_VERSION(DRV_VERSION);
45 MODULE_AUTHOR(DRV_COPYRIGHT);
46 MODULE_LICENSE("GPL");
47
48 static int cmdlog = 0;
49 static int debug = 0;
50 static int channel = 0;
51 static int mode = 0;
52
53 static u32 ipw_debug_level;
54 static int associate = 1;
55 static int auto_create = 1;
56 static int led = 0;
57 static int disable = 0;
58 static int bt_coexist = 0;
59 static int hwcrypto = 0;
60 static int roaming = 1;
61 static const char ipw_modes[] = {
62         'a', 'b', 'g', '?'
63 };
64
65 #ifdef CONFIG_IPW_QOS
66 static int qos_enable = 0;
67 static int qos_burst_enable = 0;
68 static int qos_no_ack_mask = 0;
69 static int burst_duration_CCK = 0;
70 static int burst_duration_OFDM = 0;
71
72 static struct ieee80211_qos_parameters def_qos_parameters_OFDM = {
73         {QOS_TX0_CW_MIN_OFDM, QOS_TX1_CW_MIN_OFDM, QOS_TX2_CW_MIN_OFDM,
74          QOS_TX3_CW_MIN_OFDM},
75         {QOS_TX0_CW_MAX_OFDM, QOS_TX1_CW_MAX_OFDM, QOS_TX2_CW_MAX_OFDM,
76          QOS_TX3_CW_MAX_OFDM},
77         {QOS_TX0_AIFS, QOS_TX1_AIFS, QOS_TX2_AIFS, QOS_TX3_AIFS},
78         {QOS_TX0_ACM, QOS_TX1_ACM, QOS_TX2_ACM, QOS_TX3_ACM},
79         {QOS_TX0_TXOP_LIMIT_OFDM, QOS_TX1_TXOP_LIMIT_OFDM,
80          QOS_TX2_TXOP_LIMIT_OFDM, QOS_TX3_TXOP_LIMIT_OFDM}
81 };
82
83 static struct ieee80211_qos_parameters def_qos_parameters_CCK = {
84         {QOS_TX0_CW_MIN_CCK, QOS_TX1_CW_MIN_CCK, QOS_TX2_CW_MIN_CCK,
85          QOS_TX3_CW_MIN_CCK},
86         {QOS_TX0_CW_MAX_CCK, QOS_TX1_CW_MAX_CCK, QOS_TX2_CW_MAX_CCK,
87          QOS_TX3_CW_MAX_CCK},
88         {QOS_TX0_AIFS, QOS_TX1_AIFS, QOS_TX2_AIFS, QOS_TX3_AIFS},
89         {QOS_TX0_ACM, QOS_TX1_ACM, QOS_TX2_ACM, QOS_TX3_ACM},
90         {QOS_TX0_TXOP_LIMIT_CCK, QOS_TX1_TXOP_LIMIT_CCK, QOS_TX2_TXOP_LIMIT_CCK,
91          QOS_TX3_TXOP_LIMIT_CCK}
92 };
93
94 static struct ieee80211_qos_parameters def_parameters_OFDM = {
95         {DEF_TX0_CW_MIN_OFDM, DEF_TX1_CW_MIN_OFDM, DEF_TX2_CW_MIN_OFDM,
96          DEF_TX3_CW_MIN_OFDM},
97         {DEF_TX0_CW_MAX_OFDM, DEF_TX1_CW_MAX_OFDM, DEF_TX2_CW_MAX_OFDM,
98          DEF_TX3_CW_MAX_OFDM},
99         {DEF_TX0_AIFS, DEF_TX1_AIFS, DEF_TX2_AIFS, DEF_TX3_AIFS},
100         {DEF_TX0_ACM, DEF_TX1_ACM, DEF_TX2_ACM, DEF_TX3_ACM},
101         {DEF_TX0_TXOP_LIMIT_OFDM, DEF_TX1_TXOP_LIMIT_OFDM,
102          DEF_TX2_TXOP_LIMIT_OFDM, DEF_TX3_TXOP_LIMIT_OFDM}
103 };
104
105 static struct ieee80211_qos_parameters def_parameters_CCK = {
106         {DEF_TX0_CW_MIN_CCK, DEF_TX1_CW_MIN_CCK, DEF_TX2_CW_MIN_CCK,
107          DEF_TX3_CW_MIN_CCK},
108         {DEF_TX0_CW_MAX_CCK, DEF_TX1_CW_MAX_CCK, DEF_TX2_CW_MAX_CCK,
109          DEF_TX3_CW_MAX_CCK},
110         {DEF_TX0_AIFS, DEF_TX1_AIFS, DEF_TX2_AIFS, DEF_TX3_AIFS},
111         {DEF_TX0_ACM, DEF_TX1_ACM, DEF_TX2_ACM, DEF_TX3_ACM},
112         {DEF_TX0_TXOP_LIMIT_CCK, DEF_TX1_TXOP_LIMIT_CCK, DEF_TX2_TXOP_LIMIT_CCK,
113          DEF_TX3_TXOP_LIMIT_CCK}
114 };
115
116 static u8 qos_oui[QOS_OUI_LEN] = { 0x00, 0x50, 0xF2 };
117
118 static int from_priority_to_tx_queue[] = {
119         IPW_TX_QUEUE_1, IPW_TX_QUEUE_2, IPW_TX_QUEUE_2, IPW_TX_QUEUE_1,
120         IPW_TX_QUEUE_3, IPW_TX_QUEUE_3, IPW_TX_QUEUE_4, IPW_TX_QUEUE_4
121 };
122
123 static u32 ipw_qos_get_burst_duration(struct ipw_priv *priv);
124
125 static int ipw_send_qos_params_command(struct ipw_priv *priv, struct ieee80211_qos_parameters
126                                        *qos_param);
127 static int ipw_send_qos_info_command(struct ipw_priv *priv, struct ieee80211_qos_information_element
128                                      *qos_param);
129 #endif                          /* CONFIG_IPW_QOS */
130
131 static struct iw_statistics *ipw_get_wireless_stats(struct net_device *dev);
132 static void ipw_remove_current_network(struct ipw_priv *priv);
133 static void ipw_rx(struct ipw_priv *priv);
134 static int ipw_queue_tx_reclaim(struct ipw_priv *priv,
135                                 struct clx2_tx_queue *txq, int qindex);
136 static int ipw_queue_reset(struct ipw_priv *priv);
137
138 static int ipw_queue_tx_hcmd(struct ipw_priv *priv, int hcmd, void *buf,
139                              int len, int sync);
140
141 static void ipw_tx_queue_free(struct ipw_priv *);
142
143 static struct ipw_rx_queue *ipw_rx_queue_alloc(struct ipw_priv *);
144 static void ipw_rx_queue_free(struct ipw_priv *, struct ipw_rx_queue *);
145 static void ipw_rx_queue_replenish(void *);
146 static int ipw_up(struct ipw_priv *);
147 static void ipw_bg_up(void *);
148 static void ipw_down(struct ipw_priv *);
149 static void ipw_bg_down(void *);
150 static int ipw_config(struct ipw_priv *);
151 static int init_supported_rates(struct ipw_priv *priv,
152                                 struct ipw_supported_rates *prates);
153 static void ipw_set_hwcrypto_keys(struct ipw_priv *);
154 static void ipw_send_wep_keys(struct ipw_priv *, int);
155
156 static int snprint_line(char *buf, size_t count,
157                         const u8 * data, u32 len, u32 ofs)
158 {
159         int out, i, j, l;
160         char c;
161
162         out = snprintf(buf, count, "%08X", ofs);
163
164         for (l = 0, i = 0; i < 2; i++) {
165                 out += snprintf(buf + out, count - out, " ");
166                 for (j = 0; j < 8 && l < len; j++, l++)
167                         out += snprintf(buf + out, count - out, "%02X ",
168                                         data[(i * 8 + j)]);
169                 for (; j < 8; j++)
170                         out += snprintf(buf + out, count - out, "   ");
171         }
172
173         out += snprintf(buf + out, count - out, " ");
174         for (l = 0, i = 0; i < 2; i++) {
175                 out += snprintf(buf + out, count - out, " ");
176                 for (j = 0; j < 8 && l < len; j++, l++) {
177                         c = data[(i * 8 + j)];
178                         if (!isascii(c) || !isprint(c))
179                                 c = '.';
180
181                         out += snprintf(buf + out, count - out, "%c", c);
182                 }
183
184                 for (; j < 8; j++)
185                         out += snprintf(buf + out, count - out, " ");
186         }
187
188         return out;
189 }
190
191 static void printk_buf(int level, const u8 * data, u32 len)
192 {
193         char line[81];
194         u32 ofs = 0;
195         if (!(ipw_debug_level & level))
196                 return;
197
198         while (len) {
199                 snprint_line(line, sizeof(line), &data[ofs],
200                              min(len, 16U), ofs);
201                 printk(KERN_DEBUG "%s\n", line);
202                 ofs += 16;
203                 len -= min(len, 16U);
204         }
205 }
206
207 static int snprintk_buf(u8 * output, size_t size, const u8 * data, size_t len)
208 {
209         size_t out = size;
210         u32 ofs = 0;
211         int total = 0;
212
213         while (size && len) {
214                 out = snprint_line(output, size, &data[ofs],
215                                    min_t(size_t, len, 16U), ofs);
216
217                 ofs += 16;
218                 output += out;
219                 size -= out;
220                 len -= min_t(size_t, len, 16U);
221                 total += out;
222         }
223         return total;
224 }
225
226 /* alias for 32-bit indirect read (for SRAM/reg above 4K), with debug wrapper */
227 static u32 _ipw_read_reg32(struct ipw_priv *priv, u32 reg);
228 #define ipw_read_reg32(a, b) _ipw_read_reg32(a, b)
229
230 /* alias for 8-bit indirect read (for SRAM/reg above 4K), with debug wrapper */
231 static u8 _ipw_read_reg8(struct ipw_priv *ipw, u32 reg);
232 #define ipw_read_reg8(a, b) _ipw_read_reg8(a, b)
233
234 /* 8-bit indirect write (for SRAM/reg above 4K), with debug wrapper */
235 static void _ipw_write_reg8(struct ipw_priv *priv, u32 reg, u8 value);
236 static inline void ipw_write_reg8(struct ipw_priv *a, u32 b, u8 c)
237 {
238         IPW_DEBUG_IO("%s %d: write_indirect8(0x%08X, 0x%08X)\n", __FILE__,
239                      __LINE__, (u32) (b), (u32) (c));
240         _ipw_write_reg8(a, b, c);
241 }
242
243 /* 16-bit indirect write (for SRAM/reg above 4K), with debug wrapper */
244 static void _ipw_write_reg16(struct ipw_priv *priv, u32 reg, u16 value);
245 static inline void ipw_write_reg16(struct ipw_priv *a, u32 b, u16 c)
246 {
247         IPW_DEBUG_IO("%s %d: write_indirect16(0x%08X, 0x%08X)\n", __FILE__,
248                      __LINE__, (u32) (b), (u32) (c));
249         _ipw_write_reg16(a, b, c);
250 }
251
252 /* 32-bit indirect write (for SRAM/reg above 4K), with debug wrapper */
253 static void _ipw_write_reg32(struct ipw_priv *priv, u32 reg, u32 value);
254 static inline void ipw_write_reg32(struct ipw_priv *a, u32 b, u32 c)
255 {
256         IPW_DEBUG_IO("%s %d: write_indirect32(0x%08X, 0x%08X)\n", __FILE__,
257                      __LINE__, (u32) (b), (u32) (c));
258         _ipw_write_reg32(a, b, c);
259 }
260
261 /* 8-bit direct write (low 4K) */
262 #define _ipw_write8(ipw, ofs, val) writeb((val), (ipw)->hw_base + (ofs))
263
264 /* 8-bit direct write (for low 4K of SRAM/regs), with debug wrapper */
265 #define ipw_write8(ipw, ofs, val) \
266  IPW_DEBUG_IO("%s %d: write_direct8(0x%08X, 0x%08X)\n", __FILE__, __LINE__, (u32)(ofs), (u32)(val)); \
267  _ipw_write8(ipw, ofs, val)
268
269 /* 16-bit direct write (low 4K) */
270 #define _ipw_write16(ipw, ofs, val) writew((val), (ipw)->hw_base + (ofs))
271
272 /* 16-bit direct write (for low 4K of SRAM/regs), with debug wrapper */
273 #define ipw_write16(ipw, ofs, val) \
274  IPW_DEBUG_IO("%s %d: write_direct16(0x%08X, 0x%08X)\n", __FILE__, __LINE__, (u32)(ofs), (u32)(val)); \
275  _ipw_write16(ipw, ofs, val)
276
277 /* 32-bit direct write (low 4K) */
278 #define _ipw_write32(ipw, ofs, val) writel((val), (ipw)->hw_base + (ofs))
279
280 /* 32-bit direct write (for low 4K of SRAM/regs), with debug wrapper */
281 #define ipw_write32(ipw, ofs, val) \
282  IPW_DEBUG_IO("%s %d: write_direct32(0x%08X, 0x%08X)\n", __FILE__, __LINE__, (u32)(ofs), (u32)(val)); \
283  _ipw_write32(ipw, ofs, val)
284
285 /* 8-bit direct read (low 4K) */
286 #define _ipw_read8(ipw, ofs) readb((ipw)->hw_base + (ofs))
287
288 /* 8-bit direct read (low 4K), with debug wrapper */
289 static inline u8 __ipw_read8(char *f, u32 l, struct ipw_priv *ipw, u32 ofs)
290 {
291         IPW_DEBUG_IO("%s %d: read_direct8(0x%08X)\n", f, l, (u32) (ofs));
292         return _ipw_read8(ipw, ofs);
293 }
294
295 /* alias to 8-bit direct read (low 4K of SRAM/regs), with debug wrapper */
296 #define ipw_read8(ipw, ofs) __ipw_read8(__FILE__, __LINE__, ipw, ofs)
297
298 /* 16-bit direct read (low 4K) */
299 #define _ipw_read16(ipw, ofs) readw((ipw)->hw_base + (ofs))
300
301 /* 16-bit direct read (low 4K), with debug wrapper */
302 static inline u16 __ipw_read16(char *f, u32 l, struct ipw_priv *ipw, u32 ofs)
303 {
304         IPW_DEBUG_IO("%s %d: read_direct16(0x%08X)\n", f, l, (u32) (ofs));
305         return _ipw_read16(ipw, ofs);
306 }
307
308 /* alias to 16-bit direct read (low 4K of SRAM/regs), with debug wrapper */
309 #define ipw_read16(ipw, ofs) __ipw_read16(__FILE__, __LINE__, ipw, ofs)
310
311 /* 32-bit direct read (low 4K) */
312 #define _ipw_read32(ipw, ofs) readl((ipw)->hw_base + (ofs))
313
314 /* 32-bit direct read (low 4K), with debug wrapper */
315 static inline u32 __ipw_read32(char *f, u32 l, struct ipw_priv *ipw, u32 ofs)
316 {
317         IPW_DEBUG_IO("%s %d: read_direct32(0x%08X)\n", f, l, (u32) (ofs));
318         return _ipw_read32(ipw, ofs);
319 }
320
321 /* alias to 32-bit direct read (low 4K of SRAM/regs), with debug wrapper */
322 #define ipw_read32(ipw, ofs) __ipw_read32(__FILE__, __LINE__, ipw, ofs)
323
324 /* multi-byte read (above 4K), with debug wrapper */
325 static void _ipw_read_indirect(struct ipw_priv *, u32, u8 *, int);
326 static inline void __ipw_read_indirect(const char *f, int l,
327                                        struct ipw_priv *a, u32 b, u8 * c, int d)
328 {
329         IPW_DEBUG_IO("%s %d: read_indirect(0x%08X) %d bytes\n", f, l, (u32) (b),
330                      d);
331         _ipw_read_indirect(a, b, c, d);
332 }
333
334 /* alias to multi-byte read (SRAM/regs above 4K), with debug wrapper */
335 #define ipw_read_indirect(a, b, c, d) __ipw_read_indirect(__FILE__, __LINE__, a, b, c, d)
336
337 /* alias to multi-byte read (SRAM/regs above 4K), with debug wrapper */
338 static void _ipw_write_indirect(struct ipw_priv *priv, u32 addr, u8 * data,
339                                 int num);
340 #define ipw_write_indirect(a, b, c, d) \
341         IPW_DEBUG_IO("%s %d: write_indirect(0x%08X) %d bytes\n", __FILE__, __LINE__, (u32)(b), d); \
342         _ipw_write_indirect(a, b, c, d)
343
344 /* 32-bit indirect write (above 4K) */
345 static void _ipw_write_reg32(struct ipw_priv *priv, u32 reg, u32 value)
346 {
347         IPW_DEBUG_IO(" %p : reg = 0x%8X : value = 0x%8X\n", priv, reg, value);
348         _ipw_write32(priv, IPW_INDIRECT_ADDR, reg);
349         _ipw_write32(priv, IPW_INDIRECT_DATA, value);
350 }
351
352 /* 8-bit indirect write (above 4K) */
353 static void _ipw_write_reg8(struct ipw_priv *priv, u32 reg, u8 value)
354 {
355         u32 aligned_addr = reg & IPW_INDIRECT_ADDR_MASK;        /* dword align */
356         u32 dif_len = reg - aligned_addr;
357
358         IPW_DEBUG_IO(" reg = 0x%8X : value = 0x%8X\n", reg, value);
359         _ipw_write32(priv, IPW_INDIRECT_ADDR, aligned_addr);
360         _ipw_write8(priv, IPW_INDIRECT_DATA + dif_len, value);
361 }
362
363 /* 16-bit indirect write (above 4K) */
364 static void _ipw_write_reg16(struct ipw_priv *priv, u32 reg, u16 value)
365 {
366         u32 aligned_addr = reg & IPW_INDIRECT_ADDR_MASK;        /* dword align */
367         u32 dif_len = (reg - aligned_addr) & (~0x1ul);
368
369         IPW_DEBUG_IO(" reg = 0x%8X : value = 0x%8X\n", reg, value);
370         _ipw_write32(priv, IPW_INDIRECT_ADDR, aligned_addr);
371         _ipw_write16(priv, IPW_INDIRECT_DATA + dif_len, value);
372 }
373
374 /* 8-bit indirect read (above 4K) */
375 static u8 _ipw_read_reg8(struct ipw_priv *priv, u32 reg)
376 {
377         u32 word;
378         _ipw_write32(priv, IPW_INDIRECT_ADDR, reg & IPW_INDIRECT_ADDR_MASK);
379         IPW_DEBUG_IO(" reg = 0x%8X : \n", reg);
380         word = _ipw_read32(priv, IPW_INDIRECT_DATA);
381         return (word >> ((reg & 0x3) * 8)) & 0xff;
382 }
383
384 /* 32-bit indirect read (above 4K) */
385 static u32 _ipw_read_reg32(struct ipw_priv *priv, u32 reg)
386 {
387         u32 value;
388
389         IPW_DEBUG_IO("%p : reg = 0x%08x\n", priv, reg);
390
391         _ipw_write32(priv, IPW_INDIRECT_ADDR, reg);
392         value = _ipw_read32(priv, IPW_INDIRECT_DATA);
393         IPW_DEBUG_IO(" reg = 0x%4X : value = 0x%4x \n", reg, value);
394         return value;
395 }
396
397 /* General purpose, no alignment requirement, iterative (multi-byte) read, */
398 /*    for area above 1st 4K of SRAM/reg space */
399 static void _ipw_read_indirect(struct ipw_priv *priv, u32 addr, u8 * buf,
400                                int num)
401 {
402         u32 aligned_addr = addr & IPW_INDIRECT_ADDR_MASK;       /* dword align */
403         u32 dif_len = addr - aligned_addr;
404         u32 i;
405
406         IPW_DEBUG_IO("addr = %i, buf = %p, num = %i\n", addr, buf, num);
407
408         if (num <= 0) {
409                 return;
410         }
411
412         /* Read the first dword (or portion) byte by byte */
413         if (unlikely(dif_len)) {
414                 _ipw_write32(priv, IPW_INDIRECT_ADDR, aligned_addr);
415                 /* Start reading at aligned_addr + dif_len */
416                 for (i = dif_len; ((i < 4) && (num > 0)); i++, num--)
417                         *buf++ = _ipw_read8(priv, IPW_INDIRECT_DATA + i);
418                 aligned_addr += 4;
419         }
420
421         /* Read all of the middle dwords as dwords, with auto-increment */
422         _ipw_write32(priv, IPW_AUTOINC_ADDR, aligned_addr);
423         for (; num >= 4; buf += 4, aligned_addr += 4, num -= 4)
424                 *(u32 *) buf = _ipw_read32(priv, IPW_AUTOINC_DATA);
425
426         /* Read the last dword (or portion) byte by byte */
427         if (unlikely(num)) {
428                 _ipw_write32(priv, IPW_INDIRECT_ADDR, aligned_addr);
429                 for (i = 0; num > 0; i++, num--)
430                         *buf++ = ipw_read8(priv, IPW_INDIRECT_DATA + i);
431         }
432 }
433
434 /* General purpose, no alignment requirement, iterative (multi-byte) write, */
435 /*    for area above 1st 4K of SRAM/reg space */
436 static void _ipw_write_indirect(struct ipw_priv *priv, u32 addr, u8 * buf,
437                                 int num)
438 {
439         u32 aligned_addr = addr & IPW_INDIRECT_ADDR_MASK;       /* dword align */
440         u32 dif_len = addr - aligned_addr;
441         u32 i;
442
443         IPW_DEBUG_IO("addr = %i, buf = %p, num = %i\n", addr, buf, num);
444
445         if (num <= 0) {
446                 return;
447         }
448
449         /* Write the first dword (or portion) byte by byte */
450         if (unlikely(dif_len)) {
451                 _ipw_write32(priv, IPW_INDIRECT_ADDR, aligned_addr);
452                 /* Start writing at aligned_addr + dif_len */
453                 for (i = dif_len; ((i < 4) && (num > 0)); i++, num--, buf++)
454                         _ipw_write8(priv, IPW_INDIRECT_DATA + i, *buf);
455                 aligned_addr += 4;
456         }
457
458         /* Write all of the middle dwords as dwords, with auto-increment */
459         _ipw_write32(priv, IPW_AUTOINC_ADDR, aligned_addr);
460         for (; num >= 4; buf += 4, aligned_addr += 4, num -= 4)
461                 _ipw_write32(priv, IPW_AUTOINC_DATA, *(u32 *) buf);
462
463         /* Write the last dword (or portion) byte by byte */
464         if (unlikely(num)) {
465                 _ipw_write32(priv, IPW_INDIRECT_ADDR, aligned_addr);
466                 for (i = 0; num > 0; i++, num--, buf++)
467                         _ipw_write8(priv, IPW_INDIRECT_DATA + i, *buf);
468         }
469 }
470
471 /* General purpose, no alignment requirement, iterative (multi-byte) write, */
472 /*    for 1st 4K of SRAM/regs space */
473 static void ipw_write_direct(struct ipw_priv *priv, u32 addr, void *buf,
474                              int num)
475 {
476         memcpy_toio((priv->hw_base + addr), buf, num);
477 }
478
479 /* Set bit(s) in low 4K of SRAM/regs */
480 static inline void ipw_set_bit(struct ipw_priv *priv, u32 reg, u32 mask)
481 {
482         ipw_write32(priv, reg, ipw_read32(priv, reg) | mask);
483 }
484
485 /* Clear bit(s) in low 4K of SRAM/regs */
486 static inline void ipw_clear_bit(struct ipw_priv *priv, u32 reg, u32 mask)
487 {
488         ipw_write32(priv, reg, ipw_read32(priv, reg) & ~mask);
489 }
490
491 static inline void ipw_enable_interrupts(struct ipw_priv *priv)
492 {
493         if (priv->status & STATUS_INT_ENABLED)
494                 return;
495         priv->status |= STATUS_INT_ENABLED;
496         ipw_write32(priv, IPW_INTA_MASK_R, IPW_INTA_MASK_ALL);
497 }
498
499 static inline void ipw_disable_interrupts(struct ipw_priv *priv)
500 {
501         if (!(priv->status & STATUS_INT_ENABLED))
502                 return;
503         priv->status &= ~STATUS_INT_ENABLED;
504         ipw_write32(priv, IPW_INTA_MASK_R, ~IPW_INTA_MASK_ALL);
505 }
506
507 #ifdef CONFIG_IPW2200_DEBUG
508 static char *ipw_error_desc(u32 val)
509 {
510         switch (val) {
511         case IPW_FW_ERROR_OK:
512                 return "ERROR_OK";
513         case IPW_FW_ERROR_FAIL:
514                 return "ERROR_FAIL";
515         case IPW_FW_ERROR_MEMORY_UNDERFLOW:
516                 return "MEMORY_UNDERFLOW";
517         case IPW_FW_ERROR_MEMORY_OVERFLOW:
518                 return "MEMORY_OVERFLOW";
519         case IPW_FW_ERROR_BAD_PARAM:
520                 return "BAD_PARAM";
521         case IPW_FW_ERROR_BAD_CHECKSUM:
522                 return "BAD_CHECKSUM";
523         case IPW_FW_ERROR_NMI_INTERRUPT:
524                 return "NMI_INTERRUPT";
525         case IPW_FW_ERROR_BAD_DATABASE:
526                 return "BAD_DATABASE";
527         case IPW_FW_ERROR_ALLOC_FAIL:
528                 return "ALLOC_FAIL";
529         case IPW_FW_ERROR_DMA_UNDERRUN:
530                 return "DMA_UNDERRUN";
531         case IPW_FW_ERROR_DMA_STATUS:
532                 return "DMA_STATUS";
533         case IPW_FW_ERROR_DINO_ERROR:
534                 return "DINO_ERROR";
535         case IPW_FW_ERROR_EEPROM_ERROR:
536                 return "EEPROM_ERROR";
537         case IPW_FW_ERROR_SYSASSERT:
538                 return "SYSASSERT";
539         case IPW_FW_ERROR_FATAL_ERROR:
540                 return "FATAL_ERROR";
541         default:
542                 return "UNKNOWN_ERROR";
543         }
544 }
545
546 static void ipw_dump_error_log(struct ipw_priv *priv,
547                                struct ipw_fw_error *error)
548 {
549         u32 i;
550
551         if (!error) {
552                 IPW_ERROR("Error allocating and capturing error log.  "
553                           "Nothing to dump.\n");
554                 return;
555         }
556
557         IPW_ERROR("Start IPW Error Log Dump:\n");
558         IPW_ERROR("Status: 0x%08X, Config: %08X\n",
559                   error->status, error->config);
560
561         for (i = 0; i < error->elem_len; i++)
562                 IPW_ERROR("%s %i 0x%08x  0x%08x  0x%08x  0x%08x  0x%08x\n",
563                           ipw_error_desc(error->elem[i].desc),
564                           error->elem[i].time,
565                           error->elem[i].blink1,
566                           error->elem[i].blink2,
567                           error->elem[i].link1,
568                           error->elem[i].link2, error->elem[i].data);
569         for (i = 0; i < error->log_len; i++)
570                 IPW_ERROR("%i\t0x%08x\t%i\n",
571                           error->log[i].time,
572                           error->log[i].data, error->log[i].event);
573 }
574 #endif
575
576 static inline int ipw_is_init(struct ipw_priv *priv)
577 {
578         return (priv->status & STATUS_INIT) ? 1 : 0;
579 }
580
581 static int ipw_get_ordinal(struct ipw_priv *priv, u32 ord, void *val, u32 * len)
582 {
583         u32 addr, field_info, field_len, field_count, total_len;
584
585         IPW_DEBUG_ORD("ordinal = %i\n", ord);
586
587         if (!priv || !val || !len) {
588                 IPW_DEBUG_ORD("Invalid argument\n");
589                 return -EINVAL;
590         }
591
592         /* verify device ordinal tables have been initialized */
593         if (!priv->table0_addr || !priv->table1_addr || !priv->table2_addr) {
594                 IPW_DEBUG_ORD("Access ordinals before initialization\n");
595                 return -EINVAL;
596         }
597
598         switch (IPW_ORD_TABLE_ID_MASK & ord) {
599         case IPW_ORD_TABLE_0_MASK:
600                 /*
601                  * TABLE 0: Direct access to a table of 32 bit values
602                  *
603                  * This is a very simple table with the data directly
604                  * read from the table
605                  */
606
607                 /* remove the table id from the ordinal */
608                 ord &= IPW_ORD_TABLE_VALUE_MASK;
609
610                 /* boundary check */
611                 if (ord > priv->table0_len) {
612                         IPW_DEBUG_ORD("ordinal value (%i) longer then "
613                                       "max (%i)\n", ord, priv->table0_len);
614                         return -EINVAL;
615                 }
616
617                 /* verify we have enough room to store the value */
618                 if (*len < sizeof(u32)) {
619                         IPW_DEBUG_ORD("ordinal buffer length too small, "
620                                       "need %zd\n", sizeof(u32));
621                         return -EINVAL;
622                 }
623
624                 IPW_DEBUG_ORD("Reading TABLE0[%i] from offset 0x%08x\n",
625                               ord, priv->table0_addr + (ord << 2));
626
627                 *len = sizeof(u32);
628                 ord <<= 2;
629                 *((u32 *) val) = ipw_read32(priv, priv->table0_addr + ord);
630                 break;
631
632         case IPW_ORD_TABLE_1_MASK:
633                 /*
634                  * TABLE 1: Indirect access to a table of 32 bit values
635                  *
636                  * This is a fairly large table of u32 values each
637                  * representing starting addr for the data (which is
638                  * also a u32)
639                  */
640
641                 /* remove the table id from the ordinal */
642                 ord &= IPW_ORD_TABLE_VALUE_MASK;
643
644                 /* boundary check */
645                 if (ord > priv->table1_len) {
646                         IPW_DEBUG_ORD("ordinal value too long\n");
647                         return -EINVAL;
648                 }
649
650                 /* verify we have enough room to store the value */
651                 if (*len < sizeof(u32)) {
652                         IPW_DEBUG_ORD("ordinal buffer length too small, "
653                                       "need %zd\n", sizeof(u32));
654                         return -EINVAL;
655                 }
656
657                 *((u32 *) val) =
658                     ipw_read_reg32(priv, (priv->table1_addr + (ord << 2)));
659                 *len = sizeof(u32);
660                 break;
661
662         case IPW_ORD_TABLE_2_MASK:
663                 /*
664                  * TABLE 2: Indirect access to a table of variable sized values
665                  *
666                  * This table consist of six values, each containing
667                  *     - dword containing the starting offset of the data
668                  *     - dword containing the lengh in the first 16bits
669                  *       and the count in the second 16bits
670                  */
671
672                 /* remove the table id from the ordinal */
673                 ord &= IPW_ORD_TABLE_VALUE_MASK;
674
675                 /* boundary check */
676                 if (ord > priv->table2_len) {
677                         IPW_DEBUG_ORD("ordinal value too long\n");
678                         return -EINVAL;
679                 }
680
681                 /* get the address of statistic */
682                 addr = ipw_read_reg32(priv, priv->table2_addr + (ord << 3));
683
684                 /* get the second DW of statistics ;
685                  * two 16-bit words - first is length, second is count */
686                 field_info =
687                     ipw_read_reg32(priv,
688                                    priv->table2_addr + (ord << 3) +
689                                    sizeof(u32));
690
691                 /* get each entry length */
692                 field_len = *((u16 *) & field_info);
693
694                 /* get number of entries */
695                 field_count = *(((u16 *) & field_info) + 1);
696
697                 /* abort if not enought memory */
698                 total_len = field_len * field_count;
699                 if (total_len > *len) {
700                         *len = total_len;
701                         return -EINVAL;
702                 }
703
704                 *len = total_len;
705                 if (!total_len)
706                         return 0;
707
708                 IPW_DEBUG_ORD("addr = 0x%08x, total_len = %i, "
709                               "field_info = 0x%08x\n",
710                               addr, total_len, field_info);
711                 ipw_read_indirect(priv, addr, val, total_len);
712                 break;
713
714         default:
715                 IPW_DEBUG_ORD("Invalid ordinal!\n");
716                 return -EINVAL;
717
718         }
719
720         return 0;
721 }
722
723 static void ipw_init_ordinals(struct ipw_priv *priv)
724 {
725         priv->table0_addr = IPW_ORDINALS_TABLE_LOWER;
726         priv->table0_len = ipw_read32(priv, priv->table0_addr);
727
728         IPW_DEBUG_ORD("table 0 offset at 0x%08x, len = %i\n",
729                       priv->table0_addr, priv->table0_len);
730
731         priv->table1_addr = ipw_read32(priv, IPW_ORDINALS_TABLE_1);
732         priv->table1_len = ipw_read_reg32(priv, priv->table1_addr);
733
734         IPW_DEBUG_ORD("table 1 offset at 0x%08x, len = %i\n",
735                       priv->table1_addr, priv->table1_len);
736
737         priv->table2_addr = ipw_read32(priv, IPW_ORDINALS_TABLE_2);
738         priv->table2_len = ipw_read_reg32(priv, priv->table2_addr);
739         priv->table2_len &= 0x0000ffff; /* use first two bytes */
740
741         IPW_DEBUG_ORD("table 2 offset at 0x%08x, len = %i\n",
742                       priv->table2_addr, priv->table2_len);
743
744 }
745
746 static u32 ipw_register_toggle(u32 reg)
747 {
748         reg &= ~IPW_START_STANDBY;
749         if (reg & IPW_GATE_ODMA)
750                 reg &= ~IPW_GATE_ODMA;
751         if (reg & IPW_GATE_IDMA)
752                 reg &= ~IPW_GATE_IDMA;
753         if (reg & IPW_GATE_ADMA)
754                 reg &= ~IPW_GATE_ADMA;
755         return reg;
756 }
757
758 /*
759  * LED behavior:
760  * - On radio ON, turn on any LEDs that require to be on during start
761  * - On initialization, start unassociated blink
762  * - On association, disable unassociated blink
763  * - On disassociation, start unassociated blink
764  * - On radio OFF, turn off any LEDs started during radio on
765  *
766  */
767 #define LD_TIME_LINK_ON msecs_to_jiffies(300)
768 #define LD_TIME_LINK_OFF msecs_to_jiffies(2700)
769 #define LD_TIME_ACT_ON msecs_to_jiffies(250)
770
771 static void ipw_led_link_on(struct ipw_priv *priv)
772 {
773         unsigned long flags;
774         u32 led;
775
776         /* If configured to not use LEDs, or nic_type is 1,
777          * then we don't toggle a LINK led */
778         if (priv->config & CFG_NO_LED || priv->nic_type == EEPROM_NIC_TYPE_1)
779                 return;
780
781         spin_lock_irqsave(&priv->lock, flags);
782
783         if (!(priv->status & STATUS_RF_KILL_MASK) &&
784             !(priv->status & STATUS_LED_LINK_ON)) {
785                 IPW_DEBUG_LED("Link LED On\n");
786                 led = ipw_read_reg32(priv, IPW_EVENT_REG);
787                 led |= priv->led_association_on;
788
789                 led = ipw_register_toggle(led);
790
791                 IPW_DEBUG_LED("Reg: 0x%08X\n", led);
792                 ipw_write_reg32(priv, IPW_EVENT_REG, led);
793
794                 priv->status |= STATUS_LED_LINK_ON;
795
796                 /* If we aren't associated, schedule turning the LED off */
797                 if (!(priv->status & STATUS_ASSOCIATED))
798                         queue_delayed_work(priv->workqueue,
799                                            &priv->led_link_off,
800                                            LD_TIME_LINK_ON);
801         }
802
803         spin_unlock_irqrestore(&priv->lock, flags);
804 }
805
806 static void ipw_bg_led_link_on(void *data)
807 {
808         struct ipw_priv *priv = data;
809         mutex_lock(&priv->mutex);
810         ipw_led_link_on(data);
811         mutex_unlock(&priv->mutex);
812 }
813
814 static void ipw_led_link_off(struct ipw_priv *priv)
815 {
816         unsigned long flags;
817         u32 led;
818
819         /* If configured not to use LEDs, or nic type is 1,
820          * then we don't goggle the LINK led. */
821         if (priv->config & CFG_NO_LED || priv->nic_type == EEPROM_NIC_TYPE_1)
822                 return;
823
824         spin_lock_irqsave(&priv->lock, flags);
825
826         if (priv->status & STATUS_LED_LINK_ON) {
827                 led = ipw_read_reg32(priv, IPW_EVENT_REG);
828                 led &= priv->led_association_off;
829                 led = ipw_register_toggle(led);
830
831                 IPW_DEBUG_LED("Reg: 0x%08X\n", led);
832                 ipw_write_reg32(priv, IPW_EVENT_REG, led);
833
834                 IPW_DEBUG_LED("Link LED Off\n");
835
836                 priv->status &= ~STATUS_LED_LINK_ON;
837
838                 /* If we aren't associated and the radio is on, schedule
839                  * turning the LED on (blink while unassociated) */
840                 if (!(priv->status & STATUS_RF_KILL_MASK) &&
841                     !(priv->status & STATUS_ASSOCIATED))
842                         queue_delayed_work(priv->workqueue, &priv->led_link_on,
843                                            LD_TIME_LINK_OFF);
844
845         }
846
847         spin_unlock_irqrestore(&priv->lock, flags);
848 }
849
850 static void ipw_bg_led_link_off(void *data)
851 {
852         struct ipw_priv *priv = data;
853         mutex_lock(&priv->mutex);
854         ipw_led_link_off(data);
855         mutex_unlock(&priv->mutex);
856 }
857
858 static void __ipw_led_activity_on(struct ipw_priv *priv)
859 {
860         u32 led;
861
862         if (priv->config & CFG_NO_LED)
863                 return;
864
865         if (priv->status & STATUS_RF_KILL_MASK)
866                 return;
867
868         if (!(priv->status & STATUS_LED_ACT_ON)) {
869                 led = ipw_read_reg32(priv, IPW_EVENT_REG);
870                 led |= priv->led_activity_on;
871
872                 led = ipw_register_toggle(led);
873
874                 IPW_DEBUG_LED("Reg: 0x%08X\n", led);
875                 ipw_write_reg32(priv, IPW_EVENT_REG, led);
876
877                 IPW_DEBUG_LED("Activity LED On\n");
878
879                 priv->status |= STATUS_LED_ACT_ON;
880
881                 cancel_delayed_work(&priv->led_act_off);
882                 queue_delayed_work(priv->workqueue, &priv->led_act_off,
883                                    LD_TIME_ACT_ON);
884         } else {
885                 /* Reschedule LED off for full time period */
886                 cancel_delayed_work(&priv->led_act_off);
887                 queue_delayed_work(priv->workqueue, &priv->led_act_off,
888                                    LD_TIME_ACT_ON);
889         }
890 }
891
892 #if 0
893 void ipw_led_activity_on(struct ipw_priv *priv)
894 {
895         unsigned long flags;
896         spin_lock_irqsave(&priv->lock, flags);
897         __ipw_led_activity_on(priv);
898         spin_unlock_irqrestore(&priv->lock, flags);
899 }
900 #endif  /*  0  */
901
902 static void ipw_led_activity_off(struct ipw_priv *priv)
903 {
904         unsigned long flags;
905         u32 led;
906
907         if (priv->config & CFG_NO_LED)
908                 return;
909
910         spin_lock_irqsave(&priv->lock, flags);
911
912         if (priv->status & STATUS_LED_ACT_ON) {
913                 led = ipw_read_reg32(priv, IPW_EVENT_REG);
914                 led &= priv->led_activity_off;
915
916                 led = ipw_register_toggle(led);
917
918                 IPW_DEBUG_LED("Reg: 0x%08X\n", led);
919                 ipw_write_reg32(priv, IPW_EVENT_REG, led);
920
921                 IPW_DEBUG_LED("Activity LED Off\n");
922
923                 priv->status &= ~STATUS_LED_ACT_ON;
924         }
925
926         spin_unlock_irqrestore(&priv->lock, flags);
927 }
928
929 static void ipw_bg_led_activity_off(void *data)
930 {
931         struct ipw_priv *priv = data;
932         mutex_lock(&priv->mutex);
933         ipw_led_activity_off(data);
934         mutex_unlock(&priv->mutex);
935 }
936
937 static void ipw_led_band_on(struct ipw_priv *priv)
938 {
939         unsigned long flags;
940         u32 led;
941
942         /* Only nic type 1 supports mode LEDs */
943         if (priv->config & CFG_NO_LED ||
944             priv->nic_type != EEPROM_NIC_TYPE_1 || !priv->assoc_network)
945                 return;
946
947         spin_lock_irqsave(&priv->lock, flags);
948
949         led = ipw_read_reg32(priv, IPW_EVENT_REG);
950         if (priv->assoc_network->mode == IEEE_A) {
951                 led |= priv->led_ofdm_on;
952                 led &= priv->led_association_off;
953                 IPW_DEBUG_LED("Mode LED On: 802.11a\n");
954         } else if (priv->assoc_network->mode == IEEE_G) {
955                 led |= priv->led_ofdm_on;
956                 led |= priv->led_association_on;
957                 IPW_DEBUG_LED("Mode LED On: 802.11g\n");
958         } else {
959                 led &= priv->led_ofdm_off;
960                 led |= priv->led_association_on;
961                 IPW_DEBUG_LED("Mode LED On: 802.11b\n");
962         }
963
964         led = ipw_register_toggle(led);
965
966         IPW_DEBUG_LED("Reg: 0x%08X\n", led);
967         ipw_write_reg32(priv, IPW_EVENT_REG, led);
968
969         spin_unlock_irqrestore(&priv->lock, flags);
970 }
971
972 static void ipw_led_band_off(struct ipw_priv *priv)
973 {
974         unsigned long flags;
975         u32 led;
976
977         /* Only nic type 1 supports mode LEDs */
978         if (priv->config & CFG_NO_LED || priv->nic_type != EEPROM_NIC_TYPE_1)
979                 return;
980
981         spin_lock_irqsave(&priv->lock, flags);
982
983         led = ipw_read_reg32(priv, IPW_EVENT_REG);
984         led &= priv->led_ofdm_off;
985         led &= priv->led_association_off;
986
987         led = ipw_register_toggle(led);
988
989         IPW_DEBUG_LED("Reg: 0x%08X\n", led);
990         ipw_write_reg32(priv, IPW_EVENT_REG, led);
991
992         spin_unlock_irqrestore(&priv->lock, flags);
993 }
994
995 static void ipw_led_radio_on(struct ipw_priv *priv)
996 {
997         ipw_led_link_on(priv);
998 }
999
1000 static void ipw_led_radio_off(struct ipw_priv *priv)
1001 {
1002         ipw_led_activity_off(priv);
1003         ipw_led_link_off(priv);
1004 }
1005
1006 static void ipw_led_link_up(struct ipw_priv *priv)
1007 {
1008         /* Set the Link Led on for all nic types */
1009         ipw_led_link_on(priv);
1010 }
1011
1012 static void ipw_led_link_down(struct ipw_priv *priv)
1013 {
1014         ipw_led_activity_off(priv);
1015         ipw_led_link_off(priv);
1016
1017         if (priv->status & STATUS_RF_KILL_MASK)
1018                 ipw_led_radio_off(priv);
1019 }
1020
1021 static void ipw_led_init(struct ipw_priv *priv)
1022 {
1023         priv->nic_type = priv->eeprom[EEPROM_NIC_TYPE];
1024
1025         /* Set the default PINs for the link and activity leds */
1026         priv->led_activity_on = IPW_ACTIVITY_LED;
1027         priv->led_activity_off = ~(IPW_ACTIVITY_LED);
1028
1029         priv->led_association_on = IPW_ASSOCIATED_LED;
1030         priv->led_association_off = ~(IPW_ASSOCIATED_LED);
1031
1032         /* Set the default PINs for the OFDM leds */
1033         priv->led_ofdm_on = IPW_OFDM_LED;
1034         priv->led_ofdm_off = ~(IPW_OFDM_LED);
1035
1036         switch (priv->nic_type) {
1037         case EEPROM_NIC_TYPE_1:
1038                 /* In this NIC type, the LEDs are reversed.... */
1039                 priv->led_activity_on = IPW_ASSOCIATED_LED;
1040                 priv->led_activity_off = ~(IPW_ASSOCIATED_LED);
1041                 priv->led_association_on = IPW_ACTIVITY_LED;
1042                 priv->led_association_off = ~(IPW_ACTIVITY_LED);
1043
1044                 if (!(priv->config & CFG_NO_LED))
1045                         ipw_led_band_on(priv);
1046
1047                 /* And we don't blink link LEDs for this nic, so
1048                  * just return here */
1049                 return;
1050
1051         case EEPROM_NIC_TYPE_3:
1052         case EEPROM_NIC_TYPE_2:
1053         case EEPROM_NIC_TYPE_4:
1054         case EEPROM_NIC_TYPE_0:
1055                 break;
1056
1057         default:
1058                 IPW_DEBUG_INFO("Unknown NIC type from EEPROM: %d\n",
1059                                priv->nic_type);
1060                 priv->nic_type = EEPROM_NIC_TYPE_0;
1061                 break;
1062         }
1063
1064         if (!(priv->config & CFG_NO_LED)) {
1065                 if (priv->status & STATUS_ASSOCIATED)
1066                         ipw_led_link_on(priv);
1067                 else
1068                         ipw_led_link_off(priv);
1069         }
1070 }
1071
1072 static void ipw_led_shutdown(struct ipw_priv *priv)
1073 {
1074         ipw_led_activity_off(priv);
1075         ipw_led_link_off(priv);
1076         ipw_led_band_off(priv);
1077         cancel_delayed_work(&priv->led_link_on);
1078         cancel_delayed_work(&priv->led_link_off);
1079         cancel_delayed_work(&priv->led_act_off);
1080 }
1081
1082 /*
1083  * The following adds a new attribute to the sysfs representation
1084  * of this device driver (i.e. a new file in /sys/bus/pci/drivers/ipw/)
1085  * used for controling the debug level.
1086  *
1087  * See the level definitions in ipw for details.
1088  */
1089 static ssize_t show_debug_level(struct device_driver *d, char *buf)
1090 {
1091         return sprintf(buf, "0x%08X\n", ipw_debug_level);
1092 }
1093
1094 static ssize_t store_debug_level(struct device_driver *d, const char *buf,
1095                                  size_t count)
1096 {
1097         char *p = (char *)buf;
1098         u32 val;
1099
1100         if (p[1] == 'x' || p[1] == 'X' || p[0] == 'x' || p[0] == 'X') {
1101                 p++;
1102                 if (p[0] == 'x' || p[0] == 'X')
1103                         p++;
1104                 val = simple_strtoul(p, &p, 16);
1105         } else
1106                 val = simple_strtoul(p, &p, 10);
1107         if (p == buf)
1108                 printk(KERN_INFO DRV_NAME
1109                        ": %s is not in hex or decimal form.\n", buf);
1110         else
1111                 ipw_debug_level = val;
1112
1113         return strnlen(buf, count);
1114 }
1115
1116 static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO,
1117                    show_debug_level, store_debug_level);
1118
1119 static inline u32 ipw_get_event_log_len(struct ipw_priv *priv)
1120 {
1121         /* length = 1st dword in log */
1122         return ipw_read_reg32(priv, ipw_read32(priv, IPW_EVENT_LOG));
1123 }
1124
1125 static void ipw_capture_event_log(struct ipw_priv *priv,
1126                                   u32 log_len, struct ipw_event *log)
1127 {
1128         u32 base;
1129
1130         if (log_len) {
1131                 base = ipw_read32(priv, IPW_EVENT_LOG);
1132                 ipw_read_indirect(priv, base + sizeof(base) + sizeof(u32),
1133                                   (u8 *) log, sizeof(*log) * log_len);
1134         }
1135 }
1136
1137 static struct ipw_fw_error *ipw_alloc_error_log(struct ipw_priv *priv)
1138 {
1139         struct ipw_fw_error *error;
1140         u32 log_len = ipw_get_event_log_len(priv);
1141         u32 base = ipw_read32(priv, IPW_ERROR_LOG);
1142         u32 elem_len = ipw_read_reg32(priv, base);
1143
1144         error = kmalloc(sizeof(*error) +
1145                         sizeof(*error->elem) * elem_len +
1146                         sizeof(*error->log) * log_len, GFP_ATOMIC);
1147         if (!error) {
1148                 IPW_ERROR("Memory allocation for firmware error log "
1149                           "failed.\n");
1150                 return NULL;
1151         }
1152         error->jiffies = jiffies;
1153         error->status = priv->status;
1154         error->config = priv->config;
1155         error->elem_len = elem_len;
1156         error->log_len = log_len;
1157         error->elem = (struct ipw_error_elem *)error->payload;
1158         error->log = (struct ipw_event *)(error->elem + elem_len);
1159
1160         ipw_capture_event_log(priv, log_len, error->log);
1161
1162         if (elem_len)
1163                 ipw_read_indirect(priv, base + sizeof(base), (u8 *) error->elem,
1164                                   sizeof(*error->elem) * elem_len);
1165
1166         return error;
1167 }
1168
1169 static void ipw_free_error_log(struct ipw_fw_error *error)
1170 {
1171         if (error)
1172                 kfree(error);
1173 }
1174
1175 static ssize_t show_event_log(struct device *d,
1176                               struct device_attribute *attr, char *buf)
1177 {
1178         struct ipw_priv *priv = dev_get_drvdata(d);
1179         u32 log_len = ipw_get_event_log_len(priv);
1180         struct ipw_event log[log_len];
1181         u32 len = 0, i;
1182
1183         ipw_capture_event_log(priv, log_len, log);
1184
1185         len += snprintf(buf + len, PAGE_SIZE - len, "%08X", log_len);
1186         for (i = 0; i < log_len; i++)
1187                 len += snprintf(buf + len, PAGE_SIZE - len,
1188                                 "\n%08X%08X%08X",
1189                                 log[i].time, log[i].event, log[i].data);
1190         len += snprintf(buf + len, PAGE_SIZE - len, "\n");
1191         return len;
1192 }
1193
1194 static DEVICE_ATTR(event_log, S_IRUGO, show_event_log, NULL);
1195
1196 static ssize_t show_error(struct device *d,
1197                           struct device_attribute *attr, char *buf)
1198 {
1199         struct ipw_priv *priv = dev_get_drvdata(d);
1200         u32 len = 0, i;
1201         if (!priv->error)
1202                 return 0;
1203         len += snprintf(buf + len, PAGE_SIZE - len,
1204                         "%08lX%08X%08X%08X",
1205                         priv->error->jiffies,
1206                         priv->error->status,
1207                         priv->error->config, priv->error->elem_len);
1208         for (i = 0; i < priv->error->elem_len; i++)
1209                 len += snprintf(buf + len, PAGE_SIZE - len,
1210                                 "\n%08X%08X%08X%08X%08X%08X%08X",
1211                                 priv->error->elem[i].time,
1212                                 priv->error->elem[i].desc,
1213                                 priv->error->elem[i].blink1,
1214                                 priv->error->elem[i].blink2,
1215                                 priv->error->elem[i].link1,
1216                                 priv->error->elem[i].link2,
1217                                 priv->error->elem[i].data);
1218
1219         len += snprintf(buf + len, PAGE_SIZE - len,
1220                         "\n%08X", priv->error->log_len);
1221         for (i = 0; i < priv->error->log_len; i++)
1222                 len += snprintf(buf + len, PAGE_SIZE - len,
1223                                 "\n%08X%08X%08X",
1224                                 priv->error->log[i].time,
1225                                 priv->error->log[i].event,
1226                                 priv->error->log[i].data);
1227         len += snprintf(buf + len, PAGE_SIZE - len, "\n");
1228         return len;
1229 }
1230
1231 static ssize_t clear_error(struct device *d,
1232                            struct device_attribute *attr,
1233                            const char *buf, size_t count)
1234 {
1235         struct ipw_priv *priv = dev_get_drvdata(d);
1236         if (priv->error) {
1237                 ipw_free_error_log(priv->error);
1238                 priv->error = NULL;
1239         }
1240         return count;
1241 }
1242
1243 static DEVICE_ATTR(error, S_IRUGO | S_IWUSR, show_error, clear_error);
1244
1245 static ssize_t show_cmd_log(struct device *d,
1246                             struct device_attribute *attr, char *buf)
1247 {
1248         struct ipw_priv *priv = dev_get_drvdata(d);
1249         u32 len = 0, i;
1250         if (!priv->cmdlog)
1251                 return 0;
1252         for (i = (priv->cmdlog_pos + 1) % priv->cmdlog_len;
1253              (i != priv->cmdlog_pos) && (PAGE_SIZE - len);
1254              i = (i + 1) % priv->cmdlog_len) {
1255                 len +=
1256                     snprintf(buf + len, PAGE_SIZE - len,
1257                              "\n%08lX%08X%08X%08X\n", priv->cmdlog[i].jiffies,
1258                              priv->cmdlog[i].retcode, priv->cmdlog[i].cmd.cmd,
1259                              priv->cmdlog[i].cmd.len);
1260                 len +=
1261                     snprintk_buf(buf + len, PAGE_SIZE - len,
1262                                  (u8 *) priv->cmdlog[i].cmd.param,
1263                                  priv->cmdlog[i].cmd.len);
1264                 len += snprintf(buf + len, PAGE_SIZE - len, "\n");
1265         }
1266         len += snprintf(buf + len, PAGE_SIZE - len, "\n");
1267         return len;
1268 }
1269
1270 static DEVICE_ATTR(cmd_log, S_IRUGO, show_cmd_log, NULL);
1271
1272 static ssize_t show_scan_age(struct device *d, struct device_attribute *attr,
1273                              char *buf)
1274 {
1275         struct ipw_priv *priv = dev_get_drvdata(d);
1276         return sprintf(buf, "%d\n", priv->ieee->scan_age);
1277 }
1278
1279 static ssize_t store_scan_age(struct device *d, struct device_attribute *attr,
1280                               const char *buf, size_t count)
1281 {
1282         struct ipw_priv *priv = dev_get_drvdata(d);
1283 #ifdef CONFIG_IPW2200_DEBUG
1284         struct net_device *dev = priv->net_dev;
1285 #endif
1286         char buffer[] = "00000000";
1287         unsigned long len =
1288             (sizeof(buffer) - 1) > count ? count : sizeof(buffer) - 1;
1289         unsigned long val;
1290         char *p = buffer;
1291
1292         IPW_DEBUG_INFO("enter\n");
1293
1294         strncpy(buffer, buf, len);
1295         buffer[len] = 0;
1296
1297         if (p[1] == 'x' || p[1] == 'X' || p[0] == 'x' || p[0] == 'X') {
1298                 p++;
1299                 if (p[0] == 'x' || p[0] == 'X')
1300                         p++;
1301                 val = simple_strtoul(p, &p, 16);
1302         } else
1303                 val = simple_strtoul(p, &p, 10);
1304         if (p == buffer) {
1305                 IPW_DEBUG_INFO("%s: user supplied invalid value.\n", dev->name);
1306         } else {
1307                 priv->ieee->scan_age = val;
1308                 IPW_DEBUG_INFO("set scan_age = %u\n", priv->ieee->scan_age);
1309         }
1310
1311         IPW_DEBUG_INFO("exit\n");
1312         return len;
1313 }
1314
1315 static DEVICE_ATTR(scan_age, S_IWUSR | S_IRUGO, show_scan_age, store_scan_age);
1316
1317 static ssize_t show_led(struct device *d, struct device_attribute *attr,
1318                         char *buf)
1319 {
1320         struct ipw_priv *priv = dev_get_drvdata(d);
1321         return sprintf(buf, "%d\n", (priv->config & CFG_NO_LED) ? 0 : 1);
1322 }
1323
1324 static ssize_t store_led(struct device *d, struct device_attribute *attr,
1325                          const char *buf, size_t count)
1326 {
1327         struct ipw_priv *priv = dev_get_drvdata(d);
1328
1329         IPW_DEBUG_INFO("enter\n");
1330
1331         if (count == 0)
1332                 return 0;
1333
1334         if (*buf == 0) {
1335                 IPW_DEBUG_LED("Disabling LED control.\n");
1336                 priv->config |= CFG_NO_LED;
1337                 ipw_led_shutdown(priv);
1338         } else {
1339                 IPW_DEBUG_LED("Enabling LED control.\n");
1340                 priv->config &= ~CFG_NO_LED;
1341                 ipw_led_init(priv);
1342         }
1343
1344         IPW_DEBUG_INFO("exit\n");
1345         return count;
1346 }
1347
1348 static DEVICE_ATTR(led, S_IWUSR | S_IRUGO, show_led, store_led);
1349
1350 static ssize_t show_status(struct device *d,
1351                            struct device_attribute *attr, char *buf)
1352 {
1353         struct ipw_priv *p = d->driver_data;
1354         return sprintf(buf, "0x%08x\n", (int)p->status);
1355 }
1356
1357 static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
1358
1359 static ssize_t show_cfg(struct device *d, struct device_attribute *attr,
1360                         char *buf)
1361 {
1362         struct ipw_priv *p = d->driver_data;
1363         return sprintf(buf, "0x%08x\n", (int)p->config);
1364 }
1365
1366 static DEVICE_ATTR(cfg, S_IRUGO, show_cfg, NULL);
1367
1368 static ssize_t show_nic_type(struct device *d,
1369                              struct device_attribute *attr, char *buf)
1370 {
1371         struct ipw_priv *priv = d->driver_data;
1372         return sprintf(buf, "TYPE: %d\n", priv->nic_type);
1373 }
1374
1375 static DEVICE_ATTR(nic_type, S_IRUGO, show_nic_type, NULL);
1376
1377 static ssize_t show_ucode_version(struct device *d,
1378                                   struct device_attribute *attr, char *buf)
1379 {
1380         u32 len = sizeof(u32), tmp = 0;
1381         struct ipw_priv *p = d->driver_data;
1382
1383         if (ipw_get_ordinal(p, IPW_ORD_STAT_UCODE_VERSION, &tmp, &len))
1384                 return 0;
1385
1386         return sprintf(buf, "0x%08x\n", tmp);
1387 }
1388
1389 static DEVICE_ATTR(ucode_version, S_IWUSR | S_IRUGO, show_ucode_version, NULL);
1390
1391 static ssize_t show_rtc(struct device *d, struct device_attribute *attr,
1392                         char *buf)
1393 {
1394         u32 len = sizeof(u32), tmp = 0;
1395         struct ipw_priv *p = d->driver_data;
1396
1397         if (ipw_get_ordinal(p, IPW_ORD_STAT_RTC, &tmp, &len))
1398                 return 0;
1399
1400         return sprintf(buf, "0x%08x\n", tmp);
1401 }
1402
1403 static DEVICE_ATTR(rtc, S_IWUSR | S_IRUGO, show_rtc, NULL);
1404
1405 /*
1406  * Add a device attribute to view/control the delay between eeprom
1407  * operations.
1408  */
1409 static ssize_t show_eeprom_delay(struct device *d,
1410                                  struct device_attribute *attr, char *buf)
1411 {
1412         int n = ((struct ipw_priv *)d->driver_data)->eeprom_delay;
1413         return sprintf(buf, "%i\n", n);
1414 }
1415 static ssize_t store_eeprom_delay(struct device *d,
1416                                   struct device_attribute *attr,
1417                                   const char *buf, size_t count)
1418 {
1419         struct ipw_priv *p = d->driver_data;
1420         sscanf(buf, "%i", &p->eeprom_delay);
1421         return strnlen(buf, count);
1422 }
1423
1424 static DEVICE_ATTR(eeprom_delay, S_IWUSR | S_IRUGO,
1425                    show_eeprom_delay, store_eeprom_delay);
1426
1427 static ssize_t show_command_event_reg(struct device *d,
1428                                       struct device_attribute *attr, char *buf)
1429 {
1430         u32 reg = 0;
1431         struct ipw_priv *p = d->driver_data;
1432
1433         reg = ipw_read_reg32(p, IPW_INTERNAL_CMD_EVENT);
1434         return sprintf(buf, "0x%08x\n", reg);
1435 }
1436 static ssize_t store_command_event_reg(struct device *d,
1437                                        struct device_attribute *attr,
1438                                        const char *buf, size_t count)
1439 {
1440         u32 reg;
1441         struct ipw_priv *p = d->driver_data;
1442
1443         sscanf(buf, "%x", &reg);
1444         ipw_write_reg32(p, IPW_INTERNAL_CMD_EVENT, reg);
1445         return strnlen(buf, count);
1446 }
1447
1448 static DEVICE_ATTR(command_event_reg, S_IWUSR | S_IRUGO,
1449                    show_command_event_reg, store_command_event_reg);
1450
1451 static ssize_t show_mem_gpio_reg(struct device *d,
1452                                  struct device_attribute *attr, char *buf)
1453 {
1454         u32 reg = 0;
1455         struct ipw_priv *p = d->driver_data;
1456
1457         reg = ipw_read_reg32(p, 0x301100);
1458         return sprintf(buf, "0x%08x\n", reg);
1459 }
1460 static ssize_t store_mem_gpio_reg(struct device *d,
1461                                   struct device_attribute *attr,
1462                                   const char *buf, size_t count)
1463 {
1464         u32 reg;
1465         struct ipw_priv *p = d->driver_data;
1466
1467         sscanf(buf, "%x", &reg);
1468         ipw_write_reg32(p, 0x301100, reg);
1469         return strnlen(buf, count);
1470 }
1471
1472 static DEVICE_ATTR(mem_gpio_reg, S_IWUSR | S_IRUGO,
1473                    show_mem_gpio_reg, store_mem_gpio_reg);
1474
1475 static ssize_t show_indirect_dword(struct device *d,
1476                                    struct device_attribute *attr, char *buf)
1477 {
1478         u32 reg = 0;
1479         struct ipw_priv *priv = d->driver_data;
1480
1481         if (priv->status & STATUS_INDIRECT_DWORD)
1482                 reg = ipw_read_reg32(priv, priv->indirect_dword);
1483         else
1484                 reg = 0;
1485
1486         return sprintf(buf, "0x%08x\n", reg);
1487 }
1488 static ssize_t store_indirect_dword(struct device *d,
1489                                     struct device_attribute *attr,
1490                                     const char *buf, size_t count)
1491 {
1492         struct ipw_priv *priv = d->driver_data;
1493
1494         sscanf(buf, "%x", &priv->indirect_dword);
1495         priv->status |= STATUS_INDIRECT_DWORD;
1496         return strnlen(buf, count);
1497 }
1498
1499 static DEVICE_ATTR(indirect_dword, S_IWUSR | S_IRUGO,
1500                    show_indirect_dword, store_indirect_dword);
1501
1502 static ssize_t show_indirect_byte(struct device *d,
1503                                   struct device_attribute *attr, char *buf)
1504 {
1505         u8 reg = 0;
1506         struct ipw_priv *priv = d->driver_data;
1507
1508         if (priv->status & STATUS_INDIRECT_BYTE)
1509                 reg = ipw_read_reg8(priv, priv->indirect_byte);
1510         else
1511                 reg = 0;
1512
1513         return sprintf(buf, "0x%02x\n", reg);
1514 }
1515 static ssize_t store_indirect_byte(struct device *d,
1516                                    struct device_attribute *attr,
1517                                    const char *buf, size_t count)
1518 {
1519         struct ipw_priv *priv = d->driver_data;
1520
1521         sscanf(buf, "%x", &priv->indirect_byte);
1522         priv->status |= STATUS_INDIRECT_BYTE;
1523         return strnlen(buf, count);
1524 }
1525
1526 static DEVICE_ATTR(indirect_byte, S_IWUSR | S_IRUGO,
1527                    show_indirect_byte, store_indirect_byte);
1528
1529 static ssize_t show_direct_dword(struct device *d,
1530                                  struct device_attribute *attr, char *buf)
1531 {
1532         u32 reg = 0;
1533         struct ipw_priv *priv = d->driver_data;
1534
1535         if (priv->status & STATUS_DIRECT_DWORD)
1536                 reg = ipw_read32(priv, priv->direct_dword);
1537         else
1538                 reg = 0;
1539
1540         return sprintf(buf, "0x%08x\n", reg);
1541 }
1542 static ssize_t store_direct_dword(struct device *d,
1543                                   struct device_attribute *attr,
1544                                   const char *buf, size_t count)
1545 {
1546         struct ipw_priv *priv = d->driver_data;
1547
1548         sscanf(buf, "%x", &priv->direct_dword);
1549         priv->status |= STATUS_DIRECT_DWORD;
1550         return strnlen(buf, count);
1551 }
1552
1553 static DEVICE_ATTR(direct_dword, S_IWUSR | S_IRUGO,
1554                    show_direct_dword, store_direct_dword);
1555
1556 static int rf_kill_active(struct ipw_priv *priv)
1557 {
1558         if (0 == (ipw_read32(priv, 0x30) & 0x10000))
1559                 priv->status |= STATUS_RF_KILL_HW;
1560         else
1561                 priv->status &= ~STATUS_RF_KILL_HW;
1562
1563         return (priv->status & STATUS_RF_KILL_HW) ? 1 : 0;
1564 }
1565
1566 static ssize_t show_rf_kill(struct device *d, struct device_attribute *attr,
1567                             char *buf)
1568 {
1569         /* 0 - RF kill not enabled
1570            1 - SW based RF kill active (sysfs)
1571            2 - HW based RF kill active
1572            3 - Both HW and SW baed RF kill active */
1573         struct ipw_priv *priv = d->driver_data;
1574         int val = ((priv->status & STATUS_RF_KILL_SW) ? 0x1 : 0x0) |
1575             (rf_kill_active(priv) ? 0x2 : 0x0);
1576         return sprintf(buf, "%i\n", val);
1577 }
1578
1579 static int ipw_radio_kill_sw(struct ipw_priv *priv, int disable_radio)
1580 {
1581         if ((disable_radio ? 1 : 0) ==
1582             ((priv->status & STATUS_RF_KILL_SW) ? 1 : 0))
1583                 return 0;
1584
1585         IPW_DEBUG_RF_KILL("Manual SW RF Kill set to: RADIO  %s\n",
1586                           disable_radio ? "OFF" : "ON");
1587
1588         if (disable_radio) {
1589                 priv->status |= STATUS_RF_KILL_SW;
1590
1591                 if (priv->workqueue)
1592                         cancel_delayed_work(&priv->request_scan);
1593                 queue_work(priv->workqueue, &priv->down);
1594         } else {
1595                 priv->status &= ~STATUS_RF_KILL_SW;
1596                 if (rf_kill_active(priv)) {
1597                         IPW_DEBUG_RF_KILL("Can not turn radio back on - "
1598                                           "disabled by HW switch\n");
1599                         /* Make sure the RF_KILL check timer is running */
1600                         cancel_delayed_work(&priv->rf_kill);
1601                         queue_delayed_work(priv->workqueue, &priv->rf_kill,
1602                                            2 * HZ);
1603                 } else
1604                         queue_work(priv->workqueue, &priv->up);
1605         }
1606
1607         return 1;
1608 }
1609
1610 static ssize_t store_rf_kill(struct device *d, struct device_attribute *attr,
1611                              const char *buf, size_t count)
1612 {
1613         struct ipw_priv *priv = d->driver_data;
1614
1615         ipw_radio_kill_sw(priv, buf[0] == '1');
1616
1617         return count;
1618 }
1619
1620 static DEVICE_ATTR(rf_kill, S_IWUSR | S_IRUGO, show_rf_kill, store_rf_kill);
1621
1622 static ssize_t show_speed_scan(struct device *d, struct device_attribute *attr,
1623                                char *buf)
1624 {
1625         struct ipw_priv *priv = (struct ipw_priv *)d->driver_data;
1626         int pos = 0, len = 0;
1627         if (priv->config & CFG_SPEED_SCAN) {
1628                 while (priv->speed_scan[pos] != 0)
1629                         len += sprintf(&buf[len], "%d ",
1630                                        priv->speed_scan[pos++]);
1631                 return len + sprintf(&buf[len], "\n");
1632         }
1633
1634         return sprintf(buf, "0\n");
1635 }
1636
1637 static ssize_t store_speed_scan(struct device *d, struct device_attribute *attr,
1638                                 const char *buf, size_t count)
1639 {
1640         struct ipw_priv *priv = (struct ipw_priv *)d->driver_data;
1641         int channel, pos = 0;
1642         const char *p = buf;
1643
1644         /* list of space separated channels to scan, optionally ending with 0 */
1645         while ((channel = simple_strtol(p, NULL, 0))) {
1646                 if (pos == MAX_SPEED_SCAN - 1) {
1647                         priv->speed_scan[pos] = 0;
1648                         break;
1649                 }
1650
1651                 if (ieee80211_is_valid_channel(priv->ieee, channel))
1652                         priv->speed_scan[pos++] = channel;
1653                 else
1654                         IPW_WARNING("Skipping invalid channel request: %d\n",
1655                                     channel);
1656                 p = strchr(p, ' ');
1657                 if (!p)
1658                         break;
1659                 while (*p == ' ' || *p == '\t')
1660                         p++;
1661         }
1662
1663         if (pos == 0)
1664                 priv->config &= ~CFG_SPEED_SCAN;
1665         else {
1666                 priv->speed_scan_pos = 0;
1667                 priv->config |= CFG_SPEED_SCAN;
1668         }
1669
1670         return count;
1671 }
1672
1673 static DEVICE_ATTR(speed_scan, S_IWUSR | S_IRUGO, show_speed_scan,
1674                    store_speed_scan);
1675
1676 static ssize_t show_net_stats(struct device *d, struct device_attribute *attr,
1677                               char *buf)
1678 {
1679         struct ipw_priv *priv = (struct ipw_priv *)d->driver_data;
1680         return sprintf(buf, "%c\n", (priv->config & CFG_NET_STATS) ? '1' : '0');
1681 }
1682
1683 static ssize_t store_net_stats(struct device *d, struct device_attribute *attr,
1684                                const char *buf, size_t count)
1685 {
1686         struct ipw_priv *priv = (struct ipw_priv *)d->driver_data;
1687         if (buf[0] == '1')
1688                 priv->config |= CFG_NET_STATS;
1689         else
1690                 priv->config &= ~CFG_NET_STATS;
1691
1692         return count;
1693 }
1694
1695 static DEVICE_ATTR(net_stats, S_IWUSR | S_IRUGO,
1696                    show_net_stats, store_net_stats);
1697
1698 static void notify_wx_assoc_event(struct ipw_priv *priv)
1699 {
1700         union iwreq_data wrqu;
1701         wrqu.ap_addr.sa_family = ARPHRD_ETHER;
1702         if (priv->status & STATUS_ASSOCIATED)
1703                 memcpy(wrqu.ap_addr.sa_data, priv->bssid, ETH_ALEN);
1704         else
1705                 memset(wrqu.ap_addr.sa_data, 0, ETH_ALEN);
1706         wireless_send_event(priv->net_dev, SIOCGIWAP, &wrqu, NULL);
1707 }
1708
1709 static void ipw_irq_tasklet(struct ipw_priv *priv)
1710 {
1711         u32 inta, inta_mask, handled = 0;
1712         unsigned long flags;
1713         int rc = 0;
1714
1715         spin_lock_irqsave(&priv->lock, flags);
1716
1717         inta = ipw_read32(priv, IPW_INTA_RW);
1718         inta_mask = ipw_read32(priv, IPW_INTA_MASK_R);
1719         inta &= (IPW_INTA_MASK_ALL & inta_mask);
1720
1721         /* Add any cached INTA values that need to be handled */
1722         inta |= priv->isr_inta;
1723
1724         /* handle all the justifications for the interrupt */
1725         if (inta & IPW_INTA_BIT_RX_TRANSFER) {
1726                 ipw_rx(priv);
1727                 handled |= IPW_INTA_BIT_RX_TRANSFER;
1728         }
1729
1730         if (inta & IPW_INTA_BIT_TX_CMD_QUEUE) {
1731                 IPW_DEBUG_HC("Command completed.\n");
1732                 rc = ipw_queue_tx_reclaim(priv, &priv->txq_cmd, -1);
1733                 priv->status &= ~STATUS_HCMD_ACTIVE;
1734                 wake_up_interruptible(&priv->wait_command_queue);
1735                 handled |= IPW_INTA_BIT_TX_CMD_QUEUE;
1736         }
1737
1738         if (inta & IPW_INTA_BIT_TX_QUEUE_1) {
1739                 IPW_DEBUG_TX("TX_QUEUE_1\n");
1740                 rc = ipw_queue_tx_reclaim(priv, &priv->txq[0], 0);
1741                 handled |= IPW_INTA_BIT_TX_QUEUE_1;
1742         }
1743
1744         if (inta & IPW_INTA_BIT_TX_QUEUE_2) {
1745                 IPW_DEBUG_TX("TX_QUEUE_2\n");
1746                 rc = ipw_queue_tx_reclaim(priv, &priv->txq[1], 1);
1747                 handled |= IPW_INTA_BIT_TX_QUEUE_2;
1748         }
1749
1750         if (inta & IPW_INTA_BIT_TX_QUEUE_3) {
1751                 IPW_DEBUG_TX("TX_QUEUE_3\n");
1752                 rc = ipw_queue_tx_reclaim(priv, &priv->txq[2], 2);
1753                 handled |= IPW_INTA_BIT_TX_QUEUE_3;
1754         }
1755
1756         if (inta & IPW_INTA_BIT_TX_QUEUE_4) {
1757                 IPW_DEBUG_TX("TX_QUEUE_4\n");
1758                 rc = ipw_queue_tx_reclaim(priv, &priv->txq[3], 3);
1759                 handled |= IPW_INTA_BIT_TX_QUEUE_4;
1760         }
1761
1762         if (inta & IPW_INTA_BIT_STATUS_CHANGE) {
1763                 IPW_WARNING("STATUS_CHANGE\n");
1764                 handled |= IPW_INTA_BIT_STATUS_CHANGE;
1765         }
1766
1767         if (inta & IPW_INTA_BIT_BEACON_PERIOD_EXPIRED) {
1768                 IPW_WARNING("TX_PERIOD_EXPIRED\n");
1769                 handled |= IPW_INTA_BIT_BEACON_PERIOD_EXPIRED;
1770         }
1771
1772         if (inta & IPW_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE) {
1773                 IPW_WARNING("HOST_CMD_DONE\n");
1774                 handled |= IPW_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE;
1775         }
1776
1777         if (inta & IPW_INTA_BIT_FW_INITIALIZATION_DONE) {
1778                 IPW_WARNING("FW_INITIALIZATION_DONE\n");
1779                 handled |= IPW_INTA_BIT_FW_INITIALIZATION_DONE;
1780         }
1781
1782         if (inta & IPW_INTA_BIT_FW_CARD_DISABLE_PHY_OFF_DONE) {
1783                 IPW_WARNING("PHY_OFF_DONE\n");
1784                 handled |= IPW_INTA_BIT_FW_CARD_DISABLE_PHY_OFF_DONE;
1785         }
1786
1787         if (inta & IPW_INTA_BIT_RF_KILL_DONE) {
1788                 IPW_DEBUG_RF_KILL("RF_KILL_DONE\n");
1789                 priv->status |= STATUS_RF_KILL_HW;
1790                 wake_up_interruptible(&priv->wait_command_queue);
1791                 priv->status &= ~(STATUS_ASSOCIATED | STATUS_ASSOCIATING);
1792                 cancel_delayed_work(&priv->request_scan);
1793                 schedule_work(&priv->link_down);
1794                 queue_delayed_work(priv->workqueue, &priv->rf_kill, 2 * HZ);
1795                 handled |= IPW_INTA_BIT_RF_KILL_DONE;
1796         }
1797
1798         if (inta & IPW_INTA_BIT_FATAL_ERROR) {
1799                 IPW_WARNING("Firmware error detected.  Restarting.\n");
1800                 if (priv->error) {
1801                         IPW_DEBUG_FW("Sysfs 'error' log already exists.\n");
1802 #ifdef CONFIG_IPW2200_DEBUG
1803                         if (ipw_debug_level & IPW_DL_FW_ERRORS) {
1804                                 struct ipw_fw_error *error =
1805                                     ipw_alloc_error_log(priv);
1806                                 ipw_dump_error_log(priv, error);
1807                                 if (error)
1808                                         ipw_free_error_log(error);
1809                         }
1810 #endif
1811                 } else {
1812                         priv->error = ipw_alloc_error_log(priv);
1813                         if (priv->error)
1814                                 IPW_DEBUG_FW("Sysfs 'error' log captured.\n");
1815                         else
1816                                 IPW_DEBUG_FW("Error allocating sysfs 'error' "
1817                                              "log.\n");
1818 #ifdef CONFIG_IPW2200_DEBUG
1819                         if (ipw_debug_level & IPW_DL_FW_ERRORS)
1820                                 ipw_dump_error_log(priv, priv->error);
1821 #endif
1822                 }
1823
1824                 /* XXX: If hardware encryption is for WPA/WPA2,
1825                  * we have to notify the supplicant. */
1826                 if (priv->ieee->sec.encrypt) {
1827                         priv->status &= ~STATUS_ASSOCIATED;
1828                         notify_wx_assoc_event(priv);
1829                 }
1830
1831                 /* Keep the restart process from trying to send host
1832                  * commands by clearing the INIT status bit */
1833                 priv->status &= ~STATUS_INIT;
1834
1835                 /* Cancel currently queued command. */
1836                 priv->status &= ~STATUS_HCMD_ACTIVE;
1837                 wake_up_interruptible(&priv->wait_command_queue);
1838
1839                 queue_work(priv->workqueue, &priv->adapter_restart);
1840                 handled |= IPW_INTA_BIT_FATAL_ERROR;
1841         }
1842
1843         if (inta & IPW_INTA_BIT_PARITY_ERROR) {
1844                 IPW_ERROR("Parity error\n");
1845                 handled |= IPW_INTA_BIT_PARITY_ERROR;
1846         }
1847
1848         if (handled != inta) {
1849                 IPW_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
1850         }
1851
1852         /* enable all interrupts */
1853         ipw_enable_interrupts(priv);
1854
1855         spin_unlock_irqrestore(&priv->lock, flags);
1856 }
1857
1858 #define IPW_CMD(x) case IPW_CMD_ ## x : return #x
1859 static char *get_cmd_string(u8 cmd)
1860 {
1861         switch (cmd) {
1862                 IPW_CMD(HOST_COMPLETE);
1863                 IPW_CMD(POWER_DOWN);
1864                 IPW_CMD(SYSTEM_CONFIG);
1865                 IPW_CMD(MULTICAST_ADDRESS);
1866                 IPW_CMD(SSID);
1867                 IPW_CMD(ADAPTER_ADDRESS);
1868                 IPW_CMD(PORT_TYPE);
1869                 IPW_CMD(RTS_THRESHOLD);
1870                 IPW_CMD(FRAG_THRESHOLD);
1871                 IPW_CMD(POWER_MODE);
1872                 IPW_CMD(WEP_KEY);
1873                 IPW_CMD(TGI_TX_KEY);
1874                 IPW_CMD(SCAN_REQUEST);
1875                 IPW_CMD(SCAN_REQUEST_EXT);
1876                 IPW_CMD(ASSOCIATE);
1877                 IPW_CMD(SUPPORTED_RATES);
1878                 IPW_CMD(SCAN_ABORT);
1879                 IPW_CMD(TX_FLUSH);
1880                 IPW_CMD(QOS_PARAMETERS);
1881                 IPW_CMD(DINO_CONFIG);
1882                 IPW_CMD(RSN_CAPABILITIES);
1883                 IPW_CMD(RX_KEY);
1884                 IPW_CMD(CARD_DISABLE);
1885                 IPW_CMD(SEED_NUMBER);
1886                 IPW_CMD(TX_POWER);
1887                 IPW_CMD(COUNTRY_INFO);
1888                 IPW_CMD(AIRONET_INFO);
1889                 IPW_CMD(AP_TX_POWER);
1890                 IPW_CMD(CCKM_INFO);
1891                 IPW_CMD(CCX_VER_INFO);
1892                 IPW_CMD(SET_CALIBRATION);
1893                 IPW_CMD(SENSITIVITY_CALIB);
1894                 IPW_CMD(RETRY_LIMIT);
1895                 IPW_CMD(IPW_PRE_POWER_DOWN);
1896                 IPW_CMD(VAP_BEACON_TEMPLATE);
1897                 IPW_CMD(VAP_DTIM_PERIOD);
1898                 IPW_CMD(EXT_SUPPORTED_RATES);
1899                 IPW_CMD(VAP_LOCAL_TX_PWR_CONSTRAINT);
1900                 IPW_CMD(VAP_QUIET_INTERVALS);
1901                 IPW_CMD(VAP_CHANNEL_SWITCH);
1902                 IPW_CMD(VAP_MANDATORY_CHANNELS);
1903                 IPW_CMD(VAP_CELL_PWR_LIMIT);
1904                 IPW_CMD(VAP_CF_PARAM_SET);
1905                 IPW_CMD(VAP_SET_BEACONING_STATE);
1906                 IPW_CMD(MEASUREMENT);
1907                 IPW_CMD(POWER_CAPABILITY);
1908                 IPW_CMD(SUPPORTED_CHANNELS);
1909                 IPW_CMD(TPC_REPORT);
1910                 IPW_CMD(WME_INFO);
1911                 IPW_CMD(PRODUCTION_COMMAND);
1912         default:
1913                 return "UNKNOWN";
1914         }
1915 }
1916
1917 #define HOST_COMPLETE_TIMEOUT HZ
1918
1919 static int __ipw_send_cmd(struct ipw_priv *priv, struct host_cmd *cmd)
1920 {
1921         int rc = 0;
1922         unsigned long flags;
1923
1924         spin_lock_irqsave(&priv->lock, flags);
1925         if (priv->status & STATUS_HCMD_ACTIVE) {
1926                 IPW_ERROR("Failed to send %s: Already sending a command.\n",
1927                           get_cmd_string(cmd->cmd));
1928                 spin_unlock_irqrestore(&priv->lock, flags);
1929                 return -EAGAIN;
1930         }
1931
1932         priv->status |= STATUS_HCMD_ACTIVE;
1933
1934         if (priv->cmdlog) {
1935                 priv->cmdlog[priv->cmdlog_pos].jiffies = jiffies;
1936                 priv->cmdlog[priv->cmdlog_pos].cmd.cmd = cmd->cmd;
1937                 priv->cmdlog[priv->cmdlog_pos].cmd.len = cmd->len;
1938                 memcpy(priv->cmdlog[priv->cmdlog_pos].cmd.param, cmd->param,
1939                        cmd->len);
1940                 priv->cmdlog[priv->cmdlog_pos].retcode = -1;
1941         }
1942
1943         IPW_DEBUG_HC("%s command (#%d) %d bytes: 0x%08X\n",
1944                      get_cmd_string(cmd->cmd), cmd->cmd, cmd->len,
1945                      priv->status);
1946
1947 #ifndef DEBUG_CMD_WEP_KEY
1948         if (cmd->cmd == IPW_CMD_WEP_KEY)
1949                 IPW_DEBUG_HC("WEP_KEY command masked out for secure.\n");
1950         else
1951 #endif
1952                 printk_buf(IPW_DL_HOST_COMMAND, (u8 *) cmd->param, cmd->len);
1953
1954         rc = ipw_queue_tx_hcmd(priv, cmd->cmd, cmd->param, cmd->len, 0);
1955         if (rc) {
1956                 priv->status &= ~STATUS_HCMD_ACTIVE;
1957                 IPW_ERROR("Failed to send %s: Reason %d\n",
1958                           get_cmd_string(cmd->cmd), rc);
1959                 spin_unlock_irqrestore(&priv->lock, flags);
1960                 goto exit;
1961         }
1962         spin_unlock_irqrestore(&priv->lock, flags);
1963
1964         rc = wait_event_interruptible_timeout(priv->wait_command_queue,
1965                                               !(priv->
1966                                                 status & STATUS_HCMD_ACTIVE),
1967                                               HOST_COMPLETE_TIMEOUT);
1968         if (rc == 0) {
1969                 spin_lock_irqsave(&priv->lock, flags);
1970                 if (priv->status & STATUS_HCMD_ACTIVE) {
1971                         IPW_ERROR("Failed to send %s: Command timed out.\n",
1972                                   get_cmd_string(cmd->cmd));
1973                         priv->status &= ~STATUS_HCMD_ACTIVE;
1974                         spin_unlock_irqrestore(&priv->lock, flags);
1975                         rc = -EIO;
1976                         goto exit;
1977                 }
1978                 spin_unlock_irqrestore(&priv->lock, flags);
1979         } else
1980                 rc = 0;
1981
1982         if (priv->status & STATUS_RF_KILL_HW) {
1983                 IPW_ERROR("Failed to send %s: Aborted due to RF kill switch.\n",
1984                           get_cmd_string(cmd->cmd));
1985                 rc = -EIO;
1986                 goto exit;
1987         }
1988
1989       exit:
1990         if (priv->cmdlog) {
1991                 priv->cmdlog[priv->cmdlog_pos++].retcode = rc;
1992                 priv->cmdlog_pos %= priv->cmdlog_len;
1993         }
1994         return rc;
1995 }
1996
1997 static int ipw_send_cmd_simple(struct ipw_priv *priv, u8 command)
1998 {
1999         struct host_cmd cmd = {
2000                 .cmd = command,
2001         };
2002
2003         return __ipw_send_cmd(priv, &cmd);
2004 }
2005
2006 static int ipw_send_cmd_pdu(struct ipw_priv *priv, u8 command, u8 len,
2007                             void *data)
2008 {
2009         struct host_cmd cmd = {
2010                 .cmd = command,
2011                 .len = len,
2012                 .param = data,
2013         };
2014
2015         return __ipw_send_cmd(priv, &cmd);
2016 }
2017
2018 static int ipw_send_host_complete(struct ipw_priv *priv)
2019 {
2020         if (!priv) {
2021                 IPW_ERROR("Invalid args\n");
2022                 return -1;
2023         }
2024
2025         return ipw_send_cmd_simple(priv, IPW_CMD_HOST_COMPLETE);
2026 }
2027
2028 static int ipw_send_system_config(struct ipw_priv *priv,
2029                                   struct ipw_sys_config *config)
2030 {
2031         if (!priv || !config) {
2032                 IPW_ERROR("Invalid args\n");
2033                 return -1;
2034         }
2035
2036         return ipw_send_cmd_pdu(priv, IPW_CMD_SYSTEM_CONFIG, sizeof(*config),
2037                                 config);
2038 }
2039
2040 static int ipw_send_ssid(struct ipw_priv *priv, u8 * ssid, int len)
2041 {
2042         if (!priv || !ssid) {
2043                 IPW_ERROR("Invalid args\n");
2044                 return -1;
2045         }
2046
2047         return ipw_send_cmd_pdu(priv, IPW_CMD_SSID, min(len, IW_ESSID_MAX_SIZE),
2048                                 ssid);
2049 }
2050
2051 static int ipw_send_adapter_address(struct ipw_priv *priv, u8 * mac)
2052 {
2053         if (!priv || !mac) {
2054                 IPW_ERROR("Invalid args\n");
2055                 return -1;
2056         }
2057
2058         IPW_DEBUG_INFO("%s: Setting MAC to " MAC_FMT "\n",
2059                        priv->net_dev->name, MAC_ARG(mac));
2060
2061         return ipw_send_cmd_pdu(priv, IPW_CMD_ADAPTER_ADDRESS, ETH_ALEN, mac);
2062 }
2063
2064 /*
2065  * NOTE: This must be executed from our workqueue as it results in udelay
2066  * being called which may corrupt the keyboard if executed on default
2067  * workqueue
2068  */
2069 static void ipw_adapter_restart(void *adapter)
2070 {
2071         struct ipw_priv *priv = adapter;
2072
2073         if (priv->status & STATUS_RF_KILL_MASK)
2074                 return;
2075
2076         ipw_down(priv);
2077
2078         if (priv->assoc_network &&
2079             (priv->assoc_network->capability & WLAN_CAPABILITY_IBSS))
2080                 ipw_remove_current_network(priv);
2081
2082         if (ipw_up(priv)) {
2083                 IPW_ERROR("Failed to up device\n");
2084                 return;
2085         }
2086 }
2087
2088 static void ipw_bg_adapter_restart(void *data)
2089 {
2090         struct ipw_priv *priv = data;
2091         mutex_lock(&priv->mutex);
2092         ipw_adapter_restart(data);
2093         mutex_unlock(&priv->mutex);
2094 }
2095
2096 #define IPW_SCAN_CHECK_WATCHDOG (5 * HZ)
2097
2098 static void ipw_scan_check(void *data)
2099 {
2100         struct ipw_priv *priv = data;
2101         if (priv->status & (STATUS_SCANNING | STATUS_SCAN_ABORTING)) {
2102                 IPW_DEBUG_SCAN("Scan completion watchdog resetting "
2103                                "adapter after (%dms).\n",
2104                                jiffies_to_msecs(IPW_SCAN_CHECK_WATCHDOG));
2105                 queue_work(priv->workqueue, &priv->adapter_restart);
2106         }
2107 }
2108
2109 static void ipw_bg_scan_check(void *data)
2110 {
2111         struct ipw_priv *priv = data;
2112         mutex_lock(&priv->mutex);
2113         ipw_scan_check(data);
2114         mutex_unlock(&priv->mutex);
2115 }
2116
2117 static int ipw_send_scan_request_ext(struct ipw_priv *priv,
2118                                      struct ipw_scan_request_ext *request)
2119 {
2120         return ipw_send_cmd_pdu(priv, IPW_CMD_SCAN_REQUEST_EXT,
2121                                 sizeof(*request), request);
2122 }
2123
2124 static int ipw_send_scan_abort(struct ipw_priv *priv)
2125 {
2126         if (!priv) {
2127                 IPW_ERROR("Invalid args\n");
2128                 return -1;
2129         }
2130
2131         return ipw_send_cmd_simple(priv, IPW_CMD_SCAN_ABORT);
2132 }
2133
2134 static int ipw_set_sensitivity(struct ipw_priv *priv, u16 sens)
2135 {
2136         struct ipw_sensitivity_calib calib = {
2137                 .beacon_rssi_raw = sens,
2138         };
2139
2140         return ipw_send_cmd_pdu(priv, IPW_CMD_SENSITIVITY_CALIB, sizeof(calib),
2141                                 &calib);
2142 }
2143
2144 static int ipw_send_associate(struct ipw_priv *priv,
2145                               struct ipw_associate *associate)
2146 {
2147         struct ipw_associate tmp_associate;
2148
2149         if (!priv || !associate) {
2150                 IPW_ERROR("Invalid args\n");
2151                 return -1;
2152         }
2153
2154         memcpy(&tmp_associate, associate, sizeof(*associate));
2155         tmp_associate.policy_support =
2156             cpu_to_le16(tmp_associate.policy_support);
2157         tmp_associate.assoc_tsf_msw = cpu_to_le32(tmp_associate.assoc_tsf_msw);
2158         tmp_associate.assoc_tsf_lsw = cpu_to_le32(tmp_associate.assoc_tsf_lsw);
2159         tmp_associate.capability = cpu_to_le16(tmp_associate.capability);
2160         tmp_associate.listen_interval =
2161             cpu_to_le16(tmp_associate.listen_interval);
2162         tmp_associate.beacon_interval =
2163             cpu_to_le16(tmp_associate.beacon_interval);
2164         tmp_associate.atim_window = cpu_to_le16(tmp_associate.atim_window);
2165
2166         return ipw_send_cmd_pdu(priv, IPW_CMD_ASSOCIATE, sizeof(tmp_associate),
2167                                 &tmp_associate);
2168 }
2169
2170 static int ipw_send_supported_rates(struct ipw_priv *priv,
2171                                     struct ipw_supported_rates *rates)
2172 {
2173         if (!priv || !rates) {
2174                 IPW_ERROR("Invalid args\n");
2175                 return -1;
2176         }
2177
2178         return ipw_send_cmd_pdu(priv, IPW_CMD_SUPPORTED_RATES, sizeof(*rates),
2179                                 rates);
2180 }
2181
2182 static int ipw_set_random_seed(struct ipw_priv *priv)
2183 {
2184         u32 val;
2185
2186         if (!priv) {
2187                 IPW_ERROR("Invalid args\n");
2188                 return -1;
2189         }
2190
2191         get_random_bytes(&val, sizeof(val));
2192
2193         return ipw_send_cmd_pdu(priv, IPW_CMD_SEED_NUMBER, sizeof(val), &val);
2194 }
2195
2196 static int ipw_send_card_disable(struct ipw_priv *priv, u32 phy_off)
2197 {
2198         if (!priv) {
2199                 IPW_ERROR("Invalid args\n");
2200                 return -1;
2201         }
2202
2203         return ipw_send_cmd_pdu(priv, IPW_CMD_CARD_DISABLE, sizeof(phy_off),
2204                                 &phy_off);
2205 }
2206
2207 static int ipw_send_tx_power(struct ipw_priv *priv, struct ipw_tx_power *power)
2208 {
2209         if (!priv || !power) {
2210                 IPW_ERROR("Invalid args\n");
2211                 return -1;
2212         }
2213
2214         return ipw_send_cmd_pdu(priv, IPW_CMD_TX_POWER, sizeof(*power), power);
2215 }
2216
2217 static int ipw_set_tx_power(struct ipw_priv *priv)
2218 {
2219         const struct ieee80211_geo *geo = ieee80211_get_geo(priv->ieee);
2220         struct ipw_tx_power tx_power;
2221         s8 max_power;
2222         int i;
2223
2224         memset(&tx_power, 0, sizeof(tx_power));
2225
2226         /* configure device for 'G' band */
2227         tx_power.ieee_mode = IPW_G_MODE;
2228         tx_power.num_channels = geo->bg_channels;
2229         for (i = 0; i < geo->bg_channels; i++) {
2230                 max_power = geo->bg[i].max_power;
2231                 tx_power.channels_tx_power[i].channel_number =
2232                     geo->bg[i].channel;
2233                 tx_power.channels_tx_power[i].tx_power = max_power ?
2234                     min(max_power, priv->tx_power) : priv->tx_power;
2235         }
2236         if (ipw_send_tx_power(priv, &tx_power))
2237                 return -EIO;
2238
2239         /* configure device to also handle 'B' band */
2240         tx_power.ieee_mode = IPW_B_MODE;
2241         if (ipw_send_tx_power(priv, &tx_power))
2242                 return -EIO;
2243
2244         /* configure device to also handle 'A' band */
2245         if (priv->ieee->abg_true) {
2246                 tx_power.ieee_mode = IPW_A_MODE;
2247                 tx_power.num_channels = geo->a_channels;
2248                 for (i = 0; i < tx_power.num_channels; i++) {
2249                         max_power = geo->a[i].max_power;
2250                         tx_power.channels_tx_power[i].channel_number =
2251                             geo->a[i].channel;
2252                         tx_power.channels_tx_power[i].tx_power = max_power ?
2253                             min(max_power, priv->tx_power) : priv->tx_power;
2254                 }
2255                 if (ipw_send_tx_power(priv, &tx_power))
2256                         return -EIO;
2257         }
2258         return 0;
2259 }
2260
2261 static int ipw_send_rts_threshold(struct ipw_priv *priv, u16 rts)
2262 {
2263         struct ipw_rts_threshold rts_threshold = {
2264                 .rts_threshold = rts,
2265         };
2266
2267         if (!priv) {
2268                 IPW_ERROR("Invalid args\n");
2269                 return -1;
2270         }
2271
2272         return ipw_send_cmd_pdu(priv, IPW_CMD_RTS_THRESHOLD,
2273                                 sizeof(rts_threshold), &rts_threshold);
2274 }
2275
2276 static int ipw_send_frag_threshold(struct ipw_priv *priv, u16 frag)
2277 {
2278         struct ipw_frag_threshold frag_threshold = {
2279                 .frag_threshold = frag,
2280         };
2281
2282         if (!priv) {
2283                 IPW_ERROR("Invalid args\n");
2284                 return -1;
2285         }
2286
2287         return ipw_send_cmd_pdu(priv, IPW_CMD_FRAG_THRESHOLD,
2288                                 sizeof(frag_threshold), &frag_threshold);
2289 }
2290
2291 static int ipw_send_power_mode(struct ipw_priv *priv, u32 mode)
2292 {
2293         u32 param;
2294
2295         if (!priv) {
2296                 IPW_ERROR("Invalid args\n");
2297                 return -1;
2298         }
2299
2300         /* If on battery, set to 3, if AC set to CAM, else user
2301          * level */
2302         switch (mode) {
2303         case IPW_POWER_BATTERY:
2304                 param = IPW_POWER_INDEX_3;
2305                 break;
2306         case IPW_POWER_AC:
2307                 param = IPW_POWER_MODE_CAM;
2308                 break;
2309         default:
2310                 param = mode;
2311                 break;
2312         }
2313
2314         return ipw_send_cmd_pdu(priv, IPW_CMD_POWER_MODE, sizeof(param),
2315                                 &param);
2316 }
2317
2318 static int ipw_send_retry_limit(struct ipw_priv *priv, u8 slimit, u8 llimit)
2319 {
2320         struct ipw_retry_limit retry_limit = {
2321                 .short_retry_limit = slimit,
2322                 .long_retry_limit = llimit
2323         };
2324
2325         if (!priv) {
2326                 IPW_ERROR("Invalid args\n");
2327                 return -1;
2328         }
2329
2330         return ipw_send_cmd_pdu(priv, IPW_CMD_RETRY_LIMIT, sizeof(retry_limit),
2331                                 &retry_limit);
2332 }
2333
2334 /*
2335  * The IPW device contains a Microwire compatible EEPROM that stores
2336  * various data like the MAC address.  Usually the firmware has exclusive
2337  * access to the eeprom, but during device initialization (before the
2338  * device driver has sent the HostComplete command to the firmware) the
2339  * device driver has read access to the EEPROM by way of indirect addressing
2340  * through a couple of memory mapped registers.
2341  *
2342  * The following is a simplified implementation for pulling data out of the
2343  * the eeprom, along with some helper functions to find information in
2344  * the per device private data's copy of the eeprom.
2345  *
2346  * NOTE: To better understand how these functions work (i.e what is a chip
2347  *       select and why do have to keep driving the eeprom clock?), read
2348  *       just about any data sheet for a Microwire compatible EEPROM.
2349  */
2350
2351 /* write a 32 bit value into the indirect accessor register */
2352 static inline void eeprom_write_reg(struct ipw_priv *p, u32 data)
2353 {
2354         ipw_write_reg32(p, FW_MEM_REG_EEPROM_ACCESS, data);
2355
2356         /* the eeprom requires some time to complete the operation */
2357         udelay(p->eeprom_delay);
2358
2359         return;
2360 }
2361
2362 /* perform a chip select operation */
2363 static void eeprom_cs(struct ipw_priv *priv)
2364 {
2365         eeprom_write_reg(priv, 0);
2366         eeprom_write_reg(priv, EEPROM_BIT_CS);
2367         eeprom_write_reg(priv, EEPROM_BIT_CS | EEPROM_BIT_SK);
2368         eeprom_write_reg(priv, EEPROM_BIT_CS);
2369 }
2370
2371 /* perform a chip select operation */
2372 static void eeprom_disable_cs(struct ipw_priv *priv)
2373 {
2374         eeprom_write_reg(priv, EEPROM_BIT_CS);
2375         eeprom_write_reg(priv, 0);
2376         eeprom_write_reg(priv, EEPROM_BIT_SK);
2377 }
2378
2379 /* push a single bit down to the eeprom */
2380 static inline void eeprom_write_bit(struct ipw_priv *p, u8 bit)
2381 {
2382         int d = (bit ? EEPROM_BIT_DI : 0);
2383         eeprom_write_reg(p, EEPROM_BIT_CS | d);
2384         eeprom_write_reg(p, EEPROM_BIT_CS | d | EEPROM_BIT_SK);
2385 }
2386
2387 /* push an opcode followed by an address down to the eeprom */
2388 static void eeprom_op(struct ipw_priv *priv, u8 op, u8 addr)
2389 {
2390         int i;
2391
2392         eeprom_cs(priv);
2393         eeprom_write_bit(priv, 1);
2394         eeprom_write_bit(priv, op & 2);
2395         eeprom_write_bit(priv, op & 1);
2396         for (i = 7; i >= 0; i--) {
2397                 eeprom_write_bit(priv, addr & (1 << i));
2398         }
2399 }
2400
2401 /* pull 16 bits off the eeprom, one bit at a time */
2402 static u16 eeprom_read_u16(struct ipw_priv *priv, u8 addr)
2403 {
2404         int i;
2405         u16 r = 0;
2406
2407         /* Send READ Opcode */
2408         eeprom_op(priv, EEPROM_CMD_READ, addr);
2409
2410         /* Send dummy bit */
2411         eeprom_write_reg(priv, EEPROM_BIT_CS);
2412
2413         /* Read the byte off the eeprom one bit at a time */
2414         for (i = 0; i < 16; i++) {
2415                 u32 data = 0;
2416                 eeprom_write_reg(priv, EEPROM_BIT_CS | EEPROM_BIT_SK);
2417                 eeprom_write_reg(priv, EEPROM_BIT_CS);
2418                 data = ipw_read_reg32(priv, FW_MEM_REG_EEPROM_ACCESS);
2419                 r = (r << 1) | ((data & EEPROM_BIT_DO) ? 1 : 0);
2420         }
2421
2422         /* Send another dummy bit */
2423         eeprom_write_reg(priv, 0);
2424         eeprom_disable_cs(priv);
2425
2426         return r;
2427 }
2428
2429 /* helper function for pulling the mac address out of the private */
2430 /* data's copy of the eeprom data                                 */
2431 static void eeprom_parse_mac(struct ipw_priv *priv, u8 * mac)
2432 {
2433         memcpy(mac, &priv->eeprom[EEPROM_MAC_ADDRESS], 6);
2434 }
2435
2436 /*
2437  * Either the device driver (i.e. the host) or the firmware can
2438  * load eeprom data into the designated region in SRAM.  If neither
2439  * happens then the FW will shutdown with a fatal error.
2440  *
2441  * In order to signal the FW to load the EEPROM, the EEPROM_LOAD_DISABLE
2442  * bit needs region of shared SRAM needs to be non-zero.
2443  */
2444 static void ipw_eeprom_init_sram(struct ipw_priv *priv)
2445 {
2446         int i;
2447         u16 *eeprom = (u16 *) priv->eeprom;
2448
2449         IPW_DEBUG_TRACE(">>\n");
2450
2451         /* read entire contents of eeprom into private buffer */
2452         for (i = 0; i < 128; i++)
2453                 eeprom[i] = le16_to_cpu(eeprom_read_u16(priv, (u8) i));
2454
2455         /*
2456            If the data looks correct, then copy it to our private
2457            copy.  Otherwise let the firmware know to perform the operation
2458            on its own.
2459          */
2460         if (priv->eeprom[EEPROM_VERSION] != 0) {
2461                 IPW_DEBUG_INFO("Writing EEPROM data into SRAM\n");
2462
2463                 /* write the eeprom data to sram */
2464                 for (i = 0; i < IPW_EEPROM_IMAGE_SIZE; i++)
2465                         ipw_write8(priv, IPW_EEPROM_DATA + i, priv->eeprom[i]);
2466
2467                 /* Do not load eeprom data on fatal error or suspend */
2468                 ipw_write32(priv, IPW_EEPROM_LOAD_DISABLE, 0);
2469         } else {
2470                 IPW_DEBUG_INFO("Enabling FW initializationg of SRAM\n");
2471
2472                 /* Load eeprom data on fatal error or suspend */
2473                 ipw_write32(priv, IPW_EEPROM_LOAD_DISABLE, 1);
2474         }
2475
2476         IPW_DEBUG_TRACE("<<\n");
2477 }
2478
2479 static void ipw_zero_memory(struct ipw_priv *priv, u32 start, u32 count)
2480 {
2481         count >>= 2;
2482         if (!count)
2483                 return;
2484         _ipw_write32(priv, IPW_AUTOINC_ADDR, start);
2485         while (count--)
2486                 _ipw_write32(priv, IPW_AUTOINC_DATA, 0);
2487 }
2488
2489 static inline void ipw_fw_dma_reset_command_blocks(struct ipw_priv *priv)
2490 {
2491         ipw_zero_memory(priv, IPW_SHARED_SRAM_DMA_CONTROL,
2492                         CB_NUMBER_OF_ELEMENTS_SMALL *
2493                         sizeof(struct command_block));
2494 }
2495
2496 static int ipw_fw_dma_enable(struct ipw_priv *priv)
2497 {                               /* start dma engine but no transfers yet */
2498
2499         IPW_DEBUG_FW(">> : \n");
2500
2501         /* Start the dma */
2502         ipw_fw_dma_reset_command_blocks(priv);
2503
2504         /* Write CB base address */
2505         ipw_write_reg32(priv, IPW_DMA_I_CB_BASE, IPW_SHARED_SRAM_DMA_CONTROL);
2506
2507         IPW_DEBUG_FW("<< : \n");
2508         return 0;
2509 }
2510
2511 static void ipw_fw_dma_abort(struct ipw_priv *priv)
2512 {
2513         u32 control = 0;
2514
2515         IPW_DEBUG_FW(">> :\n");
2516
2517         //set the Stop and Abort bit
2518         control = DMA_CONTROL_SMALL_CB_CONST_VALUE | DMA_CB_STOP_AND_ABORT;
2519         ipw_write_reg32(priv, IPW_DMA_I_DMA_CONTROL, control);
2520         priv->sram_desc.last_cb_index = 0;
2521
2522         IPW_DEBUG_FW("<< \n");
2523 }
2524
2525 static int ipw_fw_dma_write_command_block(struct ipw_priv *priv, int index,
2526                                           struct command_block *cb)
2527 {
2528         u32 address =
2529             IPW_SHARED_SRAM_DMA_CONTROL +
2530             (sizeof(struct command_block) * index);
2531         IPW_DEBUG_FW(">> :\n");
2532
2533         ipw_write_indirect(priv, address, (u8 *) cb,
2534                            (int)sizeof(struct command_block));
2535
2536         IPW_DEBUG_FW("<< :\n");
2537         return 0;
2538
2539 }
2540
2541 static int ipw_fw_dma_kick(struct ipw_priv *priv)
2542 {
2543         u32 control = 0;
2544         u32 index = 0;
2545
2546         IPW_DEBUG_FW(">> :\n");
2547
2548         for (index = 0; index < priv->sram_desc.last_cb_index; index++)
2549                 ipw_fw_dma_write_command_block(priv, index,
2550                                                &priv->sram_desc.cb_list[index]);
2551
2552         /* Enable the DMA in the CSR register */
2553         ipw_clear_bit(priv, IPW_RESET_REG,
2554                       IPW_RESET_REG_MASTER_DISABLED |
2555                       IPW_RESET_REG_STOP_MASTER);
2556
2557         /* Set the Start bit. */
2558         control = DMA_CONTROL_SMALL_CB_CONST_VALUE | DMA_CB_START;
2559         ipw_write_reg32(priv, IPW_DMA_I_DMA_CONTROL, control);
2560
2561         IPW_DEBUG_FW("<< :\n");
2562         return 0;
2563 }
2564
2565 static void ipw_fw_dma_dump_command_block(struct ipw_priv *priv)
2566 {
2567         u32 address;
2568         u32 register_value = 0;
2569         u32 cb_fields_address = 0;
2570
2571         IPW_DEBUG_FW(">> :\n");
2572         address = ipw_read_reg32(priv, IPW_DMA_I_CURRENT_CB);
2573         IPW_DEBUG_FW_INFO("Current CB is 0x%x \n", address);
2574
2575         /* Read the DMA Controlor register */
2576         register_value = ipw_read_reg32(priv, IPW_DMA_I_DMA_CONTROL);
2577         IPW_DEBUG_FW_INFO("IPW_DMA_I_DMA_CONTROL is 0x%x \n", register_value);
2578
2579         /* Print the CB values */
2580         cb_fields_address = address;
2581         register_value = ipw_read_reg32(priv, cb_fields_address);
2582         IPW_DEBUG_FW_INFO("Current CB ControlField is 0x%x \n", register_value);
2583
2584         cb_fields_address += sizeof(u32);
2585         register_value = ipw_read_reg32(priv, cb_fields_address);
2586         IPW_DEBUG_FW_INFO("Current CB Source Field is 0x%x \n", register_value);
2587
2588         cb_fields_address += sizeof(u32);
2589         register_value = ipw_read_reg32(priv, cb_fields_address);
2590         IPW_DEBUG_FW_INFO("Current CB Destination Field is 0x%x \n",
2591                           register_value);
2592
2593         cb_fields_address += sizeof(u32);
2594         register_value = ipw_read_reg32(priv, cb_fields_address);
2595         IPW_DEBUG_FW_INFO("Current CB Status Field is 0x%x \n", register_value);
2596
2597         IPW_DEBUG_FW(">> :\n");
2598 }
2599
2600 static int ipw_fw_dma_command_block_index(struct ipw_priv *priv)
2601 {
2602         u32 current_cb_address = 0;
2603         u32 current_cb_index = 0;
2604
2605         IPW_DEBUG_FW("<< :\n");
2606         current_cb_address = ipw_read_reg32(priv, IPW_DMA_I_CURRENT_CB);
2607
2608         current_cb_index = (current_cb_address - IPW_SHARED_SRAM_DMA_CONTROL) /
2609             sizeof(struct command_block);
2610
2611         IPW_DEBUG_FW_INFO("Current CB index 0x%x address = 0x%X \n",
2612                           current_cb_index, current_cb_address);
2613
2614         IPW_DEBUG_FW(">> :\n");
2615         return current_cb_index;
2616
2617 }
2618
2619 static int ipw_fw_dma_add_command_block(struct ipw_priv *priv,
2620                                         u32 src_address,
2621                                         u32 dest_address,
2622                                         u32 length,
2623                                         int interrupt_enabled, int is_last)
2624 {
2625
2626         u32 control = CB_VALID | CB_SRC_LE | CB_DEST_LE | CB_SRC_AUTOINC |
2627             CB_SRC_IO_GATED | CB_DEST_AUTOINC | CB_SRC_SIZE_LONG |
2628             CB_DEST_SIZE_LONG;
2629         struct command_block *cb;
2630         u32 last_cb_element = 0;
2631
2632         IPW_DEBUG_FW_INFO("src_address=0x%x dest_address=0x%x length=0x%x\n",
2633                           src_address, dest_address, length);
2634
2635         if (priv->sram_desc.last_cb_index >= CB_NUMBER_OF_ELEMENTS_SMALL)
2636                 return -1;
2637
2638         last_cb_element = priv->sram_desc.last_cb_index;
2639         cb = &priv->sram_desc.cb_list[last_cb_element];
2640         priv->sram_desc.last_cb_index++;
2641
2642         /* Calculate the new CB control word */
2643         if (interrupt_enabled)
2644                 control |= CB_INT_ENABLED;
2645
2646         if (is_last)
2647                 control |= CB_LAST_VALID;
2648
2649         control |= length;
2650
2651         /* Calculate the CB Element's checksum value */
2652         cb->status = control ^ src_address ^ dest_address;
2653
2654         /* Copy the Source and Destination addresses */
2655         cb->dest_addr = dest_address;
2656         cb->source_addr = src_address;
2657
2658         /* Copy the Control Word last */
2659         cb->control = control;
2660
2661         return 0;
2662 }
2663
2664 static int ipw_fw_dma_add_buffer(struct ipw_priv *priv,
2665                                  u32 src_phys, u32 dest_address, u32 length)
2666 {
2667         u32 bytes_left = length;
2668         u32 src_offset = 0;
2669         u32 dest_offset = 0;
2670         int status = 0;
2671         IPW_DEBUG_FW(">> \n");
2672         IPW_DEBUG_FW_INFO("src_phys=0x%x dest_address=0x%x length=0x%x\n",
2673                           src_phys, dest_address, length);
2674         while (bytes_left > CB_MAX_LENGTH) {
2675                 status = ipw_fw_dma_add_command_block(priv,
2676                                                       src_phys + src_offset,
2677                                                       dest_address +
2678                                                       dest_offset,
2679                                                       CB_MAX_LENGTH, 0, 0);
2680                 if (status) {
2681                         IPW_DEBUG_FW_INFO(": Failed\n");
2682                         return -1;
2683                 } else
2684                         IPW_DEBUG_FW_INFO(": Added new cb\n");
2685
2686                 src_offset += CB_MAX_LENGTH;
2687                 dest_offset += CB_MAX_LENGTH;
2688                 bytes_left -= CB_MAX_LENGTH;
2689         }
2690
2691         /* add the buffer tail */
2692         if (bytes_left > 0) {
2693                 status =
2694                     ipw_fw_dma_add_command_block(priv, src_phys + src_offset,
2695                                                  dest_address + dest_offset,
2696                                                  bytes_left, 0, 0);
2697                 if (status) {
2698                         IPW_DEBUG_FW_INFO(": Failed on the buffer tail\n");
2699                         return -1;
2700                 } else
2701                         IPW_DEBUG_FW_INFO
2702                             (": Adding new cb - the buffer tail\n");
2703         }
2704
2705         IPW_DEBUG_FW("<< \n");
2706         return 0;
2707 }
2708
2709 static int ipw_fw_dma_wait(struct ipw_priv *priv)
2710 {
2711         u32 current_index = 0, previous_index;
2712         u32 watchdog = 0;
2713
2714         IPW_DEBUG_FW(">> : \n");
2715
2716         current_index = ipw_fw_dma_command_block_index(priv);
2717         IPW_DEBUG_FW_INFO("sram_desc.last_cb_index:0x%08X\n",
2718                           (int)priv->sram_desc.last_cb_index);
2719
2720         while (current_index < priv->sram_desc.last_cb_index) {
2721                 udelay(50);
2722                 previous_index = current_index;
2723                 current_index = ipw_fw_dma_command_block_index(priv);
2724
2725                 if (previous_index < current_index) {
2726                         watchdog = 0;
2727                         continue;
2728                 }
2729                 if (++watchdog > 400) {
2730                         IPW_DEBUG_FW_INFO("Timeout\n");
2731                         ipw_fw_dma_dump_command_block(priv);
2732                         ipw_fw_dma_abort(priv);
2733                         return -1;
2734                 }
2735         }
2736
2737         ipw_fw_dma_abort(priv);
2738
2739         /*Disable the DMA in the CSR register */
2740         ipw_set_bit(priv, IPW_RESET_REG,
2741                     IPW_RESET_REG_MASTER_DISABLED | IPW_RESET_REG_STOP_MASTER);
2742
2743         IPW_DEBUG_FW("<< dmaWaitSync \n");
2744         return 0;
2745 }
2746
2747 static void ipw_remove_current_network(struct ipw_priv *priv)
2748 {
2749         struct list_head *element, *safe;
2750         struct ieee80211_network *network = NULL;
2751         unsigned long flags;
2752
2753         spin_lock_irqsave(&priv->ieee->lock, flags);
2754         list_for_each_safe(element, safe, &priv->ieee->network_list) {
2755                 network = list_entry(element, struct ieee80211_network, list);
2756                 if (!memcmp(network->bssid, priv->bssid, ETH_ALEN)) {
2757                         list_del(element);
2758                         list_add_tail(&network->list,
2759                                       &priv->ieee->network_free_list);
2760                 }
2761         }
2762         spin_unlock_irqrestore(&priv->ieee->lock, flags);
2763 }
2764
2765 /**
2766  * Check that card is still alive.
2767  * Reads debug register from domain0.
2768  * If card is present, pre-defined value should
2769  * be found there.
2770  *
2771  * @param priv
2772  * @return 1 if card is present, 0 otherwise
2773  */
2774 static inline int ipw_alive(struct ipw_priv *priv)
2775 {
2776         return ipw_read32(priv, 0x90) == 0xd55555d5;
2777 }
2778
2779 /* timeout in msec, attempted in 10-msec quanta */
2780 static int ipw_poll_bit(struct ipw_priv *priv, u32 addr, u32 mask,
2781                                int timeout)
2782 {
2783         int i = 0;
2784
2785         do {
2786                 if ((ipw_read32(priv, addr) & mask) == mask)
2787                         return i;
2788                 mdelay(10);
2789                 i += 10;
2790         } while (i < timeout);
2791
2792         return -ETIME;
2793 }
2794
2795 /* These functions load the firmware and micro code for the operation of
2796  * the ipw hardware.  It assumes the buffer has all the bits for the
2797  * image and the caller is handling the memory allocation and clean up.
2798  */
2799
2800 static int ipw_stop_master(struct ipw_priv *priv)
2801 {
2802         int rc;
2803
2804         IPW_DEBUG_TRACE(">> \n");
2805         /* stop master. typical delay - 0 */
2806         ipw_set_bit(priv, IPW_RESET_REG, IPW_RESET_REG_STOP_MASTER);
2807
2808         /* timeout is in msec, polled in 10-msec quanta */
2809         rc = ipw_poll_bit(priv, IPW_RESET_REG,
2810                           IPW_RESET_REG_MASTER_DISABLED, 100);
2811         if (rc < 0) {
2812                 IPW_ERROR("wait for stop master failed after 100ms\n");
2813                 return -1;
2814         }
2815
2816         IPW_DEBUG_INFO("stop master %dms\n", rc);
2817
2818         return rc;
2819 }
2820
2821 static void ipw_arc_release(struct ipw_priv *priv)
2822 {
2823         IPW_DEBUG_TRACE(">> \n");
2824         mdelay(5);
2825
2826         ipw_clear_bit(priv, IPW_RESET_REG, CBD_RESET_REG_PRINCETON_RESET);
2827
2828         /* no one knows timing, for safety add some delay */
2829         mdelay(5);
2830 }
2831
2832 struct fw_chunk {
2833         u32 address;
2834         u32 length;
2835 };
2836
2837 static int ipw_load_ucode(struct ipw_priv *priv, u8 * data, size_t len)
2838 {
2839         int rc = 0, i, addr;
2840         u8 cr = 0;
2841         u16 *image;
2842
2843         image = (u16 *) data;
2844
2845         IPW_DEBUG_TRACE(">> \n");
2846
2847         rc = ipw_stop_master(priv);
2848
2849         if (rc < 0)
2850                 return rc;
2851
2852 //      spin_lock_irqsave(&priv->lock, flags);
2853
2854         for (addr = IPW_SHARED_LOWER_BOUND;
2855              addr < IPW_REGISTER_DOMAIN1_END; addr += 4) {
2856                 ipw_write32(priv, addr, 0);
2857         }
2858
2859         /* no ucode (yet) */
2860         memset(&priv->dino_alive, 0, sizeof(priv->dino_alive));
2861         /* destroy DMA queues */
2862         /* reset sequence */
2863
2864         ipw_write_reg32(priv, IPW_MEM_HALT_AND_RESET, IPW_BIT_HALT_RESET_ON);
2865         ipw_arc_release(priv);
2866         ipw_write_reg32(priv, IPW_MEM_HALT_AND_RESET, IPW_BIT_HALT_RESET_OFF);
2867         mdelay(1);
2868
2869         /* reset PHY */
2870         ipw_write_reg32(priv, IPW_INTERNAL_CMD_EVENT, IPW_BASEBAND_POWER_DOWN);
2871         mdelay(1);
2872
2873         ipw_write_reg32(priv, IPW_INTERNAL_CMD_EVENT, 0);
2874         mdelay(1);
2875
2876         /* enable ucode store */
2877         ipw_write_reg8(priv, IPW_BASEBAND_CONTROL_STATUS, 0x0);
2878         ipw_write_reg8(priv, IPW_BASEBAND_CONTROL_STATUS, DINO_ENABLE_CS);
2879         mdelay(1);
2880
2881         /* write ucode */
2882         /**
2883          * @bug
2884          * Do NOT set indirect address register once and then
2885          * store data to indirect data register in the loop.
2886          * It seems very reasonable, but in this case DINO do not
2887          * accept ucode. It is essential to set address each time.
2888          */
2889         /* load new ipw uCode */
2890         for (i = 0; i < len / 2; i++)
2891                 ipw_write_reg16(priv, IPW_BASEBAND_CONTROL_STORE,
2892                                 cpu_to_le16(image[i]));
2893
2894         /* enable DINO */
2895         ipw_write_reg8(priv, IPW_BASEBAND_CONTROL_STATUS, 0);
2896         ipw_write_reg8(priv, IPW_BASEBAND_CONTROL_STATUS, DINO_ENABLE_SYSTEM);
2897
2898         /* this is where the igx / win driver deveates from the VAP driver. */
2899
2900         /* wait for alive response */
2901         for (i = 0; i < 100; i++) {
2902                 /* poll for incoming data */
2903                 cr = ipw_read_reg8(priv, IPW_BASEBAND_CONTROL_STATUS);
2904                 if (cr & DINO_RXFIFO_DATA)
2905                         break;
2906                 mdelay(1);
2907         }
2908
2909         if (cr & DINO_RXFIFO_DATA) {
2910                 /* alive_command_responce size is NOT multiple of 4 */
2911                 u32 response_buffer[(sizeof(priv->dino_alive) + 3) / 4];
2912
2913                 for (i = 0; i < ARRAY_SIZE(response_buffer); i++)
2914                         response_buffer[i] =
2915                             le32_to_cpu(ipw_read_reg32(priv,
2916                                                        IPW_BASEBAND_RX_FIFO_READ));
2917                 memcpy(&priv->dino_alive, response_buffer,
2918                        sizeof(priv->dino_alive));
2919                 if (priv->dino_alive.alive_command == 1
2920                     && priv->dino_alive.ucode_valid == 1) {
2921                         rc = 0;
2922                         IPW_DEBUG_INFO
2923                             ("Microcode OK, rev. %d (0x%x) dev. %d (0x%x) "
2924                              "of %02d/%02d/%02d %02d:%02d\n",
2925                              priv->dino_alive.software_revision,
2926                              priv->dino_alive.software_revision,
2927                              priv->dino_alive.device_identifier,
2928                              priv->dino_alive.device_identifier,
2929                              priv->dino_alive.time_stamp[0],
2930                              priv->dino_alive.time_stamp[1],
2931                              priv->dino_alive.time_stamp[2],
2932                              priv->dino_alive.time_stamp[3],
2933                              priv->dino_alive.time_stamp[4]);
2934                 } else {
2935                         IPW_DEBUG_INFO("Microcode is not alive\n");
2936                         rc = -EINVAL;
2937                 }
2938         } else {
2939                 IPW_DEBUG_INFO("No alive response from DINO\n");
2940                 rc = -ETIME;
2941         }
2942
2943         /* disable DINO, otherwise for some reason
2944            firmware have problem getting alive resp. */
2945         ipw_write_reg8(priv, IPW_BASEBAND_CONTROL_STATUS, 0);
2946
2947 //      spin_unlock_irqrestore(&priv->lock, flags);
2948
2949         return rc;
2950 }
2951
2952 static int ipw_load_firmware(struct ipw_priv *priv, u8 * data, size_t len)
2953 {
2954         int rc = -1;
2955         int offset = 0;
2956         struct fw_chunk *chunk;
2957         dma_addr_t shared_phys;
2958         u8 *shared_virt;
2959
2960         IPW_DEBUG_TRACE("<< : \n");
2961         shared_virt = pci_alloc_consistent(priv->pci_dev, len, &shared_phys);
2962
2963         if (!shared_virt)
2964                 return -ENOMEM;
2965
2966         memmove(shared_virt, data, len);
2967
2968         /* Start the Dma */
2969         rc = ipw_fw_dma_enable(priv);
2970
2971         if (priv->sram_desc.last_cb_index > 0) {
2972                 /* the DMA is already ready this would be a bug. */
2973                 BUG();
2974                 goto out;
2975         }
2976
2977         do {
2978                 chunk = (struct fw_chunk *)(data + offset);
2979                 offset += sizeof(struct fw_chunk);
2980                 /* build DMA packet and queue up for sending */
2981                 /* dma to chunk->address, the chunk->length bytes from data +
2982                  * offeset*/
2983                 /* Dma loading */
2984                 rc = ipw_fw_dma_add_buffer(priv, shared_phys + offset,
2985                                            le32_to_cpu(chunk->address),
2986                                            le32_to_cpu(chunk->length));
2987                 if (rc) {
2988                         IPW_DEBUG_INFO("dmaAddBuffer Failed\n");
2989                         goto out;
2990                 }
2991
2992                 offset += le32_to_cpu(chunk->length);
2993         } while (offset < len);
2994
2995         /* Run the DMA and wait for the answer */
2996         rc = ipw_fw_dma_kick(priv);
2997         if (rc) {
2998                 IPW_ERROR("dmaKick Failed\n");
2999                 goto out;
3000         }
3001
3002         rc = ipw_fw_dma_wait(priv);
3003         if (rc) {
3004                 IPW_ERROR("dmaWaitSync Failed\n");
3005                 goto out;
3006         }
3007       out:
3008         pci_free_consistent(priv->pci_dev, len, shared_virt, shared_phys);
3009         return rc;
3010 }
3011
3012 /* stop nic */
3013 static int ipw_stop_nic(struct ipw_priv *priv)
3014 {
3015         int rc = 0;
3016
3017         /* stop */
3018         ipw_write32(priv, IPW_RESET_REG, IPW_RESET_REG_STOP_MASTER);
3019
3020         rc = ipw_poll_bit(priv, IPW_RESET_REG,
3021                           IPW_RESET_REG_MASTER_DISABLED, 500);
3022         if (rc < 0) {
3023                 IPW_ERROR("wait for reg master disabled failed after 500ms\n");
3024                 return rc;
3025         }
3026
3027         ipw_set_bit(priv, IPW_RESET_REG, CBD_RESET_REG_PRINCETON_RESET);
3028
3029         return rc;
3030 }
3031
3032 static void ipw_start_nic(struct ipw_priv *priv)
3033 {
3034         IPW_DEBUG_TRACE(">>\n");
3035
3036         /* prvHwStartNic  release ARC */
3037         ipw_clear_bit(priv, IPW_RESET_REG,
3038                       IPW_RESET_REG_MASTER_DISABLED |
3039                       IPW_RESET_REG_STOP_MASTER |
3040                       CBD_RESET_REG_PRINCETON_RESET);
3041
3042         /* enable power management */
3043         ipw_set_bit(priv, IPW_GP_CNTRL_RW,
3044                     IPW_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY);
3045
3046         IPW_DEBUG_TRACE("<<\n");
3047 }
3048
3049 static int ipw_init_nic(struct ipw_priv *priv)
3050 {
3051         int rc;
3052
3053         IPW_DEBUG_TRACE(">>\n");
3054         /* reset */
3055         /*prvHwInitNic */
3056         /* set "initialization complete" bit to move adapter to D0 state */
3057         ipw_set_bit(priv, IPW_GP_CNTRL_RW, IPW_GP_CNTRL_BIT_INIT_DONE);
3058
3059         /* low-level PLL activation */
3060         ipw_write32(priv, IPW_READ_INT_REGISTER,
3061                     IPW_BIT_INT_HOST_SRAM_READ_INT_REGISTER);
3062
3063         /* wait for clock stabilization */
3064         rc = ipw_poll_bit(priv, IPW_GP_CNTRL_RW,
3065                           IPW_GP_CNTRL_BIT_CLOCK_READY, 250);
3066         if (rc < 0)
3067                 IPW_DEBUG_INFO("FAILED wait for clock stablization\n");
3068
3069         /* assert SW reset */
3070         ipw_set_bit(priv, IPW_RESET_REG, IPW_RESET_REG_SW_RESET);
3071
3072         udelay(10);
3073
3074         /* set "initialization complete" bit to move adapter to D0 state */
3075         ipw_set_bit(priv, IPW_GP_CNTRL_RW, IPW_GP_CNTRL_BIT_INIT_DONE);
3076
3077         IPW_DEBUG_TRACE(">>\n");
3078         return 0;
3079 }
3080
3081 /* Call this function from process context, it will sleep in request_firmware.
3082  * Probe is an ok place to call this from.
3083  */
3084 static int ipw_reset_nic(struct ipw_priv *priv)
3085 {
3086         int rc = 0;
3087         unsigned long flags;
3088
3089         IPW_DEBUG_TRACE(">>\n");
3090
3091         rc = ipw_init_nic(priv);
3092
3093         spin_lock_irqsave(&priv->lock, flags);
3094         /* Clear the 'host command active' bit... */
3095         priv->status &= ~STATUS_HCMD_ACTIVE;
3096         wake_up_interruptible(&priv->wait_command_queue);
3097         priv->status &= ~(STATUS_SCANNING | STATUS_SCAN_ABORTING);
3098         wake_up_interruptible(&priv->wait_state);
3099         spin_unlock_irqrestore(&priv->lock, flags);
3100
3101         IPW_DEBUG_TRACE("<<\n");
3102         return rc;
3103 }
3104
3105
3106 struct ipw_fw {
3107         u32 ver;
3108         u32 boot_size;
3109         u32 ucode_size;
3110         u32 fw_size;
3111         u8 data[0];
3112 };
3113
3114 static int ipw_get_fw(struct ipw_priv *priv,
3115                       const struct firmware **raw, const char *name)
3116 {
3117         struct ipw_fw *fw;
3118         int rc;
3119
3120         /* ask firmware_class module to get the boot firmware off disk */
3121         rc = request_firmware(raw, name, &priv->pci_dev->dev);
3122         if (rc < 0) {
3123                 IPW_ERROR("%s request_firmware failed: Reason %d\n", name, rc);
3124                 return rc;
3125         }
3126
3127         if ((*raw)->size < sizeof(*fw)) {
3128                 IPW_ERROR("%s is too small (%zd)\n", name, (*raw)->size);
3129                 return -EINVAL;
3130         }
3131
3132         fw = (void *)(*raw)->data;
3133
3134         if ((*raw)->size < sizeof(*fw) +
3135             fw->boot_size + fw->ucode_size + fw->fw_size) {
3136                 IPW_ERROR("%s is too small or corrupt (%zd)\n",
3137                           name, (*raw)->size);
3138                 return -EINVAL;
3139         }
3140
3141         IPW_DEBUG_INFO("Read firmware '%s' image v%d.%d (%zd bytes)\n",
3142                        name,
3143                        le32_to_cpu(fw->ver) >> 16,
3144                        le32_to_cpu(fw->ver) & 0xff,
3145                        (*raw)->size - sizeof(*fw));
3146         return 0;
3147 }
3148
3149 #define IPW_RX_BUF_SIZE (3000)
3150
3151 static void ipw_rx_queue_reset(struct ipw_priv *priv,
3152                                       struct ipw_rx_queue *rxq)
3153 {
3154         unsigned long flags;
3155         int i;
3156
3157         spin_lock_irqsave(&rxq->lock, flags);
3158
3159         INIT_LIST_HEAD(&rxq->rx_free);
3160         INIT_LIST_HEAD(&rxq->rx_used);
3161
3162         /* Fill the rx_used queue with _all_ of the Rx buffers */
3163         for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
3164                 /* In the reset function, these buffers may have been allocated
3165                  * to an SKB, so we need to unmap and free potential storage */
3166                 if (rxq->pool[i].skb != NULL) {
3167                         pci_unmap_single(priv->pci_dev, rxq->pool[i].dma_addr,
3168                                          IPW_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3169                         dev_kfree_skb(rxq->pool[i].skb);
3170                         rxq->pool[i].skb = NULL;
3171                 }
3172                 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
3173         }
3174
3175         /* Set us so that we have processed and used all buffers, but have
3176          * not restocked the Rx queue with fresh buffers */
3177         rxq->read = rxq->write = 0;
3178         rxq->processed = RX_QUEUE_SIZE - 1;
3179         rxq->free_count = 0;
3180         spin_unlock_irqrestore(&rxq->lock, flags);
3181 }
3182
3183 #ifdef CONFIG_PM
3184 static int fw_loaded = 0;
3185 static const struct firmware *raw = NULL;
3186
3187 static void free_firmware(void)
3188 {
3189         if (fw_loaded) {
3190                 release_firmware(raw);
3191                 raw = NULL;
3192                 fw_loaded = 0;
3193         }
3194 }
3195 #else
3196 #define free_firmware() do {} while (0)
3197 #endif
3198
3199 static int ipw_load(struct ipw_priv *priv)
3200 {
3201 #ifndef CONFIG_PM
3202         const struct firmware *raw = NULL;
3203 #endif
3204         struct ipw_fw *fw;
3205         u8 *boot_img, *ucode_img, *fw_img;
3206         u8 *name = NULL;
3207         int rc = 0, retries = 3;
3208
3209         switch (priv->ieee->iw_mode) {
3210         case IW_MODE_ADHOC:
3211                 name = "ipw2200-ibss.fw";
3212                 break;
3213 #ifdef CONFIG_IPW2200_MONITOR