Merge branch 'upstream-fixes'
[sfrench/cifs-2.6.git] / drivers / net / wireless / ipw2200.c
1 /******************************************************************************
2
3   Copyright(c) 2003 - 2005 Intel Corporation. All rights reserved.
4
5   802.11 status code portion of this file from ethereal-0.10.6:
6     Copyright 2000, Axis Communications AB
7     Ethereal - Network traffic analyzer
8     By Gerald Combs <gerald@ethereal.com>
9     Copyright 1998 Gerald Combs
10
11   This program is free software; you can redistribute it and/or modify it
12   under the terms of version 2 of the GNU General Public License as
13   published by the Free Software Foundation.
14
15   This program is distributed in the hope that it will be useful, but WITHOUT
16   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
18   more details.
19
20   You should have received a copy of the GNU General Public License along with
21   this program; if not, write to the Free Software Foundation, Inc., 59
22   Temple Place - Suite 330, Boston, MA  02111-1307, USA.
23
24   The full GNU General Public License is included in this distribution in the
25   file called LICENSE.
26
27   Contact Information:
28   James P. Ketrenos <ipw2100-admin@linux.intel.com>
29   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30
31 ******************************************************************************/
32
33 #include "ipw2200.h"
34 #include <linux/version.h>
35
36 #define IPW2200_VERSION "git-1.0.10"
37 #define DRV_DESCRIPTION "Intel(R) PRO/Wireless 2200/2915 Network Driver"
38 #define DRV_COPYRIGHT   "Copyright(c) 2003-2005 Intel Corporation"
39 #define DRV_VERSION     IPW2200_VERSION
40
41 #define ETH_P_80211_STATS (ETH_P_80211_RAW + 1)
42
43 MODULE_DESCRIPTION(DRV_DESCRIPTION);
44 MODULE_VERSION(DRV_VERSION);
45 MODULE_AUTHOR(DRV_COPYRIGHT);
46 MODULE_LICENSE("GPL");
47
48 static int cmdlog = 0;
49 static int debug = 0;
50 static int channel = 0;
51 static int mode = 0;
52
53 static u32 ipw_debug_level;
54 static int associate = 1;
55 static int auto_create = 1;
56 static int led = 0;
57 static int disable = 0;
58 static int bt_coexist = 0;
59 static int hwcrypto = 0;
60 static int roaming = 1;
61 static const char ipw_modes[] = {
62         'a', 'b', 'g', '?'
63 };
64
65 #ifdef CONFIG_IPW_QOS
66 static int qos_enable = 0;
67 static int qos_burst_enable = 0;
68 static int qos_no_ack_mask = 0;
69 static int burst_duration_CCK = 0;
70 static int burst_duration_OFDM = 0;
71
72 static struct ieee80211_qos_parameters def_qos_parameters_OFDM = {
73         {QOS_TX0_CW_MIN_OFDM, QOS_TX1_CW_MIN_OFDM, QOS_TX2_CW_MIN_OFDM,
74          QOS_TX3_CW_MIN_OFDM},
75         {QOS_TX0_CW_MAX_OFDM, QOS_TX1_CW_MAX_OFDM, QOS_TX2_CW_MAX_OFDM,
76          QOS_TX3_CW_MAX_OFDM},
77         {QOS_TX0_AIFS, QOS_TX1_AIFS, QOS_TX2_AIFS, QOS_TX3_AIFS},
78         {QOS_TX0_ACM, QOS_TX1_ACM, QOS_TX2_ACM, QOS_TX3_ACM},
79         {QOS_TX0_TXOP_LIMIT_OFDM, QOS_TX1_TXOP_LIMIT_OFDM,
80          QOS_TX2_TXOP_LIMIT_OFDM, QOS_TX3_TXOP_LIMIT_OFDM}
81 };
82
83 static struct ieee80211_qos_parameters def_qos_parameters_CCK = {
84         {QOS_TX0_CW_MIN_CCK, QOS_TX1_CW_MIN_CCK, QOS_TX2_CW_MIN_CCK,
85          QOS_TX3_CW_MIN_CCK},
86         {QOS_TX0_CW_MAX_CCK, QOS_TX1_CW_MAX_CCK, QOS_TX2_CW_MAX_CCK,
87          QOS_TX3_CW_MAX_CCK},
88         {QOS_TX0_AIFS, QOS_TX1_AIFS, QOS_TX2_AIFS, QOS_TX3_AIFS},
89         {QOS_TX0_ACM, QOS_TX1_ACM, QOS_TX2_ACM, QOS_TX3_ACM},
90         {QOS_TX0_TXOP_LIMIT_CCK, QOS_TX1_TXOP_LIMIT_CCK, QOS_TX2_TXOP_LIMIT_CCK,
91          QOS_TX3_TXOP_LIMIT_CCK}
92 };
93
94 static struct ieee80211_qos_parameters def_parameters_OFDM = {
95         {DEF_TX0_CW_MIN_OFDM, DEF_TX1_CW_MIN_OFDM, DEF_TX2_CW_MIN_OFDM,
96          DEF_TX3_CW_MIN_OFDM},
97         {DEF_TX0_CW_MAX_OFDM, DEF_TX1_CW_MAX_OFDM, DEF_TX2_CW_MAX_OFDM,
98          DEF_TX3_CW_MAX_OFDM},
99         {DEF_TX0_AIFS, DEF_TX1_AIFS, DEF_TX2_AIFS, DEF_TX3_AIFS},
100         {DEF_TX0_ACM, DEF_TX1_ACM, DEF_TX2_ACM, DEF_TX3_ACM},
101         {DEF_TX0_TXOP_LIMIT_OFDM, DEF_TX1_TXOP_LIMIT_OFDM,
102          DEF_TX2_TXOP_LIMIT_OFDM, DEF_TX3_TXOP_LIMIT_OFDM}
103 };
104
105 static struct ieee80211_qos_parameters def_parameters_CCK = {
106         {DEF_TX0_CW_MIN_CCK, DEF_TX1_CW_MIN_CCK, DEF_TX2_CW_MIN_CCK,
107          DEF_TX3_CW_MIN_CCK},
108         {DEF_TX0_CW_MAX_CCK, DEF_TX1_CW_MAX_CCK, DEF_TX2_CW_MAX_CCK,
109          DEF_TX3_CW_MAX_CCK},
110         {DEF_TX0_AIFS, DEF_TX1_AIFS, DEF_TX2_AIFS, DEF_TX3_AIFS},
111         {DEF_TX0_ACM, DEF_TX1_ACM, DEF_TX2_ACM, DEF_TX3_ACM},
112         {DEF_TX0_TXOP_LIMIT_CCK, DEF_TX1_TXOP_LIMIT_CCK, DEF_TX2_TXOP_LIMIT_CCK,
113          DEF_TX3_TXOP_LIMIT_CCK}
114 };
115
116 static u8 qos_oui[QOS_OUI_LEN] = { 0x00, 0x50, 0xF2 };
117
118 static int from_priority_to_tx_queue[] = {
119         IPW_TX_QUEUE_1, IPW_TX_QUEUE_2, IPW_TX_QUEUE_2, IPW_TX_QUEUE_1,
120         IPW_TX_QUEUE_3, IPW_TX_QUEUE_3, IPW_TX_QUEUE_4, IPW_TX_QUEUE_4
121 };
122
123 static u32 ipw_qos_get_burst_duration(struct ipw_priv *priv);
124
125 static int ipw_send_qos_params_command(struct ipw_priv *priv, struct ieee80211_qos_parameters
126                                        *qos_param);
127 static int ipw_send_qos_info_command(struct ipw_priv *priv, struct ieee80211_qos_information_element
128                                      *qos_param);
129 #endif                          /* CONFIG_IPW_QOS */
130
131 static struct iw_statistics *ipw_get_wireless_stats(struct net_device *dev);
132 static void ipw_remove_current_network(struct ipw_priv *priv);
133 static void ipw_rx(struct ipw_priv *priv);
134 static int ipw_queue_tx_reclaim(struct ipw_priv *priv,
135                                 struct clx2_tx_queue *txq, int qindex);
136 static int ipw_queue_reset(struct ipw_priv *priv);
137
138 static int ipw_queue_tx_hcmd(struct ipw_priv *priv, int hcmd, void *buf,
139                              int len, int sync);
140
141 static void ipw_tx_queue_free(struct ipw_priv *);
142
143 static struct ipw_rx_queue *ipw_rx_queue_alloc(struct ipw_priv *);
144 static void ipw_rx_queue_free(struct ipw_priv *, struct ipw_rx_queue *);
145 static void ipw_rx_queue_replenish(void *);
146 static int ipw_up(struct ipw_priv *);
147 static void ipw_bg_up(void *);
148 static void ipw_down(struct ipw_priv *);
149 static void ipw_bg_down(void *);
150 static int ipw_config(struct ipw_priv *);
151 static int init_supported_rates(struct ipw_priv *priv,
152                                 struct ipw_supported_rates *prates);
153 static void ipw_set_hwcrypto_keys(struct ipw_priv *);
154 static void ipw_send_wep_keys(struct ipw_priv *, int);
155
156 static int ipw_is_valid_channel(struct ieee80211_device *, u8);
157 static int ipw_channel_to_index(struct ieee80211_device *, u8);
158 static u8 ipw_freq_to_channel(struct ieee80211_device *, u32);
159 static int ipw_set_geo(struct ieee80211_device *, const struct ieee80211_geo *);
160 static const struct ieee80211_geo *ipw_get_geo(struct ieee80211_device *);
161
162 static int snprint_line(char *buf, size_t count,
163                         const u8 * data, u32 len, u32 ofs)
164 {
165         int out, i, j, l;
166         char c;
167
168         out = snprintf(buf, count, "%08X", ofs);
169
170         for (l = 0, i = 0; i < 2; i++) {
171                 out += snprintf(buf + out, count - out, " ");
172                 for (j = 0; j < 8 && l < len; j++, l++)
173                         out += snprintf(buf + out, count - out, "%02X ",
174                                         data[(i * 8 + j)]);
175                 for (; j < 8; j++)
176                         out += snprintf(buf + out, count - out, "   ");
177         }
178
179         out += snprintf(buf + out, count - out, " ");
180         for (l = 0, i = 0; i < 2; i++) {
181                 out += snprintf(buf + out, count - out, " ");
182                 for (j = 0; j < 8 && l < len; j++, l++) {
183                         c = data[(i * 8 + j)];
184                         if (!isascii(c) || !isprint(c))
185                                 c = '.';
186
187                         out += snprintf(buf + out, count - out, "%c", c);
188                 }
189
190                 for (; j < 8; j++)
191                         out += snprintf(buf + out, count - out, " ");
192         }
193
194         return out;
195 }
196
197 static void printk_buf(int level, const u8 * data, u32 len)
198 {
199         char line[81];
200         u32 ofs = 0;
201         if (!(ipw_debug_level & level))
202                 return;
203
204         while (len) {
205                 snprint_line(line, sizeof(line), &data[ofs],
206                              min(len, 16U), ofs);
207                 printk(KERN_DEBUG "%s\n", line);
208                 ofs += 16;
209                 len -= min(len, 16U);
210         }
211 }
212
213 static int snprintk_buf(u8 * output, size_t size, const u8 * data, size_t len)
214 {
215         size_t out = size;
216         u32 ofs = 0;
217         int total = 0;
218
219         while (size && len) {
220                 out = snprint_line(output, size, &data[ofs],
221                                    min_t(size_t, len, 16U), ofs);
222
223                 ofs += 16;
224                 output += out;
225                 size -= out;
226                 len -= min_t(size_t, len, 16U);
227                 total += out;
228         }
229         return total;
230 }
231
232 /* alias for 32-bit indirect read (for SRAM/reg above 4K), with debug wrapper */
233 static u32 _ipw_read_reg32(struct ipw_priv *priv, u32 reg);
234 #define ipw_read_reg32(a, b) _ipw_read_reg32(a, b)
235
236 /* alias for 8-bit indirect read (for SRAM/reg above 4K), with debug wrapper */
237 static u8 _ipw_read_reg8(struct ipw_priv *ipw, u32 reg);
238 #define ipw_read_reg8(a, b) _ipw_read_reg8(a, b)
239
240 /* 8-bit indirect write (for SRAM/reg above 4K), with debug wrapper */
241 static void _ipw_write_reg8(struct ipw_priv *priv, u32 reg, u8 value);
242 static inline void ipw_write_reg8(struct ipw_priv *a, u32 b, u8 c)
243 {
244         IPW_DEBUG_IO("%s %d: write_indirect8(0x%08X, 0x%08X)\n", __FILE__,
245                      __LINE__, (u32) (b), (u32) (c));
246         _ipw_write_reg8(a, b, c);
247 }
248
249 /* 16-bit indirect write (for SRAM/reg above 4K), with debug wrapper */
250 static void _ipw_write_reg16(struct ipw_priv *priv, u32 reg, u16 value);
251 static inline void ipw_write_reg16(struct ipw_priv *a, u32 b, u16 c)
252 {
253         IPW_DEBUG_IO("%s %d: write_indirect16(0x%08X, 0x%08X)\n", __FILE__,
254                      __LINE__, (u32) (b), (u32) (c));
255         _ipw_write_reg16(a, b, c);
256 }
257
258 /* 32-bit indirect write (for SRAM/reg above 4K), with debug wrapper */
259 static void _ipw_write_reg32(struct ipw_priv *priv, u32 reg, u32 value);
260 static inline void ipw_write_reg32(struct ipw_priv *a, u32 b, u32 c)
261 {
262         IPW_DEBUG_IO("%s %d: write_indirect32(0x%08X, 0x%08X)\n", __FILE__,
263                      __LINE__, (u32) (b), (u32) (c));
264         _ipw_write_reg32(a, b, c);
265 }
266
267 /* 8-bit direct write (low 4K) */
268 #define _ipw_write8(ipw, ofs, val) writeb((val), (ipw)->hw_base + (ofs))
269
270 /* 8-bit direct write (for low 4K of SRAM/regs), with debug wrapper */
271 #define ipw_write8(ipw, ofs, val) \
272  IPW_DEBUG_IO("%s %d: write_direct8(0x%08X, 0x%08X)\n", __FILE__, __LINE__, (u32)(ofs), (u32)(val)); \
273  _ipw_write8(ipw, ofs, val)
274
275 /* 16-bit direct write (low 4K) */
276 #define _ipw_write16(ipw, ofs, val) writew((val), (ipw)->hw_base + (ofs))
277
278 /* 16-bit direct write (for low 4K of SRAM/regs), with debug wrapper */
279 #define ipw_write16(ipw, ofs, val) \
280  IPW_DEBUG_IO("%s %d: write_direct16(0x%08X, 0x%08X)\n", __FILE__, __LINE__, (u32)(ofs), (u32)(val)); \
281  _ipw_write16(ipw, ofs, val)
282
283 /* 32-bit direct write (low 4K) */
284 #define _ipw_write32(ipw, ofs, val) writel((val), (ipw)->hw_base + (ofs))
285
286 /* 32-bit direct write (for low 4K of SRAM/regs), with debug wrapper */
287 #define ipw_write32(ipw, ofs, val) \
288  IPW_DEBUG_IO("%s %d: write_direct32(0x%08X, 0x%08X)\n", __FILE__, __LINE__, (u32)(ofs), (u32)(val)); \
289  _ipw_write32(ipw, ofs, val)
290
291 /* 8-bit direct read (low 4K) */
292 #define _ipw_read8(ipw, ofs) readb((ipw)->hw_base + (ofs))
293
294 /* 8-bit direct read (low 4K), with debug wrapper */
295 static inline u8 __ipw_read8(char *f, u32 l, struct ipw_priv *ipw, u32 ofs)
296 {
297         IPW_DEBUG_IO("%s %d: read_direct8(0x%08X)\n", f, l, (u32) (ofs));
298         return _ipw_read8(ipw, ofs);
299 }
300
301 /* alias to 8-bit direct read (low 4K of SRAM/regs), with debug wrapper */
302 #define ipw_read8(ipw, ofs) __ipw_read8(__FILE__, __LINE__, ipw, ofs)
303
304 /* 16-bit direct read (low 4K) */
305 #define _ipw_read16(ipw, ofs) readw((ipw)->hw_base + (ofs))
306
307 /* 16-bit direct read (low 4K), with debug wrapper */
308 static inline u16 __ipw_read16(char *f, u32 l, struct ipw_priv *ipw, u32 ofs)
309 {
310         IPW_DEBUG_IO("%s %d: read_direct16(0x%08X)\n", f, l, (u32) (ofs));
311         return _ipw_read16(ipw, ofs);
312 }
313
314 /* alias to 16-bit direct read (low 4K of SRAM/regs), with debug wrapper */
315 #define ipw_read16(ipw, ofs) __ipw_read16(__FILE__, __LINE__, ipw, ofs)
316
317 /* 32-bit direct read (low 4K) */
318 #define _ipw_read32(ipw, ofs) readl((ipw)->hw_base + (ofs))
319
320 /* 32-bit direct read (low 4K), with debug wrapper */
321 static inline u32 __ipw_read32(char *f, u32 l, struct ipw_priv *ipw, u32 ofs)
322 {
323         IPW_DEBUG_IO("%s %d: read_direct32(0x%08X)\n", f, l, (u32) (ofs));
324         return _ipw_read32(ipw, ofs);
325 }
326
327 /* alias to 32-bit direct read (low 4K of SRAM/regs), with debug wrapper */
328 #define ipw_read32(ipw, ofs) __ipw_read32(__FILE__, __LINE__, ipw, ofs)
329
330 /* multi-byte read (above 4K), with debug wrapper */
331 static void _ipw_read_indirect(struct ipw_priv *, u32, u8 *, int);
332 static inline void __ipw_read_indirect(const char *f, int l,
333                                        struct ipw_priv *a, u32 b, u8 * c, int d)
334 {
335         IPW_DEBUG_IO("%s %d: read_indirect(0x%08X) %d bytes\n", f, l, (u32) (b),
336                      d);
337         _ipw_read_indirect(a, b, c, d);
338 }
339
340 /* alias to multi-byte read (SRAM/regs above 4K), with debug wrapper */
341 #define ipw_read_indirect(a, b, c, d) __ipw_read_indirect(__FILE__, __LINE__, a, b, c, d)
342
343 /* alias to multi-byte read (SRAM/regs above 4K), with debug wrapper */
344 static void _ipw_write_indirect(struct ipw_priv *priv, u32 addr, u8 * data,
345                                 int num);
346 #define ipw_write_indirect(a, b, c, d) \
347         IPW_DEBUG_IO("%s %d: write_indirect(0x%08X) %d bytes\n", __FILE__, __LINE__, (u32)(b), d); \
348         _ipw_write_indirect(a, b, c, d)
349
350 /* 32-bit indirect write (above 4K) */
351 static void _ipw_write_reg32(struct ipw_priv *priv, u32 reg, u32 value)
352 {
353         IPW_DEBUG_IO(" %p : reg = 0x%8X : value = 0x%8X\n", priv, reg, value);
354         _ipw_write32(priv, IPW_INDIRECT_ADDR, reg);
355         _ipw_write32(priv, IPW_INDIRECT_DATA, value);
356 }
357
358 /* 8-bit indirect write (above 4K) */
359 static void _ipw_write_reg8(struct ipw_priv *priv, u32 reg, u8 value)
360 {
361         u32 aligned_addr = reg & IPW_INDIRECT_ADDR_MASK;        /* dword align */
362         u32 dif_len = reg - aligned_addr;
363
364         IPW_DEBUG_IO(" reg = 0x%8X : value = 0x%8X\n", reg, value);
365         _ipw_write32(priv, IPW_INDIRECT_ADDR, aligned_addr);
366         _ipw_write8(priv, IPW_INDIRECT_DATA + dif_len, value);
367 }
368
369 /* 16-bit indirect write (above 4K) */
370 static void _ipw_write_reg16(struct ipw_priv *priv, u32 reg, u16 value)
371 {
372         u32 aligned_addr = reg & IPW_INDIRECT_ADDR_MASK;        /* dword align */
373         u32 dif_len = (reg - aligned_addr) & (~0x1ul);
374
375         IPW_DEBUG_IO(" reg = 0x%8X : value = 0x%8X\n", reg, value);
376         _ipw_write32(priv, IPW_INDIRECT_ADDR, aligned_addr);
377         _ipw_write16(priv, IPW_INDIRECT_DATA + dif_len, value);
378 }
379
380 /* 8-bit indirect read (above 4K) */
381 static u8 _ipw_read_reg8(struct ipw_priv *priv, u32 reg)
382 {
383         u32 word;
384         _ipw_write32(priv, IPW_INDIRECT_ADDR, reg & IPW_INDIRECT_ADDR_MASK);
385         IPW_DEBUG_IO(" reg = 0x%8X : \n", reg);
386         word = _ipw_read32(priv, IPW_INDIRECT_DATA);
387         return (word >> ((reg & 0x3) * 8)) & 0xff;
388 }
389
390 /* 32-bit indirect read (above 4K) */
391 static u32 _ipw_read_reg32(struct ipw_priv *priv, u32 reg)
392 {
393         u32 value;
394
395         IPW_DEBUG_IO("%p : reg = 0x%08x\n", priv, reg);
396
397         _ipw_write32(priv, IPW_INDIRECT_ADDR, reg);
398         value = _ipw_read32(priv, IPW_INDIRECT_DATA);
399         IPW_DEBUG_IO(" reg = 0x%4X : value = 0x%4x \n", reg, value);
400         return value;
401 }
402
403 /* General purpose, no alignment requirement, iterative (multi-byte) read, */
404 /*    for area above 1st 4K of SRAM/reg space */
405 static void _ipw_read_indirect(struct ipw_priv *priv, u32 addr, u8 * buf,
406                                int num)
407 {
408         u32 aligned_addr = addr & IPW_INDIRECT_ADDR_MASK;       /* dword align */
409         u32 dif_len = addr - aligned_addr;
410         u32 i;
411
412         IPW_DEBUG_IO("addr = %i, buf = %p, num = %i\n", addr, buf, num);
413
414         if (num <= 0) {
415                 return;
416         }
417
418         /* Read the first dword (or portion) byte by byte */
419         if (unlikely(dif_len)) {
420                 _ipw_write32(priv, IPW_INDIRECT_ADDR, aligned_addr);
421                 /* Start reading at aligned_addr + dif_len */
422                 for (i = dif_len; ((i < 4) && (num > 0)); i++, num--)
423                         *buf++ = _ipw_read8(priv, IPW_INDIRECT_DATA + i);
424                 aligned_addr += 4;
425         }
426
427         /* Read all of the middle dwords as dwords, with auto-increment */
428         _ipw_write32(priv, IPW_AUTOINC_ADDR, aligned_addr);
429         for (; num >= 4; buf += 4, aligned_addr += 4, num -= 4)
430                 *(u32 *) buf = _ipw_read32(priv, IPW_AUTOINC_DATA);
431
432         /* Read the last dword (or portion) byte by byte */
433         if (unlikely(num)) {
434                 _ipw_write32(priv, IPW_INDIRECT_ADDR, aligned_addr);
435                 for (i = 0; num > 0; i++, num--)
436                         *buf++ = ipw_read8(priv, IPW_INDIRECT_DATA + i);
437         }
438 }
439
440 /* General purpose, no alignment requirement, iterative (multi-byte) write, */
441 /*    for area above 1st 4K of SRAM/reg space */
442 static void _ipw_write_indirect(struct ipw_priv *priv, u32 addr, u8 * buf,
443                                 int num)
444 {
445         u32 aligned_addr = addr & IPW_INDIRECT_ADDR_MASK;       /* dword align */
446         u32 dif_len = addr - aligned_addr;
447         u32 i;
448
449         IPW_DEBUG_IO("addr = %i, buf = %p, num = %i\n", addr, buf, num);
450
451         if (num <= 0) {
452                 return;
453         }
454
455         /* Write the first dword (or portion) byte by byte */
456         if (unlikely(dif_len)) {
457                 _ipw_write32(priv, IPW_INDIRECT_ADDR, aligned_addr);
458                 /* Start writing at aligned_addr + dif_len */
459                 for (i = dif_len; ((i < 4) && (num > 0)); i++, num--, buf++)
460                         _ipw_write8(priv, IPW_INDIRECT_DATA + i, *buf);
461                 aligned_addr += 4;
462         }
463
464         /* Write all of the middle dwords as dwords, with auto-increment */
465         _ipw_write32(priv, IPW_AUTOINC_ADDR, aligned_addr);
466         for (; num >= 4; buf += 4, aligned_addr += 4, num -= 4)
467                 _ipw_write32(priv, IPW_AUTOINC_DATA, *(u32 *) buf);
468
469         /* Write the last dword (or portion) byte by byte */
470         if (unlikely(num)) {
471                 _ipw_write32(priv, IPW_INDIRECT_ADDR, aligned_addr);
472                 for (i = 0; num > 0; i++, num--, buf++)
473                         _ipw_write8(priv, IPW_INDIRECT_DATA + i, *buf);
474         }
475 }
476
477 /* General purpose, no alignment requirement, iterative (multi-byte) write, */
478 /*    for 1st 4K of SRAM/regs space */
479 static void ipw_write_direct(struct ipw_priv *priv, u32 addr, void *buf,
480                              int num)
481 {
482         memcpy_toio((priv->hw_base + addr), buf, num);
483 }
484
485 /* Set bit(s) in low 4K of SRAM/regs */
486 static inline void ipw_set_bit(struct ipw_priv *priv, u32 reg, u32 mask)
487 {
488         ipw_write32(priv, reg, ipw_read32(priv, reg) | mask);
489 }
490
491 /* Clear bit(s) in low 4K of SRAM/regs */
492 static inline void ipw_clear_bit(struct ipw_priv *priv, u32 reg, u32 mask)
493 {
494         ipw_write32(priv, reg, ipw_read32(priv, reg) & ~mask);
495 }
496
497 static inline void ipw_enable_interrupts(struct ipw_priv *priv)
498 {
499         if (priv->status & STATUS_INT_ENABLED)
500                 return;
501         priv->status |= STATUS_INT_ENABLED;
502         ipw_write32(priv, IPW_INTA_MASK_R, IPW_INTA_MASK_ALL);
503 }
504
505 static inline void ipw_disable_interrupts(struct ipw_priv *priv)
506 {
507         if (!(priv->status & STATUS_INT_ENABLED))
508                 return;
509         priv->status &= ~STATUS_INT_ENABLED;
510         ipw_write32(priv, IPW_INTA_MASK_R, ~IPW_INTA_MASK_ALL);
511 }
512
513 #ifdef CONFIG_IPW2200_DEBUG
514 static char *ipw_error_desc(u32 val)
515 {
516         switch (val) {
517         case IPW_FW_ERROR_OK:
518                 return "ERROR_OK";
519         case IPW_FW_ERROR_FAIL:
520                 return "ERROR_FAIL";
521         case IPW_FW_ERROR_MEMORY_UNDERFLOW:
522                 return "MEMORY_UNDERFLOW";
523         case IPW_FW_ERROR_MEMORY_OVERFLOW:
524                 return "MEMORY_OVERFLOW";
525         case IPW_FW_ERROR_BAD_PARAM:
526                 return "BAD_PARAM";
527         case IPW_FW_ERROR_BAD_CHECKSUM:
528                 return "BAD_CHECKSUM";
529         case IPW_FW_ERROR_NMI_INTERRUPT:
530                 return "NMI_INTERRUPT";
531         case IPW_FW_ERROR_BAD_DATABASE:
532                 return "BAD_DATABASE";
533         case IPW_FW_ERROR_ALLOC_FAIL:
534                 return "ALLOC_FAIL";
535         case IPW_FW_ERROR_DMA_UNDERRUN:
536                 return "DMA_UNDERRUN";
537         case IPW_FW_ERROR_DMA_STATUS:
538                 return "DMA_STATUS";
539         case IPW_FW_ERROR_DINO_ERROR:
540                 return "DINO_ERROR";
541         case IPW_FW_ERROR_EEPROM_ERROR:
542                 return "EEPROM_ERROR";
543         case IPW_FW_ERROR_SYSASSERT:
544                 return "SYSASSERT";
545         case IPW_FW_ERROR_FATAL_ERROR:
546                 return "FATAL_ERROR";
547         default:
548                 return "UNKNOWN_ERROR";
549         }
550 }
551
552 static void ipw_dump_error_log(struct ipw_priv *priv,
553                                struct ipw_fw_error *error)
554 {
555         u32 i;
556
557         if (!error) {
558                 IPW_ERROR("Error allocating and capturing error log.  "
559                           "Nothing to dump.\n");
560                 return;
561         }
562
563         IPW_ERROR("Start IPW Error Log Dump:\n");
564         IPW_ERROR("Status: 0x%08X, Config: %08X\n",
565                   error->status, error->config);
566
567         for (i = 0; i < error->elem_len; i++)
568                 IPW_ERROR("%s %i 0x%08x  0x%08x  0x%08x  0x%08x  0x%08x\n",
569                           ipw_error_desc(error->elem[i].desc),
570                           error->elem[i].time,
571                           error->elem[i].blink1,
572                           error->elem[i].blink2,
573                           error->elem[i].link1,
574                           error->elem[i].link2, error->elem[i].data);
575         for (i = 0; i < error->log_len; i++)
576                 IPW_ERROR("%i\t0x%08x\t%i\n",
577                           error->log[i].time,
578                           error->log[i].data, error->log[i].event);
579 }
580 #endif
581
582 static inline int ipw_is_init(struct ipw_priv *priv)
583 {
584         return (priv->status & STATUS_INIT) ? 1 : 0;
585 }
586
587 static int ipw_get_ordinal(struct ipw_priv *priv, u32 ord, void *val, u32 * len)
588 {
589         u32 addr, field_info, field_len, field_count, total_len;
590
591         IPW_DEBUG_ORD("ordinal = %i\n", ord);
592
593         if (!priv || !val || !len) {
594                 IPW_DEBUG_ORD("Invalid argument\n");
595                 return -EINVAL;
596         }
597
598         /* verify device ordinal tables have been initialized */
599         if (!priv->table0_addr || !priv->table1_addr || !priv->table2_addr) {
600                 IPW_DEBUG_ORD("Access ordinals before initialization\n");
601                 return -EINVAL;
602         }
603
604         switch (IPW_ORD_TABLE_ID_MASK & ord) {
605         case IPW_ORD_TABLE_0_MASK:
606                 /*
607                  * TABLE 0: Direct access to a table of 32 bit values
608                  *
609                  * This is a very simple table with the data directly
610                  * read from the table
611                  */
612
613                 /* remove the table id from the ordinal */
614                 ord &= IPW_ORD_TABLE_VALUE_MASK;
615
616                 /* boundary check */
617                 if (ord > priv->table0_len) {
618                         IPW_DEBUG_ORD("ordinal value (%i) longer then "
619                                       "max (%i)\n", ord, priv->table0_len);
620                         return -EINVAL;
621                 }
622
623                 /* verify we have enough room to store the value */
624                 if (*len < sizeof(u32)) {
625                         IPW_DEBUG_ORD("ordinal buffer length too small, "
626                                       "need %zd\n", sizeof(u32));
627                         return -EINVAL;
628                 }
629
630                 IPW_DEBUG_ORD("Reading TABLE0[%i] from offset 0x%08x\n",
631                               ord, priv->table0_addr + (ord << 2));
632
633                 *len = sizeof(u32);
634                 ord <<= 2;
635                 *((u32 *) val) = ipw_read32(priv, priv->table0_addr + ord);
636                 break;
637
638         case IPW_ORD_TABLE_1_MASK:
639                 /*
640                  * TABLE 1: Indirect access to a table of 32 bit values
641                  *
642                  * This is a fairly large table of u32 values each
643                  * representing starting addr for the data (which is
644                  * also a u32)
645                  */
646
647                 /* remove the table id from the ordinal */
648                 ord &= IPW_ORD_TABLE_VALUE_MASK;
649
650                 /* boundary check */
651                 if (ord > priv->table1_len) {
652                         IPW_DEBUG_ORD("ordinal value too long\n");
653                         return -EINVAL;
654                 }
655
656                 /* verify we have enough room to store the value */
657                 if (*len < sizeof(u32)) {
658                         IPW_DEBUG_ORD("ordinal buffer length too small, "
659                                       "need %zd\n", sizeof(u32));
660                         return -EINVAL;
661                 }
662
663                 *((u32 *) val) =
664                     ipw_read_reg32(priv, (priv->table1_addr + (ord << 2)));
665                 *len = sizeof(u32);
666                 break;
667
668         case IPW_ORD_TABLE_2_MASK:
669                 /*
670                  * TABLE 2: Indirect access to a table of variable sized values
671                  *
672                  * This table consist of six values, each containing
673                  *     - dword containing the starting offset of the data
674                  *     - dword containing the lengh in the first 16bits
675                  *       and the count in the second 16bits
676                  */
677
678                 /* remove the table id from the ordinal */
679                 ord &= IPW_ORD_TABLE_VALUE_MASK;
680
681                 /* boundary check */
682                 if (ord > priv->table2_len) {
683                         IPW_DEBUG_ORD("ordinal value too long\n");
684                         return -EINVAL;
685                 }
686
687                 /* get the address of statistic */
688                 addr = ipw_read_reg32(priv, priv->table2_addr + (ord << 3));
689
690                 /* get the second DW of statistics ;
691                  * two 16-bit words - first is length, second is count */
692                 field_info =
693                     ipw_read_reg32(priv,
694                                    priv->table2_addr + (ord << 3) +
695                                    sizeof(u32));
696
697                 /* get each entry length */
698                 field_len = *((u16 *) & field_info);
699
700                 /* get number of entries */
701                 field_count = *(((u16 *) & field_info) + 1);
702
703                 /* abort if not enought memory */
704                 total_len = field_len * field_count;
705                 if (total_len > *len) {
706                         *len = total_len;
707                         return -EINVAL;
708                 }
709
710                 *len = total_len;
711                 if (!total_len)
712                         return 0;
713
714                 IPW_DEBUG_ORD("addr = 0x%08x, total_len = %i, "
715                               "field_info = 0x%08x\n",
716                               addr, total_len, field_info);
717                 ipw_read_indirect(priv, addr, val, total_len);
718                 break;
719
720         default:
721                 IPW_DEBUG_ORD("Invalid ordinal!\n");
722                 return -EINVAL;
723
724         }
725
726         return 0;
727 }
728
729 static void ipw_init_ordinals(struct ipw_priv *priv)
730 {
731         priv->table0_addr = IPW_ORDINALS_TABLE_LOWER;
732         priv->table0_len = ipw_read32(priv, priv->table0_addr);
733
734         IPW_DEBUG_ORD("table 0 offset at 0x%08x, len = %i\n",
735                       priv->table0_addr, priv->table0_len);
736
737         priv->table1_addr = ipw_read32(priv, IPW_ORDINALS_TABLE_1);
738         priv->table1_len = ipw_read_reg32(priv, priv->table1_addr);
739
740         IPW_DEBUG_ORD("table 1 offset at 0x%08x, len = %i\n",
741                       priv->table1_addr, priv->table1_len);
742
743         priv->table2_addr = ipw_read32(priv, IPW_ORDINALS_TABLE_2);
744         priv->table2_len = ipw_read_reg32(priv, priv->table2_addr);
745         priv->table2_len &= 0x0000ffff; /* use first two bytes */
746
747         IPW_DEBUG_ORD("table 2 offset at 0x%08x, len = %i\n",
748                       priv->table2_addr, priv->table2_len);
749
750 }
751
752 static u32 ipw_register_toggle(u32 reg)
753 {
754         reg &= ~IPW_START_STANDBY;
755         if (reg & IPW_GATE_ODMA)
756                 reg &= ~IPW_GATE_ODMA;
757         if (reg & IPW_GATE_IDMA)
758                 reg &= ~IPW_GATE_IDMA;
759         if (reg & IPW_GATE_ADMA)
760                 reg &= ~IPW_GATE_ADMA;
761         return reg;
762 }
763
764 /*
765  * LED behavior:
766  * - On radio ON, turn on any LEDs that require to be on during start
767  * - On initialization, start unassociated blink
768  * - On association, disable unassociated blink
769  * - On disassociation, start unassociated blink
770  * - On radio OFF, turn off any LEDs started during radio on
771  *
772  */
773 #define LD_TIME_LINK_ON msecs_to_jiffies(300)
774 #define LD_TIME_LINK_OFF msecs_to_jiffies(2700)
775 #define LD_TIME_ACT_ON msecs_to_jiffies(250)
776
777 static void ipw_led_link_on(struct ipw_priv *priv)
778 {
779         unsigned long flags;
780         u32 led;
781
782         /* If configured to not use LEDs, or nic_type is 1,
783          * then we don't toggle a LINK led */
784         if (priv->config & CFG_NO_LED || priv->nic_type == EEPROM_NIC_TYPE_1)
785                 return;
786
787         spin_lock_irqsave(&priv->lock, flags);
788
789         if (!(priv->status & STATUS_RF_KILL_MASK) &&
790             !(priv->status & STATUS_LED_LINK_ON)) {
791                 IPW_DEBUG_LED("Link LED On\n");
792                 led = ipw_read_reg32(priv, IPW_EVENT_REG);
793                 led |= priv->led_association_on;
794
795                 led = ipw_register_toggle(led);
796
797                 IPW_DEBUG_LED("Reg: 0x%08X\n", led);
798                 ipw_write_reg32(priv, IPW_EVENT_REG, led);
799
800                 priv->status |= STATUS_LED_LINK_ON;
801
802                 /* If we aren't associated, schedule turning the LED off */
803                 if (!(priv->status & STATUS_ASSOCIATED))
804                         queue_delayed_work(priv->workqueue,
805                                            &priv->led_link_off,
806                                            LD_TIME_LINK_ON);
807         }
808
809         spin_unlock_irqrestore(&priv->lock, flags);
810 }
811
812 static void ipw_bg_led_link_on(void *data)
813 {
814         struct ipw_priv *priv = data;
815         mutex_lock(&priv->mutex);
816         ipw_led_link_on(data);
817         mutex_unlock(&priv->mutex);
818 }
819
820 static void ipw_led_link_off(struct ipw_priv *priv)
821 {
822         unsigned long flags;
823         u32 led;
824
825         /* If configured not to use LEDs, or nic type is 1,
826          * then we don't goggle the LINK led. */
827         if (priv->config & CFG_NO_LED || priv->nic_type == EEPROM_NIC_TYPE_1)
828                 return;
829
830         spin_lock_irqsave(&priv->lock, flags);
831
832         if (priv->status & STATUS_LED_LINK_ON) {
833                 led = ipw_read_reg32(priv, IPW_EVENT_REG);
834                 led &= priv->led_association_off;
835                 led = ipw_register_toggle(led);
836
837                 IPW_DEBUG_LED("Reg: 0x%08X\n", led);
838                 ipw_write_reg32(priv, IPW_EVENT_REG, led);
839
840                 IPW_DEBUG_LED("Link LED Off\n");
841
842                 priv->status &= ~STATUS_LED_LINK_ON;
843
844                 /* If we aren't associated and the radio is on, schedule
845                  * turning the LED on (blink while unassociated) */
846                 if (!(priv->status & STATUS_RF_KILL_MASK) &&
847                     !(priv->status & STATUS_ASSOCIATED))
848                         queue_delayed_work(priv->workqueue, &priv->led_link_on,
849                                            LD_TIME_LINK_OFF);
850
851         }
852
853         spin_unlock_irqrestore(&priv->lock, flags);
854 }
855
856 static void ipw_bg_led_link_off(void *data)
857 {
858         struct ipw_priv *priv = data;
859         mutex_lock(&priv->mutex);
860         ipw_led_link_off(data);
861         mutex_unlock(&priv->mutex);
862 }
863
864 static void __ipw_led_activity_on(struct ipw_priv *priv)
865 {
866         u32 led;
867
868         if (priv->config & CFG_NO_LED)
869                 return;
870
871         if (priv->status & STATUS_RF_KILL_MASK)
872                 return;
873
874         if (!(priv->status & STATUS_LED_ACT_ON)) {
875                 led = ipw_read_reg32(priv, IPW_EVENT_REG);
876                 led |= priv->led_activity_on;
877
878                 led = ipw_register_toggle(led);
879
880                 IPW_DEBUG_LED("Reg: 0x%08X\n", led);
881                 ipw_write_reg32(priv, IPW_EVENT_REG, led);
882
883                 IPW_DEBUG_LED("Activity LED On\n");
884
885                 priv->status |= STATUS_LED_ACT_ON;
886
887                 cancel_delayed_work(&priv->led_act_off);
888                 queue_delayed_work(priv->workqueue, &priv->led_act_off,
889                                    LD_TIME_ACT_ON);
890         } else {
891                 /* Reschedule LED off for full time period */
892                 cancel_delayed_work(&priv->led_act_off);
893                 queue_delayed_work(priv->workqueue, &priv->led_act_off,
894                                    LD_TIME_ACT_ON);
895         }
896 }
897
898 #if 0
899 void ipw_led_activity_on(struct ipw_priv *priv)
900 {
901         unsigned long flags;
902         spin_lock_irqsave(&priv->lock, flags);
903         __ipw_led_activity_on(priv);
904         spin_unlock_irqrestore(&priv->lock, flags);
905 }
906 #endif  /*  0  */
907
908 static void ipw_led_activity_off(struct ipw_priv *priv)
909 {
910         unsigned long flags;
911         u32 led;
912
913         if (priv->config & CFG_NO_LED)
914                 return;
915
916         spin_lock_irqsave(&priv->lock, flags);
917
918         if (priv->status & STATUS_LED_ACT_ON) {
919                 led = ipw_read_reg32(priv, IPW_EVENT_REG);
920                 led &= priv->led_activity_off;
921
922                 led = ipw_register_toggle(led);
923
924                 IPW_DEBUG_LED("Reg: 0x%08X\n", led);
925                 ipw_write_reg32(priv, IPW_EVENT_REG, led);
926
927                 IPW_DEBUG_LED("Activity LED Off\n");
928
929                 priv->status &= ~STATUS_LED_ACT_ON;
930         }
931
932         spin_unlock_irqrestore(&priv->lock, flags);
933 }
934
935 static void ipw_bg_led_activity_off(void *data)
936 {
937         struct ipw_priv *priv = data;
938         mutex_lock(&priv->mutex);
939         ipw_led_activity_off(data);
940         mutex_unlock(&priv->mutex);
941 }
942
943 static void ipw_led_band_on(struct ipw_priv *priv)
944 {
945         unsigned long flags;
946         u32 led;
947
948         /* Only nic type 1 supports mode LEDs */
949         if (priv->config & CFG_NO_LED ||
950             priv->nic_type != EEPROM_NIC_TYPE_1 || !priv->assoc_network)
951                 return;
952
953         spin_lock_irqsave(&priv->lock, flags);
954
955         led = ipw_read_reg32(priv, IPW_EVENT_REG);
956         if (priv->assoc_network->mode == IEEE_A) {
957                 led |= priv->led_ofdm_on;
958                 led &= priv->led_association_off;
959                 IPW_DEBUG_LED("Mode LED On: 802.11a\n");
960         } else if (priv->assoc_network->mode == IEEE_G) {
961                 led |= priv->led_ofdm_on;
962                 led |= priv->led_association_on;
963                 IPW_DEBUG_LED("Mode LED On: 802.11g\n");
964         } else {
965                 led &= priv->led_ofdm_off;
966                 led |= priv->led_association_on;
967                 IPW_DEBUG_LED("Mode LED On: 802.11b\n");
968         }
969
970         led = ipw_register_toggle(led);
971
972         IPW_DEBUG_LED("Reg: 0x%08X\n", led);
973         ipw_write_reg32(priv, IPW_EVENT_REG, led);
974
975         spin_unlock_irqrestore(&priv->lock, flags);
976 }
977
978 static void ipw_led_band_off(struct ipw_priv *priv)
979 {
980         unsigned long flags;
981         u32 led;
982
983         /* Only nic type 1 supports mode LEDs */
984         if (priv->config & CFG_NO_LED || priv->nic_type != EEPROM_NIC_TYPE_1)
985                 return;
986
987         spin_lock_irqsave(&priv->lock, flags);
988
989         led = ipw_read_reg32(priv, IPW_EVENT_REG);
990         led &= priv->led_ofdm_off;
991         led &= priv->led_association_off;
992
993         led = ipw_register_toggle(led);
994
995         IPW_DEBUG_LED("Reg: 0x%08X\n", led);
996         ipw_write_reg32(priv, IPW_EVENT_REG, led);
997
998         spin_unlock_irqrestore(&priv->lock, flags);
999 }
1000
1001 static void ipw_led_radio_on(struct ipw_priv *priv)
1002 {
1003         ipw_led_link_on(priv);
1004 }
1005
1006 static void ipw_led_radio_off(struct ipw_priv *priv)
1007 {
1008         ipw_led_activity_off(priv);
1009         ipw_led_link_off(priv);
1010 }
1011
1012 static void ipw_led_link_up(struct ipw_priv *priv)
1013 {
1014         /* Set the Link Led on for all nic types */
1015         ipw_led_link_on(priv);
1016 }
1017
1018 static void ipw_led_link_down(struct ipw_priv *priv)
1019 {
1020         ipw_led_activity_off(priv);
1021         ipw_led_link_off(priv);
1022
1023         if (priv->status & STATUS_RF_KILL_MASK)
1024                 ipw_led_radio_off(priv);
1025 }
1026
1027 static void ipw_led_init(struct ipw_priv *priv)
1028 {
1029         priv->nic_type = priv->eeprom[EEPROM_NIC_TYPE];
1030
1031         /* Set the default PINs for the link and activity leds */
1032         priv->led_activity_on = IPW_ACTIVITY_LED;
1033         priv->led_activity_off = ~(IPW_ACTIVITY_LED);
1034
1035         priv->led_association_on = IPW_ASSOCIATED_LED;
1036         priv->led_association_off = ~(IPW_ASSOCIATED_LED);
1037
1038         /* Set the default PINs for the OFDM leds */
1039         priv->led_ofdm_on = IPW_OFDM_LED;
1040         priv->led_ofdm_off = ~(IPW_OFDM_LED);
1041
1042         switch (priv->nic_type) {
1043         case EEPROM_NIC_TYPE_1:
1044                 /* In this NIC type, the LEDs are reversed.... */
1045                 priv->led_activity_on = IPW_ASSOCIATED_LED;
1046                 priv->led_activity_off = ~(IPW_ASSOCIATED_LED);
1047                 priv->led_association_on = IPW_ACTIVITY_LED;
1048                 priv->led_association_off = ~(IPW_ACTIVITY_LED);
1049
1050                 if (!(priv->config & CFG_NO_LED))
1051                         ipw_led_band_on(priv);
1052
1053                 /* And we don't blink link LEDs for this nic, so
1054                  * just return here */
1055                 return;
1056
1057         case EEPROM_NIC_TYPE_3:
1058         case EEPROM_NIC_TYPE_2:
1059         case EEPROM_NIC_TYPE_4:
1060         case EEPROM_NIC_TYPE_0:
1061                 break;
1062
1063         default:
1064                 IPW_DEBUG_INFO("Unknown NIC type from EEPROM: %d\n",
1065                                priv->nic_type);
1066                 priv->nic_type = EEPROM_NIC_TYPE_0;
1067                 break;
1068         }
1069
1070         if (!(priv->config & CFG_NO_LED)) {
1071                 if (priv->status & STATUS_ASSOCIATED)
1072                         ipw_led_link_on(priv);
1073                 else
1074                         ipw_led_link_off(priv);
1075         }
1076 }
1077
1078 static void ipw_led_shutdown(struct ipw_priv *priv)
1079 {
1080         ipw_led_activity_off(priv);
1081         ipw_led_link_off(priv);
1082         ipw_led_band_off(priv);
1083         cancel_delayed_work(&priv->led_link_on);
1084         cancel_delayed_work(&priv->led_link_off);
1085         cancel_delayed_work(&priv->led_act_off);
1086 }
1087
1088 /*
1089  * The following adds a new attribute to the sysfs representation
1090  * of this device driver (i.e. a new file in /sys/bus/pci/drivers/ipw/)
1091  * used for controling the debug level.
1092  *
1093  * See the level definitions in ipw for details.
1094  */
1095 static ssize_t show_debug_level(struct device_driver *d, char *buf)
1096 {
1097         return sprintf(buf, "0x%08X\n", ipw_debug_level);
1098 }
1099
1100 static ssize_t store_debug_level(struct device_driver *d, const char *buf,
1101                                  size_t count)
1102 {
1103         char *p = (char *)buf;
1104         u32 val;
1105
1106         if (p[1] == 'x' || p[1] == 'X' || p[0] == 'x' || p[0] == 'X') {
1107                 p++;
1108                 if (p[0] == 'x' || p[0] == 'X')
1109                         p++;
1110                 val = simple_strtoul(p, &p, 16);
1111         } else
1112                 val = simple_strtoul(p, &p, 10);
1113         if (p == buf)
1114                 printk(KERN_INFO DRV_NAME
1115                        ": %s is not in hex or decimal form.\n", buf);
1116         else
1117                 ipw_debug_level = val;
1118
1119         return strnlen(buf, count);
1120 }
1121
1122 static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO,
1123                    show_debug_level, store_debug_level);
1124
1125 static inline u32 ipw_get_event_log_len(struct ipw_priv *priv)
1126 {
1127         /* length = 1st dword in log */
1128         return ipw_read_reg32(priv, ipw_read32(priv, IPW_EVENT_LOG));
1129 }
1130
1131 static void ipw_capture_event_log(struct ipw_priv *priv,
1132                                   u32 log_len, struct ipw_event *log)
1133 {
1134         u32 base;
1135
1136         if (log_len) {
1137                 base = ipw_read32(priv, IPW_EVENT_LOG);
1138                 ipw_read_indirect(priv, base + sizeof(base) + sizeof(u32),
1139                                   (u8 *) log, sizeof(*log) * log_len);
1140         }
1141 }
1142
1143 static struct ipw_fw_error *ipw_alloc_error_log(struct ipw_priv *priv)
1144 {
1145         struct ipw_fw_error *error;
1146         u32 log_len = ipw_get_event_log_len(priv);
1147         u32 base = ipw_read32(priv, IPW_ERROR_LOG);
1148         u32 elem_len = ipw_read_reg32(priv, base);
1149
1150         error = kmalloc(sizeof(*error) +
1151                         sizeof(*error->elem) * elem_len +
1152                         sizeof(*error->log) * log_len, GFP_ATOMIC);
1153         if (!error) {
1154                 IPW_ERROR("Memory allocation for firmware error log "
1155                           "failed.\n");
1156                 return NULL;
1157         }
1158         error->jiffies = jiffies;
1159         error->status = priv->status;
1160         error->config = priv->config;
1161         error->elem_len = elem_len;
1162         error->log_len = log_len;
1163         error->elem = (struct ipw_error_elem *)error->payload;
1164         error->log = (struct ipw_event *)(error->elem + elem_len);
1165
1166         ipw_capture_event_log(priv, log_len, error->log);
1167
1168         if (elem_len)
1169                 ipw_read_indirect(priv, base + sizeof(base), (u8 *) error->elem,
1170                                   sizeof(*error->elem) * elem_len);
1171
1172         return error;
1173 }
1174
1175 static void ipw_free_error_log(struct ipw_fw_error *error)
1176 {
1177         if (error)
1178                 kfree(error);
1179 }
1180
1181 static ssize_t show_event_log(struct device *d,
1182                               struct device_attribute *attr, char *buf)
1183 {
1184         struct ipw_priv *priv = dev_get_drvdata(d);
1185         u32 log_len = ipw_get_event_log_len(priv);
1186         struct ipw_event log[log_len];
1187         u32 len = 0, i;
1188
1189         ipw_capture_event_log(priv, log_len, log);
1190
1191         len += snprintf(buf + len, PAGE_SIZE - len, "%08X", log_len);
1192         for (i = 0; i < log_len; i++)
1193                 len += snprintf(buf + len, PAGE_SIZE - len,
1194                                 "\n%08X%08X%08X",
1195                                 log[i].time, log[i].event, log[i].data);
1196         len += snprintf(buf + len, PAGE_SIZE - len, "\n");
1197         return len;
1198 }
1199
1200 static DEVICE_ATTR(event_log, S_IRUGO, show_event_log, NULL);
1201
1202 static ssize_t show_error(struct device *d,
1203                           struct device_attribute *attr, char *buf)
1204 {
1205         struct ipw_priv *priv = dev_get_drvdata(d);
1206         u32 len = 0, i;
1207         if (!priv->error)
1208                 return 0;
1209         len += snprintf(buf + len, PAGE_SIZE - len,
1210                         "%08lX%08X%08X%08X",
1211                         priv->error->jiffies,
1212                         priv->error->status,
1213                         priv->error->config, priv->error->elem_len);
1214         for (i = 0; i < priv->error->elem_len; i++)
1215                 len += snprintf(buf + len, PAGE_SIZE - len,
1216                                 "\n%08X%08X%08X%08X%08X%08X%08X",
1217                                 priv->error->elem[i].time,
1218                                 priv->error->elem[i].desc,
1219                                 priv->error->elem[i].blink1,
1220                                 priv->error->elem[i].blink2,
1221                                 priv->error->elem[i].link1,
1222                                 priv->error->elem[i].link2,
1223                                 priv->error->elem[i].data);
1224
1225         len += snprintf(buf + len, PAGE_SIZE - len,
1226                         "\n%08X", priv->error->log_len);
1227         for (i = 0; i < priv->error->log_len; i++)
1228                 len += snprintf(buf + len, PAGE_SIZE - len,
1229                                 "\n%08X%08X%08X",
1230                                 priv->error->log[i].time,
1231                                 priv->error->log[i].event,
1232                                 priv->error->log[i].data);
1233         len += snprintf(buf + len, PAGE_SIZE - len, "\n");
1234         return len;
1235 }
1236
1237 static ssize_t clear_error(struct device *d,
1238                            struct device_attribute *attr,
1239                            const char *buf, size_t count)
1240 {
1241         struct ipw_priv *priv = dev_get_drvdata(d);
1242         if (priv->error) {
1243                 ipw_free_error_log(priv->error);
1244                 priv->error = NULL;
1245         }
1246         return count;
1247 }
1248
1249 static DEVICE_ATTR(error, S_IRUGO | S_IWUSR, show_error, clear_error);
1250
1251 static ssize_t show_cmd_log(struct device *d,
1252                             struct device_attribute *attr, char *buf)
1253 {
1254         struct ipw_priv *priv = dev_get_drvdata(d);
1255         u32 len = 0, i;
1256         if (!priv->cmdlog)
1257                 return 0;
1258         for (i = (priv->cmdlog_pos + 1) % priv->cmdlog_len;
1259              (i != priv->cmdlog_pos) && (PAGE_SIZE - len);
1260              i = (i + 1) % priv->cmdlog_len) {
1261                 len +=
1262                     snprintf(buf + len, PAGE_SIZE - len,
1263                              "\n%08lX%08X%08X%08X\n", priv->cmdlog[i].jiffies,
1264                              priv->cmdlog[i].retcode, priv->cmdlog[i].cmd.cmd,
1265                              priv->cmdlog[i].cmd.len);
1266                 len +=
1267                     snprintk_buf(buf + len, PAGE_SIZE - len,
1268                                  (u8 *) priv->cmdlog[i].cmd.param,
1269                                  priv->cmdlog[i].cmd.len);
1270                 len += snprintf(buf + len, PAGE_SIZE - len, "\n");
1271         }
1272         len += snprintf(buf + len, PAGE_SIZE - len, "\n");
1273         return len;
1274 }
1275
1276 static DEVICE_ATTR(cmd_log, S_IRUGO, show_cmd_log, NULL);
1277
1278 static ssize_t show_scan_age(struct device *d, struct device_attribute *attr,
1279                              char *buf)
1280 {
1281         struct ipw_priv *priv = dev_get_drvdata(d);
1282         return sprintf(buf, "%d\n", priv->ieee->scan_age);
1283 }
1284
1285 static ssize_t store_scan_age(struct device *d, struct device_attribute *attr,
1286                               const char *buf, size_t count)
1287 {
1288         struct ipw_priv *priv = dev_get_drvdata(d);
1289 #ifdef CONFIG_IPW2200_DEBUG
1290         struct net_device *dev = priv->net_dev;
1291 #endif
1292         char buffer[] = "00000000";
1293         unsigned long len =
1294             (sizeof(buffer) - 1) > count ? count : sizeof(buffer) - 1;
1295         unsigned long val;
1296         char *p = buffer;
1297
1298         IPW_DEBUG_INFO("enter\n");
1299
1300         strncpy(buffer, buf, len);
1301         buffer[len] = 0;
1302
1303         if (p[1] == 'x' || p[1] == 'X' || p[0] == 'x' || p[0] == 'X') {
1304                 p++;
1305                 if (p[0] == 'x' || p[0] == 'X')
1306                         p++;
1307                 val = simple_strtoul(p, &p, 16);
1308         } else
1309                 val = simple_strtoul(p, &p, 10);
1310         if (p == buffer) {
1311                 IPW_DEBUG_INFO("%s: user supplied invalid value.\n", dev->name);
1312         } else {
1313                 priv->ieee->scan_age = val;
1314                 IPW_DEBUG_INFO("set scan_age = %u\n", priv->ieee->scan_age);
1315         }
1316
1317         IPW_DEBUG_INFO("exit\n");
1318         return len;
1319 }
1320
1321 static DEVICE_ATTR(scan_age, S_IWUSR | S_IRUGO, show_scan_age, store_scan_age);
1322
1323 static ssize_t show_led(struct device *d, struct device_attribute *attr,
1324                         char *buf)
1325 {
1326         struct ipw_priv *priv = dev_get_drvdata(d);
1327         return sprintf(buf, "%d\n", (priv->config & CFG_NO_LED) ? 0 : 1);
1328 }
1329
1330 static ssize_t store_led(struct device *d, struct device_attribute *attr,
1331                          const char *buf, size_t count)
1332 {
1333         struct ipw_priv *priv = dev_get_drvdata(d);
1334
1335         IPW_DEBUG_INFO("enter\n");
1336
1337         if (count == 0)
1338                 return 0;
1339
1340         if (*buf == 0) {
1341                 IPW_DEBUG_LED("Disabling LED control.\n");
1342                 priv->config |= CFG_NO_LED;
1343                 ipw_led_shutdown(priv);
1344         } else {
1345                 IPW_DEBUG_LED("Enabling LED control.\n");
1346                 priv->config &= ~CFG_NO_LED;
1347                 ipw_led_init(priv);
1348         }
1349
1350         IPW_DEBUG_INFO("exit\n");
1351         return count;
1352 }
1353
1354 static DEVICE_ATTR(led, S_IWUSR | S_IRUGO, show_led, store_led);
1355
1356 static ssize_t show_status(struct device *d,
1357                            struct device_attribute *attr, char *buf)
1358 {
1359         struct ipw_priv *p = d->driver_data;
1360         return sprintf(buf, "0x%08x\n", (int)p->status);
1361 }
1362
1363 static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
1364
1365 static ssize_t show_cfg(struct device *d, struct device_attribute *attr,
1366                         char *buf)
1367 {
1368         struct ipw_priv *p = d->driver_data;
1369         return sprintf(buf, "0x%08x\n", (int)p->config);
1370 }
1371
1372 static DEVICE_ATTR(cfg, S_IRUGO, show_cfg, NULL);
1373
1374 static ssize_t show_nic_type(struct device *d,
1375                              struct device_attribute *attr, char *buf)
1376 {
1377         struct ipw_priv *priv = d->driver_data;
1378         return sprintf(buf, "TYPE: %d\n", priv->nic_type);
1379 }
1380
1381 static DEVICE_ATTR(nic_type, S_IRUGO, show_nic_type, NULL);
1382
1383 static ssize_t show_ucode_version(struct device *d,
1384                                   struct device_attribute *attr, char *buf)
1385 {
1386         u32 len = sizeof(u32), tmp = 0;
1387         struct ipw_priv *p = d->driver_data;
1388
1389         if (ipw_get_ordinal(p, IPW_ORD_STAT_UCODE_VERSION, &tmp, &len))
1390                 return 0;
1391
1392         return sprintf(buf, "0x%08x\n", tmp);
1393 }
1394
1395 static DEVICE_ATTR(ucode_version, S_IWUSR | S_IRUGO, show_ucode_version, NULL);
1396
1397 static ssize_t show_rtc(struct device *d, struct device_attribute *attr,
1398                         char *buf)
1399 {
1400         u32 len = sizeof(u32), tmp = 0;
1401         struct ipw_priv *p = d->driver_data;
1402
1403         if (ipw_get_ordinal(p, IPW_ORD_STAT_RTC, &tmp, &len))
1404                 return 0;
1405
1406         return sprintf(buf, "0x%08x\n", tmp);
1407 }
1408
1409 static DEVICE_ATTR(rtc, S_IWUSR | S_IRUGO, show_rtc, NULL);
1410
1411 /*
1412  * Add a device attribute to view/control the delay between eeprom
1413  * operations.
1414  */
1415 static ssize_t show_eeprom_delay(struct device *d,
1416                                  struct device_attribute *attr, char *buf)
1417 {
1418         int n = ((struct ipw_priv *)d->driver_data)->eeprom_delay;
1419         return sprintf(buf, "%i\n", n);
1420 }
1421 static ssize_t store_eeprom_delay(struct device *d,
1422                                   struct device_attribute *attr,
1423                                   const char *buf, size_t count)
1424 {
1425         struct ipw_priv *p = d->driver_data;
1426         sscanf(buf, "%i", &p->eeprom_delay);
1427         return strnlen(buf, count);
1428 }
1429
1430 static DEVICE_ATTR(eeprom_delay, S_IWUSR | S_IRUGO,
1431                    show_eeprom_delay, store_eeprom_delay);
1432
1433 static ssize_t show_command_event_reg(struct device *d,
1434                                       struct device_attribute *attr, char *buf)
1435 {
1436         u32 reg = 0;
1437         struct ipw_priv *p = d->driver_data;
1438
1439         reg = ipw_read_reg32(p, IPW_INTERNAL_CMD_EVENT);
1440         return sprintf(buf, "0x%08x\n", reg);
1441 }
1442 static ssize_t store_command_event_reg(struct device *d,
1443                                        struct device_attribute *attr,
1444                                        const char *buf, size_t count)
1445 {
1446         u32 reg;
1447         struct ipw_priv *p = d->driver_data;
1448
1449         sscanf(buf, "%x", &reg);
1450         ipw_write_reg32(p, IPW_INTERNAL_CMD_EVENT, reg);
1451         return strnlen(buf, count);
1452 }
1453
1454 static DEVICE_ATTR(command_event_reg, S_IWUSR | S_IRUGO,
1455                    show_command_event_reg, store_command_event_reg);
1456
1457 static ssize_t show_mem_gpio_reg(struct device *d,
1458                                  struct device_attribute *attr, char *buf)
1459 {
1460         u32 reg = 0;
1461         struct ipw_priv *p = d->driver_data;
1462
1463         reg = ipw_read_reg32(p, 0x301100);
1464         return sprintf(buf, "0x%08x\n", reg);
1465 }
1466 static ssize_t store_mem_gpio_reg(struct device *d,
1467                                   struct device_attribute *attr,
1468                                   const char *buf, size_t count)
1469 {
1470         u32 reg;
1471         struct ipw_priv *p = d->driver_data;
1472
1473         sscanf(buf, "%x", &reg);
1474         ipw_write_reg32(p, 0x301100, reg);
1475         return strnlen(buf, count);
1476 }
1477
1478 static DEVICE_ATTR(mem_gpio_reg, S_IWUSR | S_IRUGO,
1479                    show_mem_gpio_reg, store_mem_gpio_reg);
1480
1481 static ssize_t show_indirect_dword(struct device *d,
1482                                    struct device_attribute *attr, char *buf)
1483 {
1484         u32 reg = 0;
1485         struct ipw_priv *priv = d->driver_data;
1486
1487         if (priv->status & STATUS_INDIRECT_DWORD)
1488                 reg = ipw_read_reg32(priv, priv->indirect_dword);
1489         else
1490                 reg = 0;
1491
1492         return sprintf(buf, "0x%08x\n", reg);
1493 }
1494 static ssize_t store_indirect_dword(struct device *d,
1495                                     struct device_attribute *attr,
1496                                     const char *buf, size_t count)
1497 {
1498         struct ipw_priv *priv = d->driver_data;
1499
1500         sscanf(buf, "%x", &priv->indirect_dword);
1501         priv->status |= STATUS_INDIRECT_DWORD;
1502         return strnlen(buf, count);
1503 }
1504
1505 static DEVICE_ATTR(indirect_dword, S_IWUSR | S_IRUGO,
1506                    show_indirect_dword, store_indirect_dword);
1507
1508 static ssize_t show_indirect_byte(struct device *d,
1509                                   struct device_attribute *attr, char *buf)
1510 {
1511         u8 reg = 0;
1512         struct ipw_priv *priv = d->driver_data;
1513
1514         if (priv->status & STATUS_INDIRECT_BYTE)
1515                 reg = ipw_read_reg8(priv, priv->indirect_byte);
1516         else
1517                 reg = 0;
1518
1519         return sprintf(buf, "0x%02x\n", reg);
1520 }
1521 static ssize_t store_indirect_byte(struct device *d,
1522                                    struct device_attribute *attr,
1523                                    const char *buf, size_t count)
1524 {
1525         struct ipw_priv *priv = d->driver_data;
1526
1527         sscanf(buf, "%x", &priv->indirect_byte);
1528         priv->status |= STATUS_INDIRECT_BYTE;
1529         return strnlen(buf, count);
1530 }
1531
1532 static DEVICE_ATTR(indirect_byte, S_IWUSR | S_IRUGO,
1533                    show_indirect_byte, store_indirect_byte);
1534
1535 static ssize_t show_direct_dword(struct device *d,
1536                                  struct device_attribute *attr, char *buf)
1537 {
1538         u32 reg = 0;
1539         struct ipw_priv *priv = d->driver_data;
1540
1541         if (priv->status & STATUS_DIRECT_DWORD)
1542                 reg = ipw_read32(priv, priv->direct_dword);
1543         else
1544                 reg = 0;
1545
1546         return sprintf(buf, "0x%08x\n", reg);
1547 }
1548 static ssize_t store_direct_dword(struct device *d,
1549                                   struct device_attribute *attr,
1550                                   const char *buf, size_t count)
1551 {
1552         struct ipw_priv *priv = d->driver_data;
1553
1554         sscanf(buf, "%x", &priv->direct_dword);
1555         priv->status |= STATUS_DIRECT_DWORD;
1556         return strnlen(buf, count);
1557 }
1558
1559 static DEVICE_ATTR(direct_dword, S_IWUSR | S_IRUGO,
1560                    show_direct_dword, store_direct_dword);
1561
1562 static int rf_kill_active(struct ipw_priv *priv)
1563 {
1564         if (0 == (ipw_read32(priv, 0x30) & 0x10000))
1565                 priv->status |= STATUS_RF_KILL_HW;
1566         else
1567                 priv->status &= ~STATUS_RF_KILL_HW;
1568
1569         return (priv->status & STATUS_RF_KILL_HW) ? 1 : 0;
1570 }
1571
1572 static ssize_t show_rf_kill(struct device *d, struct device_attribute *attr,
1573                             char *buf)
1574 {
1575         /* 0 - RF kill not enabled
1576            1 - SW based RF kill active (sysfs)
1577            2 - HW based RF kill active
1578            3 - Both HW and SW baed RF kill active */
1579         struct ipw_priv *priv = d->driver_data;
1580         int val = ((priv->status & STATUS_RF_KILL_SW) ? 0x1 : 0x0) |
1581             (rf_kill_active(priv) ? 0x2 : 0x0);
1582         return sprintf(buf, "%i\n", val);
1583 }
1584
1585 static int ipw_radio_kill_sw(struct ipw_priv *priv, int disable_radio)
1586 {
1587         if ((disable_radio ? 1 : 0) ==
1588             ((priv->status & STATUS_RF_KILL_SW) ? 1 : 0))
1589                 return 0;
1590
1591         IPW_DEBUG_RF_KILL("Manual SW RF Kill set to: RADIO  %s\n",
1592                           disable_radio ? "OFF" : "ON");
1593
1594         if (disable_radio) {
1595                 priv->status |= STATUS_RF_KILL_SW;
1596
1597                 if (priv->workqueue)
1598                         cancel_delayed_work(&priv->request_scan);
1599                 queue_work(priv->workqueue, &priv->down);
1600         } else {
1601                 priv->status &= ~STATUS_RF_KILL_SW;
1602                 if (rf_kill_active(priv)) {
1603                         IPW_DEBUG_RF_KILL("Can not turn radio back on - "
1604                                           "disabled by HW switch\n");
1605                         /* Make sure the RF_KILL check timer is running */
1606                         cancel_delayed_work(&priv->rf_kill);
1607                         queue_delayed_work(priv->workqueue, &priv->rf_kill,
1608                                            2 * HZ);
1609                 } else
1610                         queue_work(priv->workqueue, &priv->up);
1611         }
1612
1613         return 1;
1614 }
1615
1616 static ssize_t store_rf_kill(struct device *d, struct device_attribute *attr,
1617                              const char *buf, size_t count)
1618 {
1619         struct ipw_priv *priv = d->driver_data;
1620
1621         ipw_radio_kill_sw(priv, buf[0] == '1');
1622
1623         return count;
1624 }
1625
1626 static DEVICE_ATTR(rf_kill, S_IWUSR | S_IRUGO, show_rf_kill, store_rf_kill);
1627
1628 static ssize_t show_speed_scan(struct device *d, struct device_attribute *attr,
1629                                char *buf)
1630 {
1631         struct ipw_priv *priv = (struct ipw_priv *)d->driver_data;
1632         int pos = 0, len = 0;
1633         if (priv->config & CFG_SPEED_SCAN) {
1634                 while (priv->speed_scan[pos] != 0)
1635                         len += sprintf(&buf[len], "%d ",
1636                                        priv->speed_scan[pos++]);
1637                 return len + sprintf(&buf[len], "\n");
1638         }
1639
1640         return sprintf(buf, "0\n");
1641 }
1642
1643 static ssize_t store_speed_scan(struct device *d, struct device_attribute *attr,
1644                                 const char *buf, size_t count)
1645 {
1646         struct ipw_priv *priv = (struct ipw_priv *)d->driver_data;
1647         int channel, pos = 0;
1648         const char *p = buf;
1649
1650         /* list of space separated channels to scan, optionally ending with 0 */
1651         while ((channel = simple_strtol(p, NULL, 0))) {
1652                 if (pos == MAX_SPEED_SCAN - 1) {
1653                         priv->speed_scan[pos] = 0;
1654                         break;
1655                 }
1656
1657                 if (ipw_is_valid_channel(priv->ieee, channel))
1658                         priv->speed_scan[pos++] = channel;
1659                 else
1660                         IPW_WARNING("Skipping invalid channel request: %d\n",
1661                                     channel);
1662                 p = strchr(p, ' ');
1663                 if (!p)
1664                         break;
1665                 while (*p == ' ' || *p == '\t')
1666                         p++;
1667         }
1668
1669         if (pos == 0)
1670                 priv->config &= ~CFG_SPEED_SCAN;
1671         else {
1672                 priv->speed_scan_pos = 0;
1673                 priv->config |= CFG_SPEED_SCAN;
1674         }
1675
1676         return count;
1677 }
1678
1679 static DEVICE_ATTR(speed_scan, S_IWUSR | S_IRUGO, show_speed_scan,
1680                    store_speed_scan);
1681
1682 static ssize_t show_net_stats(struct device *d, struct device_attribute *attr,
1683                               char *buf)
1684 {
1685         struct ipw_priv *priv = (struct ipw_priv *)d->driver_data;
1686         return sprintf(buf, "%c\n", (priv->config & CFG_NET_STATS) ? '1' : '0');
1687 }
1688
1689 static ssize_t store_net_stats(struct device *d, struct device_attribute *attr,
1690                                const char *buf, size_t count)
1691 {
1692         struct ipw_priv *priv = (struct ipw_priv *)d->driver_data;
1693         if (buf[0] == '1')
1694                 priv->config |= CFG_NET_STATS;
1695         else
1696                 priv->config &= ~CFG_NET_STATS;
1697
1698         return count;
1699 }
1700
1701 static DEVICE_ATTR(net_stats, S_IWUSR | S_IRUGO,
1702                    show_net_stats, store_net_stats);
1703
1704 static void notify_wx_assoc_event(struct ipw_priv *priv)
1705 {
1706         union iwreq_data wrqu;
1707         wrqu.ap_addr.sa_family = ARPHRD_ETHER;
1708         if (priv->status & STATUS_ASSOCIATED)
1709                 memcpy(wrqu.ap_addr.sa_data, priv->bssid, ETH_ALEN);
1710         else
1711                 memset(wrqu.ap_addr.sa_data, 0, ETH_ALEN);
1712         wireless_send_event(priv->net_dev, SIOCGIWAP, &wrqu, NULL);
1713 }
1714
1715 static void ipw_irq_tasklet(struct ipw_priv *priv)
1716 {
1717         u32 inta, inta_mask, handled = 0;
1718         unsigned long flags;
1719         int rc = 0;
1720
1721         spin_lock_irqsave(&priv->lock, flags);
1722
1723         inta = ipw_read32(priv, IPW_INTA_RW);
1724         inta_mask = ipw_read32(priv, IPW_INTA_MASK_R);
1725         inta &= (IPW_INTA_MASK_ALL & inta_mask);
1726
1727         /* Add any cached INTA values that need to be handled */
1728         inta |= priv->isr_inta;
1729
1730         /* handle all the justifications for the interrupt */
1731         if (inta & IPW_INTA_BIT_RX_TRANSFER) {
1732                 ipw_rx(priv);
1733                 handled |= IPW_INTA_BIT_RX_TRANSFER;
1734         }
1735
1736         if (inta & IPW_INTA_BIT_TX_CMD_QUEUE) {
1737                 IPW_DEBUG_HC("Command completed.\n");
1738                 rc = ipw_queue_tx_reclaim(priv, &priv->txq_cmd, -1);
1739                 priv->status &= ~STATUS_HCMD_ACTIVE;
1740                 wake_up_interruptible(&priv->wait_command_queue);
1741                 handled |= IPW_INTA_BIT_TX_CMD_QUEUE;
1742         }
1743
1744         if (inta & IPW_INTA_BIT_TX_QUEUE_1) {
1745                 IPW_DEBUG_TX("TX_QUEUE_1\n");
1746                 rc = ipw_queue_tx_reclaim(priv, &priv->txq[0], 0);
1747                 handled |= IPW_INTA_BIT_TX_QUEUE_1;
1748         }
1749
1750         if (inta & IPW_INTA_BIT_TX_QUEUE_2) {
1751                 IPW_DEBUG_TX("TX_QUEUE_2\n");
1752                 rc = ipw_queue_tx_reclaim(priv, &priv->txq[1], 1);
1753                 handled |= IPW_INTA_BIT_TX_QUEUE_2;
1754         }
1755
1756         if (inta & IPW_INTA_BIT_TX_QUEUE_3) {
1757                 IPW_DEBUG_TX("TX_QUEUE_3\n");
1758                 rc = ipw_queue_tx_reclaim(priv, &priv->txq[2], 2);
1759                 handled |= IPW_INTA_BIT_TX_QUEUE_3;
1760         }
1761
1762         if (inta & IPW_INTA_BIT_TX_QUEUE_4) {
1763                 IPW_DEBUG_TX("TX_QUEUE_4\n");
1764                 rc = ipw_queue_tx_reclaim(priv, &priv->txq[3], 3);
1765                 handled |= IPW_INTA_BIT_TX_QUEUE_4;
1766         }
1767
1768         if (inta & IPW_INTA_BIT_STATUS_CHANGE) {
1769                 IPW_WARNING("STATUS_CHANGE\n");
1770                 handled |= IPW_INTA_BIT_STATUS_CHANGE;
1771         }
1772
1773         if (inta & IPW_INTA_BIT_BEACON_PERIOD_EXPIRED) {
1774                 IPW_WARNING("TX_PERIOD_EXPIRED\n");
1775                 handled |= IPW_INTA_BIT_BEACON_PERIOD_EXPIRED;
1776         }
1777
1778         if (inta & IPW_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE) {
1779                 IPW_WARNING("HOST_CMD_DONE\n");
1780                 handled |= IPW_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE;
1781         }
1782
1783         if (inta & IPW_INTA_BIT_FW_INITIALIZATION_DONE) {
1784                 IPW_WARNING("FW_INITIALIZATION_DONE\n");
1785                 handled |= IPW_INTA_BIT_FW_INITIALIZATION_DONE;
1786         }
1787
1788         if (inta & IPW_INTA_BIT_FW_CARD_DISABLE_PHY_OFF_DONE) {
1789                 IPW_WARNING("PHY_OFF_DONE\n");
1790                 handled |= IPW_INTA_BIT_FW_CARD_DISABLE_PHY_OFF_DONE;
1791         }
1792
1793         if (inta & IPW_INTA_BIT_RF_KILL_DONE) {
1794                 IPW_DEBUG_RF_KILL("RF_KILL_DONE\n");
1795                 priv->status |= STATUS_RF_KILL_HW;
1796                 wake_up_interruptible(&priv->wait_command_queue);
1797                 priv->status &= ~(STATUS_ASSOCIATED | STATUS_ASSOCIATING);
1798                 cancel_delayed_work(&priv->request_scan);
1799                 schedule_work(&priv->link_down);
1800                 queue_delayed_work(priv->workqueue, &priv->rf_kill, 2 * HZ);
1801                 handled |= IPW_INTA_BIT_RF_KILL_DONE;
1802         }
1803
1804         if (inta & IPW_INTA_BIT_FATAL_ERROR) {
1805                 IPW_ERROR("Firmware error detected.  Restarting.\n");
1806                 if (priv->error) {
1807                         IPW_ERROR("Sysfs 'error' log already exists.\n");
1808 #ifdef CONFIG_IPW2200_DEBUG
1809                         if (ipw_debug_level & IPW_DL_FW_ERRORS) {
1810                                 struct ipw_fw_error *error =
1811                                     ipw_alloc_error_log(priv);
1812                                 ipw_dump_error_log(priv, error);
1813                                 if (error)
1814                                         ipw_free_error_log(error);
1815                         }
1816 #endif
1817                 } else {
1818                         priv->error = ipw_alloc_error_log(priv);
1819                         if (priv->error)
1820                                 IPW_ERROR("Sysfs 'error' log captured.\n");
1821                         else
1822                                 IPW_ERROR("Error allocating sysfs 'error' "
1823                                           "log.\n");
1824 #ifdef CONFIG_IPW2200_DEBUG
1825                         if (ipw_debug_level & IPW_DL_FW_ERRORS)
1826                                 ipw_dump_error_log(priv, priv->error);
1827 #endif
1828                 }
1829
1830                 /* XXX: If hardware encryption is for WPA/WPA2,
1831                  * we have to notify the supplicant. */
1832                 if (priv->ieee->sec.encrypt) {
1833                         priv->status &= ~STATUS_ASSOCIATED;
1834                         notify_wx_assoc_event(priv);
1835                 }
1836
1837                 /* Keep the restart process from trying to send host
1838                  * commands by clearing the INIT status bit */
1839                 priv->status &= ~STATUS_INIT;
1840
1841                 /* Cancel currently queued command. */
1842                 priv->status &= ~STATUS_HCMD_ACTIVE;
1843                 wake_up_interruptible(&priv->wait_command_queue);
1844
1845                 queue_work(priv->workqueue, &priv->adapter_restart);
1846                 handled |= IPW_INTA_BIT_FATAL_ERROR;
1847         }
1848
1849         if (inta & IPW_INTA_BIT_PARITY_ERROR) {
1850                 IPW_ERROR("Parity error\n");
1851                 handled |= IPW_INTA_BIT_PARITY_ERROR;
1852         }
1853
1854         if (handled != inta) {
1855                 IPW_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
1856         }
1857
1858         /* enable all interrupts */
1859         ipw_enable_interrupts(priv);
1860
1861         spin_unlock_irqrestore(&priv->lock, flags);
1862 }
1863
1864 #define IPW_CMD(x) case IPW_CMD_ ## x : return #x
1865 static char *get_cmd_string(u8 cmd)
1866 {
1867         switch (cmd) {
1868                 IPW_CMD(HOST_COMPLETE);
1869                 IPW_CMD(POWER_DOWN);
1870                 IPW_CMD(SYSTEM_CONFIG);
1871                 IPW_CMD(MULTICAST_ADDRESS);
1872                 IPW_CMD(SSID);
1873                 IPW_CMD(ADAPTER_ADDRESS);
1874                 IPW_CMD(PORT_TYPE);
1875                 IPW_CMD(RTS_THRESHOLD);
1876                 IPW_CMD(FRAG_THRESHOLD);
1877                 IPW_CMD(POWER_MODE);
1878                 IPW_CMD(WEP_KEY);
1879                 IPW_CMD(TGI_TX_KEY);
1880                 IPW_CMD(SCAN_REQUEST);
1881                 IPW_CMD(SCAN_REQUEST_EXT);
1882                 IPW_CMD(ASSOCIATE);
1883                 IPW_CMD(SUPPORTED_RATES);
1884                 IPW_CMD(SCAN_ABORT);
1885                 IPW_CMD(TX_FLUSH);
1886                 IPW_CMD(QOS_PARAMETERS);
1887                 IPW_CMD(DINO_CONFIG);
1888                 IPW_CMD(RSN_CAPABILITIES);
1889                 IPW_CMD(RX_KEY);
1890                 IPW_CMD(CARD_DISABLE);
1891                 IPW_CMD(SEED_NUMBER);
1892                 IPW_CMD(TX_POWER);
1893                 IPW_CMD(COUNTRY_INFO);
1894                 IPW_CMD(AIRONET_INFO);
1895                 IPW_CMD(AP_TX_POWER);
1896                 IPW_CMD(CCKM_INFO);
1897                 IPW_CMD(CCX_VER_INFO);
1898                 IPW_CMD(SET_CALIBRATION);
1899                 IPW_CMD(SENSITIVITY_CALIB);
1900                 IPW_CMD(RETRY_LIMIT);
1901                 IPW_CMD(IPW_PRE_POWER_DOWN);
1902                 IPW_CMD(VAP_BEACON_TEMPLATE);
1903                 IPW_CMD(VAP_DTIM_PERIOD);
1904                 IPW_CMD(EXT_SUPPORTED_RATES);
1905                 IPW_CMD(VAP_LOCAL_TX_PWR_CONSTRAINT);
1906                 IPW_CMD(VAP_QUIET_INTERVALS);
1907                 IPW_CMD(VAP_CHANNEL_SWITCH);
1908                 IPW_CMD(VAP_MANDATORY_CHANNELS);
1909                 IPW_CMD(VAP_CELL_PWR_LIMIT);
1910                 IPW_CMD(VAP_CF_PARAM_SET);
1911                 IPW_CMD(VAP_SET_BEACONING_STATE);
1912                 IPW_CMD(MEASUREMENT);
1913                 IPW_CMD(POWER_CAPABILITY);
1914                 IPW_CMD(SUPPORTED_CHANNELS);
1915                 IPW_CMD(TPC_REPORT);
1916                 IPW_CMD(WME_INFO);
1917                 IPW_CMD(PRODUCTION_COMMAND);
1918         default:
1919                 return "UNKNOWN";
1920         }
1921 }
1922
1923 #define HOST_COMPLETE_TIMEOUT HZ
1924
1925 static int __ipw_send_cmd(struct ipw_priv *priv, struct host_cmd *cmd)
1926 {
1927         int rc = 0;
1928         unsigned long flags;
1929
1930         spin_lock_irqsave(&priv->lock, flags);
1931         if (priv->status & STATUS_HCMD_ACTIVE) {
1932                 IPW_ERROR("Failed to send %s: Already sending a command.\n",
1933                           get_cmd_string(cmd->cmd));
1934                 spin_unlock_irqrestore(&priv->lock, flags);
1935                 return -EAGAIN;
1936         }
1937
1938         priv->status |= STATUS_HCMD_ACTIVE;
1939
1940         if (priv->cmdlog) {
1941                 priv->cmdlog[priv->cmdlog_pos].jiffies = jiffies;
1942                 priv->cmdlog[priv->cmdlog_pos].cmd.cmd = cmd->cmd;
1943                 priv->cmdlog[priv->cmdlog_pos].cmd.len = cmd->len;
1944                 memcpy(priv->cmdlog[priv->cmdlog_pos].cmd.param, cmd->param,
1945                        cmd->len);
1946                 priv->cmdlog[priv->cmdlog_pos].retcode = -1;
1947         }
1948
1949         IPW_DEBUG_HC("%s command (#%d) %d bytes: 0x%08X\n",
1950                      get_cmd_string(cmd->cmd), cmd->cmd, cmd->len,
1951                      priv->status);
1952
1953 #ifndef DEBUG_CMD_WEP_KEY
1954         if (cmd->cmd == IPW_CMD_WEP_KEY)
1955                 IPW_DEBUG_HC("WEP_KEY command masked out for secure.\n");
1956         else
1957 #endif
1958                 printk_buf(IPW_DL_HOST_COMMAND, (u8 *) cmd->param, cmd->len);
1959
1960         rc = ipw_queue_tx_hcmd(priv, cmd->cmd, cmd->param, cmd->len, 0);
1961         if (rc) {
1962                 priv->status &= ~STATUS_HCMD_ACTIVE;
1963                 IPW_ERROR("Failed to send %s: Reason %d\n",
1964                           get_cmd_string(cmd->cmd), rc);
1965                 spin_unlock_irqrestore(&priv->lock, flags);
1966                 goto exit;
1967         }
1968         spin_unlock_irqrestore(&priv->lock, flags);
1969
1970         rc = wait_event_interruptible_timeout(priv->wait_command_queue,
1971                                               !(priv->
1972                                                 status & STATUS_HCMD_ACTIVE),
1973                                               HOST_COMPLETE_TIMEOUT);
1974         if (rc == 0) {
1975                 spin_lock_irqsave(&priv->lock, flags);
1976                 if (priv->status & STATUS_HCMD_ACTIVE) {
1977                         IPW_ERROR("Failed to send %s: Command timed out.\n",
1978                                   get_cmd_string(cmd->cmd));
1979                         priv->status &= ~STATUS_HCMD_ACTIVE;
1980                         spin_unlock_irqrestore(&priv->lock, flags);
1981                         rc = -EIO;
1982                         goto exit;
1983                 }
1984                 spin_unlock_irqrestore(&priv->lock, flags);
1985         } else
1986                 rc = 0;
1987
1988         if (priv->status & STATUS_RF_KILL_HW) {
1989                 IPW_ERROR("Failed to send %s: Aborted due to RF kill switch.\n",
1990                           get_cmd_string(cmd->cmd));
1991                 rc = -EIO;
1992                 goto exit;
1993         }
1994
1995       exit:
1996         if (priv->cmdlog) {
1997                 priv->cmdlog[priv->cmdlog_pos++].retcode = rc;
1998                 priv->cmdlog_pos %= priv->cmdlog_len;
1999         }
2000         return rc;
2001 }
2002
2003 static int ipw_send_cmd_simple(struct ipw_priv *priv, u8 command)
2004 {
2005         struct host_cmd cmd = {
2006                 .cmd = command,
2007         };
2008
2009         return __ipw_send_cmd(priv, &cmd);
2010 }
2011
2012 static int ipw_send_cmd_pdu(struct ipw_priv *priv, u8 command, u8 len,
2013                             void *data)
2014 {
2015         struct host_cmd cmd = {
2016                 .cmd = command,
2017                 .len = len,
2018                 .param = data,
2019         };
2020
2021         return __ipw_send_cmd(priv, &cmd);
2022 }
2023
2024 static int ipw_send_host_complete(struct ipw_priv *priv)
2025 {
2026         if (!priv) {
2027                 IPW_ERROR("Invalid args\n");
2028                 return -1;
2029         }
2030
2031         return ipw_send_cmd_simple(priv, IPW_CMD_HOST_COMPLETE);
2032 }
2033
2034 static int ipw_send_system_config(struct ipw_priv *priv,
2035                                   struct ipw_sys_config *config)
2036 {
2037         if (!priv || !config) {
2038                 IPW_ERROR("Invalid args\n");
2039                 return -1;
2040         }
2041
2042         return ipw_send_cmd_pdu(priv, IPW_CMD_SYSTEM_CONFIG, sizeof(*config),
2043                                 config);
2044 }
2045
2046 static int ipw_send_ssid(struct ipw_priv *priv, u8 * ssid, int len)
2047 {
2048         if (!priv || !ssid) {
2049                 IPW_ERROR("Invalid args\n");
2050                 return -1;
2051         }
2052
2053         return ipw_send_cmd_pdu(priv, IPW_CMD_SSID, min(len, IW_ESSID_MAX_SIZE),
2054                                 ssid);
2055 }
2056
2057 static int ipw_send_adapter_address(struct ipw_priv *priv, u8 * mac)
2058 {
2059         if (!priv || !mac) {
2060                 IPW_ERROR("Invalid args\n");
2061                 return -1;
2062         }
2063
2064         IPW_DEBUG_INFO("%s: Setting MAC to " MAC_FMT "\n",
2065                        priv->net_dev->name, MAC_ARG(mac));
2066
2067         return ipw_send_cmd_pdu(priv, IPW_CMD_ADAPTER_ADDRESS, ETH_ALEN, mac);
2068 }
2069
2070 /*
2071  * NOTE: This must be executed from our workqueue as it results in udelay
2072  * being called which may corrupt the keyboard if executed on default
2073  * workqueue
2074  */
2075 static void ipw_adapter_restart(void *adapter)
2076 {
2077         struct ipw_priv *priv = adapter;
2078
2079         if (priv->status & STATUS_RF_KILL_MASK)
2080                 return;
2081
2082         ipw_down(priv);
2083
2084         if (priv->assoc_network &&
2085             (priv->assoc_network->capability & WLAN_CAPABILITY_IBSS))
2086                 ipw_remove_current_network(priv);
2087
2088         if (ipw_up(priv)) {
2089                 IPW_ERROR("Failed to up device\n");
2090                 return;
2091         }
2092 }
2093
2094 static void ipw_bg_adapter_restart(void *data)
2095 {
2096         struct ipw_priv *priv = data;
2097         mutex_lock(&priv->mutex);
2098         ipw_adapter_restart(data);
2099         mutex_unlock(&priv->mutex);
2100 }
2101
2102 #define IPW_SCAN_CHECK_WATCHDOG (5 * HZ)
2103
2104 static void ipw_scan_check(void *data)
2105 {
2106         struct ipw_priv *priv = data;
2107         if (priv->status & (STATUS_SCANNING | STATUS_SCAN_ABORTING)) {
2108                 IPW_DEBUG_SCAN("Scan completion watchdog resetting "
2109                                "adapter after (%dms).\n",
2110                                jiffies_to_msecs(IPW_SCAN_CHECK_WATCHDOG));
2111                 queue_work(priv->workqueue, &priv->adapter_restart);
2112         }
2113 }
2114
2115 static void ipw_bg_scan_check(void *data)
2116 {
2117         struct ipw_priv *priv = data;
2118         mutex_lock(&priv->mutex);
2119         ipw_scan_check(data);
2120         mutex_unlock(&priv->mutex);
2121 }
2122
2123 static int ipw_send_scan_request_ext(struct ipw_priv *priv,
2124                                      struct ipw_scan_request_ext *request)
2125 {
2126         return ipw_send_cmd_pdu(priv, IPW_CMD_SCAN_REQUEST_EXT,
2127                                 sizeof(*request), request);
2128 }
2129
2130 static int ipw_send_scan_abort(struct ipw_priv *priv)
2131 {
2132         if (!priv) {
2133                 IPW_ERROR("Invalid args\n");
2134                 return -1;
2135         }
2136
2137         return ipw_send_cmd_simple(priv, IPW_CMD_SCAN_ABORT);
2138 }
2139
2140 static int ipw_set_sensitivity(struct ipw_priv *priv, u16 sens)
2141 {
2142         struct ipw_sensitivity_calib calib = {
2143                 .beacon_rssi_raw = sens,
2144         };
2145
2146         return ipw_send_cmd_pdu(priv, IPW_CMD_SENSITIVITY_CALIB, sizeof(calib),
2147                                 &calib);
2148 }
2149
2150 static int ipw_send_associate(struct ipw_priv *priv,
2151                               struct ipw_associate *associate)
2152 {
2153         struct ipw_associate tmp_associate;
2154
2155         if (!priv || !associate) {
2156                 IPW_ERROR("Invalid args\n");
2157                 return -1;
2158         }
2159
2160         memcpy(&tmp_associate, associate, sizeof(*associate));
2161         tmp_associate.policy_support =
2162             cpu_to_le16(tmp_associate.policy_support);
2163         tmp_associate.assoc_tsf_msw = cpu_to_le32(tmp_associate.assoc_tsf_msw);
2164         tmp_associate.assoc_tsf_lsw = cpu_to_le32(tmp_associate.assoc_tsf_lsw);
2165         tmp_associate.capability = cpu_to_le16(tmp_associate.capability);
2166         tmp_associate.listen_interval =
2167             cpu_to_le16(tmp_associate.listen_interval);
2168         tmp_associate.beacon_interval =
2169             cpu_to_le16(tmp_associate.beacon_interval);
2170         tmp_associate.atim_window = cpu_to_le16(tmp_associate.atim_window);
2171
2172         return ipw_send_cmd_pdu(priv, IPW_CMD_ASSOCIATE, sizeof(tmp_associate),
2173                                 &tmp_associate);
2174 }
2175
2176 static int ipw_send_supported_rates(struct ipw_priv *priv,
2177                                     struct ipw_supported_rates *rates)
2178 {
2179         if (!priv || !rates) {
2180                 IPW_ERROR("Invalid args\n");
2181                 return -1;
2182         }
2183
2184         return ipw_send_cmd_pdu(priv, IPW_CMD_SUPPORTED_RATES, sizeof(*rates),
2185                                 rates);
2186 }
2187
2188 static int ipw_set_random_seed(struct ipw_priv *priv)
2189 {
2190         u32 val;
2191
2192         if (!priv) {
2193                 IPW_ERROR("Invalid args\n");
2194                 return -1;
2195         }
2196
2197         get_random_bytes(&val, sizeof(val));
2198
2199         return ipw_send_cmd_pdu(priv, IPW_CMD_SEED_NUMBER, sizeof(val), &val);
2200 }
2201
2202 static int ipw_send_card_disable(struct ipw_priv *priv, u32 phy_off)
2203 {
2204         if (!priv) {
2205                 IPW_ERROR("Invalid args\n");
2206                 return -1;
2207         }
2208
2209         return ipw_send_cmd_pdu(priv, IPW_CMD_CARD_DISABLE, sizeof(phy_off),
2210                                 &phy_off);
2211 }
2212
2213 static int ipw_send_tx_power(struct ipw_priv *priv, struct ipw_tx_power *power)
2214 {
2215         if (!priv || !power) {
2216                 IPW_ERROR("Invalid args\n");
2217                 return -1;
2218         }
2219
2220         return ipw_send_cmd_pdu(priv, IPW_CMD_TX_POWER, sizeof(*power), power);
2221 }
2222
2223 static int ipw_set_tx_power(struct ipw_priv *priv)
2224 {
2225         const struct ieee80211_geo *geo = ipw_get_geo(priv->ieee);
2226         struct ipw_tx_power tx_power;
2227         s8 max_power;
2228         int i;
2229
2230         memset(&tx_power, 0, sizeof(tx_power));
2231
2232         /* configure device for 'G' band */
2233         tx_power.ieee_mode = IPW_G_MODE;
2234         tx_power.num_channels = geo->bg_channels;
2235         for (i = 0; i < geo->bg_channels; i++) {
2236                 max_power = geo->bg[i].max_power;
2237                 tx_power.channels_tx_power[i].channel_number =
2238                     geo->bg[i].channel;
2239                 tx_power.channels_tx_power[i].tx_power = max_power ?
2240                     min(max_power, priv->tx_power) : priv->tx_power;
2241         }
2242         if (ipw_send_tx_power(priv, &tx_power))
2243                 return -EIO;
2244
2245         /* configure device to also handle 'B' band */
2246         tx_power.ieee_mode = IPW_B_MODE;
2247         if (ipw_send_tx_power(priv, &tx_power))
2248                 return -EIO;
2249
2250         /* configure device to also handle 'A' band */
2251         if (priv->ieee->abg_true) {
2252                 tx_power.ieee_mode = IPW_A_MODE;
2253                 tx_power.num_channels = geo->a_channels;
2254                 for (i = 0; i < tx_power.num_channels; i++) {
2255                         max_power = geo->a[i].max_power;
2256                         tx_power.channels_tx_power[i].channel_number =
2257                             geo->a[i].channel;
2258                         tx_power.channels_tx_power[i].tx_power = max_power ?
2259                             min(max_power, priv->tx_power) : priv->tx_power;
2260                 }
2261                 if (ipw_send_tx_power(priv, &tx_power))
2262                         return -EIO;
2263         }
2264         return 0;
2265 }
2266
2267 static int ipw_send_rts_threshold(struct ipw_priv *priv, u16 rts)
2268 {
2269         struct ipw_rts_threshold rts_threshold = {
2270                 .rts_threshold = rts,
2271         };
2272
2273         if (!priv) {
2274                 IPW_ERROR("Invalid args\n");
2275                 return -1;
2276         }
2277
2278         return ipw_send_cmd_pdu(priv, IPW_CMD_RTS_THRESHOLD,
2279                                 sizeof(rts_threshold), &rts_threshold);
2280 }
2281
2282 static int ipw_send_frag_threshold(struct ipw_priv *priv, u16 frag)
2283 {
2284         struct ipw_frag_threshold frag_threshold = {
2285                 .frag_threshold = frag,
2286         };
2287
2288         if (!priv) {
2289                 IPW_ERROR("Invalid args\n");
2290                 return -1;
2291         }
2292
2293         return ipw_send_cmd_pdu(priv, IPW_CMD_FRAG_THRESHOLD,
2294                                 sizeof(frag_threshold), &frag_threshold);
2295 }
2296
2297 static int ipw_send_power_mode(struct ipw_priv *priv, u32 mode)
2298 {
2299         u32 param;
2300
2301         if (!priv) {
2302                 IPW_ERROR("Invalid args\n");
2303                 return -1;
2304         }
2305
2306         /* If on battery, set to 3, if AC set to CAM, else user
2307          * level */
2308         switch (mode) {
2309         case IPW_POWER_BATTERY:
2310                 param = IPW_POWER_INDEX_3;
2311                 break;
2312         case IPW_POWER_AC:
2313                 param = IPW_POWER_MODE_CAM;
2314                 break;
2315         default:
2316                 param = mode;
2317                 break;
2318         }
2319
2320         return ipw_send_cmd_pdu(priv, IPW_CMD_POWER_MODE, sizeof(param),
2321                                 &param);
2322 }
2323
2324 static int ipw_send_retry_limit(struct ipw_priv *priv, u8 slimit, u8 llimit)
2325 {
2326         struct ipw_retry_limit retry_limit = {
2327                 .short_retry_limit = slimit,
2328                 .long_retry_limit = llimit
2329         };
2330
2331         if (!priv) {
2332                 IPW_ERROR("Invalid args\n");
2333                 return -1;
2334         }
2335
2336         return ipw_send_cmd_pdu(priv, IPW_CMD_RETRY_LIMIT, sizeof(retry_limit),
2337                                 &retry_limit);
2338 }
2339
2340 /*
2341  * The IPW device contains a Microwire compatible EEPROM that stores
2342  * various data like the MAC address.  Usually the firmware has exclusive
2343  * access to the eeprom, but during device initialization (before the
2344  * device driver has sent the HostComplete command to the firmware) the
2345  * device driver has read access to the EEPROM by way of indirect addressing
2346  * through a couple of memory mapped registers.
2347  *
2348  * The following is a simplified implementation for pulling data out of the
2349  * the eeprom, along with some helper functions to find information in
2350  * the per device private data's copy of the eeprom.
2351  *
2352  * NOTE: To better understand how these functions work (i.e what is a chip
2353  *       select and why do have to keep driving the eeprom clock?), read
2354  *       just about any data sheet for a Microwire compatible EEPROM.
2355  */
2356
2357 /* write a 32 bit value into the indirect accessor register */
2358 static inline void eeprom_write_reg(struct ipw_priv *p, u32 data)
2359 {
2360         ipw_write_reg32(p, FW_MEM_REG_EEPROM_ACCESS, data);
2361
2362         /* the eeprom requires some time to complete the operation */
2363         udelay(p->eeprom_delay);
2364
2365         return;
2366 }
2367
2368 /* perform a chip select operation */
2369 static void eeprom_cs(struct ipw_priv *priv)
2370 {
2371         eeprom_write_reg(priv, 0);
2372         eeprom_write_reg(priv, EEPROM_BIT_CS);
2373         eeprom_write_reg(priv, EEPROM_BIT_CS | EEPROM_BIT_SK);
2374         eeprom_write_reg(priv, EEPROM_BIT_CS);
2375 }
2376
2377 /* perform a chip select operation */
2378 static void eeprom_disable_cs(struct ipw_priv *priv)
2379 {
2380         eeprom_write_reg(priv, EEPROM_BIT_CS);
2381         eeprom_write_reg(priv, 0);
2382         eeprom_write_reg(priv, EEPROM_BIT_SK);
2383 }
2384
2385 /* push a single bit down to the eeprom */
2386 static inline void eeprom_write_bit(struct ipw_priv *p, u8 bit)
2387 {
2388         int d = (bit ? EEPROM_BIT_DI : 0);
2389         eeprom_write_reg(p, EEPROM_BIT_CS | d);
2390         eeprom_write_reg(p, EEPROM_BIT_CS | d | EEPROM_BIT_SK);
2391 }
2392
2393 /* push an opcode followed by an address down to the eeprom */
2394 static void eeprom_op(struct ipw_priv *priv, u8 op, u8 addr)
2395 {
2396         int i;
2397
2398         eeprom_cs(priv);
2399         eeprom_write_bit(priv, 1);
2400         eeprom_write_bit(priv, op & 2);
2401         eeprom_write_bit(priv, op & 1);
2402         for (i = 7; i >= 0; i--) {
2403                 eeprom_write_bit(priv, addr & (1 << i));
2404         }
2405 }
2406
2407 /* pull 16 bits off the eeprom, one bit at a time */
2408 static u16 eeprom_read_u16(struct ipw_priv *priv, u8 addr)
2409 {
2410         int i;
2411         u16 r = 0;
2412
2413         /* Send READ Opcode */
2414         eeprom_op(priv, EEPROM_CMD_READ, addr);
2415
2416         /* Send dummy bit */
2417         eeprom_write_reg(priv, EEPROM_BIT_CS);
2418
2419         /* Read the byte off the eeprom one bit at a time */
2420         for (i = 0; i < 16; i++) {
2421                 u32 data = 0;
2422                 eeprom_write_reg(priv, EEPROM_BIT_CS | EEPROM_BIT_SK);
2423                 eeprom_write_reg(priv, EEPROM_BIT_CS);
2424                 data = ipw_read_reg32(priv, FW_MEM_REG_EEPROM_ACCESS);
2425                 r = (r << 1) | ((data & EEPROM_BIT_DO) ? 1 : 0);
2426         }
2427
2428         /* Send another dummy bit */
2429         eeprom_write_reg(priv, 0);
2430         eeprom_disable_cs(priv);
2431
2432         return r;
2433 }
2434
2435 /* helper function for pulling the mac address out of the private */
2436 /* data's copy of the eeprom data                                 */
2437 static void eeprom_parse_mac(struct ipw_priv *priv, u8 * mac)
2438 {
2439         memcpy(mac, &priv->eeprom[EEPROM_MAC_ADDRESS], 6);
2440 }
2441
2442 /*
2443  * Either the device driver (i.e. the host) or the firmware can
2444  * load eeprom data into the designated region in SRAM.  If neither
2445  * happens then the FW will shutdown with a fatal error.
2446  *
2447  * In order to signal the FW to load the EEPROM, the EEPROM_LOAD_DISABLE
2448  * bit needs region of shared SRAM needs to be non-zero.
2449  */
2450 static void ipw_eeprom_init_sram(struct ipw_priv *priv)
2451 {
2452         int i;
2453         u16 *eeprom = (u16 *) priv->eeprom;
2454
2455         IPW_DEBUG_TRACE(">>\n");
2456
2457         /* read entire contents of eeprom into private buffer */
2458         for (i = 0; i < 128; i++)
2459                 eeprom[i] = le16_to_cpu(eeprom_read_u16(priv, (u8) i));
2460
2461         /*
2462            If the data looks correct, then copy it to our private
2463            copy.  Otherwise let the firmware know to perform the operation
2464            on its own.
2465          */
2466         if (priv->eeprom[EEPROM_VERSION] != 0) {
2467                 IPW_DEBUG_INFO("Writing EEPROM data into SRAM\n");
2468
2469                 /* write the eeprom data to sram */
2470                 for (i = 0; i < IPW_EEPROM_IMAGE_SIZE; i++)
2471                         ipw_write8(priv, IPW_EEPROM_DATA + i, priv->eeprom[i]);
2472
2473                 /* Do not load eeprom data on fatal error or suspend */
2474                 ipw_write32(priv, IPW_EEPROM_LOAD_DISABLE, 0);
2475         } else {
2476                 IPW_DEBUG_INFO("Enabling FW initializationg of SRAM\n");
2477
2478                 /* Load eeprom data on fatal error or suspend */
2479                 ipw_write32(priv, IPW_EEPROM_LOAD_DISABLE, 1);
2480         }
2481
2482         IPW_DEBUG_TRACE("<<\n");
2483 }
2484
2485 static void ipw_zero_memory(struct ipw_priv *priv, u32 start, u32 count)
2486 {
2487         count >>= 2;
2488         if (!count)
2489                 return;
2490         _ipw_write32(priv, IPW_AUTOINC_ADDR, start);
2491         while (count--)
2492                 _ipw_write32(priv, IPW_AUTOINC_DATA, 0);
2493 }
2494
2495 static inline void ipw_fw_dma_reset_command_blocks(struct ipw_priv *priv)
2496 {
2497         ipw_zero_memory(priv, IPW_SHARED_SRAM_DMA_CONTROL,
2498                         CB_NUMBER_OF_ELEMENTS_SMALL *
2499                         sizeof(struct command_block));
2500 }
2501
2502 static int ipw_fw_dma_enable(struct ipw_priv *priv)
2503 {                               /* start dma engine but no transfers yet */
2504
2505         IPW_DEBUG_FW(">> : \n");
2506
2507         /* Start the dma */
2508         ipw_fw_dma_reset_command_blocks(priv);
2509
2510         /* Write CB base address */
2511         ipw_write_reg32(priv, IPW_DMA_I_CB_BASE, IPW_SHARED_SRAM_DMA_CONTROL);
2512
2513         IPW_DEBUG_FW("<< : \n");
2514         return 0;
2515 }
2516
2517 static void ipw_fw_dma_abort(struct ipw_priv *priv)
2518 {
2519         u32 control = 0;
2520
2521         IPW_DEBUG_FW(">> :\n");
2522
2523         //set the Stop and Abort bit
2524         control = DMA_CONTROL_SMALL_CB_CONST_VALUE | DMA_CB_STOP_AND_ABORT;
2525         ipw_write_reg32(priv, IPW_DMA_I_DMA_CONTROL, control);
2526         priv->sram_desc.last_cb_index = 0;
2527
2528         IPW_DEBUG_FW("<< \n");
2529 }
2530
2531 static int ipw_fw_dma_write_command_block(struct ipw_priv *priv, int index,
2532                                           struct command_block *cb)
2533 {
2534         u32 address =
2535             IPW_SHARED_SRAM_DMA_CONTROL +
2536             (sizeof(struct command_block) * index);
2537         IPW_DEBUG_FW(">> :\n");
2538
2539         ipw_write_indirect(priv, address, (u8 *) cb,
2540                            (int)sizeof(struct command_block));
2541
2542         IPW_DEBUG_FW("<< :\n");
2543         return 0;
2544
2545 }
2546
2547 static int ipw_fw_dma_kick(struct ipw_priv *priv)
2548 {
2549         u32 control = 0;
2550         u32 index = 0;
2551
2552         IPW_DEBUG_FW(">> :\n");
2553
2554         for (index = 0; index < priv->sram_desc.last_cb_index; index++)
2555                 ipw_fw_dma_write_command_block(priv, index,
2556                                                &priv->sram_desc.cb_list[index]);
2557
2558         /* Enable the DMA in the CSR register */
2559         ipw_clear_bit(priv, IPW_RESET_REG,
2560                       IPW_RESET_REG_MASTER_DISABLED |
2561                       IPW_RESET_REG_STOP_MASTER);
2562
2563         /* Set the Start bit. */
2564         control = DMA_CONTROL_SMALL_CB_CONST_VALUE | DMA_CB_START;
2565         ipw_write_reg32(priv, IPW_DMA_I_DMA_CONTROL, control);
2566
2567         IPW_DEBUG_FW("<< :\n");
2568         return 0;
2569 }
2570
2571 static void ipw_fw_dma_dump_command_block(struct ipw_priv *priv)
2572 {
2573         u32 address;
2574         u32 register_value = 0;
2575         u32 cb_fields_address = 0;
2576
2577         IPW_DEBUG_FW(">> :\n");
2578         address = ipw_read_reg32(priv, IPW_DMA_I_CURRENT_CB);
2579         IPW_DEBUG_FW_INFO("Current CB is 0x%x \n", address);
2580
2581         /* Read the DMA Controlor register */
2582         register_value = ipw_read_reg32(priv, IPW_DMA_I_DMA_CONTROL);
2583         IPW_DEBUG_FW_INFO("IPW_DMA_I_DMA_CONTROL is 0x%x \n", register_value);
2584
2585         /* Print the CB values */
2586         cb_fields_address = address;
2587         register_value = ipw_read_reg32(priv, cb_fields_address);
2588         IPW_DEBUG_FW_INFO("Current CB ControlField is 0x%x \n", register_value);
2589
2590         cb_fields_address += sizeof(u32);
2591         register_value = ipw_read_reg32(priv, cb_fields_address);
2592         IPW_DEBUG_FW_INFO("Current CB Source Field is 0x%x \n", register_value);
2593
2594         cb_fields_address += sizeof(u32);
2595         register_value = ipw_read_reg32(priv, cb_fields_address);
2596         IPW_DEBUG_FW_INFO("Current CB Destination Field is 0x%x \n",
2597                           register_value);
2598
2599         cb_fields_address += sizeof(u32);
2600         register_value = ipw_read_reg32(priv, cb_fields_address);
2601         IPW_DEBUG_FW_INFO("Current CB Status Field is 0x%x \n", register_value);
2602
2603         IPW_DEBUG_FW(">> :\n");
2604 }
2605
2606 static int ipw_fw_dma_command_block_index(struct ipw_priv *priv)
2607 {
2608         u32 current_cb_address = 0;
2609         u32 current_cb_index = 0;
2610
2611         IPW_DEBUG_FW("<< :\n");
2612         current_cb_address = ipw_read_reg32(priv, IPW_DMA_I_CURRENT_CB);
2613
2614         current_cb_index = (current_cb_address - IPW_SHARED_SRAM_DMA_CONTROL) /
2615             sizeof(struct command_block);
2616
2617         IPW_DEBUG_FW_INFO("Current CB index 0x%x address = 0x%X \n",
2618                           current_cb_index, current_cb_address);
2619
2620         IPW_DEBUG_FW(">> :\n");
2621         return current_cb_index;
2622
2623 }
2624
2625 static int ipw_fw_dma_add_command_block(struct ipw_priv *priv,
2626                                         u32 src_address,
2627                                         u32 dest_address,
2628                                         u32 length,
2629                                         int interrupt_enabled, int is_last)
2630 {
2631
2632         u32 control = CB_VALID | CB_SRC_LE | CB_DEST_LE | CB_SRC_AUTOINC |
2633             CB_SRC_IO_GATED | CB_DEST_AUTOINC | CB_SRC_SIZE_LONG |
2634             CB_DEST_SIZE_LONG;
2635         struct command_block *cb;
2636         u32 last_cb_element = 0;
2637
2638         IPW_DEBUG_FW_INFO("src_address=0x%x dest_address=0x%x length=0x%x\n",
2639                           src_address, dest_address, length);
2640
2641         if (priv->sram_desc.last_cb_index >= CB_NUMBER_OF_ELEMENTS_SMALL)
2642                 return -1;
2643
2644         last_cb_element = priv->sram_desc.last_cb_index;
2645         cb = &priv->sram_desc.cb_list[last_cb_element];
2646         priv->sram_desc.last_cb_index++;
2647
2648         /* Calculate the new CB control word */
2649         if (interrupt_enabled)
2650                 control |= CB_INT_ENABLED;
2651
2652         if (is_last)
2653                 control |= CB_LAST_VALID;
2654
2655         control |= length;
2656
2657         /* Calculate the CB Element's checksum value */
2658         cb->status = control ^ src_address ^ dest_address;
2659
2660         /* Copy the Source and Destination addresses */
2661         cb->dest_addr = dest_address;
2662         cb->source_addr = src_address;
2663
2664         /* Copy the Control Word last */
2665         cb->control = control;
2666
2667         return 0;
2668 }
2669
2670 static int ipw_fw_dma_add_buffer(struct ipw_priv *priv,
2671                                  u32 src_phys, u32 dest_address, u32 length)
2672 {
2673         u32 bytes_left = length;
2674         u32 src_offset = 0;
2675         u32 dest_offset = 0;
2676         int status = 0;
2677         IPW_DEBUG_FW(">> \n");
2678         IPW_DEBUG_FW_INFO("src_phys=0x%x dest_address=0x%x length=0x%x\n",
2679                           src_phys, dest_address, length);
2680         while (bytes_left > CB_MAX_LENGTH) {
2681                 status = ipw_fw_dma_add_command_block(priv,
2682                                                       src_phys + src_offset,
2683                                                       dest_address +
2684                                                       dest_offset,
2685                                                       CB_MAX_LENGTH, 0, 0);
2686                 if (status) {
2687                         IPW_DEBUG_FW_INFO(": Failed\n");
2688                         return -1;
2689                 } else
2690                         IPW_DEBUG_FW_INFO(": Added new cb\n");
2691
2692                 src_offset += CB_MAX_LENGTH;
2693                 dest_offset += CB_MAX_LENGTH;
2694                 bytes_left -= CB_MAX_LENGTH;
2695         }
2696
2697         /* add the buffer tail */
2698         if (bytes_left > 0) {
2699                 status =
2700                     ipw_fw_dma_add_command_block(priv, src_phys + src_offset,
2701                                                  dest_address + dest_offset,
2702                                                  bytes_left, 0, 0);
2703                 if (status) {
2704                         IPW_DEBUG_FW_INFO(": Failed on the buffer tail\n");
2705                         return -1;
2706                 } else
2707                         IPW_DEBUG_FW_INFO
2708                             (": Adding new cb - the buffer tail\n");
2709         }
2710
2711         IPW_DEBUG_FW("<< \n");
2712         return 0;
2713 }
2714
2715 static int ipw_fw_dma_wait(struct ipw_priv *priv)
2716 {
2717         u32 current_index = 0, previous_index;
2718         u32 watchdog = 0;
2719
2720         IPW_DEBUG_FW(">> : \n");
2721
2722         current_index = ipw_fw_dma_command_block_index(priv);
2723         IPW_DEBUG_FW_INFO("sram_desc.last_cb_index:0x%08X\n",
2724                           (int)priv->sram_desc.last_cb_index);
2725
2726         while (current_index < priv->sram_desc.last_cb_index) {
2727                 udelay(50);
2728                 previous_index = current_index;
2729                 current_index = ipw_fw_dma_command_block_index(priv);
2730
2731                 if (previous_index < current_index) {
2732                         watchdog = 0;
2733                         continue;
2734                 }
2735                 if (++watchdog > 400) {
2736                         IPW_DEBUG_FW_INFO("Timeout\n");
2737                         ipw_fw_dma_dump_command_block(priv);
2738                         ipw_fw_dma_abort(priv);
2739                         return -1;
2740                 }
2741         }
2742
2743         ipw_fw_dma_abort(priv);
2744
2745         /*Disable the DMA in the CSR register */
2746         ipw_set_bit(priv, IPW_RESET_REG,
2747                     IPW_RESET_REG_MASTER_DISABLED | IPW_RESET_REG_STOP_MASTER);
2748
2749         IPW_DEBUG_FW("<< dmaWaitSync \n");
2750         return 0;
2751 }
2752
2753 static void ipw_remove_current_network(struct ipw_priv *priv)
2754 {
2755         struct list_head *element, *safe;
2756         struct ieee80211_network *network = NULL;
2757         unsigned long flags;
2758
2759         spin_lock_irqsave(&priv->ieee->lock, flags);
2760         list_for_each_safe(element, safe, &priv->ieee->network_list) {
2761                 network = list_entry(element, struct ieee80211_network, list);
2762                 if (!memcmp(network->bssid, priv->bssid, ETH_ALEN)) {
2763                         list_del(element);
2764                         list_add_tail(&network->list,
2765                                       &priv->ieee->network_free_list);
2766                 }
2767         }
2768         spin_unlock_irqrestore(&priv->ieee->lock, flags);
2769 }
2770
2771 /**
2772  * Check that card is still alive.
2773  * Reads debug register from domain0.
2774  * If card is present, pre-defined value should
2775  * be found there.
2776  *
2777  * @param priv
2778  * @return 1 if card is present, 0 otherwise
2779  */
2780 static inline int ipw_alive(struct ipw_priv *priv)
2781 {
2782         return ipw_read32(priv, 0x90) == 0xd55555d5;
2783 }
2784
2785 /* timeout in msec, attempted in 10-msec quanta */
2786 static int ipw_poll_bit(struct ipw_priv *priv, u32 addr, u32 mask,
2787                                int timeout)
2788 {
2789         int i = 0;
2790
2791         do {
2792                 if ((ipw_read32(priv, addr) & mask) == mask)
2793                         return i;
2794                 mdelay(10);
2795                 i += 10;
2796         } while (i < timeout);
2797
2798         return -ETIME;
2799 }
2800
2801 /* These functions load the firmware and micro code for the operation of
2802  * the ipw hardware.  It assumes the buffer has all the bits for the
2803  * image and the caller is handling the memory allocation and clean up.
2804  */
2805
2806 static int ipw_stop_master(struct ipw_priv *priv)
2807 {
2808         int rc;
2809
2810         IPW_DEBUG_TRACE(">> \n");
2811         /* stop master. typical delay - 0 */
2812         ipw_set_bit(priv, IPW_RESET_REG, IPW_RESET_REG_STOP_MASTER);
2813
2814         /* timeout is in msec, polled in 10-msec quanta */
2815         rc = ipw_poll_bit(priv, IPW_RESET_REG,
2816                           IPW_RESET_REG_MASTER_DISABLED, 100);
2817         if (rc < 0) {
2818                 IPW_ERROR("wait for stop master failed after 100ms\n");
2819                 return -1;
2820         }
2821
2822         IPW_DEBUG_INFO("stop master %dms\n", rc);
2823
2824         return rc;
2825 }
2826
2827 static void ipw_arc_release(struct ipw_priv *priv)
2828 {
2829         IPW_DEBUG_TRACE(">> \n");
2830         mdelay(5);
2831
2832         ipw_clear_bit(priv, IPW_RESET_REG, CBD_RESET_REG_PRINCETON_RESET);
2833
2834         /* no one knows timing, for safety add some delay */
2835         mdelay(5);
2836 }
2837
2838 struct fw_header {
2839         u32 version;
2840         u32 mode;
2841 };
2842
2843 struct fw_chunk {
2844         u32 address;
2845         u32 length;
2846 };
2847
2848 #define IPW_FW_MAJOR_VERSION 2
2849 #define IPW_FW_MINOR_VERSION 4
2850
2851 #define IPW_FW_MINOR(x) ((x & 0xff) >> 8)
2852 #define IPW_FW_MAJOR(x) (x & 0xff)
2853
2854 #define IPW_FW_VERSION ((IPW_FW_MINOR_VERSION << 8) | IPW_FW_MAJOR_VERSION)
2855
2856 #define IPW_FW_PREFIX "ipw-" __stringify(IPW_FW_MAJOR_VERSION) \
2857 "." __stringify(IPW_FW_MINOR_VERSION) "-"
2858
2859 #if IPW_FW_MAJOR_VERSION >= 2 && IPW_FW_MINOR_VERSION > 0
2860 #define IPW_FW_NAME(x) IPW_FW_PREFIX "" x ".fw"
2861 #else
2862 #define IPW_FW_NAME(x) "ipw2200_" x ".fw"
2863 #endif
2864
2865 static int ipw_load_ucode(struct ipw_priv *priv, u8 * data, size_t len)
2866 {
2867         int rc = 0, i, addr;
2868         u8 cr = 0;
2869         u16 *image;
2870
2871         image = (u16 *) data;
2872
2873         IPW_DEBUG_TRACE(">> \n");
2874
2875         rc = ipw_stop_master(priv);
2876
2877         if (rc < 0)
2878                 return rc;
2879
2880 //      spin_lock_irqsave(&priv->lock, flags);
2881
2882         for (addr = IPW_SHARED_LOWER_BOUND;
2883              addr < IPW_REGISTER_DOMAIN1_END; addr += 4) {
2884                 ipw_write32(priv, addr, 0);
2885         }
2886
2887         /* no ucode (yet) */
2888         memset(&priv->dino_alive, 0, sizeof(priv->dino_alive));
2889         /* destroy DMA queues */
2890         /* reset sequence */
2891
2892         ipw_write_reg32(priv, IPW_MEM_HALT_AND_RESET, IPW_BIT_HALT_RESET_ON);
2893         ipw_arc_release(priv);
2894         ipw_write_reg32(priv, IPW_MEM_HALT_AND_RESET, IPW_BIT_HALT_RESET_OFF);
2895         mdelay(1);
2896
2897         /* reset PHY */
2898         ipw_write_reg32(priv, IPW_INTERNAL_CMD_EVENT, IPW_BASEBAND_POWER_DOWN);
2899         mdelay(1);
2900
2901         ipw_write_reg32(priv, IPW_INTERNAL_CMD_EVENT, 0);
2902         mdelay(1);
2903
2904         /* enable ucode store */
2905         ipw_write_reg8(priv, IPW_BASEBAND_CONTROL_STATUS, 0x0);
2906         ipw_write_reg8(priv, IPW_BASEBAND_CONTROL_STATUS, DINO_ENABLE_CS);
2907         mdelay(1);
2908
2909         /* write ucode */
2910         /**
2911          * @bug
2912          * Do NOT set indirect address register once and then
2913          * store data to indirect data register in the loop.
2914          * It seems very reasonable, but in this case DINO do not
2915          * accept ucode. It is essential to set address each time.
2916          */
2917         /* load new ipw uCode */
2918         for (i = 0; i < len / 2; i++)
2919                 ipw_write_reg16(priv, IPW_BASEBAND_CONTROL_STORE,
2920                                 cpu_to_le16(image[i]));
2921
2922         /* enable DINO */
2923         ipw_write_reg8(priv, IPW_BASEBAND_CONTROL_STATUS, 0);
2924         ipw_write_reg8(priv, IPW_BASEBAND_CONTROL_STATUS, DINO_ENABLE_SYSTEM);
2925
2926         /* this is where the igx / win driver deveates from the VAP driver. */
2927
2928         /* wait for alive response */
2929         for (i = 0; i < 100; i++) {
2930                 /* poll for incoming data */
2931                 cr = ipw_read_reg8(priv, IPW_BASEBAND_CONTROL_STATUS);
2932                 if (cr & DINO_RXFIFO_DATA)
2933                         break;
2934                 mdelay(1);
2935         }
2936
2937         if (cr & DINO_RXFIFO_DATA) {
2938                 /* alive_command_responce size is NOT multiple of 4 */
2939                 u32 response_buffer[(sizeof(priv->dino_alive) + 3) / 4];
2940
2941                 for (i = 0; i < ARRAY_SIZE(response_buffer); i++)
2942                         response_buffer[i] =
2943                             le32_to_cpu(ipw_read_reg32(priv,
2944                                                        IPW_BASEBAND_RX_FIFO_READ));
2945                 memcpy(&priv->dino_alive, response_buffer,
2946                        sizeof(priv->dino_alive));
2947                 if (priv->dino_alive.alive_command == 1
2948                     && priv->dino_alive.ucode_valid == 1) {
2949                         rc = 0;
2950                         IPW_DEBUG_INFO
2951                             ("Microcode OK, rev. %d (0x%x) dev. %d (0x%x) "
2952                              "of %02d/%02d/%02d %02d:%02d\n",
2953                              priv->dino_alive.software_revision,
2954                              priv->dino_alive.software_revision,
2955                              priv->dino_alive.device_identifier,
2956                              priv->dino_alive.device_identifier,
2957                              priv->dino_alive.time_stamp[0],
2958                              priv->dino_alive.time_stamp[1],
2959                              priv->dino_alive.time_stamp[2],
2960                              priv->dino_alive.time_stamp[3],
2961                              priv->dino_alive.time_stamp[4]);
2962                 } else {
2963                         IPW_DEBUG_INFO("Microcode is not alive\n");
2964                         rc = -EINVAL;
2965                 }
2966         } else {
2967                 IPW_DEBUG_INFO("No alive response from DINO\n");
2968                 rc = -ETIME;
2969         }
2970
2971         /* disable DINO, otherwise for some reason
2972            firmware have problem getting alive resp. */
2973         ipw_write_reg8(priv, IPW_BASEBAND_CONTROL_STATUS, 0);
2974
2975 //      spin_unlock_irqrestore(&priv->lock, flags);
2976
2977         return rc;
2978 }
2979
2980 static int ipw_load_firmware(struct ipw_priv *priv, u8 * data, size_t len)
2981 {
2982         int rc = -1;
2983         int offset = 0;
2984         struct fw_chunk *chunk;
2985         dma_addr_t shared_phys;
2986         u8 *shared_virt;
2987
2988         IPW_DEBUG_TRACE("<< : \n");
2989         shared_virt = pci_alloc_consistent(priv->pci_dev, len, &shared_phys);
2990
2991         if (!shared_virt)
2992                 return -ENOMEM;
2993
2994         memmove(shared_virt, data, len);
2995
2996         /* Start the Dma */
2997         rc = ipw_fw_dma_enable(priv);
2998
2999         if (priv->sram_desc.last_cb_index > 0) {
3000                 /* the DMA is already ready this would be a bug. */
3001                 BUG();
3002                 goto out;
3003         }
3004
3005         do {
3006                 chunk = (struct fw_chunk *)(data + offset);
3007                 offset += sizeof(struct fw_chunk);
3008                 /* build DMA packet and queue up for sending */
3009                 /* dma to chunk->address, the chunk->length bytes from data +
3010                  * offeset*/
3011                 /* Dma loading */
3012                 rc = ipw_fw_dma_add_buffer(priv, shared_phys + offset,
3013                                            le32_to_cpu(chunk->address),
3014                                            le32_to_cpu(chunk->length));
3015                 if (rc) {
3016                         IPW_DEBUG_INFO("dmaAddBuffer Failed\n");
3017                         goto out;
3018                 }
3019
3020                 offset += le32_to_cpu(chunk->length);
3021         } while (offset < len);
3022
3023         /* Run the DMA and wait for the answer */
3024         rc = ipw_fw_dma_kick(priv);
3025         if (rc) {
3026                 IPW_ERROR("dmaKick Failed\n");
3027                 goto out;
3028         }
3029
3030         rc = ipw_fw_dma_wait(priv);
3031         if (rc) {
3032                 IPW_ERROR("dmaWaitSync Failed\n");
3033                 goto out;
3034         }
3035       out:
3036         pci_free_consistent(priv->pci_dev, len, shared_virt, shared_phys);
3037         return rc;
3038 }
3039
3040 /* stop nic */
3041 static int ipw_stop_nic(struct ipw_priv *priv)
3042 {
3043         int rc = 0;
3044
3045         /* stop */
3046         ipw_write32(priv, IPW_RESET_REG, IPW_RESET_REG_STOP_MASTER);
3047
3048         rc = ipw_poll_bit(priv, IPW_RESET_REG,
3049                           IPW_RESET_REG_MASTER_DISABLED, 500);
3050         if (rc < 0) {
3051                 IPW_ERROR("wait for reg master disabled failed after 500ms\n");
3052                 return rc;
3053         }
3054
3055         ipw_set_bit(priv, IPW_RESET_REG, CBD_RESET_REG_PRINCETON_RESET);
3056
3057         return rc;
3058 }
3059
3060 static void ipw_start_nic(struct ipw_priv *priv)
3061 {
3062         IPW_DEBUG_TRACE(">>\n");
3063
3064         /* prvHwStartNic  release ARC */
3065         ipw_clear_bit(priv, IPW_RESET_REG,
3066                       IPW_RESET_REG_MASTER_DISABLED |
3067                       IPW_RESET_REG_STOP_MASTER |
3068                       CBD_RESET_REG_PRINCETON_RESET);
3069
3070         /* enable power management */
3071         ipw_set_bit(priv, IPW_GP_CNTRL_RW,
3072                     IPW_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY);
3073
3074         IPW_DEBUG_TRACE("<<\n");
3075 }
3076
3077 static int ipw_init_nic(struct ipw_priv *priv)
3078 {
3079         int rc;
3080
3081         IPW_DEBUG_TRACE(">>\n");
3082         /* reset */
3083         /*prvHwInitNic */
3084         /* set "initialization complete" bit to move adapter to D0 state */
3085         ipw_set_bit(priv, IPW_GP_CNTRL_RW, IPW_GP_CNTRL_BIT_INIT_DONE);
3086
3087         /* low-level PLL activation */
3088         ipw_write32(priv, IPW_READ_INT_REGISTER,
3089                     IPW_BIT_INT_HOST_SRAM_READ_INT_REGISTER);
3090
3091         /* wait for clock stabilization */
3092         rc = ipw_poll_bit(priv, IPW_GP_CNTRL_RW,
3093                           IPW_GP_CNTRL_BIT_CLOCK_READY, 250);
3094         if (rc < 0)
3095                 IPW_DEBUG_INFO("FAILED wait for clock stablization\n");
3096
3097         /* assert SW reset */
3098         ipw_set_bit(priv, IPW_RESET_REG, IPW_RESET_REG_SW_RESET);
3099
3100         udelay(10);
3101
3102         /* set "initialization complete" bit to move adapter to D0 state */
3103         ipw_set_bit(priv, IPW_GP_CNTRL_RW, IPW_GP_CNTRL_BIT_INIT_DONE);
3104
3105         IPW_DEBUG_TRACE(">>\n");
3106         return 0;
3107 }
3108
3109 /* Call this function from process context, it will sleep in request_firmware.
3110  * Probe is an ok place to call this from.
3111  */
3112 static int ipw_reset_nic(struct ipw_priv *priv)
3113 {
3114         int rc = 0;
3115         unsigned long flags;
3116
3117         IPW_DEBUG_TRACE(">>\n");
3118
3119         rc = ipw_init_nic(priv);
3120
3121         spin_lock_irqsave(&priv->lock, flags);
3122         /* Clear the 'host command active' bit... */
3123         priv->status &= ~STATUS_HCMD_ACTIVE;
3124         wake_up_interruptible(&priv->wait_command_queue);
3125         priv->status &= ~(STATUS_SCANNING | STATUS_SCAN_ABORTING);
3126         wake_up_interruptible(&priv->wait_state);
3127         spin_unlock_irqrestore(&priv->lock, flags);
3128
3129         IPW_DEBUG_TRACE("<<\n");
3130         return rc;
3131 }
3132
3133 static int ipw_get_fw(struct ipw_priv *priv,
3134                       const struct firmware **fw, const char *name)
3135 {
3136         struct fw_header *header;
3137         int rc;
3138
3139         /* ask firmware_class module to get the boot firmware off disk */
3140         rc = request_firmware(fw, name, &priv->pci_dev->dev);
3141         if (rc < 0) {
3142                 IPW_ERROR("%s load failed: Reason %d\n", name, rc);
3143                 return rc;
3144         }
3145
3146         header = (struct fw_header *)(*fw)->data;
3147         if (IPW_FW_MAJOR(le32_to_cpu(header->version)) != IPW_FW_MAJOR_VERSION) {
3148                 IPW_ERROR("'%s' firmware version not compatible (%d != %d)\n",
3149                           name,
3150                           IPW_FW_MAJOR(le32_to_cpu(header->version)),
3151                           IPW_FW_MAJOR_VERSION);
3152                 return -EINVAL;
3153         }
3154
3155         IPW_DEBUG_INFO("Loading firmware '%s' file v%d.%d (%zd bytes)\n",
3156                        name,
3157                        IPW_FW_MAJOR(le32_to_cpu(header->version)),
3158                        IPW_FW_MINOR(le32_to_cpu(header->version)),
3159                        (*fw)->size - sizeof(struct fw_header));
3160         return 0;
3161 }
3162
3163 #define IPW_RX_BUF_SIZE (3000)
3164
3165 static void ipw_rx_queue_reset(struct ipw_priv *priv,
3166                                       struct ipw_rx_queue *rxq)
3167 {
3168         unsigned long flags;
3169         int i;
3170
3171         spin_lock_irqsave(&rxq->lock, flags);
3172
3173         INIT_LIST_HEAD(&rxq->rx_free);
3174         INIT_LIST_HEAD(&rxq->rx_used);
3175
3176         /* Fill the rx_used queue with _all_ of the Rx buffers */
3177         for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
3178                 /* In the reset function, these buffers may have been allocated
3179                  * to an SKB, so we need to unmap and free potential storage */
3180                 if (rxq->pool[i].skb != NULL) {
3181                         pci_unmap_single(priv->pci_dev, rxq->pool[i].dma_addr,
3182                                          IPW_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
3183                         dev_kfree_skb(rxq->pool[i].skb);
3184                         rxq->pool[i].skb = NULL;
3185                 }
3186                 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
3187         }
3188
3189         /* Set us so that we have processed and used all buffers, but have
3190          * not restocked the Rx queue with fresh buffers */
3191         rxq->read = rxq->write = 0;
3192         rxq->processed = RX_QUEUE_SIZE - 1;
3193         rxq->free_count = 0;
3194         spin_unlock_irqrestore(&rxq->lock, flags);
3195 }
3196
3197 #ifdef CONFIG_PM
3198 static int fw_loaded = 0;
3199 static const struct firmware *bootfw = NULL;
3200 static const struct firmware *firmware = NULL;
3201 static const struct firmware *ucode = NULL;
3202
3203 static void free_firmware(void)
3204 {
3205         if (fw_loaded) {
3206                 release_firmware(bootfw);
3207                 release_firmware(ucode);
3208                 release_firmware(firmware);
3209                 bootfw = ucode = firmware = NULL;
3210                 fw_loaded = 0;
3211         }
3212 }
3213 #else