drivers/net/wireless/intel/iwlwifi/pcie/tx.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
   4  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
   5  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
   6  *
   7  * Portions of this file are derived from the ipw3945 project, as well
   8  * as portions of the ieee80211 subsystem header files.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program; if not, write to the Free Software Foundation, Inc.,
  21  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  22  *
  23  * The full GNU General Public License is included in this distribution in the
  24  * file called LICENSE.
  25  *
  26  * Contact Information:
  27  *  Intel Linux Wireless <linuxwifi@intel.com>
  28  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  29  *
  30  *****************************************************************************/
  31 #include <linux/etherdevice.h>
  32 #include <linux/ieee80211.h>
  33 #include <linux/slab.h>
  34 #include <linux/sched.h>
  35 #include <linux/pm_runtime.h>
  36 #include <net/ip6_checksum.h>
  37 #include <net/tso.h>
  38
  39 #include "iwl-debug.h"
  40 #include "iwl-csr.h"
  41 #include "iwl-prph.h"
  42 #include "iwl-io.h"
  43 #include "iwl-scd.h"
  44 #include "iwl-op-mode.h"
  45 #include "internal.h"
  46 #include "fw/api/tx.h"
  47
  48 #define IWL_TX_CRC_SIZE 4
  49 #define IWL_TX_DELIMITER_SIZE 4
  50
  51 /*************** DMA-QUEUE-GENERAL-FUNCTIONS  *****
  52  * DMA services
  53  *
  54  * Theory of operation
  55  *
  56  * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  57  * of buffer descriptors, each of which points to one or more data buffers for
  58  * the device to read from or fill.  Driver and device exchange status of each
  59  * queue via "read" and "write" pointers.  Driver keeps minimum of 2 empty
  60  * entries in each circular buffer, to protect against confusing empty and full
  61  * queue states.
  62  *
  63  * The device reads or writes the data in the queues via the device's several
  64  * DMA/FIFO channels.  Each queue is mapped to a single DMA channel.
  65  *
  66  * For Tx queue, there are low mark and high mark limits. If, after queuing
  67  * the packet for Tx, free space become < low mark, Tx queue stopped. When
  68  * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  69  * Tx queue resumed.
  70  *
  71  ***************************************************/
  72
  73 int iwl_queue_space(const struct iwl_txq *q)
  74 {
  75         unsigned int max;
  76         unsigned int used;
  77
  78         /*
  79          * To avoid ambiguity between empty and completely full queues, there
  80          * should always be less than TFD_QUEUE_SIZE_MAX elements in the queue.
  81          * If q->n_window is smaller than TFD_QUEUE_SIZE_MAX, there is no need
  82          * to reserve any queue entries for this purpose.
  83          */
  84         if (q->n_window < TFD_QUEUE_SIZE_MAX)
  85                 max = q->n_window;
  86         else
  87                 max = TFD_QUEUE_SIZE_MAX - 1;
  88
  89         /*
  90          * TFD_QUEUE_SIZE_MAX is a power of 2, so the following is equivalent to
  91          * modulo by TFD_QUEUE_SIZE_MAX and is well defined.
  92          */
  93         used = (q->write_ptr - q->read_ptr) & (TFD_QUEUE_SIZE_MAX - 1);
  94
  95         if (WARN_ON(used > max))
  96                 return 0;
  97
  98         return max - used;
  99 }
 100
 101 /*
 102  * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
 103  */
 104 static int iwl_queue_init(struct iwl_txq *q, int slots_num)
 105 {
 106         q->n_window = slots_num;
 107
 108         /* slots_num must be power-of-two size, otherwise
 109          * iwl_pcie_get_cmd_index is broken. */
 110         if (WARN_ON(!is_power_of_2(slots_num)))
 111                 return -EINVAL;
 112
 113         q->low_mark = q->n_window / 4;
 114         if (q->low_mark < 4)
 115                 q->low_mark = 4;
 116
 117         q->high_mark = q->n_window / 8;
 118         if (q->high_mark < 2)
 119                 q->high_mark = 2;
 120
 121         q->write_ptr = 0;
 122         q->read_ptr = 0;
 123
 124         return 0;
 125 }
 126
 127 int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
 128                            struct iwl_dma_ptr *ptr, size_t size)
 129 {
 130         if (WARN_ON(ptr->addr))
 131                 return -EINVAL;
 132
 133         ptr->addr = dma_alloc_coherent(trans->dev, size,
 134                                        &ptr->dma, GFP_KERNEL);
 135         if (!ptr->addr)
 136                 return -ENOMEM;
 137         ptr->size = size;
 138         return 0;
 139 }
 140
 141 void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr)
 142 {
 143         if (unlikely(!ptr->addr))
 144                 return;
 145
 146         dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
 147         memset(ptr, 0, sizeof(*ptr));
 148 }
 149
 150 static void iwl_pcie_txq_stuck_timer(struct timer_list *t)
 151 {
 152         struct iwl_txq *txq = from_timer(txq, t, stuck_timer);
 153         struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
 154         struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
 155
 156         spin_lock(&txq->lock);
 157         /* check if triggered erroneously */
 158         if (txq->read_ptr == txq->write_ptr) {
 159                 spin_unlock(&txq->lock);
 160                 return;
 161         }
 162         spin_unlock(&txq->lock);
 163
 164         iwl_trans_pcie_log_scd_error(trans, txq);
 165
 166         iwl_force_nmi(trans);
 167 }
 168
 169 /*
 170  * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
 171  */
 172 static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
 173                                              struct iwl_txq *txq, u16 byte_cnt,
 174                                              int num_tbs)
 175 {
 176         struct iwlagn_scd_bc_tbl *scd_bc_tbl;
 177         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 178         int write_ptr = txq->write_ptr;
 179         int txq_id = txq->id;
 180         u8 sec_ctl = 0;
 181         u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
 182         __le16 bc_ent;
 183         struct iwl_tx_cmd *tx_cmd =
 184                 (void *)txq->entries[txq->write_ptr].cmd->payload;
 185         u8 sta_id = tx_cmd->sta_id;
 186
 187         scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
 188
 189         sec_ctl = tx_cmd->sec_ctl;
 190
 191         switch (sec_ctl & TX_CMD_SEC_MSK) {
 192         case TX_CMD_SEC_CCM:
 193                 len += IEEE80211_CCMP_MIC_LEN;
 194                 break;
 195         case TX_CMD_SEC_TKIP:
 196                 len += IEEE80211_TKIP_ICV_LEN;
 197                 break;
 198         case TX_CMD_SEC_WEP:
 199                 len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN;
 200                 break;
 201         }
 202         if (trans_pcie->bc_table_dword)
 203                 len = DIV_ROUND_UP(len, 4);
 204
 205         if (WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX))
 206                 return;
 207
 208         bc_ent = cpu_to_le16(len | (sta_id << 12));
 209
 210         scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
 211
 212         if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
 213                 scd_bc_tbl[txq_id].
 214                         tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
 215 }
 216
 217 static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
 218                                             struct iwl_txq *txq)
 219 {
 220         struct iwl_trans_pcie *trans_pcie =
 221                 IWL_TRANS_GET_PCIE_TRANS(trans);
 222         struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
 223         int txq_id = txq->id;
 224         int read_ptr = txq->read_ptr;
 225         u8 sta_id = 0;
 226         __le16 bc_ent;
 227         struct iwl_tx_cmd *tx_cmd =
 228                 (void *)txq->entries[read_ptr].cmd->payload;
 229
 230         WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
 231
 232         if (txq_id != trans_pcie->cmd_queue)
 233                 sta_id = tx_cmd->sta_id;
 234
 235         bc_ent = cpu_to_le16(1 | (sta_id << 12));
 236
 237         scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
 238
 239         if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
 240                 scd_bc_tbl[txq_id].
 241                         tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
 242 }
 243
 244 /*
 245  * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware
 246  */
 247 static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans,
 248                                     struct iwl_txq *txq)
 249 {
 250         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 251         u32 reg = 0;
 252         int txq_id = txq->id;
 253
 254         lockdep_assert_held(&txq->lock);
 255
 256         /*
 257          * explicitly wake up the NIC if:
 258          * 1. shadow registers aren't enabled
 259          * 2. NIC is woken up for CMD regardless of shadow outside this function
 260          * 3. there is a chance that the NIC is asleep
 261          */
 262         if (!trans->cfg->base_params->shadow_reg_enable &&
 263             txq_id != trans_pcie->cmd_queue &&
 264             test_bit(STATUS_TPOWER_PMI, &trans->status)) {
 265                 /*
 266                  * wake up nic if it's powered down ...
 267                  * uCode will wake up, and interrupt us again, so next
 268                  * time we'll skip this part.
 269                  */
 270                 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
 271
 272                 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
 273                         IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
 274                                        txq_id, reg);
 275                         iwl_set_bit(trans, CSR_GP_CNTRL,
 276                                     CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 277                         txq->need_update = true;
 278                         return;
 279                 }
 280         }
 281
 282         /*
 283          * if not in power-save mode, uCode will never sleep when we're
 284          * trying to tx (during RFKILL, we're not trying to tx).
 285          */
 286         IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->write_ptr);
 287         if (!txq->block)
 288                 iwl_write32(trans, HBUS_TARG_WRPTR,
 289                             txq->write_ptr | (txq_id << 8));
 290 }
 291
 292 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans)
 293 {
 294         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 295         int i;
 296
 297         for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
 298                 struct iwl_txq *txq = trans_pcie->txq[i];
 299
 300                 if (!test_bit(i, trans_pcie->queue_used))
 301                         continue;
 302
 303                 spin_lock_bh(&txq->lock);
 304                 if (txq->need_update) {
 305                         iwl_pcie_txq_inc_wr_ptr(trans, txq);
 306                         txq->need_update = false;
 307                 }
 308                 spin_unlock_bh(&txq->lock);
 309         }
 310 }
 311
 312 static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_trans *trans,
 313                                                   void *_tfd, u8 idx)
 314 {
 315
 316         if (trans->cfg->use_tfh) {
 317                 struct iwl_tfh_tfd *tfd = _tfd;
 318                 struct iwl_tfh_tb *tb = &tfd->tbs[idx];
 319
 320                 return (dma_addr_t)(le64_to_cpu(tb->addr));
 321         } else {
 322                 struct iwl_tfd *tfd = _tfd;
 323                 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 324                 dma_addr_t addr = get_unaligned_le32(&tb->lo);
 325                 dma_addr_t hi_len;
 326
 327                 if (sizeof(dma_addr_t) <= sizeof(u32))
 328                         return addr;
 329
 330                 hi_len = le16_to_cpu(tb->hi_n_len) & 0xF;
 331
 332                 /*
 333                  * shift by 16 twice to avoid warnings on 32-bit
 334                  * (where this code never runs anyway due to the
 335                  * if statement above)
 336                  */
 337                 return addr | ((hi_len << 16) << 16);
 338         }
 339 }
 340
 341 static inline void iwl_pcie_tfd_set_tb(struct iwl_trans *trans, void *tfd,
 342                                        u8 idx, dma_addr_t addr, u16 len)
 343 {
 344         struct iwl_tfd *tfd_fh = (void *)tfd;
 345         struct iwl_tfd_tb *tb = &tfd_fh->tbs[idx];
 346
 347         u16 hi_n_len = len << 4;
 348
 349         put_unaligned_le32(addr, &tb->lo);
 350         hi_n_len |= iwl_get_dma_hi_addr(addr);
 351
 352         tb->hi_n_len = cpu_to_le16(hi_n_len);
 353
 354         tfd_fh->num_tbs = idx + 1;
 355 }
 356
 357 static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_trans *trans, void *_tfd)
 358 {
 359         if (trans->cfg->use_tfh) {
 360                 struct iwl_tfh_tfd *tfd = _tfd;
 361
 362                 return le16_to_cpu(tfd->num_tbs) & 0x1f;
 363         } else {
 364                 struct iwl_tfd *tfd = _tfd;
 365
 366                 return tfd->num_tbs & 0x1f;
 367         }
 368 }
 369
 370 static void iwl_pcie_tfd_unmap(struct iwl_trans *trans,
 371                                struct iwl_cmd_meta *meta,
 372                                struct iwl_txq *txq, int index)
 373 {
 374         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 375         int i, num_tbs;
 376         void *tfd = iwl_pcie_get_tfd(trans, txq, index);
 377
 378         /* Sanity check on number of chunks */
 379         num_tbs = iwl_pcie_tfd_get_num_tbs(trans, tfd);
 380
 381         if (num_tbs >= trans_pcie->max_tbs) {
 382                 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
 383                 /* @todo issue fatal error, it is quite serious situation */
 384                 return;
 385         }
 386
 387         /* first TB is never freed - it's the bidirectional DMA data */
 388
 389         for (i = 1; i < num_tbs; i++) {
 390                 if (meta->tbs & BIT(i))
 391                         dma_unmap_page(trans->dev,
 392                                        iwl_pcie_tfd_tb_get_addr(trans, tfd, i),
 393                                        iwl_pcie_tfd_tb_get_len(trans, tfd, i),
 394                                        DMA_TO_DEVICE);
 395                 else
 396                         dma_unmap_single(trans->dev,
 397                                          iwl_pcie_tfd_tb_get_addr(trans, tfd,
 398                                                                   i),
 399                                          iwl_pcie_tfd_tb_get_len(trans, tfd,
 400                                                                  i),
 401                                          DMA_TO_DEVICE);
 402         }
 403
 404         if (trans->cfg->use_tfh) {
 405                 struct iwl_tfh_tfd *tfd_fh = (void *)tfd;
 406
 407                 tfd_fh->num_tbs = 0;
 408         } else {
 409                 struct iwl_tfd *tfd_fh = (void *)tfd;
 410
 411                 tfd_fh->num_tbs = 0;
 412         }
 413
 414 }
 415
 416 /*
 417  * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
 418  * @trans - transport private data
 419  * @txq - tx queue
 420  * @dma_dir - the direction of the DMA mapping
 421  *
 422  * Does NOT advance any TFD circular buffer read/write indexes
 423  * Does NOT free the TFD itself (which is within circular buffer)
 424  */
 425 void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq)
 426 {
 427         /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and
 428          * idx is bounded by n_window
 429          */
 430         int rd_ptr = txq->read_ptr;
 431         int idx = iwl_pcie_get_cmd_index(txq, rd_ptr);
 432
 433         lockdep_assert_held(&txq->lock);
 434
 435         /* We have only q->n_window txq->entries, but we use
 436          * TFD_QUEUE_SIZE_MAX tfds
 437          */
 438         iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, txq, rd_ptr);
 439
 440         /* free SKB */
 441         if (txq->entries) {
 442                 struct sk_buff *skb;
 443
 444                 skb = txq->entries[idx].skb;
 445
 446                 /* Can be called from irqs-disabled context
 447                  * If skb is not NULL, it means that the whole queue is being
 448                  * freed and that the queue is not empty - free the skb
 449                  */
 450                 if (skb) {
 451                         iwl_op_mode_free_skb(trans->op_mode, skb);
 452                         txq->entries[idx].skb = NULL;
 453                 }
 454         }
 455 }
 456
 457 static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq,
 458                                   dma_addr_t addr, u16 len, bool reset)
 459 {
 460         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 461         void *tfd;
 462         u32 num_tbs;
 463
 464         tfd = txq->tfds + trans_pcie->tfd_size * txq->write_ptr;
 465
 466         if (reset)
 467                 memset(tfd, 0, trans_pcie->tfd_size);
 468
 469         num_tbs = iwl_pcie_tfd_get_num_tbs(trans, tfd);
 470
 471         /* Each TFD can point to a maximum max_tbs Tx buffers */
 472         if (num_tbs >= trans_pcie->max_tbs) {
 473                 IWL_ERR(trans, "Error can not send more than %d chunks\n",
 474                         trans_pcie->max_tbs);
 475                 return -EINVAL;
 476         }
 477
 478         if (WARN(addr & ~IWL_TX_DMA_MASK,
 479                  "Unaligned address = %llx\n", (unsigned long long)addr))
 480                 return -EINVAL;
 481
 482         iwl_pcie_tfd_set_tb(trans, tfd, num_tbs, addr, len);
 483
 484         return num_tbs;
 485 }
 486
 487 int iwl_pcie_txq_alloc(struct iwl_trans *trans, struct iwl_txq *txq,
 488                        int slots_num, bool cmd_queue)
 489 {
 490         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 491         size_t tfd_sz = trans_pcie->tfd_size * TFD_QUEUE_SIZE_MAX;
 492         size_t tb0_buf_sz;
 493         int i;
 494
 495         if (WARN_ON(txq->entries || txq->tfds))
 496                 return -EINVAL;
 497
 498         timer_setup(&txq->stuck_timer, iwl_pcie_txq_stuck_timer, 0);
 499         txq->trans_pcie = trans_pcie;
 500
 501         txq->n_window = slots_num;
 502
 503         txq->entries = kcalloc(slots_num,
 504                                sizeof(struct iwl_pcie_txq_entry),
 505                                GFP_KERNEL);
 506
 507         if (!txq->entries)
 508                 goto error;
 509
 510         if (cmd_queue)
 511                 for (i = 0; i < slots_num; i++) {
 512                         txq->entries[i].cmd =
 513                                 kmalloc(sizeof(struct iwl_device_cmd),
 514                                         GFP_KERNEL);
 515                         if (!txq->entries[i].cmd)
 516                                 goto error;
 517                 }
 518
 519         /* Circular buffer of transmit frame descriptors (TFDs),
 520          * shared with device */
 521         txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
 522                                        &txq->dma_addr, GFP_KERNEL);
 523         if (!txq->tfds)
 524                 goto error;
 525
 526         BUILD_BUG_ON(IWL_FIRST_TB_SIZE_ALIGN != sizeof(*txq->first_tb_bufs));
 527
 528         tb0_buf_sz = sizeof(*txq->first_tb_bufs) * slots_num;
 529
 530         txq->first_tb_bufs = dma_alloc_coherent(trans->dev, tb0_buf_sz,
 531                                               &txq->first_tb_dma,
 532                                               GFP_KERNEL);
 533         if (!txq->first_tb_bufs)
 534                 goto err_free_tfds;
 535
 536         return 0;
 537 err_free_tfds:
 538         dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->dma_addr);
 539 error:
 540         if (txq->entries && cmd_queue)
 541                 for (i = 0; i < slots_num; i++)
 542                         kfree(txq->entries[i].cmd);
 543         kfree(txq->entries);
 544         txq->entries = NULL;
 545
 546         return -ENOMEM;
 547
 548 }
 549
 550 int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq,
 551                       int slots_num, bool cmd_queue)
 552 {
 553         int ret;
 554
 555         txq->need_update = false;
 556
 557         /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
 558          * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
 559         BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
 560
 561         /* Initialize queue's high/low-water marks, and head/tail indexes */
 562         ret = iwl_queue_init(txq, slots_num);
 563         if (ret)
 564                 return ret;
 565
 566         spin_lock_init(&txq->lock);
 567
 568         if (cmd_queue) {
 569                 static struct lock_class_key iwl_pcie_cmd_queue_lock_class;
 570
 571                 lockdep_set_class(&txq->lock, &iwl_pcie_cmd_queue_lock_class);
 572         }
 573
 574         __skb_queue_head_init(&txq->overflow_q);
 575
 576         return 0;
 577 }
 578
 579 void iwl_pcie_free_tso_page(struct iwl_trans_pcie *trans_pcie,
 580                             struct sk_buff *skb)
 581 {
 582         struct page **page_ptr;
 583
 584         page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs);
 585
 586         if (*page_ptr) {
 587                 __free_page(*page_ptr);
 588                 *page_ptr = NULL;
 589         }
 590 }
 591
 592 static void iwl_pcie_clear_cmd_in_flight(struct iwl_trans *trans)
 593 {
 594         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 595
 596         lockdep_assert_held(&trans_pcie->reg_lock);
 597
 598         if (trans_pcie->ref_cmd_in_flight) {
 599                 trans_pcie->ref_cmd_in_flight = false;
 600                 IWL_DEBUG_RPM(trans, "clear ref_cmd_in_flight - unref\n");
 601                 iwl_trans_unref(trans);
 602         }
 603
 604         if (!trans->cfg->base_params->apmg_wake_up_wa)
 605                 return;
 606         if (WARN_ON(!trans_pcie->cmd_hold_nic_awake))
 607                 return;
 608
 609         trans_pcie->cmd_hold_nic_awake = false;
 610         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 611                                    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 612 }
 613
 614 /*
 615  * iwl_pcie_txq_unmap -  Unmap any remaining DMA mappings and free skb's
 616  */
 617 static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id)
 618 {
 619         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 620         struct iwl_txq *txq = trans_pcie->txq[txq_id];
 621
 622         spin_lock_bh(&txq->lock);
 623         while (txq->write_ptr != txq->read_ptr) {
 624                 IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n",
 625                                    txq_id, txq->read_ptr);
 626
 627                 if (txq_id != trans_pcie->cmd_queue) {
 628                         struct sk_buff *skb = txq->entries[txq->read_ptr].skb;
 629
 630                         if (WARN_ON_ONCE(!skb))
 631                                 continue;
 632
 633                         iwl_pcie_free_tso_page(trans_pcie, skb);
 634                 }
 635                 iwl_pcie_txq_free_tfd(trans, txq);
 636                 txq->read_ptr = iwl_queue_inc_wrap(txq->read_ptr);
 637
 638                 if (txq->read_ptr == txq->write_ptr) {
 639                         unsigned long flags;
 640
 641                         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
 642                         if (txq_id != trans_pcie->cmd_queue) {
 643                                 IWL_DEBUG_RPM(trans, "Q %d - last tx freed\n",
 644                                               txq->id);
 645                                 iwl_trans_unref(trans);
 646                         } else {
 647                                 iwl_pcie_clear_cmd_in_flight(trans);
 648                         }
 649                         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
 650                 }
 651         }
 652
 653         while (!skb_queue_empty(&txq->overflow_q)) {
 654                 struct sk_buff *skb = __skb_dequeue(&txq->overflow_q);
 655
 656                 iwl_op_mode_free_skb(trans->op_mode, skb);
 657         }
 658
 659         spin_unlock_bh(&txq->lock);
 660
 661         /* just in case - this queue may have been stopped */
 662         iwl_wake_queue(trans, txq);
 663 }
 664
 665 /*
 666  * iwl_pcie_txq_free - Deallocate DMA queue.
 667  * @txq: Transmit queue to deallocate.
 668  *
 669  * Empty queue by removing and destroying all BD's.
 670  * Free all buffers.
 671  * 0-fill, but do not free "txq" descriptor structure.
 672  */
 673 static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id)
 674 {
 675         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 676         struct iwl_txq *txq = trans_pcie->txq[txq_id];
 677         struct device *dev = trans->dev;
 678         int i;
 679
 680         if (WARN_ON(!txq))
 681                 return;
 682
 683         iwl_pcie_txq_unmap(trans, txq_id);
 684
 685         /* De-alloc array of command/tx buffers */
 686         if (txq_id == trans_pcie->cmd_queue)
 687                 for (i = 0; i < txq->n_window; i++) {
 688                         kzfree(txq->entries[i].cmd);
 689                         kzfree(txq->entries[i].free_buf);
 690                 }
 691
 692         /* De-alloc circular buffer of TFDs */
 693         if (txq->tfds) {
 694                 dma_free_coherent(dev,
 695                                   trans_pcie->tfd_size * TFD_QUEUE_SIZE_MAX,
 696                                   txq->tfds, txq->dma_addr);
 697                 txq->dma_addr = 0;
 698                 txq->tfds = NULL;
 699
 700                 dma_free_coherent(dev,
 701                                   sizeof(*txq->first_tb_bufs) * txq->n_window,
 702                                   txq->first_tb_bufs, txq->first_tb_dma);
 703         }
 704
 705         kfree(txq->entries);
 706         txq->entries = NULL;
 707
 708         del_timer_sync(&txq->stuck_timer);
 709
 710         /* 0-fill queue descriptor structure */
 711         memset(txq, 0, sizeof(*txq));
 712 }
 713
 714 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
 715 {
 716         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 717         int nq = trans->cfg->base_params->num_of_queues;
 718         int chan;
 719         u32 reg_val;
 720         int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) -
 721                                 SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32);
 722
 723         /* make sure all queue are not stopped/used */
 724         memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
 725         memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
 726
 727         trans_pcie->scd_base_addr =
 728                 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
 729
 730         WARN_ON(scd_base_addr != 0 &&
 731                 scd_base_addr != trans_pcie->scd_base_addr);
 732
 733         /* reset context data, TX status and translation data */
 734         iwl_trans_write_mem(trans, trans_pcie->scd_base_addr +
 735                                    SCD_CONTEXT_MEM_LOWER_BOUND,
 736                             NULL, clear_dwords);
 737
 738         iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
 739                        trans_pcie->scd_bc_tbls.dma >> 10);
 740
 741         /* The chain extension of the SCD doesn't work well. This feature is
 742          * enabled by default by the HW, so we need to disable it manually.
 743          */
 744         if (trans->cfg->base_params->scd_chain_ext_wa)
 745                 iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
 746
 747         iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue,
 748                                 trans_pcie->cmd_fifo,
 749                                 trans_pcie->cmd_q_wdg_timeout);
 750
 751         /* Activate all Tx DMA/FIFO channels */
 752         iwl_scd_activate_fifos(trans);
 753
 754         /* Enable DMA channel */
 755         for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++)
 756                 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
 757                                    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 758                                    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
 759
 760         /* Update FH chicken bits */
 761         reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
 762         iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
 763                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
 764
 765         /* Enable L1-Active */
 766         if (trans->cfg->device_family < IWL_DEVICE_FAMILY_8000)
 767                 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
 768                                     APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 769 }
 770
 771 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans)
 772 {
 773         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 774         int txq_id;
 775
 776         /*
 777          * we should never get here in gen2 trans mode return early to avoid
 778          * having invalid accesses
 779          */
 780         if (WARN_ON_ONCE(trans->cfg->gen2))
 781                 return;
 782
 783         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
 784              txq_id++) {
 785                 struct iwl_txq *txq = trans_pcie->txq[txq_id];
 786                 if (trans->cfg->use_tfh)
 787                         iwl_write_direct64(trans,
 788                                            FH_MEM_CBBC_QUEUE(trans, txq_id),
 789                                            txq->dma_addr);
 790                 else
 791                         iwl_write_direct32(trans,
 792                                            FH_MEM_CBBC_QUEUE(trans, txq_id),
 793                                            txq->dma_addr >> 8);
 794                 iwl_pcie_txq_unmap(trans, txq_id);
 795                 txq->read_ptr = 0;
 796                 txq->write_ptr = 0;
 797         }
 798
 799         /* Tell NIC where to find the "keep warm" buffer */
 800         iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
 801                            trans_pcie->kw.dma >> 4);
 802
 803         /*
 804          * Send 0 as the scd_base_addr since the device may have be reset
 805          * while we were in WoWLAN in which case SCD_SRAM_BASE_ADDR will
 806          * contain garbage.
 807          */
 808         iwl_pcie_tx_start(trans, 0);
 809 }
 810
 811 static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans)
 812 {
 813         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 814         unsigned long flags;
 815         int ch, ret;
 816         u32 mask = 0;
 817
 818         spin_lock(&trans_pcie->irq_lock);
 819
 820         if (!iwl_trans_grab_nic_access(trans, &flags))
 821                 goto out;
 822
 823         /* Stop each Tx DMA channel */
 824         for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
 825                 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
 826                 mask |= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch);
 827         }
 828
 829         /* Wait for DMA channels to be idle */
 830         ret = iwl_poll_bit(trans, FH_TSSR_TX_STATUS_REG, mask, mask, 5000);
 831         if (ret < 0)
 832                 IWL_ERR(trans,
 833                         "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
 834                         ch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG));
 835
 836         iwl_trans_release_nic_access(trans, &flags);
 837
 838 out:
 839         spin_unlock(&trans_pcie->irq_lock);
 840 }
 841
 842 /*
 843  * iwl_pcie_tx_stop - Stop all Tx DMA channels
 844  */
 845 int iwl_pcie_tx_stop(struct iwl_trans *trans)
 846 {
 847         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 848         int txq_id;
 849
 850         /* Turn off all Tx DMA fifos */
 851         iwl_scd_deactivate_fifos(trans);
 852
 853         /* Turn off all Tx DMA channels */
 854         iwl_pcie_tx_stop_fh(trans);
 855
 856         /*
 857          * This function can be called before the op_mode disabled the
 858          * queues. This happens when we have an rfkill interrupt.
 859          * Since we stop Tx altogether - mark the queues as stopped.
 860          */
 861         memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
 862         memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
 863
 864         /* This can happen: start_hw, stop_device */
 865         if (!trans_pcie->txq_memory)
 866                 return 0;
 867
 868         /* Unmap DMA from host system and free skb's */
 869         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
 870              txq_id++)
 871                 iwl_pcie_txq_unmap(trans, txq_id);
 872
 873         return 0;
 874 }
 875
 876 /*
 877  * iwl_trans_tx_free - Free TXQ Context
 878  *
 879  * Destroy all TX DMA queues and structures
 880  */
 881 void iwl_pcie_tx_free(struct iwl_trans *trans)
 882 {
 883         int txq_id;
 884         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 885
 886         memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
 887
 888         /* Tx queues */
 889         if (trans_pcie->txq_memory) {
 890                 for (txq_id = 0;
 891                      txq_id < trans->cfg->base_params->num_of_queues;
 892                      txq_id++) {
 893                         iwl_pcie_txq_free(trans, txq_id);
 894                         trans_pcie->txq[txq_id] = NULL;
 895                 }
 896         }
 897
 898         kfree(trans_pcie->txq_memory);
 899         trans_pcie->txq_memory = NULL;
 900
 901         iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw);
 902
 903         iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
 904 }
 905
 906 /*
 907  * iwl_pcie_tx_alloc - allocate TX context
 908  * Allocate all Tx DMA structures and initialize them
 909  */
 910 static int iwl_pcie_tx_alloc(struct iwl_trans *trans)
 911 {
 912         int ret;
 913         int txq_id, slots_num;
 914         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 915
 916         u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues *
 917                         sizeof(struct iwlagn_scd_bc_tbl);
 918
 919         /*It is not allowed to alloc twice, so warn when this happens.
 920          * We cannot rely on the previous allocation, so free and fail */
 921         if (WARN_ON(trans_pcie->txq_memory)) {
 922                 ret = -EINVAL;
 923                 goto error;
 924         }
 925
 926         ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
 927                                    scd_bc_tbls_size);
 928         if (ret) {
 929                 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
 930                 goto error;
 931         }
 932
 933         /* Alloc keep-warm buffer */
 934         ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
 935         if (ret) {
 936                 IWL_ERR(trans, "Keep Warm allocation failed\n");
 937                 goto error;
 938         }
 939
 940         trans_pcie->txq_memory = kcalloc(trans->cfg->base_params->num_of_queues,
 941                                          sizeof(struct iwl_txq), GFP_KERNEL);
 942         if (!trans_pcie->txq_memory) {
 943                 IWL_ERR(trans, "Not enough memory for txq\n");
 944                 ret = -ENOMEM;
 945                 goto error;
 946         }
 947
 948         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 949         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
 950              txq_id++) {
 951                 bool cmd_queue = (txq_id == trans_pcie->cmd_queue);
 952
 953                 slots_num = cmd_queue ? trans_pcie->tx_cmd_queue_size :
 954                         TFD_TX_CMD_SLOTS;
 955                 trans_pcie->txq[txq_id] = &trans_pcie->txq_memory[txq_id];
 956                 ret = iwl_pcie_txq_alloc(trans, trans_pcie->txq[txq_id],
 957                                          slots_num, cmd_queue);
 958                 if (ret) {
 959                         IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
 960                         goto error;
 961                 }
 962                 trans_pcie->txq[txq_id]->id = txq_id;
 963         }
 964
 965         return 0;
 966
 967 error:
 968         iwl_pcie_tx_free(trans);
 969
 970         return ret;
 971 }
 972
 973 void iwl_pcie_set_tx_cmd_queue_size(struct iwl_trans *trans)
 974 {
 975         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 976         int queue_size = TFD_CMD_SLOTS;
 977
 978         if (trans->cfg->tx_cmd_queue_size)
 979                 queue_size = trans->cfg->tx_cmd_queue_size;
 980
 981         if (WARN_ON(!(is_power_of_2(queue_size) &&
 982                       TFD_QUEUE_CB_SIZE(queue_size) > 0)))
 983                 trans_pcie->tx_cmd_queue_size = TFD_CMD_SLOTS;
 984         else
 985                 trans_pcie->tx_cmd_queue_size = queue_size;
 986 }
 987
 988 int iwl_pcie_tx_init(struct iwl_trans *trans)
 989 {
 990         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 991         int ret;
 992         int txq_id, slots_num;
 993         bool alloc = false;
 994
 995         iwl_pcie_set_tx_cmd_queue_size(trans);
 996
 997         if (!trans_pcie->txq_memory) {
 998                 ret = iwl_pcie_tx_alloc(trans);
 999                 if (ret)
1000                         goto error;
1001                 alloc = true;
1002         }
1003
1004         spin_lock(&trans_pcie->irq_lock);
1005
1006         /* Turn off all Tx DMA fifos */
1007         iwl_scd_deactivate_fifos(trans);
1008
1009         /* Tell NIC where to find the "keep warm" buffer */
1010         iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
1011                            trans_pcie->kw.dma >> 4);
1012
1013         spin_unlock(&trans_pcie->irq_lock);
1014
1015         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
1016         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
1017              txq_id++) {
1018                 bool cmd_queue = (txq_id == trans_pcie->cmd_queue);
1019
1020                 slots_num = cmd_queue ? trans_pcie->tx_cmd_queue_size :
1021                         TFD_TX_CMD_SLOTS;
1022                 ret = iwl_pcie_txq_init(trans, trans_pcie->txq[txq_id],
1023                                         slots_num, cmd_queue);
1024                 if (ret) {
1025                         IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
1026                         goto error;
1027                 }
1028
1029                 /*
1030                  * Tell nic where to find circular buffer of TFDs for a
1031                  * given Tx queue, and enable the DMA channel used for that
1032                  * queue.
1033                  * Circular buffer (TFD queue in DRAM) physical base address
1034                  */
1035                 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(trans, txq_id),
1036                                    trans_pcie->txq[txq_id]->dma_addr >> 8);
1037         }
1038
1039         iwl_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE);
1040         if (trans->cfg->base_params->num_of_queues > 20)
1041                 iwl_set_bits_prph(trans, SCD_GP_CTRL,
1042                                   SCD_GP_CTRL_ENABLE_31_QUEUES);
1043
1044         return 0;
1045 error:
1046         /*Upon error, free only if we allocated something */
1047         if (alloc)
1048                 iwl_pcie_tx_free(trans);
1049         return ret;
1050 }
1051
1052 static inline void iwl_pcie_txq_progress(struct iwl_txq *txq)
1053 {
1054         lockdep_assert_held(&txq->lock);
1055
1056         if (!txq->wd_timeout)
1057                 return;
1058
1059         /*
1060          * station is asleep and we send data - that must
1061          * be uAPSD or PS-Poll. Don't rearm the timer.
1062          */
1063         if (txq->frozen)
1064                 return;
1065
1066         /*
1067          * if empty delete timer, otherwise move timer forward
1068          * since we're making progress on this queue
1069          */
1070         if (txq->read_ptr == txq->write_ptr)
1071                 del_timer(&txq->stuck_timer);
1072         else
1073                 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
1074 }
1075
1076 /* Frees buffers until index _not_ inclusive */
1077 void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
1078                             struct sk_buff_head *skbs)
1079 {
1080         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1081         struct iwl_txq *txq = trans_pcie->txq[txq_id];
1082         int tfd_num = ssn & (TFD_QUEUE_SIZE_MAX - 1);
1083         int last_to_free;
1084
1085         /* This function is not meant to release cmd queue*/
1086         if (WARN_ON(txq_id == trans_pcie->cmd_queue))
1087                 return;
1088
1089         spin_lock_bh(&txq->lock);
1090
1091         if (!test_bit(txq_id, trans_pcie->queue_used)) {
1092                 IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n",
1093                                     txq_id, ssn);
1094                 goto out;
1095         }
1096
1097         if (txq->read_ptr == tfd_num)
1098                 goto out;
1099
1100         IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
1101                            txq_id, txq->read_ptr, tfd_num, ssn);
1102
1103         /*Since we free until index _not_ inclusive, the one before index is
1104          * the last we will free. This one must be used */
1105         last_to_free = iwl_queue_dec_wrap(tfd_num);
1106
1107         if (!iwl_queue_used(txq, last_to_free)) {
1108                 IWL_ERR(trans,
1109                         "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",
1110                         __func__, txq_id, last_to_free, TFD_QUEUE_SIZE_MAX,
1111                         txq->write_ptr, txq->read_ptr);
1112                 goto out;
1113         }
1114
1115         if (WARN_ON(!skb_queue_empty(skbs)))
1116                 goto out;
1117
1118         for (;
1119              txq->read_ptr != tfd_num;
1120              txq->read_ptr = iwl_queue_inc_wrap(txq->read_ptr)) {
1121                 int idx = iwl_pcie_get_cmd_index(txq, txq->read_ptr);
1122                 struct sk_buff *skb = txq->entries[idx].skb;
1123
1124                 if (WARN_ON_ONCE(!skb))
1125                         continue;
1126
1127                 iwl_pcie_free_tso_page(trans_pcie, skb);
1128
1129                 __skb_queue_tail(skbs, skb);
1130
1131                 txq->entries[idx].skb = NULL;
1132
1133                 if (!trans->cfg->use_tfh)
1134                         iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq);
1135
1136                 iwl_pcie_txq_free_tfd(trans, txq);
1137         }
1138
1139         iwl_pcie_txq_progress(txq);
1140
1141         if (iwl_queue_space(txq) > txq->low_mark &&
1142             test_bit(txq_id, trans_pcie->queue_stopped)) {
1143                 struct sk_buff_head overflow_skbs;
1144
1145                 __skb_queue_head_init(&overflow_skbs);
1146                 skb_queue_splice_init(&txq->overflow_q, &overflow_skbs);
1147
1148                 /*
1149                  * This is tricky: we are in reclaim path which is non
1150                  * re-entrant, so noone will try to take the access the
1151                  * txq data from that path. We stopped tx, so we can't
1152                  * have tx as well. Bottom line, we can unlock and re-lock
1153                  * later.
1154                  */
1155                 spin_unlock_bh(&txq->lock);
1156
1157                 while (!skb_queue_empty(&overflow_skbs)) {
1158                         struct sk_buff *skb = __skb_dequeue(&overflow_skbs);
1159                         struct iwl_device_cmd *dev_cmd_ptr;
1160
1161                         dev_cmd_ptr = *(void **)((u8 *)skb->cb +
1162                                                  trans_pcie->dev_cmd_offs);
1163
1164                         /*
1165                          * Note that we can very well be overflowing again.
1166                          * In that case, iwl_queue_space will be small again
1167                          * and we won't wake mac80211's queue.
1168                          */
1169                         iwl_trans_pcie_tx(trans, skb, dev_cmd_ptr, txq_id);
1170                 }
1171                 spin_lock_bh(&txq->lock);
1172
1173                 if (iwl_queue_space(txq) > txq->low_mark)
1174                         iwl_wake_queue(trans, txq);
1175         }
1176
1177         if (txq->read_ptr == txq->write_ptr) {
1178                 IWL_DEBUG_RPM(trans, "Q %d - last tx reclaimed\n", txq->id);
1179                 iwl_trans_unref(trans);
1180         }
1181
1182 out:
1183         spin_unlock_bh(&txq->lock);
1184 }
1185
1186 static int iwl_pcie_set_cmd_in_flight(struct iwl_trans *trans,
1187                                       const struct iwl_host_cmd *cmd)
1188 {
1189         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1190         int ret;
1191
1192         lockdep_assert_held(&trans_pcie->reg_lock);
1193
1194         if (!(cmd->flags & CMD_SEND_IN_IDLE) &&
1195             !trans_pcie->ref_cmd_in_flight) {
1196                 trans_pcie->ref_cmd_in_flight = true;
1197                 IWL_DEBUG_RPM(trans, "set ref_cmd_in_flight - ref\n");
1198                 iwl_trans_ref(trans);
1199         }
1200
1201         /*
1202          * wake up the NIC to make sure that the firmware will see the host
1203          * command - we will let the NIC sleep once all the host commands
1204          * returned. This needs to be done only on NICs that have
1205          * apmg_wake_up_wa set.
1206          */
1207         if (trans->cfg->base_params->apmg_wake_up_wa &&
1208             !trans_pcie->cmd_hold_nic_awake) {
1209                 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1210                                          CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1211
1212                 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1213                                    CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1214                                    (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1215                                     CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP),
1216                                    15000);
1217                 if (ret < 0) {
1218                         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1219                                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1220                         IWL_ERR(trans, "Failed to wake NIC for hcmd\n");
1221                         return -EIO;
1222                 }
1223                 trans_pcie->cmd_hold_nic_awake = true;
1224         }
1225
1226         return 0;
1227 }
1228
1229 /*
1230  * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd
1231  *
1232  * When FW advances 'R' index, all entries between old and new 'R' index
1233  * need to be reclaimed. As result, some free space forms.  If there is
1234  * enough free space (> low mark), wake the stack that feeds us.
1235  */
1236 static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx)
1237 {
1238         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1239         struct iwl_txq *txq = trans_pcie->txq[txq_id];
1240         unsigned long flags;
1241         int nfreed = 0;
1242
1243         lockdep_assert_held(&txq->lock);
1244
1245         if ((idx >= TFD_QUEUE_SIZE_MAX) || (!iwl_queue_used(txq, idx))) {
1246                 IWL_ERR(trans,
1247                         "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
1248                         __func__, txq_id, idx, TFD_QUEUE_SIZE_MAX,
1249                         txq->write_ptr, txq->read_ptr);
1250                 return;
1251         }
1252
1253         for (idx = iwl_queue_inc_wrap(idx); txq->read_ptr != idx;
1254              txq->read_ptr = iwl_queue_inc_wrap(txq->read_ptr)) {
1255
1256                 if (nfreed++ > 0) {
1257                         IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n",
1258                                 idx, txq->write_ptr, txq->read_ptr);
1259                         iwl_force_nmi(trans);
1260                 }
1261         }
1262
1263         if (txq->read_ptr == txq->write_ptr) {
1264                 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1265                 iwl_pcie_clear_cmd_in_flight(trans);
1266                 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1267         }
1268
1269         iwl_pcie_txq_progress(txq);
1270 }
1271
1272 static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid,
1273                                  u16 txq_id)
1274 {
1275         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1276         u32 tbl_dw_addr;
1277         u32 tbl_dw;
1278         u16 scd_q2ratid;
1279
1280         scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
1281
1282         tbl_dw_addr = trans_pcie->scd_base_addr +
1283                         SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
1284
1285         tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr);
1286
1287         if (txq_id & 0x1)
1288                 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1289         else
1290                 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1291
1292         iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw);
1293
1294         return 0;
1295 }
1296
1297 /* Receiver address (actually, Rx station's index into station table),
1298  * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */
1299 #define BUILD_RAxTID(sta_id, tid)       (((sta_id) << 4) + (tid))
1300
1301 bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn,
1302                                const struct iwl_trans_txq_scd_cfg *cfg,
1303                                unsigned int wdg_timeout)
1304 {
1305         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1306         struct iwl_txq *txq = trans_pcie->txq[txq_id];
1307         int fifo = -1;
1308         bool scd_bug = false;
1309
1310         if (test_and_set_bit(txq_id, trans_pcie->queue_used))
1311                 WARN_ONCE(1, "queue %d already used - expect issues", txq_id);
1312
1313         txq->wd_timeout = msecs_to_jiffies(wdg_timeout);
1314
1315         if (cfg) {
1316                 fifo = cfg->fifo;
1317
1318                 /* Disable the scheduler prior configuring the cmd queue */
1319                 if (txq_id == trans_pcie->cmd_queue &&
1320                     trans_pcie->scd_set_active)
1321                         iwl_scd_enable_set_active(trans, 0);
1322
1323                 /* Stop this Tx queue before configuring it */
1324                 iwl_scd_txq_set_inactive(trans, txq_id);
1325
1326                 /* Set this queue as a chain-building queue unless it is CMD */
1327                 if (txq_id != trans_pcie->cmd_queue)
1328                         iwl_scd_txq_set_chain(trans, txq_id);
1329
1330                 if (cfg->aggregate) {
1331                         u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid);
1332
1333                         /* Map receiver-address / traffic-ID to this queue */
1334                         iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id);
1335
1336                         /* enable aggregations for the queue */
1337                         iwl_scd_txq_enable_agg(trans, txq_id);
1338                         txq->ampdu = true;
1339                 } else {
1340                         /*
1341                          * disable aggregations for the queue, this will also
1342                          * make the ra_tid mapping configuration irrelevant
1343                          * since it is now a non-AGG queue.
1344                          */
1345                         iwl_scd_txq_disable_agg(trans, txq_id);
1346
1347                         ssn = txq->read_ptr;
1348                 }
1349         } else {
1350                 /*
1351                  * If we need to move the SCD write pointer by steps of
1352                  * 0x40, 0x80 or 0xc0, it gets stuck. Avoids this and let
1353                  * the op_mode know by returning true later.
1354                  * Do this only in case cfg is NULL since this trick can
1355                  * be done only if we have DQA enabled which is true for mvm
1356                  * only. And mvm never sets a cfg pointer.
1357                  * This is really ugly, but this is the easiest way out for
1358                  * this sad hardware issue.
1359                  * This bug has been fixed on devices 9000 and up.
1360                  */
1361                 scd_bug = !trans->cfg->mq_rx_supported &&
1362                         !((ssn - txq->write_ptr) & 0x3f) &&
1363                         (ssn != txq->write_ptr);
1364                 if (scd_bug)
1365                         ssn++;
1366         }
1367
1368         /* Place first TFD at index corresponding to start sequence number.
1369          * Assumes that ssn_idx is valid (!= 0xFFF) */
1370         txq->read_ptr = (ssn & 0xff);
1371         txq->write_ptr = (ssn & 0xff);
1372         iwl_write_direct32(trans, HBUS_TARG_WRPTR,
1373                            (ssn & 0xff) | (txq_id << 8));
1374
1375         if (cfg) {
1376                 u8 frame_limit = cfg->frame_limit;
1377
1378                 iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);
1379
1380                 /* Set up Tx window size and frame limit for this queue */
1381                 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
1382                                 SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0);
1383                 iwl_trans_write_mem32(trans,
1384                         trans_pcie->scd_base_addr +
1385                         SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1386                         SCD_QUEUE_CTX_REG2_VAL(WIN_SIZE, frame_limit) |
1387                         SCD_QUEUE_CTX_REG2_VAL(FRAME_LIMIT, frame_limit));
1388
1389                 /* Set up status area in SRAM, map to Tx DMA/FIFO, activate */
1390                 iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
1391                                (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1392                                (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) |
1393                                (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
1394                                SCD_QUEUE_STTS_REG_MSK);
1395
1396                 /* enable the scheduler for this queue (only) */
1397                 if (txq_id == trans_pcie->cmd_queue &&
1398                     trans_pcie->scd_set_active)
1399                         iwl_scd_enable_set_active(trans, BIT(txq_id));
1400
1401                 IWL_DEBUG_TX_QUEUES(trans,
1402                                     "Activate queue %d on FIFO %d WrPtr: %d\n",
1403                                     txq_id, fifo, ssn & 0xff);
1404         } else {
1405                 IWL_DEBUG_TX_QUEUES(trans,
1406                                     "Activate queue %d WrPtr: %d\n",
1407                                     txq_id, ssn & 0xff);
1408         }
1409
1410         return scd_bug;
1411 }
1412
1413 void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id,
1414                                         bool shared_mode)
1415 {
1416         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1417         struct iwl_txq *txq = trans_pcie->txq[txq_id];
1418
1419         txq->ampdu = !shared_mode;
1420 }
1421
1422 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id,
1423                                 bool configure_scd)
1424 {
1425         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1426         u32 stts_addr = trans_pcie->scd_base_addr +
1427                         SCD_TX_STTS_QUEUE_OFFSET(txq_id);
1428         static const u32 zero_val[4] = {};
1429
1430         trans_pcie->txq[txq_id]->frozen_expiry_remainder = 0;
1431         trans_pcie->txq[txq_id]->frozen = false;
1432
1433         /*
1434          * Upon HW Rfkill - we stop the device, and then stop the queues
1435          * in the op_mode. Just for the sake of the simplicity of the op_mode,
1436          * allow the op_mode to call txq_disable after it already called
1437          * stop_device.
1438          */
1439         if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) {
1440                 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status),
1441                           "queue %d not used", txq_id);
1442                 return;
1443         }
1444
1445         if (configure_scd) {
1446                 iwl_scd_txq_set_inactive(trans, txq_id);
1447
1448                 iwl_trans_write_mem(trans, stts_addr, (void *)zero_val,
1449                                     ARRAY_SIZE(zero_val));
1450         }
1451
1452         iwl_pcie_txq_unmap(trans, txq_id);
1453         trans_pcie->txq[txq_id]->ampdu = false;
1454
1455         IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id);
1456 }
1457
1458 /*************** HOST COMMAND QUEUE FUNCTIONS   *****/
1459
1460 /*
1461  * iwl_pcie_enqueue_hcmd - enqueue a uCode command
1462  * @priv: device private data point
1463  * @cmd: a pointer to the ucode command structure
1464  *
1465  * The function returns < 0 values to indicate the operation
1466  * failed. On success, it returns the index (>= 0) of command in the
1467  * command queue.
1468  */
1469 static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
1470                                  struct iwl_host_cmd *cmd)
1471 {
1472         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1473         struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
1474         struct iwl_device_cmd *out_cmd;
1475         struct iwl_cmd_meta *out_meta;
1476         unsigned long flags;
1477         void *dup_buf = NULL;
1478         dma_addr_t phys_addr;
1479         int idx;
1480         u16 copy_size, cmd_size, tb0_size;
1481         bool had_nocopy = false;
1482         u8 group_id = iwl_cmd_groupid(cmd->id);
1483         int i, ret;
1484         u32 cmd_pos;
1485         const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD];
1486         u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD];
1487
1488         if (WARN(!trans->wide_cmd_header &&
1489                  group_id > IWL_ALWAYS_LONG_GROUP,
1490                  "unsupported wide command %#x\n", cmd->id))
1491                 return -EINVAL;
1492
1493         if (group_id != 0) {
1494                 copy_size = sizeof(struct iwl_cmd_header_wide);
1495                 cmd_size = sizeof(struct iwl_cmd_header_wide);
1496         } else {
1497                 copy_size = sizeof(struct iwl_cmd_header);
1498                 cmd_size = sizeof(struct iwl_cmd_header);
1499         }
1500
1501         /* need one for the header if the first is NOCOPY */
1502         BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1);
1503
1504         for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1505                 cmddata[i] = cmd->data[i];
1506                 cmdlen[i] = cmd->len[i];
1507
1508                 if (!cmd->len[i])
1509                         continue;
1510
1511                 /* need at least IWL_FIRST_TB_SIZE copied */
1512                 if (copy_size < IWL_FIRST_TB_SIZE) {
1513                         int copy = IWL_FIRST_TB_SIZE - copy_size;
1514
1515                         if (copy > cmdlen[i])
1516                                 copy = cmdlen[i];
1517                         cmdlen[i] -= copy;
1518                         cmddata[i] += copy;
1519                         copy_size += copy;
1520                 }
1521
1522                 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
1523                         had_nocopy = true;
1524                         if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) {
1525                                 idx = -EINVAL;
1526                                 goto free_dup_buf;
1527                         }
1528                 } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) {
1529                         /*
1530                          * This is also a chunk that isn't copied
1531                          * to the static buffer so set had_nocopy.
1532                          */
1533                         had_nocopy = true;
1534
1535                         /* only allowed once */
1536                         if (WARN_ON(dup_buf)) {
1537                                 idx = -EINVAL;
1538                                 goto free_dup_buf;
1539                         }
1540
1541                         dup_buf = kmemdup(cmddata[i], cmdlen[i],
1542                                           GFP_ATOMIC);
1543                         if (!dup_buf)
1544                                 return -ENOMEM;
1545                 } else {
1546                         /* NOCOPY must not be followed by normal! */
1547                         if (WARN_ON(had_nocopy)) {
1548                                 idx = -EINVAL;
1549                                 goto free_dup_buf;
1550                         }
1551                         copy_size += cmdlen[i];
1552                 }
1553                 cmd_size += cmd->len[i];
1554         }
1555
1556         /*
1557          * If any of the command structures end up being larger than
1558          * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
1559          * allocated into separate TFDs, then we will need to
1560          * increase the size of the buffers.
1561          */
1562         if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE,
1563                  "Command %s (%#x) is too large (%d bytes)\n",
1564                  iwl_get_cmd_string(trans, cmd->id),
1565                  cmd->id, copy_size)) {
1566                 idx = -EINVAL;
1567                 goto free_dup_buf;
1568         }
1569
1570         spin_lock_bh(&txq->lock);
1571
1572         if (iwl_queue_space(txq) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
1573                 spin_unlock_bh(&txq->lock);
1574
1575                 IWL_ERR(trans, "No space in command queue\n");
1576                 iwl_op_mode_cmd_queue_full(trans->op_mode);
1577                 idx = -ENOSPC;
1578                 goto free_dup_buf;
1579         }
1580
1581         idx = iwl_pcie_get_cmd_index(txq, txq->write_ptr);
1582         out_cmd = txq->entries[idx].cmd;
1583         out_meta = &txq->entries[idx].meta;
1584
1585         memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
1586         if (cmd->flags & CMD_WANT_SKB)
1587                 out_meta->source = cmd;
1588
1589         /* set up the header */
1590         if (group_id != 0) {
1591                 out_cmd->hdr_wide.cmd = iwl_cmd_opcode(cmd->id);
1592                 out_cmd->hdr_wide.group_id = group_id;
1593                 out_cmd->hdr_wide.version = iwl_cmd_version(cmd->id);
1594                 out_cmd->hdr_wide.length =
1595                         cpu_to_le16(cmd_size -
1596                                     sizeof(struct iwl_cmd_header_wide));
1597                 out_cmd->hdr_wide.reserved = 0;
1598                 out_cmd->hdr_wide.sequence =
1599                         cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1600                                                  INDEX_TO_SEQ(txq->write_ptr));
1601
1602                 cmd_pos = sizeof(struct iwl_cmd_header_wide);
1603                 copy_size = sizeof(struct iwl_cmd_header_wide);
1604         } else {
1605                 out_cmd->hdr.cmd = iwl_cmd_opcode(cmd->id);
1606                 out_cmd->hdr.sequence =
1607                         cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1608                                                  INDEX_TO_SEQ(txq->write_ptr));
1609                 out_cmd->hdr.group_id = 0;
1610
1611                 cmd_pos = sizeof(struct iwl_cmd_header);
1612                 copy_size = sizeof(struct iwl_cmd_header);
1613         }
1614
1615         /* and copy the data that needs to be copied */
1616         for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1617                 int copy;
1618
1619                 if (!cmd->len[i])
1620                         continue;
1621
1622                 /* copy everything if not nocopy/dup */
1623                 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1624                                            IWL_HCMD_DFL_DUP))) {
1625                         copy = cmd->len[i];
1626
1627                         memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1628                         cmd_pos += copy;
1629                         copy_size += copy;
1630                         continue;
1631                 }
1632
1633                 /*
1634                  * Otherwise we need at least IWL_FIRST_TB_SIZE copied
1635                  * in total (for bi-directional DMA), but copy up to what
1636                  * we can fit into the payload for debug dump purposes.
1637                  */
1638                 copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]);
1639
1640                 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1641                 cmd_pos += copy;
1642
1643                 /* However, treat copy_size the proper way, we need it below */
1644                 if (copy_size < IWL_FIRST_TB_SIZE) {
1645                         copy = IWL_FIRST_TB_SIZE - copy_size;
1646
1647                         if (copy > cmd->len[i])
1648                                 copy = cmd->len[i];
1649                         copy_size += copy;
1650                 }
1651         }
1652
1653         IWL_DEBUG_HC(trans,
1654                      "Sending command %s (%.2x.%.2x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
1655                      iwl_get_cmd_string(trans, cmd->id),
1656                      group_id, out_cmd->hdr.cmd,
1657                      le16_to_cpu(out_cmd->hdr.sequence),
1658                      cmd_size, txq->write_ptr, idx, trans_pcie->cmd_queue);
1659
1660         /* start the TFD with the minimum copy bytes */
1661         tb0_size = min_t(int, copy_size, IWL_FIRST_TB_SIZE);
1662         memcpy(&txq->first_tb_bufs[idx], &out_cmd->hdr, tb0_size);
1663         iwl_pcie_txq_build_tfd(trans, txq,
1664                                iwl_pcie_get_first_tb_dma(txq, idx),
1665                                tb0_size, true);
1666
1667         /* map first command fragment, if any remains */
1668         if (copy_size > tb0_size) {
1669                 phys_addr = dma_map_single(trans->dev,
1670                                            ((u8 *)&out_cmd->hdr) + tb0_size,
1671                                            copy_size - tb0_size,
1672                                            DMA_TO_DEVICE);
1673                 if (dma_mapping_error(trans->dev, phys_addr)) {
1674                         iwl_pcie_tfd_unmap(trans, out_meta, txq,
1675                                            txq->write_ptr);
1676                         idx = -ENOMEM;
1677                         goto out;
1678                 }
1679
1680                 iwl_pcie_txq_build_tfd(trans, txq, phys_addr,
1681                                        copy_size - tb0_size, false);
1682         }
1683
1684         /* map the remaining (adjusted) nocopy/dup fragments */
1685         for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1686                 const void *data = cmddata[i];
1687
1688                 if (!cmdlen[i])
1689                         continue;
1690                 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1691                                            IWL_HCMD_DFL_DUP)))
1692                         continue;
1693                 if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP)
1694                         data = dup_buf;
1695                 phys_addr = dma_map_single(trans->dev, (void *)data,
1696                                            cmdlen[i], DMA_TO_DEVICE);
1697                 if (dma_mapping_error(trans->dev, phys_addr)) {
1698                         iwl_pcie_tfd_unmap(trans, out_meta, txq,
1699                                            txq->write_ptr);
1700                         idx = -ENOMEM;
1701                         goto out;
1702                 }
1703
1704                 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false);
1705         }
1706
1707         BUILD_BUG_ON(IWL_TFH_NUM_TBS > sizeof(out_meta->tbs) * BITS_PER_BYTE);
1708         out_meta->flags = cmd->flags;
1709         if (WARN_ON_ONCE(txq->entries[idx].free_buf))
1710                 kzfree(txq->entries[idx].free_buf);
1711         txq->entries[idx].free_buf = dup_buf;
1712
1713         trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr_wide);
1714
1715         /* start timer if queue currently empty */
1716         if (txq->read_ptr == txq->write_ptr && txq->wd_timeout)
1717                 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
1718
1719         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1720         ret = iwl_pcie_set_cmd_in_flight(trans, cmd);
1721         if (ret < 0) {
1722                 idx = ret;
1723                 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1724                 goto out;
1725         }
1726
1727         /* Increment and update queue's write index */
1728         txq->write_ptr = iwl_queue_inc_wrap(txq->write_ptr);
1729         iwl_pcie_txq_inc_wr_ptr(trans, txq);
1730
1731         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1732
1733  out:
1734         spin_unlock_bh(&txq->lock);
1735  free_dup_buf:
1736         if (idx < 0)
1737                 kfree(dup_buf);
1738         return idx;
1739 }
1740
1741 /*
1742  * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them
1743  * @rxb: Rx buffer to reclaim
1744  */
1745 void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
1746                             struct iwl_rx_cmd_buffer *rxb)
1747 {
1748         struct iwl_rx_packet *pkt = rxb_addr(rxb);
1749         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1750         u8 group_id;
1751         u32 cmd_id;
1752         int txq_id = SEQ_TO_QUEUE(sequence);
1753         int index = SEQ_TO_INDEX(sequence);
1754         int cmd_index;
1755         struct iwl_device_cmd *cmd;
1756         struct iwl_cmd_meta *meta;
1757         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1758         struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
1759
1760         /* If a Tx command is being handled and it isn't in the actual
1761          * command queue then there a command routing bug has been introduced
1762          * in the queue management code. */
1763         if (WARN(txq_id != trans_pcie->cmd_queue,
1764                  "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
1765                  txq_id, trans_pcie->cmd_queue, sequence, txq->read_ptr,
1766                  txq->write_ptr)) {
1767                 iwl_print_hex_error(trans, pkt, 32);
1768                 return;
1769         }
1770
1771         spin_lock_bh(&txq->lock);
1772
1773         cmd_index = iwl_pcie_get_cmd_index(txq, index);
1774         cmd = txq->entries[cmd_index].cmd;
1775         meta = &txq->entries[cmd_index].meta;
1776         group_id = cmd->hdr.group_id;
1777         cmd_id = iwl_cmd_id(cmd->hdr.cmd, group_id, 0);
1778
1779         iwl_pcie_tfd_unmap(trans, meta, txq, index);
1780
1781         /* Input error checking is done when commands are added to queue. */
1782         if (meta->flags & CMD_WANT_SKB) {
1783                 struct page *p = rxb_steal_page(rxb);
1784
1785                 meta->source->resp_pkt = pkt;
1786                 meta->source->_rx_page_addr = (unsigned long)page_address(p);
1787                 meta->source->_rx_page_order = trans_pcie->rx_page_order;
1788         }
1789
1790         if (meta->flags & CMD_WANT_ASYNC_CALLBACK)
1791                 iwl_op_mode_async_cb(trans->op_mode, cmd);
1792
1793         iwl_pcie_cmdq_reclaim(trans, txq_id, index);
1794
1795         if (!(meta->flags & CMD_ASYNC)) {
1796                 if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) {
1797                         IWL_WARN(trans,
1798                                  "HCMD_ACTIVE already clear for command %s\n",
1799                                  iwl_get_cmd_string(trans, cmd_id));
1800                 }
1801                 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1802                 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1803                                iwl_get_cmd_string(trans, cmd_id));
1804                 wake_up(&trans_pcie->wait_command_queue);
1805         }
1806
1807         if (meta->flags & CMD_MAKE_TRANS_IDLE) {
1808                 IWL_DEBUG_INFO(trans, "complete %s - mark trans as idle\n",
1809                                iwl_get_cmd_string(trans, cmd->hdr.cmd));
1810                 set_bit(STATUS_TRANS_IDLE, &trans->status);
1811                 wake_up(&trans_pcie->d0i3_waitq);
1812         }
1813
1814         if (meta->flags & CMD_WAKE_UP_TRANS) {
1815                 IWL_DEBUG_INFO(trans, "complete %s - clear trans idle flag\n",
1816                                iwl_get_cmd_string(trans, cmd->hdr.cmd));
1817                 clear_bit(STATUS_TRANS_IDLE, &trans->status);
1818                 wake_up(&trans_pcie->d0i3_waitq);
1819         }
1820
1821         meta->flags = 0;
1822
1823         spin_unlock_bh(&txq->lock);
1824 }
1825
1826 #define HOST_COMPLETE_TIMEOUT   (2 * HZ)
1827
1828 static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans,
1829                                     struct iwl_host_cmd *cmd)
1830 {
1831         int ret;
1832
1833         /* An asynchronous command can not expect an SKB to be set. */
1834         if (WARN_ON(cmd->flags & CMD_WANT_SKB))
1835                 return -EINVAL;
1836
1837         ret = iwl_pcie_enqueue_hcmd(trans, cmd);
1838         if (ret < 0) {
1839                 IWL_ERR(trans,
1840                         "Error sending %s: enqueue_hcmd failed: %d\n",
1841                         iwl_get_cmd_string(trans, cmd->id), ret);
1842                 return ret;
1843         }
1844         return 0;
1845 }
1846
1847 static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans,
1848                                    struct iwl_host_cmd *cmd)
1849 {
1850         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1851         struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
1852         int cmd_idx;
1853         int ret;
1854
1855         IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n",
1856                        iwl_get_cmd_string(trans, cmd->id));
1857
1858         if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE,
1859                                   &trans->status),
1860                  "Command %s: a command is already active!\n",
1861                  iwl_get_cmd_string(trans, cmd->id)))
1862                 return -EIO;
1863
1864         IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n",
1865                        iwl_get_cmd_string(trans, cmd->id));
1866
1867         if (pm_runtime_suspended(&trans_pcie->pci_dev->dev)) {
1868                 ret = wait_event_timeout(trans_pcie->d0i3_waitq,
1869                                  pm_runtime_active(&trans_pcie->pci_dev->dev),
1870                                  msecs_to_jiffies(IWL_TRANS_IDLE_TIMEOUT));
1871                 if (!ret) {
1872                         IWL_ERR(trans, "Timeout exiting D0i3 before hcmd\n");
1873                         return -ETIMEDOUT;
1874                 }
1875         }
1876
1877         cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd);
1878         if (cmd_idx < 0) {
1879                 ret = cmd_idx;
1880                 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1881                 IWL_ERR(trans,
1882                         "Error sending %s: enqueue_hcmd failed: %d\n",
1883                         iwl_get_cmd_string(trans, cmd->id), ret);
1884                 return ret;
1885         }
1886
1887         ret = wait_event_timeout(trans_pcie->wait_command_queue,
1888                                  !test_bit(STATUS_SYNC_HCMD_ACTIVE,
1889                                            &trans->status),
1890                                  HOST_COMPLETE_TIMEOUT);
1891         if (!ret) {
1892                 IWL_ERR(trans, "Error sending %s: time out after %dms.\n",
1893                         iwl_get_cmd_string(trans, cmd->id),
1894                         jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
1895
1896                 IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n",
1897                         txq->read_ptr, txq->write_ptr);
1898
1899                 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1900                 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1901                                iwl_get_cmd_string(trans, cmd->id));
1902                 ret = -ETIMEDOUT;
1903
1904                 iwl_force_nmi(trans);
1905                 iwl_trans_fw_error(trans);
1906
1907                 goto cancel;
1908         }
1909
1910         if (test_bit(STATUS_FW_ERROR, &trans->status)) {
1911                 iwl_trans_dump_regs(trans);
1912                 IWL_ERR(trans, "FW error in SYNC CMD %s\n",
1913                         iwl_get_cmd_string(trans, cmd->id));
1914                 dump_stack();
1915                 ret = -EIO;
1916                 goto cancel;
1917         }
1918
1919         if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1920             test_bit(STATUS_RFKILL_OPMODE, &trans->status)) {
1921                 IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n");
1922                 ret = -ERFKILL;
1923                 goto cancel;
1924         }
1925
1926         if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) {
1927                 IWL_ERR(trans, "Error: Response NULL in '%s'\n",
1928                         iwl_get_cmd_string(trans, cmd->id));
1929                 ret = -EIO;
1930                 goto cancel;
1931         }
1932
1933         return 0;
1934
1935 cancel:
1936         if (cmd->flags & CMD_WANT_SKB) {
1937                 /*
1938                  * Cancel the CMD_WANT_SKB flag for the cmd in the
1939                  * TX cmd queue. Otherwise in case the cmd comes
1940                  * in later, it will possibly set an invalid
1941                  * address (cmd->meta.source).
1942                  */
1943                 txq->entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB;
1944         }
1945
1946         if (cmd->resp_pkt) {
1947                 iwl_free_resp(cmd);
1948                 cmd->resp_pkt = NULL;
1949         }
1950
1951         return ret;
1952 }
1953
1954 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
1955 {
1956         if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1957             test_bit(STATUS_RFKILL_OPMODE, &trans->status)) {
1958                 IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n",
1959                                   cmd->id);
1960                 return -ERFKILL;
1961         }
1962
1963         if (cmd->flags & CMD_ASYNC)
1964                 return iwl_pcie_send_hcmd_async(trans, cmd);
1965
1966         /* We still can fail on RFKILL that can be asserted while we wait */
1967         return iwl_pcie_send_hcmd_sync(trans, cmd);
1968 }
1969
1970 static int iwl_fill_data_tbs(struct iwl_trans *trans, struct sk_buff *skb,
1971                              struct iwl_txq *txq, u8 hdr_len,
1972                              struct iwl_cmd_meta *out_meta,
1973                              struct iwl_device_cmd *dev_cmd, u16 tb1_len)
1974 {
1975         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1976         u16 tb2_len;
1977         int i;
1978
1979         /*
1980          * Set up TFD's third entry to point directly to remainder
1981          * of skb's head, if any
1982          */
1983         tb2_len = skb_headlen(skb) - hdr_len;
1984
1985         if (tb2_len > 0) {
1986                 dma_addr_t tb2_phys = dma_map_single(trans->dev,
1987                                                      skb->data + hdr_len,
1988                                                      tb2_len, DMA_TO_DEVICE);
1989                 if (unlikely(dma_mapping_error(trans->dev, tb2_phys))) {
1990                         iwl_pcie_tfd_unmap(trans, out_meta, txq,
1991                                            txq->write_ptr);
1992                         return -EINVAL;
1993                 }
1994                 iwl_pcie_txq_build_tfd(trans, txq, tb2_phys, tb2_len, false);
1995         }
1996
1997         /* set up the remaining entries to point to the data */
1998         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1999                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2000                 dma_addr_t tb_phys;
2001                 int tb_idx;
2002
2003                 if (!skb_frag_size(frag))
2004                         continue;
2005
2006                 tb_phys = skb_frag_dma_map(trans->dev, frag, 0,
2007                                            skb_frag_size(frag), DMA_TO_DEVICE);
2008
2009                 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) {
2010                         iwl_pcie_tfd_unmap(trans, out_meta, txq,
2011                                            txq->write_ptr);
2012                         return -EINVAL;
2013                 }
2014                 tb_idx = iwl_pcie_txq_build_tfd(trans, txq, tb_phys,
2015                                                 skb_frag_size(frag), false);
2016
2017                 out_meta->tbs |= BIT(tb_idx);
2018         }
2019
2020         trace_iwlwifi_dev_tx(trans->dev, skb,
2021                              iwl_pcie_get_tfd(trans, txq, txq->write_ptr),
2022                              trans_pcie->tfd_size,
2023                              &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len,
2024                              hdr_len);
2025         trace_iwlwifi_dev_tx_data(trans->dev, skb, hdr_len);
2026         return 0;
2027 }
2028
2029 #ifdef CONFIG_INET
2030 struct iwl_tso_hdr_page *get_page_hdr(struct iwl_trans *trans, size_t len)
2031 {
2032         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2033         struct iwl_tso_hdr_page *p = this_cpu_ptr(trans_pcie->tso_hdr_page);
2034
2035         if (!p->page)
2036                 goto alloc;
2037
2038         /* enough room on this page */
2039         if (p->pos + len < (u8 *)page_address(p->page) + PAGE_SIZE)
2040                 return p;
2041
2042         /* We don't have enough room on this page, get a new one. */
2043         __free_page(p->page);
2044
2045 alloc:
2046         p->page = alloc_page(GFP_ATOMIC);
2047         if (!p->page)
2048                 return NULL;
2049         p->pos = page_address(p->page);
2050         return p;
2051 }
2052
2053 static void iwl_compute_pseudo_hdr_csum(void *iph, struct tcphdr *tcph,
2054                                         bool ipv6, unsigned int len)
2055 {
2056         if (ipv6) {
2057                 struct ipv6hdr *iphv6 = iph;
2058
2059                 tcph->check = ~csum_ipv6_magic(&iphv6->saddr, &iphv6->daddr,
2060                                                len + tcph->doff * 4,
2061                                                IPPROTO_TCP, 0);
2062         } else {
2063                 struct iphdr *iphv4 = iph;
2064
2065                 ip_send_check(iphv4);
2066                 tcph->check = ~csum_tcpudp_magic(iphv4->saddr, iphv4->daddr,
2067                                                  len + tcph->doff * 4,
2068                                                  IPPROTO_TCP, 0);
2069         }
2070 }
2071
2072 static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb,
2073                                    struct iwl_txq *txq, u8 hdr_len,
2074                                    struct iwl_cmd_meta *out_meta,
2075                                    struct iwl_device_cmd *dev_cmd, u16 tb1_len)
2076 {
2077         struct iwl_tx_cmd *tx_cmd = (void *)dev_cmd->payload;
2078         struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
2079         struct ieee80211_hdr *hdr = (void *)skb->data;
2080         unsigned int snap_ip_tcp_hdrlen, ip_hdrlen, total_len, hdr_room;
2081         unsigned int mss = skb_shinfo(skb)->gso_size;
2082         u16 length, iv_len, amsdu_pad;
2083         u8 *start_hdr;
2084         struct iwl_tso_hdr_page *hdr_page;
2085         struct page **page_ptr;
2086         int ret;
2087         struct tso_t tso;
2088
2089         /* if the packet is protected, then it must be CCMP or GCMP */
2090         BUILD_BUG_ON(IEEE80211_CCMP_HDR_LEN != IEEE80211_GCMP_HDR_LEN);
2091         iv_len = ieee80211_has_protected(hdr->frame_control) ?
2092                 IEEE80211_CCMP_HDR_LEN : 0;
2093
2094         trace_iwlwifi_dev_tx(trans->dev, skb,
2095                              iwl_pcie_get_tfd(trans, txq, txq->write_ptr),
2096                              trans_pcie->tfd_size,
2097                              &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len, 0);
2098
2099         ip_hdrlen = skb_transport_header(skb) - skb_network_header(skb);
2100         snap_ip_tcp_hdrlen = 8 + ip_hdrlen + tcp_hdrlen(skb);
2101         total_len = skb->len - snap_ip_tcp_hdrlen - hdr_len - iv_len;
2102         amsdu_pad = 0;
2103
2104         /* total amount of header we may need for this A-MSDU */
2105         hdr_room = DIV_ROUND_UP(total_len, mss) *
2106                 (3 + snap_ip_tcp_hdrlen + sizeof(struct ethhdr)) + iv_len;
2107
2108         /* Our device supports 9 segments at most, it will fit in 1 page */
2109         hdr_page = get_page_hdr(trans, hdr_room);
2110         if (!hdr_page)
2111                 return -ENOMEM;
2112
2113         get_page(hdr_page->page);
2114         start_hdr = hdr_page->pos;
2115         page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs);
2116         *page_ptr = hdr_page->page;
2117         memcpy(hdr_page->pos, skb->data + hdr_len, iv_len);
2118         hdr_page->pos += iv_len;
2119
2120         /*
2121          * Pull the ieee80211 header + IV to be able to use TSO core,
2122          * we will restore it for the tx_status flow.
2123          */
2124         skb_pull(skb, hdr_len + iv_len);
2125
2126         /*
2127          * Remove the length of all the headers that we don't actually
2128          * have in the MPDU by themselves, but that we duplicate into
2129          * all the different MSDUs inside the A-MSDU.
2130          */
2131         le16_add_cpu(&tx_cmd->len, -snap_ip_tcp_hdrlen);
2132
2133         tso_start(skb, &tso);
2134
2135         while (total_len) {
2136                 /* this is the data left for this subframe */
2137                 unsigned int data_left =
2138                         min_t(unsigned int, mss, total_len);
2139                 struct sk_buff *csum_skb = NULL;
2140                 unsigned int hdr_tb_len;
2141                 dma_addr_t hdr_tb_phys;
2142                 struct tcphdr *tcph;
2143                 u8 *iph, *subf_hdrs_start = hdr_page->pos;
2144
2145                 total_len -= data_left;
2146
2147                 memset(hdr_page->pos, 0, amsdu_pad);
2148                 hdr_page->pos += amsdu_pad;
2149                 amsdu_pad = (4 - (sizeof(struct ethhdr) + snap_ip_tcp_hdrlen +
2150                                   data_left)) & 0x3;
2151                 ether_addr_copy(hdr_page->pos, ieee80211_get_DA(hdr));
2152                 hdr_page->pos += ETH_ALEN;
2153                 ether_addr_copy(hdr_page->pos, ieee80211_get_SA(hdr));
2154                 hdr_page->pos += ETH_ALEN;
2155
2156                 length = snap_ip_tcp_hdrlen + data_left;
2157                 *((__be16 *)hdr_page->pos) = cpu_to_be16(length);
2158                 hdr_page->pos += sizeof(length);
2159
2160                 /*
2161                  * This will copy the SNAP as well which will be considered
2162                  * as MAC header.
2163                  */
2164                 tso_build_hdr(skb, hdr_page->pos, &tso, data_left, !total_len);
2165                 iph = hdr_page->pos + 8;
2166                 tcph = (void *)(iph + ip_hdrlen);
2167
2168                 /* For testing on current hardware only */
2169                 if (trans_pcie->sw_csum_tx) {
2170                         csum_skb = alloc_skb(data_left + tcp_hdrlen(skb),
2171                                              GFP_ATOMIC);
2172                         if (!csum_skb) {
2173                                 ret = -ENOMEM;
2174                                 goto out_unmap;
2175                         }
2176
2177                         iwl_compute_pseudo_hdr_csum(iph, tcph,
2178                                                     skb->protocol ==
2179                                                         htons(ETH_P_IPV6),
2180                                                     data_left);
2181
2182                         skb_put_data(csum_skb, tcph, tcp_hdrlen(skb));
2183                         skb_reset_transport_header(csum_skb);
2184                         csum_skb->csum_start =
2185                                 (unsigned char *)tcp_hdr(csum_skb) -
2186                                                  csum_skb->head;
2187                 }
2188
2189                 hdr_page->pos += snap_ip_tcp_hdrlen;
2190
2191                 hdr_tb_len = hdr_page->pos - start_hdr;
2192                 hdr_tb_phys = dma_map_single(trans->dev, start_hdr,
2193                                              hdr_tb_len, DMA_TO_DEVICE);
2194                 if (unlikely(dma_mapping_error(trans->dev, hdr_tb_phys))) {
2195                         dev_kfree_skb(csum_skb);
2196                         ret = -EINVAL;
2197                         goto out_unmap;
2198                 }
2199                 iwl_pcie_txq_build_tfd(trans, txq, hdr_tb_phys,
2200                                        hdr_tb_len, false);
2201                 trace_iwlwifi_dev_tx_tso_chunk(trans->dev, start_hdr,
2202                                                hdr_tb_len);
2203                 /* add this subframe's headers' length to the tx_cmd */
2204                 le16_add_cpu(&tx_cmd->len, hdr_page->pos - subf_hdrs_start);
2205
2206                 /* prepare the start_hdr for the next subframe */
2207                 start_hdr = hdr_page->pos;
2208
2209                 /* put the payload */
2210                 while (data_left) {
2211                         unsigned int size = min_t(unsigned int, tso.size,
2212                                                   data_left);
2213                         dma_addr_t tb_phys;
2214
2215                         if (trans_pcie->sw_csum_tx)
2216                                 skb_put_data(csum_skb, tso.data, size);
2217
2218                         tb_phys = dma_map_single(trans->dev, tso.data,
2219                                                  size, DMA_TO_DEVICE);
2220                         if (unlikely(dma_mapping_error(trans->dev, tb_phys))) {
2221                                 dev_kfree_skb(csum_skb);
2222                                 ret = -EINVAL;
2223                                 goto out_unmap;
2224                         }
2225
2226                         iwl_pcie_txq_build_tfd(trans, txq, tb_phys,
2227                                                size, false);
2228                         trace_iwlwifi_dev_tx_tso_chunk(trans->dev, tso.data,
2229                                                        size);
2230
2231                         data_left -= size;
2232                         tso_build_data(skb, &tso, size);
2233                 }
2234
2235                 /* For testing on early hardware only */
2236                 if (trans_pcie->sw_csum_tx) {
2237                         __wsum csum;
2238
2239                         csum = skb_checksum(csum_skb,
2240                                             skb_checksum_start_offset(csum_skb),
2241                                             csum_skb->len -
2242                                             skb_checksum_start_offset(csum_skb),
2243                                             0);
2244                         dev_kfree_skb(csum_skb);
2245                         dma_sync_single_for_cpu(trans->dev, hdr_tb_phys,
2246                                                 hdr_tb_len, DMA_TO_DEVICE);
2247                         tcph->check = csum_fold(csum);
2248                         dma_sync_single_for_device(trans->dev, hdr_tb_phys,
2249                                                    hdr_tb_len, DMA_TO_DEVICE);
2250                 }
2251         }
2252
2253         /* re -add the WiFi header and IV */
2254         skb_push(skb, hdr_len + iv_len);
2255
2256         return 0;
2257
2258 out_unmap:
2259         iwl_pcie_tfd_unmap(trans, out_meta, txq, txq->write_ptr);
2260         return ret;
2261 }
2262 #else /* CONFIG_INET */
2263 static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb,
2264                                    struct iwl_txq *txq, u8 hdr_len,
2265                                    struct iwl_cmd_meta *out_meta,
2266                                    struct iwl_device_cmd *dev_cmd, u16 tb1_len)
2267 {
2268         /* No A-MSDU without CONFIG_INET */
2269         WARN_ON(1);
2270
2271         return -1;
2272 }
2273 #endif /* CONFIG_INET */
2274
2275 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
2276                       struct iwl_device_cmd *dev_cmd, int txq_id)
2277 {
2278         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2279         struct ieee80211_hdr *hdr;
2280         struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload;
2281         struct iwl_cmd_meta *out_meta;
2282         struct iwl_txq *txq;
2283         dma_addr_t tb0_phys, tb1_phys, scratch_phys;
2284         void *tb1_addr;
2285         void *tfd;
2286         u16 len, tb1_len;
2287         bool wait_write_ptr;
2288         __le16 fc;
2289         u8 hdr_len;
2290         u16 wifi_seq;
2291         bool amsdu;
2292
2293         txq = trans_pcie->txq[txq_id];
2294
2295         if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used),
2296                       "TX on unused queue %d\n", txq_id))
2297                 return -EINVAL;
2298
2299         if (unlikely(trans_pcie->sw_csum_tx &&
2300                      skb->ip_summed == CHECKSUM_PARTIAL)) {
2301                 int offs = skb_checksum_start_offset(skb);
2302                 int csum_offs = offs + skb->csum_offset;
2303                 __wsum csum;
2304
2305                 if (skb_ensure_writable(skb, csum_offs + sizeof(__sum16)))
2306                         return -1;
2307
2308                 csum = skb_checksum(skb, offs, skb->len - offs, 0);
2309                 *(__sum16 *)(skb->data + csum_offs) = csum_fold(csum);
2310
2311                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2312         }
2313
2314         if (skb_is_nonlinear(skb) &&
2315             skb_shinfo(skb)->nr_frags > IWL_PCIE_MAX_FRAGS(trans_pcie) &&
2316             __skb_linearize(skb))
2317                 return -ENOMEM;
2318
2319         /* mac80211 always puts the full header into the SKB's head,
2320          * so there's no need to check if it's readable there
2321          */
2322         hdr = (struct ieee80211_hdr *)skb->data;
2323         fc = hdr->frame_control;
2324         hdr_len = ieee80211_hdrlen(fc);
2325
2326         spin_lock(&txq->lock);
2327
2328         if (iwl_queue_space(txq) < txq->high_mark) {
2329                 iwl_stop_queue(trans, txq);
2330
2331                 /* don't put the packet on the ring, if there is no room */
2332                 if (unlikely(iwl_queue_space(txq) < 3)) {
2333                         struct iwl_device_cmd **dev_cmd_ptr;
2334
2335                         dev_cmd_ptr = (void *)((u8 *)skb->cb +
2336                                                trans_pcie->dev_cmd_offs);
2337
2338                         *dev_cmd_ptr = dev_cmd;
2339                         __skb_queue_tail(&txq->overflow_q, skb);
2340
2341                         spin_unlock(&txq->lock);
2342                         return 0;
2343                 }
2344         }
2345
2346         /* In AGG mode, the index in the ring must correspond to the WiFi
2347          * sequence number. This is a HW requirements to help the SCD to parse
2348          * the BA.
2349          * Check here that the packets are in the right place on the ring.
2350          */
2351         wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
2352         WARN_ONCE(txq->ampdu &&
2353                   (wifi_seq & 0xff) != txq->write_ptr,
2354                   "Q: %d WiFi Seq %d tfdNum %d",
2355                   txq_id, wifi_seq, txq->write_ptr);
2356
2357         /* Set up driver data for this TFD */
2358         txq->entries[txq->write_ptr].skb = skb;
2359         txq->entries[txq->write_ptr].cmd = dev_cmd;
2360
2361         dev_cmd->hdr.sequence =
2362                 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
2363                             INDEX_TO_SEQ(txq->write_ptr)));
2364
2365         tb0_phys = iwl_pcie_get_first_tb_dma(txq, txq->write_ptr);
2366         scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) +
2367                        offsetof(struct iwl_tx_cmd, scratch);
2368
2369         tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
2370         tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
2371
2372         /* Set up first empty entry in queue's array of Tx/cmd buffers */
2373         out_meta = &txq->entries[txq->write_ptr].meta;
2374         out_meta->flags = 0;
2375
2376         /*
2377          * The second TB (tb1) points to the remainder of the TX command
2378          * and the 802.11 header - dword aligned size
2379          * (This calculation modifies the TX command, so do it before the
2380          * setup of the first TB)
2381          */
2382         len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) +
2383               hdr_len - IWL_FIRST_TB_SIZE;
2384         /* do not align A-MSDU to dword as the subframe header aligns it */
2385         amsdu = ieee80211_is_data_qos(fc) &&
2386                 (*ieee80211_get_qos_ctl(hdr) &
2387                  IEEE80211_QOS_CTL_A_MSDU_PRESENT);
2388         if (trans_pcie->sw_csum_tx || !amsdu) {
2389                 tb1_len = ALIGN(len, 4);
2390                 /* Tell NIC about any 2-byte padding after MAC header */
2391                 if (tb1_len != len)
2392                         tx_cmd->tx_flags |= cpu_to_le32(TX_CMD_FLG_MH_PAD);
2393         } else {
2394                 tb1_len = len;
2395         }
2396
2397         /*
2398          * The first TB points to bi-directional DMA data, we'll
2399          * memcpy the data into it later.
2400          */
2401         iwl_pcie_txq_build_tfd(trans, txq, tb0_phys,
2402                                IWL_FIRST_TB_SIZE, true);
2403
2404         /* there must be data left over for TB1 or this code must be changed */
2405         BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_FIRST_TB_SIZE);
2406
2407         /* map the data for TB1 */
2408         tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_FIRST_TB_SIZE;
2409         tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE);
2410         if (unlikely(dma_mapping_error(trans->dev, tb1_phys)))
2411                 goto out_err;
2412         iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false);
2413
2414         if (amsdu) {
2415                 if (unlikely(iwl_fill_data_tbs_amsdu(trans, skb, txq, hdr_len,
2416                                                      out_meta, dev_cmd,
2417                                                      tb1_len)))
2418                         goto out_err;
2419         } else if (unlikely(iwl_fill_data_tbs(trans, skb, txq, hdr_len,
2420                                        out_meta, dev_cmd, tb1_len))) {
2421                 goto out_err;
2422         }
2423
2424         /* building the A-MSDU might have changed this data, so memcpy it now */
2425         memcpy(&txq->first_tb_bufs[txq->write_ptr], &dev_cmd->hdr,
2426                IWL_FIRST_TB_SIZE);
2427
2428         tfd = iwl_pcie_get_tfd(trans, txq, txq->write_ptr);
2429         /* Set up entry for this TFD in Tx byte-count array */
2430         iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len),
2431                                          iwl_pcie_tfd_get_num_tbs(trans, tfd));
2432
2433         wait_write_ptr = ieee80211_has_morefrags(fc);
2434
2435         /* start timer if queue currently empty */
2436         if (txq->read_ptr == txq->write_ptr) {
2437                 if (txq->wd_timeout) {
2438                         /*
2439                          * If the TXQ is active, then set the timer, if not,
2440                          * set the timer in remainder so that the timer will
2441                          * be armed with the right value when the station will
2442                          * wake up.
2443                          */
2444                         if (!txq->frozen)
2445                                 mod_timer(&txq->stuck_timer,
2446                                           jiffies + txq->wd_timeout);
2447                         else
2448                                 txq->frozen_expiry_remainder = txq->wd_timeout;
2449                 }
2450                 IWL_DEBUG_RPM(trans, "Q: %d first tx - take ref\n", txq->id);
2451                 iwl_trans_ref(trans);
2452         }
2453
2454         /* Tell device the write index *just past* this latest filled TFD */
2455         txq->write_ptr = iwl_queue_inc_wrap(txq->write_ptr);
2456         if (!wait_write_ptr)
2457                 iwl_pcie_txq_inc_wr_ptr(trans, txq);
2458
2459         /*
2460          * At this point the frame is "transmitted" successfully
2461          * and we will get a TX status notification eventually.
2462          */
2463         spin_unlock(&txq->lock);
2464         return 0;
2465 out_err:
2466         spin_unlock(&txq->lock);
2467         return -1;
2468 }