USB: remove broken usb-serial num_endpoints check
[sfrench/cifs-2.6.git] / drivers / net / wireless / b43legacy / dma.c
1 /*
2
3   Broadcom B43legacy wireless driver
4
5   DMA ringbuffer and descriptor allocation/management
6
7   Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8
9   Some code in this file is derived from the b44.c driver
10   Copyright (C) 2002 David S. Miller
11   Copyright (C) Pekka Pietikainen
12
13   This program is free software; you can redistribute it and/or modify
14   it under the terms of the GNU General Public License as published by
15   the Free Software Foundation; either version 2 of the License, or
16   (at your option) any later version.
17
18   This program is distributed in the hope that it will be useful,
19   but WITHOUT ANY WARRANTY; without even the implied warranty of
20   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
21   GNU General Public License for more details.
22
23   You should have received a copy of the GNU General Public License
24   along with this program; see the file COPYING.  If not, write to
25   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
26   Boston, MA 02110-1301, USA.
27
28 */
29
30 #include "b43legacy.h"
31 #include "dma.h"
32 #include "main.h"
33 #include "debugfs.h"
34 #include "xmit.h"
35
36 #include <linux/dma-mapping.h>
37 #include <linux/pci.h>
38 #include <linux/delay.h>
39 #include <linux/skbuff.h>
40 #include <net/dst.h>
41
42 /* 32bit DMA ops. */
43 static
44 struct b43legacy_dmadesc_generic *op32_idx2desc(
45                                         struct b43legacy_dmaring *ring,
46                                         int slot,
47                                         struct b43legacy_dmadesc_meta **meta)
48 {
49         struct b43legacy_dmadesc32 *desc;
50
51         *meta = &(ring->meta[slot]);
52         desc = ring->descbase;
53         desc = &(desc[slot]);
54
55         return (struct b43legacy_dmadesc_generic *)desc;
56 }
57
58 static void op32_fill_descriptor(struct b43legacy_dmaring *ring,
59                                  struct b43legacy_dmadesc_generic *desc,
60                                  dma_addr_t dmaaddr, u16 bufsize,
61                                  int start, int end, int irq)
62 {
63         struct b43legacy_dmadesc32 *descbase = ring->descbase;
64         int slot;
65         u32 ctl;
66         u32 addr;
67         u32 addrext;
68
69         slot = (int)(&(desc->dma32) - descbase);
70         B43legacy_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
71
72         addr = (u32)(dmaaddr & ~SSB_DMA_TRANSLATION_MASK);
73         addrext = (u32)(dmaaddr & SSB_DMA_TRANSLATION_MASK)
74                    >> SSB_DMA_TRANSLATION_SHIFT;
75         addr |= ssb_dma_translation(ring->dev->dev);
76         ctl = (bufsize - ring->frameoffset)
77               & B43legacy_DMA32_DCTL_BYTECNT;
78         if (slot == ring->nr_slots - 1)
79                 ctl |= B43legacy_DMA32_DCTL_DTABLEEND;
80         if (start)
81                 ctl |= B43legacy_DMA32_DCTL_FRAMESTART;
82         if (end)
83                 ctl |= B43legacy_DMA32_DCTL_FRAMEEND;
84         if (irq)
85                 ctl |= B43legacy_DMA32_DCTL_IRQ;
86         ctl |= (addrext << B43legacy_DMA32_DCTL_ADDREXT_SHIFT)
87                & B43legacy_DMA32_DCTL_ADDREXT_MASK;
88
89         desc->dma32.control = cpu_to_le32(ctl);
90         desc->dma32.address = cpu_to_le32(addr);
91 }
92
93 static void op32_poke_tx(struct b43legacy_dmaring *ring, int slot)
94 {
95         b43legacy_dma_write(ring, B43legacy_DMA32_TXINDEX,
96                             (u32)(slot * sizeof(struct b43legacy_dmadesc32)));
97 }
98
99 static void op32_tx_suspend(struct b43legacy_dmaring *ring)
100 {
101         b43legacy_dma_write(ring, B43legacy_DMA32_TXCTL,
102                             b43legacy_dma_read(ring, B43legacy_DMA32_TXCTL)
103                             | B43legacy_DMA32_TXSUSPEND);
104 }
105
106 static void op32_tx_resume(struct b43legacy_dmaring *ring)
107 {
108         b43legacy_dma_write(ring, B43legacy_DMA32_TXCTL,
109                             b43legacy_dma_read(ring, B43legacy_DMA32_TXCTL)
110                             & ~B43legacy_DMA32_TXSUSPEND);
111 }
112
113 static int op32_get_current_rxslot(struct b43legacy_dmaring *ring)
114 {
115         u32 val;
116
117         val = b43legacy_dma_read(ring, B43legacy_DMA32_RXSTATUS);
118         val &= B43legacy_DMA32_RXDPTR;
119
120         return (val / sizeof(struct b43legacy_dmadesc32));
121 }
122
123 static void op32_set_current_rxslot(struct b43legacy_dmaring *ring,
124                                     int slot)
125 {
126         b43legacy_dma_write(ring, B43legacy_DMA32_RXINDEX,
127                             (u32)(slot * sizeof(struct b43legacy_dmadesc32)));
128 }
129
130 static const struct b43legacy_dma_ops dma32_ops = {
131         .idx2desc               = op32_idx2desc,
132         .fill_descriptor        = op32_fill_descriptor,
133         .poke_tx                = op32_poke_tx,
134         .tx_suspend             = op32_tx_suspend,
135         .tx_resume              = op32_tx_resume,
136         .get_current_rxslot     = op32_get_current_rxslot,
137         .set_current_rxslot     = op32_set_current_rxslot,
138 };
139
140 /* 64bit DMA ops. */
141 static
142 struct b43legacy_dmadesc_generic *op64_idx2desc(
143                                         struct b43legacy_dmaring *ring,
144                                         int slot,
145                                         struct b43legacy_dmadesc_meta
146                                         **meta)
147 {
148         struct b43legacy_dmadesc64 *desc;
149
150         *meta = &(ring->meta[slot]);
151         desc = ring->descbase;
152         desc = &(desc[slot]);
153
154         return (struct b43legacy_dmadesc_generic *)desc;
155 }
156
157 static void op64_fill_descriptor(struct b43legacy_dmaring *ring,
158                                  struct b43legacy_dmadesc_generic *desc,
159                                  dma_addr_t dmaaddr, u16 bufsize,
160                                  int start, int end, int irq)
161 {
162         struct b43legacy_dmadesc64 *descbase = ring->descbase;
163         int slot;
164         u32 ctl0 = 0;
165         u32 ctl1 = 0;
166         u32 addrlo;
167         u32 addrhi;
168         u32 addrext;
169
170         slot = (int)(&(desc->dma64) - descbase);
171         B43legacy_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
172
173         addrlo = (u32)(dmaaddr & 0xFFFFFFFF);
174         addrhi = (((u64)dmaaddr >> 32) & ~SSB_DMA_TRANSLATION_MASK);
175         addrext = (((u64)dmaaddr >> 32) & SSB_DMA_TRANSLATION_MASK)
176                   >> SSB_DMA_TRANSLATION_SHIFT;
177         addrhi |= ssb_dma_translation(ring->dev->dev);
178         if (slot == ring->nr_slots - 1)
179                 ctl0 |= B43legacy_DMA64_DCTL0_DTABLEEND;
180         if (start)
181                 ctl0 |= B43legacy_DMA64_DCTL0_FRAMESTART;
182         if (end)
183                 ctl0 |= B43legacy_DMA64_DCTL0_FRAMEEND;
184         if (irq)
185                 ctl0 |= B43legacy_DMA64_DCTL0_IRQ;
186         ctl1 |= (bufsize - ring->frameoffset)
187                 & B43legacy_DMA64_DCTL1_BYTECNT;
188         ctl1 |= (addrext << B43legacy_DMA64_DCTL1_ADDREXT_SHIFT)
189                 & B43legacy_DMA64_DCTL1_ADDREXT_MASK;
190
191         desc->dma64.control0 = cpu_to_le32(ctl0);
192         desc->dma64.control1 = cpu_to_le32(ctl1);
193         desc->dma64.address_low = cpu_to_le32(addrlo);
194         desc->dma64.address_high = cpu_to_le32(addrhi);
195 }
196
197 static void op64_poke_tx(struct b43legacy_dmaring *ring, int slot)
198 {
199         b43legacy_dma_write(ring, B43legacy_DMA64_TXINDEX,
200                             (u32)(slot * sizeof(struct b43legacy_dmadesc64)));
201 }
202
203 static void op64_tx_suspend(struct b43legacy_dmaring *ring)
204 {
205         b43legacy_dma_write(ring, B43legacy_DMA64_TXCTL,
206                             b43legacy_dma_read(ring, B43legacy_DMA64_TXCTL)
207                             | B43legacy_DMA64_TXSUSPEND);
208 }
209
210 static void op64_tx_resume(struct b43legacy_dmaring *ring)
211 {
212         b43legacy_dma_write(ring, B43legacy_DMA64_TXCTL,
213                             b43legacy_dma_read(ring, B43legacy_DMA64_TXCTL)
214                             & ~B43legacy_DMA64_TXSUSPEND);
215 }
216
217 static int op64_get_current_rxslot(struct b43legacy_dmaring *ring)
218 {
219         u32 val;
220
221         val = b43legacy_dma_read(ring, B43legacy_DMA64_RXSTATUS);
222         val &= B43legacy_DMA64_RXSTATDPTR;
223
224         return (val / sizeof(struct b43legacy_dmadesc64));
225 }
226
227 static void op64_set_current_rxslot(struct b43legacy_dmaring *ring,
228                                     int slot)
229 {
230         b43legacy_dma_write(ring, B43legacy_DMA64_RXINDEX,
231                             (u32)(slot * sizeof(struct b43legacy_dmadesc64)));
232 }
233
234 static const struct b43legacy_dma_ops dma64_ops = {
235         .idx2desc               = op64_idx2desc,
236         .fill_descriptor        = op64_fill_descriptor,
237         .poke_tx                = op64_poke_tx,
238         .tx_suspend             = op64_tx_suspend,
239         .tx_resume              = op64_tx_resume,
240         .get_current_rxslot     = op64_get_current_rxslot,
241         .set_current_rxslot     = op64_set_current_rxslot,
242 };
243
244
245 static inline int free_slots(struct b43legacy_dmaring *ring)
246 {
247         return (ring->nr_slots - ring->used_slots);
248 }
249
250 static inline int next_slot(struct b43legacy_dmaring *ring, int slot)
251 {
252         B43legacy_WARN_ON(!(slot >= -1 && slot <= ring->nr_slots - 1));
253         if (slot == ring->nr_slots - 1)
254                 return 0;
255         return slot + 1;
256 }
257
258 static inline int prev_slot(struct b43legacy_dmaring *ring, int slot)
259 {
260         B43legacy_WARN_ON(!(slot >= 0 && slot <= ring->nr_slots - 1));
261         if (slot == 0)
262                 return ring->nr_slots - 1;
263         return slot - 1;
264 }
265
266 #ifdef CONFIG_B43LEGACY_DEBUG
267 static void update_max_used_slots(struct b43legacy_dmaring *ring,
268                                   int current_used_slots)
269 {
270         if (current_used_slots <= ring->max_used_slots)
271                 return;
272         ring->max_used_slots = current_used_slots;
273         if (b43legacy_debug(ring->dev, B43legacy_DBG_DMAVERBOSE))
274                 b43legacydbg(ring->dev->wl,
275                        "max_used_slots increased to %d on %s ring %d\n",
276                        ring->max_used_slots,
277                        ring->tx ? "TX" : "RX",
278                        ring->index);
279 }
280 #else
281 static inline
282 void update_max_used_slots(struct b43legacy_dmaring *ring,
283                            int current_used_slots)
284 { }
285 #endif /* DEBUG */
286
287 /* Request a slot for usage. */
288 static inline
289 int request_slot(struct b43legacy_dmaring *ring)
290 {
291         int slot;
292
293         B43legacy_WARN_ON(!ring->tx);
294         B43legacy_WARN_ON(ring->stopped);
295         B43legacy_WARN_ON(free_slots(ring) == 0);
296
297         slot = next_slot(ring, ring->current_slot);
298         ring->current_slot = slot;
299         ring->used_slots++;
300
301         update_max_used_slots(ring, ring->used_slots);
302
303         return slot;
304 }
305
306 /* Mac80211-queue to b43legacy-ring mapping */
307 static struct b43legacy_dmaring *priority_to_txring(
308                                                 struct b43legacy_wldev *dev,
309                                                 int queue_priority)
310 {
311         struct b43legacy_dmaring *ring;
312
313 /*FIXME: For now we always run on TX-ring-1 */
314 return dev->dma.tx_ring1;
315
316         /* 0 = highest priority */
317         switch (queue_priority) {
318         default:
319                 B43legacy_WARN_ON(1);
320                 /* fallthrough */
321         case 0:
322                 ring = dev->dma.tx_ring3;
323                 break;
324         case 1:
325                 ring = dev->dma.tx_ring2;
326                 break;
327         case 2:
328                 ring = dev->dma.tx_ring1;
329                 break;
330         case 3:
331                 ring = dev->dma.tx_ring0;
332                 break;
333         case 4:
334                 ring = dev->dma.tx_ring4;
335                 break;
336         case 5:
337                 ring = dev->dma.tx_ring5;
338                 break;
339         }
340
341         return ring;
342 }
343
344 /* Bcm4301-ring to mac80211-queue mapping */
345 static inline int txring_to_priority(struct b43legacy_dmaring *ring)
346 {
347         static const u8 idx_to_prio[] =
348                 { 3, 2, 1, 0, 4, 5, };
349
350 /*FIXME: have only one queue, for now */
351 return 0;
352
353         return idx_to_prio[ring->index];
354 }
355
356
357 static u16 b43legacy_dmacontroller_base(enum b43legacy_dmatype type,
358                                         int controller_idx)
359 {
360         static const u16 map64[] = {
361                 B43legacy_MMIO_DMA64_BASE0,
362                 B43legacy_MMIO_DMA64_BASE1,
363                 B43legacy_MMIO_DMA64_BASE2,
364                 B43legacy_MMIO_DMA64_BASE3,
365                 B43legacy_MMIO_DMA64_BASE4,
366                 B43legacy_MMIO_DMA64_BASE5,
367         };
368         static const u16 map32[] = {
369                 B43legacy_MMIO_DMA32_BASE0,
370                 B43legacy_MMIO_DMA32_BASE1,
371                 B43legacy_MMIO_DMA32_BASE2,
372                 B43legacy_MMIO_DMA32_BASE3,
373                 B43legacy_MMIO_DMA32_BASE4,
374                 B43legacy_MMIO_DMA32_BASE5,
375         };
376
377         if (type == B43legacy_DMA_64BIT) {
378                 B43legacy_WARN_ON(!(controller_idx >= 0 &&
379                                   controller_idx < ARRAY_SIZE(map64)));
380                 return map64[controller_idx];
381         }
382         B43legacy_WARN_ON(!(controller_idx >= 0 &&
383                           controller_idx < ARRAY_SIZE(map32)));
384         return map32[controller_idx];
385 }
386
387 static inline
388 dma_addr_t map_descbuffer(struct b43legacy_dmaring *ring,
389                           unsigned char *buf,
390                           size_t len,
391                           int tx)
392 {
393         dma_addr_t dmaaddr;
394
395         if (tx)
396                 dmaaddr = dma_map_single(ring->dev->dev->dev,
397                                          buf, len,
398                                          DMA_TO_DEVICE);
399         else
400                 dmaaddr = dma_map_single(ring->dev->dev->dev,
401                                          buf, len,
402                                          DMA_FROM_DEVICE);
403
404         return dmaaddr;
405 }
406
407 static inline
408 void unmap_descbuffer(struct b43legacy_dmaring *ring,
409                       dma_addr_t addr,
410                       size_t len,
411                       int tx)
412 {
413         if (tx)
414                 dma_unmap_single(ring->dev->dev->dev,
415                                  addr, len,
416                                  DMA_TO_DEVICE);
417         else
418                 dma_unmap_single(ring->dev->dev->dev,
419                                  addr, len,
420                                  DMA_FROM_DEVICE);
421 }
422
423 static inline
424 void sync_descbuffer_for_cpu(struct b43legacy_dmaring *ring,
425                              dma_addr_t addr,
426                              size_t len)
427 {
428         B43legacy_WARN_ON(ring->tx);
429
430         dma_sync_single_for_cpu(ring->dev->dev->dev,
431                                 addr, len, DMA_FROM_DEVICE);
432 }
433
434 static inline
435 void sync_descbuffer_for_device(struct b43legacy_dmaring *ring,
436                                 dma_addr_t addr,
437                                 size_t len)
438 {
439         B43legacy_WARN_ON(ring->tx);
440
441         dma_sync_single_for_device(ring->dev->dev->dev,
442                                    addr, len, DMA_FROM_DEVICE);
443 }
444
445 static inline
446 void free_descriptor_buffer(struct b43legacy_dmaring *ring,
447                             struct b43legacy_dmadesc_meta *meta,
448                             int irq_context)
449 {
450         if (meta->skb) {
451                 if (irq_context)
452                         dev_kfree_skb_irq(meta->skb);
453                 else
454                         dev_kfree_skb(meta->skb);
455                 meta->skb = NULL;
456         }
457 }
458
459 static int alloc_ringmemory(struct b43legacy_dmaring *ring)
460 {
461         struct device *dev = ring->dev->dev->dev;
462
463         ring->descbase = dma_alloc_coherent(dev, B43legacy_DMA_RINGMEMSIZE,
464                                             &(ring->dmabase), GFP_KERNEL);
465         if (!ring->descbase) {
466                 b43legacyerr(ring->dev->wl, "DMA ringmemory allocation"
467                              " failed\n");
468                 return -ENOMEM;
469         }
470         memset(ring->descbase, 0, B43legacy_DMA_RINGMEMSIZE);
471
472         return 0;
473 }
474
475 static void free_ringmemory(struct b43legacy_dmaring *ring)
476 {
477         struct device *dev = ring->dev->dev->dev;
478
479         dma_free_coherent(dev, B43legacy_DMA_RINGMEMSIZE,
480                           ring->descbase, ring->dmabase);
481 }
482
483 /* Reset the RX DMA channel */
484 static int b43legacy_dmacontroller_rx_reset(struct b43legacy_wldev *dev,
485                                             u16 mmio_base,
486                                             enum b43legacy_dmatype type)
487 {
488         int i;
489         u32 value;
490         u16 offset;
491
492         might_sleep();
493
494         offset = (type == B43legacy_DMA_64BIT) ?
495                  B43legacy_DMA64_RXCTL : B43legacy_DMA32_RXCTL;
496         b43legacy_write32(dev, mmio_base + offset, 0);
497         for (i = 0; i < 10; i++) {
498                 offset = (type == B43legacy_DMA_64BIT) ?
499                          B43legacy_DMA64_RXSTATUS : B43legacy_DMA32_RXSTATUS;
500                 value = b43legacy_read32(dev, mmio_base + offset);
501                 if (type == B43legacy_DMA_64BIT) {
502                         value &= B43legacy_DMA64_RXSTAT;
503                         if (value == B43legacy_DMA64_RXSTAT_DISABLED) {
504                                 i = -1;
505                                 break;
506                         }
507                 } else {
508                         value &= B43legacy_DMA32_RXSTATE;
509                         if (value == B43legacy_DMA32_RXSTAT_DISABLED) {
510                                 i = -1;
511                                 break;
512                         }
513                 }
514                 msleep(1);
515         }
516         if (i != -1) {
517                 b43legacyerr(dev->wl, "DMA RX reset timed out\n");
518                 return -ENODEV;
519         }
520
521         return 0;
522 }
523
524 /* Reset the RX DMA channel */
525 static int b43legacy_dmacontroller_tx_reset(struct b43legacy_wldev *dev,
526                                             u16 mmio_base,
527                                             enum b43legacy_dmatype type)
528 {
529         int i;
530         u32 value;
531         u16 offset;
532
533         might_sleep();
534
535         for (i = 0; i < 10; i++) {
536                 offset = (type == B43legacy_DMA_64BIT) ?
537                          B43legacy_DMA64_TXSTATUS : B43legacy_DMA32_TXSTATUS;
538                 value = b43legacy_read32(dev, mmio_base + offset);
539                 if (type == B43legacy_DMA_64BIT) {
540                         value &= B43legacy_DMA64_TXSTAT;
541                         if (value == B43legacy_DMA64_TXSTAT_DISABLED ||
542                             value == B43legacy_DMA64_TXSTAT_IDLEWAIT ||
543                             value == B43legacy_DMA64_TXSTAT_STOPPED)
544                                 break;
545                 } else {
546                         value &= B43legacy_DMA32_TXSTATE;
547                         if (value == B43legacy_DMA32_TXSTAT_DISABLED ||
548                             value == B43legacy_DMA32_TXSTAT_IDLEWAIT ||
549                             value == B43legacy_DMA32_TXSTAT_STOPPED)
550                                 break;
551                 }
552                 msleep(1);
553         }
554         offset = (type == B43legacy_DMA_64BIT) ? B43legacy_DMA64_TXCTL :
555                                                  B43legacy_DMA32_TXCTL;
556         b43legacy_write32(dev, mmio_base + offset, 0);
557         for (i = 0; i < 10; i++) {
558                 offset = (type == B43legacy_DMA_64BIT) ?
559                          B43legacy_DMA64_TXSTATUS : B43legacy_DMA32_TXSTATUS;
560                 value = b43legacy_read32(dev, mmio_base + offset);
561                 if (type == B43legacy_DMA_64BIT) {
562                         value &= B43legacy_DMA64_TXSTAT;
563                         if (value == B43legacy_DMA64_TXSTAT_DISABLED) {
564                                 i = -1;
565                                 break;
566                         }
567                 } else {
568                         value &= B43legacy_DMA32_TXSTATE;
569                         if (value == B43legacy_DMA32_TXSTAT_DISABLED) {
570                                 i = -1;
571                                 break;
572                         }
573                 }
574                 msleep(1);
575         }
576         if (i != -1) {
577                 b43legacyerr(dev->wl, "DMA TX reset timed out\n");
578                 return -ENODEV;
579         }
580         /* ensure the reset is completed. */
581         msleep(1);
582
583         return 0;
584 }
585
586 /* Check if a DMA mapping address is invalid. */
587 static bool b43legacy_dma_mapping_error(struct b43legacy_dmaring *ring,
588                                         dma_addr_t addr,
589                                         size_t buffersize)
590 {
591         if (unlikely(dma_mapping_error(addr)))
592                 return 1;
593
594         switch (ring->type) {
595         case B43legacy_DMA_30BIT:
596                 if ((u64)addr + buffersize > (1ULL << 30))
597                         return 1;
598                 break;
599         case B43legacy_DMA_32BIT:
600                 if ((u64)addr + buffersize > (1ULL << 32))
601                         return 1;
602                 break;
603         case B43legacy_DMA_64BIT:
604                 /* Currently we can't have addresses beyond 64 bits in the kernel. */
605                 break;
606         }
607
608         /* The address is OK. */
609         return 0;
610 }
611
612 static int setup_rx_descbuffer(struct b43legacy_dmaring *ring,
613                                struct b43legacy_dmadesc_generic *desc,
614                                struct b43legacy_dmadesc_meta *meta,
615                                gfp_t gfp_flags)
616 {
617         struct b43legacy_rxhdr_fw3 *rxhdr;
618         struct b43legacy_hwtxstatus *txstat;
619         dma_addr_t dmaaddr;
620         struct sk_buff *skb;
621
622         B43legacy_WARN_ON(ring->tx);
623
624         skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
625         if (unlikely(!skb))
626                 return -ENOMEM;
627         dmaaddr = map_descbuffer(ring, skb->data,
628                                  ring->rx_buffersize, 0);
629         if (b43legacy_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize)) {
630                 /* ugh. try to realloc in zone_dma */
631                 gfp_flags |= GFP_DMA;
632
633                 dev_kfree_skb_any(skb);
634
635                 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
636                 if (unlikely(!skb))
637                         return -ENOMEM;
638                 dmaaddr = map_descbuffer(ring, skb->data,
639                                          ring->rx_buffersize, 0);
640         }
641
642         if (b43legacy_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize)) {
643                 dev_kfree_skb_any(skb);
644                 return -EIO;
645         }
646
647         meta->skb = skb;
648         meta->dmaaddr = dmaaddr;
649         ring->ops->fill_descriptor(ring, desc, dmaaddr,
650                                    ring->rx_buffersize, 0, 0, 0);
651
652         rxhdr = (struct b43legacy_rxhdr_fw3 *)(skb->data);
653         rxhdr->frame_len = 0;
654         txstat = (struct b43legacy_hwtxstatus *)(skb->data);
655         txstat->cookie = 0;
656
657         return 0;
658 }
659
660 /* Allocate the initial descbuffers.
661  * This is used for an RX ring only.
662  */
663 static int alloc_initial_descbuffers(struct b43legacy_dmaring *ring)
664 {
665         int i;
666         int err = -ENOMEM;
667         struct b43legacy_dmadesc_generic *desc;
668         struct b43legacy_dmadesc_meta *meta;
669
670         for (i = 0; i < ring->nr_slots; i++) {
671                 desc = ring->ops->idx2desc(ring, i, &meta);
672
673                 err = setup_rx_descbuffer(ring, desc, meta, GFP_KERNEL);
674                 if (err) {
675                         b43legacyerr(ring->dev->wl,
676                                "Failed to allocate initial descbuffers\n");
677                         goto err_unwind;
678                 }
679         }
680         mb(); /* all descbuffer setup before next line */
681         ring->used_slots = ring->nr_slots;
682         err = 0;
683 out:
684         return err;
685
686 err_unwind:
687         for (i--; i >= 0; i--) {
688                 desc = ring->ops->idx2desc(ring, i, &meta);
689
690                 unmap_descbuffer(ring, meta->dmaaddr, ring->rx_buffersize, 0);
691                 dev_kfree_skb(meta->skb);
692         }
693         goto out;
694 }
695
696 /* Do initial setup of the DMA controller.
697  * Reset the controller, write the ring busaddress
698  * and switch the "enable" bit on.
699  */
700 static int dmacontroller_setup(struct b43legacy_dmaring *ring)
701 {
702         int err = 0;
703         u32 value;
704         u32 addrext;
705         u32 trans = ssb_dma_translation(ring->dev->dev);
706
707         if (ring->tx) {
708                 if (ring->type == B43legacy_DMA_64BIT) {
709                         u64 ringbase = (u64)(ring->dmabase);
710
711                         addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
712                                   >> SSB_DMA_TRANSLATION_SHIFT;
713                         value = B43legacy_DMA64_TXENABLE;
714                         value |= (addrext << B43legacy_DMA64_TXADDREXT_SHIFT)
715                                 & B43legacy_DMA64_TXADDREXT_MASK;
716                         b43legacy_dma_write(ring, B43legacy_DMA64_TXCTL,
717                                             value);
718                         b43legacy_dma_write(ring, B43legacy_DMA64_TXRINGLO,
719                                             (ringbase & 0xFFFFFFFF));
720                         b43legacy_dma_write(ring, B43legacy_DMA64_TXRINGHI,
721                                             ((ringbase >> 32)
722                                             & ~SSB_DMA_TRANSLATION_MASK)
723                                             | trans);
724                 } else {
725                         u32 ringbase = (u32)(ring->dmabase);
726
727                         addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
728                                   >> SSB_DMA_TRANSLATION_SHIFT;
729                         value = B43legacy_DMA32_TXENABLE;
730                         value |= (addrext << B43legacy_DMA32_TXADDREXT_SHIFT)
731                                 & B43legacy_DMA32_TXADDREXT_MASK;
732                         b43legacy_dma_write(ring, B43legacy_DMA32_TXCTL,
733                                             value);
734                         b43legacy_dma_write(ring, B43legacy_DMA32_TXRING,
735                                             (ringbase &
736                                             ~SSB_DMA_TRANSLATION_MASK)
737                                             | trans);
738                 }
739         } else {
740                 err = alloc_initial_descbuffers(ring);
741                 if (err)
742                         goto out;
743                 if (ring->type == B43legacy_DMA_64BIT) {
744                         u64 ringbase = (u64)(ring->dmabase);
745
746                         addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
747                                   >> SSB_DMA_TRANSLATION_SHIFT;
748                         value = (ring->frameoffset <<
749                                  B43legacy_DMA64_RXFROFF_SHIFT);
750                         value |= B43legacy_DMA64_RXENABLE;
751                         value |= (addrext << B43legacy_DMA64_RXADDREXT_SHIFT)
752                                 & B43legacy_DMA64_RXADDREXT_MASK;
753                         b43legacy_dma_write(ring, B43legacy_DMA64_RXCTL,
754                                             value);
755                         b43legacy_dma_write(ring, B43legacy_DMA64_RXRINGLO,
756                                             (ringbase & 0xFFFFFFFF));
757                         b43legacy_dma_write(ring, B43legacy_DMA64_RXRINGHI,
758                                             ((ringbase >> 32) &
759                                             ~SSB_DMA_TRANSLATION_MASK) |
760                                             trans);
761                         b43legacy_dma_write(ring, B43legacy_DMA64_RXINDEX,
762                                             200);
763                 } else {
764                         u32 ringbase = (u32)(ring->dmabase);
765
766                         addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
767                                   >> SSB_DMA_TRANSLATION_SHIFT;
768                         value = (ring->frameoffset <<
769                                  B43legacy_DMA32_RXFROFF_SHIFT);
770                         value |= B43legacy_DMA32_RXENABLE;
771                         value |= (addrext <<
772                                  B43legacy_DMA32_RXADDREXT_SHIFT)
773                                  & B43legacy_DMA32_RXADDREXT_MASK;
774                         b43legacy_dma_write(ring, B43legacy_DMA32_RXCTL,
775                                             value);
776                         b43legacy_dma_write(ring, B43legacy_DMA32_RXRING,
777                                             (ringbase &
778                                             ~SSB_DMA_TRANSLATION_MASK)
779                                             | trans);
780                         b43legacy_dma_write(ring, B43legacy_DMA32_RXINDEX,
781                                             200);
782                 }
783         }
784
785 out:
786         return err;
787 }
788
789 /* Shutdown the DMA controller. */
790 static void dmacontroller_cleanup(struct b43legacy_dmaring *ring)
791 {
792         if (ring->tx) {
793                 b43legacy_dmacontroller_tx_reset(ring->dev, ring->mmio_base,
794                                                  ring->type);
795                 if (ring->type == B43legacy_DMA_64BIT) {
796                         b43legacy_dma_write(ring, B43legacy_DMA64_TXRINGLO, 0);
797                         b43legacy_dma_write(ring, B43legacy_DMA64_TXRINGHI, 0);
798                 } else
799                         b43legacy_dma_write(ring, B43legacy_DMA32_TXRING, 0);
800         } else {
801                 b43legacy_dmacontroller_rx_reset(ring->dev, ring->mmio_base,
802                                                  ring->type);
803                 if (ring->type == B43legacy_DMA_64BIT) {
804                         b43legacy_dma_write(ring, B43legacy_DMA64_RXRINGLO, 0);
805                         b43legacy_dma_write(ring, B43legacy_DMA64_RXRINGHI, 0);
806                 } else
807                         b43legacy_dma_write(ring, B43legacy_DMA32_RXRING, 0);
808         }
809 }
810
811 static void free_all_descbuffers(struct b43legacy_dmaring *ring)
812 {
813         struct b43legacy_dmadesc_generic *desc;
814         struct b43legacy_dmadesc_meta *meta;
815         int i;
816
817         if (!ring->used_slots)
818                 return;
819         for (i = 0; i < ring->nr_slots; i++) {
820                 desc = ring->ops->idx2desc(ring, i, &meta);
821
822                 if (!meta->skb) {
823                         B43legacy_WARN_ON(!ring->tx);
824                         continue;
825                 }
826                 if (ring->tx)
827                         unmap_descbuffer(ring, meta->dmaaddr,
828                                          meta->skb->len, 1);
829                 else
830                         unmap_descbuffer(ring, meta->dmaaddr,
831                                          ring->rx_buffersize, 0);
832                 free_descriptor_buffer(ring, meta, 0);
833         }
834 }
835
836 static u64 supported_dma_mask(struct b43legacy_wldev *dev)
837 {
838         u32 tmp;
839         u16 mmio_base;
840
841         tmp = b43legacy_read32(dev, SSB_TMSHIGH);
842         if (tmp & SSB_TMSHIGH_DMA64)
843                 return DMA_64BIT_MASK;
844         mmio_base = b43legacy_dmacontroller_base(0, 0);
845         b43legacy_write32(dev,
846                         mmio_base + B43legacy_DMA32_TXCTL,
847                         B43legacy_DMA32_TXADDREXT_MASK);
848         tmp = b43legacy_read32(dev, mmio_base +
849                                B43legacy_DMA32_TXCTL);
850         if (tmp & B43legacy_DMA32_TXADDREXT_MASK)
851                 return DMA_32BIT_MASK;
852
853         return DMA_30BIT_MASK;
854 }
855
856 /* Main initialization function. */
857 static
858 struct b43legacy_dmaring *b43legacy_setup_dmaring(struct b43legacy_wldev *dev,
859                                                   int controller_index,
860                                                   int for_tx,
861                                                   enum b43legacy_dmatype type)
862 {
863         struct b43legacy_dmaring *ring;
864         int err;
865         int nr_slots;
866         dma_addr_t dma_test;
867
868         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
869         if (!ring)
870                 goto out;
871         ring->type = type;
872
873         nr_slots = B43legacy_RXRING_SLOTS;
874         if (for_tx)
875                 nr_slots = B43legacy_TXRING_SLOTS;
876
877         ring->meta = kcalloc(nr_slots, sizeof(struct b43legacy_dmadesc_meta),
878                              GFP_KERNEL);
879         if (!ring->meta)
880                 goto err_kfree_ring;
881         if (for_tx) {
882                 ring->txhdr_cache = kcalloc(nr_slots,
883                                         sizeof(struct b43legacy_txhdr_fw3),
884                                         GFP_KERNEL);
885                 if (!ring->txhdr_cache)
886                         goto err_kfree_meta;
887
888                 /* test for ability to dma to txhdr_cache */
889                 dma_test = dma_map_single(dev->dev->dev, ring->txhdr_cache,
890                                           sizeof(struct b43legacy_txhdr_fw3),
891                                           DMA_TO_DEVICE);
892
893                 if (b43legacy_dma_mapping_error(ring, dma_test,
894                                         sizeof(struct b43legacy_txhdr_fw3))) {
895                         /* ugh realloc */
896                         kfree(ring->txhdr_cache);
897                         ring->txhdr_cache = kcalloc(nr_slots,
898                                         sizeof(struct b43legacy_txhdr_fw3),
899                                         GFP_KERNEL | GFP_DMA);
900                         if (!ring->txhdr_cache)
901                                 goto err_kfree_meta;
902
903                         dma_test = dma_map_single(dev->dev->dev,
904                                         ring->txhdr_cache,
905                                         sizeof(struct b43legacy_txhdr_fw3),
906                                         DMA_TO_DEVICE);
907
908                         if (b43legacy_dma_mapping_error(ring, dma_test,
909                                         sizeof(struct b43legacy_txhdr_fw3)))
910                                 goto err_kfree_txhdr_cache;
911                 }
912
913                 dma_unmap_single(dev->dev->dev,
914                                  dma_test, sizeof(struct b43legacy_txhdr_fw3),
915                                  DMA_TO_DEVICE);
916         }
917
918         ring->dev = dev;
919         ring->nr_slots = nr_slots;
920         ring->mmio_base = b43legacy_dmacontroller_base(type, controller_index);
921         ring->index = controller_index;
922         if (type == B43legacy_DMA_64BIT)
923                 ring->ops = &dma64_ops;
924         else
925                 ring->ops = &dma32_ops;
926         if (for_tx) {
927                 ring->tx = 1;
928                 ring->current_slot = -1;
929         } else {
930                 if (ring->index == 0) {
931                         ring->rx_buffersize = B43legacy_DMA0_RX_BUFFERSIZE;
932                         ring->frameoffset = B43legacy_DMA0_RX_FRAMEOFFSET;
933                 } else if (ring->index == 3) {
934                         ring->rx_buffersize = B43legacy_DMA3_RX_BUFFERSIZE;
935                         ring->frameoffset = B43legacy_DMA3_RX_FRAMEOFFSET;
936                 } else
937                         B43legacy_WARN_ON(1);
938         }
939         spin_lock_init(&ring->lock);
940 #ifdef CONFIG_B43LEGACY_DEBUG
941         ring->last_injected_overflow = jiffies;
942 #endif
943
944         err = alloc_ringmemory(ring);
945         if (err)
946                 goto err_kfree_txhdr_cache;
947         err = dmacontroller_setup(ring);
948         if (err)
949                 goto err_free_ringmemory;
950
951 out:
952         return ring;
953
954 err_free_ringmemory:
955         free_ringmemory(ring);
956 err_kfree_txhdr_cache:
957         kfree(ring->txhdr_cache);
958 err_kfree_meta:
959         kfree(ring->meta);
960 err_kfree_ring:
961         kfree(ring);
962         ring = NULL;
963         goto out;
964 }
965
966 /* Main cleanup function. */
967 static void b43legacy_destroy_dmaring(struct b43legacy_dmaring *ring)
968 {
969         if (!ring)
970                 return;
971
972         b43legacydbg(ring->dev->wl, "DMA-%u 0x%04X (%s) max used slots:"
973                      " %d/%d\n", (unsigned int)(ring->type), ring->mmio_base,
974                      (ring->tx) ? "TX" : "RX", ring->max_used_slots,
975                      ring->nr_slots);
976         /* Device IRQs are disabled prior entering this function,
977          * so no need to take care of concurrency with rx handler stuff.
978          */
979         dmacontroller_cleanup(ring);
980         free_all_descbuffers(ring);
981         free_ringmemory(ring);
982
983         kfree(ring->txhdr_cache);
984         kfree(ring->meta);
985         kfree(ring);
986 }
987
988 void b43legacy_dma_free(struct b43legacy_wldev *dev)
989 {
990         struct b43legacy_dma *dma;
991
992         if (b43legacy_using_pio(dev))
993                 return;
994         dma = &dev->dma;
995
996         b43legacy_destroy_dmaring(dma->rx_ring3);
997         dma->rx_ring3 = NULL;
998         b43legacy_destroy_dmaring(dma->rx_ring0);
999         dma->rx_ring0 = NULL;
1000
1001         b43legacy_destroy_dmaring(dma->tx_ring5);
1002         dma->tx_ring5 = NULL;
1003         b43legacy_destroy_dmaring(dma->tx_ring4);
1004         dma->tx_ring4 = NULL;
1005         b43legacy_destroy_dmaring(dma->tx_ring3);
1006         dma->tx_ring3 = NULL;
1007         b43legacy_destroy_dmaring(dma->tx_ring2);
1008         dma->tx_ring2 = NULL;
1009         b43legacy_destroy_dmaring(dma->tx_ring1);
1010         dma->tx_ring1 = NULL;
1011         b43legacy_destroy_dmaring(dma->tx_ring0);
1012         dma->tx_ring0 = NULL;
1013 }
1014
1015 int b43legacy_dma_init(struct b43legacy_wldev *dev)
1016 {
1017         struct b43legacy_dma *dma = &dev->dma;
1018         struct b43legacy_dmaring *ring;
1019         int err;
1020         u64 dmamask;
1021         enum b43legacy_dmatype type;
1022
1023         dmamask = supported_dma_mask(dev);
1024         switch (dmamask) {
1025         default:
1026                 B43legacy_WARN_ON(1);
1027         case DMA_30BIT_MASK:
1028                 type = B43legacy_DMA_30BIT;
1029                 break;
1030         case DMA_32BIT_MASK:
1031                 type = B43legacy_DMA_32BIT;
1032                 break;
1033         case DMA_64BIT_MASK:
1034                 type = B43legacy_DMA_64BIT;
1035                 break;
1036         }
1037
1038         err = ssb_dma_set_mask(dev->dev, dmamask);
1039         if (err) {
1040 #ifdef CONFIG_B43LEGACY_PIO
1041                 b43legacywarn(dev->wl, "DMA for this device not supported. "
1042                         "Falling back to PIO\n");
1043                 dev->__using_pio = 1;
1044                 return -EAGAIN;
1045 #else
1046                 b43legacyerr(dev->wl, "DMA for this device not supported and "
1047                        "no PIO support compiled in\n");
1048                 return -EOPNOTSUPP;
1049 #endif
1050         }
1051
1052         err = -ENOMEM;
1053         /* setup TX DMA channels. */
1054         ring = b43legacy_setup_dmaring(dev, 0, 1, type);
1055         if (!ring)
1056                 goto out;
1057         dma->tx_ring0 = ring;
1058
1059         ring = b43legacy_setup_dmaring(dev, 1, 1, type);
1060         if (!ring)
1061                 goto err_destroy_tx0;
1062         dma->tx_ring1 = ring;
1063
1064         ring = b43legacy_setup_dmaring(dev, 2, 1, type);
1065         if (!ring)
1066                 goto err_destroy_tx1;
1067         dma->tx_ring2 = ring;
1068
1069         ring = b43legacy_setup_dmaring(dev, 3, 1, type);
1070         if (!ring)
1071                 goto err_destroy_tx2;
1072         dma->tx_ring3 = ring;
1073
1074         ring = b43legacy_setup_dmaring(dev, 4, 1, type);
1075         if (!ring)
1076                 goto err_destroy_tx3;
1077         dma->tx_ring4 = ring;
1078
1079         ring = b43legacy_setup_dmaring(dev, 5, 1, type);
1080         if (!ring)
1081                 goto err_destroy_tx4;
1082         dma->tx_ring5 = ring;
1083
1084         /* setup RX DMA channels. */
1085         ring = b43legacy_setup_dmaring(dev, 0, 0, type);
1086         if (!ring)
1087                 goto err_destroy_tx5;
1088         dma->rx_ring0 = ring;
1089
1090         if (dev->dev->id.revision < 5) {
1091                 ring = b43legacy_setup_dmaring(dev, 3, 0, type);
1092                 if (!ring)
1093                         goto err_destroy_rx0;
1094                 dma->rx_ring3 = ring;
1095         }
1096
1097         b43legacydbg(dev->wl, "%u-bit DMA initialized\n", (unsigned int)type);
1098         err = 0;
1099 out:
1100         return err;
1101
1102 err_destroy_rx0:
1103         b43legacy_destroy_dmaring(dma->rx_ring0);
1104         dma->rx_ring0 = NULL;
1105 err_destroy_tx5:
1106         b43legacy_destroy_dmaring(dma->tx_ring5);
1107         dma->tx_ring5 = NULL;
1108 err_destroy_tx4:
1109         b43legacy_destroy_dmaring(dma->tx_ring4);
1110         dma->tx_ring4 = NULL;
1111 err_destroy_tx3:
1112         b43legacy_destroy_dmaring(dma->tx_ring3);
1113         dma->tx_ring3 = NULL;
1114 err_destroy_tx2:
1115         b43legacy_destroy_dmaring(dma->tx_ring2);
1116         dma->tx_ring2 = NULL;
1117 err_destroy_tx1:
1118         b43legacy_destroy_dmaring(dma->tx_ring1);
1119         dma->tx_ring1 = NULL;
1120 err_destroy_tx0:
1121         b43legacy_destroy_dmaring(dma->tx_ring0);
1122         dma->tx_ring0 = NULL;
1123         goto out;
1124 }
1125
1126 /* Generate a cookie for the TX header. */
1127 static u16 generate_cookie(struct b43legacy_dmaring *ring,
1128                            int slot)
1129 {
1130         u16 cookie = 0x1000;
1131
1132         /* Use the upper 4 bits of the cookie as
1133          * DMA controller ID and store the slot number
1134          * in the lower 12 bits.
1135          * Note that the cookie must never be 0, as this
1136          * is a special value used in RX path.
1137          */
1138         switch (ring->index) {
1139         case 0:
1140                 cookie = 0xA000;
1141                 break;
1142         case 1:
1143                 cookie = 0xB000;
1144                 break;
1145         case 2:
1146                 cookie = 0xC000;
1147                 break;
1148         case 3:
1149                 cookie = 0xD000;
1150                 break;
1151         case 4:
1152                 cookie = 0xE000;
1153                 break;
1154         case 5:
1155                 cookie = 0xF000;
1156                 break;
1157         }
1158         B43legacy_WARN_ON(!(((u16)slot & 0xF000) == 0x0000));
1159         cookie |= (u16)slot;
1160
1161         return cookie;
1162 }
1163
1164 /* Inspect a cookie and find out to which controller/slot it belongs. */
1165 static
1166 struct b43legacy_dmaring *parse_cookie(struct b43legacy_wldev *dev,
1167                                       u16 cookie, int *slot)
1168 {
1169         struct b43legacy_dma *dma = &dev->dma;
1170         struct b43legacy_dmaring *ring = NULL;
1171
1172         switch (cookie & 0xF000) {
1173         case 0xA000:
1174                 ring = dma->tx_ring0;
1175                 break;
1176         case 0xB000:
1177                 ring = dma->tx_ring1;
1178                 break;
1179         case 0xC000:
1180                 ring = dma->tx_ring2;
1181                 break;
1182         case 0xD000:
1183                 ring = dma->tx_ring3;
1184                 break;
1185         case 0xE000:
1186                 ring = dma->tx_ring4;
1187                 break;
1188         case 0xF000:
1189                 ring = dma->tx_ring5;
1190                 break;
1191         default:
1192                 B43legacy_WARN_ON(1);
1193         }
1194         *slot = (cookie & 0x0FFF);
1195         B43legacy_WARN_ON(!(ring && *slot >= 0 && *slot < ring->nr_slots));
1196
1197         return ring;
1198 }
1199
1200 static int dma_tx_fragment(struct b43legacy_dmaring *ring,
1201                             struct sk_buff *skb,
1202                             struct ieee80211_tx_control *ctl)
1203 {
1204         const struct b43legacy_dma_ops *ops = ring->ops;
1205         u8 *header;
1206         int slot, old_top_slot, old_used_slots;
1207         int err;
1208         struct b43legacy_dmadesc_generic *desc;
1209         struct b43legacy_dmadesc_meta *meta;
1210         struct b43legacy_dmadesc_meta *meta_hdr;
1211         struct sk_buff *bounce_skb;
1212
1213 #define SLOTS_PER_PACKET  2
1214         B43legacy_WARN_ON(skb_shinfo(skb)->nr_frags != 0);
1215
1216         old_top_slot = ring->current_slot;
1217         old_used_slots = ring->used_slots;
1218
1219         /* Get a slot for the header. */
1220         slot = request_slot(ring);
1221         desc = ops->idx2desc(ring, slot, &meta_hdr);
1222         memset(meta_hdr, 0, sizeof(*meta_hdr));
1223
1224         header = &(ring->txhdr_cache[slot * sizeof(
1225                                struct b43legacy_txhdr_fw3)]);
1226         err = b43legacy_generate_txhdr(ring->dev, header,
1227                                  skb->data, skb->len, ctl,
1228                                  generate_cookie(ring, slot));
1229         if (unlikely(err)) {
1230                 ring->current_slot = old_top_slot;
1231                 ring->used_slots = old_used_slots;
1232                 return err;
1233         }
1234
1235         meta_hdr->dmaaddr = map_descbuffer(ring, (unsigned char *)header,
1236                                            sizeof(struct b43legacy_txhdr_fw3), 1);
1237         if (b43legacy_dma_mapping_error(ring, meta_hdr->dmaaddr,
1238                                         sizeof(struct b43legacy_txhdr_fw3))) {
1239                 ring->current_slot = old_top_slot;
1240                 ring->used_slots = old_used_slots;
1241                 return -EIO;
1242         }
1243         ops->fill_descriptor(ring, desc, meta_hdr->dmaaddr,
1244                              sizeof(struct b43legacy_txhdr_fw3), 1, 0, 0);
1245
1246         /* Get a slot for the payload. */
1247         slot = request_slot(ring);
1248         desc = ops->idx2desc(ring, slot, &meta);
1249         memset(meta, 0, sizeof(*meta));
1250
1251         memcpy(&meta->txstat.control, ctl, sizeof(*ctl));
1252         meta->skb = skb;
1253         meta->is_last_fragment = 1;
1254
1255         meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1256         /* create a bounce buffer in zone_dma on mapping failure. */
1257         if (b43legacy_dma_mapping_error(ring, meta->dmaaddr, skb->len)) {
1258                 bounce_skb = __dev_alloc_skb(skb->len, GFP_ATOMIC | GFP_DMA);
1259                 if (!bounce_skb) {
1260                         ring->current_slot = old_top_slot;
1261                         ring->used_slots = old_used_slots;
1262                         err = -ENOMEM;
1263                         goto out_unmap_hdr;
1264                 }
1265
1266                 memcpy(skb_put(bounce_skb, skb->len), skb->data, skb->len);
1267                 dev_kfree_skb_any(skb);
1268                 skb = bounce_skb;
1269                 meta->skb = skb;
1270                 meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1271                 if (b43legacy_dma_mapping_error(ring, meta->dmaaddr, skb->len)) {
1272                         ring->current_slot = old_top_slot;
1273                         ring->used_slots = old_used_slots;
1274                         err = -EIO;
1275                         goto out_free_bounce;
1276                 }
1277         }
1278
1279         ops->fill_descriptor(ring, desc, meta->dmaaddr,
1280                              skb->len, 0, 1, 1);
1281
1282         wmb();  /* previous stuff MUST be done */
1283         /* Now transfer the whole frame. */
1284         ops->poke_tx(ring, next_slot(ring, slot));
1285         return 0;
1286
1287 out_free_bounce:
1288         dev_kfree_skb_any(skb);
1289 out_unmap_hdr:
1290         unmap_descbuffer(ring, meta_hdr->dmaaddr,
1291                          sizeof(struct b43legacy_txhdr_fw3), 1);
1292         return err;
1293 }
1294
1295 static inline
1296 int should_inject_overflow(struct b43legacy_dmaring *ring)
1297 {
1298 #ifdef CONFIG_B43LEGACY_DEBUG
1299         if (unlikely(b43legacy_debug(ring->dev,
1300                                      B43legacy_DBG_DMAOVERFLOW))) {
1301                 /* Check if we should inject another ringbuffer overflow
1302                  * to test handling of this situation in the stack. */
1303                 unsigned long next_overflow;
1304
1305                 next_overflow = ring->last_injected_overflow + HZ;
1306                 if (time_after(jiffies, next_overflow)) {
1307                         ring->last_injected_overflow = jiffies;
1308                         b43legacydbg(ring->dev->wl,
1309                                "Injecting TX ring overflow on "
1310                                "DMA controller %d\n", ring->index);
1311                         return 1;
1312                 }
1313         }
1314 #endif /* CONFIG_B43LEGACY_DEBUG */
1315         return 0;
1316 }
1317
1318 int b43legacy_dma_tx(struct b43legacy_wldev *dev,
1319                      struct sk_buff *skb,
1320                      struct ieee80211_tx_control *ctl)
1321 {
1322         struct b43legacy_dmaring *ring;
1323         int err = 0;
1324         unsigned long flags;
1325
1326         ring = priority_to_txring(dev, ctl->queue);
1327         spin_lock_irqsave(&ring->lock, flags);
1328         B43legacy_WARN_ON(!ring->tx);
1329         if (unlikely(free_slots(ring) < SLOTS_PER_PACKET)) {
1330                 b43legacywarn(dev->wl, "DMA queue overflow\n");
1331                 err = -ENOSPC;
1332                 goto out_unlock;
1333         }
1334         /* Check if the queue was stopped in mac80211,
1335          * but we got called nevertheless.
1336          * That would be a mac80211 bug. */
1337         B43legacy_BUG_ON(ring->stopped);
1338
1339         err = dma_tx_fragment(ring, skb, ctl);
1340         if (unlikely(err == -ENOKEY)) {
1341                 /* Drop this packet, as we don't have the encryption key
1342                  * anymore and must not transmit it unencrypted. */
1343                 dev_kfree_skb_any(skb);
1344                 err = 0;
1345                 goto out_unlock;
1346         }
1347         if (unlikely(err)) {
1348                 b43legacyerr(dev->wl, "DMA tx mapping failure\n");
1349                 goto out_unlock;
1350         }
1351         ring->nr_tx_packets++;
1352         if ((free_slots(ring) < SLOTS_PER_PACKET) ||
1353             should_inject_overflow(ring)) {
1354                 /* This TX ring is full. */
1355                 ieee80211_stop_queue(dev->wl->hw, txring_to_priority(ring));
1356                 ring->stopped = 1;
1357                 if (b43legacy_debug(dev, B43legacy_DBG_DMAVERBOSE))
1358                         b43legacydbg(dev->wl, "Stopped TX ring %d\n",
1359                                ring->index);
1360         }
1361 out_unlock:
1362         spin_unlock_irqrestore(&ring->lock, flags);
1363
1364         return err;
1365 }
1366
1367 void b43legacy_dma_handle_txstatus(struct b43legacy_wldev *dev,
1368                                  const struct b43legacy_txstatus *status)
1369 {
1370         const struct b43legacy_dma_ops *ops;
1371         struct b43legacy_dmaring *ring;
1372         struct b43legacy_dmadesc_generic *desc;
1373         struct b43legacy_dmadesc_meta *meta;
1374         int slot;
1375
1376         ring = parse_cookie(dev, status->cookie, &slot);
1377         if (unlikely(!ring))
1378                 return;
1379         B43legacy_WARN_ON(!irqs_disabled());
1380         spin_lock(&ring->lock);
1381
1382         B43legacy_WARN_ON(!ring->tx);
1383         ops = ring->ops;
1384         while (1) {
1385                 B43legacy_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
1386                 desc = ops->idx2desc(ring, slot, &meta);
1387
1388                 if (meta->skb)
1389                         unmap_descbuffer(ring, meta->dmaaddr,
1390                                          meta->skb->len, 1);
1391                 else
1392                         unmap_descbuffer(ring, meta->dmaaddr,
1393                                          sizeof(struct b43legacy_txhdr_fw3),
1394                                          1);
1395
1396                 if (meta->is_last_fragment) {
1397                         B43legacy_WARN_ON(!meta->skb);
1398                         /* Call back to inform the ieee80211 subsystem about the
1399                          * status of the transmission.
1400                          * Some fields of txstat are already filled in dma_tx().
1401                          */
1402                         if (status->acked) {
1403                                 meta->txstat.flags |= IEEE80211_TX_STATUS_ACK;
1404                         } else {
1405                                 if (!(meta->txstat.control.flags
1406                                       & IEEE80211_TXCTL_NO_ACK))
1407                                          meta->txstat.excessive_retries = 1;
1408                         }
1409                         if (status->frame_count == 0) {
1410                                 /* The frame was not transmitted at all. */
1411                                 meta->txstat.retry_count = 0;
1412                         } else
1413                                 meta->txstat.retry_count = status->frame_count
1414                                                            - 1;
1415                         ieee80211_tx_status_irqsafe(dev->wl->hw, meta->skb,
1416                                                     &(meta->txstat));
1417                         /* skb is freed by ieee80211_tx_status_irqsafe() */
1418                         meta->skb = NULL;
1419                 } else {
1420                         /* No need to call free_descriptor_buffer here, as
1421                          * this is only the txhdr, which is not allocated.
1422                          */
1423                         B43legacy_WARN_ON(meta->skb != NULL);
1424                 }
1425
1426                 /* Everything unmapped and free'd. So it's not used anymore. */
1427                 ring->used_slots--;
1428
1429                 if (meta->is_last_fragment)
1430                         break;
1431                 slot = next_slot(ring, slot);
1432         }
1433         dev->stats.last_tx = jiffies;
1434         if (ring->stopped) {
1435                 B43legacy_WARN_ON(free_slots(ring) < SLOTS_PER_PACKET);
1436                 ieee80211_wake_queue(dev->wl->hw, txring_to_priority(ring));
1437                 ring->stopped = 0;
1438                 if (b43legacy_debug(dev, B43legacy_DBG_DMAVERBOSE))
1439                         b43legacydbg(dev->wl, "Woke up TX ring %d\n",
1440                                ring->index);
1441         }
1442
1443         spin_unlock(&ring->lock);
1444 }
1445
1446 void b43legacy_dma_get_tx_stats(struct b43legacy_wldev *dev,
1447                               struct ieee80211_tx_queue_stats *stats)
1448 {
1449         const int nr_queues = dev->wl->hw->queues;
1450         struct b43legacy_dmaring *ring;
1451         struct ieee80211_tx_queue_stats_data *data;
1452         unsigned long flags;
1453         int i;
1454
1455         for (i = 0; i < nr_queues; i++) {
1456                 data = &(stats->data[i]);
1457                 ring = priority_to_txring(dev, i);
1458
1459                 spin_lock_irqsave(&ring->lock, flags);
1460                 data->len = ring->used_slots / SLOTS_PER_PACKET;
1461                 data->limit = ring->nr_slots / SLOTS_PER_PACKET;
1462                 data->count = ring->nr_tx_packets;
1463                 spin_unlock_irqrestore(&ring->lock, flags);
1464         }
1465 }
1466
1467 static void dma_rx(struct b43legacy_dmaring *ring,
1468                    int *slot)
1469 {
1470         const struct b43legacy_dma_ops *ops = ring->ops;
1471         struct b43legacy_dmadesc_generic *desc;
1472         struct b43legacy_dmadesc_meta *meta;
1473         struct b43legacy_rxhdr_fw3 *rxhdr;
1474         struct sk_buff *skb;
1475         u16 len;
1476         int err;
1477         dma_addr_t dmaaddr;
1478
1479         desc = ops->idx2desc(ring, *slot, &meta);
1480
1481         sync_descbuffer_for_cpu(ring, meta->dmaaddr, ring->rx_buffersize);
1482         skb = meta->skb;
1483
1484         if (ring->index == 3) {
1485                 /* We received an xmit status. */
1486                 struct b43legacy_hwtxstatus *hw =
1487                                 (struct b43legacy_hwtxstatus *)skb->data;
1488                 int i = 0;
1489
1490                 while (hw->cookie == 0) {
1491                         if (i > 100)
1492                                 break;
1493                         i++;
1494                         udelay(2);
1495                         barrier();
1496                 }
1497                 b43legacy_handle_hwtxstatus(ring->dev, hw);
1498                 /* recycle the descriptor buffer. */
1499                 sync_descbuffer_for_device(ring, meta->dmaaddr,
1500                                            ring->rx_buffersize);
1501
1502                 return;
1503         }
1504         rxhdr = (struct b43legacy_rxhdr_fw3 *)skb->data;
1505         len = le16_to_cpu(rxhdr->frame_len);
1506         if (len == 0) {
1507                 int i = 0;
1508
1509                 do {
1510                         udelay(2);
1511                         barrier();
1512                         len = le16_to_cpu(rxhdr->frame_len);
1513                 } while (len == 0 && i++ < 5);
1514                 if (unlikely(len == 0)) {
1515                         /* recycle the descriptor buffer. */
1516                         sync_descbuffer_for_device(ring, meta->dmaaddr,
1517                                                    ring->rx_buffersize);
1518                         goto drop;
1519                 }
1520         }
1521         if (unlikely(len > ring->rx_buffersize)) {
1522                 /* The data did not fit into one descriptor buffer
1523                  * and is split over multiple buffers.
1524                  * This should never happen, as we try to allocate buffers
1525                  * big enough. So simply ignore this packet.
1526                  */
1527                 int cnt = 0;
1528                 s32 tmp = len;
1529
1530                 while (1) {
1531                         desc = ops->idx2desc(ring, *slot, &meta);
1532                         /* recycle the descriptor buffer. */
1533                         sync_descbuffer_for_device(ring, meta->dmaaddr,
1534                                                    ring->rx_buffersize);
1535                         *slot = next_slot(ring, *slot);
1536                         cnt++;
1537                         tmp -= ring->rx_buffersize;
1538                         if (tmp <= 0)
1539                                 break;
1540                 }
1541                 b43legacyerr(ring->dev->wl, "DMA RX buffer too small "
1542                        "(len: %u, buffer: %u, nr-dropped: %d)\n",
1543                        len, ring->rx_buffersize, cnt);
1544                 goto drop;
1545         }
1546
1547         dmaaddr = meta->dmaaddr;
1548         err = setup_rx_descbuffer(ring, desc, meta, GFP_ATOMIC);
1549         if (unlikely(err)) {
1550                 b43legacydbg(ring->dev->wl, "DMA RX: setup_rx_descbuffer()"
1551                              " failed\n");
1552                 sync_descbuffer_for_device(ring, dmaaddr,
1553                                            ring->rx_buffersize);
1554                 goto drop;
1555         }
1556
1557         unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0);
1558         skb_put(skb, len + ring->frameoffset);
1559         skb_pull(skb, ring->frameoffset);
1560
1561         b43legacy_rx(ring->dev, skb, rxhdr);
1562 drop:
1563         return;
1564 }
1565
1566 void b43legacy_dma_rx(struct b43legacy_dmaring *ring)
1567 {
1568         const struct b43legacy_dma_ops *ops = ring->ops;
1569         int slot;
1570         int current_slot;
1571         int used_slots = 0;
1572
1573         B43legacy_WARN_ON(ring->tx);
1574         current_slot = ops->get_current_rxslot(ring);
1575         B43legacy_WARN_ON(!(current_slot >= 0 && current_slot <
1576                            ring->nr_slots));
1577
1578         slot = ring->current_slot;
1579         for (; slot != current_slot; slot = next_slot(ring, slot)) {
1580                 dma_rx(ring, &slot);
1581                 update_max_used_slots(ring, ++used_slots);
1582         }
1583         ops->set_current_rxslot(ring, slot);
1584         ring->current_slot = slot;
1585 }
1586
1587 static void b43legacy_dma_tx_suspend_ring(struct b43legacy_dmaring *ring)
1588 {
1589         unsigned long flags;
1590
1591         spin_lock_irqsave(&ring->lock, flags);
1592         B43legacy_WARN_ON(!ring->tx);
1593         ring->ops->tx_suspend(ring);
1594         spin_unlock_irqrestore(&ring->lock, flags);
1595 }
1596
1597 static void b43legacy_dma_tx_resume_ring(struct b43legacy_dmaring *ring)
1598 {
1599         unsigned long flags;
1600
1601         spin_lock_irqsave(&ring->lock, flags);
1602         B43legacy_WARN_ON(!ring->tx);
1603         ring->ops->tx_resume(ring);
1604         spin_unlock_irqrestore(&ring->lock, flags);
1605 }
1606
1607 void b43legacy_dma_tx_suspend(struct b43legacy_wldev *dev)
1608 {
1609         b43legacy_power_saving_ctl_bits(dev, -1, 1);
1610         b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring0);
1611         b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring1);
1612         b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring2);
1613         b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring3);
1614         b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring4);
1615         b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring5);
1616 }
1617
1618 void b43legacy_dma_tx_resume(struct b43legacy_wldev *dev)
1619 {
1620         b43legacy_dma_tx_resume_ring(dev->dma.tx_ring5);
1621         b43legacy_dma_tx_resume_ring(dev->dma.tx_ring4);
1622         b43legacy_dma_tx_resume_ring(dev->dma.tx_ring3);
1623         b43legacy_dma_tx_resume_ring(dev->dma.tx_ring2);
1624         b43legacy_dma_tx_resume_ring(dev->dma.tx_ring1);
1625         b43legacy_dma_tx_resume_ring(dev->dma.tx_ring0);
1626         b43legacy_power_saving_ctl_bits(dev, -1, -1);
1627 }