2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
19 #include "ar9003_mac.h"
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define TIME_SYMBOLS(t) ((t) >> 2)
33 #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
34 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
38 static u16 bits_per_symbol[][2] = {
40 { 26, 54 }, /* 0: BPSK */
41 { 52, 108 }, /* 1: QPSK 1/2 */
42 { 78, 162 }, /* 2: QPSK 3/4 */
43 { 104, 216 }, /* 3: 16-QAM 1/2 */
44 { 156, 324 }, /* 4: 16-QAM 3/4 */
45 { 208, 432 }, /* 5: 64-QAM 2/3 */
46 { 234, 486 }, /* 6: 64-QAM 3/4 */
47 { 260, 540 }, /* 7: 64-QAM 5/6 */
50 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
51 struct ath_atx_tid *tid, struct sk_buff *skb);
52 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
53 int tx_flags, struct ath_txq *txq,
54 struct ieee80211_sta *sta);
55 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
56 struct ath_txq *txq, struct list_head *bf_q,
57 struct ieee80211_sta *sta,
58 struct ath_tx_status *ts, int txok);
59 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
60 struct list_head *head, bool internal);
61 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
62 struct ath_tx_status *ts, int nframes, int nbad,
64 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
66 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
68 struct ath_atx_tid *tid,
70 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
71 struct ath_tx_control *txctl);
80 /*********************/
81 /* Aggregation logic */
82 /*********************/
84 static void ath_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb)
86 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
87 struct ieee80211_sta *sta = info->status.status_driver_data[0];
89 if (info->flags & (IEEE80211_TX_CTL_REQ_TX_STATUS |
90 IEEE80211_TX_STATUS_EOSP)) {
91 ieee80211_tx_status(hw, skb);
96 ieee80211_tx_status_noskb(hw, sta, info);
101 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq)
102 __releases(&txq->axq_lock)
104 struct ieee80211_hw *hw = sc->hw;
105 struct sk_buff_head q;
108 __skb_queue_head_init(&q);
109 skb_queue_splice_init(&txq->complete_q, &q);
110 spin_unlock_bh(&txq->axq_lock);
112 while ((skb = __skb_dequeue(&q)))
113 ath_tx_status(hw, skb);
116 void __ath_tx_queue_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
118 struct ath_vif *avp = (struct ath_vif *) tid->an->vif->drv_priv;
119 struct ath_chanctx *ctx = avp->chanctx;
121 struct list_head *tid_list;
122 u8 acno = TID_TO_WME_AC(tid->tidno);
124 if (!ctx || !list_empty(&tid->list))
128 acq = &ctx->acq[acno];
129 if ((sc->airtime_flags & AIRTIME_USE_NEW_QUEUES) &&
130 tid->an->airtime_deficit[acno] > 0)
131 tid_list = &acq->acq_new;
133 tid_list = &acq->acq_old;
135 list_add_tail(&tid->list, tid_list);
138 void ath_tx_queue_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
140 struct ath_vif *avp = (struct ath_vif *) tid->an->vif->drv_priv;
141 struct ath_chanctx *ctx = avp->chanctx;
144 if (!ctx || !list_empty(&tid->list))
147 acq = &ctx->acq[TID_TO_WME_AC(tid->tidno)];
148 spin_lock_bh(&acq->lock);
149 __ath_tx_queue_tid(sc, tid);
150 spin_unlock_bh(&acq->lock);
154 void ath9k_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *queue)
156 struct ath_softc *sc = hw->priv;
157 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
158 struct ath_atx_tid *tid = (struct ath_atx_tid *) queue->drv_priv;
159 struct ath_txq *txq = tid->txq;
161 ath_dbg(common, QUEUE, "Waking TX queue: %pM (%d)\n",
162 queue->sta ? queue->sta->addr : queue->vif->addr,
165 ath_txq_lock(sc, txq);
167 tid->has_queued = true;
168 ath_tx_queue_tid(sc, tid);
169 ath_txq_schedule(sc, txq);
171 ath_txq_unlock(sc, txq);
174 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
176 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
177 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
178 sizeof(tx_info->rate_driver_data));
179 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
182 static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
187 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
188 seqno << IEEE80211_SEQ_SEQ_SHIFT);
191 static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta,
194 ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates,
195 ARRAY_SIZE(bf->rates));
198 static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq,
201 struct ath_frame_info *fi = get_frame_info(skb);
207 txq = sc->tx.txq_map[q];
208 if (WARN_ON(--txq->pending_frames < 0))
209 txq->pending_frames = 0;
213 static struct ath_atx_tid *
214 ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb)
216 u8 tidno = skb->priority & IEEE80211_QOS_CTL_TID_MASK;
217 return ATH_AN_2_TID(an, tidno);
220 static struct sk_buff *
221 ath_tid_pull(struct ath_atx_tid *tid)
223 struct ieee80211_txq *txq = container_of((void*)tid, struct ieee80211_txq, drv_priv);
224 struct ath_softc *sc = tid->an->sc;
225 struct ieee80211_hw *hw = sc->hw;
226 struct ath_tx_control txctl = {
231 struct ath_frame_info *fi;
234 if (!tid->has_queued)
237 skb = ieee80211_tx_dequeue(hw, txq);
239 tid->has_queued = false;
243 if (ath_tx_prepare(hw, skb, &txctl)) {
244 ieee80211_free_txskb(hw, skb);
248 q = skb_get_queue_mapping(skb);
249 if (tid->txq == sc->tx.txq_map[q]) {
250 fi = get_frame_info(skb);
252 ++tid->txq->pending_frames;
259 static bool ath_tid_has_buffered(struct ath_atx_tid *tid)
261 return !skb_queue_empty(&tid->retry_q) || tid->has_queued;
264 static struct sk_buff *ath_tid_dequeue(struct ath_atx_tid *tid)
268 skb = __skb_dequeue(&tid->retry_q);
270 skb = ath_tid_pull(tid);
275 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
277 struct ath_txq *txq = tid->txq;
280 struct list_head bf_head;
281 struct ath_tx_status ts;
282 struct ath_frame_info *fi;
283 bool sendbar = false;
285 INIT_LIST_HEAD(&bf_head);
287 memset(&ts, 0, sizeof(ts));
289 while ((skb = __skb_dequeue(&tid->retry_q))) {
290 fi = get_frame_info(skb);
293 ath_txq_skb_done(sc, txq, skb);
294 ieee80211_free_txskb(sc->hw, skb);
298 if (fi->baw_tracked) {
299 ath_tx_update_baw(sc, tid, bf);
303 list_add_tail(&bf->list, &bf_head);
304 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0);
308 ath_txq_unlock(sc, txq);
309 ath_send_bar(tid, tid->seq_start);
310 ath_txq_lock(sc, txq);
314 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
317 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
318 u16 seqno = bf->bf_state.seqno;
321 if (!fi->baw_tracked)
324 index = ATH_BA_INDEX(tid->seq_start, seqno);
325 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
327 __clear_bit(cindex, tid->tx_buf);
329 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
330 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
331 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
332 if (tid->bar_index >= 0)
337 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
340 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
341 u16 seqno = bf->bf_state.seqno;
347 index = ATH_BA_INDEX(tid->seq_start, seqno);
348 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
349 __set_bit(cindex, tid->tx_buf);
352 if (index >= ((tid->baw_tail - tid->baw_head) &
353 (ATH_TID_MAX_BUFS - 1))) {
354 tid->baw_tail = cindex;
355 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
359 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
360 struct ath_atx_tid *tid)
365 struct list_head bf_head;
366 struct ath_tx_status ts;
367 struct ath_frame_info *fi;
369 memset(&ts, 0, sizeof(ts));
370 INIT_LIST_HEAD(&bf_head);
372 while ((skb = ath_tid_dequeue(tid))) {
373 fi = get_frame_info(skb);
377 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq, NULL);
381 list_add_tail(&bf->list, &bf_head);
382 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0);
386 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
387 struct sk_buff *skb, int count)
389 struct ath_frame_info *fi = get_frame_info(skb);
390 struct ath_buf *bf = fi->bf;
391 struct ieee80211_hdr *hdr;
392 int prev = fi->retries;
394 TX_STAT_INC(sc, txq->axq_qnum, a_retries);
395 fi->retries += count;
400 hdr = (struct ieee80211_hdr *)skb->data;
401 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
402 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
403 sizeof(*hdr), DMA_TO_DEVICE);
406 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
408 struct ath_buf *bf = NULL;
410 spin_lock_bh(&sc->tx.txbuflock);
412 if (unlikely(list_empty(&sc->tx.txbuf))) {
413 spin_unlock_bh(&sc->tx.txbuflock);
417 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
420 spin_unlock_bh(&sc->tx.txbuflock);
425 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
427 spin_lock_bh(&sc->tx.txbuflock);
428 list_add_tail(&bf->list, &sc->tx.txbuf);
429 spin_unlock_bh(&sc->tx.txbuflock);
432 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
436 tbf = ath_tx_get_buffer(sc);
440 ATH_TXBUF_RESET(tbf);
442 tbf->bf_mpdu = bf->bf_mpdu;
443 tbf->bf_buf_addr = bf->bf_buf_addr;
444 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
445 tbf->bf_state = bf->bf_state;
446 tbf->bf_state.stale = false;
451 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
452 struct ath_tx_status *ts, int txok,
453 int *nframes, int *nbad)
455 struct ath_frame_info *fi;
457 u32 ba[WME_BA_BMP_SIZE >> 5];
464 isaggr = bf_isaggr(bf);
466 seq_st = ts->ts_seqnum;
467 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
471 fi = get_frame_info(bf->bf_mpdu);
472 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
475 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
483 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
484 struct ath_buf *bf, struct list_head *bf_q,
485 struct ieee80211_sta *sta,
486 struct ath_atx_tid *tid,
487 struct ath_tx_status *ts, int txok)
489 struct ath_node *an = NULL;
491 struct ieee80211_hdr *hdr;
492 struct ieee80211_tx_info *tx_info;
493 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
494 struct list_head bf_head;
495 struct sk_buff_head bf_pending;
496 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
497 u32 ba[WME_BA_BMP_SIZE >> 5];
498 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
499 bool rc_update = true, isba;
500 struct ieee80211_tx_rate rates[4];
501 struct ath_frame_info *fi;
503 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
508 hdr = (struct ieee80211_hdr *)skb->data;
510 tx_info = IEEE80211_SKB_CB(skb);
512 memcpy(rates, bf->rates, sizeof(rates));
514 retries = ts->ts_longretry + 1;
515 for (i = 0; i < ts->ts_rateindex; i++)
516 retries += rates[i].count;
519 INIT_LIST_HEAD(&bf_head);
521 bf_next = bf->bf_next;
523 if (!bf->bf_state.stale || bf_next != NULL)
524 list_move_tail(&bf->list, &bf_head);
526 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, ts, 0);
533 an = (struct ath_node *)sta->drv_priv;
534 seq_first = tid->seq_start;
535 isba = ts->ts_flags & ATH9K_TX_BA;
538 * The hardware occasionally sends a tx status for the wrong TID.
539 * In this case, the BA status cannot be considered valid and all
540 * subframes need to be retransmitted
542 * Only BlockAcks have a TID and therefore normal Acks cannot be
545 if (isba && tid->tidno != ts->tid)
548 isaggr = bf_isaggr(bf);
549 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
551 if (isaggr && txok) {
552 if (ts->ts_flags & ATH9K_TX_BA) {
553 seq_st = ts->ts_seqnum;
554 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
557 * AR5416 can become deaf/mute when BA
558 * issue happens. Chip needs to be reset.
559 * But AP code may have sychronization issues
560 * when perform internal reset in this routine.
561 * Only enable reset in STA mode for now.
563 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
568 __skb_queue_head_init(&bf_pending);
570 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
572 u16 seqno = bf->bf_state.seqno;
574 txfail = txpending = sendbar = 0;
575 bf_next = bf->bf_next;
578 tx_info = IEEE80211_SKB_CB(skb);
579 fi = get_frame_info(skb);
581 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno) ||
584 * Outside of the current BlockAck window,
585 * maybe part of a previous session
588 } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
589 /* transmit completion, subframe is
590 * acked by block ack */
592 } else if (!isaggr && txok) {
593 /* transmit completion */
597 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
598 if (txok || !an->sleeping)
599 ath_tx_set_retry(sc, txq, bf->bf_mpdu,
606 bar_index = max_t(int, bar_index,
607 ATH_BA_INDEX(seq_first, seqno));
611 * Make sure the last desc is reclaimed if it
612 * not a holding desc.
614 INIT_LIST_HEAD(&bf_head);
615 if (bf_next != NULL || !bf_last->bf_state.stale)
616 list_move_tail(&bf->list, &bf_head);
620 * complete the acked-ones/xretried ones; update
623 ath_tx_update_baw(sc, tid, bf);
625 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
626 memcpy(tx_info->control.rates, rates, sizeof(rates));
627 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
629 if (bf == bf->bf_lastbf)
630 ath_dynack_sample_tx_ts(sc->sc_ah,
635 ath_tx_complete_buf(sc, bf, txq, &bf_head, sta, ts,
638 if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) {
639 tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP;
640 ieee80211_sta_eosp(sta);
642 /* retry the un-acked ones */
643 if (bf->bf_next == NULL && bf_last->bf_state.stale) {
646 tbf = ath_clone_txbuf(sc, bf_last);
648 * Update tx baw and complete the
649 * frame with failed status if we
653 ath_tx_update_baw(sc, tid, bf);
655 ath_tx_complete_buf(sc, bf, txq,
658 bar_index = max_t(int, bar_index,
659 ATH_BA_INDEX(seq_first, seqno));
667 * Put this buffer to the temporary pending
668 * queue to retain ordering
670 __skb_queue_tail(&bf_pending, skb);
676 /* prepend un-acked frames to the beginning of the pending frame queue */
677 if (!skb_queue_empty(&bf_pending)) {
679 ieee80211_sta_set_buffered(sta, tid->tidno, true);
681 skb_queue_splice_tail(&bf_pending, &tid->retry_q);
683 ath_tx_queue_tid(sc, tid);
685 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
686 tid->clear_ps_filter = true;
690 if (bar_index >= 0) {
691 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
693 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
694 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
696 ath_txq_unlock(sc, txq);
697 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
698 ath_txq_lock(sc, txq);
702 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR);
705 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
707 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
708 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
711 static void ath_tx_count_airtime(struct ath_softc *sc, struct ath_node *an,
712 struct ath_atx_tid *tid, struct ath_buf *bf,
713 struct ath_tx_status *ts)
715 struct ath_txq *txq = tid->txq;
719 airtime += ts->duration * (ts->ts_longretry + 1);
720 for(i = 0; i < ts->ts_rateindex; i++) {
721 int rate_dur = ath9k_hw_get_duration(sc->sc_ah, bf->bf_desc, i);
722 airtime += rate_dur * bf->rates[i].count;
725 if (sc->airtime_flags & AIRTIME_USE_TX) {
726 int q = txq->mac80211_qnum;
727 struct ath_acq *acq = &sc->cur_chan->acq[q];
729 spin_lock_bh(&acq->lock);
730 an->airtime_deficit[q] -= airtime;
731 if (an->airtime_deficit[q] <= 0)
732 __ath_tx_queue_tid(sc, tid);
733 spin_unlock_bh(&acq->lock);
735 ath_debug_airtime(sc, an, 0, airtime);
738 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
739 struct ath_tx_status *ts, struct ath_buf *bf,
740 struct list_head *bf_head)
742 struct ieee80211_hw *hw = sc->hw;
743 struct ieee80211_tx_info *info;
744 struct ieee80211_sta *sta;
745 struct ieee80211_hdr *hdr;
746 struct ath_atx_tid *tid = NULL;
749 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
750 flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
751 txq->axq_tx_inprogress = false;
754 if (bf_is_ampdu_not_probing(bf))
755 txq->axq_ampdu_depth--;
757 ts->duration = ath9k_hw_get_duration(sc->sc_ah, bf->bf_desc,
760 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
761 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
763 struct ath_node *an = (struct ath_node *)sta->drv_priv;
764 tid = ath_get_skb_tid(sc, an, bf->bf_mpdu);
765 ath_tx_count_airtime(sc, an, tid, bf, ts);
766 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
767 tid->clear_ps_filter = true;
770 if (!bf_isampdu(bf)) {
772 info = IEEE80211_SKB_CB(bf->bf_mpdu);
773 memcpy(info->control.rates, bf->rates,
774 sizeof(info->control.rates));
775 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
776 ath_dynack_sample_tx_ts(sc->sc_ah, bf->bf_mpdu, ts);
778 ath_tx_complete_buf(sc, bf, txq, bf_head, sta, ts, txok);
780 ath_tx_complete_aggr(sc, txq, bf, bf_head, sta, tid, ts, txok);
783 ath_txq_schedule(sc, txq);
786 static bool ath_lookup_legacy(struct ath_buf *bf)
789 struct ieee80211_tx_info *tx_info;
790 struct ieee80211_tx_rate *rates;
794 tx_info = IEEE80211_SKB_CB(skb);
795 rates = tx_info->control.rates;
797 for (i = 0; i < 4; i++) {
798 if (!rates[i].count || rates[i].idx < 0)
801 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
808 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
809 struct ath_atx_tid *tid)
812 struct ieee80211_tx_info *tx_info;
813 struct ieee80211_tx_rate *rates;
814 u32 max_4ms_framelen, frmlen;
815 u16 aggr_limit, bt_aggr_limit, legacy = 0;
816 int q = tid->txq->mac80211_qnum;
820 tx_info = IEEE80211_SKB_CB(skb);
824 * Find the lowest frame length among the rate series that will have a
825 * 4ms (or TXOP limited) transmit duration.
827 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
829 for (i = 0; i < 4; i++) {
835 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
840 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
845 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
848 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx];
849 max_4ms_framelen = min(max_4ms_framelen, frmlen);
853 * limit aggregate size by the minimum rate if rate selected is
854 * not a probe rate, if rate selected is a probe rate then
855 * avoid aggregation of this packet.
857 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
860 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX);
863 * Override the default aggregation limit for BTCOEX.
865 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen);
867 aggr_limit = bt_aggr_limit;
869 if (tid->an->maxampdu)
870 aggr_limit = min(aggr_limit, tid->an->maxampdu);
876 * Returns the number of delimiters to be added to
877 * meet the minimum required mpdudensity.
879 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
880 struct ath_buf *bf, u16 frmlen,
883 #define FIRST_DESC_NDELIMS 60
884 u32 nsymbits, nsymbols;
887 int width, streams, half_gi, ndelim, mindelim;
888 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
890 /* Select standard number of delimiters based on frame length alone */
891 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
894 * If encryption enabled, hardware requires some more padding between
896 * TODO - this could be improved to be dependent on the rate.
897 * The hardware can keep up at lower rates, but not higher rates
899 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
900 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
901 ndelim += ATH_AGGR_ENCRYPTDELIM;
904 * Add delimiter when using RTS/CTS with aggregation
905 * and non enterprise AR9003 card
907 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
908 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
909 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
912 * Convert desired mpdu density from microeconds to bytes based
913 * on highest rate in rate series (i.e. first rate) to determine
914 * required minimum length for subframe. Take into account
915 * whether high rate is 20 or 40Mhz and half or full GI.
917 * If there is no mpdu density restriction, no further calculation
921 if (tid->an->mpdudensity == 0)
924 rix = bf->rates[0].idx;
925 flags = bf->rates[0].flags;
926 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
927 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
930 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
932 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
937 streams = HT_RC_2_STREAMS(rix);
938 nsymbits = bits_per_symbol[rix % 8][width] * streams;
939 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
941 if (frmlen < minlen) {
942 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
943 ndelim = max(mindelim, ndelim);
949 static struct ath_buf *
950 ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq,
951 struct ath_atx_tid *tid)
953 struct ieee80211_tx_info *tx_info;
954 struct ath_frame_info *fi;
955 struct sk_buff *skb, *first_skb = NULL;
960 skb = ath_tid_dequeue(tid);
964 fi = get_frame_info(skb);
967 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
969 bf->bf_state.stale = false;
972 ath_txq_skb_done(sc, txq, skb);
973 ieee80211_free_txskb(sc->hw, skb);
980 tx_info = IEEE80211_SKB_CB(skb);
981 tx_info->flags &= ~(IEEE80211_TX_CTL_CLEAR_PS_FILT |
982 IEEE80211_TX_STATUS_EOSP);
985 * No aggregation session is running, but there may be frames
986 * from a previous session or a failed attempt in the queue.
987 * Send them out as normal data frames
990 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU;
992 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
993 bf->bf_state.bf_type = 0;
997 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
998 seqno = bf->bf_state.seqno;
1000 /* do not step over block-ack window */
1001 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) {
1002 __skb_queue_tail(&tid->retry_q, skb);
1004 /* If there are other skbs in the retry q, they are
1005 * probably within the BAW, so loop immediately to get
1006 * one of them. Otherwise the queue can get stuck. */
1007 if (!skb_queue_is_first(&tid->retry_q, skb) &&
1008 !WARN_ON(skb == first_skb)) {
1009 if(!first_skb) /* infinite loop prevention */
1016 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
1017 struct ath_tx_status ts = {};
1018 struct list_head bf_head;
1020 INIT_LIST_HEAD(&bf_head);
1021 list_add(&bf->list, &bf_head);
1022 ath_tx_update_baw(sc, tid, bf);
1023 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0);
1028 ath_tx_addto_baw(sc, tid, bf);
1037 ath_tx_form_aggr(struct ath_softc *sc, struct ath_txq *txq,
1038 struct ath_atx_tid *tid, struct list_head *bf_q,
1039 struct ath_buf *bf_first)
1041 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
1042 struct ath_buf *bf = bf_first, *bf_prev = NULL;
1043 int nframes = 0, ndelim;
1044 u16 aggr_limit = 0, al = 0, bpad = 0,
1045 al_delta, h_baw = tid->baw_size / 2;
1046 struct ieee80211_tx_info *tx_info;
1047 struct ath_frame_info *fi;
1048 struct sk_buff *skb;
1052 aggr_limit = ath_lookup_rate(sc, bf, tid);
1057 fi = get_frame_info(skb);
1059 /* do not exceed aggregation limit */
1060 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
1062 if (aggr_limit < al + bpad + al_delta ||
1063 ath_lookup_legacy(bf) || nframes >= h_baw)
1066 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1067 if ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
1068 !(tx_info->flags & IEEE80211_TX_CTL_AMPDU))
1072 /* add padding for previous frame to aggregation length */
1073 al += bpad + al_delta;
1076 * Get the delimiters needed to meet the MPDU
1077 * density for this node.
1079 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
1081 bpad = PADBYTES(al_delta) + (ndelim << 2);
1086 /* link buffers of this frame to the aggregate */
1087 bf->bf_state.ndelim = ndelim;
1089 list_add_tail(&bf->list, bf_q);
1091 bf_prev->bf_next = bf;
1095 bf = ath_tx_get_tid_subframe(sc, txq, tid);
1099 __skb_queue_tail(&tid->retry_q, bf->bf_mpdu);
1102 bf->bf_lastbf = bf_prev;
1104 if (bf == bf_prev) {
1105 al = get_frame_info(bf->bf_mpdu)->framelen;
1106 bf->bf_state.bf_type = BUF_AMPDU;
1108 TX_STAT_INC(sc, txq->axq_qnum, a_aggr);
1117 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1118 * width - 0 for 20 MHz, 1 for 40 MHz
1119 * half_gi - to use 4us v/s 3.6 us for symbol time
1121 u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1122 int width, int half_gi, bool shortPreamble)
1124 u32 nbits, nsymbits, duration, nsymbols;
1127 /* find number of symbols: PLCP + data */
1128 streams = HT_RC_2_STREAMS(rix);
1129 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1130 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1131 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1134 duration = SYMBOL_TIME(nsymbols);
1136 duration = SYMBOL_TIME_HALFGI(nsymbols);
1138 /* addup duration for legacy/ht training and signal fields */
1139 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1144 static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi)
1146 int streams = HT_RC_2_STREAMS(mcs);
1150 usec -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1151 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec);
1152 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams;
1153 bits -= OFDM_PLCP_BITS;
1161 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop)
1163 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi;
1166 /* 4ms is the default (and maximum) duration */
1167 if (!txop || txop > 4096)
1170 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20];
1171 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI];
1172 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40];
1173 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI];
1174 for (mcs = 0; mcs < 32; mcs++) {
1175 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false);
1176 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true);
1177 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false);
1178 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true);
1182 static u8 ath_get_rate_txpower(struct ath_softc *sc, struct ath_buf *bf,
1183 u8 rateidx, bool is_40, bool is_cck)
1186 struct sk_buff *skb;
1187 struct ath_frame_info *fi;
1188 struct ieee80211_tx_info *info;
1189 struct ath_hw *ah = sc->sc_ah;
1191 if (sc->tx99_state || !ah->tpc_enabled)
1192 return MAX_RATE_POWER;
1195 fi = get_frame_info(skb);
1196 info = IEEE80211_SKB_CB(skb);
1198 if (!AR_SREV_9300_20_OR_LATER(ah)) {
1199 int txpower = fi->tx_power;
1203 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1204 u16 eeprom_rev = ah->eep_ops->get_eeprom_rev(ah);
1206 if (eeprom_rev >= AR5416_EEP_MINOR_VER_2) {
1208 struct modal_eep_header *pmodal;
1210 is_2ghz = info->band == NL80211_BAND_2GHZ;
1211 pmodal = &eep->modalHeader[is_2ghz];
1212 power_ht40delta = pmodal->ht40PowerIncForPdadc;
1214 power_ht40delta = 2;
1216 txpower += power_ht40delta;
1219 if (AR_SREV_9287(ah) || AR_SREV_9285(ah) ||
1221 txpower -= 2 * AR9287_PWR_TABLE_OFFSET_DB;
1222 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
1225 power_offset = ah->eep_ops->get_eeprom(ah,
1226 EEP_PWR_TABLE_OFFSET);
1227 txpower -= 2 * power_offset;
1230 if (OLC_FOR_AR9280_20_LATER && is_cck)
1233 txpower = max(txpower, 0);
1234 max_power = min_t(u8, ah->tx_power[rateidx], txpower);
1236 /* XXX: clamp minimum TX power at 1 for AR9160 since if
1237 * max_power is set to 0, frames are transmitted at max
1240 if (!max_power && !AR_SREV_9280_20_OR_LATER(ah))
1242 } else if (!bf->bf_state.bfs_paprd) {
1243 if (rateidx < 8 && (info->flags & IEEE80211_TX_CTL_STBC))
1244 max_power = min_t(u8, ah->tx_power_stbc[rateidx],
1247 max_power = min_t(u8, ah->tx_power[rateidx],
1250 max_power = ah->paprd_training_power;
1256 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
1257 struct ath_tx_info *info, int len, bool rts)
1259 struct ath_hw *ah = sc->sc_ah;
1260 struct ath_common *common = ath9k_hw_common(ah);
1261 struct sk_buff *skb;
1262 struct ieee80211_tx_info *tx_info;
1263 struct ieee80211_tx_rate *rates;
1264 const struct ieee80211_rate *rate;
1265 struct ieee80211_hdr *hdr;
1266 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1267 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1272 tx_info = IEEE80211_SKB_CB(skb);
1274 hdr = (struct ieee80211_hdr *)skb->data;
1276 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1277 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
1278 info->rtscts_rate = fi->rtscts_rate;
1280 for (i = 0; i < ARRAY_SIZE(bf->rates); i++) {
1281 bool is_40, is_sgi, is_sp, is_cck;
1284 if (!rates[i].count || (rates[i].idx < 0))
1288 info->rates[i].Tries = rates[i].count;
1291 * Handle RTS threshold for unaggregated HT frames.
1293 if (bf_isampdu(bf) && !bf_isaggr(bf) &&
1294 (rates[i].flags & IEEE80211_TX_RC_MCS) &&
1295 unlikely(rts_thresh != (u32) -1)) {
1296 if (!rts_thresh || (len > rts_thresh))
1300 if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1301 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1302 info->flags |= ATH9K_TXDESC_RTSENA;
1303 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1304 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1305 info->flags |= ATH9K_TXDESC_CTSENA;
1308 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1309 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
1310 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1311 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1313 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1314 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1315 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1317 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1319 info->rates[i].Rate = rix | 0x80;
1320 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1321 ah->txchainmask, info->rates[i].Rate);
1322 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
1323 is_40, is_sgi, is_sp);
1324 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1325 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
1327 info->txpower[i] = ath_get_rate_txpower(sc, bf, rix,
1333 rate = &common->sbands[tx_info->band].bitrates[rates[i].idx];
1334 if ((tx_info->band == NL80211_BAND_2GHZ) &&
1335 !(rate->flags & IEEE80211_RATE_ERP_G))
1336 phy = WLAN_RC_PHY_CCK;
1338 phy = WLAN_RC_PHY_OFDM;
1340 info->rates[i].Rate = rate->hw_value;
1341 if (rate->hw_value_short) {
1342 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1343 info->rates[i].Rate |= rate->hw_value_short;
1348 if (bf->bf_state.bfs_paprd)
1349 info->rates[i].ChSel = ah->txchainmask;
1351 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1352 ah->txchainmask, info->rates[i].Rate);
1354 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1355 phy, rate->bitrate * 100, len, rix, is_sp);
1357 is_cck = IS_CCK_RATE(info->rates[i].Rate);
1358 info->txpower[i] = ath_get_rate_txpower(sc, bf, rix, false,
1362 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1363 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1364 info->flags &= ~ATH9K_TXDESC_RTSENA;
1366 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1367 if (info->flags & ATH9K_TXDESC_RTSENA)
1368 info->flags &= ~ATH9K_TXDESC_CTSENA;
1371 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1373 struct ieee80211_hdr *hdr;
1374 enum ath9k_pkt_type htype;
1377 hdr = (struct ieee80211_hdr *)skb->data;
1378 fc = hdr->frame_control;
1380 if (ieee80211_is_beacon(fc))
1381 htype = ATH9K_PKT_TYPE_BEACON;
1382 else if (ieee80211_is_probe_resp(fc))
1383 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1384 else if (ieee80211_is_atim(fc))
1385 htype = ATH9K_PKT_TYPE_ATIM;
1386 else if (ieee80211_is_pspoll(fc))
1387 htype = ATH9K_PKT_TYPE_PSPOLL;
1389 htype = ATH9K_PKT_TYPE_NORMAL;
1394 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
1395 struct ath_txq *txq, int len)
1397 struct ath_hw *ah = sc->sc_ah;
1398 struct ath_buf *bf_first = NULL;
1399 struct ath_tx_info info;
1400 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1403 memset(&info, 0, sizeof(info));
1404 info.is_first = true;
1405 info.is_last = true;
1406 info.qcu = txq->axq_qnum;
1409 struct sk_buff *skb = bf->bf_mpdu;
1410 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1411 struct ath_frame_info *fi = get_frame_info(skb);
1412 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1414 info.type = get_hw_packet_type(skb);
1416 info.link = bf->bf_next->bf_daddr;
1418 info.link = (sc->tx99_state) ? bf->bf_daddr : 0;
1423 if (!sc->tx99_state)
1424 info.flags = ATH9K_TXDESC_INTREQ;
1425 if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) ||
1426 txq == sc->tx.uapsdq)
1427 info.flags |= ATH9K_TXDESC_CLRDMASK;
1429 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1430 info.flags |= ATH9K_TXDESC_NOACK;
1431 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1432 info.flags |= ATH9K_TXDESC_LDPC;
1434 if (bf->bf_state.bfs_paprd)
1435 info.flags |= (u32) bf->bf_state.bfs_paprd <<
1436 ATH9K_TXDESC_PAPRD_S;
1439 * mac80211 doesn't handle RTS threshold for HT because
1440 * the decision has to be taken based on AMPDU length
1441 * and aggregation is done entirely inside ath9k.
1442 * Set the RTS/CTS flag for the first subframe based
1445 if (aggr && (bf == bf_first) &&
1446 unlikely(rts_thresh != (u32) -1)) {
1448 * "len" is the size of the entire AMPDU.
1450 if (!rts_thresh || (len > rts_thresh))
1457 ath_buf_set_rate(sc, bf, &info, len, rts);
1460 info.buf_addr[0] = bf->bf_buf_addr;
1461 info.buf_len[0] = skb->len;
1462 info.pkt_len = fi->framelen;
1463 info.keyix = fi->keyix;
1464 info.keytype = fi->keytype;
1468 info.aggr = AGGR_BUF_FIRST;
1469 else if (bf == bf_first->bf_lastbf)
1470 info.aggr = AGGR_BUF_LAST;
1472 info.aggr = AGGR_BUF_MIDDLE;
1474 info.ndelim = bf->bf_state.ndelim;
1475 info.aggr_len = len;
1478 if (bf == bf_first->bf_lastbf)
1481 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1487 ath_tx_form_burst(struct ath_softc *sc, struct ath_txq *txq,
1488 struct ath_atx_tid *tid, struct list_head *bf_q,
1489 struct ath_buf *bf_first)
1491 struct ath_buf *bf = bf_first, *bf_prev = NULL;
1495 struct ieee80211_tx_info *tx_info;
1498 list_add_tail(&bf->list, bf_q);
1500 bf_prev->bf_next = bf;
1506 bf = ath_tx_get_tid_subframe(sc, txq, tid);
1510 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1511 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
1512 __skb_queue_tail(&tid->retry_q, bf->bf_mpdu);
1516 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1520 static bool ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1521 struct ath_atx_tid *tid)
1524 struct ieee80211_tx_info *tx_info;
1525 struct list_head bf_q;
1529 if (!ath_tid_has_buffered(tid))
1532 INIT_LIST_HEAD(&bf_q);
1534 bf = ath_tx_get_tid_subframe(sc, txq, tid);
1538 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1539 aggr = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU);
1540 if ((aggr && txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) ||
1541 (!aggr && txq->axq_depth >= ATH_NON_AGGR_MIN_QDEPTH)) {
1542 __skb_queue_tail(&tid->retry_q, bf->bf_mpdu);
1546 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1548 aggr_len = ath_tx_form_aggr(sc, txq, tid, &bf_q, bf);
1550 ath_tx_form_burst(sc, txq, tid, &bf_q, bf);
1552 if (list_empty(&bf_q))
1555 if (tid->clear_ps_filter || tid->an->no_ps_filter) {
1556 tid->clear_ps_filter = false;
1557 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1560 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1561 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1565 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1568 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1569 struct ath_atx_tid *txtid;
1570 struct ath_txq *txq;
1571 struct ath_node *an;
1574 ath_dbg(common, XMIT, "%s called\n", __func__);
1576 an = (struct ath_node *)sta->drv_priv;
1577 txtid = ATH_AN_2_TID(an, tid);
1580 ath_txq_lock(sc, txq);
1582 /* update ampdu factor/density, they may have changed. This may happen
1583 * in HT IBSS when a beacon with HT-info is received after the station
1584 * has already been added.
1586 if (sta->ht_cap.ht_supported) {
1587 an->maxampdu = (1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
1588 sta->ht_cap.ampdu_factor)) - 1;
1589 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
1590 an->mpdudensity = density;
1593 txtid->active = true;
1594 *ssn = txtid->seq_start = txtid->seq_next;
1595 txtid->bar_index = -1;
1597 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1598 txtid->baw_head = txtid->baw_tail = 0;
1600 ath_txq_unlock_complete(sc, txq);
1605 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1607 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1608 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1609 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1610 struct ath_txq *txq = txtid->txq;
1612 ath_dbg(common, XMIT, "%s called\n", __func__);
1614 ath_txq_lock(sc, txq);
1615 txtid->active = false;
1616 ath_tx_flush_tid(sc, txtid);
1617 ath_txq_unlock_complete(sc, txq);
1620 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1621 struct ath_node *an)
1623 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1624 struct ath_atx_tid *tid;
1625 struct ath_txq *txq;
1628 ath_dbg(common, XMIT, "%s called\n", __func__);
1630 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) {
1631 tid = ath_node_to_tid(an, tidno);
1634 ath_txq_lock(sc, txq);
1636 if (list_empty(&tid->list)) {
1637 ath_txq_unlock(sc, txq);
1641 if (!skb_queue_empty(&tid->retry_q))
1642 ieee80211_sta_set_buffered(sta, tid->tidno, true);
1644 list_del_init(&tid->list);
1646 ath_txq_unlock(sc, txq);
1650 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1652 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1653 struct ath_atx_tid *tid;
1654 struct ath_txq *txq;
1657 ath_dbg(common, XMIT, "%s called\n", __func__);
1659 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) {
1660 tid = ath_node_to_tid(an, tidno);
1663 ath_txq_lock(sc, txq);
1664 tid->clear_ps_filter = true;
1665 if (ath_tid_has_buffered(tid)) {
1666 ath_tx_queue_tid(sc, tid);
1667 ath_txq_schedule(sc, txq);
1669 ath_txq_unlock_complete(sc, txq);
1675 ath9k_set_moredata(struct ath_softc *sc, struct ath_buf *bf, bool val)
1677 struct ieee80211_hdr *hdr;
1678 u16 mask = cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1679 u16 mask_val = mask * val;
1681 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
1682 if ((hdr->frame_control & mask) != mask_val) {
1683 hdr->frame_control = (hdr->frame_control & ~mask) | mask_val;
1684 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
1685 sizeof(*hdr), DMA_TO_DEVICE);
1689 void ath9k_release_buffered_frames(struct ieee80211_hw *hw,
1690 struct ieee80211_sta *sta,
1691 u16 tids, int nframes,
1692 enum ieee80211_frame_release_type reason,
1695 struct ath_softc *sc = hw->priv;
1696 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1697 struct ath_txq *txq = sc->tx.uapsdq;
1698 struct ieee80211_tx_info *info;
1699 struct list_head bf_q;
1700 struct ath_buf *bf_tail = NULL, *bf;
1704 INIT_LIST_HEAD(&bf_q);
1705 for (i = 0; tids && nframes; i++, tids >>= 1) {
1706 struct ath_atx_tid *tid;
1711 tid = ATH_AN_2_TID(an, i);
1713 ath_txq_lock(sc, tid->txq);
1714 while (nframes > 0) {
1715 bf = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq, tid);
1719 ath9k_set_moredata(sc, bf, true);
1720 list_add_tail(&bf->list, &bf_q);
1721 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1723 bf->bf_state.bf_type &= ~BUF_AGGR;
1725 bf_tail->bf_next = bf;
1730 TX_STAT_INC(sc, txq->axq_qnum, a_queued_hw);
1732 if (an->sta && skb_queue_empty(&tid->retry_q))
1733 ieee80211_sta_set_buffered(an->sta, i, false);
1735 ath_txq_unlock_complete(sc, tid->txq);
1738 if (list_empty(&bf_q))
1742 ath9k_set_moredata(sc, bf_tail, false);
1744 info = IEEE80211_SKB_CB(bf_tail->bf_mpdu);
1745 info->flags |= IEEE80211_TX_STATUS_EOSP;
1747 bf = list_first_entry(&bf_q, struct ath_buf, list);
1748 ath_txq_lock(sc, txq);
1749 ath_tx_fill_desc(sc, bf, txq, 0);
1750 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1751 ath_txq_unlock(sc, txq);
1754 /********************/
1755 /* Queue Management */
1756 /********************/
1758 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1760 struct ath_hw *ah = sc->sc_ah;
1761 struct ath9k_tx_queue_info qi;
1762 static const int subtype_txq_to_hwq[] = {
1763 [IEEE80211_AC_BE] = ATH_TXQ_AC_BE,
1764 [IEEE80211_AC_BK] = ATH_TXQ_AC_BK,
1765 [IEEE80211_AC_VI] = ATH_TXQ_AC_VI,
1766 [IEEE80211_AC_VO] = ATH_TXQ_AC_VO,
1770 memset(&qi, 0, sizeof(qi));
1771 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1772 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1773 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1774 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1775 qi.tqi_physCompBuf = 0;
1778 * Enable interrupts only for EOL and DESC conditions.
1779 * We mark tx descriptors to receive a DESC interrupt
1780 * when a tx queue gets deep; otherwise waiting for the
1781 * EOL to reap descriptors. Note that this is done to
1782 * reduce interrupt load and this only defers reaping
1783 * descriptors, never transmitting frames. Aside from
1784 * reducing interrupts this also permits more concurrency.
1785 * The only potential downside is if the tx queue backs
1786 * up in which case the top half of the kernel may backup
1787 * due to a lack of tx descriptors.
1789 * The UAPSD queue is an exception, since we take a desc-
1790 * based intr on the EOSP frames.
1792 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1793 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
1795 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1796 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1798 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1799 TXQ_FLAG_TXDESCINT_ENABLE;
1801 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1802 if (axq_qnum == -1) {
1804 * NB: don't print a message, this happens
1805 * normally on parts with too few tx queues
1809 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1810 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1812 txq->axq_qnum = axq_qnum;
1813 txq->mac80211_qnum = -1;
1814 txq->axq_link = NULL;
1815 __skb_queue_head_init(&txq->complete_q);
1816 INIT_LIST_HEAD(&txq->axq_q);
1817 spin_lock_init(&txq->axq_lock);
1819 txq->axq_ampdu_depth = 0;
1820 txq->axq_tx_inprogress = false;
1821 sc->tx.txqsetup |= 1<<axq_qnum;
1823 txq->txq_headidx = txq->txq_tailidx = 0;
1824 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1825 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1827 return &sc->tx.txq[axq_qnum];
1830 int ath_txq_update(struct ath_softc *sc, int qnum,
1831 struct ath9k_tx_queue_info *qinfo)
1833 struct ath_hw *ah = sc->sc_ah;
1835 struct ath9k_tx_queue_info qi;
1837 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1839 ath9k_hw_get_txq_props(ah, qnum, &qi);
1840 qi.tqi_aifs = qinfo->tqi_aifs;
1841 qi.tqi_cwmin = qinfo->tqi_cwmin;
1842 qi.tqi_cwmax = qinfo->tqi_cwmax;
1843 qi.tqi_burstTime = qinfo->tqi_burstTime;
1844 qi.tqi_readyTime = qinfo->tqi_readyTime;
1846 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1847 ath_err(ath9k_hw_common(sc->sc_ah),
1848 "Unable to update hardware queue %u!\n", qnum);
1851 ath9k_hw_resettxqueue(ah, qnum);
1857 int ath_cabq_update(struct ath_softc *sc)
1859 struct ath9k_tx_queue_info qi;
1860 struct ath_beacon_config *cur_conf = &sc->cur_chan->beacon;
1861 int qnum = sc->beacon.cabq->axq_qnum;
1863 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1865 qi.tqi_readyTime = (TU_TO_USEC(cur_conf->beacon_interval) *
1866 ATH_CABQ_READY_TIME) / 100;
1867 ath_txq_update(sc, qnum, &qi);
1872 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1873 struct list_head *list)
1875 struct ath_buf *bf, *lastbf;
1876 struct list_head bf_head;
1877 struct ath_tx_status ts;
1879 memset(&ts, 0, sizeof(ts));
1880 ts.ts_status = ATH9K_TX_FLUSH;
1881 INIT_LIST_HEAD(&bf_head);
1883 while (!list_empty(list)) {
1884 bf = list_first_entry(list, struct ath_buf, list);
1886 if (bf->bf_state.stale) {
1887 list_del(&bf->list);
1889 ath_tx_return_buffer(sc, bf);
1893 lastbf = bf->bf_lastbf;
1894 list_cut_position(&bf_head, list, &lastbf->list);
1895 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
1900 * Drain a given TX queue (could be Beacon or Data)
1902 * This assumes output has been stopped and
1903 * we do not need to block ath_tx_tasklet.
1905 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq)
1908 ath_txq_lock(sc, txq);
1910 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1911 int idx = txq->txq_tailidx;
1913 while (!list_empty(&txq->txq_fifo[idx])) {
1914 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]);
1916 INCR(idx, ATH_TXFIFO_DEPTH);
1918 txq->txq_tailidx = idx;
1921 txq->axq_link = NULL;
1922 txq->axq_tx_inprogress = false;
1923 ath_drain_txq_list(sc, txq, &txq->axq_q);
1925 ath_txq_unlock_complete(sc, txq);
1929 bool ath_drain_all_txq(struct ath_softc *sc)
1931 struct ath_hw *ah = sc->sc_ah;
1932 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1933 struct ath_txq *txq;
1937 if (test_bit(ATH_OP_INVALID, &common->op_flags))
1940 ath9k_hw_abort_tx_dma(ah);
1942 /* Check if any queue remains active */
1943 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1944 if (!ATH_TXQ_SETUP(sc, i))
1947 if (!sc->tx.txq[i].axq_depth)
1950 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1955 RESET_STAT_INC(sc, RESET_TX_DMA_ERROR);
1956 ath_dbg(common, RESET,
1957 "Failed to stop TX DMA, queues=0x%03x!\n", npend);
1960 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1961 if (!ATH_TXQ_SETUP(sc, i))
1964 txq = &sc->tx.txq[i];
1965 ath_draintxq(sc, txq);
1971 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1973 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1974 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1977 /* For each acq entry, for each tid, try to schedule packets
1978 * for transmit until ampdu_depth has reached min Q depth.
1980 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1982 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1983 struct ath_atx_tid *tid;
1984 struct list_head *tid_list;
1985 struct ath_acq *acq;
1986 bool active = AIRTIME_ACTIVE(sc->airtime_flags);
1988 if (txq->mac80211_qnum < 0)
1991 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
1994 spin_lock_bh(&sc->chan_lock);
1996 acq = &sc->cur_chan->acq[txq->mac80211_qnum];
1998 if (sc->cur_chan->stopped)
2002 tid_list = &acq->acq_new;
2003 if (list_empty(tid_list)) {
2004 tid_list = &acq->acq_old;
2005 if (list_empty(tid_list))
2008 tid = list_first_entry(tid_list, struct ath_atx_tid, list);
2010 if (active && tid->an->airtime_deficit[txq->mac80211_qnum] <= 0) {
2011 spin_lock_bh(&acq->lock);
2012 tid->an->airtime_deficit[txq->mac80211_qnum] += ATH_AIRTIME_QUANTUM;
2013 list_move_tail(&tid->list, &acq->acq_old);
2014 spin_unlock_bh(&acq->lock);
2018 if (!ath_tid_has_buffered(tid)) {
2019 spin_lock_bh(&acq->lock);
2020 if ((tid_list == &acq->acq_new) && !list_empty(&acq->acq_old))
2021 list_move_tail(&tid->list, &acq->acq_old);
2023 list_del_init(&tid->list);
2025 spin_unlock_bh(&acq->lock);
2031 * If we succeed in scheduling something, immediately restart to make
2032 * sure we keep the HW busy.
2034 if(ath_tx_sched_aggr(sc, txq, tid)) {
2036 spin_lock_bh(&acq->lock);
2037 list_move_tail(&tid->list, &acq->acq_old);
2038 spin_unlock_bh(&acq->lock);
2045 spin_unlock_bh(&sc->chan_lock);
2048 void ath_txq_schedule_all(struct ath_softc *sc)
2050 struct ath_txq *txq;
2053 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
2054 txq = sc->tx.txq_map[i];
2056 spin_lock_bh(&txq->axq_lock);
2057 ath_txq_schedule(sc, txq);
2058 spin_unlock_bh(&txq->axq_lock);
2067 * Insert a chain of ath_buf (descriptors) on a txq and
2068 * assume the descriptors are already chained together by caller.
2070 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
2071 struct list_head *head, bool internal)
2073 struct ath_hw *ah = sc->sc_ah;
2074 struct ath_common *common = ath9k_hw_common(ah);
2075 struct ath_buf *bf, *bf_last;
2076 bool puttxbuf = false;
2080 * Insert the frame on the outbound list and
2081 * pass it on to the hardware.
2084 if (list_empty(head))
2087 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
2088 bf = list_first_entry(head, struct ath_buf, list);
2089 bf_last = list_entry(head->prev, struct ath_buf, list);
2091 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n",
2092 txq->axq_qnum, txq->axq_depth);
2094 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
2095 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
2096 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
2099 list_splice_tail_init(head, &txq->axq_q);
2101 if (txq->axq_link) {
2102 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
2103 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n",
2104 txq->axq_qnum, txq->axq_link,
2105 ito64(bf->bf_daddr), bf->bf_desc);
2109 txq->axq_link = bf_last->bf_desc;
2113 TX_STAT_INC(sc, txq->axq_qnum, puttxbuf);
2114 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
2115 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n",
2116 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
2119 if (!edma || sc->tx99_state) {
2120 TX_STAT_INC(sc, txq->axq_qnum, txstart);
2121 ath9k_hw_txstart(ah, txq->axq_qnum);
2127 if (bf_is_ampdu_not_probing(bf))
2128 txq->axq_ampdu_depth++;
2130 bf_last = bf->bf_lastbf;
2131 bf = bf_last->bf_next;
2132 bf_last->bf_next = NULL;
2137 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
2138 struct ath_atx_tid *tid, struct sk_buff *skb)
2140 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2141 struct ath_frame_info *fi = get_frame_info(skb);
2142 struct list_head bf_head;
2143 struct ath_buf *bf = fi->bf;
2145 INIT_LIST_HEAD(&bf_head);
2146 list_add_tail(&bf->list, &bf_head);
2147 bf->bf_state.bf_type = 0;
2148 if (tid && (tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
2149 bf->bf_state.bf_type = BUF_AMPDU;
2150 ath_tx_addto_baw(sc, tid, bf);
2155 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
2156 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
2157 TX_STAT_INC(sc, txq->axq_qnum, queued);
2160 static void setup_frame_info(struct ieee80211_hw *hw,
2161 struct ieee80211_sta *sta,
2162 struct sk_buff *skb,
2165 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2166 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
2167 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2168 const struct ieee80211_rate *rate;
2169 struct ath_frame_info *fi = get_frame_info(skb);
2170 struct ath_node *an = NULL;
2171 enum ath9k_key_type keytype;
2172 bool short_preamble = false;
2176 * We check if Short Preamble is needed for the CTS rate by
2177 * checking the BSS's global flag.
2178 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
2180 if (tx_info->control.vif &&
2181 tx_info->control.vif->bss_conf.use_short_preamble)
2182 short_preamble = true;
2184 rate = ieee80211_get_rts_cts_rate(hw, tx_info);
2185 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
2188 an = (struct ath_node *) sta->drv_priv;
2190 if (tx_info->control.vif) {
2191 struct ieee80211_vif *vif = tx_info->control.vif;
2193 txpower = 2 * vif->bss_conf.txpower;
2195 struct ath_softc *sc = hw->priv;
2197 txpower = sc->cur_chan->cur_txpower;
2200 memset(fi, 0, sizeof(*fi));
2203 fi->keyix = hw_key->hw_key_idx;
2204 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
2205 fi->keyix = an->ps_key;
2207 fi->keyix = ATH9K_TXKEYIX_INVALID;
2208 fi->keytype = keytype;
2209 fi->framelen = framelen;
2210 fi->tx_power = txpower;
2214 fi->rtscts_rate = rate->hw_value;
2216 fi->rtscts_rate |= rate->hw_value_short;
2219 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
2221 struct ath_hw *ah = sc->sc_ah;
2222 struct ath9k_channel *curchan = ah->curchan;
2224 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && IS_CHAN_5GHZ(curchan) &&
2225 (chainmask == 0x7) && (rate < 0x90))
2227 else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) &&
2235 * Assign a descriptor (and sequence number if necessary,
2236 * and map buffer for DMA. Frees skb on error
2238 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
2239 struct ath_txq *txq,
2240 struct ath_atx_tid *tid,
2241 struct sk_buff *skb)
2243 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2244 struct ath_frame_info *fi = get_frame_info(skb);
2245 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2250 bf = ath_tx_get_buffer(sc);
2252 ath_dbg(common, XMIT, "TX buffers are full\n");
2256 ATH_TXBUF_RESET(bf);
2258 if (tid && ieee80211_is_data_present(hdr->frame_control)) {
2259 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
2260 seqno = tid->seq_next;
2261 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
2264 hdr->seq_ctrl |= cpu_to_le16(fragno);
2266 if (!ieee80211_has_morefrags(hdr->frame_control))
2267 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
2269 bf->bf_state.seqno = seqno;
2274 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
2275 skb->len, DMA_TO_DEVICE);
2276 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
2278 bf->bf_buf_addr = 0;
2279 ath_err(ath9k_hw_common(sc->sc_ah),
2280 "dma_mapping_error() on TX\n");
2281 ath_tx_return_buffer(sc, bf);
2290 void ath_assign_seq(struct ath_common *common, struct sk_buff *skb)
2292 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2293 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2294 struct ieee80211_vif *vif = info->control.vif;
2295 struct ath_vif *avp;
2297 if (!(info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ))
2303 avp = (struct ath_vif *)vif->drv_priv;
2305 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2306 avp->seq_no += 0x10;
2308 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2309 hdr->seq_ctrl |= cpu_to_le16(avp->seq_no);
2312 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
2313 struct ath_tx_control *txctl)
2315 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2316 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2317 struct ieee80211_sta *sta = txctl->sta;
2318 struct ieee80211_vif *vif = info->control.vif;
2319 struct ath_vif *avp;
2320 struct ath_softc *sc = hw->priv;
2321 int frmlen = skb->len + FCS_LEN;
2322 int padpos, padsize;
2324 /* NOTE: sta can be NULL according to net/mac80211.h */
2326 txctl->an = (struct ath_node *)sta->drv_priv;
2327 else if (vif && ieee80211_is_data(hdr->frame_control)) {
2328 avp = (void *)vif->drv_priv;
2329 txctl->an = &avp->mcast_node;
2332 if (info->control.hw_key)
2333 frmlen += info->control.hw_key->icv_len;
2335 ath_assign_seq(ath9k_hw_common(sc->sc_ah), skb);
2337 if ((vif && vif->type != NL80211_IFTYPE_AP &&
2338 vif->type != NL80211_IFTYPE_AP_VLAN) ||
2339 !ieee80211_is_data(hdr->frame_control))
2340 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
2342 /* Add the padding after the header if this is not already done */
2343 padpos = ieee80211_hdrlen(hdr->frame_control);
2344 padsize = padpos & 3;
2345 if (padsize && skb->len > padpos) {
2346 if (skb_headroom(skb) < padsize)
2349 skb_push(skb, padsize);
2350 memmove(skb->data, skb->data + padsize, padpos);
2353 setup_frame_info(hw, sta, skb, frmlen);
2358 /* Upon failure caller should free skb */
2359 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
2360 struct ath_tx_control *txctl)
2362 struct ieee80211_hdr *hdr;
2363 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2364 struct ieee80211_sta *sta = txctl->sta;
2365 struct ieee80211_vif *vif = info->control.vif;
2366 struct ath_frame_info *fi = get_frame_info(skb);
2367 struct ath_vif *avp = NULL;
2368 struct ath_softc *sc = hw->priv;
2369 struct ath_txq *txq = txctl->txq;
2370 struct ath_atx_tid *tid = NULL;
2371 struct ath_node *an = NULL;
2377 avp = (void *)vif->drv_priv;
2379 ps_resp = !!(info->control.flags & IEEE80211_TX_CTRL_PS_RESPONSE);
2381 ret = ath_tx_prepare(hw, skb, txctl);
2385 hdr = (struct ieee80211_hdr *) skb->data;
2387 * At this point, the vif, hw_key and sta pointers in the tx control
2388 * info are no longer valid (overwritten by the ath_frame_info data.
2391 q = skb_get_queue_mapping(skb);
2394 txq = sc->tx.uapsdq;
2397 an = (struct ath_node *) sta->drv_priv;
2398 tid = ath_get_skb_tid(sc, an, skb);
2401 ath_txq_lock(sc, txq);
2402 if (txq == sc->tx.txq_map[q]) {
2404 ++txq->pending_frames;
2407 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
2409 ath_txq_skb_done(sc, txq, skb);
2411 dev_kfree_skb_any(skb);
2413 ieee80211_free_txskb(sc->hw, skb);
2417 bf->bf_state.bfs_paprd = txctl->paprd;
2420 bf->bf_state.bfs_paprd_timestamp = jiffies;
2422 ath_set_rates(vif, sta, bf);
2423 ath_tx_send_normal(sc, txq, tid, skb);
2426 ath_txq_unlock(sc, txq);
2431 void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2432 struct sk_buff *skb)
2434 struct ath_softc *sc = hw->priv;
2435 struct ath_tx_control txctl = {
2436 .txq = sc->beacon.cabq
2438 struct ath_tx_info info = {};
2439 struct ath_buf *bf_tail = NULL;
2446 sc->cur_chan->beacon.beacon_interval * 1000 *
2447 sc->cur_chan->beacon.dtim_period / ATH_BCBUF;
2450 struct ath_frame_info *fi = get_frame_info(skb);
2452 if (ath_tx_prepare(hw, skb, &txctl))
2455 bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb);
2460 ath_set_rates(vif, NULL, bf);
2461 ath_buf_set_rate(sc, bf, &info, fi->framelen, false);
2462 duration += info.rates[0].PktDuration;
2464 bf_tail->bf_next = bf;
2466 list_add_tail(&bf->list, &bf_q);
2470 if (duration > max_duration)
2473 skb = ieee80211_get_buffered_bc(hw, vif);
2477 ieee80211_free_txskb(hw, skb);
2479 if (list_empty(&bf_q))
2482 bf = list_last_entry(&bf_q, struct ath_buf, list);
2483 ath9k_set_moredata(sc, bf, false);
2485 bf = list_first_entry(&bf_q, struct ath_buf, list);
2486 ath_txq_lock(sc, txctl.txq);
2487 ath_tx_fill_desc(sc, bf, txctl.txq, 0);
2488 ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false);
2489 TX_STAT_INC(sc, txctl.txq->axq_qnum, queued);
2490 ath_txq_unlock(sc, txctl.txq);
2497 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
2498 int tx_flags, struct ath_txq *txq,
2499 struct ieee80211_sta *sta)
2501 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2502 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2503 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
2504 int padpos, padsize;
2505 unsigned long flags;
2507 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
2509 if (sc->sc_ah->caldata)
2510 set_bit(PAPRD_PACKET_SENT, &sc->sc_ah->caldata->cal_flags);
2512 if (!(tx_flags & ATH_TX_ERROR)) {
2513 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
2514 tx_info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED;
2516 tx_info->flags |= IEEE80211_TX_STAT_ACK;
2519 if (tx_info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS) {
2520 padpos = ieee80211_hdrlen(hdr->frame_control);
2521 padsize = padpos & 3;
2522 if (padsize && skb->len>padpos+padsize) {
2524 * Remove MAC header padding before giving the frame back to
2527 memmove(skb->data + padsize, skb->data, padpos);
2528 skb_pull(skb, padsize);
2532 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2533 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
2534 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
2536 "Going back to sleep after having received TX status (0x%lx)\n",
2537 sc->ps_flags & (PS_WAIT_FOR_BEACON |
2539 PS_WAIT_FOR_PSPOLL_DATA |
2540 PS_WAIT_FOR_TX_ACK));
2542 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2544 ath_txq_skb_done(sc, txq, skb);
2545 tx_info->status.status_driver_data[0] = sta;
2546 __skb_queue_tail(&txq->complete_q, skb);
2549 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
2550 struct ath_txq *txq, struct list_head *bf_q,
2551 struct ieee80211_sta *sta,
2552 struct ath_tx_status *ts, int txok)
2554 struct sk_buff *skb = bf->bf_mpdu;
2555 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2556 unsigned long flags;
2560 tx_flags |= ATH_TX_ERROR;
2562 if (ts->ts_status & ATH9K_TXERR_FILT)
2563 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2565 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2566 bf->bf_buf_addr = 0;
2568 goto skip_tx_complete;
2570 if (bf->bf_state.bfs_paprd) {
2571 if (time_after(jiffies,
2572 bf->bf_state.bfs_paprd_timestamp +
2573 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2574 dev_kfree_skb_any(skb);
2576 complete(&sc->paprd_complete);
2578 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2579 ath_tx_complete(sc, skb, tx_flags, txq, sta);
2582 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2583 * accidentally reference it later.
2588 * Return the list of ath_buf of this mpdu to free queue
2590 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2591 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2592 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2595 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2596 struct ath_tx_status *ts, int nframes, int nbad,
2599 struct sk_buff *skb = bf->bf_mpdu;
2600 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2601 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2602 struct ieee80211_hw *hw = sc->hw;
2603 struct ath_hw *ah = sc->sc_ah;
2607 tx_info->status.ack_signal = ts->ts_rssi;
2609 tx_rateindex = ts->ts_rateindex;
2610 WARN_ON(tx_rateindex >= hw->max_rates);
2612 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2613 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2615 BUG_ON(nbad > nframes);
2617 tx_info->status.ampdu_len = nframes;
2618 tx_info->status.ampdu_ack_len = nframes - nbad;
2620 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2621 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2623 * If an underrun error is seen assume it as an excessive
2624 * retry only if max frame trigger level has been reached
2625 * (2 KB for single stream, and 4 KB for dual stream).
2626 * Adjust the long retry as if the frame was tried
2627 * hw->max_rate_tries times to affect how rate control updates
2628 * PER for the failed rate.
2629 * In case of congestion on the bus penalizing this type of
2630 * underruns should help hardware actually transmit new frames
2631 * successfully by eventually preferring slower rates.
2632 * This itself should also alleviate congestion on the bus.
2634 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2635 ATH9K_TX_DELIM_UNDERRUN)) &&
2636 ieee80211_is_data(hdr->frame_control) &&
2637 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2638 tx_info->status.rates[tx_rateindex].count =
2642 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2643 tx_info->status.rates[i].count = 0;
2644 tx_info->status.rates[i].idx = -1;
2647 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2650 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2652 struct ath_hw *ah = sc->sc_ah;
2653 struct ath_common *common = ath9k_hw_common(ah);
2654 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2655 struct list_head bf_head;
2656 struct ath_desc *ds;
2657 struct ath_tx_status ts;
2660 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n",
2661 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2664 ath_txq_lock(sc, txq);
2666 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
2669 if (list_empty(&txq->axq_q)) {
2670 txq->axq_link = NULL;
2671 ath_txq_schedule(sc, txq);
2674 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2677 * There is a race condition that a BH gets scheduled
2678 * after sw writes TxE and before hw re-load the last
2679 * descriptor to get the newly chained one.
2680 * Software must keep the last DONE descriptor as a
2681 * holding descriptor - software does so by marking
2682 * it with the STALE flag.
2685 if (bf->bf_state.stale) {
2687 if (list_is_last(&bf_held->list, &txq->axq_q))
2690 bf = list_entry(bf_held->list.next, struct ath_buf,
2694 lastbf = bf->bf_lastbf;
2695 ds = lastbf->bf_desc;
2697 memset(&ts, 0, sizeof(ts));
2698 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2699 if (status == -EINPROGRESS)
2702 TX_STAT_INC(sc, txq->axq_qnum, txprocdesc);
2705 * Remove ath_buf's of the same transmit unit from txq,
2706 * however leave the last descriptor back as the holding
2707 * descriptor for hw.
2709 lastbf->bf_state.stale = true;
2710 INIT_LIST_HEAD(&bf_head);
2711 if (!list_is_singular(&lastbf->list))
2712 list_cut_position(&bf_head,
2713 &txq->axq_q, lastbf->list.prev);
2716 list_del(&bf_held->list);
2717 ath_tx_return_buffer(sc, bf_held);
2720 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2722 ath_txq_unlock_complete(sc, txq);
2725 void ath_tx_tasklet(struct ath_softc *sc)
2727 struct ath_hw *ah = sc->sc_ah;
2728 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs;
2732 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2733 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2734 ath_tx_processq(sc, &sc->tx.txq[i]);
2739 void ath_tx_edma_tasklet(struct ath_softc *sc)
2741 struct ath_tx_status ts;
2742 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2743 struct ath_hw *ah = sc->sc_ah;
2744 struct ath_txq *txq;
2745 struct ath_buf *bf, *lastbf;
2746 struct list_head bf_head;
2747 struct list_head *fifo_list;
2752 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
2755 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2756 if (status == -EINPROGRESS)
2758 if (status == -EIO) {
2759 ath_dbg(common, XMIT, "Error processing tx status\n");
2763 /* Process beacon completions separately */
2764 if (ts.qid == sc->beacon.beaconq) {
2765 sc->beacon.tx_processed = true;
2766 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2768 if (ath9k_is_chanctx_enabled()) {
2769 ath_chanctx_event(sc, NULL,
2770 ATH_CHANCTX_EVENT_BEACON_SENT);
2773 ath9k_csa_update(sc);
2777 txq = &sc->tx.txq[ts.qid];
2779 ath_txq_lock(sc, txq);
2781 TX_STAT_INC(sc, txq->axq_qnum, txprocdesc);
2783 fifo_list = &txq->txq_fifo[txq->txq_tailidx];
2784 if (list_empty(fifo_list)) {
2785 ath_txq_unlock(sc, txq);
2789 bf = list_first_entry(fifo_list, struct ath_buf, list);
2790 if (bf->bf_state.stale) {
2791 list_del(&bf->list);
2792 ath_tx_return_buffer(sc, bf);
2793 bf = list_first_entry(fifo_list, struct ath_buf, list);
2796 lastbf = bf->bf_lastbf;
2798 INIT_LIST_HEAD(&bf_head);
2799 if (list_is_last(&lastbf->list, fifo_list)) {
2800 list_splice_tail_init(fifo_list, &bf_head);
2801 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2803 if (!list_empty(&txq->axq_q)) {
2804 struct list_head bf_q;
2806 INIT_LIST_HEAD(&bf_q);
2807 txq->axq_link = NULL;
2808 list_splice_tail_init(&txq->axq_q, &bf_q);
2809 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2812 lastbf->bf_state.stale = true;
2814 list_cut_position(&bf_head, fifo_list,
2818 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2819 ath_txq_unlock_complete(sc, txq);
2828 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2830 struct ath_descdma *dd = &sc->txsdma;
2831 u8 txs_len = sc->sc_ah->caps.txs_len;
2833 dd->dd_desc_len = size * txs_len;
2834 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
2835 &dd->dd_desc_paddr, GFP_KERNEL);
2842 static int ath_tx_edma_init(struct ath_softc *sc)
2846 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2848 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2849 sc->txsdma.dd_desc_paddr,
2850 ATH_TXSTATUS_RING_SIZE);
2855 int ath_tx_init(struct ath_softc *sc, int nbufs)
2857 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2860 spin_lock_init(&sc->tx.txbuflock);
2862 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2866 "Failed to allocate tx descriptors: %d\n", error);
2870 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2871 "beacon", ATH_BCBUF, 1, 1);
2874 "Failed to allocate beacon descriptors: %d\n", error);
2878 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2879 error = ath_tx_edma_init(sc);
2884 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2886 struct ath_atx_tid *tid;
2889 for (acno = 0; acno < IEEE80211_NUM_ACS; acno++)
2890 an->airtime_deficit[acno] = ATH_AIRTIME_QUANTUM;
2892 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) {
2893 tid = ath_node_to_tid(an, tidno);
2896 tid->seq_start = tid->seq_next = 0;
2897 tid->baw_size = WME_MAX_BA;
2898 tid->baw_head = tid->baw_tail = 0;
2899 tid->active = false;
2900 tid->clear_ps_filter = true;
2901 tid->has_queued = false;
2902 __skb_queue_head_init(&tid->retry_q);
2903 INIT_LIST_HEAD(&tid->list);
2904 acno = TID_TO_WME_AC(tidno);
2905 tid->txq = sc->tx.txq_map[acno];
2908 break; /* just one multicast ath_atx_tid */
2912 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2914 struct ath_atx_tid *tid;
2915 struct ath_txq *txq;
2920 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) {
2921 tid = ath_node_to_tid(an, tidno);
2924 ath_txq_lock(sc, txq);
2926 if (!list_empty(&tid->list))
2927 list_del_init(&tid->list);
2929 ath_tid_drain(sc, txq, tid);
2930 tid->active = false;
2932 ath_txq_unlock(sc, txq);
2935 break; /* just one multicast ath_atx_tid */
2941 #ifdef CONFIG_ATH9K_TX99
2943 int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
2944 struct ath_tx_control *txctl)
2946 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2947 struct ath_frame_info *fi = get_frame_info(skb);
2948 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2950 int padpos, padsize;
2952 padpos = ieee80211_hdrlen(hdr->frame_control);
2953 padsize = padpos & 3;
2955 if (padsize && skb->len > padpos) {
2956 if (skb_headroom(skb) < padsize) {
2957 ath_dbg(common, XMIT,
2958 "tx99 padding failed\n");
2962 skb_push(skb, padsize);
2963 memmove(skb->data, skb->data + padsize, padpos);
2966 fi->keyix = ATH9K_TXKEYIX_INVALID;
2967 fi->framelen = skb->len + FCS_LEN;
2968 fi->keytype = ATH9K_KEY_TYPE_CLEAR;
2970 bf = ath_tx_setup_buffer(sc, txctl->txq, NULL, skb);
2972 ath_dbg(common, XMIT, "tx99 buffer setup failed\n");
2976 ath_set_rates(sc->tx99_vif, NULL, bf);
2978 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, bf->bf_daddr);
2979 ath9k_hw_tx99_start(sc->sc_ah, txctl->txq->axq_qnum);
2981 ath_tx_send_normal(sc, txctl->txq, NULL, skb);
2986 #endif /* CONFIG_ATH9K_TX99 */