drivers/net/wireless/ath/ath9k/recv.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "ath9k.h"
  18 #include "ar9003_mac.h"
  19
  20 #define SKB_CB_ATHBUF(__skb)    (*((struct ath_buf **)__skb->cb))
  21
  22 static inline bool ath9k_check_auto_sleep(struct ath_softc *sc)
  23 {
  24         return sc->ps_enabled &&
  25                (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP);
  26 }
  27
  28 static struct ieee80211_hw * ath_get_virt_hw(struct ath_softc *sc,
  29                                              struct ieee80211_hdr *hdr)
  30 {
  31         struct ieee80211_hw *hw = sc->pri_wiphy->hw;
  32         int i;
  33
  34         spin_lock_bh(&sc->wiphy_lock);
  35         for (i = 0; i < sc->num_sec_wiphy; i++) {
  36                 struct ath_wiphy *aphy = sc->sec_wiphy[i];
  37                 if (aphy == NULL)
  38                         continue;
  39                 if (compare_ether_addr(hdr->addr1, aphy->hw->wiphy->perm_addr)
  40                     == 0) {
  41                         hw = aphy->hw;
  42                         break;
  43                 }
  44         }
  45         spin_unlock_bh(&sc->wiphy_lock);
  46         return hw;
  47 }
  48
  49 /*
  50  * Setup and link descriptors.
  51  *
  52  * 11N: we can no longer afford to self link the last descriptor.
  53  * MAC acknowledges BA status as long as it copies frames to host
  54  * buffer (or rx fifo). This can incorrectly acknowledge packets
  55  * to a sender if last desc is self-linked.
  56  */
  57 static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf)
  58 {
  59         struct ath_hw *ah = sc->sc_ah;
  60         struct ath_common *common = ath9k_hw_common(ah);
  61         struct ath_desc *ds;
  62         struct sk_buff *skb;
  63
  64         ATH_RXBUF_RESET(bf);
  65
  66         ds = bf->bf_desc;
  67         ds->ds_link = 0; /* link to null */
  68         ds->ds_data = bf->bf_buf_addr;
  69
  70         /* virtual addr of the beginning of the buffer. */
  71         skb = bf->bf_mpdu;
  72         BUG_ON(skb == NULL);
  73         ds->ds_vdata = skb->data;
  74
  75         /*
  76          * setup rx descriptors. The rx_bufsize here tells the hardware
  77          * how much data it can DMA to us and that we are prepared
  78          * to process
  79          */
  80         ath9k_hw_setuprxdesc(ah, ds,
  81                              common->rx_bufsize,
  82                              0);
  83
  84         if (sc->rx.rxlink == NULL)
  85                 ath9k_hw_putrxbuf(ah, bf->bf_daddr);
  86         else
  87                 *sc->rx.rxlink = bf->bf_daddr;
  88
  89         sc->rx.rxlink = &ds->ds_link;
  90         ath9k_hw_rxena(ah);
  91 }
  92
  93 static void ath_setdefantenna(struct ath_softc *sc, u32 antenna)
  94 {
  95         /* XXX block beacon interrupts */
  96         ath9k_hw_setantenna(sc->sc_ah, antenna);
  97         sc->rx.defant = antenna;
  98         sc->rx.rxotherant = 0;
  99 }
 100
 101 static void ath_opmode_init(struct ath_softc *sc)
 102 {
 103         struct ath_hw *ah = sc->sc_ah;
 104         struct ath_common *common = ath9k_hw_common(ah);
 105
 106         u32 rfilt, mfilt[2];
 107
 108         /* configure rx filter */
 109         rfilt = ath_calcrxfilter(sc);
 110         ath9k_hw_setrxfilter(ah, rfilt);
 111
 112         /* configure bssid mask */
 113         if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
 114                 ath_hw_setbssidmask(common);
 115
 116         /* configure operational mode */
 117         ath9k_hw_setopmode(ah);
 118
 119         /* Handle any link-level address change. */
 120         ath9k_hw_setmac(ah, common->macaddr);
 121
 122         /* calculate and install multicast filter */
 123         mfilt[0] = mfilt[1] = ~0;
 124         ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
 125 }
 126
 127 static bool ath_rx_edma_buf_link(struct ath_softc *sc,
 128                                  enum ath9k_rx_qtype qtype)
 129 {
 130         struct ath_hw *ah = sc->sc_ah;
 131         struct ath_rx_edma *rx_edma;
 132         struct sk_buff *skb;
 133         struct ath_buf *bf;
 134
 135         rx_edma = &sc->rx.rx_edma[qtype];
 136         if (skb_queue_len(&rx_edma->rx_fifo) >= rx_edma->rx_fifo_hwsize)
 137                 return false;
 138
 139         bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
 140         list_del_init(&bf->list);
 141
 142         skb = bf->bf_mpdu;
 143
 144         ATH_RXBUF_RESET(bf);
 145         memset(skb->data, 0, ah->caps.rx_status_len);
 146         dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
 147                                 ah->caps.rx_status_len, DMA_TO_DEVICE);
 148
 149         SKB_CB_ATHBUF(skb) = bf;
 150         ath9k_hw_addrxbuf_edma(ah, bf->bf_buf_addr, qtype);
 151         skb_queue_tail(&rx_edma->rx_fifo, skb);
 152
 153         return true;
 154 }
 155
 156 static void ath_rx_addbuffer_edma(struct ath_softc *sc,
 157                                   enum ath9k_rx_qtype qtype, int size)
 158 {
 159         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 160         u32 nbuf = 0;
 161
 162         if (list_empty(&sc->rx.rxbuf)) {
 163                 ath_print(common, ATH_DBG_QUEUE, "No free rx buf available\n");
 164                 return;
 165         }
 166
 167         while (!list_empty(&sc->rx.rxbuf)) {
 168                 nbuf++;
 169
 170                 if (!ath_rx_edma_buf_link(sc, qtype))
 171                         break;
 172
 173                 if (nbuf >= size)
 174                         break;
 175         }
 176 }
 177
 178 static void ath_rx_remove_buffer(struct ath_softc *sc,
 179                                  enum ath9k_rx_qtype qtype)
 180 {
 181         struct ath_buf *bf;
 182         struct ath_rx_edma *rx_edma;
 183         struct sk_buff *skb;
 184
 185         rx_edma = &sc->rx.rx_edma[qtype];
 186
 187         while ((skb = skb_dequeue(&rx_edma->rx_fifo)) != NULL) {
 188                 bf = SKB_CB_ATHBUF(skb);
 189                 BUG_ON(!bf);
 190                 list_add_tail(&bf->list, &sc->rx.rxbuf);
 191         }
 192 }
 193
 194 static void ath_rx_edma_cleanup(struct ath_softc *sc)
 195 {
 196         struct ath_buf *bf;
 197
 198         ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
 199         ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
 200
 201         list_for_each_entry(bf, &sc->rx.rxbuf, list) {
 202                 if (bf->bf_mpdu)
 203                         dev_kfree_skb_any(bf->bf_mpdu);
 204         }
 205
 206         INIT_LIST_HEAD(&sc->rx.rxbuf);
 207
 208         kfree(sc->rx.rx_bufptr);
 209         sc->rx.rx_bufptr = NULL;
 210 }
 211
 212 static void ath_rx_edma_init_queue(struct ath_rx_edma *rx_edma, int size)
 213 {
 214         skb_queue_head_init(&rx_edma->rx_fifo);
 215         skb_queue_head_init(&rx_edma->rx_buffers);
 216         rx_edma->rx_fifo_hwsize = size;
 217 }
 218
 219 static int ath_rx_edma_init(struct ath_softc *sc, int nbufs)
 220 {
 221         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 222         struct ath_hw *ah = sc->sc_ah;
 223         struct sk_buff *skb;
 224         struct ath_buf *bf;
 225         int error = 0, i;
 226         u32 size;
 227
 228
 229         common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN +
 230                                      ah->caps.rx_status_len,
 231                                      min(common->cachelsz, (u16)64));
 232
 233         ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
 234                                     ah->caps.rx_status_len);
 235
 236         ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_LP],
 237                                ah->caps.rx_lp_qdepth);
 238         ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_HP],
 239                                ah->caps.rx_hp_qdepth);
 240
 241         size = sizeof(struct ath_buf) * nbufs;
 242         bf = kzalloc(size, GFP_KERNEL);
 243         if (!bf)
 244                 return -ENOMEM;
 245
 246         INIT_LIST_HEAD(&sc->rx.rxbuf);
 247         sc->rx.rx_bufptr = bf;
 248
 249         for (i = 0; i < nbufs; i++, bf++) {
 250                 skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL);
 251                 if (!skb) {
 252                         error = -ENOMEM;
 253                         goto rx_init_fail;
 254                 }
 255
 256                 memset(skb->data, 0, common->rx_bufsize);
 257                 bf->bf_mpdu = skb;
 258
 259                 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
 260                                                  common->rx_bufsize,
 261                                                  DMA_BIDIRECTIONAL);
 262                 if (unlikely(dma_mapping_error(sc->dev,
 263                                                 bf->bf_buf_addr))) {
 264                                 dev_kfree_skb_any(skb);
 265                                 bf->bf_mpdu = NULL;
 266                                 ath_print(common, ATH_DBG_FATAL,
 267                                         "dma_mapping_error() on RX init\n");
 268                                 error = -ENOMEM;
 269                                 goto rx_init_fail;
 270                 }
 271
 272                 list_add_tail(&bf->list, &sc->rx.rxbuf);
 273         }
 274
 275         return 0;
 276
 277 rx_init_fail:
 278         ath_rx_edma_cleanup(sc);
 279         return error;
 280 }
 281
 282 static void ath_edma_start_recv(struct ath_softc *sc)
 283 {
 284         spin_lock_bh(&sc->rx.rxbuflock);
 285
 286         ath9k_hw_rxena(sc->sc_ah);
 287
 288         ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_HP,
 289                               sc->rx.rx_edma[ATH9K_RX_QUEUE_HP].rx_fifo_hwsize);
 290
 291         ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP,
 292                               sc->rx.rx_edma[ATH9K_RX_QUEUE_LP].rx_fifo_hwsize);
 293
 294         spin_unlock_bh(&sc->rx.rxbuflock);
 295
 296         ath_opmode_init(sc);
 297
 298         ath9k_hw_startpcureceive(sc->sc_ah);
 299 }
 300
 301 static void ath_edma_stop_recv(struct ath_softc *sc)
 302 {
 303         spin_lock_bh(&sc->rx.rxbuflock);
 304         ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
 305         ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
 306         spin_unlock_bh(&sc->rx.rxbuflock);
 307 }
 308
 309 int ath_rx_init(struct ath_softc *sc, int nbufs)
 310 {
 311         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 312         struct sk_buff *skb;
 313         struct ath_buf *bf;
 314         int error = 0;
 315
 316         spin_lock_init(&sc->rx.rxflushlock);
 317         sc->sc_flags &= ~SC_OP_RXFLUSH;
 318         spin_lock_init(&sc->rx.rxbuflock);
 319
 320         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
 321                 return ath_rx_edma_init(sc, nbufs);
 322         } else {
 323                 common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN,
 324                                 min(common->cachelsz, (u16)64));
 325
 326                 ath_print(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
 327                                 common->cachelsz, common->rx_bufsize);
 328
 329                 /* Initialize rx descriptors */
 330
 331                 error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
 332                                 "rx", nbufs, 1, 0);
 333                 if (error != 0) {
 334                         ath_print(common, ATH_DBG_FATAL,
 335                                   "failed to allocate rx descriptors: %d\n",
 336                                   error);
 337                         goto err;
 338                 }
 339
 340                 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
 341                         skb = ath_rxbuf_alloc(common, common->rx_bufsize,
 342                                               GFP_KERNEL);
 343                         if (skb == NULL) {
 344                                 error = -ENOMEM;
 345                                 goto err;
 346                         }
 347
 348                         bf->bf_mpdu = skb;
 349                         bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
 350                                         common->rx_bufsize,
 351                                         DMA_FROM_DEVICE);
 352                         if (unlikely(dma_mapping_error(sc->dev,
 353                                                         bf->bf_buf_addr))) {
 354                                 dev_kfree_skb_any(skb);
 355                                 bf->bf_mpdu = NULL;
 356                                 ath_print(common, ATH_DBG_FATAL,
 357                                           "dma_mapping_error() on RX init\n");
 358                                 error = -ENOMEM;
 359                                 goto err;
 360                         }
 361                         bf->bf_dmacontext = bf->bf_buf_addr;
 362                 }
 363                 sc->rx.rxlink = NULL;
 364         }
 365
 366 err:
 367         if (error)
 368                 ath_rx_cleanup(sc);
 369
 370         return error;
 371 }
 372
 373 void ath_rx_cleanup(struct ath_softc *sc)
 374 {
 375         struct ath_hw *ah = sc->sc_ah;
 376         struct ath_common *common = ath9k_hw_common(ah);
 377         struct sk_buff *skb;
 378         struct ath_buf *bf;
 379
 380         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
 381                 ath_rx_edma_cleanup(sc);
 382                 return;
 383         } else {
 384                 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
 385                         skb = bf->bf_mpdu;
 386                         if (skb) {
 387                                 dma_unmap_single(sc->dev, bf->bf_buf_addr,
 388                                                 common->rx_bufsize,
 389                                                 DMA_FROM_DEVICE);
 390                                 dev_kfree_skb(skb);
 391                         }
 392                 }
 393
 394                 if (sc->rx.rxdma.dd_desc_len != 0)
 395                         ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf);
 396         }
 397 }
 398
 399 /*
 400  * Calculate the receive filter according to the
 401  * operating mode and state:
 402  *
 403  * o always accept unicast, broadcast, and multicast traffic
 404  * o maintain current state of phy error reception (the hal
 405  *   may enable phy error frames for noise immunity work)
 406  * o probe request frames are accepted only when operating in
 407  *   hostap, adhoc, or monitor modes
 408  * o enable promiscuous mode according to the interface state
 409  * o accept beacons:
 410  *   - when operating in adhoc mode so the 802.11 layer creates
 411  *     node table entries for peers,
 412  *   - when operating in station mode for collecting rssi data when
 413  *     the station is otherwise quiet, or
 414  *   - when operating as a repeater so we see repeater-sta beacons
 415  *   - when scanning
 416  */
 417
 418 u32 ath_calcrxfilter(struct ath_softc *sc)
 419 {
 420 #define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR)
 421
 422         u32 rfilt;
 423
 424         rfilt = (ath9k_hw_getrxfilter(sc->sc_ah) & RX_FILTER_PRESERVE)
 425                 | ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST
 426                 | ATH9K_RX_FILTER_MCAST;
 427
 428         /* If not a STA, enable processing of Probe Requests */
 429         if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
 430                 rfilt |= ATH9K_RX_FILTER_PROBEREQ;
 431
 432         /*
 433          * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station
 434          * mode interface or when in monitor mode. AP mode does not need this
 435          * since it receives all in-BSS frames anyway.
 436          */
 437         if (((sc->sc_ah->opmode != NL80211_IFTYPE_AP) &&
 438              (sc->rx.rxfilter & FIF_PROMISC_IN_BSS)) ||
 439             (sc->sc_ah->opmode == NL80211_IFTYPE_MONITOR))
 440                 rfilt |= ATH9K_RX_FILTER_PROM;
 441
 442         if (sc->rx.rxfilter & FIF_CONTROL)
 443                 rfilt |= ATH9K_RX_FILTER_CONTROL;
 444
 445         if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
 446             !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC))
 447                 rfilt |= ATH9K_RX_FILTER_MYBEACON;
 448         else
 449                 rfilt |= ATH9K_RX_FILTER_BEACON;
 450
 451         if ((AR_SREV_9280_10_OR_LATER(sc->sc_ah) ||
 452             AR_SREV_9285_10_OR_LATER(sc->sc_ah)) &&
 453             (sc->sc_ah->opmode == NL80211_IFTYPE_AP) &&
 454             (sc->rx.rxfilter & FIF_PSPOLL))
 455                 rfilt |= ATH9K_RX_FILTER_PSPOLL;
 456
 457         if (conf_is_ht(&sc->hw->conf))
 458                 rfilt |= ATH9K_RX_FILTER_COMP_BAR;
 459
 460         if (sc->sec_wiphy || (sc->rx.rxfilter & FIF_OTHER_BSS)) {
 461                 /* TODO: only needed if more than one BSSID is in use in
 462                  * station/adhoc mode */
 463                 /* The following may also be needed for other older chips */
 464                 if (sc->sc_ah->hw_version.macVersion == AR_SREV_VERSION_9160)
 465                         rfilt |= ATH9K_RX_FILTER_PROM;
 466                 rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL;
 467         }
 468
 469         return rfilt;
 470
 471 #undef RX_FILTER_PRESERVE
 472 }
 473
 474 int ath_startrecv(struct ath_softc *sc)
 475 {
 476         struct ath_hw *ah = sc->sc_ah;
 477         struct ath_buf *bf, *tbf;
 478
 479         if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
 480                 ath_edma_start_recv(sc);
 481                 return 0;
 482         }
 483
 484         spin_lock_bh(&sc->rx.rxbuflock);
 485         if (list_empty(&sc->rx.rxbuf))
 486                 goto start_recv;
 487
 488         sc->rx.rxlink = NULL;
 489         list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) {
 490                 ath_rx_buf_link(sc, bf);
 491         }
 492
 493         /* We could have deleted elements so the list may be empty now */
 494         if (list_empty(&sc->rx.rxbuf))
 495                 goto start_recv;
 496
 497         bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
 498         ath9k_hw_putrxbuf(ah, bf->bf_daddr);
 499         ath9k_hw_rxena(ah);
 500
 501 start_recv:
 502         spin_unlock_bh(&sc->rx.rxbuflock);
 503         ath_opmode_init(sc);
 504         ath9k_hw_startpcureceive(ah);
 505
 506         return 0;
 507 }
 508
 509 bool ath_stoprecv(struct ath_softc *sc)
 510 {
 511         struct ath_hw *ah = sc->sc_ah;
 512         bool stopped;
 513
 514         ath9k_hw_stoppcurecv(ah);
 515         ath9k_hw_setrxfilter(ah, 0);
 516         stopped = ath9k_hw_stopdmarecv(ah);
 517
 518         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
 519                 ath_edma_stop_recv(sc);
 520         else
 521                 sc->rx.rxlink = NULL;
 522
 523         return stopped;
 524 }
 525
 526 void ath_flushrecv(struct ath_softc *sc)
 527 {
 528         spin_lock_bh(&sc->rx.rxflushlock);
 529         sc->sc_flags |= SC_OP_RXFLUSH;
 530         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
 531                 ath_rx_tasklet(sc, 1, true);
 532         ath_rx_tasklet(sc, 1, false);
 533         sc->sc_flags &= ~SC_OP_RXFLUSH;
 534         spin_unlock_bh(&sc->rx.rxflushlock);
 535 }
 536
 537 static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb)
 538 {
 539         /* Check whether the Beacon frame has DTIM indicating buffered bc/mc */
 540         struct ieee80211_mgmt *mgmt;
 541         u8 *pos, *end, id, elen;
 542         struct ieee80211_tim_ie *tim;
 543
 544         mgmt = (struct ieee80211_mgmt *)skb->data;
 545         pos = mgmt->u.beacon.variable;
 546         end = skb->data + skb->len;
 547
 548         while (pos + 2 < end) {
 549                 id = *pos++;
 550                 elen = *pos++;
 551                 if (pos + elen > end)
 552                         break;
 553
 554                 if (id == WLAN_EID_TIM) {
 555                         if (elen < sizeof(*tim))
 556                                 break;
 557                         tim = (struct ieee80211_tim_ie *) pos;
 558                         if (tim->dtim_count != 0)
 559                                 break;
 560                         return tim->bitmap_ctrl & 0x01;
 561                 }
 562
 563                 pos += elen;
 564         }
 565
 566         return false;
 567 }
 568
 569 static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
 570 {
 571         struct ieee80211_mgmt *mgmt;
 572         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 573
 574         if (skb->len < 24 + 8 + 2 + 2)
 575                 return;
 576
 577         mgmt = (struct ieee80211_mgmt *)skb->data;
 578         if (memcmp(common->curbssid, mgmt->bssid, ETH_ALEN) != 0)
 579                 return; /* not from our current AP */
 580
 581         sc->ps_flags &= ~PS_WAIT_FOR_BEACON;
 582
 583         if (sc->ps_flags & PS_BEACON_SYNC) {
 584                 sc->ps_flags &= ~PS_BEACON_SYNC;
 585                 ath_print(common, ATH_DBG_PS,
 586                           "Reconfigure Beacon timers based on "
 587                           "timestamp from the AP\n");
 588                 ath_beacon_config(sc, NULL);
 589         }
 590
 591         if (ath_beacon_dtim_pending_cab(skb)) {
 592                 /*
 593                  * Remain awake waiting for buffered broadcast/multicast
 594                  * frames. If the last broadcast/multicast frame is not
 595                  * received properly, the next beacon frame will work as
 596                  * a backup trigger for returning into NETWORK SLEEP state,
 597                  * so we are waiting for it as well.
 598                  */
 599                 ath_print(common, ATH_DBG_PS, "Received DTIM beacon indicating "
 600                           "buffered broadcast/multicast frame(s)\n");
 601                 sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON;
 602                 return;
 603         }
 604
 605         if (sc->ps_flags & PS_WAIT_FOR_CAB) {
 606                 /*
 607                  * This can happen if a broadcast frame is dropped or the AP
 608                  * fails to send a frame indicating that all CAB frames have
 609                  * been delivered.
 610                  */
 611                 sc->ps_flags &= ~PS_WAIT_FOR_CAB;
 612                 ath_print(common, ATH_DBG_PS,
 613                           "PS wait for CAB frames timed out\n");
 614         }
 615 }
 616
 617 static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb)
 618 {
 619         struct ieee80211_hdr *hdr;
 620         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 621
 622         hdr = (struct ieee80211_hdr *)skb->data;
 623
 624         /* Process Beacon and CAB receive in PS state */
 625         if (((sc->ps_flags & PS_WAIT_FOR_BEACON) || ath9k_check_auto_sleep(sc))
 626             && ieee80211_is_beacon(hdr->frame_control))
 627                 ath_rx_ps_beacon(sc, skb);
 628         else if ((sc->ps_flags & PS_WAIT_FOR_CAB) &&
 629                  (ieee80211_is_data(hdr->frame_control) ||
 630                   ieee80211_is_action(hdr->frame_control)) &&
 631                  is_multicast_ether_addr(hdr->addr1) &&
 632                  !ieee80211_has_moredata(hdr->frame_control)) {
 633                 /*
 634                  * No more broadcast/multicast frames to be received at this
 635                  * point.
 636                  */
 637                 sc->ps_flags &= ~PS_WAIT_FOR_CAB;
 638                 ath_print(common, ATH_DBG_PS,
 639                           "All PS CAB frames received, back to sleep\n");
 640         } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) &&
 641                    !is_multicast_ether_addr(hdr->addr1) &&
 642                    !ieee80211_has_morefrags(hdr->frame_control)) {
 643                 sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA;
 644                 ath_print(common, ATH_DBG_PS,
 645                           "Going back to sleep after having received "
 646                           "PS-Poll data (0x%lx)\n",
 647                         sc->ps_flags & (PS_WAIT_FOR_BEACON |
 648                                         PS_WAIT_FOR_CAB |
 649                                         PS_WAIT_FOR_PSPOLL_DATA |
 650                                         PS_WAIT_FOR_TX_ACK));
 651         }
 652 }
 653
 654 static void ath_rx_send_to_mac80211(struct ieee80211_hw *hw,
 655                                     struct ath_softc *sc, struct sk_buff *skb,
 656                                     struct ieee80211_rx_status *rxs)
 657 {
 658         struct ieee80211_hdr *hdr;
 659
 660         hdr = (struct ieee80211_hdr *)skb->data;
 661
 662         /* Send the frame to mac80211 */
 663         if (is_multicast_ether_addr(hdr->addr1)) {
 664                 int i;
 665                 /*
 666                  * Deliver broadcast/multicast frames to all suitable
 667                  * virtual wiphys.
 668                  */
 669                 /* TODO: filter based on channel configuration */
 670                 for (i = 0; i < sc->num_sec_wiphy; i++) {
 671                         struct ath_wiphy *aphy = sc->sec_wiphy[i];
 672                         struct sk_buff *nskb;
 673                         if (aphy == NULL)
 674                                 continue;
 675                         nskb = skb_copy(skb, GFP_ATOMIC);
 676                         if (!nskb)
 677                                 continue;
 678                         ieee80211_rx(aphy->hw, nskb);
 679                 }
 680                 ieee80211_rx(sc->hw, skb);
 681         } else
 682                 /* Deliver unicast frames based on receiver address */
 683                 ieee80211_rx(hw, skb);
 684 }
 685
 686 static bool ath_edma_get_buffers(struct ath_softc *sc,
 687                                  enum ath9k_rx_qtype qtype)
 688 {
 689         struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
 690         struct ath_hw *ah = sc->sc_ah;
 691         struct ath_common *common = ath9k_hw_common(ah);
 692         struct sk_buff *skb;
 693         struct ath_buf *bf;
 694         int ret;
 695
 696         skb = skb_peek(&rx_edma->rx_fifo);
 697         if (!skb)
 698                 return false;
 699
 700         bf = SKB_CB_ATHBUF(skb);
 701         BUG_ON(!bf);
 702
 703         dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
 704                                 common->rx_bufsize, DMA_FROM_DEVICE);
 705
 706         ret = ath9k_hw_process_rxdesc_edma(ah, NULL, skb->data);
 707         if (ret == -EINPROGRESS)
 708                 return false;
 709
 710         __skb_unlink(skb, &rx_edma->rx_fifo);
 711         if (ret == -EINVAL) {
 712                 /* corrupt descriptor, skip this one and the following one */
 713                 list_add_tail(&bf->list, &sc->rx.rxbuf);
 714                 ath_rx_edma_buf_link(sc, qtype);
 715                 skb = skb_peek(&rx_edma->rx_fifo);
 716                 if (!skb)
 717                         return true;
 718
 719                 bf = SKB_CB_ATHBUF(skb);
 720                 BUG_ON(!bf);
 721
 722                 __skb_unlink(skb, &rx_edma->rx_fifo);
 723                 list_add_tail(&bf->list, &sc->rx.rxbuf);
 724                 ath_rx_edma_buf_link(sc, qtype);
 725                 return true;
 726         }
 727         skb_queue_tail(&rx_edma->rx_buffers, skb);
 728
 729         return true;
 730 }
 731
 732 static struct ath_buf *ath_edma_get_next_rx_buf(struct ath_softc *sc,
 733                                                 struct ath_rx_status *rs,
 734                                                 enum ath9k_rx_qtype qtype)
 735 {
 736         struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
 737         struct sk_buff *skb;
 738         struct ath_buf *bf;
 739
 740         while (ath_edma_get_buffers(sc, qtype));
 741         skb = __skb_dequeue(&rx_edma->rx_buffers);
 742         if (!skb)
 743                 return NULL;
 744
 745         bf = SKB_CB_ATHBUF(skb);
 746         ath9k_hw_process_rxdesc_edma(sc->sc_ah, rs, skb->data);
 747         return bf;
 748 }
 749
 750 static struct ath_buf *ath_get_next_rx_buf(struct ath_softc *sc,
 751                                            struct ath_rx_status *rs)
 752 {
 753         struct ath_hw *ah = sc->sc_ah;
 754         struct ath_common *common = ath9k_hw_common(ah);
 755         struct ath_desc *ds;
 756         struct ath_buf *bf;
 757         int ret;
 758
 759         if (list_empty(&sc->rx.rxbuf)) {
 760                 sc->rx.rxlink = NULL;
 761                 return NULL;
 762         }
 763
 764         bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
 765         ds = bf->bf_desc;
 766
 767         /*
 768          * Must provide the virtual address of the current
 769          * descriptor, the physical address, and the virtual
 770          * address of the next descriptor in the h/w chain.
 771          * This allows the HAL to look ahead to see if the
 772          * hardware is done with a descriptor by checking the
 773          * done bit in the following descriptor and the address
 774          * of the current descriptor the DMA engine is working
 775          * on.  All this is necessary because of our use of
 776          * a self-linked list to avoid rx overruns.
 777          */
 778         ret = ath9k_hw_rxprocdesc(ah, ds, rs, 0);
 779         if (ret == -EINPROGRESS) {
 780                 struct ath_rx_status trs;
 781                 struct ath_buf *tbf;
 782                 struct ath_desc *tds;
 783
 784                 memset(&trs, 0, sizeof(trs));
 785                 if (list_is_last(&bf->list, &sc->rx.rxbuf)) {
 786                         sc->rx.rxlink = NULL;
 787                         return NULL;
 788                 }
 789
 790                 tbf = list_entry(bf->list.next, struct ath_buf, list);
 791
 792                 /*
 793                  * On some hardware the descriptor status words could
 794                  * get corrupted, including the done bit. Because of
 795                  * this, check if the next descriptor's done bit is
 796                  * set or not.
 797                  *
 798                  * If the next descriptor's done bit is set, the current
 799                  * descriptor has been corrupted. Force s/w to discard
 800                  * this descriptor and continue...
 801                  */
 802
 803                 tds = tbf->bf_desc;
 804                 ret = ath9k_hw_rxprocdesc(ah, tds, &trs, 0);
 805                 if (ret == -EINPROGRESS)
 806                         return NULL;
 807         }
 808
 809         if (!bf->bf_mpdu)
 810                 return bf;
 811
 812         /*
 813          * Synchronize the DMA transfer with CPU before
 814          * 1. accessing the frame
 815          * 2. requeueing the same buffer to h/w
 816          */
 817         dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
 818                         common->rx_bufsize,
 819                         DMA_FROM_DEVICE);
 820
 821         return bf;
 822 }
 823
 824
 825 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
 826 {
 827         struct ath_buf *bf;
 828         struct sk_buff *skb = NULL, *requeue_skb;
 829         struct ieee80211_rx_status *rxs;
 830         struct ath_hw *ah = sc->sc_ah;
 831         struct ath_common *common = ath9k_hw_common(ah);
 832         /*
 833          * The hw can techncically differ from common->hw when using ath9k
 834          * virtual wiphy so to account for that we iterate over the active
 835          * wiphys and find the appropriate wiphy and therefore hw.
 836          */
 837         struct ieee80211_hw *hw = NULL;
 838         struct ieee80211_hdr *hdr;
 839         int retval;
 840         bool decrypt_error = false;
 841         struct ath_rx_status rs;
 842         enum ath9k_rx_qtype qtype;
 843         bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
 844         int dma_type;
 845
 846         if (edma)
 847                 dma_type = DMA_BIDIRECTIONAL;
 848         else
 849                 dma_type = DMA_FROM_DEVICE;
 850
 851         qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP;
 852         spin_lock_bh(&sc->rx.rxbuflock);
 853
 854         do {
 855                 /* If handling rx interrupt and flush is in progress => exit */
 856                 if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0))
 857                         break;
 858
 859                 memset(&rs, 0, sizeof(rs));
 860                 if (edma)
 861                         bf = ath_edma_get_next_rx_buf(sc, &rs, qtype);
 862                 else
 863                         bf = ath_get_next_rx_buf(sc, &rs);
 864
 865                 if (!bf)
 866                         break;
 867
 868                 skb = bf->bf_mpdu;
 869                 if (!skb)
 870                         continue;
 871
 872                 hdr = (struct ieee80211_hdr *) skb->data;
 873                 rxs =  IEEE80211_SKB_RXCB(skb);
 874
 875                 hw = ath_get_virt_hw(sc, hdr);
 876
 877                 ath_debug_stat_rx(sc, &rs);
 878
 879                 /*
 880                  * If we're asked to flush receive queue, directly
 881                  * chain it back at the queue without processing it.
 882                  */
 883                 if (flush)
 884                         goto requeue;
 885
 886                 retval = ath9k_cmn_rx_skb_preprocess(common, hw, skb, &rs,
 887                                                      rxs, &decrypt_error);
 888                 if (retval)
 889                         goto requeue;
 890
 891                 /* Ensure we always have an skb to requeue once we are done
 892                  * processing the current buffer's skb */
 893                 requeue_skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_ATOMIC);
 894
 895                 /* If there is no memory we ignore the current RX'd frame,
 896                  * tell hardware it can give us a new frame using the old
 897                  * skb and put it at the tail of the sc->rx.rxbuf list for
 898                  * processing. */
 899                 if (!requeue_skb)
 900                         goto requeue;
 901
 902                 /* Unmap the frame */
 903                 dma_unmap_single(sc->dev, bf->bf_buf_addr,
 904                                  common->rx_bufsize,
 905                                  dma_type);
 906
 907                 skb_put(skb, rs.rs_datalen + ah->caps.rx_status_len);
 908                 if (ah->caps.rx_status_len)
 909                         skb_pull(skb, ah->caps.rx_status_len);
 910
 911                 ath9k_cmn_rx_skb_postprocess(common, skb, &rs,
 912                                              rxs, decrypt_error);
 913
 914                 /* We will now give hardware our shiny new allocated skb */
 915                 bf->bf_mpdu = requeue_skb;
 916                 bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data,
 917                                                  common->rx_bufsize,
 918                                                  dma_type);
 919                 if (unlikely(dma_mapping_error(sc->dev,
 920                           bf->bf_buf_addr))) {
 921                         dev_kfree_skb_any(requeue_skb);
 922                         bf->bf_mpdu = NULL;
 923                         ath_print(common, ATH_DBG_FATAL,
 924                                   "dma_mapping_error() on RX\n");
 925                         ath_rx_send_to_mac80211(hw, sc, skb, rxs);
 926                         break;
 927                 }
 928                 bf->bf_dmacontext = bf->bf_buf_addr;
 929
 930                 /*
 931                  * change the default rx antenna if rx diversity chooses the
 932                  * other antenna 3 times in a row.
 933                  */
 934                 if (sc->rx.defant != rs.rs_antenna) {
 935                         if (++sc->rx.rxotherant >= 3)
 936                                 ath_setdefantenna(sc, rs.rs_antenna);
 937                 } else {
 938                         sc->rx.rxotherant = 0;
 939                 }
 940
 941                 if (unlikely(ath9k_check_auto_sleep(sc) ||
 942                              (sc->ps_flags & (PS_WAIT_FOR_BEACON |
 943                                               PS_WAIT_FOR_CAB |
 944                                               PS_WAIT_FOR_PSPOLL_DATA))))
 945                         ath_rx_ps(sc, skb);
 946
 947                 ath_rx_send_to_mac80211(hw, sc, skb, rxs);
 948
 949 requeue:
 950                 if (edma) {
 951                         list_add_tail(&bf->list, &sc->rx.rxbuf);
 952                         ath_rx_edma_buf_link(sc, qtype);
 953                 } else {
 954                         list_move_tail(&bf->list, &sc->rx.rxbuf);
 955                         ath_rx_buf_link(sc, bf);
 956                 }
 957         } while (1);
 958
 959         spin_unlock_bh(&sc->rx.rxbuflock);
 960
 961         return 0;
 962 }