drivers/net/wireless/ath/ath9k/ar9003_calib.c

   1 /*
   2  * Copyright (c) 2010 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "hw.h"
  18 #include "hw-ops.h"
  19 #include "ar9003_phy.h"
  20
  21 static void ar9003_hw_setup_calibration(struct ath_hw *ah,
  22                                         struct ath9k_cal_list *currCal)
  23 {
  24         struct ath_common *common = ath9k_hw_common(ah);
  25
  26         /* Select calibration to run */
  27         switch (currCal->calData->calType) {
  28         case IQ_MISMATCH_CAL:
  29                 /*
  30                  * Start calibration with
  31                  * 2^(INIT_IQCAL_LOG_COUNT_MAX+1) samples
  32                  */
  33                 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
  34                               AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX,
  35                 currCal->calData->calCountMax);
  36                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
  37
  38                 ath_print(common, ATH_DBG_CALIBRATE,
  39                           "starting IQ Mismatch Calibration\n");
  40
  41                 /* Kick-off cal */
  42                 REG_SET_BIT(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL);
  43                 break;
  44         case TEMP_COMP_CAL:
  45                 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_THERM,
  46                               AR_PHY_65NM_CH0_THERM_LOCAL, 1);
  47                 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_THERM,
  48                               AR_PHY_65NM_CH0_THERM_START, 1);
  49
  50                 ath_print(common, ATH_DBG_CALIBRATE,
  51                           "starting Temperature Compensation Calibration\n");
  52                 break;
  53         case ADC_DC_INIT_CAL:
  54         case ADC_GAIN_CAL:
  55         case ADC_DC_CAL:
  56                 /* Not yet */
  57                 break;
  58         }
  59 }
  60
  61 /*
  62  * Generic calibration routine.
  63  * Recalibrate the lower PHY chips to account for temperature/environment
  64  * changes.
  65  */
  66 static bool ar9003_hw_per_calibration(struct ath_hw *ah,
  67                                       struct ath9k_channel *ichan,
  68                                       u8 rxchainmask,
  69                                       struct ath9k_cal_list *currCal)
  70 {
  71         struct ath9k_hw_cal_data *caldata = ah->caldata;
  72         /* Cal is assumed not done until explicitly set below */
  73         bool iscaldone = false;
  74
  75         /* Calibration in progress. */
  76         if (currCal->calState == CAL_RUNNING) {
  77                 /* Check to see if it has finished. */
  78                 if (!(REG_READ(ah, AR_PHY_TIMING4) & AR_PHY_TIMING4_DO_CAL)) {
  79                         /*
  80                         * Accumulate cal measures for active chains
  81                         */
  82                         currCal->calData->calCollect(ah);
  83                         ah->cal_samples++;
  84
  85                         if (ah->cal_samples >=
  86                             currCal->calData->calNumSamples) {
  87                                 unsigned int i, numChains = 0;
  88                                 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
  89                                         if (rxchainmask & (1 << i))
  90                                                 numChains++;
  91                                 }
  92
  93                                 /*
  94                                 * Process accumulated data
  95                                 */
  96                                 currCal->calData->calPostProc(ah, numChains);
  97
  98                                 /* Calibration has finished. */
  99                                 caldata->CalValid |= currCal->calData->calType;
 100                                 currCal->calState = CAL_DONE;
 101                                 iscaldone = true;
 102                         } else {
 103                         /*
 104                          * Set-up collection of another sub-sample until we
 105                          * get desired number
 106                          */
 107                         ar9003_hw_setup_calibration(ah, currCal);
 108                         }
 109                 }
 110         } else if (!(caldata->CalValid & currCal->calData->calType)) {
 111                 /* If current cal is marked invalid in channel, kick it off */
 112                 ath9k_hw_reset_calibration(ah, currCal);
 113         }
 114
 115         return iscaldone;
 116 }
 117
 118 static bool ar9003_hw_calibrate(struct ath_hw *ah,
 119                                 struct ath9k_channel *chan,
 120                                 u8 rxchainmask,
 121                                 bool longcal)
 122 {
 123         bool iscaldone = true;
 124         struct ath9k_cal_list *currCal = ah->cal_list_curr;
 125
 126         /*
 127          * For given calibration:
 128          * 1. Call generic cal routine
 129          * 2. When this cal is done (isCalDone) if we have more cals waiting
 130          *    (eg after reset), mask this to upper layers by not propagating
 131          *    isCalDone if it is set to TRUE.
 132          *    Instead, change isCalDone to FALSE and setup the waiting cal(s)
 133          *    to be run.
 134          */
 135         if (currCal &&
 136             (currCal->calState == CAL_RUNNING ||
 137              currCal->calState == CAL_WAITING)) {
 138                 iscaldone = ar9003_hw_per_calibration(ah, chan,
 139                                                       rxchainmask, currCal);
 140                 if (iscaldone) {
 141                         ah->cal_list_curr = currCal = currCal->calNext;
 142
 143                         if (currCal->calState == CAL_WAITING) {
 144                                 iscaldone = false;
 145                                 ath9k_hw_reset_calibration(ah, currCal);
 146                         }
 147                 }
 148         }
 149
 150         /* Do NF cal only at longer intervals */
 151         if (longcal) {
 152                 /*
 153                  * Get the value from the previous NF cal and update
 154                  * history buffer.
 155                  */
 156                 ath9k_hw_getnf(ah, chan);
 157
 158                 /*
 159                  * Load the NF from history buffer of the current channel.
 160                  * NF is slow time-variant, so it is OK to use a historical
 161                  * value.
 162                  */
 163                 ath9k_hw_loadnf(ah, ah->curchan);
 164
 165                 /* start NF calibration, without updating BB NF register */
 166                 ath9k_hw_start_nfcal(ah, false);
 167         }
 168
 169         return iscaldone;
 170 }
 171
 172 static void ar9003_hw_iqcal_collect(struct ath_hw *ah)
 173 {
 174         int i;
 175
 176         /* Accumulate IQ cal measures for active chains */
 177         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 178                 ah->totalPowerMeasI[i] +=
 179                         REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
 180                 ah->totalPowerMeasQ[i] +=
 181                         REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
 182                 ah->totalIqCorrMeas[i] +=
 183                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
 184                 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
 185                           "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
 186                           ah->cal_samples, i, ah->totalPowerMeasI[i],
 187                           ah->totalPowerMeasQ[i],
 188                           ah->totalIqCorrMeas[i]);
 189         }
 190 }
 191
 192 static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
 193 {
 194         struct ath_common *common = ath9k_hw_common(ah);
 195         u32 powerMeasQ, powerMeasI, iqCorrMeas;
 196         u32 qCoffDenom, iCoffDenom;
 197         int32_t qCoff, iCoff;
 198         int iqCorrNeg, i;
 199         const u_int32_t offset_array[3] = {
 200                 AR_PHY_RX_IQCAL_CORR_B0,
 201                 AR_PHY_RX_IQCAL_CORR_B1,
 202                 AR_PHY_RX_IQCAL_CORR_B2,
 203         };
 204
 205         for (i = 0; i < numChains; i++) {
 206                 powerMeasI = ah->totalPowerMeasI[i];
 207                 powerMeasQ = ah->totalPowerMeasQ[i];
 208                 iqCorrMeas = ah->totalIqCorrMeas[i];
 209
 210                 ath_print(common, ATH_DBG_CALIBRATE,
 211                           "Starting IQ Cal and Correction for Chain %d\n",
 212                           i);
 213
 214                 ath_print(common, ATH_DBG_CALIBRATE,
 215                           "Orignal: Chn %diq_corr_meas = 0x%08x\n",
 216                           i, ah->totalIqCorrMeas[i]);
 217
 218                 iqCorrNeg = 0;
 219
 220                 if (iqCorrMeas > 0x80000000) {
 221                         iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
 222                         iqCorrNeg = 1;
 223                 }
 224
 225                 ath_print(common, ATH_DBG_CALIBRATE,
 226                           "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
 227                 ath_print(common, ATH_DBG_CALIBRATE,
 228                           "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
 229                 ath_print(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
 230                           iqCorrNeg);
 231
 232                 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 256;
 233                 qCoffDenom = powerMeasQ / 64;
 234
 235                 if ((iCoffDenom != 0) && (qCoffDenom != 0)) {
 236                         iCoff = iqCorrMeas / iCoffDenom;
 237                         qCoff = powerMeasI / qCoffDenom - 64;
 238                         ath_print(common, ATH_DBG_CALIBRATE,
 239                                   "Chn %d iCoff = 0x%08x\n", i, iCoff);
 240                         ath_print(common, ATH_DBG_CALIBRATE,
 241                                   "Chn %d qCoff = 0x%08x\n", i, qCoff);
 242
 243                         /* Force bounds on iCoff */
 244                         if (iCoff >= 63)
 245                                 iCoff = 63;
 246                         else if (iCoff <= -63)
 247                                 iCoff = -63;
 248
 249                         /* Negate iCoff if iqCorrNeg == 0 */
 250                         if (iqCorrNeg == 0x0)
 251                                 iCoff = -iCoff;
 252
 253                         /* Force bounds on qCoff */
 254                         if (qCoff >= 63)
 255                                 qCoff = 63;
 256                         else if (qCoff <= -63)
 257                                 qCoff = -63;
 258
 259                         iCoff = iCoff & 0x7f;
 260                         qCoff = qCoff & 0x7f;
 261
 262                         ath_print(common, ATH_DBG_CALIBRATE,
 263                                   "Chn %d : iCoff = 0x%x  qCoff = 0x%x\n",
 264                                   i, iCoff, qCoff);
 265                         ath_print(common, ATH_DBG_CALIBRATE,
 266                                   "Register offset (0x%04x) "
 267                                   "before update = 0x%x\n",
 268                                   offset_array[i],
 269                                   REG_READ(ah, offset_array[i]));
 270
 271                         REG_RMW_FIELD(ah, offset_array[i],
 272                                       AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF,
 273                                       iCoff);
 274                         REG_RMW_FIELD(ah, offset_array[i],
 275                                       AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF,
 276                                       qCoff);
 277                         ath_print(common, ATH_DBG_CALIBRATE,
 278                                   "Register offset (0x%04x) QI COFF "
 279                                   "(bitfields 0x%08x) after update = 0x%x\n",
 280                                   offset_array[i],
 281                                   AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF,
 282                                   REG_READ(ah, offset_array[i]));
 283                         ath_print(common, ATH_DBG_CALIBRATE,
 284                                   "Register offset (0x%04x) QQ COFF "
 285                                   "(bitfields 0x%08x) after update = 0x%x\n",
 286                                   offset_array[i],
 287                                   AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF,
 288                                   REG_READ(ah, offset_array[i]));
 289
 290                         ath_print(common, ATH_DBG_CALIBRATE,
 291                                   "IQ Cal and Correction done for Chain %d\n",
 292                                   i);
 293                 }
 294         }
 295
 296         REG_SET_BIT(ah, AR_PHY_RX_IQCAL_CORR_B0,
 297                     AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE);
 298         ath_print(common, ATH_DBG_CALIBRATE,
 299                   "IQ Cal and Correction (offset 0x%04x) enabled "
 300                   "(bit position 0x%08x). New Value 0x%08x\n",
 301                   (unsigned) (AR_PHY_RX_IQCAL_CORR_B0),
 302                   AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE,
 303                   REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B0));
 304 }
 305
 306 static const struct ath9k_percal_data iq_cal_single_sample = {
 307         IQ_MISMATCH_CAL,
 308         MIN_CAL_SAMPLES,
 309         PER_MAX_LOG_COUNT,
 310         ar9003_hw_iqcal_collect,
 311         ar9003_hw_iqcalibrate
 312 };
 313
 314 static void ar9003_hw_init_cal_settings(struct ath_hw *ah)
 315 {
 316         ah->iq_caldata.calData = &iq_cal_single_sample;
 317         ah->supp_cals = IQ_MISMATCH_CAL;
 318 }
 319
 320 static bool ar9003_hw_iscal_supported(struct ath_hw *ah,
 321                                       enum ath9k_cal_types calType)
 322 {
 323         switch (calType & ah->supp_cals) {
 324         case IQ_MISMATCH_CAL:
 325                 /*
 326                  * XXX: Run IQ Mismatch for non-CCK only
 327                  * Note that CHANNEL_B is never set though.
 328                  */
 329                 return true;
 330         case ADC_GAIN_CAL:
 331         case ADC_DC_CAL:
 332                 return false;
 333         case TEMP_COMP_CAL:
 334                 return true;
 335         }
 336
 337         return false;
 338 }
 339
 340 /*
 341  * solve 4x4 linear equation used in loopback iq cal.
 342  */
 343 static bool ar9003_hw_solve_iq_cal(struct ath_hw *ah,
 344                                    s32 sin_2phi_1,
 345                                    s32 cos_2phi_1,
 346                                    s32 sin_2phi_2,
 347                                    s32 cos_2phi_2,
 348                                    s32 mag_a0_d0,
 349                                    s32 phs_a0_d0,
 350                                    s32 mag_a1_d0,
 351                                    s32 phs_a1_d0,
 352                                    s32 solved_eq[])
 353 {
 354         s32 f1 = cos_2phi_1 - cos_2phi_2,
 355             f3 = sin_2phi_1 - sin_2phi_2,
 356             f2;
 357         s32 mag_tx, phs_tx, mag_rx, phs_rx;
 358         const s32 result_shift = 1 << 15;
 359         struct ath_common *common = ath9k_hw_common(ah);
 360
 361         f2 = (f1 * f1 + f3 * f3) / result_shift;
 362
 363         if (!f2) {
 364                 ath_print(common, ATH_DBG_CALIBRATE, "Divide by 0\n");
 365                 return false;
 366         }
 367
 368         /* mag mismatch, tx */
 369         mag_tx = f1 * (mag_a0_d0  - mag_a1_d0) + f3 * (phs_a0_d0 - phs_a1_d0);
 370         /* phs mismatch, tx */
 371         phs_tx = f3 * (-mag_a0_d0 + mag_a1_d0) + f1 * (phs_a0_d0 - phs_a1_d0);
 372
 373         mag_tx = (mag_tx / f2);
 374         phs_tx = (phs_tx / f2);
 375
 376         /* mag mismatch, rx */
 377         mag_rx = mag_a0_d0 - (cos_2phi_1 * mag_tx + sin_2phi_1 * phs_tx) /
 378                  result_shift;
 379         /* phs mismatch, rx */
 380         phs_rx = phs_a0_d0 + (sin_2phi_1 * mag_tx - cos_2phi_1 * phs_tx) /
 381                  result_shift;
 382
 383         solved_eq[0] = mag_tx;
 384         solved_eq[1] = phs_tx;
 385         solved_eq[2] = mag_rx;
 386         solved_eq[3] = phs_rx;
 387
 388         return true;
 389 }
 390
 391 static s32 ar9003_hw_find_mag_approx(struct ath_hw *ah, s32 in_re, s32 in_im)
 392 {
 393         s32 abs_i = abs(in_re),
 394             abs_q = abs(in_im),
 395             max_abs, min_abs;
 396
 397         if (abs_i > abs_q) {
 398                 max_abs = abs_i;
 399                 min_abs = abs_q;
 400         } else {
 401                 max_abs = abs_q;
 402                 min_abs = abs_i;
 403         }
 404
 405         return max_abs - (max_abs / 32) + (min_abs / 8) + (min_abs / 4);
 406 }
 407
 408 #define DELPT 32
 409
 410 static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
 411                                    s32 chain_idx,
 412                                    const s32 iq_res[],
 413                                    s32 iqc_coeff[])
 414 {
 415         s32 i2_m_q2_a0_d0, i2_p_q2_a0_d0, iq_corr_a0_d0,
 416             i2_m_q2_a0_d1, i2_p_q2_a0_d1, iq_corr_a0_d1,
 417             i2_m_q2_a1_d0, i2_p_q2_a1_d0, iq_corr_a1_d0,
 418             i2_m_q2_a1_d1, i2_p_q2_a1_d1, iq_corr_a1_d1;
 419         s32 mag_a0_d0, mag_a1_d0, mag_a0_d1, mag_a1_d1,
 420             phs_a0_d0, phs_a1_d0, phs_a0_d1, phs_a1_d1,
 421             sin_2phi_1, cos_2phi_1,
 422             sin_2phi_2, cos_2phi_2;
 423         s32 mag_tx, phs_tx, mag_rx, phs_rx;
 424         s32 solved_eq[4], mag_corr_tx, phs_corr_tx, mag_corr_rx, phs_corr_rx,
 425             q_q_coff, q_i_coff;
 426         const s32 res_scale = 1 << 15;
 427         const s32 delpt_shift = 1 << 8;
 428         s32 mag1, mag2;
 429         struct ath_common *common = ath9k_hw_common(ah);
 430
 431         i2_m_q2_a0_d0 = iq_res[0] & 0xfff;
 432         i2_p_q2_a0_d0 = (iq_res[0] >> 12) & 0xfff;
 433         iq_corr_a0_d0 = ((iq_res[0] >> 24) & 0xff) + ((iq_res[1] & 0xf) << 8);
 434
 435         if (i2_m_q2_a0_d0 > 0x800)
 436                 i2_m_q2_a0_d0 = -((0xfff - i2_m_q2_a0_d0) + 1);
 437
 438         if (i2_p_q2_a0_d0 > 0x800)
 439                 i2_p_q2_a0_d0 = -((0xfff - i2_p_q2_a0_d0) + 1);
 440
 441         if (iq_corr_a0_d0 > 0x800)
 442                 iq_corr_a0_d0 = -((0xfff - iq_corr_a0_d0) + 1);
 443
 444         i2_m_q2_a0_d1 = (iq_res[1] >> 4) & 0xfff;
 445         i2_p_q2_a0_d1 = (iq_res[2] & 0xfff);
 446         iq_corr_a0_d1 = (iq_res[2] >> 12) & 0xfff;
 447
 448         if (i2_m_q2_a0_d1 > 0x800)
 449                 i2_m_q2_a0_d1 = -((0xfff - i2_m_q2_a0_d1) + 1);
 450
 451         if (i2_p_q2_a0_d1 > 0x800)
 452                 i2_p_q2_a0_d1 = -((0xfff - i2_p_q2_a0_d1) + 1);
 453
 454         if (iq_corr_a0_d1 > 0x800)
 455                 iq_corr_a0_d1 = -((0xfff - iq_corr_a0_d1) + 1);
 456
 457         i2_m_q2_a1_d0 = ((iq_res[2] >> 24) & 0xff) + ((iq_res[3] & 0xf) << 8);
 458         i2_p_q2_a1_d0 = (iq_res[3] >> 4) & 0xfff;
 459         iq_corr_a1_d0 = iq_res[4] & 0xfff;
 460
 461         if (i2_m_q2_a1_d0 > 0x800)
 462                 i2_m_q2_a1_d0 = -((0xfff - i2_m_q2_a1_d0) + 1);
 463
 464         if (i2_p_q2_a1_d0 > 0x800)
 465                 i2_p_q2_a1_d0 = -((0xfff - i2_p_q2_a1_d0) + 1);
 466
 467         if (iq_corr_a1_d0 > 0x800)
 468                 iq_corr_a1_d0 = -((0xfff - iq_corr_a1_d0) + 1);
 469
 470         i2_m_q2_a1_d1 = (iq_res[4] >> 12) & 0xfff;
 471         i2_p_q2_a1_d1 = ((iq_res[4] >> 24) & 0xff) + ((iq_res[5] & 0xf) << 8);
 472         iq_corr_a1_d1 = (iq_res[5] >> 4) & 0xfff;
 473
 474         if (i2_m_q2_a1_d1 > 0x800)
 475                 i2_m_q2_a1_d1 = -((0xfff - i2_m_q2_a1_d1) + 1);
 476
 477         if (i2_p_q2_a1_d1 > 0x800)
 478                 i2_p_q2_a1_d1 = -((0xfff - i2_p_q2_a1_d1) + 1);
 479
 480         if (iq_corr_a1_d1 > 0x800)
 481                 iq_corr_a1_d1 = -((0xfff - iq_corr_a1_d1) + 1);
 482
 483         if ((i2_p_q2_a0_d0 == 0) || (i2_p_q2_a0_d1 == 0) ||
 484             (i2_p_q2_a1_d0 == 0) || (i2_p_q2_a1_d1 == 0)) {
 485                 ath_print(common, ATH_DBG_CALIBRATE,
 486                           "Divide by 0:\na0_d0=%d\n"
 487                           "a0_d1=%d\na2_d0=%d\na1_d1=%d\n",
 488                           i2_p_q2_a0_d0, i2_p_q2_a0_d1,
 489                           i2_p_q2_a1_d0, i2_p_q2_a1_d1);
 490                 return false;
 491         }
 492
 493         mag_a0_d0 = (i2_m_q2_a0_d0 * res_scale) / i2_p_q2_a0_d0;
 494         phs_a0_d0 = (iq_corr_a0_d0 * res_scale) / i2_p_q2_a0_d0;
 495
 496         mag_a0_d1 = (i2_m_q2_a0_d1 * res_scale) / i2_p_q2_a0_d1;
 497         phs_a0_d1 = (iq_corr_a0_d1 * res_scale) / i2_p_q2_a0_d1;
 498
 499         mag_a1_d0 = (i2_m_q2_a1_d0 * res_scale) / i2_p_q2_a1_d0;
 500         phs_a1_d0 = (iq_corr_a1_d0 * res_scale) / i2_p_q2_a1_d0;
 501
 502         mag_a1_d1 = (i2_m_q2_a1_d1 * res_scale) / i2_p_q2_a1_d1;
 503         phs_a1_d1 = (iq_corr_a1_d1 * res_scale) / i2_p_q2_a1_d1;
 504
 505         /* w/o analog phase shift */
 506         sin_2phi_1 = (((mag_a0_d0 - mag_a0_d1) * delpt_shift) / DELPT);
 507         /* w/o analog phase shift */
 508         cos_2phi_1 = (((phs_a0_d1 - phs_a0_d0) * delpt_shift) / DELPT);
 509         /* w/  analog phase shift */
 510         sin_2phi_2 = (((mag_a1_d0 - mag_a1_d1) * delpt_shift) / DELPT);
 511         /* w/  analog phase shift */
 512         cos_2phi_2 = (((phs_a1_d1 - phs_a1_d0) * delpt_shift) / DELPT);
 513
 514         /*
 515          * force sin^2 + cos^2 = 1;
 516          * find magnitude by approximation
 517          */
 518         mag1 = ar9003_hw_find_mag_approx(ah, cos_2phi_1, sin_2phi_1);
 519         mag2 = ar9003_hw_find_mag_approx(ah, cos_2phi_2, sin_2phi_2);
 520
 521         if ((mag1 == 0) || (mag2 == 0)) {
 522                 ath_print(common, ATH_DBG_CALIBRATE,
 523                           "Divide by 0: mag1=%d, mag2=%d\n",
 524                           mag1, mag2);
 525                 return false;
 526         }
 527
 528         /* normalization sin and cos by mag */
 529         sin_2phi_1 = (sin_2phi_1 * res_scale / mag1);
 530         cos_2phi_1 = (cos_2phi_1 * res_scale / mag1);
 531         sin_2phi_2 = (sin_2phi_2 * res_scale / mag2);
 532         cos_2phi_2 = (cos_2phi_2 * res_scale / mag2);
 533
 534         /* calculate IQ mismatch */
 535         if (!ar9003_hw_solve_iq_cal(ah,
 536                              sin_2phi_1, cos_2phi_1,
 537                              sin_2phi_2, cos_2phi_2,
 538                              mag_a0_d0, phs_a0_d0,
 539                              mag_a1_d0,
 540                              phs_a1_d0, solved_eq)) {
 541                 ath_print(common, ATH_DBG_CALIBRATE,
 542                           "Call to ar9003_hw_solve_iq_cal() failed.\n");
 543                 return false;
 544         }
 545
 546         mag_tx = solved_eq[0];
 547         phs_tx = solved_eq[1];
 548         mag_rx = solved_eq[2];
 549         phs_rx = solved_eq[3];
 550
 551         ath_print(common, ATH_DBG_CALIBRATE,
 552                   "chain %d: mag mismatch=%d phase mismatch=%d\n",
 553                   chain_idx, mag_tx/res_scale, phs_tx/res_scale);
 554
 555         if (res_scale == mag_tx) {
 556                 ath_print(common, ATH_DBG_CALIBRATE,
 557                           "Divide by 0: mag_tx=%d, res_scale=%d\n",
 558                           mag_tx, res_scale);
 559                 return false;
 560         }
 561
 562         /* calculate and quantize Tx IQ correction factor */
 563         mag_corr_tx = (mag_tx * res_scale) / (res_scale - mag_tx);
 564         phs_corr_tx = -phs_tx;
 565
 566         q_q_coff = (mag_corr_tx * 128 / res_scale);
 567         q_i_coff = (phs_corr_tx * 256 / res_scale);
 568
 569         ath_print(common, ATH_DBG_CALIBRATE,
 570                   "tx chain %d: mag corr=%d  phase corr=%d\n",
 571                   chain_idx, q_q_coff, q_i_coff);
 572
 573         if (q_i_coff < -63)
 574                 q_i_coff = -63;
 575         if (q_i_coff > 63)
 576                 q_i_coff = 63;
 577         if (q_q_coff < -63)
 578                 q_q_coff = -63;
 579         if (q_q_coff > 63)
 580                 q_q_coff = 63;
 581
 582         iqc_coeff[0] = (q_q_coff * 128) + q_i_coff;
 583
 584         ath_print(common, ATH_DBG_CALIBRATE,
 585                   "tx chain %d: iq corr coeff=%x\n",
 586                   chain_idx, iqc_coeff[0]);
 587
 588         if (-mag_rx == res_scale) {
 589                 ath_print(common, ATH_DBG_CALIBRATE,
 590                           "Divide by 0: mag_rx=%d, res_scale=%d\n",
 591                           mag_rx, res_scale);
 592                 return false;
 593         }
 594
 595         /* calculate and quantize Rx IQ correction factors */
 596         mag_corr_rx = (-mag_rx * res_scale) / (res_scale + mag_rx);
 597         phs_corr_rx = -phs_rx;
 598
 599         q_q_coff = (mag_corr_rx * 128 / res_scale);
 600         q_i_coff = (phs_corr_rx * 256 / res_scale);
 601
 602         ath_print(common, ATH_DBG_CALIBRATE,
 603                   "rx chain %d: mag corr=%d  phase corr=%d\n",
 604                   chain_idx, q_q_coff, q_i_coff);
 605
 606         if (q_i_coff < -63)
 607                 q_i_coff = -63;
 608         if (q_i_coff > 63)
 609                 q_i_coff = 63;
 610         if (q_q_coff < -63)
 611                 q_q_coff = -63;
 612         if (q_q_coff > 63)
 613                 q_q_coff = 63;
 614
 615         iqc_coeff[1] = (q_q_coff * 128) + q_i_coff;
 616
 617         ath_print(common, ATH_DBG_CALIBRATE,
 618                   "rx chain %d: iq corr coeff=%x\n",
 619                   chain_idx, iqc_coeff[1]);
 620
 621         return true;
 622 }
 623
 624 static void ar9003_hw_tx_iq_cal(struct ath_hw *ah)
 625 {
 626         struct ath_common *common = ath9k_hw_common(ah);
 627         const u32 txiqcal_status[AR9300_MAX_CHAINS] = {
 628                 AR_PHY_TX_IQCAL_STATUS_B0,
 629                 AR_PHY_TX_IQCAL_STATUS_B1,
 630                 AR_PHY_TX_IQCAL_STATUS_B2,
 631         };
 632         const u32 tx_corr_coeff[AR9300_MAX_CHAINS] = {
 633                 AR_PHY_TX_IQCAL_CORR_COEFF_01_B0,
 634                 AR_PHY_TX_IQCAL_CORR_COEFF_01_B1,
 635                 AR_PHY_TX_IQCAL_CORR_COEFF_01_B2,
 636         };
 637         const u32 rx_corr[AR9300_MAX_CHAINS] = {
 638                 AR_PHY_RX_IQCAL_CORR_B0,
 639                 AR_PHY_RX_IQCAL_CORR_B1,
 640                 AR_PHY_RX_IQCAL_CORR_B2,
 641         };
 642         const u_int32_t chan_info_tab[] = {
 643                 AR_PHY_CHAN_INFO_TAB_0,
 644                 AR_PHY_CHAN_INFO_TAB_1,
 645                 AR_PHY_CHAN_INFO_TAB_2,
 646         };
 647         s32 iq_res[6];
 648         s32 iqc_coeff[2];
 649         s32 i, j;
 650         u32 num_chains = 0;
 651
 652         for (i = 0; i < AR9300_MAX_CHAINS; i++) {
 653                 if (ah->txchainmask & (1 << i))
 654                         num_chains++;
 655         }
 656
 657         REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1,
 658                       AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT,
 659                       DELPT);
 660         REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_START,
 661                       AR_PHY_TX_IQCAL_START_DO_CAL,
 662                       AR_PHY_TX_IQCAL_START_DO_CAL);
 663
 664         if (!ath9k_hw_wait(ah, AR_PHY_TX_IQCAL_START,
 665                            AR_PHY_TX_IQCAL_START_DO_CAL,
 666                            0, AH_WAIT_TIMEOUT)) {
 667                 ath_print(common, ATH_DBG_CALIBRATE,
 668                           "Tx IQ Cal not complete.\n");
 669                 goto TX_IQ_CAL_FAILED;
 670         }
 671
 672         for (i = 0; i < num_chains; i++) {
 673                 ath_print(common, ATH_DBG_CALIBRATE,
 674                           "Doing Tx IQ Cal for chain %d.\n", i);
 675
 676                 if (REG_READ(ah, txiqcal_status[i]) &
 677                              AR_PHY_TX_IQCAL_STATUS_FAILED) {
 678                         ath_print(common, ATH_DBG_CALIBRATE,
 679                                   "Tx IQ Cal failed for chain %d.\n", i);
 680                         goto TX_IQ_CAL_FAILED;
 681                 }
 682
 683                 for (j = 0; j < 3; j++) {
 684                         u_int8_t idx = 2 * j,
 685                         offset = 4 * j;
 686
 687                         REG_RMW_FIELD(ah, AR_PHY_CHAN_INFO_MEMORY,
 688                                       AR_PHY_CHAN_INFO_TAB_S2_READ, 0);
 689
 690                         /* 32 bits */
 691                         iq_res[idx] = REG_READ(ah, chan_info_tab[i] + offset);
 692
 693                         REG_RMW_FIELD(ah, AR_PHY_CHAN_INFO_MEMORY,
 694                                       AR_PHY_CHAN_INFO_TAB_S2_READ, 1);
 695
 696                         /* 16 bits */
 697                         iq_res[idx+1] = 0xffff & REG_READ(ah,
 698                                                           chan_info_tab[i] +
 699                                                           offset);
 700
 701                         ath_print(common, ATH_DBG_CALIBRATE,
 702                                   "IQ RES[%d]=0x%x IQ_RES[%d]=0x%x\n",
 703                                   idx, iq_res[idx], idx+1, iq_res[idx+1]);
 704                 }
 705
 706                 if (!ar9003_hw_calc_iq_corr(ah, i, iq_res, iqc_coeff)) {
 707                         ath_print(common, ATH_DBG_CALIBRATE,
 708                                   "Failed in calculation of IQ correction.\n");
 709                         goto TX_IQ_CAL_FAILED;
 710                 }
 711
 712                 ath_print(common, ATH_DBG_CALIBRATE,
 713                           "IQ_COEFF[0] = 0x%x IQ_COEFF[1] = 0x%x\n",
 714                           iqc_coeff[0], iqc_coeff[1]);
 715
 716                 REG_RMW_FIELD(ah, tx_corr_coeff[i],
 717                               AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE,
 718                               iqc_coeff[0]);
 719                 REG_RMW_FIELD(ah, rx_corr[i],
 720                               AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF,
 721                               iqc_coeff[1] >> 7);
 722                 REG_RMW_FIELD(ah, rx_corr[i],
 723                               AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF,
 724                               iqc_coeff[1]);
 725         }
 726
 727         REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3,
 728                       AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN, 0x1);
 729         REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0,
 730                       AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN, 0x1);
 731
 732         return;
 733
 734 TX_IQ_CAL_FAILED:
 735         ath_print(common, ATH_DBG_CALIBRATE, "Tx IQ Cal failed\n");
 736 }
 737
 738 static bool ar9003_hw_init_cal(struct ath_hw *ah,
 739                                struct ath9k_channel *chan)
 740 {
 741         struct ath_common *common = ath9k_hw_common(ah);
 742
 743         /*
 744          * 0x7 = 0b111 , AR9003 needs to be configured for 3-chain mode before
 745          * running AGC/TxIQ cals
 746          */
 747         ar9003_hw_set_chain_masks(ah, 0x7, 0x7);
 748
 749         /* Do Tx IQ Calibration */
 750         ar9003_hw_tx_iq_cal(ah);
 751         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
 752         udelay(5);
 753         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 754
 755         /* Calibrate the AGC */
 756         REG_WRITE(ah, AR_PHY_AGC_CONTROL,
 757                   REG_READ(ah, AR_PHY_AGC_CONTROL) |
 758                   AR_PHY_AGC_CONTROL_CAL);
 759
 760         /* Poll for offset calibration complete */
 761         if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
 762                            0, AH_WAIT_TIMEOUT)) {
 763                 ath_print(common, ATH_DBG_CALIBRATE,
 764                           "offset calibration failed to "
 765                           "complete in 1ms; noisy environment?\n");
 766                 return false;
 767         }
 768
 769         /* Revert chainmasks to their original values before NF cal */
 770         ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
 771
 772         ath9k_hw_start_nfcal(ah, true);
 773
 774         /* Initialize list pointers */
 775         ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
 776
 777         if (ar9003_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
 778                 INIT_CAL(&ah->iq_caldata);
 779                 INSERT_CAL(ah, &ah->iq_caldata);
 780                 ath_print(common, ATH_DBG_CALIBRATE,
 781                           "enabling IQ Calibration.\n");
 782         }
 783
 784         if (ar9003_hw_iscal_supported(ah, TEMP_COMP_CAL)) {
 785                 INIT_CAL(&ah->tempCompCalData);
 786                 INSERT_CAL(ah, &ah->tempCompCalData);
 787                 ath_print(common, ATH_DBG_CALIBRATE,
 788                           "enabling Temperature Compensation Calibration.\n");
 789         }
 790
 791         /* Initialize current pointer to first element in list */
 792         ah->cal_list_curr = ah->cal_list;
 793
 794         if (ah->cal_list_curr)
 795                 ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
 796
 797         if (ah->caldata)
 798                 ah->caldata->CalValid = 0;
 799
 800         return true;
 801 }
 802
 803 void ar9003_hw_attach_calib_ops(struct ath_hw *ah)
 804 {
 805         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
 806         struct ath_hw_ops *ops = ath9k_hw_ops(ah);
 807
 808         priv_ops->init_cal_settings = ar9003_hw_init_cal_settings;
 809         priv_ops->init_cal = ar9003_hw_init_cal;
 810         priv_ops->setup_calibration = ar9003_hw_setup_calibration;
 811         priv_ops->iscal_supported = ar9003_hw_iscal_supported;
 812
 813         ops->calibrate = ar9003_hw_calibrate;
 814 }