drivers/net/wireless/ath/ath5k/reset.c

   1 /*
   2  * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
   3  * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
   4  * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
   5  * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
   6  * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
   7  *
   8  * Permission to use, copy, modify, and distribute this software for any
   9  * purpose with or without fee is hereby granted, provided that the above
  10  * copyright notice and this permission notice appear in all copies.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  13  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  14  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  15  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  16  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  17  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  18  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  19  *
  20  */
  21
  22 /*****************************\
  23   Reset functions and helpers
  24 \*****************************/
  25
  26 #include <asm/unaligned.h>
  27
  28 #include <linux/pci.h>          /* To determine if a card is pci-e */
  29 #include <linux/log2.h>
  30 #include <linux/platform_device.h>
  31 #include "ath5k.h"
  32 #include "reg.h"
  33 #include "base.h"
  34 #include "debug.h"
  35
  36
  37 /******************\
  38 * Helper functions *
  39 \******************/
  40
  41 /*
  42  * Check if a register write has been completed
  43  */
  44 int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
  45                               bool is_set)
  46 {
  47         int i;
  48         u32 data;
  49
  50         for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
  51                 data = ath5k_hw_reg_read(ah, reg);
  52                 if (is_set && (data & flag))
  53                         break;
  54                 else if ((data & flag) == val)
  55                         break;
  56                 udelay(15);
  57         }
  58
  59         return (i <= 0) ? -EAGAIN : 0;
  60 }
  61
  62
  63 /*************************\
  64 * Clock related functions *
  65 \*************************/
  66
  67 /**
  68  * ath5k_hw_htoclock - Translate usec to hw clock units
  69  *
  70  * @ah: The &struct ath5k_hw
  71  * @usec: value in microseconds
  72  */
  73 unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec)
  74 {
  75         struct ath_common *common = ath5k_hw_common(ah);
  76         return usec * common->clockrate;
  77 }
  78
  79 /**
  80  * ath5k_hw_clocktoh - Translate hw clock units to usec
  81  * @clock: value in hw clock units
  82  */
  83 unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock)
  84 {
  85         struct ath_common *common = ath5k_hw_common(ah);
  86         return clock / common->clockrate;
  87 }
  88
  89 /**
  90  * ath5k_hw_init_core_clock - Initialize core clock
  91  *
  92  * @ah The &struct ath5k_hw
  93  *
  94  * Initialize core clock parameters (usec, usec32, latencies etc).
  95  */
  96 static void ath5k_hw_init_core_clock(struct ath5k_hw *ah)
  97 {
  98         struct ieee80211_channel *channel = ah->ah_current_channel;
  99         struct ath_common *common = ath5k_hw_common(ah);
 100         u32 usec_reg, txlat, rxlat, usec, clock, sclock, txf2txs;
 101
 102         /*
 103          * Set core clock frequency
 104          */
 105         if (channel->hw_value & CHANNEL_5GHZ)
 106                 clock = 40; /* 802.11a */
 107         else if (channel->hw_value & CHANNEL_CCK)
 108                 clock = 22; /* 802.11b */
 109         else
 110                 clock = 44; /* 802.11g */
 111
 112         /* Use clock multiplier for non-default
 113          * bwmode */
 114         switch (ah->ah_bwmode) {
 115         case AR5K_BWMODE_40MHZ:
 116                 clock *= 2;
 117                 break;
 118         case AR5K_BWMODE_10MHZ:
 119                 clock /= 2;
 120                 break;
 121         case AR5K_BWMODE_5MHZ:
 122                 clock /= 4;
 123                 break;
 124         default:
 125                 break;
 126         }
 127
 128         common->clockrate = clock;
 129
 130         /*
 131          * Set USEC parameters
 132          */
 133         /* Set USEC counter on PCU*/
 134         usec = clock - 1;
 135         usec = AR5K_REG_SM(usec, AR5K_USEC_1);
 136
 137         /* Set usec duration on DCU */
 138         if (ah->ah_version != AR5K_AR5210)
 139                 AR5K_REG_WRITE_BITS(ah, AR5K_DCU_GBL_IFS_MISC,
 140                                         AR5K_DCU_GBL_IFS_MISC_USEC_DUR,
 141                                         clock);
 142
 143         /* Set 32MHz USEC counter */
 144         if ((ah->ah_radio == AR5K_RF5112) ||
 145                 (ah->ah_radio == AR5K_RF5413) ||
 146                 (ah->ah_radio == AR5K_RF2316) ||
 147                 (ah->ah_radio == AR5K_RF2317))
 148         /* Remain on 40MHz clock ? */
 149                 sclock = 40 - 1;
 150         else
 151                 sclock = 32 - 1;
 152         sclock = AR5K_REG_SM(sclock, AR5K_USEC_32);
 153
 154         /*
 155          * Set tx/rx latencies
 156          */
 157         usec_reg = ath5k_hw_reg_read(ah, AR5K_USEC_5211);
 158         txlat = AR5K_REG_MS(usec_reg, AR5K_USEC_TX_LATENCY_5211);
 159         rxlat = AR5K_REG_MS(usec_reg, AR5K_USEC_RX_LATENCY_5211);
 160
 161         /*
 162          * Set default Tx frame to Tx data start delay
 163          */
 164         txf2txs = AR5K_INIT_TXF2TXD_START_DEFAULT;
 165
 166         /*
 167          * 5210 initvals don't include usec settings
 168          * so we need to use magic values here for
 169          * tx/rx latencies
 170          */
 171         if (ah->ah_version == AR5K_AR5210) {
 172                 /* same for turbo */
 173                 txlat = AR5K_INIT_TX_LATENCY_5210;
 174                 rxlat = AR5K_INIT_RX_LATENCY_5210;
 175         }
 176
 177         if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
 178                 /* 5311 has different tx/rx latency masks
 179                  * from 5211, since we deal 5311 the same
 180                  * as 5211 when setting initvals, shift
 181                  * values here to their proper locations
 182                  *
 183                  * Note: Initvals indicate tx/rx/ latencies
 184                  * are the same for turbo mode */
 185                 txlat = AR5K_REG_SM(txlat, AR5K_USEC_TX_LATENCY_5210);
 186                 rxlat = AR5K_REG_SM(rxlat, AR5K_USEC_RX_LATENCY_5210);
 187         } else
 188         switch (ah->ah_bwmode) {
 189         case AR5K_BWMODE_10MHZ:
 190                 txlat = AR5K_REG_SM(txlat * 2,
 191                                 AR5K_USEC_TX_LATENCY_5211);
 192                 rxlat = AR5K_REG_SM(AR5K_INIT_RX_LAT_MAX,
 193                                 AR5K_USEC_RX_LATENCY_5211);
 194                 txf2txs = AR5K_INIT_TXF2TXD_START_DELAY_10MHZ;
 195                 break;
 196         case AR5K_BWMODE_5MHZ:
 197                 txlat = AR5K_REG_SM(txlat * 4,
 198                                 AR5K_USEC_TX_LATENCY_5211);
 199                 rxlat = AR5K_REG_SM(AR5K_INIT_RX_LAT_MAX,
 200                                 AR5K_USEC_RX_LATENCY_5211);
 201                 txf2txs = AR5K_INIT_TXF2TXD_START_DELAY_5MHZ;
 202                 break;
 203         case AR5K_BWMODE_40MHZ:
 204                 txlat = AR5K_INIT_TX_LAT_MIN;
 205                 rxlat = AR5K_REG_SM(rxlat / 2,
 206                                 AR5K_USEC_RX_LATENCY_5211);
 207                 txf2txs = AR5K_INIT_TXF2TXD_START_DEFAULT;
 208                 break;
 209         default:
 210                 break;
 211         }
 212
 213         usec_reg = (usec | sclock | txlat | rxlat);
 214         ath5k_hw_reg_write(ah, usec_reg, AR5K_USEC);
 215
 216         /* On 5112 set tx frane to tx data start delay */
 217         if (ah->ah_radio == AR5K_RF5112) {
 218                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL2,
 219                                         AR5K_PHY_RF_CTL2_TXF2TXD_START,
 220                                         txf2txs);
 221         }
 222 }
 223
 224 /*
 225  * If there is an external 32KHz crystal available, use it
 226  * as ref. clock instead of 32/40MHz clock and baseband clocks
 227  * to save power during sleep or restore normal 32/40MHz
 228  * operation.
 229  *
 230  * XXX: When operating on 32KHz certain PHY registers (27 - 31,
 231  *      123 - 127) require delay on access.
 232  */
 233 static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable)
 234 {
 235         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 236         u32 scal, spending;
 237
 238         /* Only set 32KHz settings if we have an external
 239          * 32KHz crystal present */
 240         if ((AR5K_EEPROM_HAS32KHZCRYSTAL(ee->ee_misc1) ||
 241         AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(ee->ee_misc1)) &&
 242         enable) {
 243
 244                 /* 1 usec/cycle */
 245                 AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, 1);
 246                 /* Set up tsf increment on each cycle */
 247                 AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 61);
 248
 249                 /* Set baseband sleep control registers
 250                  * and sleep control rate */
 251                 ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
 252
 253                 if ((ah->ah_radio == AR5K_RF5112) ||
 254                 (ah->ah_radio == AR5K_RF5413) ||
 255                 (ah->ah_radio == AR5K_RF2316) ||
 256                 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
 257                         spending = 0x14;
 258                 else
 259                         spending = 0x18;
 260                 ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
 261
 262                 if ((ah->ah_radio == AR5K_RF5112) ||
 263                 (ah->ah_radio == AR5K_RF5413) ||
 264                 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
 265                         ath5k_hw_reg_write(ah, 0x26, AR5K_PHY_SLMT);
 266                         ath5k_hw_reg_write(ah, 0x0d, AR5K_PHY_SCAL);
 267                         ath5k_hw_reg_write(ah, 0x07, AR5K_PHY_SCLOCK);
 268                         ath5k_hw_reg_write(ah, 0x3f, AR5K_PHY_SDELAY);
 269                         AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
 270                                 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x02);
 271                 } else {
 272                         ath5k_hw_reg_write(ah, 0x0a, AR5K_PHY_SLMT);
 273                         ath5k_hw_reg_write(ah, 0x0c, AR5K_PHY_SCAL);
 274                         ath5k_hw_reg_write(ah, 0x03, AR5K_PHY_SCLOCK);
 275                         ath5k_hw_reg_write(ah, 0x20, AR5K_PHY_SDELAY);
 276                         AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
 277                                 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x03);
 278                 }
 279
 280                 /* Enable sleep clock operation */
 281                 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG,
 282                                 AR5K_PCICFG_SLEEP_CLOCK_EN);
 283
 284         } else {
 285
 286                 /* Disable sleep clock operation and
 287                  * restore default parameters */
 288                 AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG,
 289                                 AR5K_PCICFG_SLEEP_CLOCK_EN);
 290
 291                 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
 292                                 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0);
 293
 294                 /* Set DAC/ADC delays */
 295                 ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
 296                 ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT);
 297
 298                 if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))
 299                         scal = AR5K_PHY_SCAL_32MHZ_2417;
 300                 else if (ee->ee_is_hb63)
 301                         scal = AR5K_PHY_SCAL_32MHZ_HB63;
 302                 else
 303                         scal = AR5K_PHY_SCAL_32MHZ;
 304                 ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL);
 305
 306                 ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK);
 307                 ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY);
 308
 309                 if ((ah->ah_radio == AR5K_RF5112) ||
 310                 (ah->ah_radio == AR5K_RF5413) ||
 311                 (ah->ah_radio == AR5K_RF2316) ||
 312                 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
 313                         spending = 0x14;
 314                 else
 315                         spending = 0x18;
 316                 ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
 317
 318                 /* Set up tsf increment on each cycle */
 319                 AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 1);
 320         }
 321 }
 322
 323
 324 /*********************\
 325 * Reset/Sleep control *
 326 \*********************/
 327
 328 /*
 329  * Reset chipset
 330  */
 331 static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
 332 {
 333         int ret;
 334         u32 mask = val ? val : ~0U;
 335
 336         /* Read-and-clear RX Descriptor Pointer*/
 337         ath5k_hw_reg_read(ah, AR5K_RXDP);
 338
 339         /*
 340          * Reset the device and wait until success
 341          */
 342         ath5k_hw_reg_write(ah, val, AR5K_RESET_CTL);
 343
 344         /* Wait at least 128 PCI clocks */
 345         udelay(15);
 346
 347         if (ah->ah_version == AR5K_AR5210) {
 348                 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
 349                         | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY;
 350                 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
 351                         | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY;
 352         } else {
 353                 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
 354                 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
 355         }
 356
 357         ret = ath5k_hw_register_timeout(ah, AR5K_RESET_CTL, mask, val, false);
 358
 359         /*
 360          * Reset configuration register (for hw byte-swap). Note that this
 361          * is only set for big endian. We do the necessary magic in
 362          * AR5K_INIT_CFG.
 363          */
 364         if ((val & AR5K_RESET_CTL_PCU) == 0)
 365                 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
 366
 367         return ret;
 368 }
 369
 370 /*
 371  * Reset AHB chipset
 372  * AR5K_RESET_CTL_PCU flag resets WMAC
 373  * AR5K_RESET_CTL_BASEBAND flag resets WBB
 374  */
 375 static int ath5k_hw_wisoc_reset(struct ath5k_hw *ah, u32 flags)
 376 {
 377         u32 mask = flags ? flags : ~0U;
 378         volatile u32 *reg;
 379         u32 regval;
 380         u32 val = 0;
 381
 382         /* ah->ah_mac_srev is not available at this point yet */
 383         if (ah->ah_sc->devid >= AR5K_SREV_AR2315_R6) {
 384                 reg = (u32 *) AR5K_AR2315_RESET;
 385                 if (mask & AR5K_RESET_CTL_PCU)
 386                         val |= AR5K_AR2315_RESET_WMAC;
 387                 if (mask & AR5K_RESET_CTL_BASEBAND)
 388                         val |= AR5K_AR2315_RESET_BB_WARM;
 389         } else {
 390                 reg = (u32 *) AR5K_AR5312_RESET;
 391                 if (to_platform_device(ah->ah_sc->dev)->id == 0) {
 392                         if (mask & AR5K_RESET_CTL_PCU)
 393                                 val |= AR5K_AR5312_RESET_WMAC0;
 394                         if (mask & AR5K_RESET_CTL_BASEBAND)
 395                                 val |= AR5K_AR5312_RESET_BB0_COLD |
 396                                        AR5K_AR5312_RESET_BB0_WARM;
 397                 } else {
 398                         if (mask & AR5K_RESET_CTL_PCU)
 399                                 val |= AR5K_AR5312_RESET_WMAC1;
 400                         if (mask & AR5K_RESET_CTL_BASEBAND)
 401                                 val |= AR5K_AR5312_RESET_BB1_COLD |
 402                                        AR5K_AR5312_RESET_BB1_WARM;
 403                 }
 404         }
 405
 406         /* Put BB/MAC into reset */
 407         regval = __raw_readl(reg);
 408         __raw_writel(regval | val, reg);
 409         regval = __raw_readl(reg);
 410         udelay(100);
 411
 412         /* Bring BB/MAC out of reset */
 413         __raw_writel(regval & ~val, reg);
 414         regval = __raw_readl(reg);
 415
 416         /*
 417          * Reset configuration register (for hw byte-swap). Note that this
 418          * is only set for big endian. We do the necessary magic in
 419          * AR5K_INIT_CFG.
 420          */
 421         if ((flags & AR5K_RESET_CTL_PCU) == 0)
 422                 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
 423
 424         return 0;
 425 }
 426
 427
 428 /*
 429  * Sleep control
 430  */
 431 static int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
 432                               bool set_chip, u16 sleep_duration)
 433 {
 434         unsigned int i;
 435         u32 staid, data;
 436
 437         staid = ath5k_hw_reg_read(ah, AR5K_STA_ID1);
 438
 439         switch (mode) {
 440         case AR5K_PM_AUTO:
 441                 staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA;
 442                 /* fallthrough */
 443         case AR5K_PM_NETWORK_SLEEP:
 444                 if (set_chip)
 445                         ath5k_hw_reg_write(ah,
 446                                 AR5K_SLEEP_CTL_SLE_ALLOW |
 447                                 sleep_duration,
 448                                 AR5K_SLEEP_CTL);
 449
 450                 staid |= AR5K_STA_ID1_PWR_SV;
 451                 break;
 452
 453         case AR5K_PM_FULL_SLEEP:
 454                 if (set_chip)
 455                         ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_SLP,
 456                                 AR5K_SLEEP_CTL);
 457
 458                 staid |= AR5K_STA_ID1_PWR_SV;
 459                 break;
 460
 461         case AR5K_PM_AWAKE:
 462
 463                 staid &= ~AR5K_STA_ID1_PWR_SV;
 464
 465                 if (!set_chip)
 466                         goto commit;
 467
 468                 data = ath5k_hw_reg_read(ah, AR5K_SLEEP_CTL);
 469
 470                 /* If card is down we 'll get 0xffff... so we
 471                  * need to clean this up before we write the register
 472                  */
 473                 if (data & 0xffc00000)
 474                         data = 0;
 475                 else
 476                         /* Preserve sleep duration etc */
 477                         data = data & ~AR5K_SLEEP_CTL_SLE;
 478
 479                 ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE,
 480                                                         AR5K_SLEEP_CTL);
 481                 udelay(15);
 482
 483                 for (i = 200; i > 0; i--) {
 484                         /* Check if the chip did wake up */
 485                         if ((ath5k_hw_reg_read(ah, AR5K_PCICFG) &
 486                                         AR5K_PCICFG_SPWR_DN) == 0)
 487                                 break;
 488
 489                         /* Wait a bit and retry */
 490                         udelay(50);
 491                         ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE,
 492                                                         AR5K_SLEEP_CTL);
 493                 }
 494
 495                 /* Fail if the chip didn't wake up */
 496                 if (i == 0)
 497                         return -EIO;
 498
 499                 break;
 500
 501         default:
 502                 return -EINVAL;
 503         }
 504
 505 commit:
 506         ath5k_hw_reg_write(ah, staid, AR5K_STA_ID1);
 507
 508         return 0;
 509 }
 510
 511 /*
 512  * Put device on hold
 513  *
 514  * Put MAC and Baseband on warm reset and
 515  * keep that state (don't clean sleep control
 516  * register). After this MAC and Baseband are
 517  * disabled and a full reset is needed to come
 518  * back. This way we save as much power as possible
 519  * without putting the card on full sleep.
 520  */
 521 int ath5k_hw_on_hold(struct ath5k_hw *ah)
 522 {
 523         struct pci_dev *pdev = ah->ah_sc->pdev;
 524         u32 bus_flags;
 525         int ret;
 526
 527         if (ath5k_get_bus_type(ah) == ATH_AHB)
 528                 return 0;
 529
 530         /* Make sure device is awake */
 531         ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
 532         if (ret) {
 533                 ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n");
 534                 return ret;
 535         }
 536
 537         /*
 538          * Put chipset on warm reset...
 539          *
 540          * Note: putting PCI core on warm reset on PCI-E cards
 541          * results card to hang and always return 0xffff... so
 542          * we ingore that flag for PCI-E cards. On PCI cards
 543          * this flag gets cleared after 64 PCI clocks.
 544          */
 545         bus_flags = (pdev && pci_is_pcie(pdev)) ? 0 : AR5K_RESET_CTL_PCI;
 546
 547         if (ah->ah_version == AR5K_AR5210) {
 548                 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
 549                         AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
 550                         AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
 551                         mdelay(2);
 552         } else {
 553                 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
 554                         AR5K_RESET_CTL_BASEBAND | bus_flags);
 555         }
 556
 557         if (ret) {
 558                 ATH5K_ERR(ah->ah_sc, "failed to put device on warm reset\n");
 559                 return -EIO;
 560         }
 561
 562         /* ...wakeup again!*/
 563         ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
 564         if (ret) {
 565                 ATH5K_ERR(ah->ah_sc, "failed to put device on hold\n");
 566                 return ret;
 567         }
 568
 569         return ret;
 570 }
 571
 572 /*
 573  * Bring up MAC + PHY Chips and program PLL
 574  */
 575 int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
 576 {
 577         struct pci_dev *pdev = ah->ah_sc->pdev;
 578         u32 turbo, mode, clock, bus_flags;
 579         int ret;
 580
 581         turbo = 0;
 582         mode = 0;
 583         clock = 0;
 584
 585         if ((ath5k_get_bus_type(ah) != ATH_AHB) || !initial) {
 586                 /* Wakeup the device */
 587                 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
 588                 if (ret) {
 589                         ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n");
 590                         return ret;
 591                 }
 592         }
 593
 594         /*
 595          * Put chipset on warm reset...
 596          *
 597          * Note: putting PCI core on warm reset on PCI-E cards
 598          * results card to hang and always return 0xffff... so
 599          * we ingore that flag for PCI-E cards. On PCI cards
 600          * this flag gets cleared after 64 PCI clocks.
 601          */
 602         bus_flags = (pdev && pci_is_pcie(pdev)) ? 0 : AR5K_RESET_CTL_PCI;
 603
 604         if (ah->ah_version == AR5K_AR5210) {
 605                 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
 606                         AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
 607                         AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
 608                         mdelay(2);
 609         } else {
 610                 if (ath5k_get_bus_type(ah) == ATH_AHB)
 611                         ret = ath5k_hw_wisoc_reset(ah, AR5K_RESET_CTL_PCU |
 612                                 AR5K_RESET_CTL_BASEBAND);
 613                 else
 614                         ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
 615                                 AR5K_RESET_CTL_BASEBAND | bus_flags);
 616         }
 617
 618         if (ret) {
 619                 ATH5K_ERR(ah->ah_sc, "failed to reset the MAC Chip\n");
 620                 return -EIO;
 621         }
 622
 623         /* ...wakeup again!...*/
 624         ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
 625         if (ret) {
 626                 ATH5K_ERR(ah->ah_sc, "failed to resume the MAC Chip\n");
 627                 return ret;
 628         }
 629
 630         /* ...reset configuration regiter on Wisoc ...
 631          * ...clear reset control register and pull device out of
 632          * warm reset on others */
 633         if (ath5k_get_bus_type(ah) == ATH_AHB)
 634                 ret = ath5k_hw_wisoc_reset(ah, 0);
 635         else
 636                 ret = ath5k_hw_nic_reset(ah, 0);
 637
 638         if (ret) {
 639                 ATH5K_ERR(ah->ah_sc, "failed to warm reset the MAC Chip\n");
 640                 return -EIO;
 641         }
 642
 643         /* On initialization skip PLL programming since we don't have
 644          * a channel / mode set yet */
 645         if (initial)
 646                 return 0;
 647
 648         if (ah->ah_version != AR5K_AR5210) {
 649                 /*
 650                  * Get channel mode flags
 651                  */
 652
 653                 if (ah->ah_radio >= AR5K_RF5112) {
 654                         mode = AR5K_PHY_MODE_RAD_RF5112;
 655                         clock = AR5K_PHY_PLL_RF5112;
 656                 } else {
 657                         mode = AR5K_PHY_MODE_RAD_RF5111;        /*Zero*/
 658                         clock = AR5K_PHY_PLL_RF5111;            /*Zero*/
 659                 }
 660
 661                 if (flags & CHANNEL_2GHZ) {
 662                         mode |= AR5K_PHY_MODE_FREQ_2GHZ;
 663                         clock |= AR5K_PHY_PLL_44MHZ;
 664
 665                         if (flags & CHANNEL_CCK) {
 666                                 mode |= AR5K_PHY_MODE_MOD_CCK;
 667                         } else if (flags & CHANNEL_OFDM) {
 668                                 /* XXX Dynamic OFDM/CCK is not supported by the
 669                                  * AR5211 so we set MOD_OFDM for plain g (no
 670                                  * CCK headers) operation. We need to test
 671                                  * this, 5211 might support ofdm-only g after
 672                                  * all, there are also initial register values
 673                                  * in the code for g mode (see initvals.c).
 674                                  */
 675                                 if (ah->ah_version == AR5K_AR5211)
 676                                         mode |= AR5K_PHY_MODE_MOD_OFDM;
 677                                 else
 678                                         mode |= AR5K_PHY_MODE_MOD_DYN;
 679                         } else {
 680                                 ATH5K_ERR(ah->ah_sc,
 681                                         "invalid radio modulation mode\n");
 682                                 return -EINVAL;
 683                         }
 684                 } else if (flags & CHANNEL_5GHZ) {
 685                         mode |= AR5K_PHY_MODE_FREQ_5GHZ;
 686
 687                         /* Different PLL setting for 5413 */
 688                         if (ah->ah_radio == AR5K_RF5413)
 689                                 clock = AR5K_PHY_PLL_40MHZ_5413;
 690                         else
 691                                 clock |= AR5K_PHY_PLL_40MHZ;
 692
 693                         if (flags & CHANNEL_OFDM)
 694                                 mode |= AR5K_PHY_MODE_MOD_OFDM;
 695                         else {
 696                                 ATH5K_ERR(ah->ah_sc,
 697                                         "invalid radio modulation mode\n");
 698                                 return -EINVAL;
 699                         }
 700                 } else {
 701                         ATH5K_ERR(ah->ah_sc, "invalid radio frequency mode\n");
 702                         return -EINVAL;
 703                 }
 704
 705                 /*XXX: Can bwmode be used with dynamic mode ?
 706                  * (I don't think it supports 44MHz) */
 707                 /* On 2425 initvals TURBO_SHORT is not pressent */
 708                 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) {
 709                         turbo = AR5K_PHY_TURBO_MODE |
 710                                 (ah->ah_radio == AR5K_RF2425) ? 0 :
 711                                 AR5K_PHY_TURBO_SHORT;
 712                 } else if (ah->ah_bwmode != AR5K_BWMODE_DEFAULT) {
 713                         if (ah->ah_radio == AR5K_RF5413) {
 714                                 mode |= (ah->ah_bwmode == AR5K_BWMODE_10MHZ) ?
 715                                         AR5K_PHY_MODE_HALF_RATE :
 716                                         AR5K_PHY_MODE_QUARTER_RATE;
 717                         } else if (ah->ah_version == AR5K_AR5212) {
 718                                 clock |= (ah->ah_bwmode == AR5K_BWMODE_10MHZ) ?
 719                                         AR5K_PHY_PLL_HALF_RATE :
 720                                         AR5K_PHY_PLL_QUARTER_RATE;
 721                         }
 722                 }
 723
 724         } else { /* Reset the device */
 725
 726                 /* ...enable Atheros turbo mode if requested */
 727                 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
 728                         ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE,
 729                                         AR5K_PHY_TURBO);
 730         }
 731
 732         if (ah->ah_version != AR5K_AR5210) {
 733
 734                 /* ...update PLL if needed */
 735                 if (ath5k_hw_reg_read(ah, AR5K_PHY_PLL) != clock) {
 736                         ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL);
 737                         udelay(300);
 738                 }
 739
 740                 /* ...set the PHY operating mode */
 741                 ath5k_hw_reg_write(ah, mode, AR5K_PHY_MODE);
 742                 ath5k_hw_reg_write(ah, turbo, AR5K_PHY_TURBO);
 743         }
 744
 745         return 0;
 746 }
 747
 748
 749 /**************************************\
 750 * Post-initvals register modifications *
 751 \**************************************/
 752
 753 /* TODO: Half/Quarter rate */
 754 static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,
 755                                 struct ieee80211_channel *channel)
 756 {
 757         if (ah->ah_version == AR5K_AR5212 &&
 758             ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
 759
 760                 /* Setup ADC control */
 761                 ath5k_hw_reg_write(ah,
 762                                 (AR5K_REG_SM(2,
 763                                 AR5K_PHY_ADC_CTL_INBUFGAIN_OFF) |
 764                                 AR5K_REG_SM(2,
 765                                 AR5K_PHY_ADC_CTL_INBUFGAIN_ON) |
 766                                 AR5K_PHY_ADC_CTL_PWD_DAC_OFF |
 767                                 AR5K_PHY_ADC_CTL_PWD_ADC_OFF),
 768                                 AR5K_PHY_ADC_CTL);
 769
 770
 771
 772                 /* Disable barker RSSI threshold */
 773                 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_DAG_CCK_CTL,
 774                                 AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR);
 775
 776                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DAG_CCK_CTL,
 777                         AR5K_PHY_DAG_CCK_CTL_RSSI_THR, 2);
 778
 779                 /* Set the mute mask */
 780                 ath5k_hw_reg_write(ah, 0x0000000f, AR5K_SEQ_MASK);
 781         }
 782
 783         /* Clear PHY_BLUETOOTH to allow RX_CLEAR line debug */
 784         if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212B)
 785                 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BLUETOOTH);
 786
 787         /* Enable DCU double buffering */
 788         if (ah->ah_phy_revision > AR5K_SREV_PHY_5212B)
 789                 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
 790                                 AR5K_TXCFG_DCU_DBL_BUF_DIS);
 791
 792         /* Set fast ADC */
 793         if ((ah->ah_radio == AR5K_RF5413) ||
 794                 (ah->ah_radio == AR5K_RF2317) ||
 795                 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
 796                 u32 fast_adc = true;
 797
 798                 if (channel->center_freq == 2462 ||
 799                 channel->center_freq == 2467)
 800                         fast_adc = 0;
 801
 802                 /* Only update if needed */
 803                 if (ath5k_hw_reg_read(ah, AR5K_PHY_FAST_ADC) != fast_adc)
 804                                 ath5k_hw_reg_write(ah, fast_adc,
 805                                                 AR5K_PHY_FAST_ADC);
 806         }
 807
 808         /* Fix for first revision of the RF5112 RF chipset */
 809         if (ah->ah_radio == AR5K_RF5112 &&
 810                         ah->ah_radio_5ghz_revision <
 811                         AR5K_SREV_RAD_5112A) {
 812                 u32 data;
 813                 ath5k_hw_reg_write(ah, AR5K_PHY_CCKTXCTL_WORLD,
 814                                 AR5K_PHY_CCKTXCTL);
 815                 if (channel->hw_value & CHANNEL_5GHZ)
 816                         data = 0xffb81020;
 817                 else
 818                         data = 0xffb80d20;
 819                 ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL);
 820         }
 821
 822         if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
 823                 /* Clear QCU/DCU clock gating register */
 824                 ath5k_hw_reg_write(ah, 0, AR5K_QCUDCU_CLKGT);
 825                 /* Set DAC/ADC delays */
 826                 ath5k_hw_reg_write(ah, AR5K_PHY_SCAL_32MHZ_5311,
 827                                                 AR5K_PHY_SCAL);
 828                 /* Enable PCU FIFO corruption ECO */
 829                 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211,
 830                                         AR5K_DIAG_SW_ECO_ENABLE);
 831         }
 832
 833         if (ah->ah_bwmode) {
 834                 /* Increase PHY switch and AGC settling time
 835                  * on turbo mode (ath5k_hw_commit_eeprom_settings
 836                  * will override settling time if available) */
 837                 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) {
 838
 839                         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
 840                                                 AR5K_PHY_SETTLING_AGC,
 841                                                 AR5K_AGC_SETTLING_TURBO);
 842
 843                         /* XXX: Initvals indicate we only increase
 844                          * switch time on AR5212, 5211 and 5210
 845                          * only change agc time (bug?) */
 846                         if (ah->ah_version == AR5K_AR5212)
 847                                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
 848                                                 AR5K_PHY_SETTLING_SWITCH,
 849                                                 AR5K_SWITCH_SETTLING_TURBO);
 850
 851                         if (ah->ah_version == AR5K_AR5210) {
 852                                 /* Set Frame Control Register */
 853                                 ath5k_hw_reg_write(ah,
 854                                         (AR5K_PHY_FRAME_CTL_INI |
 855                                         AR5K_PHY_TURBO_MODE |
 856                                         AR5K_PHY_TURBO_SHORT | 0x2020),
 857                                         AR5K_PHY_FRAME_CTL_5210);
 858                         }
 859                 /* On 5413 PHY force window length for half/quarter rate*/
 860                 } else if ((ah->ah_mac_srev >= AR5K_SREV_AR5424) &&
 861                 (ah->ah_mac_srev <= AR5K_SREV_AR5414)) {
 862                         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL_5211,
 863                                                 AR5K_PHY_FRAME_CTL_WIN_LEN,
 864                                                 3);
 865                 }
 866         } else if (ah->ah_version == AR5K_AR5210) {
 867                 /* Set Frame Control Register for normal operation */
 868                 ath5k_hw_reg_write(ah, (AR5K_PHY_FRAME_CTL_INI | 0x1020),
 869                                                 AR5K_PHY_FRAME_CTL_5210);
 870         }
 871 }
 872
 873 static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah,
 874                 struct ieee80211_channel *channel)
 875 {
 876         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 877         s16 cck_ofdm_pwr_delta;
 878         u8 ee_mode;
 879
 880         /* TODO: Add support for AR5210 EEPROM */
 881         if (ah->ah_version == AR5K_AR5210)
 882                 return;
 883
 884         ee_mode = ath5k_eeprom_mode_from_channel(channel);
 885
 886         /* Adjust power delta for channel 14 */
 887         if (channel->center_freq == 2484)
 888                 cck_ofdm_pwr_delta =
 889                         ((ee->ee_cck_ofdm_power_delta -
 890                         ee->ee_scaled_cck_delta) * 2) / 10;
 891         else
 892                 cck_ofdm_pwr_delta =
 893                         (ee->ee_cck_ofdm_power_delta * 2) / 10;
 894
 895         /* Set CCK to OFDM power delta on tx power
 896          * adjustment register */
 897         if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
 898                 if (channel->hw_value == CHANNEL_G)
 899                         ath5k_hw_reg_write(ah,
 900                         AR5K_REG_SM((ee->ee_cck_ofdm_gain_delta * -1),
 901                                 AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA) |
 902                         AR5K_REG_SM((cck_ofdm_pwr_delta * -1),
 903                                 AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX),
 904                                 AR5K_PHY_TX_PWR_ADJ);
 905                 else
 906                         ath5k_hw_reg_write(ah, 0, AR5K_PHY_TX_PWR_ADJ);
 907         } else {
 908                 /* For older revs we scale power on sw during tx power
 909                  * setup */
 910                 ah->ah_txpower.txp_cck_ofdm_pwr_delta = cck_ofdm_pwr_delta;
 911                 ah->ah_txpower.txp_cck_ofdm_gainf_delta =
 912                                                 ee->ee_cck_ofdm_gain_delta;
 913         }
 914
 915         /* XXX: necessary here? is called from ath5k_hw_set_antenna_mode()
 916          * too */
 917         ath5k_hw_set_antenna_switch(ah, ee_mode);
 918
 919         /* Noise floor threshold */
 920         ath5k_hw_reg_write(ah,
 921                 AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]),
 922                 AR5K_PHY_NFTHRES);
 923
 924         if ((ah->ah_bwmode == AR5K_BWMODE_40MHZ) &&
 925         (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0)) {
 926                 /* Switch settling time (Turbo) */
 927                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
 928                                 AR5K_PHY_SETTLING_SWITCH,
 929                                 ee->ee_switch_settling_turbo[ee_mode]);
 930
 931                 /* Tx/Rx attenuation (Turbo) */
 932                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN,
 933                                 AR5K_PHY_GAIN_TXRX_ATTEN,
 934                                 ee->ee_atn_tx_rx_turbo[ee_mode]);
 935
 936                 /* ADC/PGA desired size (Turbo) */
 937                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
 938                                 AR5K_PHY_DESIRED_SIZE_ADC,
 939                                 ee->ee_adc_desired_size_turbo[ee_mode]);
 940
 941                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
 942                                 AR5K_PHY_DESIRED_SIZE_PGA,
 943                                 ee->ee_pga_desired_size_turbo[ee_mode]);
 944
 945                 /* Tx/Rx margin (Turbo) */
 946                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
 947                                 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
 948                                 ee->ee_margin_tx_rx_turbo[ee_mode]);
 949
 950         } else {
 951                 /* Switch settling time */
 952                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
 953                                 AR5K_PHY_SETTLING_SWITCH,
 954                                 ee->ee_switch_settling[ee_mode]);
 955
 956                 /* Tx/Rx attenuation */
 957                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN,
 958                                 AR5K_PHY_GAIN_TXRX_ATTEN,
 959                                 ee->ee_atn_tx_rx[ee_mode]);
 960
 961                 /* ADC/PGA desired size */
 962                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
 963                                 AR5K_PHY_DESIRED_SIZE_ADC,
 964                                 ee->ee_adc_desired_size[ee_mode]);
 965
 966                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
 967                                 AR5K_PHY_DESIRED_SIZE_PGA,
 968                                 ee->ee_pga_desired_size[ee_mode]);
 969
 970                 /* Tx/Rx margin */
 971                 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
 972                         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
 973                                 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
 974                                 ee->ee_margin_tx_rx[ee_mode]);
 975         }
 976
 977         /* XPA delays */
 978         ath5k_hw_reg_write(ah,
 979                 (ee->ee_tx_end2xpa_disable[ee_mode] << 24) |
 980                 (ee->ee_tx_end2xpa_disable[ee_mode] << 16) |
 981                 (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) |
 982                 (ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY_RF_CTL4);
 983
 984         /* XLNA delay */
 985         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL3,
 986                         AR5K_PHY_RF_CTL3_TXE2XLNA_ON,
 987                         ee->ee_tx_end2xlna_enable[ee_mode]);
 988
 989         /* Thresh64 (ANI) */
 990         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_NF,
 991                         AR5K_PHY_NF_THRESH62,
 992                         ee->ee_thr_62[ee_mode]);
 993
 994         /* False detect backoff for channels
 995          * that have spur noise. Write the new
 996          * cyclic power RSSI threshold. */
 997         if (ath5k_hw_chan_has_spur_noise(ah, channel))
 998                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,
 999                                 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1,
1000                                 AR5K_INIT_CYCRSSI_THR1 +
1001                                 ee->ee_false_detect[ee_mode]);
1002         else
1003                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,
1004                                 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1,
1005                                 AR5K_INIT_CYCRSSI_THR1);
1006
1007         /* I/Q correction (set enable bit last to match HAL sources) */
1008         /* TODO: Per channel i/q infos ? */
1009         if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
1010                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF,
1011                             ee->ee_i_cal[ee_mode]);
1012                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF,
1013                             ee->ee_q_cal[ee_mode]);
1014                 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE);
1015         }
1016
1017         /* Heavy clipping -disable for now */
1018         if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_1)
1019                 ath5k_hw_reg_write(ah, 0, AR5K_PHY_HEAVY_CLIP_ENABLE);
1020 }
1021
1022
1023 /*********************\
1024 * Main reset function *
1025 \*********************/
1026
1027 int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1028                 struct ieee80211_channel *channel, bool fast, bool skip_pcu)
1029 {
1030         u32 s_seq[10], s_led[3], tsf_up, tsf_lo;
1031         u8 mode;
1032         int i, ret;
1033
1034         tsf_up = 0;
1035         tsf_lo = 0;
1036         mode = 0;
1037
1038         /*
1039          * Sanity check for fast flag
1040          * Fast channel change only available
1041          * on AR2413/AR5413.
1042          */
1043         if (fast && (ah->ah_radio != AR5K_RF2413) &&
1044         (ah->ah_radio != AR5K_RF5413))
1045                 fast = 0;
1046
1047         /* Disable sleep clock operation
1048          * to avoid register access delay on certain
1049          * PHY registers */
1050         if (ah->ah_version == AR5K_AR5212)
1051                 ath5k_hw_set_sleep_clock(ah, false);
1052
1053         /*
1054          * Stop PCU
1055          */
1056         ath5k_hw_stop_rx_pcu(ah);
1057
1058         /*
1059          * Stop DMA
1060          *
1061          * Note: If DMA didn't stop continue
1062          * since only a reset will fix it.
1063          */
1064         ret = ath5k_hw_dma_stop(ah);
1065
1066         /* RF Bus grant won't work if we have pending
1067          * frames */
1068         if (ret && fast) {
1069                 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_RESET,
1070                         "DMA didn't stop, falling back to normal reset\n");
1071                 fast = 0;
1072                 /* Non fatal, just continue with
1073                  * normal reset */
1074                 ret = 0;
1075         }
1076
1077         switch (channel->hw_value & CHANNEL_MODES) {
1078         case CHANNEL_A:
1079                 mode = AR5K_MODE_11A;
1080                 break;
1081         case CHANNEL_G:
1082
1083                 if (ah->ah_version <= AR5K_AR5211) {
1084                         ATH5K_ERR(ah->ah_sc,
1085                                 "G mode not available on 5210/5211");
1086                         return -EINVAL;
1087                 }
1088
1089                 mode = AR5K_MODE_11G;
1090                 break;
1091         case CHANNEL_B:
1092
1093                 if (ah->ah_version < AR5K_AR5211) {
1094                         ATH5K_ERR(ah->ah_sc,
1095                                 "B mode not available on 5210");
1096                         return -EINVAL;
1097                 }
1098
1099                 mode = AR5K_MODE_11B;
1100                 break;
1101         case CHANNEL_XR:
1102                 if (ah->ah_version == AR5K_AR5211) {
1103                         ATH5K_ERR(ah->ah_sc,
1104                                 "XR mode not available on 5211");
1105                         return -EINVAL;
1106                 }
1107                 mode = AR5K_MODE_XR;
1108                 break;
1109         default:
1110                 ATH5K_ERR(ah->ah_sc,
1111                         "invalid channel: %d\n", channel->center_freq);
1112                 return -EINVAL;
1113         }
1114
1115         /*
1116          * If driver requested fast channel change and DMA has stopped
1117          * go on. If it fails continue with a normal reset.
1118          */
1119         if (fast) {
1120                 ret = ath5k_hw_phy_init(ah, channel, mode, true);
1121                 if (ret) {
1122                         ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_RESET,
1123                                 "fast chan change failed, falling back to normal reset\n");
1124                         /* Non fatal, can happen eg.
1125                          * on mode change */
1126                         ret = 0;
1127                 } else {
1128                         ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_RESET,
1129                                 "fast chan change successful\n");
1130                         return 0;
1131                 }
1132         }
1133
1134         /*
1135          * Save some registers before a reset
1136          */
1137         if (ah->ah_version != AR5K_AR5210) {
1138                 /*
1139                  * Save frame sequence count
1140                  * For revs. after Oahu, only save
1141                  * seq num for DCU 0 (Global seq num)
1142                  */
1143                 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
1144
1145                         for (i = 0; i < 10; i++)
1146                                 s_seq[i] = ath5k_hw_reg_read(ah,
1147                                         AR5K_QUEUE_DCU_SEQNUM(i));
1148
1149                 } else {
1150                         s_seq[0] = ath5k_hw_reg_read(ah,
1151                                         AR5K_QUEUE_DCU_SEQNUM(0));
1152                 }
1153
1154                 /* TSF accelerates on AR5211 during reset
1155                  * As a workaround save it here and restore
1156                  * it later so that it's back in time after
1157                  * reset. This way it'll get re-synced on the
1158                  * next beacon without breaking ad-hoc.
1159                  *
1160                  * On AR5212 TSF is almost preserved across a
1161                  * reset so it stays back in time anyway and
1162                  * we don't have to save/restore it.
1163                  *
1164                  * XXX: Since this breaks power saving we have
1165                  * to disable power saving until we receive the
1166                  * next beacon, so we can resync beacon timers */
1167                 if (ah->ah_version == AR5K_AR5211) {
1168                         tsf_up = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
1169                         tsf_lo = ath5k_hw_reg_read(ah, AR5K_TSF_L32);
1170                 }
1171         }
1172
1173
1174         /*GPIOs*/
1175         s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) &
1176                                         AR5K_PCICFG_LEDSTATE;
1177         s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR);
1178         s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO);
1179
1180
1181         /*
1182          * Since we are going to write rf buffer
1183          * check if we have any pending gain_F
1184          * optimization settings
1185          */
1186         if (ah->ah_version == AR5K_AR5212 &&
1187         (ah->ah_radio <= AR5K_RF5112)) {
1188                 if (!fast && ah->ah_rf_banks != NULL)
1189                                 ath5k_hw_gainf_calibrate(ah);
1190         }
1191
1192         /* Wakeup the device */
1193         ret = ath5k_hw_nic_wakeup(ah, channel->hw_value, false);
1194         if (ret)
1195                 return ret;
1196
1197         /* PHY access enable */
1198         if (ah->ah_mac_srev >= AR5K_SREV_AR5211)
1199                 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
1200         else
1201                 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ | 0x40,
1202                                                         AR5K_PHY(0));
1203
1204         /* Write initial settings */
1205         ret = ath5k_hw_write_initvals(ah, mode, skip_pcu);
1206         if (ret)
1207                 return ret;
1208
1209         /* Initialize core clock settings */
1210         ath5k_hw_init_core_clock(ah);
1211
1212         /*
1213          * Tweak initval settings for revised
1214          * chipsets and add some more config
1215          * bits
1216          */
1217         ath5k_hw_tweak_initval_settings(ah, channel);
1218
1219         /* Commit values from EEPROM */
1220         ath5k_hw_commit_eeprom_settings(ah, channel);
1221
1222
1223         /*
1224          * Restore saved values
1225          */
1226
1227         /* Seqnum, TSF */
1228         if (ah->ah_version != AR5K_AR5210) {
1229                 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
1230                         for (i = 0; i < 10; i++)
1231                                 ath5k_hw_reg_write(ah, s_seq[i],
1232                                         AR5K_QUEUE_DCU_SEQNUM(i));
1233                 } else {
1234                         ath5k_hw_reg_write(ah, s_seq[0],
1235                                 AR5K_QUEUE_DCU_SEQNUM(0));
1236                 }
1237
1238                 if (ah->ah_version == AR5K_AR5211) {
1239                         ath5k_hw_reg_write(ah, tsf_up, AR5K_TSF_U32);
1240                         ath5k_hw_reg_write(ah, tsf_lo, AR5K_TSF_L32);
1241                 }
1242         }
1243
1244         /* Ledstate */
1245         AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, s_led[0]);
1246
1247         /* Gpio settings */
1248         ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR);
1249         ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO);
1250
1251         /*
1252          * Initialize PCU
1253          */
1254         ath5k_hw_pcu_init(ah, op_mode, mode);
1255
1256         /*
1257          * Initialize PHY
1258          */
1259         ret = ath5k_hw_phy_init(ah, channel, mode, false);
1260         if (ret) {
1261                 ATH5K_ERR(ah->ah_sc,
1262                         "failed to initialize PHY (%i) !\n", ret);
1263                 return ret;
1264         }
1265
1266         /*
1267          * Configure QCUs/DCUs
1268          */
1269         ret = ath5k_hw_init_queues(ah);
1270         if (ret)
1271                 return ret;
1272
1273
1274         /*
1275          * Initialize DMA/Interrupts
1276          */
1277         ath5k_hw_dma_init(ah);
1278
1279
1280         /* Enable 32KHz clock function for AR5212+ chips
1281          * Set clocks to 32KHz operation and use an
1282          * external 32KHz crystal when sleeping if one
1283          * exists */
1284         if (ah->ah_version == AR5K_AR5212 &&
1285             op_mode != NL80211_IFTYPE_AP)
1286                 ath5k_hw_set_sleep_clock(ah, true);
1287
1288         /*
1289          * Disable beacons and reset the TSF
1290          */
1291         AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE);
1292         ath5k_hw_reset_tsf(ah);
1293         return 0;
1294 }