1 /******************************************************************************
2 * This software may be used and distributed according to the terms of
3 * the GNU General Public License (GPL), incorporated herein by reference.
4 * Drivers based on or derived from this code fall under the GPL and must
5 * retain the authorship, copyright and license notice. This file is not
6 * a complete program and may only be used when the entire operating
7 * system is licensed under the GPL.
8 * See the file COPYING in this distribution for more information.
10 * vxge-traffic.h: Driver for Neterion Inc's X3100 Series 10GbE PCIe I/O
11 * Virtualized Server Adapter.
12 * Copyright(c) 2002-2009 Neterion Inc.
13 ******************************************************************************/
14 #ifndef VXGE_TRAFFIC_H
15 #define VXGE_TRAFFIC_H
18 #include "vxge-version.h"
20 #define VXGE_HW_DTR_MAX_T_CODE 16
21 #define VXGE_HW_ALL_FOXES 0xFFFFFFFFFFFFFFFFULL
22 #define VXGE_HW_INTR_MASK_ALL 0xFFFFFFFFFFFFFFFFULL
23 #define VXGE_HW_MAX_VIRTUAL_PATHS 17
25 #define VXGE_HW_MAC_MAX_MAC_PORT_ID 2
27 #define VXGE_HW_DEFAULT_32 0xffffffff
29 #define VXGE_HW_HEADER_802_2_SIZE 3
30 #define VXGE_HW_HEADER_SNAP_SIZE 5
31 #define VXGE_HW_HEADER_VLAN_SIZE 4
32 #define VXGE_HW_MAC_HEADER_MAX_SIZE \
34 VXGE_HW_HEADER_802_2_SIZE + \
35 VXGE_HW_HEADER_VLAN_SIZE + \
36 VXGE_HW_HEADER_SNAP_SIZE)
38 #define VXGE_HW_TCPIP_HEADER_MAX_SIZE (64 + 64)
40 /* 32bit alignments */
41 #define VXGE_HW_HEADER_ETHERNET_II_802_3_ALIGN 2
42 #define VXGE_HW_HEADER_802_2_SNAP_ALIGN 2
43 #define VXGE_HW_HEADER_802_2_ALIGN 3
44 #define VXGE_HW_HEADER_SNAP_ALIGN 1
46 #define VXGE_HW_L3_CKSUM_OK 0xFFFF
47 #define VXGE_HW_L4_CKSUM_OK 0xFFFF
49 /* Forward declarations */
50 struct __vxge_hw_device;
51 struct __vxge_hw_vpath_handle;
52 struct vxge_hw_vp_config;
53 struct __vxge_hw_virtualpath;
54 struct __vxge_hw_channel;
55 struct __vxge_hw_fifo;
56 struct __vxge_hw_ring;
57 struct vxge_hw_ring_attr;
58 struct vxge_hw_mempool;
70 #define VXGE_HW_EVENT_BASE 0
71 #define VXGE_LL_EVENT_BASE 100
74 * enum vxge_hw_event- Enumerates slow-path HW events.
75 * @VXGE_HW_EVENT_UNKNOWN: Unknown (and invalid) event.
76 * @VXGE_HW_EVENT_SERR: Serious vpath hardware error event.
77 * @VXGE_HW_EVENT_ECCERR: vpath ECC error event.
78 * @VXGE_HW_EVENT_VPATH_ERR: Error local to the respective vpath
79 * @VXGE_HW_EVENT_FIFO_ERR: FIFO Doorbell fifo error.
80 * @VXGE_HW_EVENT_SRPCIM_SERR: srpcim hardware error event.
81 * @VXGE_HW_EVENT_MRPCIM_SERR: mrpcim hardware error event.
82 * @VXGE_HW_EVENT_MRPCIM_ECCERR: mrpcim ecc error event.
83 * @VXGE_HW_EVENT_RESET_START: Privileged entity is starting device reset
84 * @VXGE_HW_EVENT_RESET_COMPLETE: Device reset has been completed
85 * @VXGE_HW_EVENT_SLOT_FREEZE: Slot-freeze event. Driver tries to distinguish
86 * slot-freeze from the rest critical events (e.g. ECC) when it is
87 * impossible to PIO read "through" the bus, i.e. when getting all-foxes.
89 * enum vxge_hw_event enumerates slow-path HW eventis.
91 * See also: struct vxge_hw_uld_cbs{}, vxge_uld_link_up_f{},
92 * vxge_uld_link_down_f{}.
95 VXGE_HW_EVENT_UNKNOWN = 0,
97 VXGE_HW_EVENT_RESET_START = VXGE_HW_EVENT_BASE + 1,
98 VXGE_HW_EVENT_RESET_COMPLETE = VXGE_HW_EVENT_BASE + 2,
99 VXGE_HW_EVENT_LINK_DOWN = VXGE_HW_EVENT_BASE + 3,
100 VXGE_HW_EVENT_LINK_UP = VXGE_HW_EVENT_BASE + 4,
101 VXGE_HW_EVENT_ALARM_CLEARED = VXGE_HW_EVENT_BASE + 5,
102 VXGE_HW_EVENT_ECCERR = VXGE_HW_EVENT_BASE + 6,
103 VXGE_HW_EVENT_MRPCIM_ECCERR = VXGE_HW_EVENT_BASE + 7,
104 VXGE_HW_EVENT_FIFO_ERR = VXGE_HW_EVENT_BASE + 8,
105 VXGE_HW_EVENT_VPATH_ERR = VXGE_HW_EVENT_BASE + 9,
106 VXGE_HW_EVENT_CRITICAL_ERR = VXGE_HW_EVENT_BASE + 10,
107 VXGE_HW_EVENT_SERR = VXGE_HW_EVENT_BASE + 11,
108 VXGE_HW_EVENT_SRPCIM_SERR = VXGE_HW_EVENT_BASE + 12,
109 VXGE_HW_EVENT_MRPCIM_SERR = VXGE_HW_EVENT_BASE + 13,
110 VXGE_HW_EVENT_SLOT_FREEZE = VXGE_HW_EVENT_BASE + 14,
113 #define VXGE_HW_SET_LEVEL(a, b) (((a) > (b)) ? (a) : (b))
116 * struct vxge_hw_mempool_dma - Represents DMA objects passed to the
119 struct vxge_hw_mempool_dma {
121 struct pci_dev *handle;
122 struct pci_dev *acc_handle;
126 * vxge_hw_mempool_item_f - Mempool item alloc/free callback
127 * @mempoolh: Memory pool handle.
128 * @memblock: Address of memory block
129 * @memblock_index: Index of memory block
130 * @item: Item that gets allocated or freed.
131 * @index: Item's index in the memory pool.
132 * @is_last: True, if this item is the last one in the pool; false - otherwise.
133 * userdata: Per-pool user context.
135 * Memory pool allocation/deallocation callback.
139 * struct vxge_hw_mempool - Memory pool.
141 struct vxge_hw_mempool {
143 void (*item_func_alloc)(
144 struct vxge_hw_mempool *mempoolh,
146 struct vxge_hw_mempool_dma *dma_object,
151 void **memblocks_arr;
152 void **memblocks_priv_arr;
153 struct vxge_hw_mempool_dma *memblocks_dma_arr;
154 struct __vxge_hw_device *devh;
157 u32 memblocks_allocated;
162 u32 items_per_memblock;
167 #define VXGE_HW_MAX_INTR_PER_VP 4
168 #define VXGE_HW_VPATH_INTR_TX 0
169 #define VXGE_HW_VPATH_INTR_RX 1
170 #define VXGE_HW_VPATH_INTR_EINTA 2
171 #define VXGE_HW_VPATH_INTR_BMAP 3
173 #define VXGE_HW_BLOCK_SIZE 4096
176 * struct vxge_hw_tim_intr_config - Titan Tim interrupt configuration.
177 * @intr_enable: Set to 1, if interrupt is enabled.
178 * @btimer_val: Boundary Timer Initialization value in units of 272 ns.
179 * @timer_ac_en: Timer Automatic Cancel. 1 : Automatic Canceling Enable: when
180 * asserted, other interrupt-generating entities will cancel the
181 * scheduled timer interrupt.
182 * @timer_ci_en: Timer Continuous Interrupt. 1 : Continuous Interrupting Enable:
183 * When asserted, an interrupt will be generated every time the
184 * boundary timer expires, even if no traffic has been transmitted
186 * @timer_ri_en: Timer Consecutive (Re-) Interrupt 1 : Consecutive
187 * (Re-) Interrupt Enable: When asserted, an interrupt will be
188 * generated the next time the timer expires, even if no traffic has
189 * been transmitted on this interrupt. (This will only happen once
190 * each time that this value is written to the TIM.) This bit is
191 * cleared by H/W at the end of the current-timer-interval when
192 * the interrupt is triggered.
193 * @rtimer_val: Restriction Timer Initialization value in units of 272 ns.
194 * @util_sel: Utilization Selector. Selects which of the workload approximations
195 * to use (e.g. legacy Tx utilization, Tx/Rx utilization, host
196 * specified utilization etc.), selects one of
197 * the 17 host configured values.
202 * 17-Legacy Tx network utilization, provided by TPA
203 * 18-Legacy Rx network utilization, provided by FAU
204 * 19-Average of legacy Rx and Tx utilization calculated from link
205 * utilization values.
206 * 20-31-Invalid configurations
207 * 32-Host utilization for Virtual Path 0
208 * 33-Host utilization for Virtual Path 1
210 * 48-Host utilization for Virtual Path 17
211 * 49-Legacy Tx network utilization, provided by TPA
212 * 50-Legacy Rx network utilization, provided by FAU
213 * 51-Average of legacy Rx and Tx utilization calculated from
214 * link utilization values.
215 * 52-63-Invalid configurations
216 * @ltimer_val: Latency Timer Initialization Value in units of 272 ns.
217 * @txd_cnt_en: TxD Return Event Count Enable. This configuration bit when set
218 * to 1 enables counting of TxD0 returns (signalled by PCC's),
219 * towards utilization event count values.
220 * @urange_a: Defines the upper limit (in percent) for this utilization range
221 * to be active. This range is considered active
222 * if 0 = UTIL = URNG_A
223 * and the UEC_A field (below) is non-zero.
224 * @uec_a: Utilization Event Count A. If this range is active, the adapter will
225 * wait until UEC_A events have occurred on the interrupt before
226 * generating an interrupt.
227 * @urange_b: Link utilization range B.
228 * @uec_b: Utilization Event Count B.
229 * @urange_c: Link utilization range C.
230 * @uec_c: Utilization Event Count C.
231 * @urange_d: Link utilization range D.
232 * @uec_d: Utilization Event Count D.
233 * Traffic Interrupt Controller Module interrupt configuration.
235 struct vxge_hw_tim_intr_config {
238 #define VXGE_HW_TIM_INTR_ENABLE 1
239 #define VXGE_HW_TIM_INTR_DISABLE 0
240 #define VXGE_HW_TIM_INTR_DEFAULT 0
243 #define VXGE_HW_MIN_TIM_BTIMER_VAL 0
244 #define VXGE_HW_MAX_TIM_BTIMER_VAL 67108864
245 #define VXGE_HW_USE_FLASH_DEFAULT 0xffffffff
248 #define VXGE_HW_TIM_TIMER_AC_ENABLE 1
249 #define VXGE_HW_TIM_TIMER_AC_DISABLE 0
252 #define VXGE_HW_TIM_TIMER_CI_ENABLE 1
253 #define VXGE_HW_TIM_TIMER_CI_DISABLE 0
256 #define VXGE_HW_TIM_TIMER_RI_ENABLE 1
257 #define VXGE_HW_TIM_TIMER_RI_DISABLE 0
260 #define VXGE_HW_MIN_TIM_RTIMER_VAL 0
261 #define VXGE_HW_MAX_TIM_RTIMER_VAL 67108864
264 #define VXGE_HW_TIM_UTIL_SEL_LEGACY_TX_NET_UTIL 17
265 #define VXGE_HW_TIM_UTIL_SEL_LEGACY_RX_NET_UTIL 18
266 #define VXGE_HW_TIM_UTIL_SEL_LEGACY_TX_RX_AVE_NET_UTIL 19
267 #define VXGE_HW_TIM_UTIL_SEL_PER_VPATH 63
270 #define VXGE_HW_MIN_TIM_LTIMER_VAL 0
271 #define VXGE_HW_MAX_TIM_LTIMER_VAL 67108864
273 /* Line utilization interrupts */
275 #define VXGE_HW_MIN_TIM_URANGE_A 0
276 #define VXGE_HW_MAX_TIM_URANGE_A 100
279 #define VXGE_HW_MIN_TIM_UEC_A 0
280 #define VXGE_HW_MAX_TIM_UEC_A 65535
283 #define VXGE_HW_MIN_TIM_URANGE_B 0
284 #define VXGE_HW_MAX_TIM_URANGE_B 100
287 #define VXGE_HW_MIN_TIM_UEC_B 0
288 #define VXGE_HW_MAX_TIM_UEC_B 65535
291 #define VXGE_HW_MIN_TIM_URANGE_C 0
292 #define VXGE_HW_MAX_TIM_URANGE_C 100
295 #define VXGE_HW_MIN_TIM_UEC_C 0
296 #define VXGE_HW_MAX_TIM_UEC_C 65535
299 #define VXGE_HW_MIN_TIM_UEC_D 0
300 #define VXGE_HW_MAX_TIM_UEC_D 65535
303 #define VXGE_HW_STATS_OP_READ 0
304 #define VXGE_HW_STATS_OP_CLEAR_STAT 1
305 #define VXGE_HW_STATS_OP_CLEAR_ALL_VPATH_STATS 2
306 #define VXGE_HW_STATS_OP_CLEAR_ALL_STATS_OF_LOC 2
307 #define VXGE_HW_STATS_OP_CLEAR_ALL_STATS 3
309 #define VXGE_HW_STATS_LOC_AGGR 17
310 #define VXGE_HW_STATS_AGGRn_OFFSET 0x00720
312 #define VXGE_HW_STATS_VPATH_TX_OFFSET 0x0
313 #define VXGE_HW_STATS_VPATH_RX_OFFSET 0x00090
315 #define VXGE_HW_STATS_VPATH_PROG_EVENT_VNUM0_OFFSET (0x001d0 >> 3)
316 #define VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM0(bits) \
317 vxge_bVALn(bits, 0, 32)
319 #define VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM1(bits) \
320 vxge_bVALn(bits, 32, 32)
322 #define VXGE_HW_STATS_VPATH_PROG_EVENT_VNUM2_OFFSET (0x001d8 >> 3)
323 #define VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM2(bits) \
324 vxge_bVALn(bits, 0, 32)
326 #define VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM3(bits) \
327 vxge_bVALn(bits, 32, 32)
330 * struct vxge_hw_xmac_aggr_stats - Per-Aggregator XMAC Statistics
332 * @tx_frms: Count of data frames transmitted on this Aggregator on all
333 * its Aggregation ports. Does not include LACPDUs or Marker PDUs.
334 * However, does include frames discarded by the Distribution
336 * @tx_data_octets: Count of data and padding octets of frames transmitted
337 * on this Aggregator on all its Aggregation ports. Does not include
338 * octets of LACPDUs or Marker PDUs. However, does include octets of
339 * frames discarded by the Distribution function.
340 * @tx_mcast_frms: Count of data frames transmitted (to a group destination
341 * address other than the broadcast address) on this Aggregator on
342 * all its Aggregation ports. Does not include LACPDUs or Marker
343 * PDUs. However, does include frames discarded by the Distribution
345 * @tx_bcast_frms: Count of broadcast data frames transmitted on this Aggregator
346 * on all its Aggregation ports. Does not include LACPDUs or Marker
347 * PDUs. However, does include frames discarded by the Distribution
349 * @tx_discarded_frms: Count of data frames to be transmitted on this Aggregator
350 * that are discarded by the Distribution function. This occurs when
351 * conversation are allocated to different ports and have to be
352 * flushed on old ports
353 * @tx_errored_frms: Count of data frames transmitted on this Aggregator that
354 * experience transmission errors on its Aggregation ports.
355 * @rx_frms: Count of data frames received on this Aggregator on all its
356 * Aggregation ports. Does not include LACPDUs or Marker PDUs.
357 * Also, does not include frames discarded by the Collection
359 * @rx_data_octets: Count of data and padding octets of frames received on this
360 * Aggregator on all its Aggregation ports. Does not include octets
361 * of LACPDUs or Marker PDUs. Also, does not include
363 * discarded by the Collection function.
364 * @rx_mcast_frms: Count of data frames received (from a group destination
365 * address other than the broadcast address) on this Aggregator on
366 * all its Aggregation ports. Does not include LACPDUs or Marker
367 * PDUs. Also, does not include frames discarded by the Collection
369 * @rx_bcast_frms: Count of broadcast data frames received on this Aggregator on
370 * all its Aggregation ports. Does not include LACPDUs or Marker
371 * PDUs. Also, does not include frames discarded by the Collection
373 * @rx_discarded_frms: Count of data frames received on this Aggregator that are
374 * discarded by the Collection function because the Collection
375 * function was disabled on the port which the frames are received.
376 * @rx_errored_frms: Count of data frames received on this Aggregator that are
377 * discarded by its Aggregation ports, or are discarded by the
378 * Collection function of the Aggregator, or that are discarded by
379 * the Aggregator due to detection of an illegal Slow Protocols PDU.
380 * @rx_unknown_slow_proto_frms: Count of data frames received on this Aggregator
381 * that are discarded by its Aggregation ports due to detection of
382 * an unknown Slow Protocols PDU.
384 * Per aggregator XMAC RX statistics.
386 struct vxge_hw_xmac_aggr_stats {
387 /*0x000*/ u64 tx_frms;
388 /*0x008*/ u64 tx_data_octets;
389 /*0x010*/ u64 tx_mcast_frms;
390 /*0x018*/ u64 tx_bcast_frms;
391 /*0x020*/ u64 tx_discarded_frms;
392 /*0x028*/ u64 tx_errored_frms;
393 /*0x030*/ u64 rx_frms;
394 /*0x038*/ u64 rx_data_octets;
395 /*0x040*/ u64 rx_mcast_frms;
396 /*0x048*/ u64 rx_bcast_frms;
397 /*0x050*/ u64 rx_discarded_frms;
398 /*0x058*/ u64 rx_errored_frms;
399 /*0x060*/ u64 rx_unknown_slow_proto_frms;
403 * struct vxge_hw_xmac_port_stats - XMAC Port Statistics
405 * @tx_ttl_frms: Count of successfully transmitted MAC frames
406 * @tx_ttl_octets: Count of total octets of transmitted frames, not including
407 * framing characters (i.e. less framing bits). To determine the
408 * total octets of transmitted frames, including framing characters,
409 * multiply PORTn_TX_TTL_FRMS by 8 and add it to this stat (unless
410 * otherwise configured, this stat only counts frames that have
411 * 8 bytes of preamble for each frame). This stat can be configured
412 * (see XMAC_STATS_GLOBAL_CFG.TTL_FRMS_HANDLING) to count everything
413 * including the preamble octets.
414 * @tx_data_octets: Count of data and padding octets of successfully transmitted
416 * @tx_mcast_frms: Count of successfully transmitted frames to a group address
417 * other than the broadcast address.
418 * @tx_bcast_frms: Count of successfully transmitted frames to the broadcast
420 * @tx_ucast_frms: Count of transmitted frames containing a unicast address.
421 * Includes discarded frames that are not sent to the network.
422 * @tx_tagged_frms: Count of transmitted frames containing a VLAN tag.
423 * @tx_vld_ip: Count of transmitted IP datagrams that are passed to the network.
424 * @tx_vld_ip_octets: Count of total octets of transmitted IP datagrams that
425 * are passed to the network.
426 * @tx_icmp: Count of transmitted ICMP messages. Includes messages not sent
427 * due to problems within ICMP.
428 * @tx_tcp: Count of transmitted TCP segments. Does not include segments
429 * containing retransmitted octets.
430 * @tx_rst_tcp: Count of transmitted TCP segments containing the RST flag.
431 * @tx_udp: Count of transmitted UDP datagrams.
432 * @tx_parse_error: Increments when the TPA is unable to parse a packet. This
433 * generally occurs when a packet is corrupt somehow, including
434 * packets that have IP version mismatches, invalid Layer 2 control
435 * fields, etc. L3/L4 checksums are not offloaded, but the packet
436 * is still be transmitted.
437 * @tx_unknown_protocol: Increments when the TPA encounters an unknown
438 * protocol, such as a new IPv6 extension header, or an unsupported
439 * Routing Type. The packet still has a checksum calculated but it
441 * @tx_pause_ctrl_frms: Count of MAC PAUSE control frames that are transmitted.
442 * Since, the only control frames supported by this device are
443 * PAUSE frames, this register is a count of all transmitted MAC
445 * @tx_marker_pdu_frms: Count of Marker PDUs transmitted
446 * on this Aggregation port.
447 * @tx_lacpdu_frms: Count of LACPDUs transmitted on this Aggregation port.
448 * @tx_drop_ip: Count of transmitted IP datagrams that could not be passed to
449 * the network. Increments because of:
450 * 1) An internal processing error
451 * (such as an uncorrectable ECC error). 2) A frame parsing error
452 * during IP checksum calculation.
453 * @tx_marker_resp_pdu_frms: Count of Marker Response PDUs transmitted on this
455 * @tx_xgmii_char2_match: Maintains a count of the number of transmitted XGMII
456 * characters that match a pattern that is programmable through
457 * register XMAC_STATS_TX_XGMII_CHAR_PORTn. By default, the pattern
458 * is set to /T/ (i.e. the terminate character), thus the statistic
459 * tracks the number of transmitted Terminate characters.
460 * @tx_xgmii_char1_match: Maintains a count of the number of transmitted XGMII
461 * characters that match a pattern that is programmable through
462 * register XMAC_STATS_TX_XGMII_CHAR_PORTn. By default, the pattern
463 * is set to /S/ (i.e. the start character),
464 * thus the statistic tracks
465 * the number of transmitted Start characters.
466 * @tx_xgmii_column2_match: Maintains a count of the number of transmitted XGMII
467 * columns that match a pattern that is programmable through register
468 * XMAC_STATS_TX_XGMII_COLUMN2_PORTn. By default, the pattern is set
469 * to 4 x /E/ (i.e. a column containing all error characters), thus
470 * the statistic tracks the number of Error columns transmitted at
471 * any time. If XMAC_STATS_TX_XGMII_BEHAV_COLUMN2_PORTn.NEAR_COL1 is
472 * set to 1, then this stat increments when COLUMN2 is found within
473 * 'n' clocks after COLUMN1. Here, 'n' is defined by
474 * XMAC_STATS_TX_XGMII_BEHAV_COLUMN2_PORTn.NUM_COL (if 'n' is set
475 * to 0, then it means to search anywhere for COLUMN2).
476 * @tx_xgmii_column1_match: Maintains a count of the number of transmitted XGMII
477 * columns that match a pattern that is programmable through register
478 * XMAC_STATS_TX_XGMII_COLUMN1_PORTn. By default, the pattern is set
479 * to 4 x /I/ (i.e. a column containing all idle characters),
480 * thus the statistic tracks the number of transmitted Idle columns.
481 * @tx_any_err_frms: Count of transmitted frames containing any error that
482 * prevents them from being passed to the network. Increments if
483 * there is an ECC while reading the frame out of the transmit
484 * buffer. Also increments if the transmit protocol assist (TPA)
485 * block determines that the frame should not be sent.
486 * @tx_drop_frms: Count of frames that could not be sent for no other reason
487 * than internal MAC processing. Increments once whenever the
488 * transmit buffer is flushed (due to an ECC error on a memory
490 * @rx_ttl_frms: Count of total received MAC frames, including frames received
491 * with frame-too-long, FCS, or length errors. This stat can be
492 * configured (see XMAC_STATS_GLOBAL_CFG.TTL_FRMS_HANDLING) to count
493 * everything, even "frames" as small one byte of preamble.
494 * @rx_vld_frms: Count of successfully received MAC frames. Does not include
495 * frames received with frame-too-long, FCS, or length errors.
496 * @rx_offload_frms: Count of offloaded received frames that are passed to
498 * @rx_ttl_octets: Count of total octets of received frames, not including
499 * framing characters (i.e. less framing bits). To determine the
500 * total octets of received frames, including framing characters,
501 * multiply PORTn_RX_TTL_FRMS by 8 and add it to this stat (unless
502 * otherwise configured, this stat only counts frames that have 8
503 * bytes of preamble for each frame). This stat can be configured
504 * (see XMAC_STATS_GLOBAL_CFG.TTL_FRMS_HANDLING) to count everything,
505 * even the preamble octets of "frames" as small one byte of preamble
506 * @rx_data_octets: Count of data and padding octets of successfully received
507 * frames. Does not include frames received with frame-too-long,
508 * FCS, or length errors.
509 * @rx_offload_octets: Count of total octets, not including framing
510 * characters, of offloaded received frames that are passed
512 * @rx_vld_mcast_frms: Count of successfully received MAC frames containing a
513 * nonbroadcast group address. Does not include frames received
514 * with frame-too-long, FCS, or length errors.
515 * @rx_vld_bcast_frms: Count of successfully received MAC frames containing
516 * the broadcast group address. Does not include frames received
517 * with frame-too-long, FCS, or length errors.
518 * @rx_accepted_ucast_frms: Count of successfully received frames containing
519 * a unicast address. Only includes frames that are passed to
521 * @rx_accepted_nucast_frms: Count of successfully received frames containing
522 * a non-unicast (broadcast or multicast) address. Only includes
523 * frames that are passed to the system. Could include, for instance,
524 * non-unicast frames that contain FCS errors if the MAC_ERROR_CFG
525 * register is set to pass FCS-errored frames to the host.
526 * @rx_tagged_frms: Count of received frames containing a VLAN tag.
527 * @rx_long_frms: Count of received frames that are longer than RX_MAX_PYLD_LEN
528 * + 18 bytes (+ 22 bytes if VLAN-tagged).
529 * @rx_usized_frms: Count of received frames of length (including FCS, but not
530 * framing bits) less than 64 octets, that are otherwise well-formed.
531 * In other words, counts runts.
532 * @rx_osized_frms: Count of received frames of length (including FCS, but not
533 * framing bits) more than 1518 octets, that are otherwise
534 * well-formed. Note: If register XMAC_STATS_GLOBAL_CFG.VLAN_HANDLING
535 * is set to 1, then "more than 1518 octets" becomes "more than 1518
536 * (1522 if VLAN-tagged) octets".
537 * @rx_frag_frms: Count of received frames of length (including FCS, but not
538 * framing bits) less than 64 octets that had bad FCS. In other
539 * words, counts fragments.
540 * @rx_jabber_frms: Count of received frames of length (including FCS, but not
541 * framing bits) more than 1518 octets that had bad FCS. In other
542 * words, counts jabbers. Note: If register
543 * XMAC_STATS_GLOBAL_CFG.VLAN_HANDLING is set to 1, then "more than
544 * 1518 octets" becomes "more than 1518 (1522 if VLAN-tagged)
546 * @rx_ttl_64_frms: Count of total received MAC frames with length (including
547 * FCS, but not framing bits) of exactly 64 octets. Includes frames
548 * received with frame-too-long, FCS, or length errors.
549 * @rx_ttl_65_127_frms: Count of total received MAC frames with length
550 * (including FCS, but not framing bits) of between 65 and 127
551 * octets inclusive. Includes frames received with frame-too-long,
552 * FCS, or length errors.
553 * @rx_ttl_128_255_frms: Count of total received MAC frames with length
554 * (including FCS, but not framing bits) of between 128 and 255
555 * octets inclusive. Includes frames received with frame-too-long,
556 * FCS, or length errors.
557 * @rx_ttl_256_511_frms: Count of total received MAC frames with length
558 * (including FCS, but not framing bits) of between 256 and 511
559 * octets inclusive. Includes frames received with frame-too-long,
560 * FCS, or length errors.
561 * @rx_ttl_512_1023_frms: Count of total received MAC frames with length
562 * (including FCS, but not framing bits) of between 512 and 1023
563 * octets inclusive. Includes frames received with frame-too-long,
564 * FCS, or length errors.
565 * @rx_ttl_1024_1518_frms: Count of total received MAC frames with length
566 * (including FCS, but not framing bits) of between 1024 and 1518
567 * octets inclusive. Includes frames received with frame-too-long,
568 * FCS, or length errors.
569 * @rx_ttl_1519_4095_frms: Count of total received MAC frames with length
570 * (including FCS, but not framing bits) of between 1519 and 4095
571 * octets inclusive. Includes frames received with frame-too-long,
572 * FCS, or length errors.
573 * @rx_ttl_4096_8191_frms: Count of total received MAC frames with length
574 * (including FCS, but not framing bits) of between 4096 and 8191
575 * octets inclusive. Includes frames received with frame-too-long,
576 * FCS, or length errors.
577 * @rx_ttl_8192_max_frms: Count of total received MAC frames with length
578 * (including FCS, but not framing bits) of between 8192 and
579 * RX_MAX_PYLD_LEN+18 octets inclusive. Includes frames received
580 * with frame-too-long, FCS, or length errors.
581 * @rx_ttl_gt_max_frms: Count of total received MAC frames with length
582 * (including FCS, but not framing bits) exceeding
583 * RX_MAX_PYLD_LEN+18 (+22 bytes if VLAN-tagged) octets inclusive.
584 * Includes frames received with frame-too-long,
585 * FCS, or length errors.
586 * @rx_ip: Count of received IP datagrams. Includes errored IP datagrams.
587 * @rx_accepted_ip: Count of received IP datagrams that
588 * are passed to the system.
589 * @rx_ip_octets: Count of number of octets in received IP datagrams. Includes
590 * errored IP datagrams.
591 * @rx_err_ip: Count of received IP datagrams containing errors. For example,
593 * @rx_icmp: Count of received ICMP messages. Includes errored ICMP messages.
594 * @rx_tcp: Count of received TCP segments. Includes errored TCP segments.
595 * Note: This stat contains a count of all received TCP segments,
596 * regardless of whether or not they pertain to an established
598 * @rx_udp: Count of received UDP datagrams.
599 * @rx_err_tcp: Count of received TCP segments containing errors. For example,
601 * @rx_pause_count: Count of number of pause quanta that the MAC has been in
602 * the paused state. Recall, one pause quantum equates to 512
604 * @rx_pause_ctrl_frms: Count of received MAC PAUSE control frames.
605 * @rx_unsup_ctrl_frms: Count of received MAC control frames that do not
606 * contain the PAUSE opcode. The sum of RX_PAUSE_CTRL_FRMS and
607 * this register is a count of all received MAC control frames.
608 * Note: This stat may be configured to count all layer 2 errors
609 * (i.e. length errors and FCS errors).
610 * @rx_fcs_err_frms: Count of received MAC frames that do not pass FCS. Does
611 * not include frames received with frame-too-long or
612 * frame-too-short error.
613 * @rx_in_rng_len_err_frms: Count of received frames with a length/type field
614 * value between 46 (42 for VLAN-tagged frames) and 1500 (also 1500
615 * for VLAN-tagged frames), inclusive, that does not match the
616 * number of data octets (including pad) received. Also contains
617 * a count of received frames with a length/type field less than
618 * 46 (42 for VLAN-tagged frames) and the number of data octets
619 * (including pad) received is greater than 46 (42 for VLAN-tagged
621 * @rx_out_rng_len_err_frms: Count of received frames with length/type field
622 * between 1501 and 1535 decimal, inclusive.
623 * @rx_drop_frms: Count of received frames that could not be passed to the host.
624 * See PORTn_RX_L2_MGMT_DISCARD, PORTn_RX_RPA_DISCARD,
625 * PORTn_RX_TRASH_DISCARD, PORTn_RX_RTS_DISCARD, PORTn_RX_RED_DISCARD
626 * for a list of reasons. Because the RMAC drops one frame at a time,
627 * this stat also indicates the number of drop events.
628 * @rx_discarded_frms: Count of received frames containing
629 * any error that prevents
630 * them from being passed to the system. See PORTn_RX_FCS_DISCARD,
631 * PORTn_RX_LEN_DISCARD, and PORTn_RX_SWITCH_DISCARD for a list of
633 * @rx_drop_ip: Count of received IP datagrams that could not be passed to the
634 * host. See PORTn_RX_DROP_FRMS for a list of reasons.
635 * @rx_drop_udp: Count of received UDP datagrams that are not delivered to the
636 * host. See PORTn_RX_DROP_FRMS for a list of reasons.
637 * @rx_marker_pdu_frms: Count of valid Marker PDUs received on this Aggregation
639 * @rx_lacpdu_frms: Count of valid LACPDUs received on this Aggregation port.
640 * @rx_unknown_pdu_frms: Count of received frames (on this Aggregation port)
641 * that carry the Slow Protocols EtherType, but contain an unknown
642 * PDU. Or frames that contain the Slow Protocols group MAC address,
643 * but do not carry the Slow Protocols EtherType.
644 * @rx_marker_resp_pdu_frms: Count of valid Marker Response PDUs received on
645 * this Aggregation port.
646 * @rx_fcs_discard: Count of received frames that are discarded because the
648 * @rx_illegal_pdu_frms: Count of received frames (on this Aggregation port)
649 * that carry the Slow Protocols EtherType, but contain a badly
650 * formed PDU. Or frames that carry the Slow Protocols EtherType,
651 * but contain an illegal value of Protocol Subtype.
652 * @rx_switch_discard: Count of received frames that are discarded by the
653 * internal switch because they did not have an entry in the
654 * Filtering Database. This includes frames that had an invalid
655 * destination MAC address or VLAN ID. It also includes frames are
656 * discarded because they did not satisfy the length requirements
657 * of the target VPATH.
658 * @rx_len_discard: Count of received frames that are discarded because of an
659 * invalid frame length (includes fragments, oversized frames and
660 * mismatch between frame length and length/type field). This stat
662 * (see XMAC_STATS_GLOBAL_CFG.LEN_DISCARD_HANDLING).
663 * @rx_rpa_discard: Count of received frames that were discarded because the
664 * receive protocol assist (RPA) discovered and error in the frame
665 * or was unable to parse the frame.
666 * @rx_l2_mgmt_discard: Count of Layer 2 management frames (eg. pause frames,
667 * Link Aggregation Control Protocol (LACP) frames, etc.) that are
669 * @rx_rts_discard: Count of received frames that are discarded by the receive
670 * traffic steering (RTS) logic. Includes those frame discarded
671 * because the SSC response contradicted the switch table, because
672 * the SSC timed out, or because the target queue could not fit the
674 * @rx_trash_discard: Count of received frames that are discarded because
675 * receive traffic steering (RTS) steered the frame to the trash
677 * @rx_buff_full_discard: Count of received frames that are discarded because
678 * internal buffers are full. Includes frames discarded because the
679 * RTS logic is waiting for an SSC lookup that has no timeout bound.
680 * Also, includes frames that are dropped because the MAC2FAU buffer
681 * is nearly full -- this can happen if the external receive buffer
682 * is full and the receive path is backing up.
683 * @rx_red_discard: Count of received frames that are discarded because of RED
684 * (Random Early Discard).
685 * @rx_xgmii_ctrl_err_cnt: Maintains a count of unexpected or misplaced control
686 * characters occuring between times of normal data transmission
687 * (i.e. not included in RX_XGMII_DATA_ERR_CNT). This counter is
688 * incremented when either -
689 * 1) The Reconciliation Sublayer (RS) is expecting one control
690 * character and gets another (i.e. is expecting a Start
691 * character, but gets another control character).
692 * 2) Start control character is not in lane 0
693 * Only increments the count by one for each XGMII column.
694 * @rx_xgmii_data_err_cnt: Maintains a count of unexpected control characters
695 * during normal data transmission. If the Reconciliation Sublayer
696 * (RS) receives a control character, other than a terminate control
697 * character, during receipt of data octets then this register is
698 * incremented. Also increments if the start frame delimiter is not
699 * found in the correct location. Only increments the count by one
700 * for each XGMII column.
701 * @rx_xgmii_char1_match: Maintains a count of the number of XGMII characters
702 * that match a pattern that is programmable through register
703 * XMAC_STATS_RX_XGMII_CHAR_PORTn. By default, the pattern is set
704 * to /E/ (i.e. the error character), thus the statistic tracks the
705 * number of Error characters received at any time.
706 * @rx_xgmii_err_sym: Count of the number of symbol errors in the received
707 * XGMII data (i.e. PHY indicates "Receive Error" on the XGMII).
708 * Only includes symbol errors that are observed between the XGMII
709 * Start Frame Delimiter and End Frame Delimiter, inclusive. And
710 * only increments the count by one for each frame.
711 * @rx_xgmii_column1_match: Maintains a count of the number of XGMII columns
712 * that match a pattern that is programmable through register
713 * XMAC_STATS_RX_XGMII_COLUMN1_PORTn. By default, the pattern is set
714 * to 4 x /E/ (i.e. a column containing all error characters), thus
715 * the statistic tracks the number of Error columns received at any
717 * @rx_xgmii_char2_match: Maintains a count of the number of XGMII characters
718 * that match a pattern that is programmable through register
719 * XMAC_STATS_RX_XGMII_CHAR_PORTn. By default, the pattern is set
720 * to /E/ (i.e. the error character), thus the statistic tracks the
721 * number of Error characters received at any time.
722 * @rx_local_fault: Maintains a count of the number of times that link
723 * transitioned from "up" to "down" due to a local fault.
724 * @rx_xgmii_column2_match: Maintains a count of the number of XGMII columns
725 * that match a pattern that is programmable through register
726 * XMAC_STATS_RX_XGMII_COLUMN2_PORTn. By default, the pattern is set
727 * to 4 x /E/ (i.e. a column containing all error characters), thus
728 * the statistic tracks the number of Error columns received at any
729 * time. If XMAC_STATS_RX_XGMII_BEHAV_COLUMN2_PORTn.NEAR_COL1 is set
730 * to 1, then this stat increments when COLUMN2 is found within 'n'
731 * clocks after COLUMN1. Here, 'n' is defined by
732 * XMAC_STATS_RX_XGMII_BEHAV_COLUMN2_PORTn.NUM_COL (if 'n' is set to
733 * 0, then it means to search anywhere for COLUMN2).
734 * @rx_jettison: Count of received frames that are jettisoned because internal
736 * @rx_remote_fault: Maintains a count of the number of times that link
737 * transitioned from "up" to "down" due to a remote fault.
739 * XMAC Port Statistics.
741 struct vxge_hw_xmac_port_stats {
742 /*0x000*/ u64 tx_ttl_frms;
743 /*0x008*/ u64 tx_ttl_octets;
744 /*0x010*/ u64 tx_data_octets;
745 /*0x018*/ u64 tx_mcast_frms;
746 /*0x020*/ u64 tx_bcast_frms;
747 /*0x028*/ u64 tx_ucast_frms;
748 /*0x030*/ u64 tx_tagged_frms;
749 /*0x038*/ u64 tx_vld_ip;
750 /*0x040*/ u64 tx_vld_ip_octets;
751 /*0x048*/ u64 tx_icmp;
752 /*0x050*/ u64 tx_tcp;
753 /*0x058*/ u64 tx_rst_tcp;
754 /*0x060*/ u64 tx_udp;
755 /*0x068*/ u32 tx_parse_error;
756 /*0x06c*/ u32 tx_unknown_protocol;
757 /*0x070*/ u64 tx_pause_ctrl_frms;
758 /*0x078*/ u32 tx_marker_pdu_frms;
759 /*0x07c*/ u32 tx_lacpdu_frms;
760 /*0x080*/ u32 tx_drop_ip;
761 /*0x084*/ u32 tx_marker_resp_pdu_frms;
762 /*0x088*/ u32 tx_xgmii_char2_match;
763 /*0x08c*/ u32 tx_xgmii_char1_match;
764 /*0x090*/ u32 tx_xgmii_column2_match;
765 /*0x094*/ u32 tx_xgmii_column1_match;
766 /*0x098*/ u32 unused1;
767 /*0x09c*/ u16 tx_any_err_frms;
768 /*0x09e*/ u16 tx_drop_frms;
769 /*0x0a0*/ u64 rx_ttl_frms;
770 /*0x0a8*/ u64 rx_vld_frms;
771 /*0x0b0*/ u64 rx_offload_frms;
772 /*0x0b8*/ u64 rx_ttl_octets;
773 /*0x0c0*/ u64 rx_data_octets;
774 /*0x0c8*/ u64 rx_offload_octets;
775 /*0x0d0*/ u64 rx_vld_mcast_frms;
776 /*0x0d8*/ u64 rx_vld_bcast_frms;
777 /*0x0e0*/ u64 rx_accepted_ucast_frms;
778 /*0x0e8*/ u64 rx_accepted_nucast_frms;
779 /*0x0f0*/ u64 rx_tagged_frms;
780 /*0x0f8*/ u64 rx_long_frms;
781 /*0x100*/ u64 rx_usized_frms;
782 /*0x108*/ u64 rx_osized_frms;
783 /*0x110*/ u64 rx_frag_frms;
784 /*0x118*/ u64 rx_jabber_frms;
785 /*0x120*/ u64 rx_ttl_64_frms;
786 /*0x128*/ u64 rx_ttl_65_127_frms;
787 /*0x130*/ u64 rx_ttl_128_255_frms;
788 /*0x138*/ u64 rx_ttl_256_511_frms;
789 /*0x140*/ u64 rx_ttl_512_1023_frms;
790 /*0x148*/ u64 rx_ttl_1024_1518_frms;
791 /*0x150*/ u64 rx_ttl_1519_4095_frms;
792 /*0x158*/ u64 rx_ttl_4096_8191_frms;
793 /*0x160*/ u64 rx_ttl_8192_max_frms;
794 /*0x168*/ u64 rx_ttl_gt_max_frms;
796 /*0x178*/ u64 rx_accepted_ip;
797 /*0x180*/ u64 rx_ip_octets;
798 /*0x188*/ u64 rx_err_ip;
799 /*0x190*/ u64 rx_icmp;
800 /*0x198*/ u64 rx_tcp;
801 /*0x1a0*/ u64 rx_udp;
802 /*0x1a8*/ u64 rx_err_tcp;
803 /*0x1b0*/ u64 rx_pause_count;
804 /*0x1b8*/ u64 rx_pause_ctrl_frms;
805 /*0x1c0*/ u64 rx_unsup_ctrl_frms;
806 /*0x1c8*/ u64 rx_fcs_err_frms;
807 /*0x1d0*/ u64 rx_in_rng_len_err_frms;
808 /*0x1d8*/ u64 rx_out_rng_len_err_frms;
809 /*0x1e0*/ u64 rx_drop_frms;
810 /*0x1e8*/ u64 rx_discarded_frms;
811 /*0x1f0*/ u64 rx_drop_ip;
812 /*0x1f8*/ u64 rx_drop_udp;
813 /*0x200*/ u32 rx_marker_pdu_frms;
814 /*0x204*/ u32 rx_lacpdu_frms;
815 /*0x208*/ u32 rx_unknown_pdu_frms;
816 /*0x20c*/ u32 rx_marker_resp_pdu_frms;
817 /*0x210*/ u32 rx_fcs_discard;
818 /*0x214*/ u32 rx_illegal_pdu_frms;
819 /*0x218*/ u32 rx_switch_discard;
820 /*0x21c*/ u32 rx_len_discard;
821 /*0x220*/ u32 rx_rpa_discard;
822 /*0x224*/ u32 rx_l2_mgmt_discard;
823 /*0x228*/ u32 rx_rts_discard;
824 /*0x22c*/ u32 rx_trash_discard;
825 /*0x230*/ u32 rx_buff_full_discard;
826 /*0x234*/ u32 rx_red_discard;
827 /*0x238*/ u32 rx_xgmii_ctrl_err_cnt;
828 /*0x23c*/ u32 rx_xgmii_data_err_cnt;
829 /*0x240*/ u32 rx_xgmii_char1_match;
830 /*0x244*/ u32 rx_xgmii_err_sym;
831 /*0x248*/ u32 rx_xgmii_column1_match;
832 /*0x24c*/ u32 rx_xgmii_char2_match;
833 /*0x250*/ u32 rx_local_fault;
834 /*0x254*/ u32 rx_xgmii_column2_match;
835 /*0x258*/ u32 rx_jettison;
836 /*0x25c*/ u32 rx_remote_fault;
840 * struct vxge_hw_xmac_vpath_tx_stats - XMAC Vpath Tx Statistics
842 * @tx_ttl_eth_frms: Count of successfully transmitted MAC frames.
843 * @tx_ttl_eth_octets: Count of total octets of transmitted frames,
844 * not including framing characters (i.e. less framing bits).
845 * To determine the total octets of transmitted frames, including
846 * framing characters, multiply TX_TTL_ETH_FRMS by 8 and add it to
847 * this stat (the device always prepends 8 bytes of preamble for
849 * @tx_data_octets: Count of data and padding octets of successfully transmitted
851 * @tx_mcast_frms: Count of successfully transmitted frames to a group address
852 * other than the broadcast address.
853 * @tx_bcast_frms: Count of successfully transmitted frames to the broadcast
855 * @tx_ucast_frms: Count of transmitted frames containing a unicast address.
856 * Includes discarded frames that are not sent to the network.
857 * @tx_tagged_frms: Count of transmitted frames containing a VLAN tag.
858 * @tx_vld_ip: Count of transmitted IP datagrams that are passed to the network.
859 * @tx_vld_ip_octets: Count of total octets of transmitted IP datagrams that
860 * are passed to the network.
861 * @tx_icmp: Count of transmitted ICMP messages. Includes messages not sent due
862 * to problems within ICMP.
863 * @tx_tcp: Count of transmitted TCP segments. Does not include segments
864 * containing retransmitted octets.
865 * @tx_rst_tcp: Count of transmitted TCP segments containing the RST flag.
866 * @tx_udp: Count of transmitted UDP datagrams.
867 * @tx_unknown_protocol: Increments when the TPA encounters an unknown protocol,
868 * such as a new IPv6 extension header, or an unsupported Routing
869 * Type. The packet still has a checksum calculated but it may be
871 * @tx_lost_ip: Count of transmitted IP datagrams that could not be passed
872 * to the network. Increments because of: 1) An internal processing
873 * error (such as an uncorrectable ECC error). 2) A frame parsing
874 * error during IP checksum calculation.
875 * @tx_parse_error: Increments when the TPA is unable to parse a packet. This
876 * generally occurs when a packet is corrupt somehow, including
877 * packets that have IP version mismatches, invalid Layer 2 control
878 * fields, etc. L3/L4 checksums are not offloaded, but the packet
879 * is still be transmitted.
880 * @tx_tcp_offload: For frames belonging to offloaded sessions only, a count
881 * of transmitted TCP segments. Does not include segments containing
882 * retransmitted octets.
883 * @tx_retx_tcp_offload: For frames belonging to offloaded sessions only, the
884 * total number of segments retransmitted. Retransmitted segments
885 * that are sourced by the host are counted by the host.
886 * @tx_lost_ip_offload: For frames belonging to offloaded sessions only, a count
887 * of transmitted IP datagrams that could not be passed to the
890 * XMAC Vpath TX Statistics.
892 struct vxge_hw_xmac_vpath_tx_stats {
894 u64 tx_ttl_eth_octets;
901 u64 tx_vld_ip_octets;
906 u32 tx_unknown_protocol;
911 u64 tx_retx_tcp_offload;
912 u64 tx_lost_ip_offload;
916 * struct vxge_hw_xmac_vpath_rx_stats - XMAC Vpath RX Statistics
918 * @rx_ttl_eth_frms: Count of successfully received MAC frames.
919 * @rx_vld_frms: Count of successfully received MAC frames. Does not include
920 * frames received with frame-too-long, FCS, or length errors.
921 * @rx_offload_frms: Count of offloaded received frames that are passed to
923 * @rx_ttl_eth_octets: Count of total octets of received frames, not including
924 * framing characters (i.e. less framing bits). Only counts octets
925 * of frames that are at least 14 bytes (18 bytes for VLAN-tagged)
926 * before FCS. To determine the total octets of received frames,
927 * including framing characters, multiply RX_TTL_ETH_FRMS by 8 and
928 * add it to this stat (the stat RX_TTL_ETH_FRMS only counts frames
929 * that have the required 8 bytes of preamble).
930 * @rx_data_octets: Count of data and padding octets of successfully received
931 * frames. Does not include frames received with frame-too-long,
932 * FCS, or length errors.
933 * @rx_offload_octets: Count of total octets, not including framing characters,
934 * of offloaded received frames that are passed to the host.
935 * @rx_vld_mcast_frms: Count of successfully received MAC frames containing a
936 * nonbroadcast group address. Does not include frames received with
937 * frame-too-long, FCS, or length errors.
938 * @rx_vld_bcast_frms: Count of successfully received MAC frames containing the
939 * broadcast group address. Does not include frames received with
940 * frame-too-long, FCS, or length errors.
941 * @rx_accepted_ucast_frms: Count of successfully received frames containing
942 * a unicast address. Only includes frames that are passed to the
944 * @rx_accepted_nucast_frms: Count of successfully received frames containing
945 * a non-unicast (broadcast or multicast) address. Only includes
946 * frames that are passed to the system. Could include, for instance,
947 * non-unicast frames that contain FCS errors if the MAC_ERROR_CFG
948 * register is set to pass FCS-errored frames to the host.
949 * @rx_tagged_frms: Count of received frames containing a VLAN tag.
950 * @rx_long_frms: Count of received frames that are longer than RX_MAX_PYLD_LEN
951 * + 18 bytes (+ 22 bytes if VLAN-tagged).
952 * @rx_usized_frms: Count of received frames of length (including FCS, but not
953 * framing bits) less than 64 octets, that are otherwise well-formed.
954 * In other words, counts runts.
955 * @rx_osized_frms: Count of received frames of length (including FCS, but not
956 * framing bits) more than 1518 octets, that are otherwise
958 * @rx_frag_frms: Count of received frames of length (including FCS, but not
959 * framing bits) less than 64 octets that had bad FCS.
960 * In other words, counts fragments.
961 * @rx_jabber_frms: Count of received frames of length (including FCS, but not
962 * framing bits) more than 1518 octets that had bad FCS. In other
963 * words, counts jabbers.
964 * @rx_ttl_64_frms: Count of total received MAC frames with length (including
965 * FCS, but not framing bits) of exactly 64 octets. Includes frames
966 * received with frame-too-long, FCS, or length errors.
967 * @rx_ttl_65_127_frms: Count of total received MAC frames
968 * with length (including
969 * FCS, but not framing bits) of between 65 and 127 octets inclusive.
970 * Includes frames received with frame-too-long, FCS,
972 * @rx_ttl_128_255_frms: Count of total received MAC frames with length
973 * (including FCS, but not framing bits)
974 * of between 128 and 255 octets
975 * inclusive. Includes frames received with frame-too-long, FCS,
977 * @rx_ttl_256_511_frms: Count of total received MAC frames with length
978 * (including FCS, but not framing bits)
979 * of between 256 and 511 octets
980 * inclusive. Includes frames received with frame-too-long, FCS, or
982 * @rx_ttl_512_1023_frms: Count of total received MAC frames with length
983 * (including FCS, but not framing bits) of between 512 and 1023
984 * octets inclusive. Includes frames received with frame-too-long,
985 * FCS, or length errors.
986 * @rx_ttl_1024_1518_frms: Count of total received MAC frames with length
987 * (including FCS, but not framing bits) of between 1024 and 1518
988 * octets inclusive. Includes frames received with frame-too-long,
989 * FCS, or length errors.
990 * @rx_ttl_1519_4095_frms: Count of total received MAC frames with length
991 * (including FCS, but not framing bits) of between 1519 and 4095
992 * octets inclusive. Includes frames received with frame-too-long,
993 * FCS, or length errors.
994 * @rx_ttl_4096_8191_frms: Count of total received MAC frames with length
995 * (including FCS, but not framing bits) of between 4096 and 8191
996 * octets inclusive. Includes frames received with frame-too-long,
997 * FCS, or length errors.
998 * @rx_ttl_8192_max_frms: Count of total received MAC frames with length
999 * (including FCS, but not framing bits) of between 8192 and
1000 * RX_MAX_PYLD_LEN+18 octets inclusive. Includes frames received
1001 * with frame-too-long, FCS, or length errors.
1002 * @rx_ttl_gt_max_frms: Count of total received MAC frames with length
1003 * (including FCS, but not framing bits) exceeding RX_MAX_PYLD_LEN+18
1004 * (+22 bytes if VLAN-tagged) octets inclusive. Includes frames
1005 * received with frame-too-long, FCS, or length errors.
1006 * @rx_ip: Count of received IP datagrams. Includes errored IP datagrams.
1007 * @rx_accepted_ip: Count of received IP datagrams that
1008 * are passed to the system.
1009 * @rx_ip_octets: Count of number of octets in received IP datagrams.
1010 * Includes errored IP datagrams.
1011 * @rx_err_ip: Count of received IP datagrams containing errors. For example,
1013 * @rx_icmp: Count of received ICMP messages. Includes errored ICMP messages.
1014 * @rx_tcp: Count of received TCP segments. Includes errored TCP segments.
1015 * Note: This stat contains a count of all received TCP segments,
1016 * regardless of whether or not they pertain to an established
1018 * @rx_udp: Count of received UDP datagrams.
1019 * @rx_err_tcp: Count of received TCP segments containing errors. For example,
1021 * @rx_lost_frms: Count of received frames that could not be passed to the host.
1022 * See RX_QUEUE_FULL_DISCARD and RX_RED_DISCARD
1023 * for a list of reasons.
1024 * @rx_lost_ip: Count of received IP datagrams that could not be passed to
1025 * the host. See RX_LOST_FRMS for a list of reasons.
1026 * @rx_lost_ip_offload: For frames belonging to offloaded sessions only, a count
1027 * of received IP datagrams that could not be passed to the host.
1028 * See RX_LOST_FRMS for a list of reasons.
1029 * @rx_various_discard: Count of received frames that are discarded because
1030 * the target receive queue is full.
1031 * @rx_sleep_discard: Count of received frames that are discarded because the
1032 * target VPATH is asleep (a Wake-on-LAN magic packet can be used
1033 * to awaken the VPATH).
1034 * @rx_red_discard: Count of received frames that are discarded because of RED
1035 * (Random Early Discard).
1036 * @rx_queue_full_discard: Count of received frames that are discarded because
1037 * the target receive queue is full.
1038 * @rx_mpa_ok_frms: Count of received frames that pass the MPA checks.
1040 * XMAC Vpath RX Statistics.
1042 struct vxge_hw_xmac_vpath_rx_stats {
1043 u64 rx_ttl_eth_frms;
1045 u64 rx_offload_frms;
1046 u64 rx_ttl_eth_octets;
1048 u64 rx_offload_octets;
1049 u64 rx_vld_mcast_frms;
1050 u64 rx_vld_bcast_frms;
1051 u64 rx_accepted_ucast_frms;
1052 u64 rx_accepted_nucast_frms;
1060 u64 rx_ttl_65_127_frms;
1061 u64 rx_ttl_128_255_frms;
1062 u64 rx_ttl_256_511_frms;
1063 u64 rx_ttl_512_1023_frms;
1064 u64 rx_ttl_1024_1518_frms;
1065 u64 rx_ttl_1519_4095_frms;
1066 u64 rx_ttl_4096_8191_frms;
1067 u64 rx_ttl_8192_max_frms;
1068 u64 rx_ttl_gt_max_frms;
1079 u64 rx_lost_ip_offload;
1080 u16 rx_various_discard;
1081 u16 rx_sleep_discard;
1083 u16 rx_queue_full_discard;
1088 * struct vxge_hw_xmac_stats - XMAC Statistics
1090 * @aggr_stats: Statistics on aggregate port(port 0, port 1)
1091 * @port_stats: Staticstics on ports(wire 0, wire 1, lag)
1092 * @vpath_tx_stats: Per vpath XMAC TX stats
1093 * @vpath_rx_stats: Per vpath XMAC RX stats
1097 struct vxge_hw_xmac_stats {
1098 struct vxge_hw_xmac_aggr_stats
1099 aggr_stats[VXGE_HW_MAC_MAX_MAC_PORT_ID];
1100 struct vxge_hw_xmac_port_stats
1101 port_stats[VXGE_HW_MAC_MAX_MAC_PORT_ID+1];
1102 struct vxge_hw_xmac_vpath_tx_stats
1103 vpath_tx_stats[VXGE_HW_MAX_VIRTUAL_PATHS];
1104 struct vxge_hw_xmac_vpath_rx_stats
1105 vpath_rx_stats[VXGE_HW_MAX_VIRTUAL_PATHS];
1109 * struct vxge_hw_vpath_stats_hw_info - Titan vpath hardware statistics.
1110 * @ini_num_mwr_sent: The number of PCI memory writes initiated by the PIC block
1111 * for the given VPATH
1112 * @ini_num_mrd_sent: The number of PCI memory reads initiated by the PIC block
1113 * @ini_num_cpl_rcvd: The number of PCI read completions received by the
1115 * @ini_num_mwr_byte_sent: The number of PCI memory write bytes sent by the PIC
1117 * @ini_num_cpl_byte_rcvd: The number of PCI read completion bytes received by
1119 * @wrcrdtarb_xoff: TBD
1120 * @rdcrdtarb_xoff: TBD
1121 * @vpath_genstats_count0: TBD
1122 * @vpath_genstats_count1: TBD
1123 * @vpath_genstats_count2: TBD
1124 * @vpath_genstats_count3: TBD
1125 * @vpath_genstats_count4: TBD
1126 * @vpath_gennstats_count5: TBD
1127 * @tx_stats: Transmit stats
1128 * @rx_stats: Receive stats
1129 * @prog_event_vnum1: Programmable statistic. Increments when internal logic
1130 * detects a certain event. See register
1131 * XMAC_STATS_CFG.EVENT_VNUM1_CFG for more information.
1132 * @prog_event_vnum0: Programmable statistic. Increments when internal logic
1133 * detects a certain event. See register
1134 * XMAC_STATS_CFG.EVENT_VNUM0_CFG for more information.
1135 * @prog_event_vnum3: Programmable statistic. Increments when internal logic
1136 * detects a certain event. See register
1137 * XMAC_STATS_CFG.EVENT_VNUM3_CFG for more information.
1138 * @prog_event_vnum2: Programmable statistic. Increments when internal logic
1139 * detects a certain event. See register
1140 * XMAC_STATS_CFG.EVENT_VNUM2_CFG for more information.
1141 * @rx_multi_cast_frame_discard: TBD
1142 * @rx_frm_transferred: TBD
1143 * @rxd_returned: TBD
1144 * @rx_mpa_len_fail_frms: Count of received frames
1145 * that fail the MPA length check
1146 * @rx_mpa_mrk_fail_frms: Count of received frames
1147 * that fail the MPA marker check
1148 * @rx_mpa_crc_fail_frms: Count of received frames that fail the MPA CRC check
1149 * @rx_permitted_frms: Count of frames that pass through the FAU and on to the
1150 * frame buffer (and subsequently to the host).
1151 * @rx_vp_reset_discarded_frms: Count of receive frames that are discarded
1152 * because the VPATH is in reset
1153 * @rx_wol_frms: Count of received "magic packet" frames. Stat increments
1154 * whenever the received frame matches the VPATH's Wake-on-LAN
1156 * @tx_vp_reset_discarded_frms: Count of transmit frames that are discarded
1157 * because the VPATH is in reset. Includes frames that are discarded
1158 * because the current VPIN does not match that VPIN of the frame
1160 * Titan vpath hardware statistics.
1162 struct vxge_hw_vpath_stats_hw_info {
1163 /*0x000*/ u32 ini_num_mwr_sent;
1164 /*0x004*/ u32 unused1;
1165 /*0x008*/ u32 ini_num_mrd_sent;
1166 /*0x00c*/ u32 unused2;
1167 /*0x010*/ u32 ini_num_cpl_rcvd;
1168 /*0x014*/ u32 unused3;
1169 /*0x018*/ u64 ini_num_mwr_byte_sent;
1170 /*0x020*/ u64 ini_num_cpl_byte_rcvd;
1171 /*0x028*/ u32 wrcrdtarb_xoff;
1172 /*0x02c*/ u32 unused4;
1173 /*0x030*/ u32 rdcrdtarb_xoff;
1174 /*0x034*/ u32 unused5;
1175 /*0x038*/ u32 vpath_genstats_count0;
1176 /*0x03c*/ u32 vpath_genstats_count1;
1177 /*0x040*/ u32 vpath_genstats_count2;
1178 /*0x044*/ u32 vpath_genstats_count3;
1179 /*0x048*/ u32 vpath_genstats_count4;
1180 /*0x04c*/ u32 unused6;
1181 /*0x050*/ u32 vpath_genstats_count5;
1182 /*0x054*/ u32 unused7;
1183 /*0x058*/ struct vxge_hw_xmac_vpath_tx_stats tx_stats;
1184 /*0x0e8*/ struct vxge_hw_xmac_vpath_rx_stats rx_stats;
1185 /*0x220*/ u64 unused9;
1186 /*0x228*/ u32 prog_event_vnum1;
1187 /*0x22c*/ u32 prog_event_vnum0;
1188 /*0x230*/ u32 prog_event_vnum3;
1189 /*0x234*/ u32 prog_event_vnum2;
1190 /*0x238*/ u16 rx_multi_cast_frame_discard;
1191 /*0x23a*/ u8 unused10[6];
1192 /*0x240*/ u32 rx_frm_transferred;
1193 /*0x244*/ u32 unused11;
1194 /*0x248*/ u16 rxd_returned;
1195 /*0x24a*/ u8 unused12[6];
1196 /*0x252*/ u16 rx_mpa_len_fail_frms;
1197 /*0x254*/ u16 rx_mpa_mrk_fail_frms;
1198 /*0x256*/ u16 rx_mpa_crc_fail_frms;
1199 /*0x258*/ u16 rx_permitted_frms;
1200 /*0x25c*/ u64 rx_vp_reset_discarded_frms;
1201 /*0x25e*/ u64 rx_wol_frms;
1202 /*0x260*/ u64 tx_vp_reset_discarded_frms;
1207 * struct vxge_hw_device_stats_mrpcim_info - Titan mrpcim hardware statistics.
1208 * @pic.ini_rd_drop 0x0000 4 Number of DMA reads initiated
1209 * by the adapter that were discarded because the VPATH is out of service
1210 * @pic.ini_wr_drop 0x0004 4 Number of DMA writes initiated by the
1211 * adapter that were discared because the VPATH is out of service
1212 * @pic.wrcrdtarb_ph_crdt_depleted[vplane0] 0x0008 4 Number of times
1213 * the posted header credits for upstream PCI writes were depleted
1214 * @pic.wrcrdtarb_ph_crdt_depleted[vplane1] 0x0010 4 Number of times
1215 * the posted header credits for upstream PCI writes were depleted
1216 * @pic.wrcrdtarb_ph_crdt_depleted[vplane2] 0x0018 4 Number of times
1217 * the posted header credits for upstream PCI writes were depleted
1218 * @pic.wrcrdtarb_ph_crdt_depleted[vplane3] 0x0020 4 Number of times
1219 * the posted header credits for upstream PCI writes were depleted
1220 * @pic.wrcrdtarb_ph_crdt_depleted[vplane4] 0x0028 4 Number of times
1221 * the posted header credits for upstream PCI writes were depleted
1222 * @pic.wrcrdtarb_ph_crdt_depleted[vplane5] 0x0030 4 Number of times
1223 * the posted header credits for upstream PCI writes were depleted
1224 * @pic.wrcrdtarb_ph_crdt_depleted[vplane6] 0x0038 4 Number of times
1225 * the posted header credits for upstream PCI writes were depleted
1226 * @pic.wrcrdtarb_ph_crdt_depleted[vplane7] 0x0040 4 Number of times
1227 * the posted header credits for upstream PCI writes were depleted
1228 * @pic.wrcrdtarb_ph_crdt_depleted[vplane8] 0x0048 4 Number of times
1229 * the posted header credits for upstream PCI writes were depleted
1230 * @pic.wrcrdtarb_ph_crdt_depleted[vplane9] 0x0050 4 Number of times
1231 * the posted header credits for upstream PCI writes were depleted
1232 * @pic.wrcrdtarb_ph_crdt_depleted[vplane10] 0x0058 4 Number of times
1233 * the posted header credits for upstream PCI writes were depleted
1234 * @pic.wrcrdtarb_ph_crdt_depleted[vplane11] 0x0060 4 Number of times
1235 * the posted header credits for upstream PCI writes were depleted
1236 * @pic.wrcrdtarb_ph_crdt_depleted[vplane12] 0x0068 4 Number of times
1237 * the posted header credits for upstream PCI writes were depleted
1238 * @pic.wrcrdtarb_ph_crdt_depleted[vplane13] 0x0070 4 Number of times
1239 * the posted header credits for upstream PCI writes were depleted
1240 * @pic.wrcrdtarb_ph_crdt_depleted[vplane14] 0x0078 4 Number of times
1241 * the posted header credits for upstream PCI writes were depleted
1242 * @pic.wrcrdtarb_ph_crdt_depleted[vplane15] 0x0080 4 Number of times
1243 * the posted header credits for upstream PCI writes were depleted
1244 * @pic.wrcrdtarb_ph_crdt_depleted[vplane16] 0x0088 4 Number of times
1245 * the posted header credits for upstream PCI writes were depleted
1246 * @pic.wrcrdtarb_pd_crdt_depleted[vplane0] 0x0090 4 Number of times
1247 * the posted data credits for upstream PCI writes were depleted
1248 * @pic.wrcrdtarb_pd_crdt_depleted[vplane1] 0x0098 4 Number of times
1249 * the posted data credits for upstream PCI writes were depleted
1250 * @pic.wrcrdtarb_pd_crdt_depleted[vplane2] 0x00a0 4 Number of times
1251 * the posted data credits for upstream PCI writes were depleted
1252 * @pic.wrcrdtarb_pd_crdt_depleted[vplane3] 0x00a8 4 Number of times
1253 * the posted data credits for upstream PCI writes were depleted
1254 * @pic.wrcrdtarb_pd_crdt_depleted[vplane4] 0x00b0 4 Number of times
1255 * the posted data credits for upstream PCI writes were depleted
1256 * @pic.wrcrdtarb_pd_crdt_depleted[vplane5] 0x00b8 4 Number of times
1257 * the posted data credits for upstream PCI writes were depleted
1258 * @pic.wrcrdtarb_pd_crdt_depleted[vplane6] 0x00c0 4 Number of times
1259 * the posted data credits for upstream PCI writes were depleted
1260 * @pic.wrcrdtarb_pd_crdt_depleted[vplane7] 0x00c8 4 Number of times
1261 * the posted data credits for upstream PCI writes were depleted
1262 * @pic.wrcrdtarb_pd_crdt_depleted[vplane8] 0x00d0 4 Number of times
1263 * the posted data credits for upstream PCI writes were depleted
1264 * @pic.wrcrdtarb_pd_crdt_depleted[vplane9] 0x00d8 4 Number of times
1265 * the posted data credits for upstream PCI writes were depleted
1266 * @pic.wrcrdtarb_pd_crdt_depleted[vplane10] 0x00e0 4 Number of times
1267 * the posted data credits for upstream PCI writes were depleted
1268 * @pic.wrcrdtarb_pd_crdt_depleted[vplane11] 0x00e8 4 Number of times
1269 * the posted data credits for upstream PCI writes were depleted
1270 * @pic.wrcrdtarb_pd_crdt_depleted[vplane12] 0x00f0 4 Number of times
1271 * the posted data credits for upstream PCI writes were depleted
1272 * @pic.wrcrdtarb_pd_crdt_depleted[vplane13] 0x00f8 4 Number of times
1273 * the posted data credits for upstream PCI writes were depleted
1274 * @pic.wrcrdtarb_pd_crdt_depleted[vplane14] 0x0100 4 Number of times
1275 * the posted data credits for upstream PCI writes were depleted
1276 * @pic.wrcrdtarb_pd_crdt_depleted[vplane15] 0x0108 4 Number of times
1277 * the posted data credits for upstream PCI writes were depleted
1278 * @pic.wrcrdtarb_pd_crdt_depleted[vplane16] 0x0110 4 Number of times
1279 * the posted data credits for upstream PCI writes were depleted
1280 * @pic.rdcrdtarb_nph_crdt_depleted[vplane0] 0x0118 4 Number of times
1281 * the non-posted header credits for upstream PCI reads were depleted
1282 * @pic.rdcrdtarb_nph_crdt_depleted[vplane1] 0x0120 4 Number of times
1283 * the non-posted header credits for upstream PCI reads were depleted
1284 * @pic.rdcrdtarb_nph_crdt_depleted[vplane2] 0x0128 4 Number of times
1285 * the non-posted header credits for upstream PCI reads were depleted
1286 * @pic.rdcrdtarb_nph_crdt_depleted[vplane3] 0x0130 4 Number of times
1287 * the non-posted header credits for upstream PCI reads were depleted
1288 * @pic.rdcrdtarb_nph_crdt_depleted[vplane4] 0x0138 4 Number of times
1289 * the non-posted header credits for upstream PCI reads were depleted
1290 * @pic.rdcrdtarb_nph_crdt_depleted[vplane5] 0x0140 4 Number of times
1291 * the non-posted header credits for upstream PCI reads were depleted
1292 * @pic.rdcrdtarb_nph_crdt_depleted[vplane6] 0x0148 4 Number of times
1293 * the non-posted header credits for upstream PCI reads were depleted
1294 * @pic.rdcrdtarb_nph_crdt_depleted[vplane7] 0x0150 4 Number of times
1295 * the non-posted header credits for upstream PCI reads were depleted
1296 * @pic.rdcrdtarb_nph_crdt_depleted[vplane8] 0x0158 4 Number of times
1297 * the non-posted header credits for upstream PCI reads were depleted
1298 * @pic.rdcrdtarb_nph_crdt_depleted[vplane9] 0x0160 4 Number of times
1299 * the non-posted header credits for upstream PCI reads were depleted
1300 * @pic.rdcrdtarb_nph_crdt_depleted[vplane10] 0x0168 4 Number of times
1301 * the non-posted header credits for upstream PCI reads were depleted
1302 * @pic.rdcrdtarb_nph_crdt_depleted[vplane11] 0x0170 4 Number of times
1303 * the non-posted header credits for upstream PCI reads were depleted
1304 * @pic.rdcrdtarb_nph_crdt_depleted[vplane12] 0x0178 4 Number of times
1305 * the non-posted header credits for upstream PCI reads were depleted
1306 * @pic.rdcrdtarb_nph_crdt_depleted[vplane13] 0x0180 4 Number of times
1307 * the non-posted header credits for upstream PCI reads were depleted
1308 * @pic.rdcrdtarb_nph_crdt_depleted[vplane14] 0x0188 4 Number of times
1309 * the non-posted header credits for upstream PCI reads were depleted
1310 * @pic.rdcrdtarb_nph_crdt_depleted[vplane15] 0x0190 4 Number of times
1311 * the non-posted header credits for upstream PCI reads were depleted
1312 * @pic.rdcrdtarb_nph_crdt_depleted[vplane16] 0x0198 4 Number of times
1313 * the non-posted header credits for upstream PCI reads were depleted
1314 * @pic.ini_rd_vpin_drop 0x01a0 4 Number of DMA reads initiated by
1315 * the adapter that were discarded because the VPATH instance number does
1317 * @pic.ini_wr_vpin_drop 0x01a4 4 Number of DMA writes initiated
1318 * by the adapter that were discarded because the VPATH instance number
1320 * @pic.genstats_count0 0x01a8 4 Configurable statistic #1. Refer
1321 * to the GENSTATS0_CFG for information on configuring this statistic
1322 * @pic.genstats_count1 0x01ac 4 Configurable statistic #2. Refer
1323 * to the GENSTATS1_CFG for information on configuring this statistic
1324 * @pic.genstats_count2 0x01b0 4 Configurable statistic #3. Refer
1325 * to the GENSTATS2_CFG for information on configuring this statistic
1326 * @pic.genstats_count3 0x01b4 4 Configurable statistic #4. Refer
1327 * to the GENSTATS3_CFG for information on configuring this statistic
1328 * @pic.genstats_count4 0x01b8 4 Configurable statistic #5. Refer
1329 * to the GENSTATS4_CFG for information on configuring this statistic
1330 * @pic.genstats_count5 0x01c0 4 Configurable statistic #6. Refer
1331 * to the GENSTATS5_CFG for information on configuring this statistic
1332 * @pci.rstdrop_cpl 0x01c8 4
1333 * @pci.rstdrop_msg 0x01cc 4
1334 * @pci.rstdrop_client1 0x01d0 4
1335 * @pci.rstdrop_client0 0x01d4 4
1336 * @pci.rstdrop_client2 0x01d8 4
1337 * @pci.depl_cplh[vplane0] 0x01e2 2 Number of times completion
1338 * header credits were depleted
1339 * @pci.depl_nph[vplane0] 0x01e4 2 Number of times non posted
1340 * header credits were depleted
1341 * @pci.depl_ph[vplane0] 0x01e6 2 Number of times the posted
1342 * header credits were depleted
1343 * @pci.depl_cplh[vplane1] 0x01ea 2
1344 * @pci.depl_nph[vplane1] 0x01ec 2
1345 * @pci.depl_ph[vplane1] 0x01ee 2
1346 * @pci.depl_cplh[vplane2] 0x01f2 2
1347 * @pci.depl_nph[vplane2] 0x01f4 2
1348 * @pci.depl_ph[vplane2] 0x01f6 2
1349 * @pci.depl_cplh[vplane3] 0x01fa 2
1350 * @pci.depl_nph[vplane3] 0x01fc 2
1351 * @pci.depl_ph[vplane3] 0x01fe 2
1352 * @pci.depl_cplh[vplane4] 0x0202 2
1353 * @pci.depl_nph[vplane4] 0x0204 2
1354 * @pci.depl_ph[vplane4] 0x0206 2
1355 * @pci.depl_cplh[vplane5] 0x020a 2
1356 * @pci.depl_nph[vplane5] 0x020c 2
1357 * @pci.depl_ph[vplane5] 0x020e 2
1358 * @pci.depl_cplh[vplane6] 0x0212 2
1359 * @pci.depl_nph[vplane6] 0x0214 2
1360 * @pci.depl_ph[vplane6] 0x0216 2
1361 * @pci.depl_cplh[vplane7] 0x021a 2
1362 * @pci.depl_nph[vplane7] 0x021c 2
1363 * @pci.depl_ph[vplane7] 0x021e 2
1364 * @pci.depl_cplh[vplane8] 0x0222 2
1365 * @pci.depl_nph[vplane8] 0x0224 2
1366 * @pci.depl_ph[vplane8] 0x0226 2
1367 * @pci.depl_cplh[vplane9] 0x022a 2
1368 * @pci.depl_nph[vplane9] 0x022c 2
1369 * @pci.depl_ph[vplane9] 0x022e 2
1370 * @pci.depl_cplh[vplane10] 0x0232 2
1371 * @pci.depl_nph[vplane10] 0x0234 2
1372 * @pci.depl_ph[vplane10] 0x0236 2
1373 * @pci.depl_cplh[vplane11] 0x023a 2
1374 * @pci.depl_nph[vplane11] 0x023c 2
1375 * @pci.depl_ph[vplane11] 0x023e 2
1376 * @pci.depl_cplh[vplane12] 0x0242 2
1377 * @pci.depl_nph[vplane12] 0x0244 2
1378 * @pci.depl_ph[vplane12] 0x0246 2
1379 * @pci.depl_cplh[vplane13] 0x024a 2
1380 * @pci.depl_nph[vplane13] 0x024c 2
1381 * @pci.depl_ph[vplane13] 0x024e 2
1382 * @pci.depl_cplh[vplane14] 0x0252 2
1383 * @pci.depl_nph[vplane14] 0x0254 2
1384 * @pci.depl_ph[vplane14] 0x0256 2
1385 * @pci.depl_cplh[vplane15] 0x025a 2
1386 * @pci.depl_nph[vplane15] 0x025c 2
1387 * @pci.depl_ph[vplane15] 0x025e 2
1388 * @pci.depl_cplh[vplane16] 0x0262 2
1389 * @pci.depl_nph[vplane16] 0x0264 2
1390 * @pci.depl_ph[vplane16] 0x0266 2
1391 * @pci.depl_cpld[vplane0] 0x026a 2 Number of times completion data
1392 * credits were depleted
1393 * @pci.depl_npd[vplane0] 0x026c 2 Number of times non posted data
1394 * credits were depleted
1395 * @pci.depl_pd[vplane0] 0x026e 2 Number of times the posted data
1396 * credits were depleted
1397 * @pci.depl_cpld[vplane1] 0x0272 2
1398 * @pci.depl_npd[vplane1] 0x0274 2
1399 * @pci.depl_pd[vplane1] 0x0276 2
1400 * @pci.depl_cpld[vplane2] 0x027a 2
1401 * @pci.depl_npd[vplane2] 0x027c 2
1402 * @pci.depl_pd[vplane2] 0x027e 2
1403 * @pci.depl_cpld[vplane3] 0x0282 2
1404 * @pci.depl_npd[vplane3] 0x0284 2
1405 * @pci.depl_pd[vplane3] 0x0286 2
1406 * @pci.depl_cpld[vplane4] 0x028a 2
1407 * @pci.depl_npd[vplane4] 0x028c 2
1408 * @pci.depl_pd[vplane4] 0x028e 2
1409 * @pci.depl_cpld[vplane5] 0x0292 2
1410 * @pci.depl_npd[vplane5] 0x0294 2
1411 * @pci.depl_pd[vplane5] 0x0296 2
1412 * @pci.depl_cpld[vplane6] 0x029a 2
1413 * @pci.depl_npd[vplane6] 0x029c 2
1414 * @pci.depl_pd[vplane6] 0x029e 2
1415 * @pci.depl_cpld[vplane7] 0x02a2 2
1416 * @pci.depl_npd[vplane7] 0x02a4 2
1417 * @pci.depl_pd[vplane7] 0x02a6 2
1418 * @pci.depl_cpld[vplane8] 0x02aa 2
1419 * @pci.depl_npd[vplane8] 0x02ac 2
1420 * @pci.depl_pd[vplane8] 0x02ae 2
1421 * @pci.depl_cpld[vplane9] 0x02b2 2
1422 * @pci.depl_npd[vplane9] 0x02b4 2
1423 * @pci.depl_pd[vplane9] 0x02b6 2
1424 * @pci.depl_cpld[vplane10] 0x02ba 2
1425 * @pci.depl_npd[vplane10] 0x02bc 2
1426 * @pci.depl_pd[vplane10] 0x02be 2
1427 * @pci.depl_cpld[vplane11] 0x02c2 2
1428 * @pci.depl_npd[vplane11] 0x02c4 2
1429 * @pci.depl_pd[vplane11] 0x02c6 2
1430 * @pci.depl_cpld[vplane12] 0x02ca 2
1431 * @pci.depl_npd[vplane12] 0x02cc 2
1432 * @pci.depl_pd[vplane12] 0x02ce 2
1433 * @pci.depl_cpld[vplane13] 0x02d2 2
1434 * @pci.depl_npd[vplane13] 0x02d4 2
1435 * @pci.depl_pd[vplane13] 0x02d6 2
1436 * @pci.depl_cpld[vplane14] 0x02da 2
1437 * @pci.depl_npd[vplane14] 0x02dc 2
1438 * @pci.depl_pd[vplane14] 0x02de 2
1439 * @pci.depl_cpld[vplane15] 0x02e2 2
1440 * @pci.depl_npd[vplane15] 0x02e4 2
1441 * @pci.depl_pd[vplane15] 0x02e6 2
1442 * @pci.depl_cpld[vplane16] 0x02ea 2
1443 * @pci.depl_npd[vplane16] 0x02ec 2
1444 * @pci.depl_pd[vplane16] 0x02ee 2
1447 * @xgmac.global_prog_event_gnum0 0x0ae0 8 Programmable statistic.
1448 * Increments when internal logic detects a certain event. See register
1449 * XMAC_STATS_GLOBAL_CFG.EVENT_GNUM0_CFG for more information.
1450 * @xgmac.global_prog_event_gnum1 0x0ae8 8 Programmable statistic.
1451 * Increments when internal logic detects a certain event. See register
1452 * XMAC_STATS_GLOBAL_CFG.EVENT_GNUM1_CFG for more information.
1453 * @xgmac.orp_lro_events 0x0af8 8
1454 * @xgmac.orp_bs_events 0x0b00 8
1455 * @xgmac.orp_iwarp_events 0x0b08 8
1456 * @xgmac.tx_permitted_frms 0x0b14 4
1457 * @xgmac.port2_tx_any_frms 0x0b1d 1
1458 * @xgmac.port1_tx_any_frms 0x0b1e 1
1459 * @xgmac.port0_tx_any_frms 0x0b1f 1
1460 * @xgmac.port2_rx_any_frms 0x0b25 1
1461 * @xgmac.port1_rx_any_frms 0x0b26 1
1462 * @xgmac.port0_rx_any_frms 0x0b27 1
1464 * Titan mrpcim hardware statistics.
1466 struct vxge_hw_device_stats_mrpcim_info {
1467 /*0x0000*/ u32 pic_ini_rd_drop;
1468 /*0x0004*/ u32 pic_ini_wr_drop;
1470 /*0x0000*/ u32 pic_wrcrdtarb_ph_crdt_depleted;
1471 /*0x0004*/ u32 unused1;
1472 } pic_wrcrdtarb_ph_crdt_depleted_vplane[17];
1474 /*0x0000*/ u32 pic_wrcrdtarb_pd_crdt_depleted;
1475 /*0x0004*/ u32 unused2;
1476 } pic_wrcrdtarb_pd_crdt_depleted_vplane[17];
1478 /*0x0000*/ u32 pic_rdcrdtarb_nph_crdt_depleted;
1479 /*0x0004*/ u32 unused3;
1480 } pic_rdcrdtarb_nph_crdt_depleted_vplane[17];
1481 /*0x01a0*/ u32 pic_ini_rd_vpin_drop;
1482 /*0x01a4*/ u32 pic_ini_wr_vpin_drop;
1483 /*0x01a8*/ u32 pic_genstats_count0;
1484 /*0x01ac*/ u32 pic_genstats_count1;
1485 /*0x01b0*/ u32 pic_genstats_count2;
1486 /*0x01b4*/ u32 pic_genstats_count3;
1487 /*0x01b8*/ u32 pic_genstats_count4;
1488 /*0x01bc*/ u32 unused4;
1489 /*0x01c0*/ u32 pic_genstats_count5;
1490 /*0x01c4*/ u32 unused5;
1491 /*0x01c8*/ u32 pci_rstdrop_cpl;
1492 /*0x01cc*/ u32 pci_rstdrop_msg;
1493 /*0x01d0*/ u32 pci_rstdrop_client1;
1494 /*0x01d4*/ u32 pci_rstdrop_client0;
1495 /*0x01d8*/ u32 pci_rstdrop_client2;
1496 /*0x01dc*/ u32 unused6;
1498 /*0x0000*/ u16 unused7;
1499 /*0x0002*/ u16 pci_depl_cplh;
1500 /*0x0004*/ u16 pci_depl_nph;
1501 /*0x0006*/ u16 pci_depl_ph;
1502 } pci_depl_h_vplane[17];
1504 /*0x0000*/ u16 unused8;
1505 /*0x0002*/ u16 pci_depl_cpld;
1506 /*0x0004*/ u16 pci_depl_npd;
1507 /*0x0006*/ u16 pci_depl_pd;
1508 } pci_depl_d_vplane[17];
1509 /*0x02f0*/ struct vxge_hw_xmac_port_stats xgmac_port[3];
1510 /*0x0a10*/ struct vxge_hw_xmac_aggr_stats xgmac_aggr[2];
1511 /*0x0ae0*/ u64 xgmac_global_prog_event_gnum0;
1512 /*0x0ae8*/ u64 xgmac_global_prog_event_gnum1;
1513 /*0x0af0*/ u64 unused7;
1514 /*0x0af8*/ u64 unused8;
1515 /*0x0b00*/ u64 unused9;
1516 /*0x0b08*/ u64 unused10;
1517 /*0x0b10*/ u32 unused11;
1518 /*0x0b14*/ u32 xgmac_tx_permitted_frms;
1519 /*0x0b18*/ u32 unused12;
1520 /*0x0b1c*/ u8 unused13;
1521 /*0x0b1d*/ u8 xgmac_port2_tx_any_frms;
1522 /*0x0b1e*/ u8 xgmac_port1_tx_any_frms;
1523 /*0x0b1f*/ u8 xgmac_port0_tx_any_frms;
1524 /*0x0b20*/ u32 unused14;
1525 /*0x0b24*/ u8 unused15;
1526 /*0x0b25*/ u8 xgmac_port2_rx_any_frms;
1527 /*0x0b26*/ u8 xgmac_port1_rx_any_frms;
1528 /*0x0b27*/ u8 xgmac_port0_rx_any_frms;
1532 * struct vxge_hw_device_stats_hw_info - Titan hardware statistics.
1533 * @vpath_info: VPath statistics
1534 * @vpath_info_sav: Vpath statistics saved
1536 * Titan hardware statistics.
1538 struct vxge_hw_device_stats_hw_info {
1539 struct vxge_hw_vpath_stats_hw_info
1540 *vpath_info[VXGE_HW_MAX_VIRTUAL_PATHS];
1541 struct vxge_hw_vpath_stats_hw_info
1542 vpath_info_sav[VXGE_HW_MAX_VIRTUAL_PATHS];
1546 * struct vxge_hw_vpath_stats_sw_common_info - HW common
1547 * statistics for queues.
1548 * @full_cnt: Number of times the queue was full
1549 * @usage_cnt: usage count.
1550 * @usage_max: Maximum usage
1551 * @reserve_free_swaps_cnt: Reserve/free swap counter. Internal usage.
1552 * @total_compl_cnt: Total descriptor completion count.
1555 * See also: struct vxge_hw_vpath_stats_sw_fifo_info{},
1556 * struct vxge_hw_vpath_stats_sw_ring_info{},
1558 struct vxge_hw_vpath_stats_sw_common_info {
1562 u32 reserve_free_swaps_cnt;
1563 u32 total_compl_cnt;
1567 * struct vxge_hw_vpath_stats_sw_fifo_info - HW fifo statistics
1568 * @common_stats: Common counters for all queues
1569 * @total_posts: Total number of postings on the queue.
1570 * @total_buffers: Total number of buffers posted.
1571 * @txd_t_code_err_cnt: Array of transmit transfer codes. The position
1572 * (index) in this array reflects the transfer code type, for instance
1573 * 0xA - "loss of link".
1574 * Value txd_t_code_err_cnt[i] reflects the
1575 * number of times the corresponding transfer code was encountered.
1578 * See also: struct vxge_hw_vpath_stats_sw_common_info{},
1579 * struct vxge_hw_vpath_stats_sw_ring_info{},
1581 struct vxge_hw_vpath_stats_sw_fifo_info {
1582 struct vxge_hw_vpath_stats_sw_common_info common_stats;
1585 u32 txd_t_code_err_cnt[VXGE_HW_DTR_MAX_T_CODE];
1589 * struct vxge_hw_vpath_stats_sw_ring_info - HW ring statistics
1590 * @common_stats: Common counters for all queues
1591 * @rxd_t_code_err_cnt: Array of receive transfer codes. The position
1592 * (index) in this array reflects the transfer code type,
1594 * 0x7 - for "invalid receive buffer size", or 0x8 - for ECC.
1595 * Value rxd_t_code_err_cnt[i] reflects the
1596 * number of times the corresponding transfer code was encountered.
1599 * See also: struct vxge_hw_vpath_stats_sw_common_info{},
1600 * struct vxge_hw_vpath_stats_sw_fifo_info{},
1602 struct vxge_hw_vpath_stats_sw_ring_info {
1603 struct vxge_hw_vpath_stats_sw_common_info common_stats;
1604 u32 rxd_t_code_err_cnt[VXGE_HW_DTR_MAX_T_CODE];
1609 * struct vxge_hw_vpath_stats_sw_err - HW vpath error statistics
1611 * @network_sustained_fault:
1612 * @network_sustained_ok:
1613 * @kdfcctl_fifo0_overwrite:
1614 * @kdfcctl_fifo0_poison:
1615 * @kdfcctl_fifo0_dma_error:
1616 * @dblgen_fifo0_overflow:
1617 * @statsb_pif_chain_error:
1618 * @statsb_drop_timeout:
1619 * @target_illegal_access:
1622 * @prc_rxdcm_sc_err:
1623 * @prc_rxdcm_sc_abort:
1624 * @prc_quanta_size_err:
1626 * HW vpath error statistics
1628 struct vxge_hw_vpath_stats_sw_err {
1630 u32 network_sustained_fault;
1631 u32 network_sustained_ok;
1632 u32 kdfcctl_fifo0_overwrite;
1633 u32 kdfcctl_fifo0_poison;
1634 u32 kdfcctl_fifo0_dma_error;
1635 u32 dblgen_fifo0_overflow;
1636 u32 statsb_pif_chain_error;
1637 u32 statsb_drop_timeout;
1638 u32 target_illegal_access;
1641 u32 prc_rxdcm_sc_err;
1642 u32 prc_rxdcm_sc_abort;
1643 u32 prc_quanta_size_err;
1647 * struct vxge_hw_vpath_stats_sw_info - HW vpath sw statistics
1648 * @soft_reset_cnt: Number of times soft reset is done on this vpath.
1649 * @error_stats: error counters for the vpath
1650 * @ring_stats: counters for ring belonging to the vpath
1651 * @fifo_stats: counters for fifo belonging to the vpath
1653 * HW vpath sw statistics
1654 * See also: struct vxge_hw_device_info{} }.
1656 struct vxge_hw_vpath_stats_sw_info {
1658 struct vxge_hw_vpath_stats_sw_err error_stats;
1659 struct vxge_hw_vpath_stats_sw_ring_info ring_stats;
1660 struct vxge_hw_vpath_stats_sw_fifo_info fifo_stats;
1664 * struct vxge_hw_device_stats_sw_info - HW own per-device statistics.
1666 * @not_traffic_intr_cnt: Number of times the host was interrupted
1667 * without new completions.
1668 * "Non-traffic interrupt counter".
1669 * @traffic_intr_cnt: Number of traffic interrupts for the device.
1670 * @total_intr_cnt: Total number of traffic interrupts for the device.
1671 * @total_intr_cnt == @traffic_intr_cnt +
1672 * @not_traffic_intr_cnt
1673 * @soft_reset_cnt: Number of times soft reset is done on this device.
1674 * @vpath_info: please see struct vxge_hw_vpath_stats_sw_info{}
1675 * HW per-device statistics.
1677 struct vxge_hw_device_stats_sw_info {
1678 u32 not_traffic_intr_cnt;
1679 u32 traffic_intr_cnt;
1682 struct vxge_hw_vpath_stats_sw_info
1683 vpath_info[VXGE_HW_MAX_VIRTUAL_PATHS];
1687 * struct vxge_hw_device_stats_sw_err - HW device error statistics.
1688 * @vpath_alarms: Number of vpath alarms
1690 * HW Device error stats
1692 struct vxge_hw_device_stats_sw_err {
1697 * struct vxge_hw_device_stats - Contains HW per-device statistics,
1699 * @devh: HW device handle.
1700 * @dma_addr: DMA addres of the %hw_info. Given to device to fill-in the stats.
1701 * @hw_info_dmah: DMA handle used to map hw statistics onto the device memory
1703 * @hw_info_dma_acch: One more DMA handle used subsequently to free the
1704 * DMA object. Note that this and the previous handle have
1705 * physical meaning for Solaris; on Windows and Linux the
1706 * corresponding value will be simply pointer to PCI device.
1708 * @hw_dev_info_stats: Titan statistics maintained by the hardware.
1709 * @sw_dev_info_stats: HW's "soft" device informational statistics, e.g. number
1710 * of completions per interrupt.
1711 * @sw_dev_err_stats: HW's "soft" device error statistics.
1713 * Structure-container of HW per-device statistics. Note that per-channel
1714 * statistics are kept in separate structures under HW's fifo and ring
1717 struct vxge_hw_device_stats {
1719 struct __vxge_hw_device *devh;
1721 /* HW device hardware statistics */
1722 struct vxge_hw_device_stats_hw_info hw_dev_info_stats;
1724 /* HW device "soft" stats */
1725 struct vxge_hw_device_stats_sw_err sw_dev_err_stats;
1726 struct vxge_hw_device_stats_sw_info sw_dev_info_stats;
1730 enum vxge_hw_status vxge_hw_device_hw_stats_enable(
1731 struct __vxge_hw_device *devh);
1733 enum vxge_hw_status vxge_hw_device_stats_get(
1734 struct __vxge_hw_device *devh,
1735 struct vxge_hw_device_stats_hw_info *hw_stats);
1737 enum vxge_hw_status vxge_hw_driver_stats_get(
1738 struct __vxge_hw_device *devh,
1739 struct vxge_hw_device_stats_sw_info *sw_stats);
1741 enum vxge_hw_status vxge_hw_mrpcim_stats_enable(struct __vxge_hw_device *devh);
1743 enum vxge_hw_status vxge_hw_mrpcim_stats_disable(struct __vxge_hw_device *devh);
1746 vxge_hw_mrpcim_stats_access(
1747 struct __vxge_hw_device *devh,
1754 vxge_hw_device_xmac_aggr_stats_get(struct __vxge_hw_device *devh, u32 port,
1755 struct vxge_hw_xmac_aggr_stats *aggr_stats);
1758 vxge_hw_device_xmac_port_stats_get(struct __vxge_hw_device *devh, u32 port,
1759 struct vxge_hw_xmac_port_stats *port_stats);
1762 vxge_hw_device_xmac_stats_get(struct __vxge_hw_device *devh,
1763 struct vxge_hw_xmac_stats *xmac_stats);
1766 * enum enum vxge_hw_mgmt_reg_type - Register types.
1768 * @vxge_hw_mgmt_reg_type_legacy: Legacy registers
1769 * @vxge_hw_mgmt_reg_type_toc: TOC Registers
1770 * @vxge_hw_mgmt_reg_type_common: Common Registers
1771 * @vxge_hw_mgmt_reg_type_mrpcim: mrpcim registers
1772 * @vxge_hw_mgmt_reg_type_srpcim: srpcim registers
1773 * @vxge_hw_mgmt_reg_type_vpmgmt: vpath management registers
1774 * @vxge_hw_mgmt_reg_type_vpath: vpath registers
1776 * Register type enumaration
1778 enum vxge_hw_mgmt_reg_type {
1779 vxge_hw_mgmt_reg_type_legacy = 0,
1780 vxge_hw_mgmt_reg_type_toc = 1,
1781 vxge_hw_mgmt_reg_type_common = 2,
1782 vxge_hw_mgmt_reg_type_mrpcim = 3,
1783 vxge_hw_mgmt_reg_type_srpcim = 4,
1784 vxge_hw_mgmt_reg_type_vpmgmt = 5,
1785 vxge_hw_mgmt_reg_type_vpath = 6
1789 vxge_hw_mgmt_reg_read(struct __vxge_hw_device *devh,
1790 enum vxge_hw_mgmt_reg_type type,
1796 vxge_hw_mgmt_reg_write(struct __vxge_hw_device *devh,
1797 enum vxge_hw_mgmt_reg_type type,
1803 * enum enum vxge_hw_rxd_state - Descriptor (RXD) state.
1804 * @VXGE_HW_RXD_STATE_NONE: Invalid state.
1805 * @VXGE_HW_RXD_STATE_AVAIL: Descriptor is available for reservation.
1806 * @VXGE_HW_RXD_STATE_POSTED: Descriptor is posted for processing by the
1808 * @VXGE_HW_RXD_STATE_FREED: Descriptor is free and can be reused for
1809 * filling-in and posting later.
1811 * Titan/HW descriptor states.
1814 enum vxge_hw_rxd_state {
1815 VXGE_HW_RXD_STATE_NONE = 0,
1816 VXGE_HW_RXD_STATE_AVAIL = 1,
1817 VXGE_HW_RXD_STATE_POSTED = 2,
1818 VXGE_HW_RXD_STATE_FREED = 3
1822 * struct vxge_hw_ring_rxd_info - Extended information associated with a
1823 * completed ring descriptor.
1824 * @syn_flag: SYN flag
1826 * @fast_path_eligible: Fast Path Eligible flag
1827 * @l3_cksum: in L3 checksum is valid
1828 * @l3_cksum: Result of IP checksum check (by Titan hardware).
1829 * This field containing VXGE_HW_L3_CKSUM_OK would mean that
1830 * the checksum is correct, otherwise - the datagram is
1832 * @l4_cksum: in L4 checksum is valid
1833 * @l4_cksum: Result of TCP/UDP checksum check (by Titan hardware).
1834 * This field containing VXGE_HW_L4_CKSUM_OK would mean that
1835 * the checksum is correct. Otherwise - the packet is
1837 * @frame: Zero or more of enum vxge_hw_frame_type flags.
1838 * See enum vxge_hw_frame_type{}.
1839 * @proto: zero or more of enum vxge_hw_frame_proto flags. Reporting bits for
1840 * various higher-layer protocols, including (but note restricted to)
1841 * TCP and UDP. See enum vxge_hw_frame_proto{}.
1842 * @is_vlan: If vlan tag is valid
1843 * @vlan: VLAN tag extracted from the received frame.
1844 * @rth_bucket: RTH bucket
1845 * @rth_it_hit: Set, If RTH hash value calculated by the Titan hardware
1846 * has a matching entry in the Indirection table.
1847 * @rth_spdm_hit: Set, If RTH hash value calculated by the Titan hardware
1848 * has a matching entry in the Socket Pair Direct Match table.
1849 * @rth_hash_type: RTH hash code of the function used to calculate the hash.
1850 * @rth_value: Receive Traffic Hashing(RTH) hash value. Produced by Titan
1851 * hardware if RTH is enabled.
1853 struct vxge_hw_ring_rxd_info {
1856 u32 fast_path_eligible;
1873 * enum enum vxge_hw_ring_hash_type - RTH hash types
1874 * @VXGE_HW_RING_HASH_TYPE_NONE: No Hash
1875 * @VXGE_HW_RING_HASH_TYPE_TCP_IPV4: TCP IPv4
1876 * @VXGE_HW_RING_HASH_TYPE_UDP_IPV4: UDP IPv4
1877 * @VXGE_HW_RING_HASH_TYPE_IPV4: IPv4
1878 * @VXGE_HW_RING_HASH_TYPE_TCP_IPV6: TCP IPv6
1879 * @VXGE_HW_RING_HASH_TYPE_UDP_IPV6: UDP IPv6
1880 * @VXGE_HW_RING_HASH_TYPE_IPV6: IPv6
1881 * @VXGE_HW_RING_HASH_TYPE_TCP_IPV6_EX: TCP IPv6 extension
1882 * @VXGE_HW_RING_HASH_TYPE_UDP_IPV6_EX: UDP IPv6 extension
1883 * @VXGE_HW_RING_HASH_TYPE_IPV6_EX: IPv6 extension
1887 enum vxge_hw_ring_hash_type {
1888 VXGE_HW_RING_HASH_TYPE_NONE = 0x0,
1889 VXGE_HW_RING_HASH_TYPE_TCP_IPV4 = 0x1,
1890 VXGE_HW_RING_HASH_TYPE_UDP_IPV4 = 0x2,
1891 VXGE_HW_RING_HASH_TYPE_IPV4 = 0x3,
1892 VXGE_HW_RING_HASH_TYPE_TCP_IPV6 = 0x4,
1893 VXGE_HW_RING_HASH_TYPE_UDP_IPV6 = 0x5,
1894 VXGE_HW_RING_HASH_TYPE_IPV6 = 0x6,
1895 VXGE_HW_RING_HASH_TYPE_TCP_IPV6_EX = 0x7,
1896 VXGE_HW_RING_HASH_TYPE_UDP_IPV6_EX = 0x8,
1897 VXGE_HW_RING_HASH_TYPE_IPV6_EX = 0x9
1900 enum vxge_hw_status vxge_hw_ring_rxd_reserve(
1901 struct __vxge_hw_ring *ring_handle,
1905 vxge_hw_ring_rxd_pre_post(
1906 struct __vxge_hw_ring *ring_handle,
1910 vxge_hw_ring_rxd_post_post(
1911 struct __vxge_hw_ring *ring_handle,
1915 vxge_hw_ring_replenish(struct __vxge_hw_ring *ring_handle, u16 min_flag);
1918 vxge_hw_ring_rxd_post_post_wmb(
1919 struct __vxge_hw_ring *ring_handle,
1922 void vxge_hw_ring_rxd_post(
1923 struct __vxge_hw_ring *ring_handle,
1926 enum vxge_hw_status vxge_hw_ring_rxd_next_completed(
1927 struct __vxge_hw_ring *ring_handle,
1931 enum vxge_hw_status vxge_hw_ring_handle_tcode(
1932 struct __vxge_hw_ring *ring_handle,
1936 void vxge_hw_ring_rxd_free(
1937 struct __vxge_hw_ring *ring_handle,
1941 * enum enum vxge_hw_frame_proto - Higher-layer ethernet protocols.
1942 * @VXGE_HW_FRAME_PROTO_VLAN_TAGGED: VLAN.
1943 * @VXGE_HW_FRAME_PROTO_IPV4: IPv4.
1944 * @VXGE_HW_FRAME_PROTO_IPV6: IPv6.
1945 * @VXGE_HW_FRAME_PROTO_IP_FRAG: IP fragmented.
1946 * @VXGE_HW_FRAME_PROTO_TCP: TCP.
1947 * @VXGE_HW_FRAME_PROTO_UDP: UDP.
1948 * @VXGE_HW_FRAME_PROTO_TCP_OR_UDP: TCP or UDP.
1950 * Higher layer ethernet protocols and options.
1952 enum vxge_hw_frame_proto {
1953 VXGE_HW_FRAME_PROTO_VLAN_TAGGED = 0x80,
1954 VXGE_HW_FRAME_PROTO_IPV4 = 0x10,
1955 VXGE_HW_FRAME_PROTO_IPV6 = 0x08,
1956 VXGE_HW_FRAME_PROTO_IP_FRAG = 0x04,
1957 VXGE_HW_FRAME_PROTO_TCP = 0x02,
1958 VXGE_HW_FRAME_PROTO_UDP = 0x01,
1959 VXGE_HW_FRAME_PROTO_TCP_OR_UDP = (VXGE_HW_FRAME_PROTO_TCP | \
1960 VXGE_HW_FRAME_PROTO_UDP)
1964 * enum enum vxge_hw_fifo_gather_code - Gather codes used in fifo TxD
1965 * @VXGE_HW_FIFO_GATHER_CODE_FIRST: First TxDL
1966 * @VXGE_HW_FIFO_GATHER_CODE_MIDDLE: Middle TxDL
1967 * @VXGE_HW_FIFO_GATHER_CODE_LAST: Last TxDL
1968 * @VXGE_HW_FIFO_GATHER_CODE_FIRST_LAST: First and Last TxDL.
1970 * These gather codes are used to indicate the position of a TxD in a TxD list
1972 enum vxge_hw_fifo_gather_code {
1973 VXGE_HW_FIFO_GATHER_CODE_FIRST = 0x2,
1974 VXGE_HW_FIFO_GATHER_CODE_MIDDLE = 0x0,
1975 VXGE_HW_FIFO_GATHER_CODE_LAST = 0x1,
1976 VXGE_HW_FIFO_GATHER_CODE_FIRST_LAST = 0x3
1980 * enum enum vxge_hw_fifo_tcode - tcodes used in fifo
1981 * @VXGE_HW_FIFO_T_CODE_OK: Transfer OK
1982 * @VXGE_HW_FIFO_T_CODE_PCI_READ_CORRUPT: PCI read transaction (either TxD or
1983 * frame data) returned with corrupt data.
1984 * @VXGE_HW_FIFO_T_CODE_PCI_READ_FAIL:PCI read transaction was returned
1986 * @VXGE_HW_FIFO_T_CODE_INVALID_MSS: The host attempted to send either a
1987 * frame or LSO MSS that was too long (>9800B).
1988 * @VXGE_HW_FIFO_T_CODE_LSO_ERROR: Error detected during TCP/UDP Large Send
1989 * Offload operation, due to improper header template,
1990 * unsupported protocol, etc.
1991 * @VXGE_HW_FIFO_T_CODE_UNUSED: Unused
1992 * @VXGE_HW_FIFO_T_CODE_MULTI_ERROR: Set to 1 by the adapter if multiple
1993 * data buffer transfer errors are encountered (see below).
1994 * Otherwise it is set to 0.
1996 * These tcodes are returned in various API for TxD status
1998 enum vxge_hw_fifo_tcode {
1999 VXGE_HW_FIFO_T_CODE_OK = 0x0,
2000 VXGE_HW_FIFO_T_CODE_PCI_READ_CORRUPT = 0x1,
2001 VXGE_HW_FIFO_T_CODE_PCI_READ_FAIL = 0x2,
2002 VXGE_HW_FIFO_T_CODE_INVALID_MSS = 0x3,
2003 VXGE_HW_FIFO_T_CODE_LSO_ERROR = 0x4,
2004 VXGE_HW_FIFO_T_CODE_UNUSED = 0x7,
2005 VXGE_HW_FIFO_T_CODE_MULTI_ERROR = 0x8
2008 enum vxge_hw_status vxge_hw_fifo_txdl_reserve(
2009 struct __vxge_hw_fifo *fifoh,
2013 void vxge_hw_fifo_txdl_buffer_set(
2014 struct __vxge_hw_fifo *fifo_handle,
2017 dma_addr_t dma_pointer,
2020 void vxge_hw_fifo_txdl_post(
2021 struct __vxge_hw_fifo *fifo_handle,
2024 u32 vxge_hw_fifo_free_txdl_count_get(
2025 struct __vxge_hw_fifo *fifo_handle);
2027 enum vxge_hw_status vxge_hw_fifo_txdl_next_completed(
2028 struct __vxge_hw_fifo *fifoh,
2030 enum vxge_hw_fifo_tcode *t_code);
2032 enum vxge_hw_status vxge_hw_fifo_handle_tcode(
2033 struct __vxge_hw_fifo *fifoh,
2035 enum vxge_hw_fifo_tcode t_code);
2037 void vxge_hw_fifo_txdl_free(
2038 struct __vxge_hw_fifo *fifoh,
2045 #define VXGE_HW_RING_NEXT_BLOCK_POINTER_OFFSET (VXGE_HW_BLOCK_SIZE-8)
2046 #define VXGE_HW_RING_MEMBLOCK_IDX_OFFSET (VXGE_HW_BLOCK_SIZE-16)
2047 #define VXGE_HW_RING_MIN_BUFF_ALLOCATION 64
2050 * struct __vxge_hw_ring_rxd_priv - Receive descriptor HW-private data.
2051 * @dma_addr: DMA (mapped) address of _this_ descriptor.
2052 * @dma_handle: DMA handle used to map the descriptor onto device.
2053 * @dma_offset: Descriptor's offset in the memory block. HW allocates
2054 * descriptors in memory blocks of %VXGE_HW_BLOCK_SIZE
2055 * bytes. Each memblock is contiguous DMA-able memory. Each
2056 * memblock contains 1 or more 4KB RxD blocks visible to the
2058 * @dma_object: DMA address and handle of the memory block that contains
2059 * the descriptor. This member is used only in the "checked"
2060 * version of the HW (to enforce certain assertions);
2061 * otherwise it gets compiled out.
2062 * @allocated: True if the descriptor is reserved, 0 otherwise. Internal usage.
2064 * Per-receive decsriptor HW-private data. HW uses the space to keep DMA
2065 * information associated with the descriptor. Note that driver can ask HW
2066 * to allocate additional per-descriptor space for its own (driver-specific)
2069 struct __vxge_hw_ring_rxd_priv {
2070 dma_addr_t dma_addr;
2071 struct pci_dev *dma_handle;
2072 ptrdiff_t dma_offset;
2073 #ifdef VXGE_DEBUG_ASSERT
2074 struct vxge_hw_mempool_dma *dma_object;
2078 /* ========================= RING PRIVATE API ============================= */
2080 __vxge_hw_ring_first_block_address_get(
2081 struct __vxge_hw_ring *ringh);
2084 __vxge_hw_ring_create(
2085 struct __vxge_hw_vpath_handle *vpath_handle,
2086 struct vxge_hw_ring_attr *attr);
2089 __vxge_hw_ring_abort(
2090 struct __vxge_hw_ring *ringh);
2093 __vxge_hw_ring_reset(
2094 struct __vxge_hw_ring *ringh);
2097 __vxge_hw_ring_delete(
2098 struct __vxge_hw_vpath_handle *vpath_handle);
2100 /* ========================= FIFO PRIVATE API ============================= */
2102 struct vxge_hw_fifo_attr;
2105 __vxge_hw_fifo_create(
2106 struct __vxge_hw_vpath_handle *vpath_handle,
2107 struct vxge_hw_fifo_attr *attr);
2110 __vxge_hw_fifo_abort(
2111 struct __vxge_hw_fifo *fifoh);
2114 __vxge_hw_fifo_reset(
2115 struct __vxge_hw_fifo *ringh);
2118 __vxge_hw_fifo_delete(
2119 struct __vxge_hw_vpath_handle *vpath_handle);
2121 struct vxge_hw_mempool_cbs {
2122 void (*item_func_alloc)(
2123 struct vxge_hw_mempool *mempoolh,
2125 struct vxge_hw_mempool_dma *dma_object,
2131 __vxge_hw_mempool_destroy(
2132 struct vxge_hw_mempool *mempool);
2134 #define VXGE_HW_VIRTUAL_PATH_HANDLE(vpath) \
2135 ((struct __vxge_hw_vpath_handle *)(vpath)->vpath_handles.next)
2138 __vxge_hw_vpath_rts_table_get(
2139 struct __vxge_hw_vpath_handle *vpath_handle,
2147 __vxge_hw_vpath_rts_table_set(
2148 struct __vxge_hw_vpath_handle *vpath_handle,
2156 __vxge_hw_vpath_reset(
2157 struct __vxge_hw_device *devh,
2161 __vxge_hw_vpath_sw_reset(
2162 struct __vxge_hw_device *devh,
2166 __vxge_hw_vpath_enable(
2167 struct __vxge_hw_device *devh,
2171 __vxge_hw_vpath_prc_configure(
2172 struct __vxge_hw_device *devh,
2176 __vxge_hw_vpath_kdfc_configure(
2177 struct __vxge_hw_device *devh,
2181 __vxge_hw_vpath_mac_configure(
2182 struct __vxge_hw_device *devh,
2186 __vxge_hw_vpath_tim_configure(
2187 struct __vxge_hw_device *devh,
2191 __vxge_hw_vpath_initialize(
2192 struct __vxge_hw_device *devh,
2196 __vxge_hw_vp_initialize(
2197 struct __vxge_hw_device *devh,
2199 struct vxge_hw_vp_config *config);
2202 __vxge_hw_vp_terminate(
2203 struct __vxge_hw_device *devh,
2207 __vxge_hw_vpath_alarm_process(
2208 struct __vxge_hw_virtualpath *vpath,
2211 void vxge_hw_device_intr_enable(
2212 struct __vxge_hw_device *devh);
2214 u32 vxge_hw_device_set_intr_type(struct __vxge_hw_device *devh, u32 intr_mode);
2216 void vxge_hw_device_intr_disable(
2217 struct __vxge_hw_device *devh);
2219 void vxge_hw_device_mask_all(
2220 struct __vxge_hw_device *devh);
2222 void vxge_hw_device_unmask_all(
2223 struct __vxge_hw_device *devh);
2225 enum vxge_hw_status vxge_hw_device_begin_irq(
2226 struct __vxge_hw_device *devh,
2230 void vxge_hw_device_clear_tx_rx(
2231 struct __vxge_hw_device *devh);
2237 u32 vxge_hw_vpath_id(
2238 struct __vxge_hw_vpath_handle *vpath_handle);
2240 enum vxge_hw_vpath_mac_addr_add_mode {
2241 VXGE_HW_VPATH_MAC_ADDR_ADD_DUPLICATE = 0,
2242 VXGE_HW_VPATH_MAC_ADDR_DISCARD_DUPLICATE = 1,
2243 VXGE_HW_VPATH_MAC_ADDR_REPLACE_DUPLICATE = 2
2247 vxge_hw_vpath_mac_addr_add(
2248 struct __vxge_hw_vpath_handle *vpath_handle,
2249 u8 (macaddr)[ETH_ALEN],
2250 u8 (macaddr_mask)[ETH_ALEN],
2251 enum vxge_hw_vpath_mac_addr_add_mode duplicate_mode);
2254 vxge_hw_vpath_mac_addr_get(
2255 struct __vxge_hw_vpath_handle *vpath_handle,
2256 u8 (macaddr)[ETH_ALEN],
2257 u8 (macaddr_mask)[ETH_ALEN]);
2260 vxge_hw_vpath_mac_addr_get_next(
2261 struct __vxge_hw_vpath_handle *vpath_handle,
2262 u8 (macaddr)[ETH_ALEN],
2263 u8 (macaddr_mask)[ETH_ALEN]);
2266 vxge_hw_vpath_mac_addr_delete(
2267 struct __vxge_hw_vpath_handle *vpath_handle,
2268 u8 (macaddr)[ETH_ALEN],
2269 u8 (macaddr_mask)[ETH_ALEN]);
2272 vxge_hw_vpath_vid_add(
2273 struct __vxge_hw_vpath_handle *vpath_handle,
2277 vxge_hw_vpath_vid_get(
2278 struct __vxge_hw_vpath_handle *vpath_handle,
2282 vxge_hw_vpath_vid_get_next(
2283 struct __vxge_hw_vpath_handle *vpath_handle,
2287 vxge_hw_vpath_vid_delete(
2288 struct __vxge_hw_vpath_handle *vpath_handle,
2292 vxge_hw_vpath_etype_add(
2293 struct __vxge_hw_vpath_handle *vpath_handle,
2297 vxge_hw_vpath_etype_get(
2298 struct __vxge_hw_vpath_handle *vpath_handle,
2302 vxge_hw_vpath_etype_get_next(
2303 struct __vxge_hw_vpath_handle *vpath_handle,
2307 vxge_hw_vpath_etype_delete(
2308 struct __vxge_hw_vpath_handle *vpath_handle,
2311 enum vxge_hw_status vxge_hw_vpath_promisc_enable(
2312 struct __vxge_hw_vpath_handle *vpath_handle);
2314 enum vxge_hw_status vxge_hw_vpath_promisc_disable(
2315 struct __vxge_hw_vpath_handle *vpath_handle);
2317 enum vxge_hw_status vxge_hw_vpath_bcast_enable(
2318 struct __vxge_hw_vpath_handle *vpath_handle);
2320 enum vxge_hw_status vxge_hw_vpath_mcast_enable(
2321 struct __vxge_hw_vpath_handle *vpath_handle);
2323 enum vxge_hw_status vxge_hw_vpath_mcast_disable(
2324 struct __vxge_hw_vpath_handle *vpath_handle);
2326 enum vxge_hw_status vxge_hw_vpath_poll_rx(
2327 struct __vxge_hw_ring *ringh);
2329 enum vxge_hw_status vxge_hw_vpath_poll_tx(
2330 struct __vxge_hw_fifo *fifoh,
2333 enum vxge_hw_status vxge_hw_vpath_alarm_process(
2334 struct __vxge_hw_vpath_handle *vpath_handle,
2338 vxge_hw_vpath_msix_set(struct __vxge_hw_vpath_handle *vpath_handle,
2339 int *tim_msix_id, int alarm_msix_id);
2342 vxge_hw_vpath_msix_mask(struct __vxge_hw_vpath_handle *vpath_handle,
2345 void vxge_hw_device_flush_io(struct __vxge_hw_device *devh);
2348 vxge_hw_vpath_msix_clear(struct __vxge_hw_vpath_handle *vpath_handle,
2352 vxge_hw_vpath_msix_unmask(struct __vxge_hw_vpath_handle *vpath_handle,
2356 vxge_hw_vpath_msix_mask_all(struct __vxge_hw_vpath_handle *vpath_handle);
2358 enum vxge_hw_status vxge_hw_vpath_intr_enable(
2359 struct __vxge_hw_vpath_handle *vpath_handle);
2361 enum vxge_hw_status vxge_hw_vpath_intr_disable(
2362 struct __vxge_hw_vpath_handle *vpath_handle);
2364 void vxge_hw_vpath_inta_mask_tx_rx(
2365 struct __vxge_hw_vpath_handle *vpath_handle);
2367 void vxge_hw_vpath_inta_unmask_tx_rx(
2368 struct __vxge_hw_vpath_handle *vpath_handle);
2371 vxge_hw_channel_msix_mask(struct __vxge_hw_channel *channelh, int msix_id);
2374 vxge_hw_channel_msix_unmask(struct __vxge_hw_channel *channelh, int msix_id);
2377 vxge_hw_channel_dtr_alloc(struct __vxge_hw_channel *channel, void **dtrh);
2380 vxge_hw_channel_dtr_post(struct __vxge_hw_channel *channel, void *dtrh);
2383 vxge_hw_channel_dtr_try_complete(struct __vxge_hw_channel *channel,
2387 vxge_hw_channel_dtr_complete(struct __vxge_hw_channel *channel);
2390 vxge_hw_channel_dtr_free(struct __vxge_hw_channel *channel, void *dtrh);
2393 vxge_hw_channel_dtr_count(struct __vxge_hw_channel *channel);
2395 /* ========================== PRIVATE API ================================= */
2398 __vxge_hw_device_handle_link_up_ind(struct __vxge_hw_device *hldev);
2401 __vxge_hw_device_handle_link_down_ind(struct __vxge_hw_device *hldev);
2404 __vxge_hw_device_handle_error(
2405 struct __vxge_hw_device *hldev,
2407 enum vxge_hw_event type);
git.samba.org / sfrench / cifs-2.6.git / blob