Merge tag 'drm-misc-fixes-2017-11-02' of git://anongit.freedesktop.org/drm/drm-misc...
[sfrench/cifs-2.6.git] / drivers / net / usb / r8152.c
1 /*
2  *  Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * version 2 as published by the Free Software Foundation.
7  *
8  */
9
10 #include <linux/signal.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/mii.h>
16 #include <linux/ethtool.h>
17 #include <linux/usb.h>
18 #include <linux/crc32.h>
19 #include <linux/if_vlan.h>
20 #include <linux/uaccess.h>
21 #include <linux/list.h>
22 #include <linux/ip.h>
23 #include <linux/ipv6.h>
24 #include <net/ip6_checksum.h>
25 #include <uapi/linux/mdio.h>
26 #include <linux/mdio.h>
27 #include <linux/usb/cdc.h>
28 #include <linux/suspend.h>
29 #include <linux/acpi.h>
30
31 /* Information for net-next */
32 #define NETNEXT_VERSION         "09"
33
34 /* Information for net */
35 #define NET_VERSION             "9"
36
37 #define DRIVER_VERSION          "v1." NETNEXT_VERSION "." NET_VERSION
38 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
39 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
40 #define MODULENAME "r8152"
41
42 #define R8152_PHY_ID            32
43
44 #define PLA_IDR                 0xc000
45 #define PLA_RCR                 0xc010
46 #define PLA_RMS                 0xc016
47 #define PLA_RXFIFO_CTRL0        0xc0a0
48 #define PLA_RXFIFO_CTRL1        0xc0a4
49 #define PLA_RXFIFO_CTRL2        0xc0a8
50 #define PLA_DMY_REG0            0xc0b0
51 #define PLA_FMC                 0xc0b4
52 #define PLA_CFG_WOL             0xc0b6
53 #define PLA_TEREDO_CFG          0xc0bc
54 #define PLA_TEREDO_WAKE_BASE    0xc0c4
55 #define PLA_MAR                 0xcd00
56 #define PLA_BACKUP              0xd000
57 #define PAL_BDC_CR              0xd1a0
58 #define PLA_TEREDO_TIMER        0xd2cc
59 #define PLA_REALWOW_TIMER       0xd2e8
60 #define PLA_EFUSE_DATA          0xdd00
61 #define PLA_EFUSE_CMD           0xdd02
62 #define PLA_LEDSEL              0xdd90
63 #define PLA_LED_FEATURE         0xdd92
64 #define PLA_PHYAR               0xde00
65 #define PLA_BOOT_CTRL           0xe004
66 #define PLA_GPHY_INTR_IMR       0xe022
67 #define PLA_EEE_CR              0xe040
68 #define PLA_EEEP_CR             0xe080
69 #define PLA_MAC_PWR_CTRL        0xe0c0
70 #define PLA_MAC_PWR_CTRL2       0xe0ca
71 #define PLA_MAC_PWR_CTRL3       0xe0cc
72 #define PLA_MAC_PWR_CTRL4       0xe0ce
73 #define PLA_WDT6_CTRL           0xe428
74 #define PLA_TCR0                0xe610
75 #define PLA_TCR1                0xe612
76 #define PLA_MTPS                0xe615
77 #define PLA_TXFIFO_CTRL         0xe618
78 #define PLA_RSTTALLY            0xe800
79 #define PLA_CR                  0xe813
80 #define PLA_CRWECR              0xe81c
81 #define PLA_CONFIG12            0xe81e  /* CONFIG1, CONFIG2 */
82 #define PLA_CONFIG34            0xe820  /* CONFIG3, CONFIG4 */
83 #define PLA_CONFIG5             0xe822
84 #define PLA_PHY_PWR             0xe84c
85 #define PLA_OOB_CTRL            0xe84f
86 #define PLA_CPCR                0xe854
87 #define PLA_MISC_0              0xe858
88 #define PLA_MISC_1              0xe85a
89 #define PLA_OCP_GPHY_BASE       0xe86c
90 #define PLA_TALLYCNT            0xe890
91 #define PLA_SFF_STS_7           0xe8de
92 #define PLA_PHYSTATUS           0xe908
93 #define PLA_BP_BA               0xfc26
94 #define PLA_BP_0                0xfc28
95 #define PLA_BP_1                0xfc2a
96 #define PLA_BP_2                0xfc2c
97 #define PLA_BP_3                0xfc2e
98 #define PLA_BP_4                0xfc30
99 #define PLA_BP_5                0xfc32
100 #define PLA_BP_6                0xfc34
101 #define PLA_BP_7                0xfc36
102 #define PLA_BP_EN               0xfc38
103
104 #define USB_USB2PHY             0xb41e
105 #define USB_SSPHYLINK2          0xb428
106 #define USB_U2P3_CTRL           0xb460
107 #define USB_CSR_DUMMY1          0xb464
108 #define USB_CSR_DUMMY2          0xb466
109 #define USB_DEV_STAT            0xb808
110 #define USB_CONNECT_TIMER       0xcbf8
111 #define USB_MSC_TIMER           0xcbfc
112 #define USB_BURST_SIZE          0xcfc0
113 #define USB_LPM_CONFIG          0xcfd8
114 #define USB_USB_CTRL            0xd406
115 #define USB_PHY_CTRL            0xd408
116 #define USB_TX_AGG              0xd40a
117 #define USB_RX_BUF_TH           0xd40c
118 #define USB_USB_TIMER           0xd428
119 #define USB_RX_EARLY_TIMEOUT    0xd42c
120 #define USB_RX_EARLY_SIZE       0xd42e
121 #define USB_PM_CTRL_STATUS      0xd432  /* RTL8153A */
122 #define USB_RX_EXTRA_AGGR_TMR   0xd432  /* RTL8153B */
123 #define USB_TX_DMA              0xd434
124 #define USB_UPT_RXDMA_OWN       0xd437
125 #define USB_TOLERANCE           0xd490
126 #define USB_LPM_CTRL            0xd41a
127 #define USB_BMU_RESET           0xd4b0
128 #define USB_U1U2_TIMER          0xd4da
129 #define USB_UPS_CTRL            0xd800
130 #define USB_POWER_CUT           0xd80a
131 #define USB_MISC_0              0xd81a
132 #define USB_AFE_CTRL2           0xd824
133 #define USB_UPS_CFG             0xd842
134 #define USB_UPS_FLAGS           0xd848
135 #define USB_WDT11_CTRL          0xe43c
136 #define USB_BP_BA               0xfc26
137 #define USB_BP_0                0xfc28
138 #define USB_BP_1                0xfc2a
139 #define USB_BP_2                0xfc2c
140 #define USB_BP_3                0xfc2e
141 #define USB_BP_4                0xfc30
142 #define USB_BP_5                0xfc32
143 #define USB_BP_6                0xfc34
144 #define USB_BP_7                0xfc36
145 #define USB_BP_EN               0xfc38
146 #define USB_BP_8                0xfc38
147 #define USB_BP_9                0xfc3a
148 #define USB_BP_10               0xfc3c
149 #define USB_BP_11               0xfc3e
150 #define USB_BP_12               0xfc40
151 #define USB_BP_13               0xfc42
152 #define USB_BP_14               0xfc44
153 #define USB_BP_15               0xfc46
154 #define USB_BP2_EN              0xfc48
155
156 /* OCP Registers */
157 #define OCP_ALDPS_CONFIG        0x2010
158 #define OCP_EEE_CONFIG1         0x2080
159 #define OCP_EEE_CONFIG2         0x2092
160 #define OCP_EEE_CONFIG3         0x2094
161 #define OCP_BASE_MII            0xa400
162 #define OCP_EEE_AR              0xa41a
163 #define OCP_EEE_DATA            0xa41c
164 #define OCP_PHY_STATUS          0xa420
165 #define OCP_NCTL_CFG            0xa42c
166 #define OCP_POWER_CFG           0xa430
167 #define OCP_EEE_CFG             0xa432
168 #define OCP_SRAM_ADDR           0xa436
169 #define OCP_SRAM_DATA           0xa438
170 #define OCP_DOWN_SPEED          0xa442
171 #define OCP_EEE_ABLE            0xa5c4
172 #define OCP_EEE_ADV             0xa5d0
173 #define OCP_EEE_LPABLE          0xa5d2
174 #define OCP_PHY_STATE           0xa708          /* nway state for 8153 */
175 #define OCP_PHY_PATCH_STAT      0xb800
176 #define OCP_PHY_PATCH_CMD       0xb820
177 #define OCP_ADC_IOFFSET         0xbcfc
178 #define OCP_ADC_CFG             0xbc06
179 #define OCP_SYSCLK_CFG          0xc416
180
181 /* SRAM Register */
182 #define SRAM_GREEN_CFG          0x8011
183 #define SRAM_LPF_CFG            0x8012
184 #define SRAM_10M_AMP1           0x8080
185 #define SRAM_10M_AMP2           0x8082
186 #define SRAM_IMPEDANCE          0x8084
187
188 /* PLA_RCR */
189 #define RCR_AAP                 0x00000001
190 #define RCR_APM                 0x00000002
191 #define RCR_AM                  0x00000004
192 #define RCR_AB                  0x00000008
193 #define RCR_ACPT_ALL            (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
194
195 /* PLA_RXFIFO_CTRL0 */
196 #define RXFIFO_THR1_NORMAL      0x00080002
197 #define RXFIFO_THR1_OOB         0x01800003
198
199 /* PLA_RXFIFO_CTRL1 */
200 #define RXFIFO_THR2_FULL        0x00000060
201 #define RXFIFO_THR2_HIGH        0x00000038
202 #define RXFIFO_THR2_OOB         0x0000004a
203 #define RXFIFO_THR2_NORMAL      0x00a0
204
205 /* PLA_RXFIFO_CTRL2 */
206 #define RXFIFO_THR3_FULL        0x00000078
207 #define RXFIFO_THR3_HIGH        0x00000048
208 #define RXFIFO_THR3_OOB         0x0000005a
209 #define RXFIFO_THR3_NORMAL      0x0110
210
211 /* PLA_TXFIFO_CTRL */
212 #define TXFIFO_THR_NORMAL       0x00400008
213 #define TXFIFO_THR_NORMAL2      0x01000008
214
215 /* PLA_DMY_REG0 */
216 #define ECM_ALDPS               0x0002
217
218 /* PLA_FMC */
219 #define FMC_FCR_MCU_EN          0x0001
220
221 /* PLA_EEEP_CR */
222 #define EEEP_CR_EEEP_TX         0x0002
223
224 /* PLA_WDT6_CTRL */
225 #define WDT6_SET_MODE           0x0010
226
227 /* PLA_TCR0 */
228 #define TCR0_TX_EMPTY           0x0800
229 #define TCR0_AUTO_FIFO          0x0080
230
231 /* PLA_TCR1 */
232 #define VERSION_MASK            0x7cf0
233
234 /* PLA_MTPS */
235 #define MTPS_JUMBO              (12 * 1024 / 64)
236 #define MTPS_DEFAULT            (6 * 1024 / 64)
237
238 /* PLA_RSTTALLY */
239 #define TALLY_RESET             0x0001
240
241 /* PLA_CR */
242 #define CR_RST                  0x10
243 #define CR_RE                   0x08
244 #define CR_TE                   0x04
245
246 /* PLA_CRWECR */
247 #define CRWECR_NORAML           0x00
248 #define CRWECR_CONFIG           0xc0
249
250 /* PLA_OOB_CTRL */
251 #define NOW_IS_OOB              0x80
252 #define TXFIFO_EMPTY            0x20
253 #define RXFIFO_EMPTY            0x10
254 #define LINK_LIST_READY         0x02
255 #define DIS_MCU_CLROOB          0x01
256 #define FIFO_EMPTY              (TXFIFO_EMPTY | RXFIFO_EMPTY)
257
258 /* PLA_MISC_1 */
259 #define RXDY_GATED_EN           0x0008
260
261 /* PLA_SFF_STS_7 */
262 #define RE_INIT_LL              0x8000
263 #define MCU_BORW_EN             0x4000
264
265 /* PLA_CPCR */
266 #define CPCR_RX_VLAN            0x0040
267
268 /* PLA_CFG_WOL */
269 #define MAGIC_EN                0x0001
270
271 /* PLA_TEREDO_CFG */
272 #define TEREDO_SEL              0x8000
273 #define TEREDO_WAKE_MASK        0x7f00
274 #define TEREDO_RS_EVENT_MASK    0x00fe
275 #define OOB_TEREDO_EN           0x0001
276
277 /* PAL_BDC_CR */
278 #define ALDPS_PROXY_MODE        0x0001
279
280 /* PLA_EFUSE_CMD */
281 #define EFUSE_READ_CMD          BIT(15)
282 #define EFUSE_DATA_BIT16        BIT(7)
283
284 /* PLA_CONFIG34 */
285 #define LINK_ON_WAKE_EN         0x0010
286 #define LINK_OFF_WAKE_EN        0x0008
287
288 /* PLA_CONFIG5 */
289 #define BWF_EN                  0x0040
290 #define MWF_EN                  0x0020
291 #define UWF_EN                  0x0010
292 #define LAN_WAKE_EN             0x0002
293
294 /* PLA_LED_FEATURE */
295 #define LED_MODE_MASK           0x0700
296
297 /* PLA_PHY_PWR */
298 #define TX_10M_IDLE_EN          0x0080
299 #define PFM_PWM_SWITCH          0x0040
300
301 /* PLA_MAC_PWR_CTRL */
302 #define D3_CLK_GATED_EN         0x00004000
303 #define MCU_CLK_RATIO           0x07010f07
304 #define MCU_CLK_RATIO_MASK      0x0f0f0f0f
305 #define ALDPS_SPDWN_RATIO       0x0f87
306
307 /* PLA_MAC_PWR_CTRL2 */
308 #define EEE_SPDWN_RATIO         0x8007
309 #define MAC_CLK_SPDWN_EN        BIT(15)
310
311 /* PLA_MAC_PWR_CTRL3 */
312 #define PKT_AVAIL_SPDWN_EN      0x0100
313 #define SUSPEND_SPDWN_EN        0x0004
314 #define U1U2_SPDWN_EN           0x0002
315 #define L1_SPDWN_EN             0x0001
316
317 /* PLA_MAC_PWR_CTRL4 */
318 #define PWRSAVE_SPDWN_EN        0x1000
319 #define RXDV_SPDWN_EN           0x0800
320 #define TX10MIDLE_EN            0x0100
321 #define TP100_SPDWN_EN          0x0020
322 #define TP500_SPDWN_EN          0x0010
323 #define TP1000_SPDWN_EN         0x0008
324 #define EEE_SPDWN_EN            0x0001
325
326 /* PLA_GPHY_INTR_IMR */
327 #define GPHY_STS_MSK            0x0001
328 #define SPEED_DOWN_MSK          0x0002
329 #define SPDWN_RXDV_MSK          0x0004
330 #define SPDWN_LINKCHG_MSK       0x0008
331
332 /* PLA_PHYAR */
333 #define PHYAR_FLAG              0x80000000
334
335 /* PLA_EEE_CR */
336 #define EEE_RX_EN               0x0001
337 #define EEE_TX_EN               0x0002
338
339 /* PLA_BOOT_CTRL */
340 #define AUTOLOAD_DONE           0x0002
341
342 /* USB_USB2PHY */
343 #define USB2PHY_SUSPEND         0x0001
344 #define USB2PHY_L1              0x0002
345
346 /* USB_SSPHYLINK2 */
347 #define pwd_dn_scale_mask       0x3ffe
348 #define pwd_dn_scale(x)         ((x) << 1)
349
350 /* USB_CSR_DUMMY1 */
351 #define DYNAMIC_BURST           0x0001
352
353 /* USB_CSR_DUMMY2 */
354 #define EP4_FULL_FC             0x0001
355
356 /* USB_DEV_STAT */
357 #define STAT_SPEED_MASK         0x0006
358 #define STAT_SPEED_HIGH         0x0000
359 #define STAT_SPEED_FULL         0x0002
360
361 /* USB_LPM_CONFIG */
362 #define LPM_U1U2_EN             BIT(0)
363
364 /* USB_TX_AGG */
365 #define TX_AGG_MAX_THRESHOLD    0x03
366
367 /* USB_RX_BUF_TH */
368 #define RX_THR_SUPPER           0x0c350180
369 #define RX_THR_HIGH             0x7a120180
370 #define RX_THR_SLOW             0xffff0180
371 #define RX_THR_B                0x00010001
372
373 /* USB_TX_DMA */
374 #define TEST_MODE_DISABLE       0x00000001
375 #define TX_SIZE_ADJUST1         0x00000100
376
377 /* USB_BMU_RESET */
378 #define BMU_RESET_EP_IN         0x01
379 #define BMU_RESET_EP_OUT        0x02
380
381 /* USB_UPT_RXDMA_OWN */
382 #define OWN_UPDATE              BIT(0)
383 #define OWN_CLEAR               BIT(1)
384
385 /* USB_UPS_CTRL */
386 #define POWER_CUT               0x0100
387
388 /* USB_PM_CTRL_STATUS */
389 #define RESUME_INDICATE         0x0001
390
391 /* USB_USB_CTRL */
392 #define RX_AGG_DISABLE          0x0010
393 #define RX_ZERO_EN              0x0080
394
395 /* USB_U2P3_CTRL */
396 #define U2P3_ENABLE             0x0001
397
398 /* USB_POWER_CUT */
399 #define PWR_EN                  0x0001
400 #define PHASE2_EN               0x0008
401 #define UPS_EN                  BIT(4)
402 #define USP_PREWAKE             BIT(5)
403
404 /* USB_MISC_0 */
405 #define PCUT_STATUS             0x0001
406
407 /* USB_RX_EARLY_TIMEOUT */
408 #define COALESCE_SUPER           85000U
409 #define COALESCE_HIGH           250000U
410 #define COALESCE_SLOW           524280U
411
412 /* USB_WDT11_CTRL */
413 #define TIMER11_EN              0x0001
414
415 /* USB_LPM_CTRL */
416 /* bit 4 ~ 5: fifo empty boundary */
417 #define FIFO_EMPTY_1FB          0x30    /* 0x1fb * 64 = 32448 bytes */
418 /* bit 2 ~ 3: LMP timer */
419 #define LPM_TIMER_MASK          0x0c
420 #define LPM_TIMER_500MS         0x04    /* 500 ms */
421 #define LPM_TIMER_500US         0x0c    /* 500 us */
422 #define ROK_EXIT_LPM            0x02
423
424 /* USB_AFE_CTRL2 */
425 #define SEN_VAL_MASK            0xf800
426 #define SEN_VAL_NORMAL          0xa000
427 #define SEL_RXIDLE              0x0100
428
429 /* USB_UPS_CFG */
430 #define SAW_CNT_1MS_MASK        0x0fff
431
432 /* USB_UPS_FLAGS */
433 #define UPS_FLAGS_R_TUNE                BIT(0)
434 #define UPS_FLAGS_EN_10M_CKDIV          BIT(1)
435 #define UPS_FLAGS_250M_CKDIV            BIT(2)
436 #define UPS_FLAGS_EN_ALDPS              BIT(3)
437 #define UPS_FLAGS_CTAP_SHORT_DIS        BIT(4)
438 #define UPS_FLAGS_SPEED_MASK            (0xf << 16)
439 #define ups_flags_speed(x)              ((x) << 16)
440 #define UPS_FLAGS_EN_EEE                BIT(20)
441 #define UPS_FLAGS_EN_500M_EEE           BIT(21)
442 #define UPS_FLAGS_EN_EEE_CKDIV          BIT(22)
443 #define UPS_FLAGS_EEE_PLLOFF_GIGA       BIT(24)
444 #define UPS_FLAGS_EEE_CMOD_LV_EN        BIT(25)
445 #define UPS_FLAGS_EN_GREEN              BIT(26)
446 #define UPS_FLAGS_EN_FLOW_CTR           BIT(27)
447
448 enum spd_duplex {
449         NWAY_10M_HALF = 1,
450         NWAY_10M_FULL,
451         NWAY_100M_HALF,
452         NWAY_100M_FULL,
453         NWAY_1000M_FULL,
454         FORCE_10M_HALF,
455         FORCE_10M_FULL,
456         FORCE_100M_HALF,
457         FORCE_100M_FULL,
458 };
459
460 /* OCP_ALDPS_CONFIG */
461 #define ENPWRSAVE               0x8000
462 #define ENPDNPS                 0x0200
463 #define LINKENA                 0x0100
464 #define DIS_SDSAVE              0x0010
465
466 /* OCP_PHY_STATUS */
467 #define PHY_STAT_MASK           0x0007
468 #define PHY_STAT_EXT_INIT       2
469 #define PHY_STAT_LAN_ON         3
470 #define PHY_STAT_PWRDN          5
471
472 /* OCP_NCTL_CFG */
473 #define PGA_RETURN_EN           BIT(1)
474
475 /* OCP_POWER_CFG */
476 #define EEE_CLKDIV_EN           0x8000
477 #define EN_ALDPS                0x0004
478 #define EN_10M_PLLOFF           0x0001
479
480 /* OCP_EEE_CONFIG1 */
481 #define RG_TXLPI_MSK_HFDUP      0x8000
482 #define RG_MATCLR_EN            0x4000
483 #define EEE_10_CAP              0x2000
484 #define EEE_NWAY_EN             0x1000
485 #define TX_QUIET_EN             0x0200
486 #define RX_QUIET_EN             0x0100
487 #define sd_rise_time_mask       0x0070
488 #define sd_rise_time(x)         (min(x, 7) << 4)        /* bit 4 ~ 6 */
489 #define RG_RXLPI_MSK_HFDUP      0x0008
490 #define SDFALLTIME              0x0007  /* bit 0 ~ 2 */
491
492 /* OCP_EEE_CONFIG2 */
493 #define RG_LPIHYS_NUM           0x7000  /* bit 12 ~ 15 */
494 #define RG_DACQUIET_EN          0x0400
495 #define RG_LDVQUIET_EN          0x0200
496 #define RG_CKRSEL               0x0020
497 #define RG_EEEPRG_EN            0x0010
498
499 /* OCP_EEE_CONFIG3 */
500 #define fast_snr_mask           0xff80
501 #define fast_snr(x)             (min(x, 0x1ff) << 7)    /* bit 7 ~ 15 */
502 #define RG_LFS_SEL              0x0060  /* bit 6 ~ 5 */
503 #define MSK_PH                  0x0006  /* bit 0 ~ 3 */
504
505 /* OCP_EEE_AR */
506 /* bit[15:14] function */
507 #define FUN_ADDR                0x0000
508 #define FUN_DATA                0x4000
509 /* bit[4:0] device addr */
510
511 /* OCP_EEE_CFG */
512 #define CTAP_SHORT_EN           0x0040
513 #define EEE10_EN                0x0010
514
515 /* OCP_DOWN_SPEED */
516 #define EN_EEE_CMODE            BIT(14)
517 #define EN_EEE_1000             BIT(13)
518 #define EN_EEE_100              BIT(12)
519 #define EN_10M_CLKDIV           BIT(11)
520 #define EN_10M_BGOFF            0x0080
521
522 /* OCP_PHY_STATE */
523 #define TXDIS_STATE             0x01
524 #define ABD_STATE               0x02
525
526 /* OCP_PHY_PATCH_STAT */
527 #define PATCH_READY             BIT(6)
528
529 /* OCP_PHY_PATCH_CMD */
530 #define PATCH_REQUEST           BIT(4)
531
532 /* OCP_ADC_CFG */
533 #define CKADSEL_L               0x0100
534 #define ADC_EN                  0x0080
535 #define EN_EMI_L                0x0040
536
537 /* OCP_SYSCLK_CFG */
538 #define clk_div_expo(x)         (min(x, 5) << 8)
539
540 /* SRAM_GREEN_CFG */
541 #define GREEN_ETH_EN            BIT(15)
542 #define R_TUNE_EN               BIT(11)
543
544 /* SRAM_LPF_CFG */
545 #define LPF_AUTO_TUNE           0x8000
546
547 /* SRAM_10M_AMP1 */
548 #define GDAC_IB_UPALL           0x0008
549
550 /* SRAM_10M_AMP2 */
551 #define AMP_DN                  0x0200
552
553 /* SRAM_IMPEDANCE */
554 #define RX_DRIVING_MASK         0x6000
555
556 /* MAC PASSTHRU */
557 #define AD_MASK                 0xfee0
558 #define EFUSE                   0xcfdb
559 #define PASS_THRU_MASK          0x1
560
561 enum rtl_register_content {
562         _1000bps        = 0x10,
563         _100bps         = 0x08,
564         _10bps          = 0x04,
565         LINK_STATUS     = 0x02,
566         FULL_DUP        = 0x01,
567 };
568
569 #define RTL8152_MAX_TX          4
570 #define RTL8152_MAX_RX          10
571 #define INTBUFSIZE              2
572 #define TX_ALIGN                4
573 #define RX_ALIGN                8
574
575 #define INTR_LINK               0x0004
576
577 #define RTL8152_REQT_READ       0xc0
578 #define RTL8152_REQT_WRITE      0x40
579 #define RTL8152_REQ_GET_REGS    0x05
580 #define RTL8152_REQ_SET_REGS    0x05
581
582 #define BYTE_EN_DWORD           0xff
583 #define BYTE_EN_WORD            0x33
584 #define BYTE_EN_BYTE            0x11
585 #define BYTE_EN_SIX_BYTES       0x3f
586 #define BYTE_EN_START_MASK      0x0f
587 #define BYTE_EN_END_MASK        0xf0
588
589 #define RTL8153_MAX_PACKET      9216 /* 9K */
590 #define RTL8153_MAX_MTU         (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \
591                                  ETH_FCS_LEN)
592 #define RTL8152_RMS             (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
593 #define RTL8153_RMS             RTL8153_MAX_PACKET
594 #define RTL8152_TX_TIMEOUT      (5 * HZ)
595 #define RTL8152_NAPI_WEIGHT     64
596 #define rx_reserved_size(x)     ((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \
597                                  sizeof(struct rx_desc) + RX_ALIGN)
598
599 /* rtl8152 flags */
600 enum rtl8152_flags {
601         RTL8152_UNPLUG = 0,
602         RTL8152_SET_RX_MODE,
603         WORK_ENABLE,
604         RTL8152_LINK_CHG,
605         SELECTIVE_SUSPEND,
606         PHY_RESET,
607         SCHEDULE_NAPI,
608         GREEN_ETHERNET,
609 };
610
611 /* Define these values to match your device */
612 #define VENDOR_ID_REALTEK               0x0bda
613 #define VENDOR_ID_MICROSOFT             0x045e
614 #define VENDOR_ID_SAMSUNG               0x04e8
615 #define VENDOR_ID_LENOVO                0x17ef
616 #define VENDOR_ID_LINKSYS               0x13b1
617 #define VENDOR_ID_NVIDIA                0x0955
618 #define VENDOR_ID_TPLINK                0x2357
619
620 #define MCU_TYPE_PLA                    0x0100
621 #define MCU_TYPE_USB                    0x0000
622
623 struct tally_counter {
624         __le64  tx_packets;
625         __le64  rx_packets;
626         __le64  tx_errors;
627         __le32  rx_errors;
628         __le16  rx_missed;
629         __le16  align_errors;
630         __le32  tx_one_collision;
631         __le32  tx_multi_collision;
632         __le64  rx_unicast;
633         __le64  rx_broadcast;
634         __le32  rx_multicast;
635         __le16  tx_aborted;
636         __le16  tx_underrun;
637 };
638
639 struct rx_desc {
640         __le32 opts1;
641 #define RX_LEN_MASK                     0x7fff
642
643         __le32 opts2;
644 #define RD_UDP_CS                       BIT(23)
645 #define RD_TCP_CS                       BIT(22)
646 #define RD_IPV6_CS                      BIT(20)
647 #define RD_IPV4_CS                      BIT(19)
648
649         __le32 opts3;
650 #define IPF                             BIT(23) /* IP checksum fail */
651 #define UDPF                            BIT(22) /* UDP checksum fail */
652 #define TCPF                            BIT(21) /* TCP checksum fail */
653 #define RX_VLAN_TAG                     BIT(16)
654
655         __le32 opts4;
656         __le32 opts5;
657         __le32 opts6;
658 };
659
660 struct tx_desc {
661         __le32 opts1;
662 #define TX_FS                   BIT(31) /* First segment of a packet */
663 #define TX_LS                   BIT(30) /* Final segment of a packet */
664 #define GTSENDV4                BIT(28)
665 #define GTSENDV6                BIT(27)
666 #define GTTCPHO_SHIFT           18
667 #define GTTCPHO_MAX             0x7fU
668 #define TX_LEN_MAX              0x3ffffU
669
670         __le32 opts2;
671 #define UDP_CS                  BIT(31) /* Calculate UDP/IP checksum */
672 #define TCP_CS                  BIT(30) /* Calculate TCP/IP checksum */
673 #define IPV4_CS                 BIT(29) /* Calculate IPv4 checksum */
674 #define IPV6_CS                 BIT(28) /* Calculate IPv6 checksum */
675 #define MSS_SHIFT               17
676 #define MSS_MAX                 0x7ffU
677 #define TCPHO_SHIFT             17
678 #define TCPHO_MAX               0x7ffU
679 #define TX_VLAN_TAG             BIT(16)
680 };
681
682 struct r8152;
683
684 struct rx_agg {
685         struct list_head list;
686         struct urb *urb;
687         struct r8152 *context;
688         void *buffer;
689         void *head;
690 };
691
692 struct tx_agg {
693         struct list_head list;
694         struct urb *urb;
695         struct r8152 *context;
696         void *buffer;
697         void *head;
698         u32 skb_num;
699         u32 skb_len;
700 };
701
702 struct r8152 {
703         unsigned long flags;
704         struct usb_device *udev;
705         struct napi_struct napi;
706         struct usb_interface *intf;
707         struct net_device *netdev;
708         struct urb *intr_urb;
709         struct tx_agg tx_info[RTL8152_MAX_TX];
710         struct rx_agg rx_info[RTL8152_MAX_RX];
711         struct list_head rx_done, tx_free;
712         struct sk_buff_head tx_queue, rx_queue;
713         spinlock_t rx_lock, tx_lock;
714         struct delayed_work schedule, hw_phy_work;
715         struct mii_if_info mii;
716         struct mutex control;   /* use for hw setting */
717 #ifdef CONFIG_PM_SLEEP
718         struct notifier_block pm_notifier;
719 #endif
720
721         struct rtl_ops {
722                 void (*init)(struct r8152 *);
723                 int (*enable)(struct r8152 *);
724                 void (*disable)(struct r8152 *);
725                 void (*up)(struct r8152 *);
726                 void (*down)(struct r8152 *);
727                 void (*unload)(struct r8152 *);
728                 int (*eee_get)(struct r8152 *, struct ethtool_eee *);
729                 int (*eee_set)(struct r8152 *, struct ethtool_eee *);
730                 bool (*in_nway)(struct r8152 *);
731                 void (*hw_phy_cfg)(struct r8152 *);
732                 void (*autosuspend_en)(struct r8152 *tp, bool enable);
733         } rtl_ops;
734
735         int intr_interval;
736         u32 saved_wolopts;
737         u32 msg_enable;
738         u32 tx_qlen;
739         u32 coalesce;
740         u16 ocp_base;
741         u16 speed;
742         u8 *intr_buff;
743         u8 version;
744         u8 duplex;
745         u8 autoneg;
746 };
747
748 enum rtl_version {
749         RTL_VER_UNKNOWN = 0,
750         RTL_VER_01,
751         RTL_VER_02,
752         RTL_VER_03,
753         RTL_VER_04,
754         RTL_VER_05,
755         RTL_VER_06,
756         RTL_VER_07,
757         RTL_VER_08,
758         RTL_VER_09,
759         RTL_VER_MAX
760 };
761
762 enum tx_csum_stat {
763         TX_CSUM_SUCCESS = 0,
764         TX_CSUM_TSO,
765         TX_CSUM_NONE
766 };
767
768 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
769  * The RTL chips use a 64 element hash table based on the Ethernet CRC.
770  */
771 static const int multicast_filter_limit = 32;
772 static unsigned int agg_buf_sz = 16384;
773
774 #define RTL_LIMITED_TSO_SIZE    (agg_buf_sz - sizeof(struct tx_desc) - \
775                                  VLAN_ETH_HLEN - ETH_FCS_LEN)
776
777 static
778 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
779 {
780         int ret;
781         void *tmp;
782
783         tmp = kmalloc(size, GFP_KERNEL);
784         if (!tmp)
785                 return -ENOMEM;
786
787         ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
788                               RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
789                               value, index, tmp, size, 500);
790
791         memcpy(data, tmp, size);
792         kfree(tmp);
793
794         return ret;
795 }
796
797 static
798 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
799 {
800         int ret;
801         void *tmp;
802
803         tmp = kmemdup(data, size, GFP_KERNEL);
804         if (!tmp)
805                 return -ENOMEM;
806
807         ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
808                               RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
809                               value, index, tmp, size, 500);
810
811         kfree(tmp);
812
813         return ret;
814 }
815
816 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
817                             void *data, u16 type)
818 {
819         u16 limit = 64;
820         int ret = 0;
821
822         if (test_bit(RTL8152_UNPLUG, &tp->flags))
823                 return -ENODEV;
824
825         /* both size and indix must be 4 bytes align */
826         if ((size & 3) || !size || (index & 3) || !data)
827                 return -EPERM;
828
829         if ((u32)index + (u32)size > 0xffff)
830                 return -EPERM;
831
832         while (size) {
833                 if (size > limit) {
834                         ret = get_registers(tp, index, type, limit, data);
835                         if (ret < 0)
836                                 break;
837
838                         index += limit;
839                         data += limit;
840                         size -= limit;
841                 } else {
842                         ret = get_registers(tp, index, type, size, data);
843                         if (ret < 0)
844                                 break;
845
846                         index += size;
847                         data += size;
848                         size = 0;
849                         break;
850                 }
851         }
852
853         if (ret == -ENODEV)
854                 set_bit(RTL8152_UNPLUG, &tp->flags);
855
856         return ret;
857 }
858
859 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
860                              u16 size, void *data, u16 type)
861 {
862         int ret;
863         u16 byteen_start, byteen_end, byen;
864         u16 limit = 512;
865
866         if (test_bit(RTL8152_UNPLUG, &tp->flags))
867                 return -ENODEV;
868
869         /* both size and indix must be 4 bytes align */
870         if ((size & 3) || !size || (index & 3) || !data)
871                 return -EPERM;
872
873         if ((u32)index + (u32)size > 0xffff)
874                 return -EPERM;
875
876         byteen_start = byteen & BYTE_EN_START_MASK;
877         byteen_end = byteen & BYTE_EN_END_MASK;
878
879         byen = byteen_start | (byteen_start << 4);
880         ret = set_registers(tp, index, type | byen, 4, data);
881         if (ret < 0)
882                 goto error1;
883
884         index += 4;
885         data += 4;
886         size -= 4;
887
888         if (size) {
889                 size -= 4;
890
891                 while (size) {
892                         if (size > limit) {
893                                 ret = set_registers(tp, index,
894                                                     type | BYTE_EN_DWORD,
895                                                     limit, data);
896                                 if (ret < 0)
897                                         goto error1;
898
899                                 index += limit;
900                                 data += limit;
901                                 size -= limit;
902                         } else {
903                                 ret = set_registers(tp, index,
904                                                     type | BYTE_EN_DWORD,
905                                                     size, data);
906                                 if (ret < 0)
907                                         goto error1;
908
909                                 index += size;
910                                 data += size;
911                                 size = 0;
912                                 break;
913                         }
914                 }
915
916                 byen = byteen_end | (byteen_end >> 4);
917                 ret = set_registers(tp, index, type | byen, 4, data);
918                 if (ret < 0)
919                         goto error1;
920         }
921
922 error1:
923         if (ret == -ENODEV)
924                 set_bit(RTL8152_UNPLUG, &tp->flags);
925
926         return ret;
927 }
928
929 static inline
930 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
931 {
932         return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
933 }
934
935 static inline
936 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
937 {
938         return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
939 }
940
941 static inline
942 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
943 {
944         return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
945 }
946
947 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
948 {
949         __le32 data;
950
951         generic_ocp_read(tp, index, sizeof(data), &data, type);
952
953         return __le32_to_cpu(data);
954 }
955
956 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
957 {
958         __le32 tmp = __cpu_to_le32(data);
959
960         generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
961 }
962
963 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
964 {
965         u32 data;
966         __le32 tmp;
967         u16 byen = BYTE_EN_WORD;
968         u8 shift = index & 2;
969
970         index &= ~3;
971         byen <<= shift;
972
973         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
974
975         data = __le32_to_cpu(tmp);
976         data >>= (shift * 8);
977         data &= 0xffff;
978
979         return (u16)data;
980 }
981
982 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
983 {
984         u32 mask = 0xffff;
985         __le32 tmp;
986         u16 byen = BYTE_EN_WORD;
987         u8 shift = index & 2;
988
989         data &= mask;
990
991         if (index & 2) {
992                 byen <<= shift;
993                 mask <<= (shift * 8);
994                 data <<= (shift * 8);
995                 index &= ~3;
996         }
997
998         tmp = __cpu_to_le32(data);
999
1000         generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1001 }
1002
1003 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
1004 {
1005         u32 data;
1006         __le32 tmp;
1007         u8 shift = index & 3;
1008
1009         index &= ~3;
1010
1011         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
1012
1013         data = __le32_to_cpu(tmp);
1014         data >>= (shift * 8);
1015         data &= 0xff;
1016
1017         return (u8)data;
1018 }
1019
1020 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
1021 {
1022         u32 mask = 0xff;
1023         __le32 tmp;
1024         u16 byen = BYTE_EN_BYTE;
1025         u8 shift = index & 3;
1026
1027         data &= mask;
1028
1029         if (index & 3) {
1030                 byen <<= shift;
1031                 mask <<= (shift * 8);
1032                 data <<= (shift * 8);
1033                 index &= ~3;
1034         }
1035
1036         tmp = __cpu_to_le32(data);
1037
1038         generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1039 }
1040
1041 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
1042 {
1043         u16 ocp_base, ocp_index;
1044
1045         ocp_base = addr & 0xf000;
1046         if (ocp_base != tp->ocp_base) {
1047                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1048                 tp->ocp_base = ocp_base;
1049         }
1050
1051         ocp_index = (addr & 0x0fff) | 0xb000;
1052         return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
1053 }
1054
1055 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
1056 {
1057         u16 ocp_base, ocp_index;
1058
1059         ocp_base = addr & 0xf000;
1060         if (ocp_base != tp->ocp_base) {
1061                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1062                 tp->ocp_base = ocp_base;
1063         }
1064
1065         ocp_index = (addr & 0x0fff) | 0xb000;
1066         ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
1067 }
1068
1069 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
1070 {
1071         ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
1072 }
1073
1074 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
1075 {
1076         return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
1077 }
1078
1079 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
1080 {
1081         ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1082         ocp_reg_write(tp, OCP_SRAM_DATA, data);
1083 }
1084
1085 static u16 sram_read(struct r8152 *tp, u16 addr)
1086 {
1087         ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1088         return ocp_reg_read(tp, OCP_SRAM_DATA);
1089 }
1090
1091 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
1092 {
1093         struct r8152 *tp = netdev_priv(netdev);
1094         int ret;
1095
1096         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1097                 return -ENODEV;
1098
1099         if (phy_id != R8152_PHY_ID)
1100                 return -EINVAL;
1101
1102         ret = r8152_mdio_read(tp, reg);
1103
1104         return ret;
1105 }
1106
1107 static
1108 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1109 {
1110         struct r8152 *tp = netdev_priv(netdev);
1111
1112         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1113                 return;
1114
1115         if (phy_id != R8152_PHY_ID)
1116                 return;
1117
1118         r8152_mdio_write(tp, reg, val);
1119 }
1120
1121 static int
1122 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1123
1124 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1125 {
1126         struct r8152 *tp = netdev_priv(netdev);
1127         struct sockaddr *addr = p;
1128         int ret = -EADDRNOTAVAIL;
1129
1130         if (!is_valid_ether_addr(addr->sa_data))
1131                 goto out1;
1132
1133         ret = usb_autopm_get_interface(tp->intf);
1134         if (ret < 0)
1135                 goto out1;
1136
1137         mutex_lock(&tp->control);
1138
1139         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1140
1141         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1142         pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1143         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1144
1145         mutex_unlock(&tp->control);
1146
1147         usb_autopm_put_interface(tp->intf);
1148 out1:
1149         return ret;
1150 }
1151
1152 /* Devices containing RTL8153-AD can support a persistent
1153  * host system provided MAC address.
1154  * Examples of this are Dell TB15 and Dell WD15 docks
1155  */
1156 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1157 {
1158         acpi_status status;
1159         struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1160         union acpi_object *obj;
1161         int ret = -EINVAL;
1162         u32 ocp_data;
1163         unsigned char buf[6];
1164
1165         /* test for -AD variant of RTL8153 */
1166         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1167         if ((ocp_data & AD_MASK) != 0x1000)
1168                 return -ENODEV;
1169
1170         /* test for MAC address pass-through bit */
1171         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1172         if ((ocp_data & PASS_THRU_MASK) != 1)
1173                 return -ENODEV;
1174
1175         /* returns _AUXMAC_#AABBCCDDEEFF# */
1176         status = acpi_evaluate_object(NULL, "\\_SB.AMAC", NULL, &buffer);
1177         obj = (union acpi_object *)buffer.pointer;
1178         if (!ACPI_SUCCESS(status))
1179                 return -ENODEV;
1180         if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) {
1181                 netif_warn(tp, probe, tp->netdev,
1182                            "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1183                            obj->type, obj->string.length);
1184                 goto amacout;
1185         }
1186         if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1187             strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1188                 netif_warn(tp, probe, tp->netdev,
1189                            "Invalid header when reading pass-thru MAC addr\n");
1190                 goto amacout;
1191         }
1192         ret = hex2bin(buf, obj->string.pointer + 9, 6);
1193         if (!(ret == 0 && is_valid_ether_addr(buf))) {
1194                 netif_warn(tp, probe, tp->netdev,
1195                            "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1196                            ret, buf);
1197                 ret = -EINVAL;
1198                 goto amacout;
1199         }
1200         memcpy(sa->sa_data, buf, 6);
1201         ether_addr_copy(tp->netdev->dev_addr, sa->sa_data);
1202         netif_info(tp, probe, tp->netdev,
1203                    "Using pass-thru MAC addr %pM\n", sa->sa_data);
1204
1205 amacout:
1206         kfree(obj);
1207         return ret;
1208 }
1209
1210 static int set_ethernet_addr(struct r8152 *tp)
1211 {
1212         struct net_device *dev = tp->netdev;
1213         struct sockaddr sa;
1214         int ret;
1215
1216         if (tp->version == RTL_VER_01) {
1217                 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
1218         } else {
1219                 /* if this is not an RTL8153-AD, no eFuse mac pass thru set,
1220                  * or system doesn't provide valid _SB.AMAC this will be
1221                  * be expected to non-zero
1222                  */
1223                 ret = vendor_mac_passthru_addr_read(tp, &sa);
1224                 if (ret < 0)
1225                         ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
1226         }
1227
1228         if (ret < 0) {
1229                 netif_err(tp, probe, dev, "Get ether addr fail\n");
1230         } else if (!is_valid_ether_addr(sa.sa_data)) {
1231                 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1232                           sa.sa_data);
1233                 eth_hw_addr_random(dev);
1234                 ether_addr_copy(sa.sa_data, dev->dev_addr);
1235                 ret = rtl8152_set_mac_address(dev, &sa);
1236                 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1237                            sa.sa_data);
1238         } else {
1239                 if (tp->version == RTL_VER_01)
1240                         ether_addr_copy(dev->dev_addr, sa.sa_data);
1241                 else
1242                         ret = rtl8152_set_mac_address(dev, &sa);
1243         }
1244
1245         return ret;
1246 }
1247
1248 static void read_bulk_callback(struct urb *urb)
1249 {
1250         struct net_device *netdev;
1251         int status = urb->status;
1252         struct rx_agg *agg;
1253         struct r8152 *tp;
1254
1255         agg = urb->context;
1256         if (!agg)
1257                 return;
1258
1259         tp = agg->context;
1260         if (!tp)
1261                 return;
1262
1263         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1264                 return;
1265
1266         if (!test_bit(WORK_ENABLE, &tp->flags))
1267                 return;
1268
1269         netdev = tp->netdev;
1270
1271         /* When link down, the driver would cancel all bulks. */
1272         /* This avoid the re-submitting bulk */
1273         if (!netif_carrier_ok(netdev))
1274                 return;
1275
1276         usb_mark_last_busy(tp->udev);
1277
1278         switch (status) {
1279         case 0:
1280                 if (urb->actual_length < ETH_ZLEN)
1281                         break;
1282
1283                 spin_lock(&tp->rx_lock);
1284                 list_add_tail(&agg->list, &tp->rx_done);
1285                 spin_unlock(&tp->rx_lock);
1286                 napi_schedule(&tp->napi);
1287                 return;
1288         case -ESHUTDOWN:
1289                 set_bit(RTL8152_UNPLUG, &tp->flags);
1290                 netif_device_detach(tp->netdev);
1291                 return;
1292         case -ENOENT:
1293                 return; /* the urb is in unlink state */
1294         case -ETIME:
1295                 if (net_ratelimit())
1296                         netdev_warn(netdev, "maybe reset is needed?\n");
1297                 break;
1298         default:
1299                 if (net_ratelimit())
1300                         netdev_warn(netdev, "Rx status %d\n", status);
1301                 break;
1302         }
1303
1304         r8152_submit_rx(tp, agg, GFP_ATOMIC);
1305 }
1306
1307 static void write_bulk_callback(struct urb *urb)
1308 {
1309         struct net_device_stats *stats;
1310         struct net_device *netdev;
1311         struct tx_agg *agg;
1312         struct r8152 *tp;
1313         int status = urb->status;
1314
1315         agg = urb->context;
1316         if (!agg)
1317                 return;
1318
1319         tp = agg->context;
1320         if (!tp)
1321                 return;
1322
1323         netdev = tp->netdev;
1324         stats = &netdev->stats;
1325         if (status) {
1326                 if (net_ratelimit())
1327                         netdev_warn(netdev, "Tx status %d\n", status);
1328                 stats->tx_errors += agg->skb_num;
1329         } else {
1330                 stats->tx_packets += agg->skb_num;
1331                 stats->tx_bytes += agg->skb_len;
1332         }
1333
1334         spin_lock(&tp->tx_lock);
1335         list_add_tail(&agg->list, &tp->tx_free);
1336         spin_unlock(&tp->tx_lock);
1337
1338         usb_autopm_put_interface_async(tp->intf);
1339
1340         if (!netif_carrier_ok(netdev))
1341                 return;
1342
1343         if (!test_bit(WORK_ENABLE, &tp->flags))
1344                 return;
1345
1346         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1347                 return;
1348
1349         if (!skb_queue_empty(&tp->tx_queue))
1350                 napi_schedule(&tp->napi);
1351 }
1352
1353 static void intr_callback(struct urb *urb)
1354 {
1355         struct r8152 *tp;
1356         __le16 *d;
1357         int status = urb->status;
1358         int res;
1359
1360         tp = urb->context;
1361         if (!tp)
1362                 return;
1363
1364         if (!test_bit(WORK_ENABLE, &tp->flags))
1365                 return;
1366
1367         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1368                 return;
1369
1370         switch (status) {
1371         case 0:                 /* success */
1372                 break;
1373         case -ECONNRESET:       /* unlink */
1374         case -ESHUTDOWN:
1375                 netif_device_detach(tp->netdev);
1376         case -ENOENT:
1377         case -EPROTO:
1378                 netif_info(tp, intr, tp->netdev,
1379                            "Stop submitting intr, status %d\n", status);
1380                 return;
1381         case -EOVERFLOW:
1382                 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1383                 goto resubmit;
1384         /* -EPIPE:  should clear the halt */
1385         default:
1386                 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1387                 goto resubmit;
1388         }
1389
1390         d = urb->transfer_buffer;
1391         if (INTR_LINK & __le16_to_cpu(d[0])) {
1392                 if (!netif_carrier_ok(tp->netdev)) {
1393                         set_bit(RTL8152_LINK_CHG, &tp->flags);
1394                         schedule_delayed_work(&tp->schedule, 0);
1395                 }
1396         } else {
1397                 if (netif_carrier_ok(tp->netdev)) {
1398                         netif_stop_queue(tp->netdev);
1399                         set_bit(RTL8152_LINK_CHG, &tp->flags);
1400                         schedule_delayed_work(&tp->schedule, 0);
1401                 }
1402         }
1403
1404 resubmit:
1405         res = usb_submit_urb(urb, GFP_ATOMIC);
1406         if (res == -ENODEV) {
1407                 set_bit(RTL8152_UNPLUG, &tp->flags);
1408                 netif_device_detach(tp->netdev);
1409         } else if (res) {
1410                 netif_err(tp, intr, tp->netdev,
1411                           "can't resubmit intr, status %d\n", res);
1412         }
1413 }
1414
1415 static inline void *rx_agg_align(void *data)
1416 {
1417         return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1418 }
1419
1420 static inline void *tx_agg_align(void *data)
1421 {
1422         return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1423 }
1424
1425 static void free_all_mem(struct r8152 *tp)
1426 {
1427         int i;
1428
1429         for (i = 0; i < RTL8152_MAX_RX; i++) {
1430                 usb_free_urb(tp->rx_info[i].urb);
1431                 tp->rx_info[i].urb = NULL;
1432
1433                 kfree(tp->rx_info[i].buffer);
1434                 tp->rx_info[i].buffer = NULL;
1435                 tp->rx_info[i].head = NULL;
1436         }
1437
1438         for (i = 0; i < RTL8152_MAX_TX; i++) {
1439                 usb_free_urb(tp->tx_info[i].urb);
1440                 tp->tx_info[i].urb = NULL;
1441
1442                 kfree(tp->tx_info[i].buffer);
1443                 tp->tx_info[i].buffer = NULL;
1444                 tp->tx_info[i].head = NULL;
1445         }
1446
1447         usb_free_urb(tp->intr_urb);
1448         tp->intr_urb = NULL;
1449
1450         kfree(tp->intr_buff);
1451         tp->intr_buff = NULL;
1452 }
1453
1454 static int alloc_all_mem(struct r8152 *tp)
1455 {
1456         struct net_device *netdev = tp->netdev;
1457         struct usb_interface *intf = tp->intf;
1458         struct usb_host_interface *alt = intf->cur_altsetting;
1459         struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1460         struct urb *urb;
1461         int node, i;
1462         u8 *buf;
1463
1464         node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1465
1466         spin_lock_init(&tp->rx_lock);
1467         spin_lock_init(&tp->tx_lock);
1468         INIT_LIST_HEAD(&tp->tx_free);
1469         INIT_LIST_HEAD(&tp->rx_done);
1470         skb_queue_head_init(&tp->tx_queue);
1471         skb_queue_head_init(&tp->rx_queue);
1472
1473         for (i = 0; i < RTL8152_MAX_RX; i++) {
1474                 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1475                 if (!buf)
1476                         goto err1;
1477
1478                 if (buf != rx_agg_align(buf)) {
1479                         kfree(buf);
1480                         buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
1481                                            node);
1482                         if (!buf)
1483                                 goto err1;
1484                 }
1485
1486                 urb = usb_alloc_urb(0, GFP_KERNEL);
1487                 if (!urb) {
1488                         kfree(buf);
1489                         goto err1;
1490                 }
1491
1492                 INIT_LIST_HEAD(&tp->rx_info[i].list);
1493                 tp->rx_info[i].context = tp;
1494                 tp->rx_info[i].urb = urb;
1495                 tp->rx_info[i].buffer = buf;
1496                 tp->rx_info[i].head = rx_agg_align(buf);
1497         }
1498
1499         for (i = 0; i < RTL8152_MAX_TX; i++) {
1500                 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1501                 if (!buf)
1502                         goto err1;
1503
1504                 if (buf != tx_agg_align(buf)) {
1505                         kfree(buf);
1506                         buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1507                                            node);
1508                         if (!buf)
1509                                 goto err1;
1510                 }
1511
1512                 urb = usb_alloc_urb(0, GFP_KERNEL);
1513                 if (!urb) {
1514                         kfree(buf);
1515                         goto err1;
1516                 }
1517
1518                 INIT_LIST_HEAD(&tp->tx_info[i].list);
1519                 tp->tx_info[i].context = tp;
1520                 tp->tx_info[i].urb = urb;
1521                 tp->tx_info[i].buffer = buf;
1522                 tp->tx_info[i].head = tx_agg_align(buf);
1523
1524                 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1525         }
1526
1527         tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1528         if (!tp->intr_urb)
1529                 goto err1;
1530
1531         tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1532         if (!tp->intr_buff)
1533                 goto err1;
1534
1535         tp->intr_interval = (int)ep_intr->desc.bInterval;
1536         usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1537                          tp->intr_buff, INTBUFSIZE, intr_callback,
1538                          tp, tp->intr_interval);
1539
1540         return 0;
1541
1542 err1:
1543         free_all_mem(tp);
1544         return -ENOMEM;
1545 }
1546
1547 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1548 {
1549         struct tx_agg *agg = NULL;
1550         unsigned long flags;
1551
1552         if (list_empty(&tp->tx_free))
1553                 return NULL;
1554
1555         spin_lock_irqsave(&tp->tx_lock, flags);
1556         if (!list_empty(&tp->tx_free)) {
1557                 struct list_head *cursor;
1558
1559                 cursor = tp->tx_free.next;
1560                 list_del_init(cursor);
1561                 agg = list_entry(cursor, struct tx_agg, list);
1562         }
1563         spin_unlock_irqrestore(&tp->tx_lock, flags);
1564
1565         return agg;
1566 }
1567
1568 /* r8152_csum_workaround()
1569  * The hw limites the value the transport offset. When the offset is out of the
1570  * range, calculate the checksum by sw.
1571  */
1572 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1573                                   struct sk_buff_head *list)
1574 {
1575         if (skb_shinfo(skb)->gso_size) {
1576                 netdev_features_t features = tp->netdev->features;
1577                 struct sk_buff_head seg_list;
1578                 struct sk_buff *segs, *nskb;
1579
1580                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1581                 segs = skb_gso_segment(skb, features);
1582                 if (IS_ERR(segs) || !segs)
1583                         goto drop;
1584
1585                 __skb_queue_head_init(&seg_list);
1586
1587                 do {
1588                         nskb = segs;
1589                         segs = segs->next;
1590                         nskb->next = NULL;
1591                         __skb_queue_tail(&seg_list, nskb);
1592                 } while (segs);
1593
1594                 skb_queue_splice(&seg_list, list);
1595                 dev_kfree_skb(skb);
1596         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1597                 if (skb_checksum_help(skb) < 0)
1598                         goto drop;
1599
1600                 __skb_queue_head(list, skb);
1601         } else {
1602                 struct net_device_stats *stats;
1603
1604 drop:
1605                 stats = &tp->netdev->stats;
1606                 stats->tx_dropped++;
1607                 dev_kfree_skb(skb);
1608         }
1609 }
1610
1611 /* msdn_giant_send_check()
1612  * According to the document of microsoft, the TCP Pseudo Header excludes the
1613  * packet length for IPv6 TCP large packets.
1614  */
1615 static int msdn_giant_send_check(struct sk_buff *skb)
1616 {
1617         const struct ipv6hdr *ipv6h;
1618         struct tcphdr *th;
1619         int ret;
1620
1621         ret = skb_cow_head(skb, 0);
1622         if (ret)
1623                 return ret;
1624
1625         ipv6h = ipv6_hdr(skb);
1626         th = tcp_hdr(skb);
1627
1628         th->check = 0;
1629         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1630
1631         return ret;
1632 }
1633
1634 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1635 {
1636         if (skb_vlan_tag_present(skb)) {
1637                 u32 opts2;
1638
1639                 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
1640                 desc->opts2 |= cpu_to_le32(opts2);
1641         }
1642 }
1643
1644 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1645 {
1646         u32 opts2 = le32_to_cpu(desc->opts2);
1647
1648         if (opts2 & RX_VLAN_TAG)
1649                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1650                                        swab16(opts2 & 0xffff));
1651 }
1652
1653 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1654                          struct sk_buff *skb, u32 len, u32 transport_offset)
1655 {
1656         u32 mss = skb_shinfo(skb)->gso_size;
1657         u32 opts1, opts2 = 0;
1658         int ret = TX_CSUM_SUCCESS;
1659
1660         WARN_ON_ONCE(len > TX_LEN_MAX);
1661
1662         opts1 = len | TX_FS | TX_LS;
1663
1664         if (mss) {
1665                 if (transport_offset > GTTCPHO_MAX) {
1666                         netif_warn(tp, tx_err, tp->netdev,
1667                                    "Invalid transport offset 0x%x for TSO\n",
1668                                    transport_offset);
1669                         ret = TX_CSUM_TSO;
1670                         goto unavailable;
1671                 }
1672
1673                 switch (vlan_get_protocol(skb)) {
1674                 case htons(ETH_P_IP):
1675                         opts1 |= GTSENDV4;
1676                         break;
1677
1678                 case htons(ETH_P_IPV6):
1679                         if (msdn_giant_send_check(skb)) {
1680                                 ret = TX_CSUM_TSO;
1681                                 goto unavailable;
1682                         }
1683                         opts1 |= GTSENDV6;
1684                         break;
1685
1686                 default:
1687                         WARN_ON_ONCE(1);
1688                         break;
1689                 }
1690
1691                 opts1 |= transport_offset << GTTCPHO_SHIFT;
1692                 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1693         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1694                 u8 ip_protocol;
1695
1696                 if (transport_offset > TCPHO_MAX) {
1697                         netif_warn(tp, tx_err, tp->netdev,
1698                                    "Invalid transport offset 0x%x\n",
1699                                    transport_offset);
1700                         ret = TX_CSUM_NONE;
1701                         goto unavailable;
1702                 }
1703
1704                 switch (vlan_get_protocol(skb)) {
1705                 case htons(ETH_P_IP):
1706                         opts2 |= IPV4_CS;
1707                         ip_protocol = ip_hdr(skb)->protocol;
1708                         break;
1709
1710                 case htons(ETH_P_IPV6):
1711                         opts2 |= IPV6_CS;
1712                         ip_protocol = ipv6_hdr(skb)->nexthdr;
1713                         break;
1714
1715                 default:
1716                         ip_protocol = IPPROTO_RAW;
1717                         break;
1718                 }
1719
1720                 if (ip_protocol == IPPROTO_TCP)
1721                         opts2 |= TCP_CS;
1722                 else if (ip_protocol == IPPROTO_UDP)
1723                         opts2 |= UDP_CS;
1724                 else
1725                         WARN_ON_ONCE(1);
1726
1727                 opts2 |= transport_offset << TCPHO_SHIFT;
1728         }
1729
1730         desc->opts2 = cpu_to_le32(opts2);
1731         desc->opts1 = cpu_to_le32(opts1);
1732
1733 unavailable:
1734         return ret;
1735 }
1736
1737 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1738 {
1739         struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1740         int remain, ret;
1741         u8 *tx_data;
1742
1743         __skb_queue_head_init(&skb_head);
1744         spin_lock(&tx_queue->lock);
1745         skb_queue_splice_init(tx_queue, &skb_head);
1746         spin_unlock(&tx_queue->lock);
1747
1748         tx_data = agg->head;
1749         agg->skb_num = 0;
1750         agg->skb_len = 0;
1751         remain = agg_buf_sz;
1752
1753         while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
1754                 struct tx_desc *tx_desc;
1755                 struct sk_buff *skb;
1756                 unsigned int len;
1757                 u32 offset;
1758
1759                 skb = __skb_dequeue(&skb_head);
1760                 if (!skb)
1761                         break;
1762
1763                 len = skb->len + sizeof(*tx_desc);
1764
1765                 if (len > remain) {
1766                         __skb_queue_head(&skb_head, skb);
1767                         break;
1768                 }
1769
1770                 tx_data = tx_agg_align(tx_data);
1771                 tx_desc = (struct tx_desc *)tx_data;
1772
1773                 offset = (u32)skb_transport_offset(skb);
1774
1775                 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1776                         r8152_csum_workaround(tp, skb, &skb_head);
1777                         continue;
1778                 }
1779
1780                 rtl_tx_vlan_tag(tx_desc, skb);
1781
1782                 tx_data += sizeof(*tx_desc);
1783
1784                 len = skb->len;
1785                 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1786                         struct net_device_stats *stats = &tp->netdev->stats;
1787
1788                         stats->tx_dropped++;
1789                         dev_kfree_skb_any(skb);
1790                         tx_data -= sizeof(*tx_desc);
1791                         continue;
1792                 }
1793
1794                 tx_data += len;
1795                 agg->skb_len += len;
1796                 agg->skb_num++;
1797
1798                 dev_kfree_skb_any(skb);
1799
1800                 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
1801         }
1802
1803         if (!skb_queue_empty(&skb_head)) {
1804                 spin_lock(&tx_queue->lock);
1805                 skb_queue_splice(&skb_head, tx_queue);
1806                 spin_unlock(&tx_queue->lock);
1807         }
1808
1809         netif_tx_lock(tp->netdev);
1810
1811         if (netif_queue_stopped(tp->netdev) &&
1812             skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1813                 netif_wake_queue(tp->netdev);
1814
1815         netif_tx_unlock(tp->netdev);
1816
1817         ret = usb_autopm_get_interface_async(tp->intf);
1818         if (ret < 0)
1819                 goto out_tx_fill;
1820
1821         usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1822                           agg->head, (int)(tx_data - (u8 *)agg->head),
1823                           (usb_complete_t)write_bulk_callback, agg);
1824
1825         ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
1826         if (ret < 0)
1827                 usb_autopm_put_interface_async(tp->intf);
1828
1829 out_tx_fill:
1830         return ret;
1831 }
1832
1833 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1834 {
1835         u8 checksum = CHECKSUM_NONE;
1836         u32 opts2, opts3;
1837
1838         if (!(tp->netdev->features & NETIF_F_RXCSUM))
1839                 goto return_result;
1840
1841         opts2 = le32_to_cpu(rx_desc->opts2);
1842         opts3 = le32_to_cpu(rx_desc->opts3);
1843
1844         if (opts2 & RD_IPV4_CS) {
1845                 if (opts3 & IPF)
1846                         checksum = CHECKSUM_NONE;
1847                 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
1848                         checksum = CHECKSUM_NONE;
1849                 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
1850                         checksum = CHECKSUM_NONE;
1851                 else
1852                         checksum = CHECKSUM_UNNECESSARY;
1853         } else if (opts2 & RD_IPV6_CS) {
1854                 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1855                         checksum = CHECKSUM_UNNECESSARY;
1856                 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1857                         checksum = CHECKSUM_UNNECESSARY;
1858         }
1859
1860 return_result:
1861         return checksum;
1862 }
1863
1864 static int rx_bottom(struct r8152 *tp, int budget)
1865 {
1866         unsigned long flags;
1867         struct list_head *cursor, *next, rx_queue;
1868         int ret = 0, work_done = 0;
1869         struct napi_struct *napi = &tp->napi;
1870
1871         if (!skb_queue_empty(&tp->rx_queue)) {
1872                 while (work_done < budget) {
1873                         struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
1874                         struct net_device *netdev = tp->netdev;
1875                         struct net_device_stats *stats = &netdev->stats;
1876                         unsigned int pkt_len;
1877
1878                         if (!skb)
1879                                 break;
1880
1881                         pkt_len = skb->len;
1882                         napi_gro_receive(napi, skb);
1883                         work_done++;
1884                         stats->rx_packets++;
1885                         stats->rx_bytes += pkt_len;
1886                 }
1887         }
1888
1889         if (list_empty(&tp->rx_done))
1890                 goto out1;
1891
1892         INIT_LIST_HEAD(&rx_queue);
1893         spin_lock_irqsave(&tp->rx_lock, flags);
1894         list_splice_init(&tp->rx_done, &rx_queue);
1895         spin_unlock_irqrestore(&tp->rx_lock, flags);
1896
1897         list_for_each_safe(cursor, next, &rx_queue) {
1898                 struct rx_desc *rx_desc;
1899                 struct rx_agg *agg;
1900                 int len_used = 0;
1901                 struct urb *urb;
1902                 u8 *rx_data;
1903
1904                 list_del_init(cursor);
1905
1906                 agg = list_entry(cursor, struct rx_agg, list);
1907                 urb = agg->urb;
1908                 if (urb->actual_length < ETH_ZLEN)
1909                         goto submit;
1910
1911                 rx_desc = agg->head;
1912                 rx_data = agg->head;
1913                 len_used += sizeof(struct rx_desc);
1914
1915                 while (urb->actual_length > len_used) {
1916                         struct net_device *netdev = tp->netdev;
1917                         struct net_device_stats *stats = &netdev->stats;
1918                         unsigned int pkt_len;
1919                         struct sk_buff *skb;
1920
1921                         /* limite the skb numbers for rx_queue */
1922                         if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
1923                                 break;
1924
1925                         pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1926                         if (pkt_len < ETH_ZLEN)
1927                                 break;
1928
1929                         len_used += pkt_len;
1930                         if (urb->actual_length < len_used)
1931                                 break;
1932
1933                         pkt_len -= ETH_FCS_LEN;
1934                         rx_data += sizeof(struct rx_desc);
1935
1936                         skb = napi_alloc_skb(napi, pkt_len);
1937                         if (!skb) {
1938                                 stats->rx_dropped++;
1939                                 goto find_next_rx;
1940                         }
1941
1942                         skb->ip_summed = r8152_rx_csum(tp, rx_desc);
1943                         memcpy(skb->data, rx_data, pkt_len);
1944                         skb_put(skb, pkt_len);
1945                         skb->protocol = eth_type_trans(skb, netdev);
1946                         rtl_rx_vlan_tag(rx_desc, skb);
1947                         if (work_done < budget) {
1948                                 napi_gro_receive(napi, skb);
1949                                 work_done++;
1950                                 stats->rx_packets++;
1951                                 stats->rx_bytes += pkt_len;
1952                         } else {
1953                                 __skb_queue_tail(&tp->rx_queue, skb);
1954                         }
1955
1956 find_next_rx:
1957                         rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN);
1958                         rx_desc = (struct rx_desc *)rx_data;
1959                         len_used = (int)(rx_data - (u8 *)agg->head);
1960                         len_used += sizeof(struct rx_desc);
1961                 }
1962
1963 submit:
1964                 if (!ret) {
1965                         ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1966                 } else {
1967                         urb->actual_length = 0;
1968                         list_add_tail(&agg->list, next);
1969                 }
1970         }
1971
1972         if (!list_empty(&rx_queue)) {
1973                 spin_lock_irqsave(&tp->rx_lock, flags);
1974                 list_splice_tail(&rx_queue, &tp->rx_done);
1975                 spin_unlock_irqrestore(&tp->rx_lock, flags);
1976         }
1977
1978 out1:
1979         return work_done;
1980 }
1981
1982 static void tx_bottom(struct r8152 *tp)
1983 {
1984         int res;
1985
1986         do {
1987                 struct tx_agg *agg;
1988
1989                 if (skb_queue_empty(&tp->tx_queue))
1990                         break;
1991
1992                 agg = r8152_get_tx_agg(tp);
1993                 if (!agg)
1994                         break;
1995
1996                 res = r8152_tx_agg_fill(tp, agg);
1997                 if (res) {
1998                         struct net_device *netdev = tp->netdev;
1999
2000                         if (res == -ENODEV) {
2001                                 set_bit(RTL8152_UNPLUG, &tp->flags);
2002                                 netif_device_detach(netdev);
2003                         } else {
2004                                 struct net_device_stats *stats = &netdev->stats;
2005                                 unsigned long flags;
2006
2007                                 netif_warn(tp, tx_err, netdev,
2008                                            "failed tx_urb %d\n", res);
2009                                 stats->tx_dropped += agg->skb_num;
2010
2011                                 spin_lock_irqsave(&tp->tx_lock, flags);
2012                                 list_add_tail(&agg->list, &tp->tx_free);
2013                                 spin_unlock_irqrestore(&tp->tx_lock, flags);
2014                         }
2015                 }
2016         } while (res == 0);
2017 }
2018
2019 static void bottom_half(struct r8152 *tp)
2020 {
2021         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2022                 return;
2023
2024         if (!test_bit(WORK_ENABLE, &tp->flags))
2025                 return;
2026
2027         /* When link down, the driver would cancel all bulks. */
2028         /* This avoid the re-submitting bulk */
2029         if (!netif_carrier_ok(tp->netdev))
2030                 return;
2031
2032         clear_bit(SCHEDULE_NAPI, &tp->flags);
2033
2034         tx_bottom(tp);
2035 }
2036
2037 static int r8152_poll(struct napi_struct *napi, int budget)
2038 {
2039         struct r8152 *tp = container_of(napi, struct r8152, napi);
2040         int work_done;
2041
2042         work_done = rx_bottom(tp, budget);
2043         bottom_half(tp);
2044
2045         if (work_done < budget) {
2046                 if (!napi_complete_done(napi, work_done))
2047                         goto out;
2048                 if (!list_empty(&tp->rx_done))
2049                         napi_schedule(napi);
2050                 else if (!skb_queue_empty(&tp->tx_queue) &&
2051                          !list_empty(&tp->tx_free))
2052                         napi_schedule(napi);
2053         }
2054
2055 out:
2056         return work_done;
2057 }
2058
2059 static
2060 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
2061 {
2062         int ret;
2063
2064         /* The rx would be stopped, so skip submitting */
2065         if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
2066             !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
2067                 return 0;
2068
2069         usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
2070                           agg->head, agg_buf_sz,
2071                           (usb_complete_t)read_bulk_callback, agg);
2072
2073         ret = usb_submit_urb(agg->urb, mem_flags);
2074         if (ret == -ENODEV) {
2075                 set_bit(RTL8152_UNPLUG, &tp->flags);
2076                 netif_device_detach(tp->netdev);
2077         } else if (ret) {
2078                 struct urb *urb = agg->urb;
2079                 unsigned long flags;
2080
2081                 urb->actual_length = 0;
2082                 spin_lock_irqsave(&tp->rx_lock, flags);
2083                 list_add_tail(&agg->list, &tp->rx_done);
2084                 spin_unlock_irqrestore(&tp->rx_lock, flags);
2085
2086                 netif_err(tp, rx_err, tp->netdev,
2087                           "Couldn't submit rx[%p], ret = %d\n", agg, ret);
2088
2089                 napi_schedule(&tp->napi);
2090         }
2091
2092         return ret;
2093 }
2094
2095 static void rtl_drop_queued_tx(struct r8152 *tp)
2096 {
2097         struct net_device_stats *stats = &tp->netdev->stats;
2098         struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2099         struct sk_buff *skb;
2100
2101         if (skb_queue_empty(tx_queue))
2102                 return;
2103
2104         __skb_queue_head_init(&skb_head);
2105         spin_lock_bh(&tx_queue->lock);
2106         skb_queue_splice_init(tx_queue, &skb_head);
2107         spin_unlock_bh(&tx_queue->lock);
2108
2109         while ((skb = __skb_dequeue(&skb_head))) {
2110                 dev_kfree_skb(skb);
2111                 stats->tx_dropped++;
2112         }
2113 }
2114
2115 static void rtl8152_tx_timeout(struct net_device *netdev)
2116 {
2117         struct r8152 *tp = netdev_priv(netdev);
2118
2119         netif_warn(tp, tx_err, netdev, "Tx timeout\n");
2120
2121         usb_queue_reset_device(tp->intf);
2122 }
2123
2124 static void rtl8152_set_rx_mode(struct net_device *netdev)
2125 {
2126         struct r8152 *tp = netdev_priv(netdev);
2127
2128         if (netif_carrier_ok(netdev)) {
2129                 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2130                 schedule_delayed_work(&tp->schedule, 0);
2131         }
2132 }
2133
2134 static void _rtl8152_set_rx_mode(struct net_device *netdev)
2135 {
2136         struct r8152 *tp = netdev_priv(netdev);
2137         u32 mc_filter[2];       /* Multicast hash filter */
2138         __le32 tmp[2];
2139         u32 ocp_data;
2140
2141         netif_stop_queue(netdev);
2142         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2143         ocp_data &= ~RCR_ACPT_ALL;
2144         ocp_data |= RCR_AB | RCR_APM;
2145
2146         if (netdev->flags & IFF_PROMISC) {
2147                 /* Unconditionally log net taps. */
2148                 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2149                 ocp_data |= RCR_AM | RCR_AAP;
2150                 mc_filter[1] = 0xffffffff;
2151                 mc_filter[0] = 0xffffffff;
2152         } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
2153                    (netdev->flags & IFF_ALLMULTI)) {
2154                 /* Too many to filter perfectly -- accept all multicasts. */
2155                 ocp_data |= RCR_AM;
2156                 mc_filter[1] = 0xffffffff;
2157                 mc_filter[0] = 0xffffffff;
2158         } else {
2159                 struct netdev_hw_addr *ha;
2160
2161                 mc_filter[1] = 0;
2162                 mc_filter[0] = 0;
2163                 netdev_for_each_mc_addr(ha, netdev) {
2164                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2165
2166                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2167                         ocp_data |= RCR_AM;
2168                 }
2169         }
2170
2171         tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2172         tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2173
2174         pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
2175         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2176         netif_wake_queue(netdev);
2177 }
2178
2179 static netdev_features_t
2180 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2181                        netdev_features_t features)
2182 {
2183         u32 mss = skb_shinfo(skb)->gso_size;
2184         int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2185         int offset = skb_transport_offset(skb);
2186
2187         if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
2188                 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2189         else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2190                 features &= ~NETIF_F_GSO_MASK;
2191
2192         return features;
2193 }
2194
2195 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2196                                       struct net_device *netdev)
2197 {
2198         struct r8152 *tp = netdev_priv(netdev);
2199
2200         skb_tx_timestamp(skb);
2201
2202         skb_queue_tail(&tp->tx_queue, skb);
2203
2204         if (!list_empty(&tp->tx_free)) {
2205                 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2206                         set_bit(SCHEDULE_NAPI, &tp->flags);
2207                         schedule_delayed_work(&tp->schedule, 0);
2208                 } else {
2209                         usb_mark_last_busy(tp->udev);
2210                         napi_schedule(&tp->napi);
2211                 }
2212         } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2213                 netif_stop_queue(netdev);
2214         }
2215
2216         return NETDEV_TX_OK;
2217 }
2218
2219 static void r8152b_reset_packet_filter(struct r8152 *tp)
2220 {
2221         u32     ocp_data;
2222
2223         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2224         ocp_data &= ~FMC_FCR_MCU_EN;
2225         ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2226         ocp_data |= FMC_FCR_MCU_EN;
2227         ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2228 }
2229
2230 static void rtl8152_nic_reset(struct r8152 *tp)
2231 {
2232         int     i;
2233
2234         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2235
2236         for (i = 0; i < 1000; i++) {
2237                 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2238                         break;
2239                 usleep_range(100, 400);
2240         }
2241 }
2242
2243 static void set_tx_qlen(struct r8152 *tp)
2244 {
2245         struct net_device *netdev = tp->netdev;
2246
2247         tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN +
2248                                     sizeof(struct tx_desc));
2249 }
2250
2251 static inline u8 rtl8152_get_speed(struct r8152 *tp)
2252 {
2253         return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2254 }
2255
2256 static void rtl_set_eee_plus(struct r8152 *tp)
2257 {
2258         u32 ocp_data;
2259         u8 speed;
2260
2261         speed = rtl8152_get_speed(tp);
2262         if (speed & _10bps) {
2263                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2264                 ocp_data |= EEEP_CR_EEEP_TX;
2265                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2266         } else {
2267                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2268                 ocp_data &= ~EEEP_CR_EEEP_TX;
2269                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2270         }
2271 }
2272
2273 static void rxdy_gated_en(struct r8152 *tp, bool enable)
2274 {
2275         u32 ocp_data;
2276
2277         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2278         if (enable)
2279                 ocp_data |= RXDY_GATED_EN;
2280         else
2281                 ocp_data &= ~RXDY_GATED_EN;
2282         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2283 }
2284
2285 static int rtl_start_rx(struct r8152 *tp)
2286 {
2287         int i, ret = 0;
2288
2289         INIT_LIST_HEAD(&tp->rx_done);
2290         for (i = 0; i < RTL8152_MAX_RX; i++) {
2291                 INIT_LIST_HEAD(&tp->rx_info[i].list);
2292                 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
2293                 if (ret)
2294                         break;
2295         }
2296
2297         if (ret && ++i < RTL8152_MAX_RX) {
2298                 struct list_head rx_queue;
2299                 unsigned long flags;
2300
2301                 INIT_LIST_HEAD(&rx_queue);
2302
2303                 do {
2304                         struct rx_agg *agg = &tp->rx_info[i++];
2305                         struct urb *urb = agg->urb;
2306
2307                         urb->actual_length = 0;
2308                         list_add_tail(&agg->list, &rx_queue);
2309                 } while (i < RTL8152_MAX_RX);
2310
2311                 spin_lock_irqsave(&tp->rx_lock, flags);
2312                 list_splice_tail(&rx_queue, &tp->rx_done);
2313                 spin_unlock_irqrestore(&tp->rx_lock, flags);
2314         }
2315
2316         return ret;
2317 }
2318
2319 static int rtl_stop_rx(struct r8152 *tp)
2320 {
2321         int i;
2322
2323         for (i = 0; i < RTL8152_MAX_RX; i++)
2324                 usb_kill_urb(tp->rx_info[i].urb);
2325
2326         while (!skb_queue_empty(&tp->rx_queue))
2327                 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2328
2329         return 0;
2330 }
2331
2332 static int rtl_enable(struct r8152 *tp)
2333 {
2334         u32 ocp_data;
2335
2336         r8152b_reset_packet_filter(tp);
2337
2338         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2339         ocp_data |= CR_RE | CR_TE;
2340         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2341
2342         rxdy_gated_en(tp, false);
2343
2344         return 0;
2345 }
2346
2347 static int rtl8152_enable(struct r8152 *tp)
2348 {
2349         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2350                 return -ENODEV;
2351
2352         set_tx_qlen(tp);
2353         rtl_set_eee_plus(tp);
2354
2355         return rtl_enable(tp);
2356 }
2357
2358 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
2359 {
2360         ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
2361                        OWN_UPDATE | OWN_CLEAR);
2362 }
2363
2364 static void r8153_set_rx_early_timeout(struct r8152 *tp)
2365 {
2366         u32 ocp_data = tp->coalesce / 8;
2367
2368         switch (tp->version) {
2369         case RTL_VER_03:
2370         case RTL_VER_04:
2371         case RTL_VER_05:
2372         case RTL_VER_06:
2373                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2374                                ocp_data);
2375                 break;
2376
2377         case RTL_VER_08:
2378         case RTL_VER_09:
2379                 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
2380                  * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
2381                  */
2382                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2383                                128 / 8);
2384                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
2385                                ocp_data);
2386                 r8153b_rx_agg_chg_indicate(tp);
2387                 break;
2388
2389         default:
2390                 break;
2391         }
2392 }
2393
2394 static void r8153_set_rx_early_size(struct r8152 *tp)
2395 {
2396         u32 ocp_data = agg_buf_sz - rx_reserved_size(tp->netdev->mtu);
2397
2398         switch (tp->version) {
2399         case RTL_VER_03:
2400         case RTL_VER_04:
2401         case RTL_VER_05:
2402         case RTL_VER_06:
2403                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2404                                ocp_data / 4);
2405                 break;
2406         case RTL_VER_08:
2407         case RTL_VER_09:
2408                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2409                                ocp_data / 8);
2410                 r8153b_rx_agg_chg_indicate(tp);
2411                 break;
2412         default:
2413                 WARN_ON_ONCE(1);
2414                 break;
2415         }
2416 }
2417
2418 static int rtl8153_enable(struct r8152 *tp)
2419 {
2420         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2421                 return -ENODEV;
2422
2423         set_tx_qlen(tp);
2424         rtl_set_eee_plus(tp);
2425         r8153_set_rx_early_timeout(tp);
2426         r8153_set_rx_early_size(tp);
2427
2428         return rtl_enable(tp);
2429 }
2430
2431 static void rtl_disable(struct r8152 *tp)
2432 {
2433         u32 ocp_data;
2434         int i;
2435
2436         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2437                 rtl_drop_queued_tx(tp);
2438                 return;
2439         }
2440
2441         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2442         ocp_data &= ~RCR_ACPT_ALL;
2443         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2444
2445         rtl_drop_queued_tx(tp);
2446
2447         for (i = 0; i < RTL8152_MAX_TX; i++)
2448                 usb_kill_urb(tp->tx_info[i].urb);
2449
2450         rxdy_gated_en(tp, true);
2451
2452         for (i = 0; i < 1000; i++) {
2453                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2454                 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2455                         break;
2456                 usleep_range(1000, 2000);
2457         }
2458
2459         for (i = 0; i < 1000; i++) {
2460                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2461                         break;
2462                 usleep_range(1000, 2000);
2463         }
2464
2465         rtl_stop_rx(tp);
2466
2467         rtl8152_nic_reset(tp);
2468 }
2469
2470 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2471 {
2472         u32 ocp_data;
2473
2474         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2475         if (enable)
2476                 ocp_data |= POWER_CUT;
2477         else
2478                 ocp_data &= ~POWER_CUT;
2479         ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2480
2481         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2482         ocp_data &= ~RESUME_INDICATE;
2483         ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2484 }
2485
2486 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2487 {
2488         u32 ocp_data;
2489
2490         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2491         if (enable)
2492                 ocp_data |= CPCR_RX_VLAN;
2493         else
2494                 ocp_data &= ~CPCR_RX_VLAN;
2495         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2496 }
2497
2498 static int rtl8152_set_features(struct net_device *dev,
2499                                 netdev_features_t features)
2500 {
2501         netdev_features_t changed = features ^ dev->features;
2502         struct r8152 *tp = netdev_priv(dev);
2503         int ret;
2504
2505         ret = usb_autopm_get_interface(tp->intf);
2506         if (ret < 0)
2507                 goto out;
2508
2509         mutex_lock(&tp->control);
2510
2511         if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2512                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2513                         rtl_rx_vlan_en(tp, true);
2514                 else
2515                         rtl_rx_vlan_en(tp, false);
2516         }
2517
2518         mutex_unlock(&tp->control);
2519
2520         usb_autopm_put_interface(tp->intf);
2521
2522 out:
2523         return ret;
2524 }
2525
2526 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2527
2528 static u32 __rtl_get_wol(struct r8152 *tp)
2529 {
2530         u32 ocp_data;
2531         u32 wolopts = 0;
2532
2533         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2534         if (ocp_data & LINK_ON_WAKE_EN)
2535                 wolopts |= WAKE_PHY;
2536
2537         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2538         if (ocp_data & UWF_EN)
2539                 wolopts |= WAKE_UCAST;
2540         if (ocp_data & BWF_EN)
2541                 wolopts |= WAKE_BCAST;
2542         if (ocp_data & MWF_EN)
2543                 wolopts |= WAKE_MCAST;
2544
2545         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2546         if (ocp_data & MAGIC_EN)
2547                 wolopts |= WAKE_MAGIC;
2548
2549         return wolopts;
2550 }
2551
2552 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2553 {
2554         u32 ocp_data;
2555
2556         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2557
2558         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2559         ocp_data &= ~LINK_ON_WAKE_EN;
2560         if (wolopts & WAKE_PHY)
2561                 ocp_data |= LINK_ON_WAKE_EN;
2562         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2563
2564         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2565         ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
2566         if (wolopts & WAKE_UCAST)
2567                 ocp_data |= UWF_EN;
2568         if (wolopts & WAKE_BCAST)
2569                 ocp_data |= BWF_EN;
2570         if (wolopts & WAKE_MCAST)
2571                 ocp_data |= MWF_EN;
2572         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2573
2574         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2575
2576         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2577         ocp_data &= ~MAGIC_EN;
2578         if (wolopts & WAKE_MAGIC)
2579                 ocp_data |= MAGIC_EN;
2580         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2581
2582         if (wolopts & WAKE_ANY)
2583                 device_set_wakeup_enable(&tp->udev->dev, true);
2584         else
2585                 device_set_wakeup_enable(&tp->udev->dev, false);
2586 }
2587
2588 static void r8153_mac_clk_spd(struct r8152 *tp, bool enable)
2589 {
2590         /* MAC clock speed down */
2591         if (enable) {
2592                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL,
2593                                ALDPS_SPDWN_RATIO);
2594                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2,
2595                                EEE_SPDWN_RATIO);
2596                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
2597                                PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
2598                                U1U2_SPDWN_EN | L1_SPDWN_EN);
2599                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
2600                                PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
2601                                TP100_SPDWN_EN | TP500_SPDWN_EN | EEE_SPDWN_EN |
2602                                TP1000_SPDWN_EN);
2603         } else {
2604                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0);
2605                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0);
2606                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);
2607                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);
2608         }
2609 }
2610
2611 static void r8153_u1u2en(struct r8152 *tp, bool enable)
2612 {
2613         u8 u1u2[8];
2614
2615         if (enable)
2616                 memset(u1u2, 0xff, sizeof(u1u2));
2617         else
2618                 memset(u1u2, 0x00, sizeof(u1u2));
2619
2620         usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2621 }
2622
2623 static void r8153b_u1u2en(struct r8152 *tp, bool enable)
2624 {
2625         u32 ocp_data;
2626
2627         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
2628         if (enable)
2629                 ocp_data |= LPM_U1U2_EN;
2630         else
2631                 ocp_data &= ~LPM_U1U2_EN;
2632
2633         ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
2634 }
2635
2636 static void r8153_u2p3en(struct r8152 *tp, bool enable)
2637 {
2638         u32 ocp_data;
2639
2640         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2641         if (enable)
2642                 ocp_data |= U2P3_ENABLE;
2643         else
2644                 ocp_data &= ~U2P3_ENABLE;
2645         ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2646 }
2647
2648 static void r8153b_ups_flags_w1w0(struct r8152 *tp, u32 set, u32 clear)
2649 {
2650         u32 ocp_data;
2651
2652         ocp_data = ocp_read_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS);
2653         ocp_data &= ~clear;
2654         ocp_data |= set;
2655         ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ocp_data);
2656 }
2657
2658 static void r8153b_green_en(struct r8152 *tp, bool enable)
2659 {
2660         u16 data;
2661
2662         if (enable) {
2663                 sram_write(tp, 0x8045, 0);      /* 10M abiq&ldvbias */
2664                 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */
2665                 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */
2666         } else {
2667                 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */
2668                 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */
2669                 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */
2670         }
2671
2672         data = sram_read(tp, SRAM_GREEN_CFG);
2673         data |= GREEN_ETH_EN;
2674         sram_write(tp, SRAM_GREEN_CFG, data);
2675
2676         r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_GREEN, 0);
2677 }
2678
2679 static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
2680 {
2681         u16 data;
2682         int i;
2683
2684         for (i = 0; i < 500; i++) {
2685                 data = ocp_reg_read(tp, OCP_PHY_STATUS);
2686                 data &= PHY_STAT_MASK;
2687                 if (desired) {
2688                         if (data == desired)
2689                                 break;
2690                 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
2691                            data == PHY_STAT_EXT_INIT) {
2692                         break;
2693                 }
2694
2695                 msleep(20);
2696         }
2697
2698         return data;
2699 }
2700
2701 static void r8153b_ups_en(struct r8152 *tp, bool enable)
2702 {
2703         u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
2704
2705         if (enable) {
2706                 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
2707                 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2708
2709                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
2710                 ocp_data |= BIT(0);
2711                 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
2712         } else {
2713                 u16 data;
2714
2715                 ocp_data &= ~(UPS_EN | USP_PREWAKE);
2716                 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2717
2718                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
2719                 ocp_data &= ~BIT(0);
2720                 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
2721
2722                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2723                 ocp_data &= ~PCUT_STATUS;
2724                 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2725
2726                 data = r8153_phy_status(tp, 0);
2727
2728                 switch (data) {
2729                 case PHY_STAT_PWRDN:
2730                 case PHY_STAT_EXT_INIT:
2731                         r8153b_green_en(tp,
2732                                         test_bit(GREEN_ETHERNET, &tp->flags));
2733
2734                         data = r8152_mdio_read(tp, MII_BMCR);
2735                         data &= ~BMCR_PDOWN;
2736                         data |= BMCR_RESET;
2737                         r8152_mdio_write(tp, MII_BMCR, data);
2738
2739                         data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
2740
2741                 default:
2742                         if (data != PHY_STAT_LAN_ON)
2743                                 netif_warn(tp, link, tp->netdev,
2744                                            "PHY not ready");
2745                         break;
2746                 }
2747         }
2748 }
2749
2750 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
2751 {
2752         u32 ocp_data;
2753
2754         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2755         if (enable)
2756                 ocp_data |= PWR_EN | PHASE2_EN;
2757         else
2758                 ocp_data &= ~(PWR_EN | PHASE2_EN);
2759         ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2760
2761         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2762         ocp_data &= ~PCUT_STATUS;
2763         ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2764 }
2765
2766 static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
2767 {
2768         u32 ocp_data;
2769
2770         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2771         if (enable)
2772                 ocp_data |= PWR_EN | PHASE2_EN;
2773         else
2774                 ocp_data &= ~PWR_EN;
2775         ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2776
2777         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2778         ocp_data &= ~PCUT_STATUS;
2779         ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2780 }
2781
2782 static void r8153b_queue_wake(struct r8152 *tp, bool enable)
2783 {
2784         u32 ocp_data;
2785
2786         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 0xd38a);
2787         if (enable)
2788                 ocp_data |= BIT(0);
2789         else
2790                 ocp_data &= ~BIT(0);
2791         ocp_write_byte(tp, MCU_TYPE_PLA, 0xd38a, ocp_data);
2792
2793         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 0xd38c);
2794         ocp_data &= ~BIT(0);
2795         ocp_write_byte(tp, MCU_TYPE_PLA, 0xd38c, ocp_data);
2796 }
2797
2798 static bool rtl_can_wakeup(struct r8152 *tp)
2799 {
2800         struct usb_device *udev = tp->udev;
2801
2802         return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
2803 }
2804
2805 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2806 {
2807         if (enable) {
2808                 u32 ocp_data;
2809
2810                 __rtl_set_wol(tp, WAKE_ANY);
2811
2812                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2813
2814                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2815                 ocp_data |= LINK_OFF_WAKE_EN;
2816                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2817
2818                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2819         } else {
2820                 u32 ocp_data;
2821
2822                 __rtl_set_wol(tp, tp->saved_wolopts);
2823
2824                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2825
2826                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2827                 ocp_data &= ~LINK_OFF_WAKE_EN;
2828                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2829
2830                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2831         }
2832 }
2833
2834 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
2835 {
2836         if (enable) {
2837                 r8153_u1u2en(tp, false);
2838                 r8153_u2p3en(tp, false);
2839                 r8153_mac_clk_spd(tp, true);
2840                 rtl_runtime_suspend_enable(tp, true);
2841         } else {
2842                 rtl_runtime_suspend_enable(tp, false);
2843                 r8153_mac_clk_spd(tp, false);
2844
2845                 switch (tp->version) {
2846                 case RTL_VER_03:
2847                 case RTL_VER_04:
2848                         break;
2849                 case RTL_VER_05:
2850                 case RTL_VER_06:
2851                 default:
2852                         r8153_u2p3en(tp, true);
2853                         break;
2854                 }
2855
2856                 r8153_u1u2en(tp, true);
2857         }
2858 }
2859
2860 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
2861 {
2862         if (enable) {
2863                 r8153b_queue_wake(tp, true);
2864                 r8153b_u1u2en(tp, false);
2865                 r8153_u2p3en(tp, false);
2866                 rtl_runtime_suspend_enable(tp, true);
2867                 r8153b_ups_en(tp, true);
2868         } else {
2869                 r8153b_ups_en(tp, false);
2870                 r8153b_queue_wake(tp, false);
2871                 rtl_runtime_suspend_enable(tp, false);
2872                 r8153_u2p3en(tp, true);
2873                 r8153b_u1u2en(tp, true);
2874         }
2875 }
2876
2877 static void r8153_teredo_off(struct r8152 *tp)
2878 {
2879         u32 ocp_data;
2880
2881         switch (tp->version) {
2882         case RTL_VER_01:
2883         case RTL_VER_02:
2884         case RTL_VER_03:
2885         case RTL_VER_04:
2886         case RTL_VER_05:
2887         case RTL_VER_06:
2888         case RTL_VER_07:
2889                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2890                 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
2891                               OOB_TEREDO_EN);
2892                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2893                 break;
2894
2895         case RTL_VER_08:
2896         case RTL_VER_09:
2897                 /* The bit 0 ~ 7 are relative with teredo settings. They are
2898                  * W1C (write 1 to clear), so set all 1 to disable it.
2899                  */
2900                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
2901                 break;
2902
2903         default:
2904                 break;
2905         }
2906
2907         ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2908         ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2909         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2910 }
2911
2912 static void rtl_reset_bmu(struct r8152 *tp)
2913 {
2914         u32 ocp_data;
2915
2916         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
2917         ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
2918         ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2919         ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
2920         ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2921 }
2922
2923 static void r8152_aldps_en(struct r8152 *tp, bool enable)
2924 {
2925         if (enable) {
2926                 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2927                                                     LINKENA | DIS_SDSAVE);
2928         } else {
2929                 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
2930                                                     DIS_SDSAVE);
2931                 msleep(20);
2932         }
2933 }
2934
2935 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
2936 {
2937         ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
2938         ocp_reg_write(tp, OCP_EEE_DATA, reg);
2939         ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
2940 }
2941
2942 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
2943 {
2944         u16 data;
2945
2946         r8152_mmd_indirect(tp, dev, reg);
2947         data = ocp_reg_read(tp, OCP_EEE_DATA);
2948         ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2949
2950         return data;
2951 }
2952
2953 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
2954 {
2955         r8152_mmd_indirect(tp, dev, reg);
2956         ocp_reg_write(tp, OCP_EEE_DATA, data);
2957         ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2958 }
2959
2960 static void r8152_eee_en(struct r8152 *tp, bool enable)
2961 {
2962         u16 config1, config2, config3;
2963         u32 ocp_data;
2964
2965         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
2966         config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
2967         config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
2968         config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
2969
2970         if (enable) {
2971                 ocp_data |= EEE_RX_EN | EEE_TX_EN;
2972                 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
2973                 config1 |= sd_rise_time(1);
2974                 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
2975                 config3 |= fast_snr(42);
2976         } else {
2977                 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
2978                 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
2979                              RX_QUIET_EN);
2980                 config1 |= sd_rise_time(7);
2981                 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
2982                 config3 |= fast_snr(511);
2983         }
2984
2985         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
2986         ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
2987         ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
2988         ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
2989 }
2990
2991 static void r8152b_enable_eee(struct r8152 *tp)
2992 {
2993         r8152_eee_en(tp, true);
2994         r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
2995 }
2996
2997 static void r8152b_enable_fc(struct r8152 *tp)
2998 {
2999         u16 anar;
3000
3001         anar = r8152_mdio_read(tp, MII_ADVERTISE);
3002         anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3003         r8152_mdio_write(tp, MII_ADVERTISE, anar);
3004 }
3005
3006 static void rtl8152_disable(struct r8152 *tp)
3007 {
3008         r8152_aldps_en(tp, false);
3009         rtl_disable(tp);
3010         r8152_aldps_en(tp, true);
3011 }
3012
3013 static void r8152b_hw_phy_cfg(struct r8152 *tp)
3014 {
3015         r8152b_enable_eee(tp);
3016         r8152_aldps_en(tp, true);
3017         r8152b_enable_fc(tp);
3018
3019         set_bit(PHY_RESET, &tp->flags);
3020 }
3021
3022 static void r8152b_exit_oob(struct r8152 *tp)
3023 {
3024         u32 ocp_data;
3025         int i;
3026
3027         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3028         ocp_data &= ~RCR_ACPT_ALL;
3029         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3030
3031         rxdy_gated_en(tp, true);
3032         r8153_teredo_off(tp);
3033         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3034         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
3035
3036         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3037         ocp_data &= ~NOW_IS_OOB;
3038         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3039
3040         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3041         ocp_data &= ~MCU_BORW_EN;
3042         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3043
3044         for (i = 0; i < 1000; i++) {
3045                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3046                 if (ocp_data & LINK_LIST_READY)
3047                         break;
3048                 usleep_range(1000, 2000);
3049         }
3050
3051         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3052         ocp_data |= RE_INIT_LL;
3053         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3054
3055         for (i = 0; i < 1000; i++) {
3056                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3057                 if (ocp_data & LINK_LIST_READY)
3058                         break;
3059                 usleep_range(1000, 2000);
3060         }
3061
3062         rtl8152_nic_reset(tp);
3063
3064         /* rx share fifo credit full threshold */
3065         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
3066
3067         if (tp->udev->speed == USB_SPEED_FULL ||
3068             tp->udev->speed == USB_SPEED_LOW) {
3069                 /* rx share fifo credit near full threshold */
3070                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
3071                                 RXFIFO_THR2_FULL);
3072                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
3073                                 RXFIFO_THR3_FULL);
3074         } else {
3075                 /* rx share fifo credit near full threshold */
3076                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
3077                                 RXFIFO_THR2_HIGH);
3078                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
3079                                 RXFIFO_THR3_HIGH);
3080         }
3081
3082         /* TX share fifo free credit full threshold */
3083         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
3084
3085         ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
3086         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
3087         ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
3088                         TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
3089
3090         rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
3091
3092         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
3093
3094         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
3095         ocp_data |= TCR0_AUTO_FIFO;
3096         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
3097 }
3098
3099 static void r8152b_enter_oob(struct r8152 *tp)
3100 {
3101         u32 ocp_data;
3102         int i;
3103
3104         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3105         ocp_data &= ~NOW_IS_OOB;
3106         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3107
3108         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
3109         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
3110         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
3111
3112         rtl_disable(tp);
3113
3114         for (i = 0; i < 1000; i++) {
3115                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3116                 if (ocp_data & LINK_LIST_READY)
3117                         break;
3118                 usleep_range(1000, 2000);
3119         }
3120
3121         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3122         ocp_data |= RE_INIT_LL;
3123         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3124
3125         for (i = 0; i < 1000; i++) {
3126                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3127                 if (ocp_data & LINK_LIST_READY)
3128                         break;
3129                 usleep_range(1000, 2000);
3130         }
3131
3132         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
3133
3134         rtl_rx_vlan_en(tp, true);
3135
3136         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
3137         ocp_data |= ALDPS_PROXY_MODE;
3138         ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
3139
3140         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3141         ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
3142         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3143
3144         rxdy_gated_en(tp, false);
3145
3146         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3147         ocp_data |= RCR_APM | RCR_AM | RCR_AB;
3148         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3149 }
3150
3151 static int r8153_patch_request(struct r8152 *tp, bool request)
3152 {
3153         u16 data;
3154         int i;
3155
3156         data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
3157         if (request)
3158                 data |= PATCH_REQUEST;
3159         else
3160                 data &= ~PATCH_REQUEST;
3161         ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
3162
3163         for (i = 0; request && i < 5000; i++) {
3164                 usleep_range(1000, 2000);
3165                 if (ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)
3166                         break;
3167         }
3168
3169         if (request && !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
3170                 netif_err(tp, drv, tp->netdev, "patch request fail\n");
3171                 r8153_patch_request(tp, false);
3172                 return -ETIME;
3173         } else {
3174                 return 0;
3175         }
3176 }
3177
3178 static void r8153_aldps_en(struct r8152 *tp, bool enable)
3179 {
3180         u16 data;
3181
3182         data = ocp_reg_read(tp, OCP_POWER_CFG);
3183         if (enable) {
3184                 data |= EN_ALDPS;
3185                 ocp_reg_write(tp, OCP_POWER_CFG, data);
3186         } else {
3187                 int i;
3188
3189                 data &= ~EN_ALDPS;
3190                 ocp_reg_write(tp, OCP_POWER_CFG, data);
3191                 for (i = 0; i < 20; i++) {
3192                         usleep_range(1000, 2000);
3193                         if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
3194                                 break;
3195                 }
3196         }
3197 }
3198
3199 static void r8153b_aldps_en(struct r8152 *tp, bool enable)
3200 {
3201         r8153_aldps_en(tp, enable);
3202
3203         if (enable)
3204                 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_ALDPS, 0);
3205         else
3206                 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_ALDPS);
3207 }
3208
3209 static void r8153_eee_en(struct r8152 *tp, bool enable)
3210 {
3211         u32 ocp_data;
3212         u16 config;
3213
3214         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3215         config = ocp_reg_read(tp, OCP_EEE_CFG);
3216
3217         if (enable) {
3218                 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3219                 config |= EEE10_EN;
3220         } else {
3221                 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3222                 config &= ~EEE10_EN;
3223         }
3224
3225         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3226         ocp_reg_write(tp, OCP_EEE_CFG, config);
3227 }
3228
3229 static void r8153b_eee_en(struct r8152 *tp, bool enable)
3230 {
3231         r8153_eee_en(tp, enable);
3232
3233         if (enable)
3234                 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_EEE, 0);
3235         else
3236                 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_EEE);
3237 }
3238
3239 static void r8153b_enable_fc(struct r8152 *tp)
3240 {
3241         r8152b_enable_fc(tp);
3242         r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_FLOW_CTR, 0);
3243 }
3244
3245 static void r8153_hw_phy_cfg(struct r8152 *tp)
3246 {
3247         u32 ocp_data;
3248         u16 data;
3249
3250         /* disable ALDPS before updating the PHY parameters */
3251         r8153_aldps_en(tp, false);
3252
3253         /* disable EEE before updating the PHY parameters */
3254         r8153_eee_en(tp, false);
3255         ocp_reg_write(tp, OCP_EEE_ADV, 0);
3256
3257         if (tp->version == RTL_VER_03) {
3258                 data = ocp_reg_read(tp, OCP_EEE_CFG);
3259                 data &= ~CTAP_SHORT_EN;
3260                 ocp_reg_write(tp, OCP_EEE_CFG, data);
3261         }
3262
3263         data = ocp_reg_read(tp, OCP_POWER_CFG);
3264         data |= EEE_CLKDIV_EN;
3265         ocp_reg_write(tp, OCP_POWER_CFG, data);
3266
3267         data = ocp_reg_read(tp, OCP_DOWN_SPEED);
3268         data |= EN_10M_BGOFF;
3269         ocp_reg_write(tp, OCP_DOWN_SPEED, data);
3270         data = ocp_reg_read(tp, OCP_POWER_CFG);
3271         data |= EN_10M_PLLOFF;
3272         ocp_reg_write(tp, OCP_POWER_CFG, data);
3273         sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
3274
3275         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3276         ocp_data |= PFM_PWM_SWITCH;
3277         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3278
3279         /* Enable LPF corner auto tune */
3280         sram_write(tp, SRAM_LPF_CFG, 0xf70f);
3281
3282         /* Adjust 10M Amplitude */
3283         sram_write(tp, SRAM_10M_AMP1, 0x00af);
3284         sram_write(tp, SRAM_10M_AMP2, 0x0208);
3285
3286         r8153_eee_en(tp, true);
3287         ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
3288
3289         r8153_aldps_en(tp, true);
3290         r8152b_enable_fc(tp);
3291
3292         switch (tp->version) {
3293         case RTL_VER_03:
3294         case RTL_VER_04:
3295                 break;
3296         case RTL_VER_05:
3297         case RTL_VER_06:
3298         default:
3299                 r8153_u2p3en(tp, true);
3300                 break;
3301         }
3302
3303         set_bit(PHY_RESET, &tp->flags);
3304 }
3305
3306 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
3307 {
3308         u32 ocp_data;
3309
3310         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
3311         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
3312         ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9;  /* data of bit16 */
3313         ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
3314
3315         return ocp_data;
3316 }
3317
3318 static void r8153b_hw_phy_cfg(struct r8152 *tp)
3319 {
3320         u32 ocp_data, ups_flags = 0;
3321         u16 data;
3322
3323         /* disable ALDPS before updating the PHY parameters */
3324         r8153b_aldps_en(tp, false);
3325
3326         /* disable EEE before updating the PHY parameters */
3327         r8153b_eee_en(tp, false);
3328         ocp_reg_write(tp, OCP_EEE_ADV, 0);
3329
3330         r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
3331
3332         data = sram_read(tp, SRAM_GREEN_CFG);
3333         data |= R_TUNE_EN;
3334         sram_write(tp, SRAM_GREEN_CFG, data);
3335         data = ocp_reg_read(tp, OCP_NCTL_CFG);
3336         data |= PGA_RETURN_EN;
3337         ocp_reg_write(tp, OCP_NCTL_CFG, data);
3338
3339         /* ADC Bias Calibration:
3340          * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
3341          * bit (bit3) to rebuild the real 16-bit data. Write the data to the
3342          * ADC ioffset.
3343          */
3344         ocp_data = r8152_efuse_read(tp, 0x7d);
3345         data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
3346         if (data != 0xffff)
3347                 ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
3348
3349         /* ups mode tx-link-pulse timing adjustment:
3350          * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
3351          * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
3352          */
3353         ocp_data = ocp_reg_read(tp, 0xc426);
3354         ocp_data &= 0x3fff;
3355         if (ocp_data) {
3356                 u32 swr_cnt_1ms_ini;
3357
3358                 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
3359                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
3360                 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
3361                 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
3362         }
3363
3364         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3365         ocp_data |= PFM_PWM_SWITCH;
3366         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3367
3368         /* Advnace EEE */
3369         if (!r8153_patch_request(tp, true)) {
3370                 data = ocp_reg_read(tp, OCP_POWER_CFG);
3371                 data |= EEE_CLKDIV_EN;
3372                 ocp_reg_write(tp, OCP_POWER_CFG, data);
3373
3374                 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
3375                 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
3376                 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
3377
3378                 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
3379                 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
3380
3381                 ups_flags |= UPS_FLAGS_EN_10M_CKDIV | UPS_FLAGS_250M_CKDIV |
3382                              UPS_FLAGS_EN_EEE_CKDIV | UPS_FLAGS_EEE_CMOD_LV_EN |
3383                              UPS_FLAGS_EEE_PLLOFF_GIGA;
3384
3385                 r8153_patch_request(tp, false);
3386         }
3387
3388         r8153b_ups_flags_w1w0(tp, ups_flags, 0);
3389
3390         r8153b_eee_en(tp, true);
3391         ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
3392
3393         r8153b_aldps_en(tp, true);
3394         r8153b_enable_fc(tp);
3395         r8153_u2p3en(tp, true);
3396
3397         set_bit(PHY_RESET, &tp->flags);
3398 }
3399
3400 static void r8153_first_init(struct r8152 *tp)
3401 {
3402         u32 ocp_data;
3403         int i;
3404
3405         r8153_mac_clk_spd(tp, false);
3406         rxdy_gated_en(tp, true);
3407         r8153_teredo_off(tp);
3408
3409         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3410         ocp_data &= ~RCR_ACPT_ALL;
3411         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3412
3413         rtl8152_nic_reset(tp);
3414         rtl_reset_bmu(tp);
3415
3416         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3417         ocp_data &= ~NOW_IS_OOB;
3418         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3419
3420         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3421         ocp_data &= ~MCU_BORW_EN;
3422         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3423
3424         for (i = 0; i < 1000; i++) {
3425                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3426                 if (ocp_data & LINK_LIST_READY)
3427                         break;
3428                 usleep_range(1000, 2000);
3429         }
3430
3431         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3432         ocp_data |= RE_INIT_LL;
3433         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3434
3435         for (i = 0; i < 1000; i++) {
3436                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3437                 if (ocp_data & LINK_LIST_READY)
3438                         break;
3439                 usleep_range(1000, 2000);
3440         }
3441
3442         rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
3443
3444         ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
3445         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
3446         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
3447
3448         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
3449         ocp_data |= TCR0_AUTO_FIFO;
3450         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
3451
3452         rtl8152_nic_reset(tp);
3453
3454         /* rx share fifo credit full threshold */
3455         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
3456         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
3457         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
3458         /* TX share fifo free credit full threshold */
3459         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
3460 }
3461
3462 static void r8153_enter_oob(struct r8152 *tp)
3463 {
3464         u32 ocp_data;
3465         int i;
3466
3467         r8153_mac_clk_spd(tp, true);
3468
3469         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3470         ocp_data &= ~NOW_IS_OOB;
3471         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3472
3473         rtl_disable(tp);
3474         rtl_reset_bmu(tp);
3475
3476         for (i = 0; i < 1000; i++) {
3477                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3478                 if (ocp_data & LINK_LIST_READY)
3479                         break;
3480                 usleep_range(1000, 2000);
3481         }
3482
3483         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3484         ocp_data |= RE_INIT_LL;
3485         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3486
3487         for (i = 0; i < 1000; i++) {
3488                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3489                 if (ocp_data & LINK_LIST_READY)
3490                         break;
3491                 usleep_range(1000, 2000);
3492         }
3493
3494         ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
3495         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
3496
3497         switch (tp->version) {
3498         case RTL_VER_03:
3499         case RTL_VER_04:
3500         case RTL_VER_05:
3501         case RTL_VER_06:
3502                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
3503                 ocp_data &= ~TEREDO_WAKE_MASK;
3504                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
3505                 break;
3506
3507         case RTL_VER_08:
3508         case RTL_VER_09:
3509                 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
3510                  * type. Set it to zero. bits[7:0] are the W1C bits about
3511                  * the events. Set them to all 1 to clear them.
3512                  */
3513                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
3514                 break;
3515
3516         default:
3517                 break;
3518         }
3519
3520         rtl_rx_vlan_en(tp, true);
3521
3522         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
3523         ocp_data |= ALDPS_PROXY_MODE;
3524         ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
3525
3526         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3527         ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
3528         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3529
3530         rxdy_gated_en(tp, false);
3531
3532         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3533         ocp_data |= RCR_APM | RCR_AM | RCR_AB;
3534         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3535 }
3536
3537 static void rtl8153_disable(struct r8152 *tp)
3538 {
3539         r8153_aldps_en(tp, false);
3540         rtl_disable(tp);
3541         rtl_reset_bmu(tp);
3542         r8153_aldps_en(tp, true);
3543 }
3544
3545 static void rtl8153b_disable(struct r8152 *tp)
3546 {
3547         r8153b_aldps_en(tp, false);
3548         rtl_disable(tp);
3549         rtl_reset_bmu(tp);
3550         r8153b_aldps_en(tp, true);
3551 }
3552
3553 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
3554 {
3555         u16 bmcr, anar, gbcr;
3556         enum spd_duplex speed_duplex;
3557         int ret = 0;
3558
3559         anar = r8152_mdio_read(tp, MII_ADVERTISE);
3560         anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
3561                   ADVERTISE_100HALF | ADVERTISE_100FULL);
3562         if (tp->mii.supports_gmii) {
3563                 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
3564                 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
3565         } else {
3566                 gbcr = 0;
3567         }
3568
3569         if (autoneg == AUTONEG_DISABLE) {
3570                 if (speed == SPEED_10) {
3571                         bmcr = 0;
3572                         anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3573                         speed_duplex = FORCE_10M_HALF;
3574                 } else if (speed == SPEED_100) {
3575                         bmcr = BMCR_SPEED100;
3576                         anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3577                         speed_duplex = FORCE_100M_HALF;
3578                 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
3579                         bmcr = BMCR_SPEED1000;
3580                         gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
3581                         speed_duplex = NWAY_1000M_FULL;
3582                 } else {
3583                         ret = -EINVAL;
3584                         goto out;
3585                 }
3586
3587                 if (duplex == DUPLEX_FULL) {
3588                         bmcr |= BMCR_FULLDPLX;
3589                         if (speed != SPEED_1000)
3590                                 speed_duplex++;
3591                 }
3592         } else {
3593                 if (speed == SPEED_10) {
3594                         if (duplex == DUPLEX_FULL) {
3595                                 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3596                                 speed_duplex = NWAY_10M_FULL;
3597                         } else {
3598                                 anar |= ADVERTISE_10HALF;
3599                                 speed_duplex = NWAY_10M_HALF;
3600                         }
3601                 } else if (speed == SPEED_100) {
3602                         if (duplex == DUPLEX_FULL) {
3603                                 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3604                                 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3605                                 speed_duplex = NWAY_100M_FULL;
3606                         } else {
3607                                 anar |= ADVERTISE_10HALF;
3608                                 anar |= ADVERTISE_100HALF;
3609                                 speed_duplex = NWAY_100M_HALF;
3610                         }
3611                 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
3612                         if (duplex == DUPLEX_FULL) {
3613                                 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3614                                 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3615                                 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
3616                         } else {
3617                                 anar |= ADVERTISE_10HALF;
3618                                 anar |= ADVERTISE_100HALF;
3619                                 gbcr |= ADVERTISE_1000HALF;
3620                         }
3621                         speed_duplex = NWAY_1000M_FULL;
3622                 } else {
3623                         ret = -EINVAL;
3624                         goto out;
3625                 }
3626
3627                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
3628         }
3629
3630         if (test_and_clear_bit(PHY_RESET, &tp->flags))
3631                 bmcr |= BMCR_RESET;
3632
3633         if (tp->mii.supports_gmii)
3634                 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
3635
3636         r8152_mdio_write(tp, MII_ADVERTISE, anar);
3637         r8152_mdio_write(tp, MII_BMCR, bmcr);
3638
3639         switch (tp->version) {
3640         case RTL_VER_08:
3641         case RTL_VER_09:
3642                 r8153b_ups_flags_w1w0(tp, ups_flags_speed(speed_duplex),
3643                                       UPS_FLAGS_SPEED_MASK);
3644                 break;
3645
3646         default:
3647                 break;
3648         }
3649
3650         if (bmcr & BMCR_RESET) {
3651                 int i;
3652
3653                 for (i = 0; i < 50; i++) {
3654                         msleep(20);
3655                         if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
3656                                 break;
3657                 }
3658         }
3659
3660 out:
3661         return ret;
3662 }
3663
3664 static void rtl8152_up(struct r8152 *tp)
3665 {
3666         if (test_bit(RTL8152_UNPLUG, &tp->flags))
3667                 return;
3668
3669         r8152_aldps_en(tp, false);
3670         r8152b_exit_oob(tp);
3671         r8152_aldps_en(tp, true);
3672 }
3673
3674 static void rtl8152_down(struct r8152 *tp)
3675 {
3676         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3677                 rtl_drop_queued_tx(tp);
3678                 return;
3679         }
3680
3681         r8152_power_cut_en(tp, false);
3682         r8152_aldps_en(tp, false);
3683         r8152b_enter_oob(tp);
3684         r8152_aldps_en(tp, true);
3685 }
3686
3687 static void rtl8153_up(struct r8152 *tp)
3688 {
3689         if (test_bit(RTL8152_UNPLUG, &tp->flags))
3690                 return;
3691
3692         r8153_u1u2en(tp, false);
3693         r8153_u2p3en(tp, false);
3694         r8153_aldps_en(tp, false);
3695         r8153_first_init(tp);
3696         r8153_aldps_en(tp, true);
3697
3698         switch (tp->version) {
3699         case RTL_VER_03:
3700         case RTL_VER_04:
3701                 break;
3702         case RTL_VER_05:
3703         case RTL_VER_06:
3704         default:
3705                 r8153_u2p3en(tp, true);
3706                 break;
3707         }
3708
3709         r8153_u1u2en(tp, true);
3710 }
3711
3712 static void rtl8153_down(struct r8152 *tp)
3713 {
3714         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3715                 rtl_drop_queued_tx(tp);
3716                 return;
3717         }
3718
3719         r8153_u1u2en(tp, false);
3720         r8153_u2p3en(tp, false);
3721         r8153_power_cut_en(tp, false);
3722         r8153_aldps_en(tp, false);
3723         r8153_enter_oob(tp);
3724         r8153_aldps_en(tp, true);
3725 }
3726
3727 static void rtl8153b_up(struct r8152 *tp)
3728 {
3729         if (test_bit(RTL8152_UNPLUG, &tp->flags))
3730                 return;
3731
3732         r8153b_u1u2en(tp, false);
3733         r8153_u2p3en(tp, false);
3734         r8153b_aldps_en(tp, false);
3735
3736         r8153_first_init(tp);
3737         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
3738
3739         r8153b_aldps_en(tp, true);
3740         r8153_u2p3en(tp, true);
3741         r8153b_u1u2en(tp, true);
3742 }
3743
3744 static void rtl8153b_down(struct r8152 *tp)
3745 {
3746         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3747                 rtl_drop_queued_tx(tp);
3748                 return;
3749         }
3750
3751         r8153b_u1u2en(tp, false);
3752         r8153_u2p3en(tp, false);
3753         r8153b_power_cut_en(tp, false);
3754         r8153b_aldps_en(tp, false);
3755         r8153_enter_oob(tp);
3756         r8153b_aldps_en(tp, true);
3757 }
3758
3759 static bool rtl8152_in_nway(struct r8152 *tp)
3760 {
3761         u16 nway_state;
3762
3763         ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
3764         tp->ocp_base = 0x2000;
3765         ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c);         /* phy state */
3766         nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
3767
3768         /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
3769         if (nway_state & 0xc000)
3770                 return false;
3771         else
3772                 return true;
3773 }
3774
3775 static bool rtl8153_in_nway(struct r8152 *tp)
3776 {
3777         u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
3778
3779         if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
3780                 return false;
3781         else
3782                 return true;
3783 }
3784
3785 static void set_carrier(struct r8152 *tp)
3786 {
3787         struct net_device *netdev = tp->netdev;
3788         struct napi_struct *napi = &tp->napi;
3789         u8 speed;
3790
3791         speed = rtl8152_get_speed(tp);
3792
3793         if (speed & LINK_STATUS) {
3794                 if (!netif_carrier_ok(netdev)) {
3795                         tp->rtl_ops.enable(tp);
3796                         set_bit(RTL8152_SET_RX_MODE, &tp->flags);
3797                         netif_stop_queue(netdev);
3798                         napi_disable(napi);
3799                         netif_carrier_on(netdev);
3800                         rtl_start_rx(tp);
3801                         napi_enable(&tp->napi);
3802                         netif_wake_queue(netdev);
3803                         netif_info(tp, link, netdev, "carrier on\n");
3804                 } else if (netif_queue_stopped(netdev) &&
3805                            skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
3806                         netif_wake_queue(netdev);
3807                 }
3808         } else {
3809                 if (netif_carrier_ok(netdev)) {
3810                         netif_carrier_off(netdev);
3811                         napi_disable(napi);
3812                         tp->rtl_ops.disable(tp);
3813                         napi_enable(napi);
3814                         netif_info(tp, link, netdev, "carrier off\n");
3815                 }
3816         }
3817 }
3818
3819 static void rtl_work_func_t(struct work_struct *work)
3820 {
3821         struct r8152 *tp = container_of(work, struct r8152, schedule.work);
3822
3823         /* If the device is unplugged or !netif_running(), the workqueue
3824          * doesn't need to wake the device, and could return directly.
3825          */
3826         if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
3827                 return;
3828
3829         if (usb_autopm_get_interface(tp->intf) < 0)
3830                 return;
3831
3832         if (!test_bit(WORK_ENABLE, &tp->flags))
3833                 goto out1;
3834
3835         if (!mutex_trylock(&tp->control)) {
3836                 schedule_delayed_work(&tp->schedule, 0);
3837                 goto out1;
3838         }
3839
3840         if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
3841                 set_carrier(tp);
3842
3843         if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
3844                 _rtl8152_set_rx_mode(tp->netdev);
3845
3846         /* don't schedule napi before linking */
3847         if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) &&
3848             netif_carrier_ok(tp->netdev))
3849                 napi_schedule(&tp->napi);
3850
3851         mutex_unlock(&tp->control);
3852
3853 out1:
3854         usb_autopm_put_interface(tp->intf);
3855 }
3856
3857 static void rtl_hw_phy_work_func_t(struct work_struct *work)
3858 {
3859         struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
3860
3861         if (test_bit(RTL8152_UNPLUG, &tp->flags))
3862                 return;
3863
3864         if (usb_autopm_get_interface(tp->intf) < 0)
3865                 return;
3866
3867         mutex_lock(&tp->control);
3868
3869         tp->rtl_ops.hw_phy_cfg(tp);
3870
3871         rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex);
3872
3873         mutex_unlock(&tp->control);
3874
3875         usb_autopm_put_interface(tp->intf);
3876 }
3877
3878 #ifdef CONFIG_PM_SLEEP
3879 static int rtl_notifier(struct notifier_block *nb, unsigned long action,
3880                         void *data)
3881 {
3882         struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
3883
3884         switch (action) {
3885         case PM_HIBERNATION_PREPARE:
3886         case PM_SUSPEND_PREPARE:
3887                 usb_autopm_get_interface(tp->intf);
3888                 break;
3889
3890         case PM_POST_HIBERNATION:
3891         case PM_POST_SUSPEND:
3892                 usb_autopm_put_interface(tp->intf);
3893                 break;
3894
3895         case PM_POST_RESTORE:
3896         case PM_RESTORE_PREPARE:
3897         default:
3898                 break;
3899         }
3900
3901         return NOTIFY_DONE;
3902 }
3903 #endif
3904
3905 static int rtl8152_open(struct net_device *netdev)
3906 {
3907         struct r8152 *tp = netdev_priv(netdev);
3908         int res = 0;
3909
3910         res = alloc_all_mem(tp);
3911         if (res)
3912                 goto out;
3913
3914         res = usb_autopm_get_interface(tp->intf);
3915         if (res < 0)
3916                 goto out_free;
3917
3918         mutex_lock(&tp->control);
3919
3920         tp->rtl_ops.up(tp);
3921
3922         netif_carrier_off(netdev);
3923         netif_start_queue(netdev);
3924         set_bit(WORK_ENABLE, &tp->flags);
3925
3926         res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3927         if (res) {
3928                 if (res == -ENODEV)
3929                         netif_device_detach(tp->netdev);
3930                 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
3931                            res);
3932                 goto out_unlock;
3933         }
3934         napi_enable(&tp->napi);
3935
3936         mutex_unlock(&tp->control);
3937
3938         usb_autopm_put_interface(tp->intf);
3939 #ifdef CONFIG_PM_SLEEP
3940         tp->pm_notifier.notifier_call = rtl_notifier;
3941         register_pm_notifier(&tp->pm_notifier);
3942 #endif
3943         return 0;
3944
3945 out_unlock:
3946         mutex_unlock(&tp->control);
3947         usb_autopm_put_interface(tp->intf);
3948 out_free:
3949         free_all_mem(tp);
3950 out:
3951         return res;
3952 }
3953
3954 static int rtl8152_close(struct net_device *netdev)
3955 {
3956         struct r8152 *tp = netdev_priv(netdev);
3957         int res = 0;
3958
3959 #ifdef CONFIG_PM_SLEEP
3960         unregister_pm_notifier(&tp->pm_notifier);
3961 #endif
3962         napi_disable(&tp->napi);
3963         clear_bit(WORK_ENABLE, &tp->flags);
3964         usb_kill_urb(tp->intr_urb);
3965         cancel_delayed_work_sync(&tp->schedule);
3966         netif_stop_queue(netdev);
3967
3968         res = usb_autopm_get_interface(tp->intf);
3969         if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
3970                 rtl_drop_queued_tx(tp);
3971                 rtl_stop_rx(tp);
3972         } else {
3973                 mutex_lock(&tp->control);
3974
3975                 tp->rtl_ops.down(tp);
3976
3977                 mutex_unlock(&tp->control);
3978
3979                 usb_autopm_put_interface(tp->intf);
3980         }
3981
3982         free_all_mem(tp);
3983
3984         return res;
3985 }
3986
3987 static void rtl_tally_reset(struct r8152 *tp)
3988 {
3989         u32 ocp_data;
3990
3991         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
3992         ocp_data |= TALLY_RESET;
3993         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
3994 }
3995
3996 static void r8152b_init(struct r8152 *tp)
3997 {
3998         u32 ocp_data;
3999         u16 data;
4000
4001         if (test_bit(RTL8152_UNPLUG, &tp->flags))
4002                 return;
4003
4004         data = r8152_mdio_read(tp, MII_BMCR);
4005         if (data & BMCR_PDOWN) {
4006                 data &= ~BMCR_PDOWN;
4007                 r8152_mdio_write(tp, MII_BMCR, data);
4008         }
4009
4010         r8152_aldps_en(tp, false);
4011
4012         if (tp->version == RTL_VER_01) {
4013                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
4014                 ocp_data &= ~LED_MODE_MASK;
4015                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
4016         }
4017
4018         r8152_power_cut_en(tp, false);
4019
4020         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
4021         ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
4022         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
4023         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
4024         ocp_data &= ~MCU_CLK_RATIO_MASK;
4025         ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
4026         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
4027         ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
4028                    SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
4029         ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
4030
4031         rtl_tally_reset(tp);
4032
4033         /* enable rx aggregation */
4034         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4035         ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4036         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4037 }
4038
4039 static void r8153_init(struct r8152 *tp)
4040 {
4041         u32 ocp_data;
4042         u16 data;
4043         int i;
4044
4045         if (test_bit(RTL8152_UNPLUG, &tp->flags))
4046                 return;
4047
4048         r8153_u1u2en(tp, false);
4049
4050         for (i = 0; i < 500; i++) {
4051                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
4052                     AUTOLOAD_DONE)
4053                         break;
4054                 msleep(20);
4055         }
4056
4057         data = r8153_phy_status(tp, 0);
4058
4059         if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
4060             tp->version == RTL_VER_05)
4061                 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
4062
4063         data = r8152_mdio_read(tp, MII_BMCR);
4064         if (data & BMCR_PDOWN) {
4065                 data &= ~BMCR_PDOWN;
4066                 r8152_mdio_write(tp, MII_BMCR, data);
4067         }
4068
4069         data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
4070
4071         r8153_u2p3en(tp, false);
4072
4073         if (tp->version == RTL_VER_04) {
4074                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
4075                 ocp_data &= ~pwd_dn_scale_mask;
4076                 ocp_data |= pwd_dn_scale(96);
4077                 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
4078
4079                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
4080                 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
4081                 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
4082         } else if (tp->version == RTL_VER_05) {
4083                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
4084                 ocp_data &= ~ECM_ALDPS;
4085                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
4086
4087                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
4088                 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
4089                         ocp_data &= ~DYNAMIC_BURST;
4090                 else
4091                         ocp_data |= DYNAMIC_BURST;
4092                 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
4093         } else if (tp->version == RTL_VER_06) {
4094                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
4095                 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
4096                         ocp_data &= ~DYNAMIC_BURST;
4097                 else
4098                         ocp_data |= DYNAMIC_BURST;
4099                 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
4100         }
4101
4102         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
4103         ocp_data |= EP4_FULL_FC;
4104         ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
4105
4106         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
4107         ocp_data &= ~TIMER11_EN;
4108         ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
4109
4110         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
4111         ocp_data &= ~LED_MODE_MASK;
4112         ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
4113
4114         ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
4115         if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
4116                 ocp_data |= LPM_TIMER_500MS;
4117         else
4118                 ocp_data |= LPM_TIMER_500US;
4119         ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
4120
4121         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
4122         ocp_data &= ~SEN_VAL_MASK;
4123         ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
4124         ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
4125
4126         ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
4127
4128         r8153_power_cut_en(tp, false);
4129         r8153_u1u2en(tp, true);
4130         r8153_mac_clk_spd(tp, false);
4131         usb_enable_lpm(tp->udev);
4132
4133         /* rx aggregation */
4134         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4135         ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4136         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4137
4138         rtl_tally_reset(tp);
4139
4140         switch (tp->udev->speed) {
4141         case USB_SPEED_SUPER:
4142         case USB_SPEED_SUPER_PLUS:
4143                 tp->coalesce = COALESCE_SUPER;
4144                 break;
4145         case USB_SPEED_HIGH:
4146                 tp->coalesce = COALESCE_HIGH;
4147                 break;
4148         default:
4149                 tp->coalesce = COALESCE_SLOW;
4150                 break;
4151         }
4152 }
4153
4154 static void r8153b_init(struct r8152 *tp)
4155 {
4156         u32 ocp_data;
4157         u16 data;
4158         int i;
4159
4160         if (test_bit(RTL8152_UNPLUG, &tp->flags))
4161                 return;
4162
4163         r8153b_u1u2en(tp, false);
4164
4165         for (i = 0; i < 500; i++) {
4166                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
4167                     AUTOLOAD_DONE)
4168                         break;
4169                 msleep(20);
4170         }
4171
4172         data = r8153_phy_status(tp, 0);
4173
4174         data = r8152_mdio_read(tp, MII_BMCR);
4175         if (data & BMCR_PDOWN) {
4176                 data &= ~BMCR_PDOWN;
4177                 r8152_mdio_write(tp, MII_BMCR, data);
4178         }
4179
4180         data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
4181
4182         r8153_u2p3en(tp, false);
4183
4184         /* MSC timer = 0xfff * 8ms = 32760 ms */
4185         ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
4186
4187         /* U1/U2/L1 idle timer. 500 us */
4188         ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
4189
4190         r8153b_power_cut_en(tp, false);
4191         r8153b_ups_en(tp, false);
4192         r8153b_queue_wake(tp, false);
4193         rtl_runtime_suspend_enable(tp, false);
4194         r8153b_u1u2en(tp, true);
4195         usb_enable_lpm(tp->udev);
4196
4197         /* MAC clock speed down */
4198         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
4199         ocp_data |= MAC_CLK_SPDWN_EN;
4200         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
4201
4202         set_bit(GREEN_ETHERNET, &tp->flags);
4203
4204         /* rx aggregation */
4205         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4206         ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4207         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4208
4209         rtl_tally_reset(tp);
4210
4211         tp->coalesce = 15000;   /* 15 us */
4212 }
4213
4214 static int rtl8152_pre_reset(struct usb_interface *intf)
4215 {
4216         struct r8152 *tp = usb_get_intfdata(intf);
4217         struct net_device *netdev;
4218
4219         if (!tp)
4220                 return 0;
4221
4222         netdev = tp->netdev;
4223         if (!netif_running(netdev))
4224                 return 0;
4225
4226         netif_stop_queue(netdev);
4227         napi_disable(&tp->napi);
4228         clear_bit(WORK_ENABLE, &tp->flags);
4229         usb_kill_urb(tp->intr_urb);
4230         cancel_delayed_work_sync(&tp->schedule);
4231         if (netif_carrier_ok(netdev)) {
4232                 mutex_lock(&tp->control);
4233                 tp->rtl_ops.disable(tp);
4234                 mutex_unlock(&tp->control);
4235         }
4236
4237         return 0;
4238 }
4239
4240 static int rtl8152_post_reset(struct usb_interface *intf)
4241 {
4242         struct r8152 *tp = usb_get_intfdata(intf);
4243         struct net_device *netdev;
4244
4245         if (!tp)
4246                 return 0;
4247
4248         netdev = tp->netdev;
4249         if (!netif_running(netdev))
4250                 return 0;
4251
4252         set_bit(WORK_ENABLE, &tp->flags);
4253         if (netif_carrier_ok(netdev)) {
4254                 mutex_lock(&tp->control);
4255                 tp->rtl_ops.enable(tp);
4256                 rtl_start_rx(tp);
4257                 rtl8152_set_rx_mode(netdev);
4258                 mutex_unlock(&tp->control);
4259         }
4260
4261         napi_enable(&tp->napi);
4262         netif_wake_queue(netdev);
4263         usb_submit_urb(tp->intr_urb, GFP_KERNEL);
4264
4265         if (!list_empty(&tp->rx_done))
4266                 napi_schedule(&tp->napi);
4267
4268         return 0;
4269 }
4270
4271 static bool delay_autosuspend(struct r8152 *tp)
4272 {
4273         bool sw_linking = !!netif_carrier_ok(tp->netdev);
4274         bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
4275
4276         /* This means a linking change occurs and the driver doesn't detect it,
4277          * yet. If the driver has disabled tx/rx and hw is linking on, the
4278          * device wouldn't wake up by receiving any packet.
4279          */
4280         if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
4281                 return true;
4282
4283         /* If the linking down is occurred by nway, the device may miss the
4284          * linking change event. And it wouldn't wake when linking on.
4285          */
4286         if (!sw_linking && tp->rtl_ops.in_nway(tp))
4287                 return true;
4288         else if (!skb_queue_empty(&tp->tx_queue))
4289                 return true;
4290         else
4291                 return false;
4292 }
4293
4294 static int rtl8152_runtime_resume(struct r8152 *tp)
4295 {
4296         struct net_device *netdev = tp->netdev;
4297
4298         if (netif_running(netdev) && netdev->flags & IFF_UP) {
4299                 struct napi_struct *napi = &tp->napi;
4300
4301                 tp->rtl_ops.autosuspend_en(tp, false);
4302                 napi_disable(napi);
4303                 set_bit(WORK_ENABLE, &tp->flags);
4304
4305                 if (netif_carrier_ok(netdev)) {
4306                         if (rtl8152_get_speed(tp) & LINK_STATUS) {
4307                                 rtl_start_rx(tp);
4308                         } else {
4309                                 netif_carrier_off(netdev);
4310                                 tp->rtl_ops.disable(tp);
4311                                 netif_info(tp, link, netdev, "linking down\n");
4312                         }
4313                 }
4314
4315                 napi_enable(napi);
4316                 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4317                 smp_mb__after_atomic();
4318
4319                 if (!list_empty(&tp->rx_done))
4320                         napi_schedule(&tp->napi);
4321
4322                 usb_submit_urb(tp->intr_urb, GFP_NOIO);
4323         } else {
4324                 if (netdev->flags & IFF_UP)
4325                         tp->rtl_ops.autosuspend_en(tp, false);
4326
4327                 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4328         }
4329
4330         return 0;
4331 }
4332
4333 static int rtl8152_system_resume(struct r8152 *tp)
4334 {
4335         struct net_device *netdev = tp->netdev;
4336
4337         netif_device_attach(netdev);
4338
4339         if (netif_running(netdev) && netdev->flags & IFF_UP) {
4340                 tp->rtl_ops.up(tp);
4341                 netif_carrier_off(netdev);
4342                 set_bit(WORK_ENABLE, &tp->flags);
4343                 usb_submit_urb(tp->intr_urb, GFP_NOIO);
4344         }
4345
4346         return 0;
4347 }
4348
4349 static int rtl8152_runtime_suspend(struct r8152 *tp)
4350 {
4351         struct net_device *netdev = tp->netdev;
4352         int ret = 0;
4353
4354         set_bit(SELECTIVE_SUSPEND, &tp->flags);
4355         smp_mb__after_atomic();
4356
4357         if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
4358                 u32 rcr = 0;
4359
4360                 if (netif_carrier_ok(netdev)) {
4361                         u32 ocp_data;
4362
4363                         rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4364                         ocp_data = rcr & ~RCR_ACPT_ALL;
4365                         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4366                         rxdy_gated_en(tp, true);
4367                         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
4368                                                  PLA_OOB_CTRL);
4369                         if (!(ocp_data & RXFIFO_EMPTY)) {
4370                                 rxdy_gated_en(tp, false);
4371                                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
4372                                 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4373                                 smp_mb__after_atomic();
4374                                 ret = -EBUSY;
4375                                 goto out1;
4376                         }
4377                 }
4378
4379                 clear_bit(WORK_ENABLE, &tp->flags);
4380                 usb_kill_urb(tp->intr_urb);
4381
4382                 tp->rtl_ops.autosuspend_en(tp, true);
4383
4384                 if (netif_carrier_ok(netdev)) {
4385                         struct napi_struct *napi = &tp->napi;
4386
4387                         napi_disable(napi);
4388                         rtl_stop_rx(tp);
4389                         rxdy_gated_en(tp, false);
4390                         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
4391                         napi_enable(napi);
4392                 }
4393
4394                 if (delay_autosuspend(tp)) {
4395                         rtl8152_runtime_resume(tp);
4396                         ret = -EBUSY;
4397                 }
4398         }
4399
4400 out1:
4401         return ret;
4402 }
4403
4404 static int rtl8152_system_suspend(struct r8152 *tp)
4405 {
4406         struct net_device *netdev = tp->netdev;
4407         int ret = 0;
4408
4409         netif_device_detach(netdev);
4410
4411         if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
4412                 struct napi_struct *napi = &tp->napi;
4413
4414                 clear_bit(WORK_ENABLE, &tp->flags);
4415                 usb_kill_urb(tp->intr_urb);
4416                 napi_disable(napi);
4417                 cancel_delayed_work_sync(&tp->schedule);
4418                 tp->rtl_ops.down(tp);
4419                 napi_enable(napi);
4420         }
4421
4422         return ret;
4423 }
4424
4425 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
4426 {
4427         struct r8152 *tp = usb_get_intfdata(intf);
4428         int ret;
4429
4430         mutex_lock(&tp->control);
4431
4432         if (PMSG_IS_AUTO(message))
4433                 ret = rtl8152_runtime_suspend(tp);
4434         else
4435                 ret = rtl8152_system_suspend(tp);
4436
4437         mutex_unlock(&tp->control);
4438
4439         return ret;
4440 }
4441
4442 static int rtl8152_resume(struct usb_interface *intf)
4443 {
4444         struct r8152 *tp = usb_get_intfdata(intf);
4445         int ret;
4446
4447         mutex_lock(&tp->control);
4448
4449         if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
4450                 ret = rtl8152_runtime_resume(tp);
4451         else
4452                 ret = rtl8152_system_resume(tp);
4453
4454         mutex_unlock(&tp->control);
4455
4456         return ret;
4457 }
4458
4459 static int rtl8152_reset_resume(struct usb_interface *intf)
4460 {
4461         struct r8152 *tp = usb_get_intfdata(intf);
4462
4463         clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4464         mutex_lock(&tp->control);
4465         tp->rtl_ops.init(tp);
4466         queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
4467         mutex_unlock(&tp->control);
4468         return rtl8152_resume(intf);
4469 }
4470
4471 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4472 {
4473         struct r8152 *tp = netdev_priv(dev);
4474
4475         if (usb_autopm_get_interface(tp->intf) < 0)
4476                 return;
4477
4478         if (!rtl_can_wakeup(tp)) {
4479                 wol->supported = 0;
4480                 wol->wolopts = 0;
4481         } else {
4482                 mutex_lock(&tp->control);
4483                 wol->supported = WAKE_ANY;
4484                 wol->wolopts = __rtl_get_wol(tp);
4485                 mutex_unlock(&tp->control);
4486         }
4487
4488         usb_autopm_put_interface(tp->intf);
4489 }
4490
4491 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4492 {
4493         struct r8152 *tp = netdev_priv(dev);
4494         int ret;
4495
4496         if (!rtl_can_wakeup(tp))
4497                 return -EOPNOTSUPP;
4498
4499         ret = usb_autopm_get_interface(tp->intf);
4500         if (ret < 0)
4501                 goto out_set_wol;
4502
4503         mutex_lock(&tp->control);
4504
4505         __rtl_set_wol(tp, wol->wolopts);
4506         tp->saved_wolopts = wol->wolopts & WAKE_ANY;
4507
4508         mutex_unlock(&tp->control);
4509
4510         usb_autopm_put_interface(tp->intf);
4511
4512 out_set_wol:
4513         return ret;
4514 }
4515
4516 static u32 rtl8152_get_msglevel(struct net_device *dev)
4517 {
4518         struct r8152 *tp = netdev_priv(dev);
4519
4520         return tp->msg_enable;
4521 }
4522
4523 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
4524 {
4525         struct r8152 *tp = netdev_priv(dev);
4526
4527         tp->msg_enable = value;
4528 }
4529
4530 static void rtl8152_get_drvinfo(struct net_device *netdev,
4531                                 struct ethtool_drvinfo *info)
4532 {
4533         struct r8152 *tp = netdev_priv(netdev);
4534
4535         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
4536         strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
4537         usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
4538 }
4539
4540 static
4541 int rtl8152_get_link_ksettings(struct net_device *netdev,
4542                                struct ethtool_link_ksettings *cmd)
4543 {
4544         struct r8152 *tp = netdev_priv(netdev);
4545         int ret;
4546
4547         if (!tp->mii.mdio_read)
4548                 return -EOPNOTSUPP;
4549
4550         ret = usb_autopm_get_interface(tp->intf);
4551         if (ret < 0)
4552                 goto out;
4553
4554         mutex_lock(&tp->control);
4555
4556         mii_ethtool_get_link_ksettings(&tp->mii, cmd);
4557
4558         mutex_unlock(&tp->control);
4559
4560         usb_autopm_put_interface(tp->intf);
4561
4562 out:
4563         return ret;
4564 }
4565
4566 static int rtl8152_set_link_ksettings(struct net_device *dev,
4567                                       const struct ethtool_link_ksettings *cmd)
4568 {
4569         struct r8152 *tp = netdev_priv(dev);
4570         int ret;
4571
4572         ret = usb_autopm_get_interface(tp->intf);
4573         if (ret < 0)
4574                 goto out;
4575
4576         mutex_lock(&tp->control);
4577
4578         ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
4579                                 cmd->base.duplex);
4580         if (!ret) {
4581                 tp->autoneg = cmd->base.autoneg;
4582                 tp->speed = cmd->base.speed;
4583                 tp->duplex = cmd->base.duplex;
4584         }
4585
4586         mutex_unlock(&tp->control);
4587
4588         usb_autopm_put_interface(tp->intf);
4589
4590 out:
4591         return ret;
4592 }
4593
4594 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
4595         "tx_packets",
4596         "rx_packets",
4597         "tx_errors",
4598         "rx_errors",
4599         "rx_missed",
4600         "align_errors",
4601         "tx_single_collisions",
4602         "tx_multi_collisions",
4603         "rx_unicast",
4604         "rx_broadcast",
4605         "rx_multicast",
4606         "tx_aborted",
4607         "tx_underrun",
4608 };
4609
4610 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
4611 {
4612         switch (sset) {
4613         case ETH_SS_STATS:
4614                 return ARRAY_SIZE(rtl8152_gstrings);
4615         default:
4616                 return -EOPNOTSUPP;
4617         }
4618 }
4619
4620 static void rtl8152_get_ethtool_stats(struct net_device *dev,
4621                                       struct ethtool_stats *stats, u64 *data)
4622 {
4623         struct r8152 *tp = netdev_priv(dev);
4624         struct tally_counter tally;
4625
4626         if (usb_autopm_get_interface(tp->intf) < 0)
4627                 return;
4628
4629         generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
4630
4631         usb_autopm_put_interface(tp->intf);
4632
4633         data[0] = le64_to_cpu(tally.tx_packets);
4634         data[1] = le64_to_cpu(tally.rx_packets);
4635         data[2] = le64_to_cpu(tally.tx_errors);
4636         data[3] = le32_to_cpu(tally.rx_errors);
4637         data[4] = le16_to_cpu(tally.rx_missed);
4638         data[5] = le16_to_cpu(tally.align_errors);
4639         data[6] = le32_to_cpu(tally.tx_one_collision);
4640         data[7] = le32_to_cpu(tally.tx_multi_collision);
4641         data[8] = le64_to_cpu(tally.rx_unicast);
4642         data[9] = le64_to_cpu(tally.rx_broadcast);
4643         data[10] = le32_to_cpu(tally.rx_multicast);
4644         data[11] = le16_to_cpu(tally.tx_aborted);
4645         data[12] = le16_to_cpu(tally.tx_underrun);
4646 }
4647
4648 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
4649 {
4650         switch (stringset) {
4651         case ETH_SS_STATS:
4652                 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
4653                 break;
4654         }
4655 }
4656
4657 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
4658 {
4659         u32 ocp_data, lp, adv, supported = 0;
4660         u16 val;
4661
4662         val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
4663         supported = mmd_eee_cap_to_ethtool_sup_t(val);
4664
4665         val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
4666         adv = mmd_eee_adv_to_ethtool_adv_t(val);
4667
4668         val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
4669         lp = mmd_eee_adv_to_ethtool_adv_t(val);
4670
4671         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4672         ocp_data &= EEE_RX_EN | EEE_TX_EN;
4673
4674         eee->eee_enabled = !!ocp_data;
4675         eee->eee_active = !!(supported & adv & lp);
4676         eee->supported = supported;
4677         eee->advertised = adv;
4678         eee->lp_advertised = lp;
4679
4680         return 0;
4681 }
4682
4683 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4684 {
4685         u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4686
4687         r8152_eee_en(tp, eee->eee_enabled);
4688
4689         if (!eee->eee_enabled)
4690                 val = 0;
4691
4692         r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4693
4694         return 0;
4695 }
4696
4697 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
4698 {
4699         u32 ocp_data, lp, adv, supported = 0;
4700         u16 val;
4701
4702         val = ocp_reg_read(tp, OCP_EEE_ABLE);
4703         supported = mmd_eee_cap_to_ethtool_sup_t(val);
4704
4705         val = ocp_reg_read(tp, OCP_EEE_ADV);
4706         adv = mmd_eee_adv_to_ethtool_adv_t(val);
4707
4708         val = ocp_reg_read(tp, OCP_EEE_LPABLE);
4709         lp = mmd_eee_adv_to_ethtool_adv_t(val);
4710
4711         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4712         ocp_data &= EEE_RX_EN | EEE_TX_EN;
4713
4714         eee->eee_enabled = !!ocp_data;
4715         eee->eee_active = !!(supported & adv & lp);
4716         eee->supported = supported;
4717         eee->advertised = adv;
4718         eee->lp_advertised = lp;
4719
4720         return 0;
4721 }
4722
4723 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4724 {
4725         u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4726
4727         r8153_eee_en(tp, eee->eee_enabled);
4728
4729         if (!eee->eee_enabled)
4730                 val = 0;
4731
4732         ocp_reg_write(tp, OCP_EEE_ADV, val);
4733
4734         return 0;
4735 }
4736
4737 static int r8153b_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4738 {
4739         u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4740
4741         r8153b_eee_en(tp, eee->eee_enabled);
4742
4743         if (!eee->eee_enabled)
4744                 val = 0;
4745
4746         ocp_reg_write(tp, OCP_EEE_ADV, val);
4747
4748         return 0;
4749 }
4750
4751 static int
4752 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
4753 {
4754         struct r8152 *tp = netdev_priv(net);
4755         int ret;
4756
4757         ret = usb_autopm_get_interface(tp->intf);
4758         if (ret < 0)
4759                 goto out;
4760
4761         mutex_lock(&tp->control);
4762
4763         ret = tp->rtl_ops.eee_get(tp, edata);
4764
4765         mutex_unlock(&tp->control);
4766
4767         usb_autopm_put_interface(tp->intf);
4768
4769 out:
4770         return ret;
4771 }
4772
4773 static int
4774 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
4775 {
4776         struct r8152 *tp = netdev_priv(net);
4777         int ret;
4778
4779         ret = usb_autopm_get_interface(tp->intf);
4780         if (ret < 0)
4781                 goto out;
4782
4783         mutex_lock(&tp->control);
4784
4785         ret = tp->rtl_ops.eee_set(tp, edata);
4786         if (!ret)
4787                 ret = mii_nway_restart(&tp->mii);
4788
4789         mutex_unlock(&tp->control);
4790
4791         usb_autopm_put_interface(tp->intf);
4792
4793 out:
4794         return ret;
4795 }
4796
4797 static int rtl8152_nway_reset(struct net_device *dev)
4798 {
4799         struct r8152 *tp = netdev_priv(dev);
4800         int ret;
4801
4802         ret = usb_autopm_get_interface(tp->intf);
4803         if (ret < 0)
4804                 goto out;
4805
4806         mutex_lock(&tp->control);
4807
4808         ret = mii_nway_restart(&tp->mii);
4809
4810         mutex_unlock(&tp->control);
4811
4812         usb_autopm_put_interface(tp->intf);
4813
4814 out:
4815         return ret;
4816 }
4817
4818 static int rtl8152_get_coalesce(struct net_device *netdev,
4819                                 struct ethtool_coalesce *coalesce)
4820 {
4821         struct r8152 *tp = netdev_priv(netdev);
4822
4823         switch (tp->version) {
4824         case RTL_VER_01:
4825         case RTL_VER_02:
4826         case RTL_VER_07:
4827                 return -EOPNOTSUPP;
4828         default:
4829                 break;
4830         }
4831
4832         coalesce->rx_coalesce_usecs = tp->coalesce;
4833
4834         return 0;
4835 }
4836
4837 static int rtl8152_set_coalesce(struct net_device *netdev,
4838                                 struct ethtool_coalesce *coalesce)
4839 {
4840         struct r8152 *tp = netdev_priv(netdev);
4841         int ret;
4842
4843         switch (tp->version) {
4844         case RTL_VER_01:
4845         case RTL_VER_02:
4846         case RTL_VER_07:
4847                 return -EOPNOTSUPP;
4848         default:
4849                 break;
4850         }
4851
4852         if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
4853                 return -EINVAL;
4854
4855         ret = usb_autopm_get_interface(tp->intf);
4856         if (ret < 0)
4857                 return ret;
4858
4859         mutex_lock(&tp->control);
4860
4861         if (tp->coalesce != coalesce->rx_coalesce_usecs) {
4862                 tp->coalesce = coalesce->rx_coalesce_usecs;
4863
4864                 if (netif_running(tp->netdev) && netif_carrier_ok(netdev))
4865                         r8153_set_rx_early_timeout(tp);
4866         }
4867
4868         mutex_unlock(&tp->control);
4869
4870         usb_autopm_put_interface(tp->intf);
4871
4872         return ret;
4873 }
4874
4875 static const struct ethtool_ops ops = {
4876         .get_drvinfo = rtl8152_get_drvinfo,
4877         .get_link = ethtool_op_get_link,
4878         .nway_reset = rtl8152_nway_reset,
4879         .get_msglevel = rtl8152_get_msglevel,
4880         .set_msglevel = rtl8152_set_msglevel,
4881         .get_wol = rtl8152_get_wol,
4882         .set_wol = rtl8152_set_wol,
4883         .get_strings = rtl8152_get_strings,
4884         .get_sset_count = rtl8152_get_sset_count,
4885         .get_ethtool_stats = rtl8152_get_ethtool_stats,
4886         .get_coalesce = rtl8152_get_coalesce,
4887         .set_coalesce = rtl8152_set_coalesce,
4888         .get_eee = rtl_ethtool_get_eee,
4889         .set_eee = rtl_ethtool_set_eee,
4890         .get_link_ksettings = rtl8152_get_link_ksettings,
4891         .set_link_ksettings = rtl8152_set_link_ksettings,
4892 };
4893
4894 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
4895 {
4896         struct r8152 *tp = netdev_priv(netdev);
4897         struct mii_ioctl_data *data = if_mii(rq);
4898         int res;
4899
4900         if (test_bit(RTL8152_UNPLUG, &tp->flags))
4901                 return -ENODEV;
4902
4903         res = usb_autopm_get_interface(tp->intf);
4904         if (res < 0)
4905                 goto out;
4906
4907         switch (cmd) {
4908         case SIOCGMIIPHY:
4909                 data->phy_id = R8152_PHY_ID; /* Internal PHY */
4910                 break;
4911
4912         case SIOCGMIIREG:
4913                 mutex_lock(&tp->control);
4914                 data->val_out = r8152_mdio_read(tp, data->reg_num);
4915                 mutex_unlock(&tp->control);
4916                 break;
4917
4918         case SIOCSMIIREG:
4919                 if (!capable(CAP_NET_ADMIN)) {
4920                         res = -EPERM;
4921                         break;
4922                 }
4923                 mutex_lock(&tp->control);
4924                 r8152_mdio_write(tp, data->reg_num, data->val_in);
4925                 mutex_unlock(&tp->control);
4926                 break;
4927
4928         default:
4929                 res = -EOPNOTSUPP;
4930         }
4931
4932         usb_autopm_put_interface(tp->intf);
4933
4934 out:
4935         return res;
4936 }
4937
4938 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
4939 {
4940         struct r8152 *tp = netdev_priv(dev);
4941         int ret;
4942
4943         switch (tp->version) {
4944         case RTL_VER_01:
4945         case RTL_VER_02:
4946         case RTL_VER_07:
4947                 dev->mtu = new_mtu;
4948                 return 0;
4949         default:
4950                 break;
4951         }
4952
4953         ret = usb_autopm_get_interface(tp->intf);
4954         if (ret < 0)
4955                 return ret;
4956
4957         mutex_lock(&tp->control);
4958
4959         dev->mtu = new_mtu;
4960
4961         if (netif_running(dev)) {
4962                 u32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4963
4964                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms);
4965
4966                 if (netif_carrier_ok(dev))
4967                         r8153_set_rx_early_size(tp);
4968         }
4969
4970         mutex_unlock(&tp->control);
4971
4972         usb_autopm_put_interface(tp->intf);
4973
4974         return ret;
4975 }
4976
4977 static const struct net_device_ops rtl8152_netdev_ops = {
4978         .ndo_open               = rtl8152_open,
4979         .ndo_stop               = rtl8152_close,
4980         .ndo_do_ioctl           = rtl8152_ioctl,
4981         .ndo_start_xmit         = rtl8152_start_xmit,
4982         .ndo_tx_timeout         = rtl8152_tx_timeout,
4983         .ndo_set_features       = rtl8152_set_features,
4984         .ndo_set_rx_mode        = rtl8152_set_rx_mode,
4985         .ndo_set_mac_address    = rtl8152_set_mac_address,
4986         .ndo_change_mtu         = rtl8152_change_mtu,
4987         .ndo_validate_addr      = eth_validate_addr,
4988         .ndo_features_check     = rtl8152_features_check,
4989 };
4990
4991 static void rtl8152_unload(struct r8152 *tp)
4992 {
4993         if (test_bit(RTL8152_UNPLUG, &tp->flags))
4994                 return;
4995
4996         if (tp->version != RTL_VER_01)
4997                 r8152_power_cut_en(tp, true);
4998 }
4999
5000 static void rtl8153_unload(struct r8152 *tp)
5001 {
5002         if (test_bit(RTL8152_UNPLUG, &tp->flags))
5003                 return;
5004
5005         r8153_power_cut_en(tp, false);
5006 }
5007
5008 static void rtl8153b_unload(struct r8152 *tp)
5009 {
5010         if (test_bit(RTL8152_UNPLUG, &tp->flags))
5011                 return;
5012
5013         r8153b_power_cut_en(tp, false);
5014 }
5015
5016 static int rtl_ops_init(struct r8152 *tp)
5017 {
5018         struct rtl_ops *ops = &tp->rtl_ops;
5019         int ret = 0;
5020
5021         switch (tp->version) {
5022         case RTL_VER_01:
5023         case RTL_VER_02:
5024         case RTL_VER_07:
5025                 ops->init               = r8152b_init;
5026                 ops->enable             = rtl8152_enable;
5027                 ops->disable            = rtl8152_disable;
5028                 ops->up                 = rtl8152_up;
5029                 ops->down               = rtl8152_down;
5030                 ops->unload             = rtl8152_unload;
5031                 ops->eee_get            = r8152_get_eee;
5032                 ops->eee_set            = r8152_set_eee;
5033                 ops->in_nway            = rtl8152_in_nway;
5034                 ops->hw_phy_cfg         = r8152b_hw_phy_cfg;
5035                 ops->autosuspend_en     = rtl_runtime_suspend_enable;
5036                 break;
5037
5038         case RTL_VER_03:
5039         case RTL_VER_04:
5040         case RTL_VER_05:
5041         case RTL_VER_06:
5042                 ops->init               = r8153_init;
5043                 ops->enable             = rtl8153_enable;
5044                 ops->disable            = rtl8153_disable;
5045                 ops->up                 = rtl8153_up;
5046                 ops->down               = rtl8153_down;
5047                 ops->unload             = rtl8153_unload;
5048                 ops->eee_get            = r8153_get_eee;
5049                 ops->eee_set            = r8153_set_eee;
5050                 ops->in_nway            = rtl8153_in_nway;
5051                 ops->hw_phy_cfg         = r8153_hw_phy_cfg;
5052                 ops->autosuspend_en     = rtl8153_runtime_enable;
5053                 break;
5054
5055         case RTL_VER_08:
5056         case RTL_VER_09:
5057                 ops->init               = r8153b_init;
5058                 ops->enable             = rtl8153_enable;
5059                 ops->disable            = rtl8153b_disable;
5060                 ops->up                 = rtl8153b_up;
5061                 ops->down               = rtl8153b_down;
5062                 ops->unload             = rtl8153b_unload;
5063                 ops->eee_get            = r8153_get_eee;
5064                 ops->eee_set            = r8153b_set_eee;
5065                 ops->in_nway            = rtl8153_in_nway;
5066                 ops->hw_phy_cfg         = r8153b_hw_phy_cfg;
5067                 ops->autosuspend_en     = rtl8153b_runtime_enable;
5068                 break;
5069
5070         default:
5071                 ret = -ENODEV;
5072                 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
5073                 break;
5074         }
5075
5076         return ret;
5077 }
5078
5079 static u8 rtl_get_version(struct usb_interface *intf)
5080 {
5081         struct usb_device *udev = interface_to_usbdev(intf);
5082         u32 ocp_data = 0;
5083         __le32 *tmp;
5084         u8 version;
5085         int ret;
5086
5087         tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
5088         if (!tmp)
5089                 return 0;
5090
5091         ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
5092                               RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
5093                               PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500);
5094         if (ret > 0)
5095                 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
5096
5097         kfree(tmp);
5098
5099         switch (ocp_data) {
5100         case 0x4c00:
5101                 version = RTL_VER_01;
5102                 break;
5103         case 0x4c10:
5104                 version = RTL_VER_02;
5105                 break;
5106         case 0x5c00:
5107                 version = RTL_VER_03;
5108                 break;
5109         case 0x5c10:
5110                 version = RTL_VER_04;
5111                 break;
5112         case 0x5c20:
5113                 version = RTL_VER_05;
5114                 break;
5115         case 0x5c30:
5116                 version = RTL_VER_06;
5117                 break;
5118         case 0x4800:
5119                 version = RTL_VER_07;
5120                 break;
5121         case 0x6000:
5122                 version = RTL_VER_08;
5123                 break;
5124         case 0x6010:
5125                 version = RTL_VER_09;
5126                 break;
5127         default:
5128                 version = RTL_VER_UNKNOWN;
5129                 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
5130                 break;
5131         }
5132
5133         dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
5134
5135         return version;
5136 }
5137
5138 static int rtl8152_probe(struct usb_interface *intf,
5139                          const struct usb_device_id *id)
5140 {
5141         struct usb_device *udev = interface_to_usbdev(intf);
5142         u8 version = rtl_get_version(intf);
5143         struct r8152 *tp;
5144         struct net_device *netdev;
5145         int ret;
5146
5147         if (version == RTL_VER_UNKNOWN)
5148                 return -ENODEV;
5149
5150         if (udev->actconfig->desc.bConfigurationValue != 1) {
5151                 usb_driver_set_configuration(udev, 1);
5152                 return -ENODEV;
5153         }
5154
5155         usb_reset_device(udev);
5156         netdev = alloc_etherdev(sizeof(struct r8152));
5157         if (!netdev) {
5158                 dev_err(&intf->dev, "Out of memory\n");
5159                 return -ENOMEM;
5160         }
5161
5162         SET_NETDEV_DEV(netdev, &intf->dev);
5163         tp = netdev_priv(netdev);
5164         tp->msg_enable = 0x7FFF;
5165
5166         tp->udev = udev;
5167         tp->netdev = netdev;
5168         tp->intf = intf;
5169         tp->version = version;
5170
5171         switch (version) {
5172         case RTL_VER_01:
5173         case RTL_VER_02:
5174         case RTL_VER_07:
5175                 tp->mii.supports_gmii = 0;
5176                 break;
5177         default:
5178                 tp->mii.supports_gmii = 1;
5179                 break;
5180         }
5181
5182         ret = rtl_ops_init(tp);
5183         if (ret)
5184                 goto out;
5185
5186         mutex_init(&tp->control);
5187         INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
5188         INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
5189
5190         netdev->netdev_ops = &rtl8152_netdev_ops;
5191         netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
5192
5193         netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
5194                             NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
5195                             NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
5196                             NETIF_F_HW_VLAN_CTAG_TX;
5197         netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
5198                               NETIF_F_TSO | NETIF_F_FRAGLIST |
5199                               NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
5200                               NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
5201         netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
5202                                 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
5203                                 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
5204
5205         if (tp->version == RTL_VER_01) {
5206                 netdev->features &= ~NETIF_F_RXCSUM;
5207                 netdev->hw_features &= ~NETIF_F_RXCSUM;
5208         }
5209
5210         netdev->ethtool_ops = &ops;
5211         netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
5212
5213         /* MTU range: 68 - 1500 or 9194 */
5214         netdev->min_mtu = ETH_MIN_MTU;
5215         switch (tp->version) {
5216         case RTL_VER_01:
5217         case RTL_VER_02:
5218                 netdev->max_mtu = ETH_DATA_LEN;
5219                 break;
5220         default:
5221                 netdev->max_mtu = RTL8153_MAX_MTU;
5222                 break;
5223         }
5224
5225         tp->mii.dev = netdev;
5226         tp->mii.mdio_read = read_mii_word;
5227         tp->mii.mdio_write = write_mii_word;
5228         tp->mii.phy_id_mask = 0x3f;
5229         tp->mii.reg_num_mask = 0x1f;
5230         tp->mii.phy_id = R8152_PHY_ID;
5231
5232         tp->autoneg = AUTONEG_ENABLE;
5233         tp->speed = tp->mii.supports_gmii ? SPEED_1000 : SPEED_100;
5234         tp->duplex = DUPLEX_FULL;
5235
5236         intf->needs_remote_wakeup = 1;
5237
5238         tp->rtl_ops.init(tp);
5239         queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
5240         set_ethernet_addr(tp);
5241
5242         usb_set_intfdata(intf, tp);
5243         netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
5244
5245         ret = register_netdev(netdev);
5246         if (ret != 0) {
5247                 netif_err(tp, probe, netdev, "couldn't register the device\n");
5248                 goto out1;
5249         }
5250
5251         if (!rtl_can_wakeup(tp))
5252                 __rtl_set_wol(tp, 0);
5253
5254         tp->saved_wolopts = __rtl_get_wol(tp);
5255         if (tp->saved_wolopts)
5256                 device_set_wakeup_enable(&udev->dev, true);
5257         else
5258                 device_set_wakeup_enable(&udev->dev, false);
5259
5260         netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
5261
5262         return 0;
5263
5264 out1:
5265         netif_napi_del(&tp->napi);
5266         usb_set_intfdata(intf, NULL);
5267 out:
5268         free_netdev(netdev);
5269         return ret;
5270 }
5271
5272 static void rtl8152_disconnect(struct usb_interface *intf)
5273 {
5274         struct r8152 *tp = usb_get_intfdata(intf);
5275
5276         usb_set_intfdata(intf, NULL);
5277         if (tp) {
5278                 struct usb_device *udev = tp->udev;
5279
5280                 if (udev->state == USB_STATE_NOTATTACHED)
5281                         set_bit(RTL8152_UNPLUG, &tp->flags);
5282
5283                 netif_napi_del(&tp->napi);
5284                 unregister_netdev(tp->netdev);
5285                 cancel_delayed_work_sync(&tp->hw_phy_work);
5286                 tp->rtl_ops.unload(tp);
5287                 free_netdev(tp->netdev);
5288         }
5289 }
5290
5291 #define REALTEK_USB_DEVICE(vend, prod)  \
5292         .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
5293                        USB_DEVICE_ID_MATCH_INT_CLASS, \
5294         .idVendor = (vend), \
5295         .idProduct = (prod), \
5296         .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
5297 }, \
5298 { \
5299         .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
5300                        USB_DEVICE_ID_MATCH_DEVICE, \
5301         .idVendor = (vend), \
5302         .idProduct = (prod), \
5303         .bInterfaceClass = USB_CLASS_COMM, \
5304         .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
5305         .bInterfaceProtocol = USB_CDC_PROTO_NONE
5306
5307 /* table of devices that work with this driver */
5308 static const struct usb_device_id rtl8152_table[] = {
5309         {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)},
5310         {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
5311         {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
5312         {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)},
5313         {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)},
5314         {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
5315         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x304f)},
5316         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3062)},
5317         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3069)},
5318         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x7205)},
5319         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x720c)},
5320         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x7214)},
5321         {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)},
5322         {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA,  0x09ff)},
5323         {REALTEK_USB_DEVICE(VENDOR_ID_TPLINK,  0x0601)},
5324         {}
5325 };
5326
5327 MODULE_DEVICE_TABLE(usb, rtl8152_table);
5328
5329 static struct usb_driver rtl8152_driver = {
5330         .name =         MODULENAME,
5331         .id_table =     rtl8152_table,
5332         .probe =        rtl8152_probe,
5333         .disconnect =   rtl8152_disconnect,
5334         .suspend =      rtl8152_suspend,
5335         .resume =       rtl8152_resume,
5336         .reset_resume = rtl8152_reset_resume,
5337         .pre_reset =    rtl8152_pre_reset,
5338         .post_reset =   rtl8152_post_reset,
5339         .supports_autosuspend = 1,
5340         .disable_hub_initiated_lpm = 1,
5341 };
5342
5343 module_usb_driver(rtl8152_driver);
5344
5345 MODULE_AUTHOR(DRIVER_AUTHOR);
5346 MODULE_DESCRIPTION(DRIVER_DESC);
5347 MODULE_LICENSE("GPL");
5348 MODULE_VERSION(DRIVER_VERSION);