60dd1ec1665f992ea9b50551672d4a85a5b6b670
[sfrench/cifs-2.6.git] / drivers / net / usb / r8152.c
1 /*
2  *  Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * version 2 as published by the Free Software Foundation.
7  *
8  */
9
10 #include <linux/signal.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/mii.h>
16 #include <linux/ethtool.h>
17 #include <linux/usb.h>
18 #include <linux/crc32.h>
19 #include <linux/if_vlan.h>
20 #include <linux/uaccess.h>
21 #include <linux/list.h>
22 #include <linux/ip.h>
23 #include <linux/ipv6.h>
24 #include <net/ip6_checksum.h>
25 #include <uapi/linux/mdio.h>
26 #include <linux/mdio.h>
27 #include <linux/usb/cdc.h>
28 #include <linux/suspend.h>
29 #include <linux/acpi.h>
30
31 /* Information for net-next */
32 #define NETNEXT_VERSION         "09"
33
34 /* Information for net */
35 #define NET_VERSION             "9"
36
37 #define DRIVER_VERSION          "v1." NETNEXT_VERSION "." NET_VERSION
38 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
39 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
40 #define MODULENAME "r8152"
41
42 #define R8152_PHY_ID            32
43
44 #define PLA_IDR                 0xc000
45 #define PLA_RCR                 0xc010
46 #define PLA_RMS                 0xc016
47 #define PLA_RXFIFO_CTRL0        0xc0a0
48 #define PLA_RXFIFO_CTRL1        0xc0a4
49 #define PLA_RXFIFO_CTRL2        0xc0a8
50 #define PLA_DMY_REG0            0xc0b0
51 #define PLA_FMC                 0xc0b4
52 #define PLA_CFG_WOL             0xc0b6
53 #define PLA_TEREDO_CFG          0xc0bc
54 #define PLA_TEREDO_WAKE_BASE    0xc0c4
55 #define PLA_MAR                 0xcd00
56 #define PLA_BACKUP              0xd000
57 #define PAL_BDC_CR              0xd1a0
58 #define PLA_TEREDO_TIMER        0xd2cc
59 #define PLA_REALWOW_TIMER       0xd2e8
60 #define PLA_EFUSE_DATA          0xdd00
61 #define PLA_EFUSE_CMD           0xdd02
62 #define PLA_LEDSEL              0xdd90
63 #define PLA_LED_FEATURE         0xdd92
64 #define PLA_PHYAR               0xde00
65 #define PLA_BOOT_CTRL           0xe004
66 #define PLA_GPHY_INTR_IMR       0xe022
67 #define PLA_EEE_CR              0xe040
68 #define PLA_EEEP_CR             0xe080
69 #define PLA_MAC_PWR_CTRL        0xe0c0
70 #define PLA_MAC_PWR_CTRL2       0xe0ca
71 #define PLA_MAC_PWR_CTRL3       0xe0cc
72 #define PLA_MAC_PWR_CTRL4       0xe0ce
73 #define PLA_WDT6_CTRL           0xe428
74 #define PLA_TCR0                0xe610
75 #define PLA_TCR1                0xe612
76 #define PLA_MTPS                0xe615
77 #define PLA_TXFIFO_CTRL         0xe618
78 #define PLA_RSTTALLY            0xe800
79 #define PLA_CR                  0xe813
80 #define PLA_CRWECR              0xe81c
81 #define PLA_CONFIG12            0xe81e  /* CONFIG1, CONFIG2 */
82 #define PLA_CONFIG34            0xe820  /* CONFIG3, CONFIG4 */
83 #define PLA_CONFIG5             0xe822
84 #define PLA_PHY_PWR             0xe84c
85 #define PLA_OOB_CTRL            0xe84f
86 #define PLA_CPCR                0xe854
87 #define PLA_MISC_0              0xe858
88 #define PLA_MISC_1              0xe85a
89 #define PLA_OCP_GPHY_BASE       0xe86c
90 #define PLA_TALLYCNT            0xe890
91 #define PLA_SFF_STS_7           0xe8de
92 #define PLA_PHYSTATUS           0xe908
93 #define PLA_BP_BA               0xfc26
94 #define PLA_BP_0                0xfc28
95 #define PLA_BP_1                0xfc2a
96 #define PLA_BP_2                0xfc2c
97 #define PLA_BP_3                0xfc2e
98 #define PLA_BP_4                0xfc30
99 #define PLA_BP_5                0xfc32
100 #define PLA_BP_6                0xfc34
101 #define PLA_BP_7                0xfc36
102 #define PLA_BP_EN               0xfc38
103
104 #define USB_USB2PHY             0xb41e
105 #define USB_SSPHYLINK2          0xb428
106 #define USB_U2P3_CTRL           0xb460
107 #define USB_CSR_DUMMY1          0xb464
108 #define USB_CSR_DUMMY2          0xb466
109 #define USB_DEV_STAT            0xb808
110 #define USB_CONNECT_TIMER       0xcbf8
111 #define USB_MSC_TIMER           0xcbfc
112 #define USB_BURST_SIZE          0xcfc0
113 #define USB_LPM_CONFIG          0xcfd8
114 #define USB_USB_CTRL            0xd406
115 #define USB_PHY_CTRL            0xd408
116 #define USB_TX_AGG              0xd40a
117 #define USB_RX_BUF_TH           0xd40c
118 #define USB_USB_TIMER           0xd428
119 #define USB_RX_EARLY_TIMEOUT    0xd42c
120 #define USB_RX_EARLY_SIZE       0xd42e
121 #define USB_PM_CTRL_STATUS      0xd432  /* RTL8153A */
122 #define USB_RX_EXTRA_AGGR_TMR   0xd432  /* RTL8153B */
123 #define USB_TX_DMA              0xd434
124 #define USB_UPT_RXDMA_OWN       0xd437
125 #define USB_TOLERANCE           0xd490
126 #define USB_LPM_CTRL            0xd41a
127 #define USB_BMU_RESET           0xd4b0
128 #define USB_U1U2_TIMER          0xd4da
129 #define USB_UPS_CTRL            0xd800
130 #define USB_POWER_CUT           0xd80a
131 #define USB_MISC_0              0xd81a
132 #define USB_MISC_1              0xd81f
133 #define USB_AFE_CTRL2           0xd824
134 #define USB_UPS_CFG             0xd842
135 #define USB_UPS_FLAGS           0xd848
136 #define USB_WDT11_CTRL          0xe43c
137 #define USB_BP_BA               0xfc26
138 #define USB_BP_0                0xfc28
139 #define USB_BP_1                0xfc2a
140 #define USB_BP_2                0xfc2c
141 #define USB_BP_3                0xfc2e
142 #define USB_BP_4                0xfc30
143 #define USB_BP_5                0xfc32
144 #define USB_BP_6                0xfc34
145 #define USB_BP_7                0xfc36
146 #define USB_BP_EN               0xfc38
147 #define USB_BP_8                0xfc38
148 #define USB_BP_9                0xfc3a
149 #define USB_BP_10               0xfc3c
150 #define USB_BP_11               0xfc3e
151 #define USB_BP_12               0xfc40
152 #define USB_BP_13               0xfc42
153 #define USB_BP_14               0xfc44
154 #define USB_BP_15               0xfc46
155 #define USB_BP2_EN              0xfc48
156
157 /* OCP Registers */
158 #define OCP_ALDPS_CONFIG        0x2010
159 #define OCP_EEE_CONFIG1         0x2080
160 #define OCP_EEE_CONFIG2         0x2092
161 #define OCP_EEE_CONFIG3         0x2094
162 #define OCP_BASE_MII            0xa400
163 #define OCP_EEE_AR              0xa41a
164 #define OCP_EEE_DATA            0xa41c
165 #define OCP_PHY_STATUS          0xa420
166 #define OCP_NCTL_CFG            0xa42c
167 #define OCP_POWER_CFG           0xa430
168 #define OCP_EEE_CFG             0xa432
169 #define OCP_SRAM_ADDR           0xa436
170 #define OCP_SRAM_DATA           0xa438
171 #define OCP_DOWN_SPEED          0xa442
172 #define OCP_EEE_ABLE            0xa5c4
173 #define OCP_EEE_ADV             0xa5d0
174 #define OCP_EEE_LPABLE          0xa5d2
175 #define OCP_PHY_STATE           0xa708          /* nway state for 8153 */
176 #define OCP_PHY_PATCH_STAT      0xb800
177 #define OCP_PHY_PATCH_CMD       0xb820
178 #define OCP_ADC_IOFFSET         0xbcfc
179 #define OCP_ADC_CFG             0xbc06
180 #define OCP_SYSCLK_CFG          0xc416
181
182 /* SRAM Register */
183 #define SRAM_GREEN_CFG          0x8011
184 #define SRAM_LPF_CFG            0x8012
185 #define SRAM_10M_AMP1           0x8080
186 #define SRAM_10M_AMP2           0x8082
187 #define SRAM_IMPEDANCE          0x8084
188
189 /* PLA_RCR */
190 #define RCR_AAP                 0x00000001
191 #define RCR_APM                 0x00000002
192 #define RCR_AM                  0x00000004
193 #define RCR_AB                  0x00000008
194 #define RCR_ACPT_ALL            (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
195
196 /* PLA_RXFIFO_CTRL0 */
197 #define RXFIFO_THR1_NORMAL      0x00080002
198 #define RXFIFO_THR1_OOB         0x01800003
199
200 /* PLA_RXFIFO_CTRL1 */
201 #define RXFIFO_THR2_FULL        0x00000060
202 #define RXFIFO_THR2_HIGH        0x00000038
203 #define RXFIFO_THR2_OOB         0x0000004a
204 #define RXFIFO_THR2_NORMAL      0x00a0
205
206 /* PLA_RXFIFO_CTRL2 */
207 #define RXFIFO_THR3_FULL        0x00000078
208 #define RXFIFO_THR3_HIGH        0x00000048
209 #define RXFIFO_THR3_OOB         0x0000005a
210 #define RXFIFO_THR3_NORMAL      0x0110
211
212 /* PLA_TXFIFO_CTRL */
213 #define TXFIFO_THR_NORMAL       0x00400008
214 #define TXFIFO_THR_NORMAL2      0x01000008
215
216 /* PLA_DMY_REG0 */
217 #define ECM_ALDPS               0x0002
218
219 /* PLA_FMC */
220 #define FMC_FCR_MCU_EN          0x0001
221
222 /* PLA_EEEP_CR */
223 #define EEEP_CR_EEEP_TX         0x0002
224
225 /* PLA_WDT6_CTRL */
226 #define WDT6_SET_MODE           0x0010
227
228 /* PLA_TCR0 */
229 #define TCR0_TX_EMPTY           0x0800
230 #define TCR0_AUTO_FIFO          0x0080
231
232 /* PLA_TCR1 */
233 #define VERSION_MASK            0x7cf0
234
235 /* PLA_MTPS */
236 #define MTPS_JUMBO              (12 * 1024 / 64)
237 #define MTPS_DEFAULT            (6 * 1024 / 64)
238
239 /* PLA_RSTTALLY */
240 #define TALLY_RESET             0x0001
241
242 /* PLA_CR */
243 #define CR_RST                  0x10
244 #define CR_RE                   0x08
245 #define CR_TE                   0x04
246
247 /* PLA_CRWECR */
248 #define CRWECR_NORAML           0x00
249 #define CRWECR_CONFIG           0xc0
250
251 /* PLA_OOB_CTRL */
252 #define NOW_IS_OOB              0x80
253 #define TXFIFO_EMPTY            0x20
254 #define RXFIFO_EMPTY            0x10
255 #define LINK_LIST_READY         0x02
256 #define DIS_MCU_CLROOB          0x01
257 #define FIFO_EMPTY              (TXFIFO_EMPTY | RXFIFO_EMPTY)
258
259 /* PLA_MISC_1 */
260 #define RXDY_GATED_EN           0x0008
261
262 /* PLA_SFF_STS_7 */
263 #define RE_INIT_LL              0x8000
264 #define MCU_BORW_EN             0x4000
265
266 /* PLA_CPCR */
267 #define CPCR_RX_VLAN            0x0040
268
269 /* PLA_CFG_WOL */
270 #define MAGIC_EN                0x0001
271
272 /* PLA_TEREDO_CFG */
273 #define TEREDO_SEL              0x8000
274 #define TEREDO_WAKE_MASK        0x7f00
275 #define TEREDO_RS_EVENT_MASK    0x00fe
276 #define OOB_TEREDO_EN           0x0001
277
278 /* PAL_BDC_CR */
279 #define ALDPS_PROXY_MODE        0x0001
280
281 /* PLA_EFUSE_CMD */
282 #define EFUSE_READ_CMD          BIT(15)
283 #define EFUSE_DATA_BIT16        BIT(7)
284
285 /* PLA_CONFIG34 */
286 #define LINK_ON_WAKE_EN         0x0010
287 #define LINK_OFF_WAKE_EN        0x0008
288
289 /* PLA_CONFIG5 */
290 #define BWF_EN                  0x0040
291 #define MWF_EN                  0x0020
292 #define UWF_EN                  0x0010
293 #define LAN_WAKE_EN             0x0002
294
295 /* PLA_LED_FEATURE */
296 #define LED_MODE_MASK           0x0700
297
298 /* PLA_PHY_PWR */
299 #define TX_10M_IDLE_EN          0x0080
300 #define PFM_PWM_SWITCH          0x0040
301
302 /* PLA_MAC_PWR_CTRL */
303 #define D3_CLK_GATED_EN         0x00004000
304 #define MCU_CLK_RATIO           0x07010f07
305 #define MCU_CLK_RATIO_MASK      0x0f0f0f0f
306 #define ALDPS_SPDWN_RATIO       0x0f87
307
308 /* PLA_MAC_PWR_CTRL2 */
309 #define EEE_SPDWN_RATIO         0x8007
310 #define MAC_CLK_SPDWN_EN        BIT(15)
311
312 /* PLA_MAC_PWR_CTRL3 */
313 #define PKT_AVAIL_SPDWN_EN      0x0100
314 #define SUSPEND_SPDWN_EN        0x0004
315 #define U1U2_SPDWN_EN           0x0002
316 #define L1_SPDWN_EN             0x0001
317
318 /* PLA_MAC_PWR_CTRL4 */
319 #define PWRSAVE_SPDWN_EN        0x1000
320 #define RXDV_SPDWN_EN           0x0800
321 #define TX10MIDLE_EN            0x0100
322 #define TP100_SPDWN_EN          0x0020
323 #define TP500_SPDWN_EN          0x0010
324 #define TP1000_SPDWN_EN         0x0008
325 #define EEE_SPDWN_EN            0x0001
326
327 /* PLA_GPHY_INTR_IMR */
328 #define GPHY_STS_MSK            0x0001
329 #define SPEED_DOWN_MSK          0x0002
330 #define SPDWN_RXDV_MSK          0x0004
331 #define SPDWN_LINKCHG_MSK       0x0008
332
333 /* PLA_PHYAR */
334 #define PHYAR_FLAG              0x80000000
335
336 /* PLA_EEE_CR */
337 #define EEE_RX_EN               0x0001
338 #define EEE_TX_EN               0x0002
339
340 /* PLA_BOOT_CTRL */
341 #define AUTOLOAD_DONE           0x0002
342
343 /* USB_USB2PHY */
344 #define USB2PHY_SUSPEND         0x0001
345 #define USB2PHY_L1              0x0002
346
347 /* USB_SSPHYLINK2 */
348 #define pwd_dn_scale_mask       0x3ffe
349 #define pwd_dn_scale(x)         ((x) << 1)
350
351 /* USB_CSR_DUMMY1 */
352 #define DYNAMIC_BURST           0x0001
353
354 /* USB_CSR_DUMMY2 */
355 #define EP4_FULL_FC             0x0001
356
357 /* USB_DEV_STAT */
358 #define STAT_SPEED_MASK         0x0006
359 #define STAT_SPEED_HIGH         0x0000
360 #define STAT_SPEED_FULL         0x0002
361
362 /* USB_LPM_CONFIG */
363 #define LPM_U1U2_EN             BIT(0)
364
365 /* USB_TX_AGG */
366 #define TX_AGG_MAX_THRESHOLD    0x03
367
368 /* USB_RX_BUF_TH */
369 #define RX_THR_SUPPER           0x0c350180
370 #define RX_THR_HIGH             0x7a120180
371 #define RX_THR_SLOW             0xffff0180
372 #define RX_THR_B                0x00010001
373
374 /* USB_TX_DMA */
375 #define TEST_MODE_DISABLE       0x00000001
376 #define TX_SIZE_ADJUST1         0x00000100
377
378 /* USB_BMU_RESET */
379 #define BMU_RESET_EP_IN         0x01
380 #define BMU_RESET_EP_OUT        0x02
381
382 /* USB_UPT_RXDMA_OWN */
383 #define OWN_UPDATE              BIT(0)
384 #define OWN_CLEAR               BIT(1)
385
386 /* USB_UPS_CTRL */
387 #define POWER_CUT               0x0100
388
389 /* USB_PM_CTRL_STATUS */
390 #define RESUME_INDICATE         0x0001
391
392 /* USB_USB_CTRL */
393 #define RX_AGG_DISABLE          0x0010
394 #define RX_ZERO_EN              0x0080
395
396 /* USB_U2P3_CTRL */
397 #define U2P3_ENABLE             0x0001
398
399 /* USB_POWER_CUT */
400 #define PWR_EN                  0x0001
401 #define PHASE2_EN               0x0008
402 #define UPS_EN                  BIT(4)
403 #define USP_PREWAKE             BIT(5)
404
405 /* USB_MISC_0 */
406 #define PCUT_STATUS             0x0001
407
408 /* USB_RX_EARLY_TIMEOUT */
409 #define COALESCE_SUPER           85000U
410 #define COALESCE_HIGH           250000U
411 #define COALESCE_SLOW           524280U
412
413 /* USB_WDT11_CTRL */
414 #define TIMER11_EN              0x0001
415
416 /* USB_LPM_CTRL */
417 /* bit 4 ~ 5: fifo empty boundary */
418 #define FIFO_EMPTY_1FB          0x30    /* 0x1fb * 64 = 32448 bytes */
419 /* bit 2 ~ 3: LMP timer */
420 #define LPM_TIMER_MASK          0x0c
421 #define LPM_TIMER_500MS         0x04    /* 500 ms */
422 #define LPM_TIMER_500US         0x0c    /* 500 us */
423 #define ROK_EXIT_LPM            0x02
424
425 /* USB_AFE_CTRL2 */
426 #define SEN_VAL_MASK            0xf800
427 #define SEN_VAL_NORMAL          0xa000
428 #define SEL_RXIDLE              0x0100
429
430 /* USB_UPS_CFG */
431 #define SAW_CNT_1MS_MASK        0x0fff
432
433 /* USB_UPS_FLAGS */
434 #define UPS_FLAGS_R_TUNE                BIT(0)
435 #define UPS_FLAGS_EN_10M_CKDIV          BIT(1)
436 #define UPS_FLAGS_250M_CKDIV            BIT(2)
437 #define UPS_FLAGS_EN_ALDPS              BIT(3)
438 #define UPS_FLAGS_CTAP_SHORT_DIS        BIT(4)
439 #define UPS_FLAGS_SPEED_MASK            (0xf << 16)
440 #define ups_flags_speed(x)              ((x) << 16)
441 #define UPS_FLAGS_EN_EEE                BIT(20)
442 #define UPS_FLAGS_EN_500M_EEE           BIT(21)
443 #define UPS_FLAGS_EN_EEE_CKDIV          BIT(22)
444 #define UPS_FLAGS_EEE_PLLOFF_GIGA       BIT(24)
445 #define UPS_FLAGS_EEE_CMOD_LV_EN        BIT(25)
446 #define UPS_FLAGS_EN_GREEN              BIT(26)
447 #define UPS_FLAGS_EN_FLOW_CTR           BIT(27)
448
449 enum spd_duplex {
450         NWAY_10M_HALF = 1,
451         NWAY_10M_FULL,
452         NWAY_100M_HALF,
453         NWAY_100M_FULL,
454         NWAY_1000M_FULL,
455         FORCE_10M_HALF,
456         FORCE_10M_FULL,
457         FORCE_100M_HALF,
458         FORCE_100M_FULL,
459 };
460
461 /* OCP_ALDPS_CONFIG */
462 #define ENPWRSAVE               0x8000
463 #define ENPDNPS                 0x0200
464 #define LINKENA                 0x0100
465 #define DIS_SDSAVE              0x0010
466
467 /* OCP_PHY_STATUS */
468 #define PHY_STAT_MASK           0x0007
469 #define PHY_STAT_EXT_INIT       2
470 #define PHY_STAT_LAN_ON         3
471 #define PHY_STAT_PWRDN          5
472
473 /* OCP_NCTL_CFG */
474 #define PGA_RETURN_EN           BIT(1)
475
476 /* OCP_POWER_CFG */
477 #define EEE_CLKDIV_EN           0x8000
478 #define EN_ALDPS                0x0004
479 #define EN_10M_PLLOFF           0x0001
480
481 /* OCP_EEE_CONFIG1 */
482 #define RG_TXLPI_MSK_HFDUP      0x8000
483 #define RG_MATCLR_EN            0x4000
484 #define EEE_10_CAP              0x2000
485 #define EEE_NWAY_EN             0x1000
486 #define TX_QUIET_EN             0x0200
487 #define RX_QUIET_EN             0x0100
488 #define sd_rise_time_mask       0x0070
489 #define sd_rise_time(x)         (min(x, 7) << 4)        /* bit 4 ~ 6 */
490 #define RG_RXLPI_MSK_HFDUP      0x0008
491 #define SDFALLTIME              0x0007  /* bit 0 ~ 2 */
492
493 /* OCP_EEE_CONFIG2 */
494 #define RG_LPIHYS_NUM           0x7000  /* bit 12 ~ 15 */
495 #define RG_DACQUIET_EN          0x0400
496 #define RG_LDVQUIET_EN          0x0200
497 #define RG_CKRSEL               0x0020
498 #define RG_EEEPRG_EN            0x0010
499
500 /* OCP_EEE_CONFIG3 */
501 #define fast_snr_mask           0xff80
502 #define fast_snr(x)             (min(x, 0x1ff) << 7)    /* bit 7 ~ 15 */
503 #define RG_LFS_SEL              0x0060  /* bit 6 ~ 5 */
504 #define MSK_PH                  0x0006  /* bit 0 ~ 3 */
505
506 /* OCP_EEE_AR */
507 /* bit[15:14] function */
508 #define FUN_ADDR                0x0000
509 #define FUN_DATA                0x4000
510 /* bit[4:0] device addr */
511
512 /* OCP_EEE_CFG */
513 #define CTAP_SHORT_EN           0x0040
514 #define EEE10_EN                0x0010
515
516 /* OCP_DOWN_SPEED */
517 #define EN_EEE_CMODE            BIT(14)
518 #define EN_EEE_1000             BIT(13)
519 #define EN_EEE_100              BIT(12)
520 #define EN_10M_CLKDIV           BIT(11)
521 #define EN_10M_BGOFF            0x0080
522
523 /* OCP_PHY_STATE */
524 #define TXDIS_STATE             0x01
525 #define ABD_STATE               0x02
526
527 /* OCP_PHY_PATCH_STAT */
528 #define PATCH_READY             BIT(6)
529
530 /* OCP_PHY_PATCH_CMD */
531 #define PATCH_REQUEST           BIT(4)
532
533 /* OCP_ADC_CFG */
534 #define CKADSEL_L               0x0100
535 #define ADC_EN                  0x0080
536 #define EN_EMI_L                0x0040
537
538 /* OCP_SYSCLK_CFG */
539 #define clk_div_expo(x)         (min(x, 5) << 8)
540
541 /* SRAM_GREEN_CFG */
542 #define GREEN_ETH_EN            BIT(15)
543 #define R_TUNE_EN               BIT(11)
544
545 /* SRAM_LPF_CFG */
546 #define LPF_AUTO_TUNE           0x8000
547
548 /* SRAM_10M_AMP1 */
549 #define GDAC_IB_UPALL           0x0008
550
551 /* SRAM_10M_AMP2 */
552 #define AMP_DN                  0x0200
553
554 /* SRAM_IMPEDANCE */
555 #define RX_DRIVING_MASK         0x6000
556
557 /* MAC PASSTHRU */
558 #define AD_MASK                 0xfee0
559 #define BND_MASK                0x0004
560 #define EFUSE                   0xcfdb
561 #define PASS_THRU_MASK          0x1
562
563 enum rtl_register_content {
564         _1000bps        = 0x10,
565         _100bps         = 0x08,
566         _10bps          = 0x04,
567         LINK_STATUS     = 0x02,
568         FULL_DUP        = 0x01,
569 };
570
571 #define RTL8152_MAX_TX          4
572 #define RTL8152_MAX_RX          10
573 #define INTBUFSIZE              2
574 #define TX_ALIGN                4
575 #define RX_ALIGN                8
576
577 #define INTR_LINK               0x0004
578
579 #define RTL8152_REQT_READ       0xc0
580 #define RTL8152_REQT_WRITE      0x40
581 #define RTL8152_REQ_GET_REGS    0x05
582 #define RTL8152_REQ_SET_REGS    0x05
583
584 #define BYTE_EN_DWORD           0xff
585 #define BYTE_EN_WORD            0x33
586 #define BYTE_EN_BYTE            0x11
587 #define BYTE_EN_SIX_BYTES       0x3f
588 #define BYTE_EN_START_MASK      0x0f
589 #define BYTE_EN_END_MASK        0xf0
590
591 #define RTL8153_MAX_PACKET      9216 /* 9K */
592 #define RTL8153_MAX_MTU         (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \
593                                  ETH_FCS_LEN)
594 #define RTL8152_RMS             (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
595 #define RTL8153_RMS             RTL8153_MAX_PACKET
596 #define RTL8152_TX_TIMEOUT      (5 * HZ)
597 #define RTL8152_NAPI_WEIGHT     64
598 #define rx_reserved_size(x)     ((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \
599                                  sizeof(struct rx_desc) + RX_ALIGN)
600
601 /* rtl8152 flags */
602 enum rtl8152_flags {
603         RTL8152_UNPLUG = 0,
604         RTL8152_SET_RX_MODE,
605         WORK_ENABLE,
606         RTL8152_LINK_CHG,
607         SELECTIVE_SUSPEND,
608         PHY_RESET,
609         SCHEDULE_NAPI,
610         GREEN_ETHERNET,
611         DELL_TB_RX_AGG_BUG,
612 };
613
614 /* Define these values to match your device */
615 #define VENDOR_ID_REALTEK               0x0bda
616 #define VENDOR_ID_MICROSOFT             0x045e
617 #define VENDOR_ID_SAMSUNG               0x04e8
618 #define VENDOR_ID_LENOVO                0x17ef
619 #define VENDOR_ID_LINKSYS               0x13b1
620 #define VENDOR_ID_NVIDIA                0x0955
621 #define VENDOR_ID_TPLINK                0x2357
622
623 #define MCU_TYPE_PLA                    0x0100
624 #define MCU_TYPE_USB                    0x0000
625
626 struct tally_counter {
627         __le64  tx_packets;
628         __le64  rx_packets;
629         __le64  tx_errors;
630         __le32  rx_errors;
631         __le16  rx_missed;
632         __le16  align_errors;
633         __le32  tx_one_collision;
634         __le32  tx_multi_collision;
635         __le64  rx_unicast;
636         __le64  rx_broadcast;
637         __le32  rx_multicast;
638         __le16  tx_aborted;
639         __le16  tx_underrun;
640 };
641
642 struct rx_desc {
643         __le32 opts1;
644 #define RX_LEN_MASK                     0x7fff
645
646         __le32 opts2;
647 #define RD_UDP_CS                       BIT(23)
648 #define RD_TCP_CS                       BIT(22)
649 #define RD_IPV6_CS                      BIT(20)
650 #define RD_IPV4_CS                      BIT(19)
651
652         __le32 opts3;
653 #define IPF                             BIT(23) /* IP checksum fail */
654 #define UDPF                            BIT(22) /* UDP checksum fail */
655 #define TCPF                            BIT(21) /* TCP checksum fail */
656 #define RX_VLAN_TAG                     BIT(16)
657
658         __le32 opts4;
659         __le32 opts5;
660         __le32 opts6;
661 };
662
663 struct tx_desc {
664         __le32 opts1;
665 #define TX_FS                   BIT(31) /* First segment of a packet */
666 #define TX_LS                   BIT(30) /* Final segment of a packet */
667 #define GTSENDV4                BIT(28)
668 #define GTSENDV6                BIT(27)
669 #define GTTCPHO_SHIFT           18
670 #define GTTCPHO_MAX             0x7fU
671 #define TX_LEN_MAX              0x3ffffU
672
673         __le32 opts2;
674 #define UDP_CS                  BIT(31) /* Calculate UDP/IP checksum */
675 #define TCP_CS                  BIT(30) /* Calculate TCP/IP checksum */
676 #define IPV4_CS                 BIT(29) /* Calculate IPv4 checksum */
677 #define IPV6_CS                 BIT(28) /* Calculate IPv6 checksum */
678 #define MSS_SHIFT               17
679 #define MSS_MAX                 0x7ffU
680 #define TCPHO_SHIFT             17
681 #define TCPHO_MAX               0x7ffU
682 #define TX_VLAN_TAG             BIT(16)
683 };
684
685 struct r8152;
686
687 struct rx_agg {
688         struct list_head list;
689         struct urb *urb;
690         struct r8152 *context;
691         void *buffer;
692         void *head;
693 };
694
695 struct tx_agg {
696         struct list_head list;
697         struct urb *urb;
698         struct r8152 *context;
699         void *buffer;
700         void *head;
701         u32 skb_num;
702         u32 skb_len;
703 };
704
705 struct r8152 {
706         unsigned long flags;
707         struct usb_device *udev;
708         struct napi_struct napi;
709         struct usb_interface *intf;
710         struct net_device *netdev;
711         struct urb *intr_urb;
712         struct tx_agg tx_info[RTL8152_MAX_TX];
713         struct rx_agg rx_info[RTL8152_MAX_RX];
714         struct list_head rx_done, tx_free;
715         struct sk_buff_head tx_queue, rx_queue;
716         spinlock_t rx_lock, tx_lock;
717         struct delayed_work schedule, hw_phy_work;
718         struct mii_if_info mii;
719         struct mutex control;   /* use for hw setting */
720 #ifdef CONFIG_PM_SLEEP
721         struct notifier_block pm_notifier;
722 #endif
723
724         struct rtl_ops {
725                 void (*init)(struct r8152 *);
726                 int (*enable)(struct r8152 *);
727                 void (*disable)(struct r8152 *);
728                 void (*up)(struct r8152 *);
729                 void (*down)(struct r8152 *);
730                 void (*unload)(struct r8152 *);
731                 int (*eee_get)(struct r8152 *, struct ethtool_eee *);
732                 int (*eee_set)(struct r8152 *, struct ethtool_eee *);
733                 bool (*in_nway)(struct r8152 *);
734                 void (*hw_phy_cfg)(struct r8152 *);
735                 void (*autosuspend_en)(struct r8152 *tp, bool enable);
736         } rtl_ops;
737
738         int intr_interval;
739         u32 saved_wolopts;
740         u32 msg_enable;
741         u32 tx_qlen;
742         u32 coalesce;
743         u16 ocp_base;
744         u16 speed;
745         u8 *intr_buff;
746         u8 version;
747         u8 duplex;
748         u8 autoneg;
749 };
750
751 enum rtl_version {
752         RTL_VER_UNKNOWN = 0,
753         RTL_VER_01,
754         RTL_VER_02,
755         RTL_VER_03,
756         RTL_VER_04,
757         RTL_VER_05,
758         RTL_VER_06,
759         RTL_VER_07,
760         RTL_VER_08,
761         RTL_VER_09,
762         RTL_VER_MAX
763 };
764
765 enum tx_csum_stat {
766         TX_CSUM_SUCCESS = 0,
767         TX_CSUM_TSO,
768         TX_CSUM_NONE
769 };
770
771 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
772  * The RTL chips use a 64 element hash table based on the Ethernet CRC.
773  */
774 static const int multicast_filter_limit = 32;
775 static unsigned int agg_buf_sz = 16384;
776
777 #define RTL_LIMITED_TSO_SIZE    (agg_buf_sz - sizeof(struct tx_desc) - \
778                                  VLAN_ETH_HLEN - ETH_FCS_LEN)
779
780 static
781 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
782 {
783         int ret;
784         void *tmp;
785
786         tmp = kmalloc(size, GFP_KERNEL);
787         if (!tmp)
788                 return -ENOMEM;
789
790         ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
791                               RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
792                               value, index, tmp, size, 500);
793
794         memcpy(data, tmp, size);
795         kfree(tmp);
796
797         return ret;
798 }
799
800 static
801 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
802 {
803         int ret;
804         void *tmp;
805
806         tmp = kmemdup(data, size, GFP_KERNEL);
807         if (!tmp)
808                 return -ENOMEM;
809
810         ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
811                               RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
812                               value, index, tmp, size, 500);
813
814         kfree(tmp);
815
816         return ret;
817 }
818
819 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
820                             void *data, u16 type)
821 {
822         u16 limit = 64;
823         int ret = 0;
824
825         if (test_bit(RTL8152_UNPLUG, &tp->flags))
826                 return -ENODEV;
827
828         /* both size and indix must be 4 bytes align */
829         if ((size & 3) || !size || (index & 3) || !data)
830                 return -EPERM;
831
832         if ((u32)index + (u32)size > 0xffff)
833                 return -EPERM;
834
835         while (size) {
836                 if (size > limit) {
837                         ret = get_registers(tp, index, type, limit, data);
838                         if (ret < 0)
839                                 break;
840
841                         index += limit;
842                         data += limit;
843                         size -= limit;
844                 } else {
845                         ret = get_registers(tp, index, type, size, data);
846                         if (ret < 0)
847                                 break;
848
849                         index += size;
850                         data += size;
851                         size = 0;
852                         break;
853                 }
854         }
855
856         if (ret == -ENODEV)
857                 set_bit(RTL8152_UNPLUG, &tp->flags);
858
859         return ret;
860 }
861
862 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
863                              u16 size, void *data, u16 type)
864 {
865         int ret;
866         u16 byteen_start, byteen_end, byen;
867         u16 limit = 512;
868
869         if (test_bit(RTL8152_UNPLUG, &tp->flags))
870                 return -ENODEV;
871
872         /* both size and indix must be 4 bytes align */
873         if ((size & 3) || !size || (index & 3) || !data)
874                 return -EPERM;
875
876         if ((u32)index + (u32)size > 0xffff)
877                 return -EPERM;
878
879         byteen_start = byteen & BYTE_EN_START_MASK;
880         byteen_end = byteen & BYTE_EN_END_MASK;
881
882         byen = byteen_start | (byteen_start << 4);
883         ret = set_registers(tp, index, type | byen, 4, data);
884         if (ret < 0)
885                 goto error1;
886
887         index += 4;
888         data += 4;
889         size -= 4;
890
891         if (size) {
892                 size -= 4;
893
894                 while (size) {
895                         if (size > limit) {
896                                 ret = set_registers(tp, index,
897                                                     type | BYTE_EN_DWORD,
898                                                     limit, data);
899                                 if (ret < 0)
900                                         goto error1;
901
902                                 index += limit;
903                                 data += limit;
904                                 size -= limit;
905                         } else {
906                                 ret = set_registers(tp, index,
907                                                     type | BYTE_EN_DWORD,
908                                                     size, data);
909                                 if (ret < 0)
910                                         goto error1;
911
912                                 index += size;
913                                 data += size;
914                                 size = 0;
915                                 break;
916                         }
917                 }
918
919                 byen = byteen_end | (byteen_end >> 4);
920                 ret = set_registers(tp, index, type | byen, 4, data);
921                 if (ret < 0)
922                         goto error1;
923         }
924
925 error1:
926         if (ret == -ENODEV)
927                 set_bit(RTL8152_UNPLUG, &tp->flags);
928
929         return ret;
930 }
931
932 static inline
933 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
934 {
935         return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
936 }
937
938 static inline
939 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
940 {
941         return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
942 }
943
944 static inline
945 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
946 {
947         return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
948 }
949
950 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
951 {
952         __le32 data;
953
954         generic_ocp_read(tp, index, sizeof(data), &data, type);
955
956         return __le32_to_cpu(data);
957 }
958
959 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
960 {
961         __le32 tmp = __cpu_to_le32(data);
962
963         generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
964 }
965
966 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
967 {
968         u32 data;
969         __le32 tmp;
970         u16 byen = BYTE_EN_WORD;
971         u8 shift = index & 2;
972
973         index &= ~3;
974         byen <<= shift;
975
976         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
977
978         data = __le32_to_cpu(tmp);
979         data >>= (shift * 8);
980         data &= 0xffff;
981
982         return (u16)data;
983 }
984
985 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
986 {
987         u32 mask = 0xffff;
988         __le32 tmp;
989         u16 byen = BYTE_EN_WORD;
990         u8 shift = index & 2;
991
992         data &= mask;
993
994         if (index & 2) {
995                 byen <<= shift;
996                 mask <<= (shift * 8);
997                 data <<= (shift * 8);
998                 index &= ~3;
999         }
1000
1001         tmp = __cpu_to_le32(data);
1002
1003         generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1004 }
1005
1006 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
1007 {
1008         u32 data;
1009         __le32 tmp;
1010         u8 shift = index & 3;
1011
1012         index &= ~3;
1013
1014         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
1015
1016         data = __le32_to_cpu(tmp);
1017         data >>= (shift * 8);
1018         data &= 0xff;
1019
1020         return (u8)data;
1021 }
1022
1023 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
1024 {
1025         u32 mask = 0xff;
1026         __le32 tmp;
1027         u16 byen = BYTE_EN_BYTE;
1028         u8 shift = index & 3;
1029
1030         data &= mask;
1031
1032         if (index & 3) {
1033                 byen <<= shift;
1034                 mask <<= (shift * 8);
1035                 data <<= (shift * 8);
1036                 index &= ~3;
1037         }
1038
1039         tmp = __cpu_to_le32(data);
1040
1041         generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1042 }
1043
1044 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
1045 {
1046         u16 ocp_base, ocp_index;
1047
1048         ocp_base = addr & 0xf000;
1049         if (ocp_base != tp->ocp_base) {
1050                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1051                 tp->ocp_base = ocp_base;
1052         }
1053
1054         ocp_index = (addr & 0x0fff) | 0xb000;
1055         return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
1056 }
1057
1058 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
1059 {
1060         u16 ocp_base, ocp_index;
1061
1062         ocp_base = addr & 0xf000;
1063         if (ocp_base != tp->ocp_base) {
1064                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1065                 tp->ocp_base = ocp_base;
1066         }
1067
1068         ocp_index = (addr & 0x0fff) | 0xb000;
1069         ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
1070 }
1071
1072 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
1073 {
1074         ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
1075 }
1076
1077 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
1078 {
1079         return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
1080 }
1081
1082 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
1083 {
1084         ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1085         ocp_reg_write(tp, OCP_SRAM_DATA, data);
1086 }
1087
1088 static u16 sram_read(struct r8152 *tp, u16 addr)
1089 {
1090         ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1091         return ocp_reg_read(tp, OCP_SRAM_DATA);
1092 }
1093
1094 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
1095 {
1096         struct r8152 *tp = netdev_priv(netdev);
1097         int ret;
1098
1099         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1100                 return -ENODEV;
1101
1102         if (phy_id != R8152_PHY_ID)
1103                 return -EINVAL;
1104
1105         ret = r8152_mdio_read(tp, reg);
1106
1107         return ret;
1108 }
1109
1110 static
1111 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1112 {
1113         struct r8152 *tp = netdev_priv(netdev);
1114
1115         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1116                 return;
1117
1118         if (phy_id != R8152_PHY_ID)
1119                 return;
1120
1121         r8152_mdio_write(tp, reg, val);
1122 }
1123
1124 static int
1125 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1126
1127 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1128 {
1129         struct r8152 *tp = netdev_priv(netdev);
1130         struct sockaddr *addr = p;
1131         int ret = -EADDRNOTAVAIL;
1132
1133         if (!is_valid_ether_addr(addr->sa_data))
1134                 goto out1;
1135
1136         ret = usb_autopm_get_interface(tp->intf);
1137         if (ret < 0)
1138                 goto out1;
1139
1140         mutex_lock(&tp->control);
1141
1142         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1143
1144         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1145         pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1146         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1147
1148         mutex_unlock(&tp->control);
1149
1150         usb_autopm_put_interface(tp->intf);
1151 out1:
1152         return ret;
1153 }
1154
1155 /* Devices containing proper chips can support a persistent
1156  * host system provided MAC address.
1157  * Examples of this are Dell TB15 and Dell WD15 docks
1158  */
1159 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1160 {
1161         acpi_status status;
1162         struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1163         union acpi_object *obj;
1164         int ret = -EINVAL;
1165         u32 ocp_data;
1166         unsigned char buf[6];
1167
1168         /* test for -AD variant of RTL8153 */
1169         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1170         if ((ocp_data & AD_MASK) == 0x1000) {
1171                 /* test for MAC address pass-through bit */
1172                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1173                 if ((ocp_data & PASS_THRU_MASK) != 1) {
1174                         netif_dbg(tp, probe, tp->netdev,
1175                                   "No efuse for RTL8153-AD MAC pass through\n");
1176                         return -ENODEV;
1177                 }
1178         } else {
1179                 /* test for RTL8153-BND */
1180                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
1181                 if ((ocp_data & BND_MASK) == 0) {
1182                         netif_dbg(tp, probe, tp->netdev,
1183                                   "Invalid variant for MAC pass through\n");
1184                         return -ENODEV;
1185                 }
1186         }
1187
1188         /* returns _AUXMAC_#AABBCCDDEEFF# */
1189         status = acpi_evaluate_object(NULL, "\\_SB.AMAC", NULL, &buffer);
1190         obj = (union acpi_object *)buffer.pointer;
1191         if (!ACPI_SUCCESS(status))
1192                 return -ENODEV;
1193         if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) {
1194                 netif_warn(tp, probe, tp->netdev,
1195                            "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1196                            obj->type, obj->string.length);
1197                 goto amacout;
1198         }
1199         if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1200             strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1201                 netif_warn(tp, probe, tp->netdev,
1202                            "Invalid header when reading pass-thru MAC addr\n");
1203                 goto amacout;
1204         }
1205         ret = hex2bin(buf, obj->string.pointer + 9, 6);
1206         if (!(ret == 0 && is_valid_ether_addr(buf))) {
1207                 netif_warn(tp, probe, tp->netdev,
1208                            "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1209                            ret, buf);
1210                 ret = -EINVAL;
1211                 goto amacout;
1212         }
1213         memcpy(sa->sa_data, buf, 6);
1214         ether_addr_copy(tp->netdev->dev_addr, sa->sa_data);
1215         netif_info(tp, probe, tp->netdev,
1216                    "Using pass-thru MAC addr %pM\n", sa->sa_data);
1217
1218 amacout:
1219         kfree(obj);
1220         return ret;
1221 }
1222
1223 static int set_ethernet_addr(struct r8152 *tp)
1224 {
1225         struct net_device *dev = tp->netdev;
1226         struct sockaddr sa;
1227         int ret;
1228
1229         if (tp->version == RTL_VER_01) {
1230                 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
1231         } else {
1232                 /* if device doesn't support MAC pass through this will
1233                  * be expected to be non-zero
1234                  */
1235                 ret = vendor_mac_passthru_addr_read(tp, &sa);
1236                 if (ret < 0)
1237                         ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
1238         }
1239
1240         if (ret < 0) {
1241                 netif_err(tp, probe, dev, "Get ether addr fail\n");
1242         } else if (!is_valid_ether_addr(sa.sa_data)) {
1243                 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1244                           sa.sa_data);
1245                 eth_hw_addr_random(dev);
1246                 ether_addr_copy(sa.sa_data, dev->dev_addr);
1247                 ret = rtl8152_set_mac_address(dev, &sa);
1248                 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1249                            sa.sa_data);
1250         } else {
1251                 if (tp->version == RTL_VER_01)
1252                         ether_addr_copy(dev->dev_addr, sa.sa_data);
1253                 else
1254                         ret = rtl8152_set_mac_address(dev, &sa);
1255         }
1256
1257         return ret;
1258 }
1259
1260 static void read_bulk_callback(struct urb *urb)
1261 {
1262         struct net_device *netdev;
1263         int status = urb->status;
1264         struct rx_agg *agg;
1265         struct r8152 *tp;
1266         unsigned long flags;
1267
1268         agg = urb->context;
1269         if (!agg)
1270                 return;
1271
1272         tp = agg->context;
1273         if (!tp)
1274                 return;
1275
1276         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1277                 return;
1278
1279         if (!test_bit(WORK_ENABLE, &tp->flags))
1280                 return;
1281
1282         netdev = tp->netdev;
1283
1284         /* When link down, the driver would cancel all bulks. */
1285         /* This avoid the re-submitting bulk */
1286         if (!netif_carrier_ok(netdev))
1287                 return;
1288
1289         usb_mark_last_busy(tp->udev);
1290
1291         switch (status) {
1292         case 0:
1293                 if (urb->actual_length < ETH_ZLEN)
1294                         break;
1295
1296                 spin_lock_irqsave(&tp->rx_lock, flags);
1297                 list_add_tail(&agg->list, &tp->rx_done);
1298                 spin_unlock_irqrestore(&tp->rx_lock, flags);
1299                 napi_schedule(&tp->napi);
1300                 return;
1301         case -ESHUTDOWN:
1302                 set_bit(RTL8152_UNPLUG, &tp->flags);
1303                 netif_device_detach(tp->netdev);
1304                 return;
1305         case -ENOENT:
1306                 return; /* the urb is in unlink state */
1307         case -ETIME:
1308                 if (net_ratelimit())
1309                         netdev_warn(netdev, "maybe reset is needed?\n");
1310                 break;
1311         default:
1312                 if (net_ratelimit())
1313                         netdev_warn(netdev, "Rx status %d\n", status);
1314                 break;
1315         }
1316
1317         r8152_submit_rx(tp, agg, GFP_ATOMIC);
1318 }
1319
1320 static void write_bulk_callback(struct urb *urb)
1321 {
1322         struct net_device_stats *stats;
1323         struct net_device *netdev;
1324         struct tx_agg *agg;
1325         struct r8152 *tp;
1326         unsigned long flags;
1327         int status = urb->status;
1328
1329         agg = urb->context;
1330         if (!agg)
1331                 return;
1332
1333         tp = agg->context;
1334         if (!tp)
1335                 return;
1336
1337         netdev = tp->netdev;
1338         stats = &netdev->stats;
1339         if (status) {
1340                 if (net_ratelimit())
1341                         netdev_warn(netdev, "Tx status %d\n", status);
1342                 stats->tx_errors += agg->skb_num;
1343         } else {
1344                 stats->tx_packets += agg->skb_num;
1345                 stats->tx_bytes += agg->skb_len;
1346         }
1347
1348         spin_lock_irqsave(&tp->tx_lock, flags);
1349         list_add_tail(&agg->list, &tp->tx_free);
1350         spin_unlock_irqrestore(&tp->tx_lock, flags);
1351
1352         usb_autopm_put_interface_async(tp->intf);
1353
1354         if (!netif_carrier_ok(netdev))
1355                 return;
1356
1357         if (!test_bit(WORK_ENABLE, &tp->flags))
1358                 return;
1359
1360         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1361                 return;
1362
1363         if (!skb_queue_empty(&tp->tx_queue))
1364                 napi_schedule(&tp->napi);
1365 }
1366
1367 static void intr_callback(struct urb *urb)
1368 {
1369         struct r8152 *tp;
1370         __le16 *d;
1371         int status = urb->status;
1372         int res;
1373
1374         tp = urb->context;
1375         if (!tp)
1376                 return;
1377
1378         if (!test_bit(WORK_ENABLE, &tp->flags))
1379                 return;
1380
1381         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1382                 return;
1383
1384         switch (status) {
1385         case 0:                 /* success */
1386                 break;
1387         case -ECONNRESET:       /* unlink */
1388         case -ESHUTDOWN:
1389                 netif_device_detach(tp->netdev);
1390                 /* fall through */
1391         case -ENOENT:
1392         case -EPROTO:
1393                 netif_info(tp, intr, tp->netdev,
1394                            "Stop submitting intr, status %d\n", status);
1395                 return;
1396         case -EOVERFLOW:
1397                 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1398                 goto resubmit;
1399         /* -EPIPE:  should clear the halt */
1400         default:
1401                 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1402                 goto resubmit;
1403         }
1404
1405         d = urb->transfer_buffer;
1406         if (INTR_LINK & __le16_to_cpu(d[0])) {
1407                 if (!netif_carrier_ok(tp->netdev)) {
1408                         set_bit(RTL8152_LINK_CHG, &tp->flags);
1409                         schedule_delayed_work(&tp->schedule, 0);
1410                 }
1411         } else {
1412                 if (netif_carrier_ok(tp->netdev)) {
1413                         netif_stop_queue(tp->netdev);
1414                         set_bit(RTL8152_LINK_CHG, &tp->flags);
1415                         schedule_delayed_work(&tp->schedule, 0);
1416                 }
1417         }
1418
1419 resubmit:
1420         res = usb_submit_urb(urb, GFP_ATOMIC);
1421         if (res == -ENODEV) {
1422                 set_bit(RTL8152_UNPLUG, &tp->flags);
1423                 netif_device_detach(tp->netdev);
1424         } else if (res) {
1425                 netif_err(tp, intr, tp->netdev,
1426                           "can't resubmit intr, status %d\n", res);
1427         }
1428 }
1429
1430 static inline void *rx_agg_align(void *data)
1431 {
1432         return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1433 }
1434
1435 static inline void *tx_agg_align(void *data)
1436 {
1437         return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1438 }
1439
1440 static void free_all_mem(struct r8152 *tp)
1441 {
1442         int i;
1443
1444         for (i = 0; i < RTL8152_MAX_RX; i++) {
1445                 usb_free_urb(tp->rx_info[i].urb);
1446                 tp->rx_info[i].urb = NULL;
1447
1448                 kfree(tp->rx_info[i].buffer);
1449                 tp->rx_info[i].buffer = NULL;
1450                 tp->rx_info[i].head = NULL;
1451         }
1452
1453         for (i = 0; i < RTL8152_MAX_TX; i++) {
1454                 usb_free_urb(tp->tx_info[i].urb);
1455                 tp->tx_info[i].urb = NULL;
1456
1457                 kfree(tp->tx_info[i].buffer);
1458                 tp->tx_info[i].buffer = NULL;
1459                 tp->tx_info[i].head = NULL;
1460         }
1461
1462         usb_free_urb(tp->intr_urb);
1463         tp->intr_urb = NULL;
1464
1465         kfree(tp->intr_buff);
1466         tp->intr_buff = NULL;
1467 }
1468
1469 static int alloc_all_mem(struct r8152 *tp)
1470 {
1471         struct net_device *netdev = tp->netdev;
1472         struct usb_interface *intf = tp->intf;
1473         struct usb_host_interface *alt = intf->cur_altsetting;
1474         struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1475         struct urb *urb;
1476         int node, i;
1477         u8 *buf;
1478
1479         node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1480
1481         spin_lock_init(&tp->rx_lock);
1482         spin_lock_init(&tp->tx_lock);
1483         INIT_LIST_HEAD(&tp->tx_free);
1484         INIT_LIST_HEAD(&tp->rx_done);
1485         skb_queue_head_init(&tp->tx_queue);
1486         skb_queue_head_init(&tp->rx_queue);
1487
1488         for (i = 0; i < RTL8152_MAX_RX; i++) {
1489                 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1490                 if (!buf)
1491                         goto err1;
1492
1493                 if (buf != rx_agg_align(buf)) {
1494                         kfree(buf);
1495                         buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
1496                                            node);
1497                         if (!buf)
1498                                 goto err1;
1499                 }
1500
1501                 urb = usb_alloc_urb(0, GFP_KERNEL);
1502                 if (!urb) {
1503                         kfree(buf);
1504                         goto err1;
1505                 }
1506
1507                 INIT_LIST_HEAD(&tp->rx_info[i].list);
1508                 tp->rx_info[i].context = tp;
1509                 tp->rx_info[i].urb = urb;
1510                 tp->rx_info[i].buffer = buf;
1511                 tp->rx_info[i].head = rx_agg_align(buf);
1512         }
1513
1514         for (i = 0; i < RTL8152_MAX_TX; i++) {
1515                 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1516                 if (!buf)
1517                         goto err1;
1518
1519                 if (buf != tx_agg_align(buf)) {
1520                         kfree(buf);
1521                         buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1522                                            node);
1523                         if (!buf)
1524                                 goto err1;
1525                 }
1526
1527                 urb = usb_alloc_urb(0, GFP_KERNEL);
1528                 if (!urb) {
1529                         kfree(buf);
1530                         goto err1;
1531                 }
1532
1533                 INIT_LIST_HEAD(&tp->tx_info[i].list);
1534                 tp->tx_info[i].context = tp;
1535                 tp->tx_info[i].urb = urb;
1536                 tp->tx_info[i].buffer = buf;
1537                 tp->tx_info[i].head = tx_agg_align(buf);
1538
1539                 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1540         }
1541
1542         tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1543         if (!tp->intr_urb)
1544                 goto err1;
1545
1546         tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1547         if (!tp->intr_buff)
1548                 goto err1;
1549
1550         tp->intr_interval = (int)ep_intr->desc.bInterval;
1551         usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1552                          tp->intr_buff, INTBUFSIZE, intr_callback,
1553                          tp, tp->intr_interval);
1554
1555         return 0;
1556
1557 err1:
1558         free_all_mem(tp);
1559         return -ENOMEM;
1560 }
1561
1562 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1563 {
1564         struct tx_agg *agg = NULL;
1565         unsigned long flags;
1566
1567         if (list_empty(&tp->tx_free))
1568                 return NULL;
1569
1570         spin_lock_irqsave(&tp->tx_lock, flags);
1571         if (!list_empty(&tp->tx_free)) {
1572                 struct list_head *cursor;
1573
1574                 cursor = tp->tx_free.next;
1575                 list_del_init(cursor);
1576                 agg = list_entry(cursor, struct tx_agg, list);
1577         }
1578         spin_unlock_irqrestore(&tp->tx_lock, flags);
1579
1580         return agg;
1581 }
1582
1583 /* r8152_csum_workaround()
1584  * The hw limites the value the transport offset. When the offset is out of the
1585  * range, calculate the checksum by sw.
1586  */
1587 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1588                                   struct sk_buff_head *list)
1589 {
1590         if (skb_shinfo(skb)->gso_size) {
1591                 netdev_features_t features = tp->netdev->features;
1592                 struct sk_buff_head seg_list;
1593                 struct sk_buff *segs, *nskb;
1594
1595                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1596                 segs = skb_gso_segment(skb, features);
1597                 if (IS_ERR(segs) || !segs)
1598                         goto drop;
1599
1600                 __skb_queue_head_init(&seg_list);
1601
1602                 do {
1603                         nskb = segs;
1604                         segs = segs->next;
1605                         nskb->next = NULL;
1606                         __skb_queue_tail(&seg_list, nskb);
1607                 } while (segs);
1608
1609                 skb_queue_splice(&seg_list, list);
1610                 dev_kfree_skb(skb);
1611         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1612                 if (skb_checksum_help(skb) < 0)
1613                         goto drop;
1614
1615                 __skb_queue_head(list, skb);
1616         } else {
1617                 struct net_device_stats *stats;
1618
1619 drop:
1620                 stats = &tp->netdev->stats;
1621                 stats->tx_dropped++;
1622                 dev_kfree_skb(skb);
1623         }
1624 }
1625
1626 /* msdn_giant_send_check()
1627  * According to the document of microsoft, the TCP Pseudo Header excludes the
1628  * packet length for IPv6 TCP large packets.
1629  */
1630 static int msdn_giant_send_check(struct sk_buff *skb)
1631 {
1632         const struct ipv6hdr *ipv6h;
1633         struct tcphdr *th;
1634         int ret;
1635
1636         ret = skb_cow_head(skb, 0);
1637         if (ret)
1638                 return ret;
1639
1640         ipv6h = ipv6_hdr(skb);
1641         th = tcp_hdr(skb);
1642
1643         th->check = 0;
1644         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1645
1646         return ret;
1647 }
1648
1649 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1650 {
1651         if (skb_vlan_tag_present(skb)) {
1652                 u32 opts2;
1653
1654                 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
1655                 desc->opts2 |= cpu_to_le32(opts2);
1656         }
1657 }
1658
1659 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1660 {
1661         u32 opts2 = le32_to_cpu(desc->opts2);
1662
1663         if (opts2 & RX_VLAN_TAG)
1664                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1665                                        swab16(opts2 & 0xffff));
1666 }
1667
1668 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1669                          struct sk_buff *skb, u32 len, u32 transport_offset)
1670 {
1671         u32 mss = skb_shinfo(skb)->gso_size;
1672         u32 opts1, opts2 = 0;
1673         int ret = TX_CSUM_SUCCESS;
1674
1675         WARN_ON_ONCE(len > TX_LEN_MAX);
1676
1677         opts1 = len | TX_FS | TX_LS;
1678
1679         if (mss) {
1680                 if (transport_offset > GTTCPHO_MAX) {
1681                         netif_warn(tp, tx_err, tp->netdev,
1682                                    "Invalid transport offset 0x%x for TSO\n",
1683                                    transport_offset);
1684                         ret = TX_CSUM_TSO;
1685                         goto unavailable;
1686                 }
1687
1688                 switch (vlan_get_protocol(skb)) {
1689                 case htons(ETH_P_IP):
1690                         opts1 |= GTSENDV4;
1691                         break;
1692
1693                 case htons(ETH_P_IPV6):
1694                         if (msdn_giant_send_check(skb)) {
1695                                 ret = TX_CSUM_TSO;
1696                                 goto unavailable;
1697                         }
1698                         opts1 |= GTSENDV6;
1699                         break;
1700
1701                 default:
1702                         WARN_ON_ONCE(1);
1703                         break;
1704                 }
1705
1706                 opts1 |= transport_offset << GTTCPHO_SHIFT;
1707                 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1708         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1709                 u8 ip_protocol;
1710
1711                 if (transport_offset > TCPHO_MAX) {
1712                         netif_warn(tp, tx_err, tp->netdev,
1713                                    "Invalid transport offset 0x%x\n",
1714                                    transport_offset);
1715                         ret = TX_CSUM_NONE;
1716                         goto unavailable;
1717                 }
1718
1719                 switch (vlan_get_protocol(skb)) {
1720                 case htons(ETH_P_IP):
1721                         opts2 |= IPV4_CS;
1722                         ip_protocol = ip_hdr(skb)->protocol;
1723                         break;
1724
1725                 case htons(ETH_P_IPV6):
1726                         opts2 |= IPV6_CS;
1727                         ip_protocol = ipv6_hdr(skb)->nexthdr;
1728                         break;
1729
1730                 default:
1731                         ip_protocol = IPPROTO_RAW;
1732                         break;
1733                 }
1734
1735                 if (ip_protocol == IPPROTO_TCP)
1736                         opts2 |= TCP_CS;
1737                 else if (ip_protocol == IPPROTO_UDP)
1738                         opts2 |= UDP_CS;
1739                 else
1740                         WARN_ON_ONCE(1);
1741
1742                 opts2 |= transport_offset << TCPHO_SHIFT;
1743         }
1744
1745         desc->opts2 = cpu_to_le32(opts2);
1746         desc->opts1 = cpu_to_le32(opts1);
1747
1748 unavailable:
1749         return ret;
1750 }
1751
1752 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1753 {
1754         struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1755         int remain, ret;
1756         u8 *tx_data;
1757
1758         __skb_queue_head_init(&skb_head);
1759         spin_lock(&tx_queue->lock);
1760         skb_queue_splice_init(tx_queue, &skb_head);
1761         spin_unlock(&tx_queue->lock);
1762
1763         tx_data = agg->head;
1764         agg->skb_num = 0;
1765         agg->skb_len = 0;
1766         remain = agg_buf_sz;
1767
1768         while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
1769                 struct tx_desc *tx_desc;
1770                 struct sk_buff *skb;
1771                 unsigned int len;
1772                 u32 offset;
1773
1774                 skb = __skb_dequeue(&skb_head);
1775                 if (!skb)
1776                         break;
1777
1778                 len = skb->len + sizeof(*tx_desc);
1779
1780                 if (len > remain) {
1781                         __skb_queue_head(&skb_head, skb);
1782                         break;
1783                 }
1784
1785                 tx_data = tx_agg_align(tx_data);
1786                 tx_desc = (struct tx_desc *)tx_data;
1787
1788                 offset = (u32)skb_transport_offset(skb);
1789
1790                 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1791                         r8152_csum_workaround(tp, skb, &skb_head);
1792                         continue;
1793                 }
1794
1795                 rtl_tx_vlan_tag(tx_desc, skb);
1796
1797                 tx_data += sizeof(*tx_desc);
1798
1799                 len = skb->len;
1800                 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1801                         struct net_device_stats *stats = &tp->netdev->stats;
1802
1803                         stats->tx_dropped++;
1804                         dev_kfree_skb_any(skb);
1805                         tx_data -= sizeof(*tx_desc);
1806                         continue;
1807                 }
1808
1809                 tx_data += len;
1810                 agg->skb_len += len;
1811                 agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
1812
1813                 dev_kfree_skb_any(skb);
1814
1815                 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
1816
1817                 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
1818                         break;
1819         }
1820
1821         if (!skb_queue_empty(&skb_head)) {
1822                 spin_lock(&tx_queue->lock);
1823                 skb_queue_splice(&skb_head, tx_queue);
1824                 spin_unlock(&tx_queue->lock);
1825         }
1826
1827         netif_tx_lock(tp->netdev);
1828
1829         if (netif_queue_stopped(tp->netdev) &&
1830             skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1831                 netif_wake_queue(tp->netdev);
1832
1833         netif_tx_unlock(tp->netdev);
1834
1835         ret = usb_autopm_get_interface_async(tp->intf);
1836         if (ret < 0)
1837                 goto out_tx_fill;
1838
1839         usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1840                           agg->head, (int)(tx_data - (u8 *)agg->head),
1841                           (usb_complete_t)write_bulk_callback, agg);
1842
1843         ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
1844         if (ret < 0)
1845                 usb_autopm_put_interface_async(tp->intf);
1846
1847 out_tx_fill:
1848         return ret;
1849 }
1850
1851 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1852 {
1853         u8 checksum = CHECKSUM_NONE;
1854         u32 opts2, opts3;
1855
1856         if (!(tp->netdev->features & NETIF_F_RXCSUM))
1857                 goto return_result;
1858
1859         opts2 = le32_to_cpu(rx_desc->opts2);
1860         opts3 = le32_to_cpu(rx_desc->opts3);
1861
1862         if (opts2 & RD_IPV4_CS) {
1863                 if (opts3 & IPF)
1864                         checksum = CHECKSUM_NONE;
1865                 else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1866                         checksum = CHECKSUM_UNNECESSARY;
1867                 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1868                         checksum = CHECKSUM_UNNECESSARY;
1869         } else if (opts2 & RD_IPV6_CS) {
1870                 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1871                         checksum = CHECKSUM_UNNECESSARY;
1872                 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1873                         checksum = CHECKSUM_UNNECESSARY;
1874         }
1875
1876 return_result:
1877         return checksum;
1878 }
1879
1880 static int rx_bottom(struct r8152 *tp, int budget)
1881 {
1882         unsigned long flags;
1883         struct list_head *cursor, *next, rx_queue;
1884         int ret = 0, work_done = 0;
1885         struct napi_struct *napi = &tp->napi;
1886
1887         if (!skb_queue_empty(&tp->rx_queue)) {
1888                 while (work_done < budget) {
1889                         struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
1890                         struct net_device *netdev = tp->netdev;
1891                         struct net_device_stats *stats = &netdev->stats;
1892                         unsigned int pkt_len;
1893
1894                         if (!skb)
1895                                 break;
1896
1897                         pkt_len = skb->len;
1898                         napi_gro_receive(napi, skb);
1899                         work_done++;
1900                         stats->rx_packets++;
1901                         stats->rx_bytes += pkt_len;
1902                 }
1903         }
1904
1905         if (list_empty(&tp->rx_done))
1906                 goto out1;
1907
1908         INIT_LIST_HEAD(&rx_queue);
1909         spin_lock_irqsave(&tp->rx_lock, flags);
1910         list_splice_init(&tp->rx_done, &rx_queue);
1911         spin_unlock_irqrestore(&tp->rx_lock, flags);
1912
1913         list_for_each_safe(cursor, next, &rx_queue) {
1914                 struct rx_desc *rx_desc;
1915                 struct rx_agg *agg;
1916                 int len_used = 0;
1917                 struct urb *urb;
1918                 u8 *rx_data;
1919
1920                 list_del_init(cursor);
1921
1922                 agg = list_entry(cursor, struct rx_agg, list);
1923                 urb = agg->urb;
1924                 if (urb->actual_length < ETH_ZLEN)
1925                         goto submit;
1926
1927                 rx_desc = agg->head;
1928                 rx_data = agg->head;
1929                 len_used += sizeof(struct rx_desc);
1930
1931                 while (urb->actual_length > len_used) {
1932                         struct net_device *netdev = tp->netdev;
1933                         struct net_device_stats *stats = &netdev->stats;
1934                         unsigned int pkt_len;
1935                         struct sk_buff *skb;
1936
1937                         /* limite the skb numbers for rx_queue */
1938                         if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
1939                                 break;
1940
1941                         pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1942                         if (pkt_len < ETH_ZLEN)
1943                                 break;
1944
1945                         len_used += pkt_len;
1946                         if (urb->actual_length < len_used)
1947                                 break;
1948
1949                         pkt_len -= ETH_FCS_LEN;
1950                         rx_data += sizeof(struct rx_desc);
1951
1952                         skb = napi_alloc_skb(napi, pkt_len);
1953                         if (!skb) {
1954                                 stats->rx_dropped++;
1955                                 goto find_next_rx;
1956                         }
1957
1958                         skb->ip_summed = r8152_rx_csum(tp, rx_desc);
1959                         memcpy(skb->data, rx_data, pkt_len);
1960                         skb_put(skb, pkt_len);
1961                         skb->protocol = eth_type_trans(skb, netdev);
1962                         rtl_rx_vlan_tag(rx_desc, skb);
1963                         if (work_done < budget) {
1964                                 napi_gro_receive(napi, skb);
1965                                 work_done++;
1966                                 stats->rx_packets++;
1967                                 stats->rx_bytes += pkt_len;
1968                         } else {
1969                                 __skb_queue_tail(&tp->rx_queue, skb);
1970                         }
1971
1972 find_next_rx:
1973                         rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN);
1974                         rx_desc = (struct rx_desc *)rx_data;
1975                         len_used = (int)(rx_data - (u8 *)agg->head);
1976                         len_used += sizeof(struct rx_desc);
1977                 }
1978
1979 submit:
1980                 if (!ret) {
1981                         ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1982                 } else {
1983                         urb->actual_length = 0;
1984                         list_add_tail(&agg->list, next);
1985                 }
1986         }
1987
1988         if (!list_empty(&rx_queue)) {
1989                 spin_lock_irqsave(&tp->rx_lock, flags);
1990                 list_splice_tail(&rx_queue, &tp->rx_done);
1991                 spin_unlock_irqrestore(&tp->rx_lock, flags);
1992         }
1993
1994 out1:
1995         return work_done;
1996 }
1997
1998 static void tx_bottom(struct r8152 *tp)
1999 {
2000         int res;
2001
2002         do {
2003                 struct tx_agg *agg;
2004
2005                 if (skb_queue_empty(&tp->tx_queue))
2006                         break;
2007
2008                 agg = r8152_get_tx_agg(tp);
2009                 if (!agg)
2010                         break;
2011
2012                 res = r8152_tx_agg_fill(tp, agg);
2013                 if (res) {
2014                         struct net_device *netdev = tp->netdev;
2015
2016                         if (res == -ENODEV) {
2017                                 set_bit(RTL8152_UNPLUG, &tp->flags);
2018                                 netif_device_detach(netdev);
2019                         } else {
2020                                 struct net_device_stats *stats = &netdev->stats;
2021                                 unsigned long flags;
2022
2023                                 netif_warn(tp, tx_err, netdev,
2024                                            "failed tx_urb %d\n", res);
2025                                 stats->tx_dropped += agg->skb_num;
2026
2027                                 spin_lock_irqsave(&tp->tx_lock, flags);
2028                                 list_add_tail(&agg->list, &tp->tx_free);
2029                                 spin_unlock_irqrestore(&tp->tx_lock, flags);
2030                         }
2031                 }
2032         } while (res == 0);
2033 }
2034
2035 static void bottom_half(struct r8152 *tp)
2036 {
2037         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2038                 return;
2039
2040         if (!test_bit(WORK_ENABLE, &tp->flags))
2041                 return;
2042
2043         /* When link down, the driver would cancel all bulks. */
2044         /* This avoid the re-submitting bulk */
2045         if (!netif_carrier_ok(tp->netdev))
2046                 return;
2047
2048         clear_bit(SCHEDULE_NAPI, &tp->flags);
2049
2050         tx_bottom(tp);
2051 }
2052
2053 static int r8152_poll(struct napi_struct *napi, int budget)
2054 {
2055         struct r8152 *tp = container_of(napi, struct r8152, napi);
2056         int work_done;
2057
2058         work_done = rx_bottom(tp, budget);
2059         bottom_half(tp);
2060
2061         if (work_done < budget) {
2062                 if (!napi_complete_done(napi, work_done))
2063                         goto out;
2064                 if (!list_empty(&tp->rx_done))
2065                         napi_schedule(napi);
2066                 else if (!skb_queue_empty(&tp->tx_queue) &&
2067                          !list_empty(&tp->tx_free))
2068                         napi_schedule(napi);
2069         }
2070
2071 out:
2072         return work_done;
2073 }
2074
2075 static
2076 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
2077 {
2078         int ret;
2079
2080         /* The rx would be stopped, so skip submitting */
2081         if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
2082             !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
2083                 return 0;
2084
2085         usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
2086                           agg->head, agg_buf_sz,
2087                           (usb_complete_t)read_bulk_callback, agg);
2088
2089         ret = usb_submit_urb(agg->urb, mem_flags);
2090         if (ret == -ENODEV) {
2091                 set_bit(RTL8152_UNPLUG, &tp->flags);
2092                 netif_device_detach(tp->netdev);
2093         } else if (ret) {
2094                 struct urb *urb = agg->urb;
2095                 unsigned long flags;
2096
2097                 urb->actual_length = 0;
2098                 spin_lock_irqsave(&tp->rx_lock, flags);
2099                 list_add_tail(&agg->list, &tp->rx_done);
2100                 spin_unlock_irqrestore(&tp->rx_lock, flags);
2101
2102                 netif_err(tp, rx_err, tp->netdev,
2103                           "Couldn't submit rx[%p], ret = %d\n", agg, ret);
2104
2105                 napi_schedule(&tp->napi);
2106         }
2107
2108         return ret;
2109 }
2110
2111 static void rtl_drop_queued_tx(struct r8152 *tp)
2112 {
2113         struct net_device_stats *stats = &tp->netdev->stats;
2114         struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2115         struct sk_buff *skb;
2116
2117         if (skb_queue_empty(tx_queue))
2118                 return;
2119
2120         __skb_queue_head_init(&skb_head);
2121         spin_lock_bh(&tx_queue->lock);
2122         skb_queue_splice_init(tx_queue, &skb_head);
2123         spin_unlock_bh(&tx_queue->lock);
2124
2125         while ((skb = __skb_dequeue(&skb_head))) {
2126                 dev_kfree_skb(skb);
2127                 stats->tx_dropped++;
2128         }
2129 }
2130
2131 static void rtl8152_tx_timeout(struct net_device *netdev)
2132 {
2133         struct r8152 *tp = netdev_priv(netdev);
2134
2135         netif_warn(tp, tx_err, netdev, "Tx timeout\n");
2136
2137         usb_queue_reset_device(tp->intf);
2138 }
2139
2140 static void rtl8152_set_rx_mode(struct net_device *netdev)
2141 {
2142         struct r8152 *tp = netdev_priv(netdev);
2143
2144         if (netif_carrier_ok(netdev)) {
2145                 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2146                 schedule_delayed_work(&tp->schedule, 0);
2147         }
2148 }
2149
2150 static void _rtl8152_set_rx_mode(struct net_device *netdev)
2151 {
2152         struct r8152 *tp = netdev_priv(netdev);
2153         u32 mc_filter[2];       /* Multicast hash filter */
2154         __le32 tmp[2];
2155         u32 ocp_data;
2156
2157         netif_stop_queue(netdev);
2158         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2159         ocp_data &= ~RCR_ACPT_ALL;
2160         ocp_data |= RCR_AB | RCR_APM;
2161
2162         if (netdev->flags & IFF_PROMISC) {
2163                 /* Unconditionally log net taps. */
2164                 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2165                 ocp_data |= RCR_AM | RCR_AAP;
2166                 mc_filter[1] = 0xffffffff;
2167                 mc_filter[0] = 0xffffffff;
2168         } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
2169                    (netdev->flags & IFF_ALLMULTI)) {
2170                 /* Too many to filter perfectly -- accept all multicasts. */
2171                 ocp_data |= RCR_AM;
2172                 mc_filter[1] = 0xffffffff;
2173                 mc_filter[0] = 0xffffffff;
2174         } else {
2175                 struct netdev_hw_addr *ha;
2176
2177                 mc_filter[1] = 0;
2178                 mc_filter[0] = 0;
2179                 netdev_for_each_mc_addr(ha, netdev) {
2180                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2181
2182                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2183                         ocp_data |= RCR_AM;
2184                 }
2185         }
2186
2187         tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2188         tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2189
2190         pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
2191         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2192         netif_wake_queue(netdev);
2193 }
2194
2195 static netdev_features_t
2196 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2197                        netdev_features_t features)
2198 {
2199         u32 mss = skb_shinfo(skb)->gso_size;
2200         int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2201         int offset = skb_transport_offset(skb);
2202
2203         if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
2204                 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2205         else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2206                 features &= ~NETIF_F_GSO_MASK;
2207
2208         return features;
2209 }
2210
2211 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2212                                       struct net_device *netdev)
2213 {
2214         struct r8152 *tp = netdev_priv(netdev);
2215
2216         skb_tx_timestamp(skb);
2217
2218         skb_queue_tail(&tp->tx_queue, skb);
2219
2220         if (!list_empty(&tp->tx_free)) {
2221                 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2222                         set_bit(SCHEDULE_NAPI, &tp->flags);
2223                         schedule_delayed_work(&tp->schedule, 0);
2224                 } else {
2225                         usb_mark_last_busy(tp->udev);
2226                         napi_schedule(&tp->napi);
2227                 }
2228         } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2229                 netif_stop_queue(netdev);
2230         }
2231
2232         return NETDEV_TX_OK;
2233 }
2234
2235 static void r8152b_reset_packet_filter(struct r8152 *tp)
2236 {
2237         u32     ocp_data;
2238
2239         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2240         ocp_data &= ~FMC_FCR_MCU_EN;
2241         ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2242         ocp_data |= FMC_FCR_MCU_EN;
2243         ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2244 }
2245
2246 static void rtl8152_nic_reset(struct r8152 *tp)
2247 {
2248         int     i;
2249
2250         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2251
2252         for (i = 0; i < 1000; i++) {
2253                 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2254                         break;
2255                 usleep_range(100, 400);
2256         }
2257 }
2258
2259 static void set_tx_qlen(struct r8152 *tp)
2260 {
2261         struct net_device *netdev = tp->netdev;
2262
2263         tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN +
2264                                     sizeof(struct tx_desc));
2265 }
2266
2267 static inline u8 rtl8152_get_speed(struct r8152 *tp)
2268 {
2269         return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2270 }
2271
2272 static void rtl_set_eee_plus(struct r8152 *tp)
2273 {
2274         u32 ocp_data;
2275         u8 speed;
2276
2277         speed = rtl8152_get_speed(tp);
2278         if (speed & _10bps) {
2279                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2280                 ocp_data |= EEEP_CR_EEEP_TX;
2281                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2282         } else {
2283                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2284                 ocp_data &= ~EEEP_CR_EEEP_TX;
2285                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2286         }
2287 }
2288
2289 static void rxdy_gated_en(struct r8152 *tp, bool enable)
2290 {
2291         u32 ocp_data;
2292
2293         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2294         if (enable)
2295                 ocp_data |= RXDY_GATED_EN;
2296         else
2297                 ocp_data &= ~RXDY_GATED_EN;
2298         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2299 }
2300
2301 static int rtl_start_rx(struct r8152 *tp)
2302 {
2303         int i, ret = 0;
2304
2305         INIT_LIST_HEAD(&tp->rx_done);
2306         for (i = 0; i < RTL8152_MAX_RX; i++) {
2307                 INIT_LIST_HEAD(&tp->rx_info[i].list);
2308                 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
2309                 if (ret)
2310                         break;
2311         }
2312
2313         if (ret && ++i < RTL8152_MAX_RX) {
2314                 struct list_head rx_queue;
2315                 unsigned long flags;
2316
2317                 INIT_LIST_HEAD(&rx_queue);
2318
2319                 do {
2320                         struct rx_agg *agg = &tp->rx_info[i++];
2321                         struct urb *urb = agg->urb;
2322
2323                         urb->actual_length = 0;
2324                         list_add_tail(&agg->list, &rx_queue);
2325                 } while (i < RTL8152_MAX_RX);
2326
2327                 spin_lock_irqsave(&tp->rx_lock, flags);
2328                 list_splice_tail(&rx_queue, &tp->rx_done);
2329                 spin_unlock_irqrestore(&tp->rx_lock, flags);
2330         }
2331
2332         return ret;
2333 }
2334
2335 static int rtl_stop_rx(struct r8152 *tp)
2336 {
2337         int i;
2338
2339         for (i = 0; i < RTL8152_MAX_RX; i++)
2340                 usb_kill_urb(tp->rx_info[i].urb);
2341
2342         while (!skb_queue_empty(&tp->rx_queue))
2343                 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2344
2345         return 0;
2346 }
2347
2348 static int rtl_enable(struct r8152 *tp)
2349 {
2350         u32 ocp_data;
2351
2352         r8152b_reset_packet_filter(tp);
2353
2354         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2355         ocp_data |= CR_RE | CR_TE;
2356         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2357
2358         rxdy_gated_en(tp, false);
2359
2360         return 0;
2361 }
2362
2363 static int rtl8152_enable(struct r8152 *tp)
2364 {
2365         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2366                 return -ENODEV;
2367
2368         set_tx_qlen(tp);
2369         rtl_set_eee_plus(tp);
2370
2371         return rtl_enable(tp);
2372 }
2373
2374 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
2375 {
2376         ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
2377                        OWN_UPDATE | OWN_CLEAR);
2378 }
2379
2380 static void r8153_set_rx_early_timeout(struct r8152 *tp)
2381 {
2382         u32 ocp_data = tp->coalesce / 8;
2383
2384         switch (tp->version) {
2385         case RTL_VER_03:
2386         case RTL_VER_04:
2387         case RTL_VER_05:
2388         case RTL_VER_06:
2389                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2390                                ocp_data);
2391                 break;
2392
2393         case RTL_VER_08:
2394         case RTL_VER_09:
2395                 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
2396                  * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
2397                  */
2398                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2399                                128 / 8);
2400                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
2401                                ocp_data);
2402                 r8153b_rx_agg_chg_indicate(tp);
2403                 break;
2404
2405         default:
2406                 break;
2407         }
2408 }
2409
2410 static void r8153_set_rx_early_size(struct r8152 *tp)
2411 {
2412         u32 ocp_data = agg_buf_sz - rx_reserved_size(tp->netdev->mtu);
2413
2414         switch (tp->version) {
2415         case RTL_VER_03:
2416         case RTL_VER_04:
2417         case RTL_VER_05:
2418         case RTL_VER_06:
2419                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2420                                ocp_data / 4);
2421                 break;
2422         case RTL_VER_08:
2423         case RTL_VER_09:
2424                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2425                                ocp_data / 8);
2426                 r8153b_rx_agg_chg_indicate(tp);
2427                 break;
2428         default:
2429                 WARN_ON_ONCE(1);
2430                 break;
2431         }
2432 }
2433
2434 static int rtl8153_enable(struct r8152 *tp)
2435 {
2436         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2437                 return -ENODEV;
2438
2439         set_tx_qlen(tp);
2440         rtl_set_eee_plus(tp);
2441         r8153_set_rx_early_timeout(tp);
2442         r8153_set_rx_early_size(tp);
2443
2444         return rtl_enable(tp);
2445 }
2446
2447 static void rtl_disable(struct r8152 *tp)
2448 {
2449         u32 ocp_data;
2450         int i;
2451
2452         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2453                 rtl_drop_queued_tx(tp);
2454                 return;
2455         }
2456
2457         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2458         ocp_data &= ~RCR_ACPT_ALL;
2459         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2460
2461         rtl_drop_queued_tx(tp);
2462
2463         for (i = 0; i < RTL8152_MAX_TX; i++)
2464                 usb_kill_urb(tp->tx_info[i].urb);
2465
2466         rxdy_gated_en(tp, true);
2467
2468         for (i = 0; i < 1000; i++) {
2469                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2470                 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2471                         break;
2472                 usleep_range(1000, 2000);
2473         }
2474
2475         for (i = 0; i < 1000; i++) {
2476                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2477                         break;
2478                 usleep_range(1000, 2000);
2479         }
2480
2481         rtl_stop_rx(tp);
2482
2483         rtl8152_nic_reset(tp);
2484 }
2485
2486 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2487 {
2488         u32 ocp_data;
2489
2490         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2491         if (enable)
2492                 ocp_data |= POWER_CUT;
2493         else
2494                 ocp_data &= ~POWER_CUT;
2495         ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2496
2497         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2498         ocp_data &= ~RESUME_INDICATE;
2499         ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2500 }
2501
2502 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2503 {
2504         u32 ocp_data;
2505
2506         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2507         if (enable)
2508                 ocp_data |= CPCR_RX_VLAN;
2509         else
2510                 ocp_data &= ~CPCR_RX_VLAN;
2511         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2512 }
2513
2514 static int rtl8152_set_features(struct net_device *dev,
2515                                 netdev_features_t features)
2516 {
2517         netdev_features_t changed = features ^ dev->features;
2518         struct r8152 *tp = netdev_priv(dev);
2519         int ret;
2520
2521         ret = usb_autopm_get_interface(tp->intf);
2522         if (ret < 0)
2523                 goto out;
2524
2525         mutex_lock(&tp->control);
2526
2527         if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2528                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2529                         rtl_rx_vlan_en(tp, true);
2530                 else
2531                         rtl_rx_vlan_en(tp, false);
2532         }
2533
2534         mutex_unlock(&tp->control);
2535
2536         usb_autopm_put_interface(tp->intf);
2537
2538 out:
2539         return ret;
2540 }
2541
2542 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2543
2544 static u32 __rtl_get_wol(struct r8152 *tp)
2545 {
2546         u32 ocp_data;
2547         u32 wolopts = 0;
2548
2549         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2550         if (ocp_data & LINK_ON_WAKE_EN)
2551                 wolopts |= WAKE_PHY;
2552
2553         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2554         if (ocp_data & UWF_EN)
2555                 wolopts |= WAKE_UCAST;
2556         if (ocp_data & BWF_EN)
2557                 wolopts |= WAKE_BCAST;
2558         if (ocp_data & MWF_EN)
2559                 wolopts |= WAKE_MCAST;
2560
2561         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2562         if (ocp_data & MAGIC_EN)
2563                 wolopts |= WAKE_MAGIC;
2564
2565         return wolopts;
2566 }
2567
2568 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2569 {
2570         u32 ocp_data;
2571
2572         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2573
2574         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2575         ocp_data &= ~LINK_ON_WAKE_EN;
2576         if (wolopts & WAKE_PHY)
2577                 ocp_data |= LINK_ON_WAKE_EN;
2578         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2579
2580         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2581         ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
2582         if (wolopts & WAKE_UCAST)
2583                 ocp_data |= UWF_EN;
2584         if (wolopts & WAKE_BCAST)
2585                 ocp_data |= BWF_EN;
2586         if (wolopts & WAKE_MCAST)
2587                 ocp_data |= MWF_EN;
2588         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2589
2590         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2591
2592         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2593         ocp_data &= ~MAGIC_EN;
2594         if (wolopts & WAKE_MAGIC)
2595                 ocp_data |= MAGIC_EN;
2596         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2597
2598         if (wolopts & WAKE_ANY)
2599                 device_set_wakeup_enable(&tp->udev->dev, true);
2600         else
2601                 device_set_wakeup_enable(&tp->udev->dev, false);
2602 }
2603
2604 static void r8153_mac_clk_spd(struct r8152 *tp, bool enable)
2605 {
2606         /* MAC clock speed down */
2607         if (enable) {
2608                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL,
2609                                ALDPS_SPDWN_RATIO);
2610                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2,
2611                                EEE_SPDWN_RATIO);
2612                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
2613                                PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
2614                                U1U2_SPDWN_EN | L1_SPDWN_EN);
2615                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
2616                                PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
2617                                TP100_SPDWN_EN | TP500_SPDWN_EN | EEE_SPDWN_EN |
2618                                TP1000_SPDWN_EN);
2619         } else {
2620                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0);
2621                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0);
2622                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);
2623                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);
2624         }
2625 }
2626
2627 static void r8153_u1u2en(struct r8152 *tp, bool enable)
2628 {
2629         u8 u1u2[8];
2630
2631         if (enable)
2632                 memset(u1u2, 0xff, sizeof(u1u2));
2633         else
2634                 memset(u1u2, 0x00, sizeof(u1u2));
2635
2636         usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2637 }
2638
2639 static void r8153b_u1u2en(struct r8152 *tp, bool enable)
2640 {
2641         u32 ocp_data;
2642
2643         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
2644         if (enable)
2645                 ocp_data |= LPM_U1U2_EN;
2646         else
2647                 ocp_data &= ~LPM_U1U2_EN;
2648
2649         ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
2650 }
2651
2652 static void r8153_u2p3en(struct r8152 *tp, bool enable)
2653 {
2654         u32 ocp_data;
2655
2656         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2657         if (enable)
2658                 ocp_data |= U2P3_ENABLE;
2659         else
2660                 ocp_data &= ~U2P3_ENABLE;
2661         ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2662 }
2663
2664 static void r8153b_ups_flags_w1w0(struct r8152 *tp, u32 set, u32 clear)
2665 {
2666         u32 ocp_data;
2667
2668         ocp_data = ocp_read_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS);
2669         ocp_data &= ~clear;
2670         ocp_data |= set;
2671         ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ocp_data);
2672 }
2673
2674 static void r8153b_green_en(struct r8152 *tp, bool enable)
2675 {
2676         u16 data;
2677
2678         if (enable) {
2679                 sram_write(tp, 0x8045, 0);      /* 10M abiq&ldvbias */
2680                 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */
2681                 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */
2682         } else {
2683                 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */
2684                 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */
2685                 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */
2686         }
2687
2688         data = sram_read(tp, SRAM_GREEN_CFG);
2689         data |= GREEN_ETH_EN;
2690         sram_write(tp, SRAM_GREEN_CFG, data);
2691
2692         r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_GREEN, 0);
2693 }
2694
2695 static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
2696 {
2697         u16 data;
2698         int i;
2699
2700         for (i = 0; i < 500; i++) {
2701                 data = ocp_reg_read(tp, OCP_PHY_STATUS);
2702                 data &= PHY_STAT_MASK;
2703                 if (desired) {
2704                         if (data == desired)
2705                                 break;
2706                 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
2707                            data == PHY_STAT_EXT_INIT) {
2708                         break;
2709                 }
2710
2711                 msleep(20);
2712         }
2713
2714         return data;
2715 }
2716
2717 static void r8153b_ups_en(struct r8152 *tp, bool enable)
2718 {
2719         u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
2720
2721         if (enable) {
2722                 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
2723                 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2724
2725                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
2726                 ocp_data |= BIT(0);
2727                 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
2728         } else {
2729                 u16 data;
2730
2731                 ocp_data &= ~(UPS_EN | USP_PREWAKE);
2732                 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2733
2734                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
2735                 ocp_data &= ~BIT(0);
2736                 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
2737
2738                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2739                 ocp_data &= ~PCUT_STATUS;
2740                 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2741
2742                 data = r8153_phy_status(tp, 0);
2743
2744                 switch (data) {
2745                 case PHY_STAT_PWRDN:
2746                 case PHY_STAT_EXT_INIT:
2747                         r8153b_green_en(tp,
2748                                         test_bit(GREEN_ETHERNET, &tp->flags));
2749
2750                         data = r8152_mdio_read(tp, MII_BMCR);
2751                         data &= ~BMCR_PDOWN;
2752                         data |= BMCR_RESET;
2753                         r8152_mdio_write(tp, MII_BMCR, data);
2754
2755                         data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
2756                         /* fall through */
2757
2758                 default:
2759                         if (data != PHY_STAT_LAN_ON)
2760                                 netif_warn(tp, link, tp->netdev,
2761                                            "PHY not ready");
2762                         break;
2763                 }
2764         }
2765 }
2766
2767 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
2768 {
2769         u32 ocp_data;
2770
2771         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2772         if (enable)
2773                 ocp_data |= PWR_EN | PHASE2_EN;
2774         else
2775                 ocp_data &= ~(PWR_EN | PHASE2_EN);
2776         ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2777
2778         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2779         ocp_data &= ~PCUT_STATUS;
2780         ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2781 }
2782
2783 static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
2784 {
2785         u32 ocp_data;
2786
2787         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2788         if (enable)
2789                 ocp_data |= PWR_EN | PHASE2_EN;
2790         else
2791                 ocp_data &= ~PWR_EN;
2792         ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2793
2794         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2795         ocp_data &= ~PCUT_STATUS;
2796         ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2797 }
2798
2799 static void r8153b_queue_wake(struct r8152 *tp, bool enable)
2800 {
2801         u32 ocp_data;
2802
2803         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 0xd38a);
2804         if (enable)
2805                 ocp_data |= BIT(0);
2806         else
2807                 ocp_data &= ~BIT(0);
2808         ocp_write_byte(tp, MCU_TYPE_PLA, 0xd38a, ocp_data);
2809
2810         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 0xd38c);
2811         ocp_data &= ~BIT(0);
2812         ocp_write_byte(tp, MCU_TYPE_PLA, 0xd38c, ocp_data);
2813 }
2814
2815 static bool rtl_can_wakeup(struct r8152 *tp)
2816 {
2817         struct usb_device *udev = tp->udev;
2818
2819         return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
2820 }
2821
2822 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2823 {
2824         if (enable) {
2825                 u32 ocp_data;
2826
2827                 __rtl_set_wol(tp, WAKE_ANY);
2828
2829                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2830
2831                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2832                 ocp_data |= LINK_OFF_WAKE_EN;
2833                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2834
2835                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2836         } else {
2837                 u32 ocp_data;
2838
2839                 __rtl_set_wol(tp, tp->saved_wolopts);
2840
2841                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2842
2843                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2844                 ocp_data &= ~LINK_OFF_WAKE_EN;
2845                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2846
2847                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2848         }
2849 }
2850
2851 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
2852 {
2853         if (enable) {
2854                 r8153_u1u2en(tp, false);
2855                 r8153_u2p3en(tp, false);
2856                 r8153_mac_clk_spd(tp, true);
2857                 rtl_runtime_suspend_enable(tp, true);
2858         } else {
2859                 rtl_runtime_suspend_enable(tp, false);
2860                 r8153_mac_clk_spd(tp, false);
2861
2862                 switch (tp->version) {
2863                 case RTL_VER_03:
2864                 case RTL_VER_04:
2865                         break;
2866                 case RTL_VER_05:
2867                 case RTL_VER_06:
2868                 default:
2869                         r8153_u2p3en(tp, true);
2870                         break;
2871                 }
2872
2873                 r8153_u1u2en(tp, true);
2874         }
2875 }
2876
2877 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
2878 {
2879         if (enable) {
2880                 r8153b_queue_wake(tp, true);
2881                 r8153b_u1u2en(tp, false);
2882                 r8153_u2p3en(tp, false);
2883                 rtl_runtime_suspend_enable(tp, true);
2884                 r8153b_ups_en(tp, true);
2885         } else {
2886                 r8153b_ups_en(tp, false);
2887                 r8153b_queue_wake(tp, false);
2888                 rtl_runtime_suspend_enable(tp, false);
2889                 r8153_u2p3en(tp, true);
2890                 r8153b_u1u2en(tp, true);
2891         }
2892 }
2893
2894 static void r8153_teredo_off(struct r8152 *tp)
2895 {
2896         u32 ocp_data;
2897
2898         switch (tp->version) {
2899         case RTL_VER_01:
2900         case RTL_VER_02:
2901         case RTL_VER_03:
2902         case RTL_VER_04:
2903         case RTL_VER_05:
2904         case RTL_VER_06:
2905         case RTL_VER_07:
2906                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2907                 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
2908                               OOB_TEREDO_EN);
2909                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2910                 break;
2911
2912         case RTL_VER_08:
2913         case RTL_VER_09:
2914                 /* The bit 0 ~ 7 are relative with teredo settings. They are
2915                  * W1C (write 1 to clear), so set all 1 to disable it.
2916                  */
2917                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
2918                 break;
2919
2920         default:
2921                 break;
2922         }
2923
2924         ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2925         ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2926         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2927 }
2928
2929 static void rtl_reset_bmu(struct r8152 *tp)
2930 {
2931         u32 ocp_data;
2932
2933         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
2934         ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
2935         ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2936         ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
2937         ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2938 }
2939
2940 static void r8152_aldps_en(struct r8152 *tp, bool enable)
2941 {
2942         if (enable) {
2943                 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2944                                                     LINKENA | DIS_SDSAVE);
2945         } else {
2946                 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
2947                                                     DIS_SDSAVE);
2948                 msleep(20);
2949         }
2950 }
2951
2952 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
2953 {
2954         ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
2955         ocp_reg_write(tp, OCP_EEE_DATA, reg);
2956         ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
2957 }
2958
2959 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
2960 {
2961         u16 data;
2962
2963         r8152_mmd_indirect(tp, dev, reg);
2964         data = ocp_reg_read(tp, OCP_EEE_DATA);
2965         ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2966
2967         return data;
2968 }
2969
2970 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
2971 {
2972         r8152_mmd_indirect(tp, dev, reg);
2973         ocp_reg_write(tp, OCP_EEE_DATA, data);
2974         ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2975 }
2976
2977 static void r8152_eee_en(struct r8152 *tp, bool enable)
2978 {
2979         u16 config1, config2, config3;
2980         u32 ocp_data;
2981
2982         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
2983         config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
2984         config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
2985         config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
2986
2987         if (enable) {
2988                 ocp_data |= EEE_RX_EN | EEE_TX_EN;
2989                 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
2990                 config1 |= sd_rise_time(1);
2991                 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
2992                 config3 |= fast_snr(42);
2993         } else {
2994                 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
2995                 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
2996                              RX_QUIET_EN);
2997                 config1 |= sd_rise_time(7);
2998                 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
2999                 config3 |= fast_snr(511);
3000         }
3001
3002         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3003         ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
3004         ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
3005         ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
3006 }
3007
3008 static void r8152b_enable_eee(struct r8152 *tp)
3009 {
3010         r8152_eee_en(tp, true);
3011         r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
3012 }
3013
3014 static void r8152b_enable_fc(struct r8152 *tp)
3015 {
3016         u16 anar;
3017
3018         anar = r8152_mdio_read(tp, MII_ADVERTISE);
3019         anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3020         r8152_mdio_write(tp, MII_ADVERTISE, anar);
3021 }
3022
3023 static void rtl8152_disable(struct r8152 *tp)
3024 {
3025         r8152_aldps_en(tp, false);
3026         rtl_disable(tp);
3027         r8152_aldps_en(tp, true);
3028 }
3029
3030 static void r8152b_hw_phy_cfg(struct r8152 *tp)
3031 {
3032         r8152b_enable_eee(tp);
3033         r8152_aldps_en(tp, true);
3034         r8152b_enable_fc(tp);
3035
3036         set_bit(PHY_RESET, &tp->flags);
3037 }
3038
3039 static void r8152b_exit_oob(struct r8152 *tp)
3040 {
3041         u32 ocp_data;
3042         int i;
3043
3044         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3045         ocp_data &= ~RCR_ACPT_ALL;
3046         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3047
3048         rxdy_gated_en(tp, true);
3049         r8153_teredo_off(tp);
3050         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3051         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
3052
3053         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3054         ocp_data &= ~NOW_IS_OOB;
3055         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3056
3057         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3058         ocp_data &= ~MCU_BORW_EN;
3059         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3060
3061         for (i = 0; i < 1000; i++) {
3062                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3063                 if (ocp_data & LINK_LIST_READY)
3064                         break;
3065                 usleep_range(1000, 2000);
3066         }
3067
3068         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3069         ocp_data |= RE_INIT_LL;
3070         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3071
3072         for (i = 0; i < 1000; i++) {
3073                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3074                 if (ocp_data & LINK_LIST_READY)
3075                         break;
3076                 usleep_range(1000, 2000);
3077         }
3078
3079         rtl8152_nic_reset(tp);
3080
3081         /* rx share fifo credit full threshold */
3082         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
3083
3084         if (tp->udev->speed == USB_SPEED_FULL ||
3085             tp->udev->speed == USB_SPEED_LOW) {
3086                 /* rx share fifo credit near full threshold */
3087                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
3088                                 RXFIFO_THR2_FULL);
3089                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
3090                                 RXFIFO_THR3_FULL);
3091         } else {
3092                 /* rx share fifo credit near full threshold */
3093                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
3094                                 RXFIFO_THR2_HIGH);
3095                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
3096                                 RXFIFO_THR3_HIGH);
3097         }
3098
3099         /* TX share fifo free credit full threshold */
3100         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
3101
3102         ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
3103         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
3104         ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
3105                         TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
3106
3107         rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
3108
3109         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
3110
3111         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
3112         ocp_data |= TCR0_AUTO_FIFO;
3113         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
3114 }
3115
3116 static void r8152b_enter_oob(struct r8152 *tp)
3117 {
3118         u32 ocp_data;
3119         int i;
3120
3121         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3122         ocp_data &= ~NOW_IS_OOB;
3123         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3124
3125         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
3126         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
3127         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
3128
3129         rtl_disable(tp);
3130
3131         for (i = 0; i < 1000; i++) {
3132                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3133                 if (ocp_data & LINK_LIST_READY)
3134                         break;
3135                 usleep_range(1000, 2000);
3136         }
3137
3138         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3139         ocp_data |= RE_INIT_LL;
3140         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3141
3142         for (i = 0; i < 1000; i++) {
3143                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3144                 if (ocp_data & LINK_LIST_READY)
3145                         break;
3146                 usleep_range(1000, 2000);
3147         }
3148
3149         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
3150
3151         rtl_rx_vlan_en(tp, true);
3152
3153         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
3154         ocp_data |= ALDPS_PROXY_MODE;
3155         ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
3156
3157         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3158         ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
3159         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3160
3161         rxdy_gated_en(tp, false);
3162
3163         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3164         ocp_data |= RCR_APM | RCR_AM | RCR_AB;
3165         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3166 }
3167
3168 static int r8153_patch_request(struct r8152 *tp, bool request)
3169 {
3170         u16 data;
3171         int i;
3172
3173         data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
3174         if (request)
3175                 data |= PATCH_REQUEST;
3176         else
3177                 data &= ~PATCH_REQUEST;
3178         ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
3179
3180         for (i = 0; request && i < 5000; i++) {
3181                 usleep_range(1000, 2000);
3182                 if (ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)
3183                         break;
3184         }
3185
3186         if (request && !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
3187                 netif_err(tp, drv, tp->netdev, "patch request fail\n");
3188                 r8153_patch_request(tp, false);
3189                 return -ETIME;
3190         } else {
3191                 return 0;
3192         }
3193 }
3194
3195 static void r8153_aldps_en(struct r8152 *tp, bool enable)
3196 {
3197         u16 data;
3198
3199         data = ocp_reg_read(tp, OCP_POWER_CFG);
3200         if (enable) {
3201                 data |= EN_ALDPS;
3202                 ocp_reg_write(tp, OCP_POWER_CFG, data);
3203         } else {
3204                 int i;
3205
3206                 data &= ~EN_ALDPS;
3207                 ocp_reg_write(tp, OCP_POWER_CFG, data);
3208                 for (i = 0; i < 20; i++) {
3209                         usleep_range(1000, 2000);
3210                         if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
3211                                 break;
3212                 }
3213         }
3214 }
3215
3216 static void r8153b_aldps_en(struct r8152 *tp, bool enable)
3217 {
3218         r8153_aldps_en(tp, enable);
3219
3220         if (enable)
3221                 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_ALDPS, 0);
3222         else
3223                 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_ALDPS);
3224 }
3225
3226 static void r8153_eee_en(struct r8152 *tp, bool enable)
3227 {
3228         u32 ocp_data;
3229         u16 config;
3230
3231         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3232         config = ocp_reg_read(tp, OCP_EEE_CFG);
3233
3234         if (enable) {
3235                 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3236                 config |= EEE10_EN;
3237         } else {
3238                 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3239                 config &= ~EEE10_EN;
3240         }
3241
3242         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3243         ocp_reg_write(tp, OCP_EEE_CFG, config);
3244 }
3245
3246 static void r8153b_eee_en(struct r8152 *tp, bool enable)
3247 {
3248         r8153_eee_en(tp, enable);
3249
3250         if (enable)
3251                 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_EEE, 0);
3252         else
3253                 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_EEE);
3254 }
3255
3256 static void r8153b_enable_fc(struct r8152 *tp)
3257 {
3258         r8152b_enable_fc(tp);
3259         r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_FLOW_CTR, 0);
3260 }
3261
3262 static void r8153_hw_phy_cfg(struct r8152 *tp)
3263 {
3264         u32 ocp_data;
3265         u16 data;
3266
3267         /* disable ALDPS before updating the PHY parameters */
3268         r8153_aldps_en(tp, false);
3269
3270         /* disable EEE before updating the PHY parameters */
3271         r8153_eee_en(tp, false);
3272         ocp_reg_write(tp, OCP_EEE_ADV, 0);
3273
3274         if (tp->version == RTL_VER_03) {
3275                 data = ocp_reg_read(tp, OCP_EEE_CFG);
3276                 data &= ~CTAP_SHORT_EN;
3277                 ocp_reg_write(tp, OCP_EEE_CFG, data);
3278         }
3279
3280         data = ocp_reg_read(tp, OCP_POWER_CFG);
3281         data |= EEE_CLKDIV_EN;
3282         ocp_reg_write(tp, OCP_POWER_CFG, data);
3283
3284         data = ocp_reg_read(tp, OCP_DOWN_SPEED);
3285         data |= EN_10M_BGOFF;
3286         ocp_reg_write(tp, OCP_DOWN_SPEED, data);
3287         data = ocp_reg_read(tp, OCP_POWER_CFG);
3288         data |= EN_10M_PLLOFF;
3289         ocp_reg_write(tp, OCP_POWER_CFG, data);
3290         sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
3291
3292         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3293         ocp_data |= PFM_PWM_SWITCH;
3294         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3295
3296         /* Enable LPF corner auto tune */
3297         sram_write(tp, SRAM_LPF_CFG, 0xf70f);
3298
3299         /* Adjust 10M Amplitude */
3300         sram_write(tp, SRAM_10M_AMP1, 0x00af);
3301         sram_write(tp, SRAM_10M_AMP2, 0x0208);
3302
3303         r8153_eee_en(tp, true);
3304         ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
3305
3306         r8153_aldps_en(tp, true);
3307         r8152b_enable_fc(tp);
3308
3309         switch (tp->version) {
3310         case RTL_VER_03:
3311         case RTL_VER_04:
3312                 break;
3313         case RTL_VER_05:
3314         case RTL_VER_06:
3315         default:
3316                 r8153_u2p3en(tp, true);
3317                 break;
3318         }
3319
3320         set_bit(PHY_RESET, &tp->flags);
3321 }
3322
3323 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
3324 {
3325         u32 ocp_data;
3326
3327         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
3328         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
3329         ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9;  /* data of bit16 */
3330         ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
3331
3332         return ocp_data;
3333 }
3334
3335 static void r8153b_hw_phy_cfg(struct r8152 *tp)
3336 {
3337         u32 ocp_data, ups_flags = 0;
3338         u16 data;
3339
3340         /* disable ALDPS before updating the PHY parameters */
3341         r8153b_aldps_en(tp, false);
3342
3343         /* disable EEE before updating the PHY parameters */
3344         r8153b_eee_en(tp, false);
3345         ocp_reg_write(tp, OCP_EEE_ADV, 0);
3346
3347         r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
3348
3349         data = sram_read(tp, SRAM_GREEN_CFG);
3350         data |= R_TUNE_EN;
3351         sram_write(tp, SRAM_GREEN_CFG, data);
3352         data = ocp_reg_read(tp, OCP_NCTL_CFG);
3353         data |= PGA_RETURN_EN;
3354         ocp_reg_write(tp, OCP_NCTL_CFG, data);
3355
3356         /* ADC Bias Calibration:
3357          * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
3358          * bit (bit3) to rebuild the real 16-bit data. Write the data to the
3359          * ADC ioffset.
3360          */
3361         ocp_data = r8152_efuse_read(tp, 0x7d);
3362         data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
3363         if (data != 0xffff)
3364                 ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
3365
3366         /* ups mode tx-link-pulse timing adjustment:
3367          * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
3368          * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
3369          */
3370         ocp_data = ocp_reg_read(tp, 0xc426);
3371         ocp_data &= 0x3fff;
3372         if (ocp_data) {
3373                 u32 swr_cnt_1ms_ini;
3374
3375                 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
3376                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
3377                 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
3378                 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
3379         }
3380
3381         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3382         ocp_data |= PFM_PWM_SWITCH;
3383         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3384
3385         /* Advnace EEE */
3386         if (!r8153_patch_request(tp, true)) {
3387                 data = ocp_reg_read(tp, OCP_POWER_CFG);
3388                 data |= EEE_CLKDIV_EN;
3389                 ocp_reg_write(tp, OCP_POWER_CFG, data);
3390
3391                 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
3392                 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
3393                 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
3394
3395                 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
3396                 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
3397
3398                 ups_flags |= UPS_FLAGS_EN_10M_CKDIV | UPS_FLAGS_250M_CKDIV |
3399                              UPS_FLAGS_EN_EEE_CKDIV | UPS_FLAGS_EEE_CMOD_LV_EN |
3400                              UPS_FLAGS_EEE_PLLOFF_GIGA;
3401
3402                 r8153_patch_request(tp, false);
3403         }
3404
3405         r8153b_ups_flags_w1w0(tp, ups_flags, 0);
3406
3407         r8153b_eee_en(tp, true);
3408         ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
3409
3410         r8153b_aldps_en(tp, true);
3411         r8153b_enable_fc(tp);
3412         r8153_u2p3en(tp, true);
3413
3414         set_bit(PHY_RESET, &tp->flags);
3415 }
3416
3417 static void r8153_first_init(struct r8152 *tp)
3418 {
3419         u32 ocp_data;
3420         int i;
3421
3422         r8153_mac_clk_spd(tp, false);
3423         rxdy_gated_en(tp, true);
3424         r8153_teredo_off(tp);
3425
3426         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3427         ocp_data &= ~RCR_ACPT_ALL;
3428         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3429
3430         rtl8152_nic_reset(tp);
3431         rtl_reset_bmu(tp);
3432
3433         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3434         ocp_data &= ~NOW_IS_OOB;
3435         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3436
3437         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3438         ocp_data &= ~MCU_BORW_EN;
3439         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3440
3441         for (i = 0; i < 1000; i++) {
3442                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3443                 if (ocp_data & LINK_LIST_READY)
3444                         break;
3445                 usleep_range(1000, 2000);
3446         }
3447
3448         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3449         ocp_data |= RE_INIT_LL;
3450         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3451
3452         for (i = 0; i < 1000; i++) {
3453                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3454                 if (ocp_data & LINK_LIST_READY)
3455                         break;
3456                 usleep_range(1000, 2000);
3457         }
3458
3459         rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
3460
3461         ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
3462         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
3463         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
3464
3465         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
3466         ocp_data |= TCR0_AUTO_FIFO;
3467         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
3468
3469         rtl8152_nic_reset(tp);
3470
3471         /* rx share fifo credit full threshold */
3472         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
3473         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
3474         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
3475         /* TX share fifo free credit full threshold */
3476         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
3477 }
3478
3479 static void r8153_enter_oob(struct r8152 *tp)
3480 {
3481         u32 ocp_data;
3482         int i;
3483
3484         r8153_mac_clk_spd(tp, true);
3485
3486         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3487         ocp_data &= ~NOW_IS_OOB;
3488         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3489
3490         rtl_disable(tp);
3491         rtl_reset_bmu(tp);
3492
3493         for (i = 0; i < 1000; i++) {
3494                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3495                 if (ocp_data & LINK_LIST_READY)
3496                         break;
3497                 usleep_range(1000, 2000);
3498         }
3499
3500         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3501         ocp_data |= RE_INIT_LL;
3502         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3503
3504         for (i = 0; i < 1000; i++) {
3505                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3506                 if (ocp_data & LINK_LIST_READY)
3507                         break;
3508                 usleep_range(1000, 2000);
3509         }
3510
3511         ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
3512         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
3513
3514         switch (tp->version) {
3515         case RTL_VER_03:
3516         case RTL_VER_04:
3517         case RTL_VER_05:
3518         case RTL_VER_06:
3519                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
3520                 ocp_data &= ~TEREDO_WAKE_MASK;
3521                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
3522                 break;
3523
3524         case RTL_VER_08:
3525         case RTL_VER_09:
3526                 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
3527                  * type. Set it to zero. bits[7:0] are the W1C bits about
3528                  * the events. Set them to all 1 to clear them.
3529                  */
3530                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
3531                 break;
3532
3533         default:
3534                 break;
3535         }
3536
3537         rtl_rx_vlan_en(tp, true);
3538
3539         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
3540         ocp_data |= ALDPS_PROXY_MODE;
3541         ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
3542
3543         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3544         ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
3545         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3546
3547         rxdy_gated_en(tp, false);
3548
3549         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3550         ocp_data |= RCR_APM | RCR_AM | RCR_AB;
3551         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3552 }
3553
3554 static void rtl8153_disable(struct r8152 *tp)
3555 {
3556         r8153_aldps_en(tp, false);
3557         rtl_disable(tp);
3558         rtl_reset_bmu(tp);
3559         r8153_aldps_en(tp, true);
3560 }
3561
3562 static void rtl8153b_disable(struct r8152 *tp)
3563 {
3564         r8153b_aldps_en(tp, false);
3565         rtl_disable(tp);
3566         rtl_reset_bmu(tp);
3567         r8153b_aldps_en(tp, true);
3568 }
3569
3570 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
3571 {
3572         u16 bmcr, anar, gbcr;
3573         enum spd_duplex speed_duplex;
3574         int ret = 0;
3575
3576         anar = r8152_mdio_read(tp, MII_ADVERTISE);
3577         anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
3578                   ADVERTISE_100HALF | ADVERTISE_100FULL);
3579         if (tp->mii.supports_gmii) {
3580                 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
3581                 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
3582         } else {
3583                 gbcr = 0;
3584         }
3585
3586         if (autoneg == AUTONEG_DISABLE) {
3587                 if (speed == SPEED_10) {
3588                         bmcr = 0;
3589                         anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3590                         speed_duplex = FORCE_10M_HALF;
3591                 } else if (speed == SPEED_100) {
3592                         bmcr = BMCR_SPEED100;
3593                         anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3594                         speed_duplex = FORCE_100M_HALF;
3595                 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
3596                         bmcr = BMCR_SPEED1000;
3597                         gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
3598                         speed_duplex = NWAY_1000M_FULL;
3599                 } else {
3600                         ret = -EINVAL;
3601                         goto out;
3602                 }
3603
3604                 if (duplex == DUPLEX_FULL) {
3605                         bmcr |= BMCR_FULLDPLX;
3606                         if (speed != SPEED_1000)
3607                                 speed_duplex++;
3608                 }
3609         } else {
3610                 if (speed == SPEED_10) {
3611                         if (duplex == DUPLEX_FULL) {
3612                                 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3613                                 speed_duplex = NWAY_10M_FULL;
3614                         } else {
3615                                 anar |= ADVERTISE_10HALF;
3616                                 speed_duplex = NWAY_10M_HALF;
3617                         }
3618                 } else if (speed == SPEED_100) {
3619                         if (duplex == DUPLEX_FULL) {
3620                                 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3621                                 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3622                                 speed_duplex = NWAY_100M_FULL;
3623                         } else {
3624                                 anar |= ADVERTISE_10HALF;
3625                                 anar |= ADVERTISE_100HALF;
3626                                 speed_duplex = NWAY_100M_HALF;
3627                         }
3628                 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
3629                         if (duplex == DUPLEX_FULL) {
3630                                 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3631                                 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3632                                 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
3633                         } else {
3634                                 anar |= ADVERTISE_10HALF;
3635                                 anar |= ADVERTISE_100HALF;
3636                                 gbcr |= ADVERTISE_1000HALF;
3637                         }
3638                         speed_duplex = NWAY_1000M_FULL;
3639                 } else {
3640                         ret = -EINVAL;
3641                         goto out;
3642                 }
3643
3644                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
3645         }
3646
3647         if (test_and_clear_bit(PHY_RESET, &tp->flags))
3648                 bmcr |= BMCR_RESET;
3649
3650         if (tp->mii.supports_gmii)
3651                 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
3652
3653         r8152_mdio_write(tp, MII_ADVERTISE, anar);
3654         r8152_mdio_write(tp, MII_BMCR, bmcr);
3655
3656         switch (tp->version) {
3657         case RTL_VER_08:
3658         case RTL_VER_09:
3659                 r8153b_ups_flags_w1w0(tp, ups_flags_speed(speed_duplex),
3660                                       UPS_FLAGS_SPEED_MASK);
3661                 break;
3662
3663         default:
3664                 break;
3665         }
3666
3667         if (bmcr & BMCR_RESET) {
3668                 int i;
3669
3670                 for (i = 0; i < 50; i++) {
3671                         msleep(20);
3672                         if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
3673                                 break;
3674                 }
3675         }
3676
3677 out:
3678         return ret;
3679 }
3680
3681 static void rtl8152_up(struct r8152 *tp)
3682 {
3683         if (test_bit(RTL8152_UNPLUG, &tp->flags))
3684                 return;
3685
3686         r8152_aldps_en(tp, false);
3687         r8152b_exit_oob(tp);
3688         r8152_aldps_en(tp, true);
3689 }
3690
3691 static void rtl8152_down(struct r8152 *tp)
3692 {
3693         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3694                 rtl_drop_queued_tx(tp);
3695                 return;
3696         }
3697
3698         r8152_power_cut_en(tp, false);
3699         r8152_aldps_en(tp, false);
3700         r8152b_enter_oob(tp);
3701         r8152_aldps_en(tp, true);
3702 }
3703
3704 static void rtl8153_up(struct r8152 *tp)
3705 {
3706         if (test_bit(RTL8152_UNPLUG, &tp->flags))
3707                 return;
3708
3709         r8153_u1u2en(tp, false);
3710         r8153_u2p3en(tp, false);
3711         r8153_aldps_en(tp, false);
3712         r8153_first_init(tp);
3713         r8153_aldps_en(tp, true);
3714
3715         switch (tp->version) {
3716         case RTL_VER_03:
3717         case RTL_VER_04:
3718                 break;
3719         case RTL_VER_05:
3720         case RTL_VER_06:
3721         default:
3722                 r8153_u2p3en(tp, true);
3723                 break;
3724         }
3725
3726         r8153_u1u2en(tp, true);
3727 }
3728
3729 static void rtl8153_down(struct r8152 *tp)
3730 {
3731         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3732                 rtl_drop_queued_tx(tp);
3733                 return;
3734         }
3735
3736         r8153_u1u2en(tp, false);
3737         r8153_u2p3en(tp, false);
3738         r8153_power_cut_en(tp, false);
3739         r8153_aldps_en(tp, false);
3740         r8153_enter_oob(tp);
3741         r8153_aldps_en(tp, true);
3742 }
3743
3744 static void rtl8153b_up(struct r8152 *tp)
3745 {
3746         if (test_bit(RTL8152_UNPLUG, &tp->flags))
3747                 return;
3748
3749         r8153b_u1u2en(tp, false);
3750         r8153_u2p3en(tp, false);
3751         r8153b_aldps_en(tp, false);
3752
3753         r8153_first_init(tp);
3754         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
3755
3756         r8153b_aldps_en(tp, true);
3757         r8153_u2p3en(tp, true);
3758         r8153b_u1u2en(tp, true);
3759 }
3760
3761 static void rtl8153b_down(struct r8152 *tp)
3762 {
3763         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3764                 rtl_drop_queued_tx(tp);
3765                 return;
3766         }
3767
3768         r8153b_u1u2en(tp, false);
3769         r8153_u2p3en(tp, false);
3770         r8153b_power_cut_en(tp, false);
3771         r8153b_aldps_en(tp, false);
3772         r8153_enter_oob(tp);
3773         r8153b_aldps_en(tp, true);
3774 }
3775
3776 static bool rtl8152_in_nway(struct r8152 *tp)
3777 {
3778         u16 nway_state;
3779
3780         ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
3781         tp->ocp_base = 0x2000;
3782         ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c);         /* phy state */
3783         nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
3784
3785         /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
3786         if (nway_state & 0xc000)
3787                 return false;
3788         else
3789                 return true;
3790 }
3791
3792 static bool rtl8153_in_nway(struct r8152 *tp)
3793 {
3794         u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
3795
3796         if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
3797                 return false;
3798         else
3799                 return true;
3800 }
3801
3802 static void set_carrier(struct r8152 *tp)
3803 {
3804         struct net_device *netdev = tp->netdev;
3805         struct napi_struct *napi = &tp->napi;
3806         u8 speed;
3807
3808         speed = rtl8152_get_speed(tp);
3809
3810         if (speed & LINK_STATUS) {
3811                 if (!netif_carrier_ok(netdev)) {
3812                         tp->rtl_ops.enable(tp);
3813                         netif_stop_queue(netdev);
3814                         napi_disable(napi);
3815                         netif_carrier_on(netdev);
3816                         rtl_start_rx(tp);
3817                         clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
3818                         _rtl8152_set_rx_mode(netdev);
3819                         napi_enable(&tp->napi);
3820                         netif_wake_queue(netdev);
3821                         netif_info(tp, link, netdev, "carrier on\n");
3822                 } else if (netif_queue_stopped(netdev) &&
3823                            skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
3824                         netif_wake_queue(netdev);
3825                 }
3826         } else {
3827                 if (netif_carrier_ok(netdev)) {
3828                         netif_carrier_off(netdev);
3829                         napi_disable(napi);
3830                         tp->rtl_ops.disable(tp);
3831                         napi_enable(napi);
3832                         netif_info(tp, link, netdev, "carrier off\n");
3833                 }
3834         }
3835 }
3836
3837 static void rtl_work_func_t(struct work_struct *work)
3838 {
3839         struct r8152 *tp = container_of(work, struct r8152, schedule.work);
3840
3841         /* If the device is unplugged or !netif_running(), the workqueue
3842          * doesn't need to wake the device, and could return directly.
3843          */
3844         if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
3845                 return;
3846
3847         if (usb_autopm_get_interface(tp->intf) < 0)
3848                 return;
3849
3850         if (!test_bit(WORK_ENABLE, &tp->flags))
3851                 goto out1;
3852
3853         if (!mutex_trylock(&tp->control)) {
3854                 schedule_delayed_work(&tp->schedule, 0);
3855                 goto out1;
3856         }
3857
3858         if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
3859                 set_carrier(tp);
3860
3861         if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
3862                 _rtl8152_set_rx_mode(tp->netdev);
3863
3864         /* don't schedule napi before linking */
3865         if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) &&
3866             netif_carrier_ok(tp->netdev))
3867                 napi_schedule(&tp->napi);
3868
3869         mutex_unlock(&tp->control);
3870
3871 out1:
3872         usb_autopm_put_interface(tp->intf);
3873 }
3874
3875 static void rtl_hw_phy_work_func_t(struct work_struct *work)
3876 {
3877         struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
3878
3879         if (test_bit(RTL8152_UNPLUG, &tp->flags))
3880                 return;
3881
3882         if (usb_autopm_get_interface(tp->intf) < 0)
3883                 return;
3884
3885         mutex_lock(&tp->control);
3886
3887         tp->rtl_ops.hw_phy_cfg(tp);
3888
3889         rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex);
3890
3891         mutex_unlock(&tp->control);
3892
3893         usb_autopm_put_interface(tp->intf);
3894 }
3895
3896 #ifdef CONFIG_PM_SLEEP
3897 static int rtl_notifier(struct notifier_block *nb, unsigned long action,
3898                         void *data)
3899 {
3900         struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
3901
3902         switch (action) {
3903         case PM_HIBERNATION_PREPARE:
3904         case PM_SUSPEND_PREPARE:
3905                 usb_autopm_get_interface(tp->intf);
3906                 break;
3907
3908         case PM_POST_HIBERNATION:
3909         case PM_POST_SUSPEND:
3910                 usb_autopm_put_interface(tp->intf);
3911                 break;
3912
3913         case PM_POST_RESTORE:
3914         case PM_RESTORE_PREPARE:
3915         default:
3916                 break;
3917         }
3918
3919         return NOTIFY_DONE;
3920 }
3921 #endif
3922
3923 static int rtl8152_open(struct net_device *netdev)
3924 {
3925         struct r8152 *tp = netdev_priv(netdev);
3926         int res = 0;
3927
3928         res = alloc_all_mem(tp);
3929         if (res)
3930                 goto out;
3931
3932         res = usb_autopm_get_interface(tp->intf);
3933         if (res < 0)
3934                 goto out_free;
3935
3936         mutex_lock(&tp->control);
3937
3938         tp->rtl_ops.up(tp);
3939
3940         netif_carrier_off(netdev);
3941         netif_start_queue(netdev);
3942         set_bit(WORK_ENABLE, &tp->flags);
3943
3944         res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3945         if (res) {
3946                 if (res == -ENODEV)
3947                         netif_device_detach(tp->netdev);
3948                 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
3949                            res);
3950                 goto out_unlock;
3951         }
3952         napi_enable(&tp->napi);
3953
3954         mutex_unlock(&tp->control);
3955
3956         usb_autopm_put_interface(tp->intf);
3957 #ifdef CONFIG_PM_SLEEP
3958         tp->pm_notifier.notifier_call = rtl_notifier;
3959         register_pm_notifier(&tp->pm_notifier);
3960 #endif
3961         return 0;
3962
3963 out_unlock:
3964         mutex_unlock(&tp->control);
3965         usb_autopm_put_interface(tp->intf);
3966 out_free:
3967         free_all_mem(tp);
3968 out:
3969         return res;
3970 }
3971
3972 static int rtl8152_close(struct net_device *netdev)
3973 {
3974         struct r8152 *tp = netdev_priv(netdev);
3975         int res = 0;
3976
3977 #ifdef CONFIG_PM_SLEEP
3978         unregister_pm_notifier(&tp->pm_notifier);
3979 #endif
3980         if (!test_bit(RTL8152_UNPLUG, &tp->flags))
3981                 napi_disable(&tp->napi);
3982         clear_bit(WORK_ENABLE, &tp->flags);
3983         usb_kill_urb(tp->intr_urb);
3984         cancel_delayed_work_sync(&tp->schedule);
3985         netif_stop_queue(netdev);
3986
3987         res = usb_autopm_get_interface(tp->intf);
3988         if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
3989                 rtl_drop_queued_tx(tp);
3990                 rtl_stop_rx(tp);
3991         } else {
3992                 mutex_lock(&tp->control);
3993
3994                 tp->rtl_ops.down(tp);
3995
3996                 mutex_unlock(&tp->control);
3997
3998                 usb_autopm_put_interface(tp->intf);
3999         }
4000
4001         free_all_mem(tp);
4002
4003         return res;
4004 }
4005
4006 static void rtl_tally_reset(struct r8152 *tp)
4007 {
4008         u32 ocp_data;
4009
4010         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
4011         ocp_data |= TALLY_RESET;
4012         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
4013 }
4014
4015 static void r8152b_init(struct r8152 *tp)
4016 {
4017         u32 ocp_data;
4018         u16 data;
4019
4020         if (test_bit(RTL8152_UNPLUG, &tp->flags))
4021                 return;
4022
4023         data = r8152_mdio_read(tp, MII_BMCR);
4024         if (data & BMCR_PDOWN) {
4025                 data &= ~BMCR_PDOWN;
4026                 r8152_mdio_write(tp, MII_BMCR, data);
4027         }
4028
4029         r8152_aldps_en(tp, false);
4030
4031         if (tp->version == RTL_VER_01) {
4032                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
4033                 ocp_data &= ~LED_MODE_MASK;
4034                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
4035         }
4036
4037         r8152_power_cut_en(tp, false);
4038
4039         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
4040         ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
4041         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
4042         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
4043         ocp_data &= ~MCU_CLK_RATIO_MASK;
4044         ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
4045         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
4046         ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
4047                    SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
4048         ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
4049
4050         rtl_tally_reset(tp);
4051
4052         /* enable rx aggregation */
4053         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4054         ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4055         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4056 }
4057
4058 static void r8153_init(struct r8152 *tp)
4059 {
4060         u32 ocp_data;
4061         u16 data;
4062         int i;
4063
4064         if (test_bit(RTL8152_UNPLUG, &tp->flags))
4065                 return;
4066
4067         r8153_u1u2en(tp, false);
4068
4069         for (i = 0; i < 500; i++) {
4070                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
4071                     AUTOLOAD_DONE)
4072                         break;
4073                 msleep(20);
4074         }
4075
4076         data = r8153_phy_status(tp, 0);
4077
4078         if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
4079             tp->version == RTL_VER_05)
4080                 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
4081
4082         data = r8152_mdio_read(tp, MII_BMCR);
4083         if (data & BMCR_PDOWN) {
4084                 data &= ~BMCR_PDOWN;
4085                 r8152_mdio_write(tp, MII_BMCR, data);
4086         }
4087
4088         data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
4089
4090         r8153_u2p3en(tp, false);
4091
4092         if (tp->version == RTL_VER_04) {
4093                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
4094                 ocp_data &= ~pwd_dn_scale_mask;
4095                 ocp_data |= pwd_dn_scale(96);
4096                 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
4097
4098                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
4099                 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
4100                 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
4101         } else if (tp->version == RTL_VER_05) {
4102                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
4103                 ocp_data &= ~ECM_ALDPS;
4104                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
4105
4106                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
4107                 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
4108                         ocp_data &= ~DYNAMIC_BURST;
4109                 else
4110                         ocp_data |= DYNAMIC_BURST;
4111                 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
4112         } else if (tp->version == RTL_VER_06) {
4113                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
4114                 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
4115                         ocp_data &= ~DYNAMIC_BURST;
4116                 else
4117                         ocp_data |= DYNAMIC_BURST;
4118                 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
4119         }
4120
4121         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
4122         ocp_data |= EP4_FULL_FC;
4123         ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
4124
4125         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
4126         ocp_data &= ~TIMER11_EN;
4127         ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
4128
4129         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
4130         ocp_data &= ~LED_MODE_MASK;
4131         ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
4132
4133         ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
4134         if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
4135                 ocp_data |= LPM_TIMER_500MS;
4136         else
4137                 ocp_data |= LPM_TIMER_500US;
4138         ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
4139
4140         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
4141         ocp_data &= ~SEN_VAL_MASK;
4142         ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
4143         ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
4144
4145         ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
4146
4147         r8153_power_cut_en(tp, false);
4148         r8153_u1u2en(tp, true);
4149         r8153_mac_clk_spd(tp, false);
4150         usb_enable_lpm(tp->udev);
4151
4152         /* rx aggregation */
4153         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4154         ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4155         if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
4156                 ocp_data |= RX_AGG_DISABLE;
4157
4158         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4159
4160         rtl_tally_reset(tp);
4161
4162         switch (tp->udev->speed) {
4163         case USB_SPEED_SUPER:
4164         case USB_SPEED_SUPER_PLUS:
4165                 tp->coalesce = COALESCE_SUPER;
4166                 break;
4167         case USB_SPEED_HIGH:
4168                 tp->coalesce = COALESCE_HIGH;
4169                 break;
4170         default:
4171                 tp->coalesce = COALESCE_SLOW;
4172                 break;
4173         }
4174 }
4175
4176 static void r8153b_init(struct r8152 *tp)
4177 {
4178         u32 ocp_data;
4179         u16 data;
4180         int i;
4181
4182         if (test_bit(RTL8152_UNPLUG, &tp->flags))
4183                 return;
4184
4185         r8153b_u1u2en(tp, false);
4186
4187         for (i = 0; i < 500; i++) {
4188                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
4189                     AUTOLOAD_DONE)
4190                         break;
4191                 msleep(20);
4192         }
4193
4194         data = r8153_phy_status(tp, 0);
4195
4196         data = r8152_mdio_read(tp, MII_BMCR);
4197         if (data & BMCR_PDOWN) {
4198                 data &= ~BMCR_PDOWN;
4199                 r8152_mdio_write(tp, MII_BMCR, data);
4200         }
4201
4202         data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
4203
4204         r8153_u2p3en(tp, false);
4205
4206         /* MSC timer = 0xfff * 8ms = 32760 ms */
4207         ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
4208
4209         /* U1/U2/L1 idle timer. 500 us */
4210         ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
4211
4212         r8153b_power_cut_en(tp, false);
4213         r8153b_ups_en(tp, false);
4214         r8153b_queue_wake(tp, false);
4215         rtl_runtime_suspend_enable(tp, false);
4216         r8153b_u1u2en(tp, true);
4217         usb_enable_lpm(tp->udev);
4218
4219         /* MAC clock speed down */
4220         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
4221         ocp_data |= MAC_CLK_SPDWN_EN;
4222         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
4223
4224         set_bit(GREEN_ETHERNET, &tp->flags);
4225
4226         /* rx aggregation */
4227         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4228         ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4229         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4230
4231         rtl_tally_reset(tp);
4232
4233         tp->coalesce = 15000;   /* 15 us */
4234 }
4235
4236 static int rtl8152_pre_reset(struct usb_interface *intf)
4237 {
4238         struct r8152 *tp = usb_get_intfdata(intf);
4239         struct net_device *netdev;
4240
4241         if (!tp)
4242                 return 0;
4243
4244         netdev = tp->netdev;
4245         if (!netif_running(netdev))
4246                 return 0;
4247
4248         netif_stop_queue(netdev);
4249         napi_disable(&tp->napi);
4250         clear_bit(WORK_ENABLE, &tp->flags);
4251         usb_kill_urb(tp->intr_urb);
4252         cancel_delayed_work_sync(&tp->schedule);
4253         if (netif_carrier_ok(netdev)) {
4254                 mutex_lock(&tp->control);
4255                 tp->rtl_ops.disable(tp);
4256                 mutex_unlock(&tp->control);
4257         }
4258
4259         return 0;
4260 }
4261
4262 static int rtl8152_post_reset(struct usb_interface *intf)
4263 {
4264         struct r8152 *tp = usb_get_intfdata(intf);
4265         struct net_device *netdev;
4266
4267         if (!tp)
4268                 return 0;
4269
4270         netdev = tp->netdev;
4271         if (!netif_running(netdev))
4272                 return 0;
4273
4274         set_bit(WORK_ENABLE, &tp->flags);
4275         if (netif_carrier_ok(netdev)) {
4276                 mutex_lock(&tp->control);
4277                 tp->rtl_ops.enable(tp);
4278                 rtl_start_rx(tp);
4279                 _rtl8152_set_rx_mode(netdev);
4280                 mutex_unlock(&tp->control);
4281         }
4282
4283         napi_enable(&tp->napi);
4284         netif_wake_queue(netdev);
4285         usb_submit_urb(tp->intr_urb, GFP_KERNEL);
4286
4287         if (!list_empty(&tp->rx_done))
4288                 napi_schedule(&tp->napi);
4289
4290         return 0;
4291 }
4292
4293 static bool delay_autosuspend(struct r8152 *tp)
4294 {
4295         bool sw_linking = !!netif_carrier_ok(tp->netdev);
4296         bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
4297
4298         /* This means a linking change occurs and the driver doesn't detect it,
4299          * yet. If the driver has disabled tx/rx and hw is linking on, the
4300          * device wouldn't wake up by receiving any packet.
4301          */
4302         if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
4303                 return true;
4304
4305         /* If the linking down is occurred by nway, the device may miss the
4306          * linking change event. And it wouldn't wake when linking on.
4307          */
4308         if (!sw_linking && tp->rtl_ops.in_nway(tp))
4309                 return true;
4310         else if (!skb_queue_empty(&tp->tx_queue))
4311                 return true;
4312         else
4313                 return false;
4314 }
4315
4316 static int rtl8152_runtime_resume(struct r8152 *tp)
4317 {
4318         struct net_device *netdev = tp->netdev;
4319
4320         if (netif_running(netdev) && netdev->flags & IFF_UP) {
4321                 struct napi_struct *napi = &tp->napi;
4322
4323                 tp->rtl_ops.autosuspend_en(tp, false);
4324                 napi_disable(napi);
4325                 set_bit(WORK_ENABLE, &tp->flags);
4326
4327                 if (netif_carrier_ok(netdev)) {
4328                         if (rtl8152_get_speed(tp) & LINK_STATUS) {
4329                                 rtl_start_rx(tp);
4330                         } else {
4331                                 netif_carrier_off(netdev);
4332                                 tp->rtl_ops.disable(tp);
4333                                 netif_info(tp, link, netdev, "linking down\n");
4334                         }
4335                 }
4336
4337                 napi_enable(napi);
4338                 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4339                 smp_mb__after_atomic();
4340
4341                 if (!list_empty(&tp->rx_done))
4342                         napi_schedule(&tp->napi);
4343
4344                 usb_submit_urb(tp->intr_urb, GFP_NOIO);
4345         } else {
4346                 if (netdev->flags & IFF_UP)
4347                         tp->rtl_ops.autosuspend_en(tp, false);
4348
4349                 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4350         }
4351
4352         return 0;
4353 }
4354
4355 static int rtl8152_system_resume(struct r8152 *tp)
4356 {
4357         struct net_device *netdev = tp->netdev;
4358
4359         netif_device_attach(netdev);
4360
4361         if (netif_running(netdev) && netdev->flags & IFF_UP) {
4362                 tp->rtl_ops.up(tp);
4363                 netif_carrier_off(netdev);
4364                 set_bit(WORK_ENABLE, &tp->flags);
4365                 usb_submit_urb(tp->intr_urb, GFP_NOIO);
4366         }
4367
4368         return 0;
4369 }
4370
4371 static int rtl8152_runtime_suspend(struct r8152 *tp)
4372 {
4373         struct net_device *netdev = tp->netdev;
4374         int ret = 0;
4375
4376         set_bit(SELECTIVE_SUSPEND, &tp->flags);
4377         smp_mb__after_atomic();
4378
4379         if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
4380                 u32 rcr = 0;
4381
4382                 if (netif_carrier_ok(netdev)) {
4383                         u32 ocp_data;
4384
4385                         rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4386                         ocp_data = rcr & ~RCR_ACPT_ALL;
4387                         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4388                         rxdy_gated_en(tp, true);
4389                         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
4390                                                  PLA_OOB_CTRL);
4391                         if (!(ocp_data & RXFIFO_EMPTY)) {
4392                                 rxdy_gated_en(tp, false);
4393                                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
4394                                 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4395                                 smp_mb__after_atomic();
4396                                 ret = -EBUSY;
4397                                 goto out1;
4398                         }
4399                 }
4400
4401                 clear_bit(WORK_ENABLE, &tp->flags);
4402                 usb_kill_urb(tp->intr_urb);
4403
4404                 tp->rtl_ops.autosuspend_en(tp, true);
4405
4406                 if (netif_carrier_ok(netdev)) {
4407                         struct napi_struct *napi = &tp->napi;
4408
4409                         napi_disable(napi);
4410                         rtl_stop_rx(tp);
4411                         rxdy_gated_en(tp, false);
4412                         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
4413                         napi_enable(napi);
4414                 }
4415
4416                 if (delay_autosuspend(tp)) {
4417                         rtl8152_runtime_resume(tp);
4418                         ret = -EBUSY;
4419                 }
4420         }
4421
4422 out1:
4423         return ret;
4424 }
4425
4426 static int rtl8152_system_suspend(struct r8152 *tp)
4427 {
4428         struct net_device *netdev = tp->netdev;
4429
4430         netif_device_detach(netdev);
4431
4432         if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
4433                 struct napi_struct *napi = &tp->napi;
4434
4435                 clear_bit(WORK_ENABLE, &tp->flags);
4436                 usb_kill_urb(tp->intr_urb);
4437                 napi_disable(napi);
4438                 cancel_delayed_work_sync(&tp->schedule);
4439                 tp->rtl_ops.down(tp);
4440                 napi_enable(napi);
4441         }
4442
4443         return 0;
4444 }
4445
4446 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
4447 {
4448         struct r8152 *tp = usb_get_intfdata(intf);
4449         int ret;
4450
4451         mutex_lock(&tp->control);
4452
4453         if (PMSG_IS_AUTO(message))
4454                 ret = rtl8152_runtime_suspend(tp);
4455         else
4456                 ret = rtl8152_system_suspend(tp);
4457
4458         mutex_unlock(&tp->control);
4459
4460         return ret;
4461 }
4462
4463 static int rtl8152_resume(struct usb_interface *intf)
4464 {
4465         struct r8152 *tp = usb_get_intfdata(intf);
4466         int ret;
4467
4468         mutex_lock(&tp->control);
4469
4470         if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
4471                 ret = rtl8152_runtime_resume(tp);
4472         else
4473                 ret = rtl8152_system_resume(tp);
4474
4475         mutex_unlock(&tp->control);
4476
4477         return ret;
4478 }
4479
4480 static int rtl8152_reset_resume(struct usb_interface *intf)
4481 {
4482         struct r8152 *tp = usb_get_intfdata(intf);
4483
4484         clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4485         mutex_lock(&tp->control);
4486         tp->rtl_ops.init(tp);
4487         queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
4488         mutex_unlock(&tp->control);
4489         return rtl8152_resume(intf);
4490 }
4491
4492 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4493 {
4494         struct r8152 *tp = netdev_priv(dev);
4495
4496         if (usb_autopm_get_interface(tp->intf) < 0)
4497                 return;
4498
4499         if (!rtl_can_wakeup(tp)) {
4500                 wol->supported = 0;
4501                 wol->wolopts = 0;
4502         } else {
4503                 mutex_lock(&tp->control);
4504                 wol->supported = WAKE_ANY;
4505                 wol->wolopts = __rtl_get_wol(tp);
4506                 mutex_unlock(&tp->control);
4507         }
4508
4509         usb_autopm_put_interface(tp->intf);
4510 }
4511
4512 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4513 {
4514         struct r8152 *tp = netdev_priv(dev);
4515         int ret;
4516
4517         if (!rtl_can_wakeup(tp))
4518                 return -EOPNOTSUPP;
4519
4520         if (wol->wolopts & ~WAKE_ANY)
4521                 return -EINVAL;
4522
4523         ret = usb_autopm_get_interface(tp->intf);
4524         if (ret < 0)
4525                 goto out_set_wol;
4526
4527         mutex_lock(&tp->control);
4528
4529         __rtl_set_wol(tp, wol->wolopts);
4530         tp->saved_wolopts = wol->wolopts & WAKE_ANY;
4531
4532         mutex_unlock(&tp->control);
4533
4534         usb_autopm_put_interface(tp->intf);
4535
4536 out_set_wol:
4537         return ret;
4538 }
4539
4540 static u32 rtl8152_get_msglevel(struct net_device *dev)
4541 {
4542         struct r8152 *tp = netdev_priv(dev);
4543
4544         return tp->msg_enable;
4545 }
4546
4547 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
4548 {
4549         struct r8152 *tp = netdev_priv(dev);
4550
4551         tp->msg_enable = value;
4552 }
4553
4554 static void rtl8152_get_drvinfo(struct net_device *netdev,
4555                                 struct ethtool_drvinfo *info)
4556 {
4557         struct r8152 *tp = netdev_priv(netdev);
4558
4559         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
4560         strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
4561         usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
4562 }
4563
4564 static
4565 int rtl8152_get_link_ksettings(struct net_device *netdev,
4566                                struct ethtool_link_ksettings *cmd)
4567 {
4568         struct r8152 *tp = netdev_priv(netdev);
4569         int ret;
4570
4571         if (!tp->mii.mdio_read)
4572                 return -EOPNOTSUPP;
4573
4574         ret = usb_autopm_get_interface(tp->intf);
4575         if (ret < 0)
4576                 goto out;
4577
4578         mutex_lock(&tp->control);
4579
4580         mii_ethtool_get_link_ksettings(&tp->mii, cmd);
4581
4582         mutex_unlock(&tp->control);
4583
4584         usb_autopm_put_interface(tp->intf);
4585
4586 out:
4587         return ret;
4588 }
4589
4590 static int rtl8152_set_link_ksettings(struct net_device *dev,
4591                                       const struct ethtool_link_ksettings *cmd)
4592 {
4593         struct r8152 *tp = netdev_priv(dev);
4594         int ret;
4595
4596         ret = usb_autopm_get_interface(tp->intf);
4597         if (ret < 0)
4598                 goto out;
4599
4600         mutex_lock(&tp->control);
4601
4602         ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
4603                                 cmd->base.duplex);
4604         if (!ret) {
4605                 tp->autoneg = cmd->base.autoneg;
4606                 tp->speed = cmd->base.speed;
4607                 tp->duplex = cmd->base.duplex;
4608         }
4609
4610         mutex_unlock(&tp->control);
4611
4612         usb_autopm_put_interface(tp->intf);
4613
4614 out:
4615         return ret;
4616 }
4617
4618 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
4619         "tx_packets",
4620         "rx_packets",
4621         "tx_errors",
4622         "rx_errors",
4623         "rx_missed",
4624         "align_errors",
4625         "tx_single_collisions",
4626         "tx_multi_collisions",
4627         "rx_unicast",
4628         "rx_broadcast",
4629         "rx_multicast",
4630         "tx_aborted",
4631         "tx_underrun",
4632 };
4633
4634 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
4635 {
4636         switch (sset) {
4637         case ETH_SS_STATS:
4638                 return ARRAY_SIZE(rtl8152_gstrings);
4639         default:
4640                 return -EOPNOTSUPP;
4641         }
4642 }
4643
4644 static void rtl8152_get_ethtool_stats(struct net_device *dev,
4645                                       struct ethtool_stats *stats, u64 *data)
4646 {
4647         struct r8152 *tp = netdev_priv(dev);
4648         struct tally_counter tally;
4649
4650         if (usb_autopm_get_interface(tp->intf) < 0)
4651                 return;
4652
4653         generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
4654
4655         usb_autopm_put_interface(tp->intf);
4656
4657         data[0] = le64_to_cpu(tally.tx_packets);
4658         data[1] = le64_to_cpu(tally.rx_packets);
4659         data[2] = le64_to_cpu(tally.tx_errors);
4660         data[3] = le32_to_cpu(tally.rx_errors);
4661         data[4] = le16_to_cpu(tally.rx_missed);
4662         data[5] = le16_to_cpu(tally.align_errors);
4663         data[6] = le32_to_cpu(tally.tx_one_collision);
4664         data[7] = le32_to_cpu(tally.tx_multi_collision);
4665         data[8] = le64_to_cpu(tally.rx_unicast);
4666         data[9] = le64_to_cpu(tally.rx_broadcast);
4667         data[10] = le32_to_cpu(tally.rx_multicast);
4668         data[11] = le16_to_cpu(tally.tx_aborted);
4669         data[12] = le16_to_cpu(tally.tx_underrun);
4670 }
4671
4672 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
4673 {
4674         switch (stringset) {
4675         case ETH_SS_STATS:
4676                 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
4677                 break;
4678         }
4679 }
4680
4681 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
4682 {
4683         u32 ocp_data, lp, adv, supported = 0;
4684         u16 val;
4685
4686         val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
4687         supported = mmd_eee_cap_to_ethtool_sup_t(val);
4688
4689         val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
4690         adv = mmd_eee_adv_to_ethtool_adv_t(val);
4691
4692         val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
4693         lp = mmd_eee_adv_to_ethtool_adv_t(val);
4694
4695         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4696         ocp_data &= EEE_RX_EN | EEE_TX_EN;
4697
4698         eee->eee_enabled = !!ocp_data;
4699         eee->eee_active = !!(supported & adv & lp);
4700         eee->supported = supported;
4701         eee->advertised = adv;
4702         eee->lp_advertised = lp;
4703
4704         return 0;
4705 }
4706
4707 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4708 {
4709         u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4710
4711         r8152_eee_en(tp, eee->eee_enabled);
4712
4713         if (!eee->eee_enabled)
4714                 val = 0;
4715
4716         r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4717
4718         return 0;
4719 }
4720
4721 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
4722 {
4723         u32 ocp_data, lp, adv, supported = 0;
4724         u16 val;
4725
4726         val = ocp_reg_read(tp, OCP_EEE_ABLE);
4727         supported = mmd_eee_cap_to_ethtool_sup_t(val);
4728
4729         val = ocp_reg_read(tp, OCP_EEE_ADV);
4730         adv = mmd_eee_adv_to_ethtool_adv_t(val);
4731
4732         val = ocp_reg_read(tp, OCP_EEE_LPABLE);
4733         lp = mmd_eee_adv_to_ethtool_adv_t(val);
4734
4735         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4736         ocp_data &= EEE_RX_EN | EEE_TX_EN;
4737
4738         eee->eee_enabled = !!ocp_data;
4739         eee->eee_active = !!(supported & adv & lp);
4740         eee->supported = supported;
4741         eee->advertised = adv;
4742         eee->lp_advertised = lp;
4743
4744         return 0;
4745 }
4746
4747 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4748 {
4749         u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4750
4751         r8153_eee_en(tp, eee->eee_enabled);
4752
4753         if (!eee->eee_enabled)
4754                 val = 0;
4755
4756         ocp_reg_write(tp, OCP_EEE_ADV, val);
4757
4758         return 0;
4759 }
4760
4761 static int r8153b_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4762 {
4763         u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4764
4765         r8153b_eee_en(tp, eee->eee_enabled);
4766
4767         if (!eee->eee_enabled)
4768                 val = 0;
4769
4770         ocp_reg_write(tp, OCP_EEE_ADV, val);
4771
4772         return 0;
4773 }
4774
4775 static int
4776 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
4777 {
4778         struct r8152 *tp = netdev_priv(net);
4779         int ret;
4780
4781         ret = usb_autopm_get_interface(tp->intf);
4782         if (ret < 0)
4783                 goto out;
4784
4785         mutex_lock(&tp->control);
4786
4787         ret = tp->rtl_ops.eee_get(tp, edata);
4788
4789         mutex_unlock(&tp->control);
4790
4791         usb_autopm_put_interface(tp->intf);
4792
4793 out:
4794         return ret;
4795 }
4796
4797 static int
4798 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
4799 {
4800         struct r8152 *tp = netdev_priv(net);
4801         int ret;
4802
4803         ret = usb_autopm_get_interface(tp->intf);
4804         if (ret < 0)
4805                 goto out;
4806
4807         mutex_lock(&tp->control);
4808
4809         ret = tp->rtl_ops.eee_set(tp, edata);
4810         if (!ret)
4811                 ret = mii_nway_restart(&tp->mii);
4812
4813         mutex_unlock(&tp->control);
4814
4815         usb_autopm_put_interface(tp->intf);
4816
4817 out:
4818         return ret;
4819 }
4820
4821 static int rtl8152_nway_reset(struct net_device *dev)
4822 {
4823         struct r8152 *tp = netdev_priv(dev);
4824         int ret;
4825
4826         ret = usb_autopm_get_interface(tp->intf);
4827         if (ret < 0)
4828                 goto out;
4829
4830         mutex_lock(&tp->control);
4831
4832         ret = mii_nway_restart(&tp->mii);
4833
4834         mutex_unlock(&tp->control);
4835
4836         usb_autopm_put_interface(tp->intf);
4837
4838 out:
4839         return ret;
4840 }
4841
4842 static int rtl8152_get_coalesce(struct net_device *netdev,
4843                                 struct ethtool_coalesce *coalesce)
4844 {
4845         struct r8152 *tp = netdev_priv(netdev);
4846
4847         switch (tp->version) {
4848         case RTL_VER_01:
4849         case RTL_VER_02:
4850         case RTL_VER_07:
4851                 return -EOPNOTSUPP;
4852         default:
4853                 break;
4854         }
4855
4856         coalesce->rx_coalesce_usecs = tp->coalesce;
4857
4858         return 0;
4859 }
4860
4861 static int rtl8152_set_coalesce(struct net_device *netdev,
4862                                 struct ethtool_coalesce *coalesce)
4863 {
4864         struct r8152 *tp = netdev_priv(netdev);
4865         int ret;
4866
4867         switch (tp->version) {
4868         case RTL_VER_01:
4869         case RTL_VER_02:
4870         case RTL_VER_07:
4871                 return -EOPNOTSUPP;
4872         default:
4873                 break;
4874         }
4875
4876         if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
4877                 return -EINVAL;
4878
4879         ret = usb_autopm_get_interface(tp->intf);
4880         if (ret < 0)
4881                 return ret;
4882
4883         mutex_lock(&tp->control);
4884
4885         if (tp->coalesce != coalesce->rx_coalesce_usecs) {
4886                 tp->coalesce = coalesce->rx_coalesce_usecs;
4887
4888                 if (netif_running(tp->netdev) && netif_carrier_ok(netdev))
4889                         r8153_set_rx_early_timeout(tp);
4890         }
4891
4892         mutex_unlock(&tp->control);
4893
4894         usb_autopm_put_interface(tp->intf);
4895
4896         return ret;
4897 }
4898
4899 static const struct ethtool_ops ops = {
4900         .get_drvinfo = rtl8152_get_drvinfo,
4901         .get_link = ethtool_op_get_link,
4902         .nway_reset = rtl8152_nway_reset,
4903         .get_msglevel = rtl8152_get_msglevel,
4904         .set_msglevel = rtl8152_set_msglevel,
4905         .get_wol = rtl8152_get_wol,
4906         .set_wol = rtl8152_set_wol,
4907         .get_strings = rtl8152_get_strings,
4908         .get_sset_count = rtl8152_get_sset_count,
4909         .get_ethtool_stats = rtl8152_get_ethtool_stats,
4910         .get_coalesce = rtl8152_get_coalesce,
4911         .set_coalesce = rtl8152_set_coalesce,
4912         .get_eee = rtl_ethtool_get_eee,
4913         .set_eee = rtl_ethtool_set_eee,
4914         .get_link_ksettings = rtl8152_get_link_ksettings,
4915         .set_link_ksettings = rtl8152_set_link_ksettings,
4916 };
4917
4918 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
4919 {
4920         struct r8152 *tp = netdev_priv(netdev);
4921         struct mii_ioctl_data *data = if_mii(rq);
4922         int res;
4923
4924         if (test_bit(RTL8152_UNPLUG, &tp->flags))
4925                 return -ENODEV;
4926
4927         res = usb_autopm_get_interface(tp->intf);
4928         if (res < 0)
4929                 goto out;
4930
4931         switch (cmd) {
4932         case SIOCGMIIPHY:
4933                 data->phy_id = R8152_PHY_ID; /* Internal PHY */
4934                 break;
4935
4936         case SIOCGMIIREG:
4937                 mutex_lock(&tp->control);
4938                 data->val_out = r8152_mdio_read(tp, data->reg_num);
4939                 mutex_unlock(&tp->control);
4940                 break;
4941
4942         case SIOCSMIIREG:
4943                 if (!capable(CAP_NET_ADMIN)) {
4944                         res = -EPERM;
4945                         break;
4946                 }
4947                 mutex_lock(&tp->control);
4948                 r8152_mdio_write(tp, data->reg_num, data->val_in);
4949                 mutex_unlock(&tp->control);
4950                 break;
4951
4952         default:
4953                 res = -EOPNOTSUPP;
4954         }
4955
4956         usb_autopm_put_interface(tp->intf);
4957
4958 out:
4959         return res;
4960 }
4961
4962 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
4963 {
4964         struct r8152 *tp = netdev_priv(dev);
4965         int ret;
4966
4967         switch (tp->version) {
4968         case RTL_VER_01:
4969         case RTL_VER_02:
4970         case RTL_VER_07:
4971                 dev->mtu = new_mtu;
4972                 return 0;
4973         default:
4974                 break;
4975         }
4976
4977         ret = usb_autopm_get_interface(tp->intf);
4978         if (ret < 0)
4979                 return ret;
4980
4981         mutex_lock(&tp->control);
4982
4983         dev->mtu = new_mtu;
4984
4985         if (netif_running(dev)) {
4986                 u32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4987
4988                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms);
4989
4990                 if (netif_carrier_ok(dev))
4991                         r8153_set_rx_early_size(tp);
4992         }
4993
4994         mutex_unlock(&tp->control);
4995
4996         usb_autopm_put_interface(tp->intf);
4997
4998         return ret;
4999 }
5000
5001 static const struct net_device_ops rtl8152_netdev_ops = {
5002         .ndo_open               = rtl8152_open,
5003         .ndo_stop               = rtl8152_close,
5004         .ndo_do_ioctl           = rtl8152_ioctl,
5005         .ndo_start_xmit         = rtl8152_start_xmit,
5006         .ndo_tx_timeout         = rtl8152_tx_timeout,
5007         .ndo_set_features       = rtl8152_set_features,
5008         .ndo_set_rx_mode        = rtl8152_set_rx_mode,
5009         .ndo_set_mac_address    = rtl8152_set_mac_address,
5010         .ndo_change_mtu         = rtl8152_change_mtu,
5011         .ndo_validate_addr      = eth_validate_addr,
5012         .ndo_features_check     = rtl8152_features_check,
5013 };
5014
5015 static void rtl8152_unload(struct r8152 *tp)
5016 {
5017         if (test_bit(RTL8152_UNPLUG, &tp->flags))
5018                 return;
5019
5020         if (tp->version != RTL_VER_01)
5021                 r8152_power_cut_en(tp, true);
5022 }
5023
5024 static void rtl8153_unload(struct r8152 *tp)
5025 {
5026         if (test_bit(RTL8152_UNPLUG, &tp->flags))
5027                 return;
5028
5029         r8153_power_cut_en(tp, false);
5030 }
5031
5032 static void rtl8153b_unload(struct r8152 *tp)
5033 {
5034         if (test_bit(RTL8152_UNPLUG, &tp->flags))
5035                 return;
5036
5037         r8153b_power_cut_en(tp, false);
5038 }
5039
5040 static int rtl_ops_init(struct r8152 *tp)
5041 {
5042         struct rtl_ops *ops = &tp->rtl_ops;
5043         int ret = 0;
5044
5045         switch (tp->version) {
5046         case RTL_VER_01:
5047         case RTL_VER_02:
5048         case RTL_VER_07:
5049                 ops->init               = r8152b_init;
5050                 ops->enable             = rtl8152_enable;
5051                 ops->disable            = rtl8152_disable;
5052                 ops->up                 = rtl8152_up;
5053                 ops->down               = rtl8152_down;
5054                 ops->unload             = rtl8152_unload;
5055                 ops->eee_get            = r8152_get_eee;
5056                 ops->eee_set            = r8152_set_eee;
5057                 ops->in_nway            = rtl8152_in_nway;
5058                 ops->hw_phy_cfg         = r8152b_hw_phy_cfg;
5059                 ops->autosuspend_en     = rtl_runtime_suspend_enable;
5060                 break;
5061
5062         case RTL_VER_03:
5063         case RTL_VER_04:
5064         case RTL_VER_05:
5065         case RTL_VER_06:
5066                 ops->init               = r8153_init;
5067                 ops->enable             = rtl8153_enable;
5068                 ops->disable            = rtl8153_disable;
5069                 ops->up                 = rtl8153_up;
5070                 ops->down               = rtl8153_down;
5071                 ops->unload             = rtl8153_unload;
5072                 ops->eee_get            = r8153_get_eee;
5073                 ops->eee_set            = r8153_set_eee;
5074                 ops->in_nway            = rtl8153_in_nway;
5075                 ops->hw_phy_cfg         = r8153_hw_phy_cfg;
5076                 ops->autosuspend_en     = rtl8153_runtime_enable;
5077                 break;
5078
5079         case RTL_VER_08:
5080         case RTL_VER_09:
5081                 ops->init               = r8153b_init;
5082                 ops->enable             = rtl8153_enable;
5083                 ops->disable            = rtl8153b_disable;
5084                 ops->up                 = rtl8153b_up;
5085                 ops->down               = rtl8153b_down;
5086                 ops->unload             = rtl8153b_unload;
5087                 ops->eee_get            = r8153_get_eee;
5088                 ops->eee_set            = r8153b_set_eee;
5089                 ops->in_nway            = rtl8153_in_nway;
5090                 ops->hw_phy_cfg         = r8153b_hw_phy_cfg;
5091                 ops->autosuspend_en     = rtl8153b_runtime_enable;
5092                 break;
5093
5094         default:
5095                 ret = -ENODEV;
5096                 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
5097                 break;
5098         }
5099
5100         return ret;
5101 }
5102
5103 static u8 rtl_get_version(struct usb_interface *intf)
5104 {
5105         struct usb_device *udev = interface_to_usbdev(intf);
5106         u32 ocp_data = 0;
5107         __le32 *tmp;
5108         u8 version;
5109         int ret;
5110
5111         tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
5112         if (!tmp)
5113                 return 0;
5114
5115         ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
5116                               RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
5117                               PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500);
5118         if (ret > 0)
5119                 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
5120
5121         kfree(tmp);
5122
5123         switch (ocp_data) {
5124         case 0x4c00:
5125                 version = RTL_VER_01;
5126                 break;
5127         case 0x4c10:
5128                 version = RTL_VER_02;
5129                 break;
5130         case 0x5c00:
5131                 version = RTL_VER_03;
5132                 break;
5133         case 0x5c10:
5134                 version = RTL_VER_04;
5135                 break;
5136         case 0x5c20:
5137                 version = RTL_VER_05;
5138                 break;
5139         case 0x5c30:
5140                 version = RTL_VER_06;
5141                 break;
5142         case 0x4800:
5143                 version = RTL_VER_07;
5144                 break;
5145         case 0x6000:
5146                 version = RTL_VER_08;
5147                 break;
5148         case 0x6010:
5149                 version = RTL_VER_09;
5150                 break;
5151         default:
5152                 version = RTL_VER_UNKNOWN;
5153                 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
5154                 break;
5155         }
5156
5157         dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
5158
5159         return version;
5160 }
5161
5162 static int rtl8152_probe(struct usb_interface *intf,
5163                          const struct usb_device_id *id)
5164 {
5165         struct usb_device *udev = interface_to_usbdev(intf);
5166         u8 version = rtl_get_version(intf);
5167         struct r8152 *tp;
5168         struct net_device *netdev;
5169         int ret;
5170
5171         if (version == RTL_VER_UNKNOWN)
5172                 return -ENODEV;
5173
5174         if (udev->actconfig->desc.bConfigurationValue != 1) {
5175                 usb_driver_set_configuration(udev, 1);
5176                 return -ENODEV;
5177         }
5178
5179         usb_reset_device(udev);
5180         netdev = alloc_etherdev(sizeof(struct r8152));
5181         if (!netdev) {
5182                 dev_err(&intf->dev, "Out of memory\n");
5183                 return -ENOMEM;
5184         }
5185
5186         SET_NETDEV_DEV(netdev, &intf->dev);
5187         tp = netdev_priv(netdev);
5188         tp->msg_enable = 0x7FFF;
5189
5190         tp->udev = udev;
5191         tp->netdev = netdev;
5192         tp->intf = intf;
5193         tp->version = version;
5194
5195         switch (version) {
5196         case RTL_VER_01:
5197         case RTL_VER_02:
5198         case RTL_VER_07:
5199                 tp->mii.supports_gmii = 0;
5200                 break;
5201         default:
5202                 tp->mii.supports_gmii = 1;
5203                 break;
5204         }
5205
5206         ret = rtl_ops_init(tp);
5207         if (ret)
5208                 goto out;
5209
5210         mutex_init(&tp->control);
5211         INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
5212         INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
5213
5214         netdev->netdev_ops = &rtl8152_netdev_ops;
5215         netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
5216
5217         netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
5218                             NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
5219                             NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
5220                             NETIF_F_HW_VLAN_CTAG_TX;
5221         netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
5222                               NETIF_F_TSO | NETIF_F_FRAGLIST |
5223                               NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
5224                               NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
5225         netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
5226                                 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
5227                                 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
5228
5229         if (tp->version == RTL_VER_01) {
5230                 netdev->features &= ~NETIF_F_RXCSUM;
5231                 netdev->hw_features &= ~NETIF_F_RXCSUM;
5232         }
5233
5234         if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial &&
5235             (!strcmp(udev->serial, "000001000000") || !strcmp(udev->serial, "000002000000"))) {
5236                 dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation");
5237                 set_bit(DELL_TB_RX_AGG_BUG, &tp->flags);
5238         }
5239
5240         netdev->ethtool_ops = &ops;
5241         netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
5242
5243         /* MTU range: 68 - 1500 or 9194 */
5244         netdev->min_mtu = ETH_MIN_MTU;
5245         switch (tp->version) {
5246         case RTL_VER_01:
5247         case RTL_VER_02:
5248                 netdev->max_mtu = ETH_DATA_LEN;
5249                 break;
5250         default:
5251                 netdev->max_mtu = RTL8153_MAX_MTU;
5252                 break;
5253         }
5254
5255         tp->mii.dev = netdev;
5256         tp->mii.mdio_read = read_mii_word;
5257         tp->mii.mdio_write = write_mii_word;
5258         tp->mii.phy_id_mask = 0x3f;
5259         tp->mii.reg_num_mask = 0x1f;
5260         tp->mii.phy_id = R8152_PHY_ID;
5261
5262         tp->autoneg = AUTONEG_ENABLE;
5263         tp->speed = tp->mii.supports_gmii ? SPEED_1000 : SPEED_100;
5264         tp->duplex = DUPLEX_FULL;
5265
5266         intf->needs_remote_wakeup = 1;
5267
5268         tp->rtl_ops.init(tp);
5269         queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
5270         set_ethernet_addr(tp);
5271
5272         usb_set_intfdata(intf, tp);
5273         netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
5274
5275         ret = register_netdev(netdev);
5276         if (ret != 0) {
5277                 netif_err(tp, probe, netdev, "couldn't register the device\n");
5278                 goto out1;
5279         }
5280
5281         if (!rtl_can_wakeup(tp))
5282                 __rtl_set_wol(tp, 0);
5283
5284         tp->saved_wolopts = __rtl_get_wol(tp);
5285         if (tp->saved_wolopts)
5286                 device_set_wakeup_enable(&udev->dev, true);
5287         else
5288                 device_set_wakeup_enable(&udev->dev, false);
5289
5290         netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
5291
5292         return 0;
5293
5294 out1:
5295         netif_napi_del(&tp->napi);
5296         usb_set_intfdata(intf, NULL);
5297 out:
5298         free_netdev(netdev);
5299         return ret;
5300 }
5301
5302 static void rtl8152_disconnect(struct usb_interface *intf)
5303 {
5304         struct r8152 *tp = usb_get_intfdata(intf);
5305
5306         usb_set_intfdata(intf, NULL);
5307         if (tp) {
5308                 struct usb_device *udev = tp->udev;
5309
5310                 if (udev->state == USB_STATE_NOTATTACHED)
5311                         set_bit(RTL8152_UNPLUG, &tp->flags);
5312
5313                 netif_napi_del(&tp->napi);
5314                 unregister_netdev(tp->netdev);
5315                 cancel_delayed_work_sync(&tp->hw_phy_work);
5316                 tp->rtl_ops.unload(tp);
5317                 free_netdev(tp->netdev);
5318         }
5319 }
5320
5321 #define REALTEK_USB_DEVICE(vend, prod)  \
5322         .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
5323                        USB_DEVICE_ID_MATCH_INT_CLASS, \
5324         .idVendor = (vend), \
5325         .idProduct = (prod), \
5326         .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
5327 }, \
5328 { \
5329         .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
5330                        USB_DEVICE_ID_MATCH_DEVICE, \
5331         .idVendor = (vend), \
5332         .idProduct = (prod), \
5333         .bInterfaceClass = USB_CLASS_COMM, \
5334         .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
5335         .bInterfaceProtocol = USB_CDC_PROTO_NONE
5336
5337 /* table of devices that work with this driver */
5338 static const struct usb_device_id rtl8152_table[] = {
5339         {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)},
5340         {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
5341         {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
5342         {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)},
5343         {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)},
5344         {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
5345         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x304f)},
5346         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3062)},
5347         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3069)},
5348         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x7205)},
5349         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x720c)},
5350         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x7214)},
5351         {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)},
5352         {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA,  0x09ff)},
5353         {REALTEK_USB_DEVICE(VENDOR_ID_TPLINK,  0x0601)},
5354         {}
5355 };
5356
5357 MODULE_DEVICE_TABLE(usb, rtl8152_table);
5358
5359 static struct usb_driver rtl8152_driver = {
5360         .name =         MODULENAME,
5361         .id_table =     rtl8152_table,
5362         .probe =        rtl8152_probe,
5363         .disconnect =   rtl8152_disconnect,
5364         .suspend =      rtl8152_suspend,
5365         .resume =       rtl8152_resume,
5366         .reset_resume = rtl8152_reset_resume,
5367         .pre_reset =    rtl8152_pre_reset,
5368         .post_reset =   rtl8152_post_reset,
5369         .supports_autosuspend = 1,
5370         .disable_hub_initiated_lpm = 1,
5371 };
5372
5373 module_usb_driver(rtl8152_driver);
5374
5375 MODULE_AUTHOR(DRIVER_AUTHOR);
5376 MODULE_DESCRIPTION(DRIVER_DESC);
5377 MODULE_LICENSE("GPL");
5378 MODULE_VERSION(DRIVER_VERSION);