2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
10 #include <linux/signal.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/mii.h>
16 #include <linux/ethtool.h>
17 #include <linux/usb.h>
18 #include <linux/crc32.h>
19 #include <linux/if_vlan.h>
20 #include <linux/uaccess.h>
21 #include <linux/list.h>
23 #include <linux/ipv6.h>
24 #include <net/ip6_checksum.h>
25 #include <uapi/linux/mdio.h>
26 #include <linux/mdio.h>
27 #include <linux/usb/cdc.h>
28 #include <linux/suspend.h>
29 #include <linux/acpi.h>
31 /* Information for net-next */
32 #define NETNEXT_VERSION "09"
34 /* Information for net */
35 #define NET_VERSION "9"
37 #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
38 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
39 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
40 #define MODULENAME "r8152"
42 #define R8152_PHY_ID 32
44 #define PLA_IDR 0xc000
45 #define PLA_RCR 0xc010
46 #define PLA_RMS 0xc016
47 #define PLA_RXFIFO_CTRL0 0xc0a0
48 #define PLA_RXFIFO_CTRL1 0xc0a4
49 #define PLA_RXFIFO_CTRL2 0xc0a8
50 #define PLA_DMY_REG0 0xc0b0
51 #define PLA_FMC 0xc0b4
52 #define PLA_CFG_WOL 0xc0b6
53 #define PLA_TEREDO_CFG 0xc0bc
54 #define PLA_TEREDO_WAKE_BASE 0xc0c4
55 #define PLA_MAR 0xcd00
56 #define PLA_BACKUP 0xd000
57 #define PAL_BDC_CR 0xd1a0
58 #define PLA_TEREDO_TIMER 0xd2cc
59 #define PLA_REALWOW_TIMER 0xd2e8
60 #define PLA_EFUSE_DATA 0xdd00
61 #define PLA_EFUSE_CMD 0xdd02
62 #define PLA_LEDSEL 0xdd90
63 #define PLA_LED_FEATURE 0xdd92
64 #define PLA_PHYAR 0xde00
65 #define PLA_BOOT_CTRL 0xe004
66 #define PLA_GPHY_INTR_IMR 0xe022
67 #define PLA_EEE_CR 0xe040
68 #define PLA_EEEP_CR 0xe080
69 #define PLA_MAC_PWR_CTRL 0xe0c0
70 #define PLA_MAC_PWR_CTRL2 0xe0ca
71 #define PLA_MAC_PWR_CTRL3 0xe0cc
72 #define PLA_MAC_PWR_CTRL4 0xe0ce
73 #define PLA_WDT6_CTRL 0xe428
74 #define PLA_TCR0 0xe610
75 #define PLA_TCR1 0xe612
76 #define PLA_MTPS 0xe615
77 #define PLA_TXFIFO_CTRL 0xe618
78 #define PLA_RSTTALLY 0xe800
80 #define PLA_CRWECR 0xe81c
81 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
82 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
83 #define PLA_CONFIG5 0xe822
84 #define PLA_PHY_PWR 0xe84c
85 #define PLA_OOB_CTRL 0xe84f
86 #define PLA_CPCR 0xe854
87 #define PLA_MISC_0 0xe858
88 #define PLA_MISC_1 0xe85a
89 #define PLA_OCP_GPHY_BASE 0xe86c
90 #define PLA_TALLYCNT 0xe890
91 #define PLA_SFF_STS_7 0xe8de
92 #define PLA_PHYSTATUS 0xe908
93 #define PLA_BP_BA 0xfc26
94 #define PLA_BP_0 0xfc28
95 #define PLA_BP_1 0xfc2a
96 #define PLA_BP_2 0xfc2c
97 #define PLA_BP_3 0xfc2e
98 #define PLA_BP_4 0xfc30
99 #define PLA_BP_5 0xfc32
100 #define PLA_BP_6 0xfc34
101 #define PLA_BP_7 0xfc36
102 #define PLA_BP_EN 0xfc38
104 #define USB_USB2PHY 0xb41e
105 #define USB_SSPHYLINK2 0xb428
106 #define USB_U2P3_CTRL 0xb460
107 #define USB_CSR_DUMMY1 0xb464
108 #define USB_CSR_DUMMY2 0xb466
109 #define USB_DEV_STAT 0xb808
110 #define USB_CONNECT_TIMER 0xcbf8
111 #define USB_MSC_TIMER 0xcbfc
112 #define USB_BURST_SIZE 0xcfc0
113 #define USB_LPM_CONFIG 0xcfd8
114 #define USB_USB_CTRL 0xd406
115 #define USB_PHY_CTRL 0xd408
116 #define USB_TX_AGG 0xd40a
117 #define USB_RX_BUF_TH 0xd40c
118 #define USB_USB_TIMER 0xd428
119 #define USB_RX_EARLY_TIMEOUT 0xd42c
120 #define USB_RX_EARLY_SIZE 0xd42e
121 #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */
122 #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */
123 #define USB_TX_DMA 0xd434
124 #define USB_UPT_RXDMA_OWN 0xd437
125 #define USB_TOLERANCE 0xd490
126 #define USB_LPM_CTRL 0xd41a
127 #define USB_BMU_RESET 0xd4b0
128 #define USB_U1U2_TIMER 0xd4da
129 #define USB_UPS_CTRL 0xd800
130 #define USB_POWER_CUT 0xd80a
131 #define USB_MISC_0 0xd81a
132 #define USB_MISC_1 0xd81f
133 #define USB_AFE_CTRL2 0xd824
134 #define USB_UPS_CFG 0xd842
135 #define USB_UPS_FLAGS 0xd848
136 #define USB_WDT11_CTRL 0xe43c
137 #define USB_BP_BA 0xfc26
138 #define USB_BP_0 0xfc28
139 #define USB_BP_1 0xfc2a
140 #define USB_BP_2 0xfc2c
141 #define USB_BP_3 0xfc2e
142 #define USB_BP_4 0xfc30
143 #define USB_BP_5 0xfc32
144 #define USB_BP_6 0xfc34
145 #define USB_BP_7 0xfc36
146 #define USB_BP_EN 0xfc38
147 #define USB_BP_8 0xfc38
148 #define USB_BP_9 0xfc3a
149 #define USB_BP_10 0xfc3c
150 #define USB_BP_11 0xfc3e
151 #define USB_BP_12 0xfc40
152 #define USB_BP_13 0xfc42
153 #define USB_BP_14 0xfc44
154 #define USB_BP_15 0xfc46
155 #define USB_BP2_EN 0xfc48
158 #define OCP_ALDPS_CONFIG 0x2010
159 #define OCP_EEE_CONFIG1 0x2080
160 #define OCP_EEE_CONFIG2 0x2092
161 #define OCP_EEE_CONFIG3 0x2094
162 #define OCP_BASE_MII 0xa400
163 #define OCP_EEE_AR 0xa41a
164 #define OCP_EEE_DATA 0xa41c
165 #define OCP_PHY_STATUS 0xa420
166 #define OCP_NCTL_CFG 0xa42c
167 #define OCP_POWER_CFG 0xa430
168 #define OCP_EEE_CFG 0xa432
169 #define OCP_SRAM_ADDR 0xa436
170 #define OCP_SRAM_DATA 0xa438
171 #define OCP_DOWN_SPEED 0xa442
172 #define OCP_EEE_ABLE 0xa5c4
173 #define OCP_EEE_ADV 0xa5d0
174 #define OCP_EEE_LPABLE 0xa5d2
175 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
176 #define OCP_PHY_PATCH_STAT 0xb800
177 #define OCP_PHY_PATCH_CMD 0xb820
178 #define OCP_ADC_IOFFSET 0xbcfc
179 #define OCP_ADC_CFG 0xbc06
180 #define OCP_SYSCLK_CFG 0xc416
183 #define SRAM_GREEN_CFG 0x8011
184 #define SRAM_LPF_CFG 0x8012
185 #define SRAM_10M_AMP1 0x8080
186 #define SRAM_10M_AMP2 0x8082
187 #define SRAM_IMPEDANCE 0x8084
190 #define RCR_AAP 0x00000001
191 #define RCR_APM 0x00000002
192 #define RCR_AM 0x00000004
193 #define RCR_AB 0x00000008
194 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
196 /* PLA_RXFIFO_CTRL0 */
197 #define RXFIFO_THR1_NORMAL 0x00080002
198 #define RXFIFO_THR1_OOB 0x01800003
200 /* PLA_RXFIFO_CTRL1 */
201 #define RXFIFO_THR2_FULL 0x00000060
202 #define RXFIFO_THR2_HIGH 0x00000038
203 #define RXFIFO_THR2_OOB 0x0000004a
204 #define RXFIFO_THR2_NORMAL 0x00a0
206 /* PLA_RXFIFO_CTRL2 */
207 #define RXFIFO_THR3_FULL 0x00000078
208 #define RXFIFO_THR3_HIGH 0x00000048
209 #define RXFIFO_THR3_OOB 0x0000005a
210 #define RXFIFO_THR3_NORMAL 0x0110
212 /* PLA_TXFIFO_CTRL */
213 #define TXFIFO_THR_NORMAL 0x00400008
214 #define TXFIFO_THR_NORMAL2 0x01000008
217 #define ECM_ALDPS 0x0002
220 #define FMC_FCR_MCU_EN 0x0001
223 #define EEEP_CR_EEEP_TX 0x0002
226 #define WDT6_SET_MODE 0x0010
229 #define TCR0_TX_EMPTY 0x0800
230 #define TCR0_AUTO_FIFO 0x0080
233 #define VERSION_MASK 0x7cf0
236 #define MTPS_JUMBO (12 * 1024 / 64)
237 #define MTPS_DEFAULT (6 * 1024 / 64)
240 #define TALLY_RESET 0x0001
248 #define CRWECR_NORAML 0x00
249 #define CRWECR_CONFIG 0xc0
252 #define NOW_IS_OOB 0x80
253 #define TXFIFO_EMPTY 0x20
254 #define RXFIFO_EMPTY 0x10
255 #define LINK_LIST_READY 0x02
256 #define DIS_MCU_CLROOB 0x01
257 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
260 #define RXDY_GATED_EN 0x0008
263 #define RE_INIT_LL 0x8000
264 #define MCU_BORW_EN 0x4000
267 #define CPCR_RX_VLAN 0x0040
270 #define MAGIC_EN 0x0001
273 #define TEREDO_SEL 0x8000
274 #define TEREDO_WAKE_MASK 0x7f00
275 #define TEREDO_RS_EVENT_MASK 0x00fe
276 #define OOB_TEREDO_EN 0x0001
279 #define ALDPS_PROXY_MODE 0x0001
282 #define EFUSE_READ_CMD BIT(15)
283 #define EFUSE_DATA_BIT16 BIT(7)
286 #define LINK_ON_WAKE_EN 0x0010
287 #define LINK_OFF_WAKE_EN 0x0008
290 #define BWF_EN 0x0040
291 #define MWF_EN 0x0020
292 #define UWF_EN 0x0010
293 #define LAN_WAKE_EN 0x0002
295 /* PLA_LED_FEATURE */
296 #define LED_MODE_MASK 0x0700
299 #define TX_10M_IDLE_EN 0x0080
300 #define PFM_PWM_SWITCH 0x0040
302 /* PLA_MAC_PWR_CTRL */
303 #define D3_CLK_GATED_EN 0x00004000
304 #define MCU_CLK_RATIO 0x07010f07
305 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
306 #define ALDPS_SPDWN_RATIO 0x0f87
308 /* PLA_MAC_PWR_CTRL2 */
309 #define EEE_SPDWN_RATIO 0x8007
310 #define MAC_CLK_SPDWN_EN BIT(15)
312 /* PLA_MAC_PWR_CTRL3 */
313 #define PKT_AVAIL_SPDWN_EN 0x0100
314 #define SUSPEND_SPDWN_EN 0x0004
315 #define U1U2_SPDWN_EN 0x0002
316 #define L1_SPDWN_EN 0x0001
318 /* PLA_MAC_PWR_CTRL4 */
319 #define PWRSAVE_SPDWN_EN 0x1000
320 #define RXDV_SPDWN_EN 0x0800
321 #define TX10MIDLE_EN 0x0100
322 #define TP100_SPDWN_EN 0x0020
323 #define TP500_SPDWN_EN 0x0010
324 #define TP1000_SPDWN_EN 0x0008
325 #define EEE_SPDWN_EN 0x0001
327 /* PLA_GPHY_INTR_IMR */
328 #define GPHY_STS_MSK 0x0001
329 #define SPEED_DOWN_MSK 0x0002
330 #define SPDWN_RXDV_MSK 0x0004
331 #define SPDWN_LINKCHG_MSK 0x0008
334 #define PHYAR_FLAG 0x80000000
337 #define EEE_RX_EN 0x0001
338 #define EEE_TX_EN 0x0002
341 #define AUTOLOAD_DONE 0x0002
344 #define USB2PHY_SUSPEND 0x0001
345 #define USB2PHY_L1 0x0002
348 #define pwd_dn_scale_mask 0x3ffe
349 #define pwd_dn_scale(x) ((x) << 1)
352 #define DYNAMIC_BURST 0x0001
355 #define EP4_FULL_FC 0x0001
358 #define STAT_SPEED_MASK 0x0006
359 #define STAT_SPEED_HIGH 0x0000
360 #define STAT_SPEED_FULL 0x0002
363 #define LPM_U1U2_EN BIT(0)
366 #define TX_AGG_MAX_THRESHOLD 0x03
369 #define RX_THR_SUPPER 0x0c350180
370 #define RX_THR_HIGH 0x7a120180
371 #define RX_THR_SLOW 0xffff0180
372 #define RX_THR_B 0x00010001
375 #define TEST_MODE_DISABLE 0x00000001
376 #define TX_SIZE_ADJUST1 0x00000100
379 #define BMU_RESET_EP_IN 0x01
380 #define BMU_RESET_EP_OUT 0x02
382 /* USB_UPT_RXDMA_OWN */
383 #define OWN_UPDATE BIT(0)
384 #define OWN_CLEAR BIT(1)
387 #define POWER_CUT 0x0100
389 /* USB_PM_CTRL_STATUS */
390 #define RESUME_INDICATE 0x0001
393 #define RX_AGG_DISABLE 0x0010
394 #define RX_ZERO_EN 0x0080
397 #define U2P3_ENABLE 0x0001
400 #define PWR_EN 0x0001
401 #define PHASE2_EN 0x0008
402 #define UPS_EN BIT(4)
403 #define USP_PREWAKE BIT(5)
406 #define PCUT_STATUS 0x0001
408 /* USB_RX_EARLY_TIMEOUT */
409 #define COALESCE_SUPER 85000U
410 #define COALESCE_HIGH 250000U
411 #define COALESCE_SLOW 524280U
414 #define TIMER11_EN 0x0001
417 /* bit 4 ~ 5: fifo empty boundary */
418 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
419 /* bit 2 ~ 3: LMP timer */
420 #define LPM_TIMER_MASK 0x0c
421 #define LPM_TIMER_500MS 0x04 /* 500 ms */
422 #define LPM_TIMER_500US 0x0c /* 500 us */
423 #define ROK_EXIT_LPM 0x02
426 #define SEN_VAL_MASK 0xf800
427 #define SEN_VAL_NORMAL 0xa000
428 #define SEL_RXIDLE 0x0100
431 #define SAW_CNT_1MS_MASK 0x0fff
434 #define UPS_FLAGS_R_TUNE BIT(0)
435 #define UPS_FLAGS_EN_10M_CKDIV BIT(1)
436 #define UPS_FLAGS_250M_CKDIV BIT(2)
437 #define UPS_FLAGS_EN_ALDPS BIT(3)
438 #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4)
439 #define UPS_FLAGS_SPEED_MASK (0xf << 16)
440 #define ups_flags_speed(x) ((x) << 16)
441 #define UPS_FLAGS_EN_EEE BIT(20)
442 #define UPS_FLAGS_EN_500M_EEE BIT(21)
443 #define UPS_FLAGS_EN_EEE_CKDIV BIT(22)
444 #define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24)
445 #define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25)
446 #define UPS_FLAGS_EN_GREEN BIT(26)
447 #define UPS_FLAGS_EN_FLOW_CTR BIT(27)
461 /* OCP_ALDPS_CONFIG */
462 #define ENPWRSAVE 0x8000
463 #define ENPDNPS 0x0200
464 #define LINKENA 0x0100
465 #define DIS_SDSAVE 0x0010
468 #define PHY_STAT_MASK 0x0007
469 #define PHY_STAT_EXT_INIT 2
470 #define PHY_STAT_LAN_ON 3
471 #define PHY_STAT_PWRDN 5
474 #define PGA_RETURN_EN BIT(1)
477 #define EEE_CLKDIV_EN 0x8000
478 #define EN_ALDPS 0x0004
479 #define EN_10M_PLLOFF 0x0001
481 /* OCP_EEE_CONFIG1 */
482 #define RG_TXLPI_MSK_HFDUP 0x8000
483 #define RG_MATCLR_EN 0x4000
484 #define EEE_10_CAP 0x2000
485 #define EEE_NWAY_EN 0x1000
486 #define TX_QUIET_EN 0x0200
487 #define RX_QUIET_EN 0x0100
488 #define sd_rise_time_mask 0x0070
489 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
490 #define RG_RXLPI_MSK_HFDUP 0x0008
491 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
493 /* OCP_EEE_CONFIG2 */
494 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
495 #define RG_DACQUIET_EN 0x0400
496 #define RG_LDVQUIET_EN 0x0200
497 #define RG_CKRSEL 0x0020
498 #define RG_EEEPRG_EN 0x0010
500 /* OCP_EEE_CONFIG3 */
501 #define fast_snr_mask 0xff80
502 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
503 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
504 #define MSK_PH 0x0006 /* bit 0 ~ 3 */
507 /* bit[15:14] function */
508 #define FUN_ADDR 0x0000
509 #define FUN_DATA 0x4000
510 /* bit[4:0] device addr */
513 #define CTAP_SHORT_EN 0x0040
514 #define EEE10_EN 0x0010
517 #define EN_EEE_CMODE BIT(14)
518 #define EN_EEE_1000 BIT(13)
519 #define EN_EEE_100 BIT(12)
520 #define EN_10M_CLKDIV BIT(11)
521 #define EN_10M_BGOFF 0x0080
524 #define TXDIS_STATE 0x01
525 #define ABD_STATE 0x02
527 /* OCP_PHY_PATCH_STAT */
528 #define PATCH_READY BIT(6)
530 /* OCP_PHY_PATCH_CMD */
531 #define PATCH_REQUEST BIT(4)
534 #define CKADSEL_L 0x0100
535 #define ADC_EN 0x0080
536 #define EN_EMI_L 0x0040
539 #define clk_div_expo(x) (min(x, 5) << 8)
542 #define GREEN_ETH_EN BIT(15)
543 #define R_TUNE_EN BIT(11)
546 #define LPF_AUTO_TUNE 0x8000
549 #define GDAC_IB_UPALL 0x0008
552 #define AMP_DN 0x0200
555 #define RX_DRIVING_MASK 0x6000
558 #define AD_MASK 0xfee0
559 #define BND_MASK 0x0004
561 #define PASS_THRU_MASK 0x1
563 enum rtl_register_content {
571 #define RTL8152_MAX_TX 4
572 #define RTL8152_MAX_RX 10
577 #define INTR_LINK 0x0004
579 #define RTL8152_REQT_READ 0xc0
580 #define RTL8152_REQT_WRITE 0x40
581 #define RTL8152_REQ_GET_REGS 0x05
582 #define RTL8152_REQ_SET_REGS 0x05
584 #define BYTE_EN_DWORD 0xff
585 #define BYTE_EN_WORD 0x33
586 #define BYTE_EN_BYTE 0x11
587 #define BYTE_EN_SIX_BYTES 0x3f
588 #define BYTE_EN_START_MASK 0x0f
589 #define BYTE_EN_END_MASK 0xf0
591 #define RTL8153_MAX_PACKET 9216 /* 9K */
592 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \
594 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
595 #define RTL8153_RMS RTL8153_MAX_PACKET
596 #define RTL8152_TX_TIMEOUT (5 * HZ)
597 #define RTL8152_NAPI_WEIGHT 64
598 #define rx_reserved_size(x) ((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \
599 sizeof(struct rx_desc) + RX_ALIGN)
614 /* Define these values to match your device */
615 #define VENDOR_ID_REALTEK 0x0bda
616 #define VENDOR_ID_MICROSOFT 0x045e
617 #define VENDOR_ID_SAMSUNG 0x04e8
618 #define VENDOR_ID_LENOVO 0x17ef
619 #define VENDOR_ID_LINKSYS 0x13b1
620 #define VENDOR_ID_NVIDIA 0x0955
621 #define VENDOR_ID_TPLINK 0x2357
623 #define MCU_TYPE_PLA 0x0100
624 #define MCU_TYPE_USB 0x0000
626 struct tally_counter {
633 __le32 tx_one_collision;
634 __le32 tx_multi_collision;
644 #define RX_LEN_MASK 0x7fff
647 #define RD_UDP_CS BIT(23)
648 #define RD_TCP_CS BIT(22)
649 #define RD_IPV6_CS BIT(20)
650 #define RD_IPV4_CS BIT(19)
653 #define IPF BIT(23) /* IP checksum fail */
654 #define UDPF BIT(22) /* UDP checksum fail */
655 #define TCPF BIT(21) /* TCP checksum fail */
656 #define RX_VLAN_TAG BIT(16)
665 #define TX_FS BIT(31) /* First segment of a packet */
666 #define TX_LS BIT(30) /* Final segment of a packet */
667 #define GTSENDV4 BIT(28)
668 #define GTSENDV6 BIT(27)
669 #define GTTCPHO_SHIFT 18
670 #define GTTCPHO_MAX 0x7fU
671 #define TX_LEN_MAX 0x3ffffU
674 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
675 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
676 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
677 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
679 #define MSS_MAX 0x7ffU
680 #define TCPHO_SHIFT 17
681 #define TCPHO_MAX 0x7ffU
682 #define TX_VLAN_TAG BIT(16)
688 struct list_head list;
690 struct r8152 *context;
696 struct list_head list;
698 struct r8152 *context;
707 struct usb_device *udev;
708 struct napi_struct napi;
709 struct usb_interface *intf;
710 struct net_device *netdev;
711 struct urb *intr_urb;
712 struct tx_agg tx_info[RTL8152_MAX_TX];
713 struct rx_agg rx_info[RTL8152_MAX_RX];
714 struct list_head rx_done, tx_free;
715 struct sk_buff_head tx_queue, rx_queue;
716 spinlock_t rx_lock, tx_lock;
717 struct delayed_work schedule, hw_phy_work;
718 struct mii_if_info mii;
719 struct mutex control; /* use for hw setting */
720 #ifdef CONFIG_PM_SLEEP
721 struct notifier_block pm_notifier;
725 void (*init)(struct r8152 *);
726 int (*enable)(struct r8152 *);
727 void (*disable)(struct r8152 *);
728 void (*up)(struct r8152 *);
729 void (*down)(struct r8152 *);
730 void (*unload)(struct r8152 *);
731 int (*eee_get)(struct r8152 *, struct ethtool_eee *);
732 int (*eee_set)(struct r8152 *, struct ethtool_eee *);
733 bool (*in_nway)(struct r8152 *);
734 void (*hw_phy_cfg)(struct r8152 *);
735 void (*autosuspend_en)(struct r8152 *tp, bool enable);
771 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
772 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
774 static const int multicast_filter_limit = 32;
775 static unsigned int agg_buf_sz = 16384;
777 #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
778 VLAN_ETH_HLEN - ETH_FCS_LEN)
781 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
786 tmp = kmalloc(size, GFP_KERNEL);
790 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
791 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
792 value, index, tmp, size, 500);
794 memcpy(data, tmp, size);
801 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
806 tmp = kmemdup(data, size, GFP_KERNEL);
810 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
811 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
812 value, index, tmp, size, 500);
819 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
820 void *data, u16 type)
825 if (test_bit(RTL8152_UNPLUG, &tp->flags))
828 /* both size and indix must be 4 bytes align */
829 if ((size & 3) || !size || (index & 3) || !data)
832 if ((u32)index + (u32)size > 0xffff)
837 ret = get_registers(tp, index, type, limit, data);
845 ret = get_registers(tp, index, type, size, data);
857 set_bit(RTL8152_UNPLUG, &tp->flags);
862 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
863 u16 size, void *data, u16 type)
866 u16 byteen_start, byteen_end, byen;
869 if (test_bit(RTL8152_UNPLUG, &tp->flags))
872 /* both size and indix must be 4 bytes align */
873 if ((size & 3) || !size || (index & 3) || !data)
876 if ((u32)index + (u32)size > 0xffff)
879 byteen_start = byteen & BYTE_EN_START_MASK;
880 byteen_end = byteen & BYTE_EN_END_MASK;
882 byen = byteen_start | (byteen_start << 4);
883 ret = set_registers(tp, index, type | byen, 4, data);
896 ret = set_registers(tp, index,
897 type | BYTE_EN_DWORD,
906 ret = set_registers(tp, index,
907 type | BYTE_EN_DWORD,
919 byen = byteen_end | (byteen_end >> 4);
920 ret = set_registers(tp, index, type | byen, 4, data);
927 set_bit(RTL8152_UNPLUG, &tp->flags);
933 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
935 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
939 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
941 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
945 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
947 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
950 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
954 generic_ocp_read(tp, index, sizeof(data), &data, type);
956 return __le32_to_cpu(data);
959 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
961 __le32 tmp = __cpu_to_le32(data);
963 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
966 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
970 u16 byen = BYTE_EN_WORD;
971 u8 shift = index & 2;
976 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
978 data = __le32_to_cpu(tmp);
979 data >>= (shift * 8);
985 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
989 u16 byen = BYTE_EN_WORD;
990 u8 shift = index & 2;
996 mask <<= (shift * 8);
997 data <<= (shift * 8);
1001 tmp = __cpu_to_le32(data);
1003 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1006 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
1010 u8 shift = index & 3;
1014 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
1016 data = __le32_to_cpu(tmp);
1017 data >>= (shift * 8);
1023 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
1027 u16 byen = BYTE_EN_BYTE;
1028 u8 shift = index & 3;
1034 mask <<= (shift * 8);
1035 data <<= (shift * 8);
1039 tmp = __cpu_to_le32(data);
1041 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1044 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
1046 u16 ocp_base, ocp_index;
1048 ocp_base = addr & 0xf000;
1049 if (ocp_base != tp->ocp_base) {
1050 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1051 tp->ocp_base = ocp_base;
1054 ocp_index = (addr & 0x0fff) | 0xb000;
1055 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
1058 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
1060 u16 ocp_base, ocp_index;
1062 ocp_base = addr & 0xf000;
1063 if (ocp_base != tp->ocp_base) {
1064 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1065 tp->ocp_base = ocp_base;
1068 ocp_index = (addr & 0x0fff) | 0xb000;
1069 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
1072 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
1074 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
1077 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
1079 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
1082 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
1084 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1085 ocp_reg_write(tp, OCP_SRAM_DATA, data);
1088 static u16 sram_read(struct r8152 *tp, u16 addr)
1090 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1091 return ocp_reg_read(tp, OCP_SRAM_DATA);
1094 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
1096 struct r8152 *tp = netdev_priv(netdev);
1099 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1102 if (phy_id != R8152_PHY_ID)
1105 ret = r8152_mdio_read(tp, reg);
1111 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1113 struct r8152 *tp = netdev_priv(netdev);
1115 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1118 if (phy_id != R8152_PHY_ID)
1121 r8152_mdio_write(tp, reg, val);
1125 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1127 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1129 struct r8152 *tp = netdev_priv(netdev);
1130 struct sockaddr *addr = p;
1131 int ret = -EADDRNOTAVAIL;
1133 if (!is_valid_ether_addr(addr->sa_data))
1136 ret = usb_autopm_get_interface(tp->intf);
1140 mutex_lock(&tp->control);
1142 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1144 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1145 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1146 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1148 mutex_unlock(&tp->control);
1150 usb_autopm_put_interface(tp->intf);
1155 /* Devices containing proper chips can support a persistent
1156 * host system provided MAC address.
1157 * Examples of this are Dell TB15 and Dell WD15 docks
1159 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1162 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1163 union acpi_object *obj;
1166 unsigned char buf[6];
1168 /* test for -AD variant of RTL8153 */
1169 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1170 if ((ocp_data & AD_MASK) == 0x1000) {
1171 /* test for MAC address pass-through bit */
1172 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1173 if ((ocp_data & PASS_THRU_MASK) != 1) {
1174 netif_dbg(tp, probe, tp->netdev,
1175 "No efuse for RTL8153-AD MAC pass through\n");
1179 /* test for RTL8153-BND */
1180 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
1181 if ((ocp_data & BND_MASK) == 0) {
1182 netif_dbg(tp, probe, tp->netdev,
1183 "Invalid variant for MAC pass through\n");
1188 /* returns _AUXMAC_#AABBCCDDEEFF# */
1189 status = acpi_evaluate_object(NULL, "\\_SB.AMAC", NULL, &buffer);
1190 obj = (union acpi_object *)buffer.pointer;
1191 if (!ACPI_SUCCESS(status))
1193 if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) {
1194 netif_warn(tp, probe, tp->netdev,
1195 "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1196 obj->type, obj->string.length);
1199 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1200 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1201 netif_warn(tp, probe, tp->netdev,
1202 "Invalid header when reading pass-thru MAC addr\n");
1205 ret = hex2bin(buf, obj->string.pointer + 9, 6);
1206 if (!(ret == 0 && is_valid_ether_addr(buf))) {
1207 netif_warn(tp, probe, tp->netdev,
1208 "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1213 memcpy(sa->sa_data, buf, 6);
1214 ether_addr_copy(tp->netdev->dev_addr, sa->sa_data);
1215 netif_info(tp, probe, tp->netdev,
1216 "Using pass-thru MAC addr %pM\n", sa->sa_data);
1223 static int set_ethernet_addr(struct r8152 *tp)
1225 struct net_device *dev = tp->netdev;
1229 if (tp->version == RTL_VER_01) {
1230 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
1232 /* if device doesn't support MAC pass through this will
1233 * be expected to be non-zero
1235 ret = vendor_mac_passthru_addr_read(tp, &sa);
1237 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
1241 netif_err(tp, probe, dev, "Get ether addr fail\n");
1242 } else if (!is_valid_ether_addr(sa.sa_data)) {
1243 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1245 eth_hw_addr_random(dev);
1246 ether_addr_copy(sa.sa_data, dev->dev_addr);
1247 ret = rtl8152_set_mac_address(dev, &sa);
1248 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1251 if (tp->version == RTL_VER_01)
1252 ether_addr_copy(dev->dev_addr, sa.sa_data);
1254 ret = rtl8152_set_mac_address(dev, &sa);
1260 static void read_bulk_callback(struct urb *urb)
1262 struct net_device *netdev;
1263 int status = urb->status;
1266 unsigned long flags;
1276 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1279 if (!test_bit(WORK_ENABLE, &tp->flags))
1282 netdev = tp->netdev;
1284 /* When link down, the driver would cancel all bulks. */
1285 /* This avoid the re-submitting bulk */
1286 if (!netif_carrier_ok(netdev))
1289 usb_mark_last_busy(tp->udev);
1293 if (urb->actual_length < ETH_ZLEN)
1296 spin_lock_irqsave(&tp->rx_lock, flags);
1297 list_add_tail(&agg->list, &tp->rx_done);
1298 spin_unlock_irqrestore(&tp->rx_lock, flags);
1299 napi_schedule(&tp->napi);
1302 set_bit(RTL8152_UNPLUG, &tp->flags);
1303 netif_device_detach(tp->netdev);
1306 return; /* the urb is in unlink state */
1308 if (net_ratelimit())
1309 netdev_warn(netdev, "maybe reset is needed?\n");
1312 if (net_ratelimit())
1313 netdev_warn(netdev, "Rx status %d\n", status);
1317 r8152_submit_rx(tp, agg, GFP_ATOMIC);
1320 static void write_bulk_callback(struct urb *urb)
1322 struct net_device_stats *stats;
1323 struct net_device *netdev;
1326 unsigned long flags;
1327 int status = urb->status;
1337 netdev = tp->netdev;
1338 stats = &netdev->stats;
1340 if (net_ratelimit())
1341 netdev_warn(netdev, "Tx status %d\n", status);
1342 stats->tx_errors += agg->skb_num;
1344 stats->tx_packets += agg->skb_num;
1345 stats->tx_bytes += agg->skb_len;
1348 spin_lock_irqsave(&tp->tx_lock, flags);
1349 list_add_tail(&agg->list, &tp->tx_free);
1350 spin_unlock_irqrestore(&tp->tx_lock, flags);
1352 usb_autopm_put_interface_async(tp->intf);
1354 if (!netif_carrier_ok(netdev))
1357 if (!test_bit(WORK_ENABLE, &tp->flags))
1360 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1363 if (!skb_queue_empty(&tp->tx_queue))
1364 napi_schedule(&tp->napi);
1367 static void intr_callback(struct urb *urb)
1371 int status = urb->status;
1378 if (!test_bit(WORK_ENABLE, &tp->flags))
1381 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1385 case 0: /* success */
1387 case -ECONNRESET: /* unlink */
1389 netif_device_detach(tp->netdev);
1393 netif_info(tp, intr, tp->netdev,
1394 "Stop submitting intr, status %d\n", status);
1397 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1399 /* -EPIPE: should clear the halt */
1401 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1405 d = urb->transfer_buffer;
1406 if (INTR_LINK & __le16_to_cpu(d[0])) {
1407 if (!netif_carrier_ok(tp->netdev)) {
1408 set_bit(RTL8152_LINK_CHG, &tp->flags);
1409 schedule_delayed_work(&tp->schedule, 0);
1412 if (netif_carrier_ok(tp->netdev)) {
1413 netif_stop_queue(tp->netdev);
1414 set_bit(RTL8152_LINK_CHG, &tp->flags);
1415 schedule_delayed_work(&tp->schedule, 0);
1420 res = usb_submit_urb(urb, GFP_ATOMIC);
1421 if (res == -ENODEV) {
1422 set_bit(RTL8152_UNPLUG, &tp->flags);
1423 netif_device_detach(tp->netdev);
1425 netif_err(tp, intr, tp->netdev,
1426 "can't resubmit intr, status %d\n", res);
1430 static inline void *rx_agg_align(void *data)
1432 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1435 static inline void *tx_agg_align(void *data)
1437 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1440 static void free_all_mem(struct r8152 *tp)
1444 for (i = 0; i < RTL8152_MAX_RX; i++) {
1445 usb_free_urb(tp->rx_info[i].urb);
1446 tp->rx_info[i].urb = NULL;
1448 kfree(tp->rx_info[i].buffer);
1449 tp->rx_info[i].buffer = NULL;
1450 tp->rx_info[i].head = NULL;
1453 for (i = 0; i < RTL8152_MAX_TX; i++) {
1454 usb_free_urb(tp->tx_info[i].urb);
1455 tp->tx_info[i].urb = NULL;
1457 kfree(tp->tx_info[i].buffer);
1458 tp->tx_info[i].buffer = NULL;
1459 tp->tx_info[i].head = NULL;
1462 usb_free_urb(tp->intr_urb);
1463 tp->intr_urb = NULL;
1465 kfree(tp->intr_buff);
1466 tp->intr_buff = NULL;
1469 static int alloc_all_mem(struct r8152 *tp)
1471 struct net_device *netdev = tp->netdev;
1472 struct usb_interface *intf = tp->intf;
1473 struct usb_host_interface *alt = intf->cur_altsetting;
1474 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1479 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1481 spin_lock_init(&tp->rx_lock);
1482 spin_lock_init(&tp->tx_lock);
1483 INIT_LIST_HEAD(&tp->tx_free);
1484 INIT_LIST_HEAD(&tp->rx_done);
1485 skb_queue_head_init(&tp->tx_queue);
1486 skb_queue_head_init(&tp->rx_queue);
1488 for (i = 0; i < RTL8152_MAX_RX; i++) {
1489 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1493 if (buf != rx_agg_align(buf)) {
1495 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
1501 urb = usb_alloc_urb(0, GFP_KERNEL);
1507 INIT_LIST_HEAD(&tp->rx_info[i].list);
1508 tp->rx_info[i].context = tp;
1509 tp->rx_info[i].urb = urb;
1510 tp->rx_info[i].buffer = buf;
1511 tp->rx_info[i].head = rx_agg_align(buf);
1514 for (i = 0; i < RTL8152_MAX_TX; i++) {
1515 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1519 if (buf != tx_agg_align(buf)) {
1521 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1527 urb = usb_alloc_urb(0, GFP_KERNEL);
1533 INIT_LIST_HEAD(&tp->tx_info[i].list);
1534 tp->tx_info[i].context = tp;
1535 tp->tx_info[i].urb = urb;
1536 tp->tx_info[i].buffer = buf;
1537 tp->tx_info[i].head = tx_agg_align(buf);
1539 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1542 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1546 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1550 tp->intr_interval = (int)ep_intr->desc.bInterval;
1551 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1552 tp->intr_buff, INTBUFSIZE, intr_callback,
1553 tp, tp->intr_interval);
1562 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1564 struct tx_agg *agg = NULL;
1565 unsigned long flags;
1567 if (list_empty(&tp->tx_free))
1570 spin_lock_irqsave(&tp->tx_lock, flags);
1571 if (!list_empty(&tp->tx_free)) {
1572 struct list_head *cursor;
1574 cursor = tp->tx_free.next;
1575 list_del_init(cursor);
1576 agg = list_entry(cursor, struct tx_agg, list);
1578 spin_unlock_irqrestore(&tp->tx_lock, flags);
1583 /* r8152_csum_workaround()
1584 * The hw limites the value the transport offset. When the offset is out of the
1585 * range, calculate the checksum by sw.
1587 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1588 struct sk_buff_head *list)
1590 if (skb_shinfo(skb)->gso_size) {
1591 netdev_features_t features = tp->netdev->features;
1592 struct sk_buff_head seg_list;
1593 struct sk_buff *segs, *nskb;
1595 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1596 segs = skb_gso_segment(skb, features);
1597 if (IS_ERR(segs) || !segs)
1600 __skb_queue_head_init(&seg_list);
1606 __skb_queue_tail(&seg_list, nskb);
1609 skb_queue_splice(&seg_list, list);
1611 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1612 if (skb_checksum_help(skb) < 0)
1615 __skb_queue_head(list, skb);
1617 struct net_device_stats *stats;
1620 stats = &tp->netdev->stats;
1621 stats->tx_dropped++;
1626 /* msdn_giant_send_check()
1627 * According to the document of microsoft, the TCP Pseudo Header excludes the
1628 * packet length for IPv6 TCP large packets.
1630 static int msdn_giant_send_check(struct sk_buff *skb)
1632 const struct ipv6hdr *ipv6h;
1636 ret = skb_cow_head(skb, 0);
1640 ipv6h = ipv6_hdr(skb);
1644 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1649 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1651 if (skb_vlan_tag_present(skb)) {
1654 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
1655 desc->opts2 |= cpu_to_le32(opts2);
1659 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1661 u32 opts2 = le32_to_cpu(desc->opts2);
1663 if (opts2 & RX_VLAN_TAG)
1664 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1665 swab16(opts2 & 0xffff));
1668 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1669 struct sk_buff *skb, u32 len, u32 transport_offset)
1671 u32 mss = skb_shinfo(skb)->gso_size;
1672 u32 opts1, opts2 = 0;
1673 int ret = TX_CSUM_SUCCESS;
1675 WARN_ON_ONCE(len > TX_LEN_MAX);
1677 opts1 = len | TX_FS | TX_LS;
1680 if (transport_offset > GTTCPHO_MAX) {
1681 netif_warn(tp, tx_err, tp->netdev,
1682 "Invalid transport offset 0x%x for TSO\n",
1688 switch (vlan_get_protocol(skb)) {
1689 case htons(ETH_P_IP):
1693 case htons(ETH_P_IPV6):
1694 if (msdn_giant_send_check(skb)) {
1706 opts1 |= transport_offset << GTTCPHO_SHIFT;
1707 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1708 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1711 if (transport_offset > TCPHO_MAX) {
1712 netif_warn(tp, tx_err, tp->netdev,
1713 "Invalid transport offset 0x%x\n",
1719 switch (vlan_get_protocol(skb)) {
1720 case htons(ETH_P_IP):
1722 ip_protocol = ip_hdr(skb)->protocol;
1725 case htons(ETH_P_IPV6):
1727 ip_protocol = ipv6_hdr(skb)->nexthdr;
1731 ip_protocol = IPPROTO_RAW;
1735 if (ip_protocol == IPPROTO_TCP)
1737 else if (ip_protocol == IPPROTO_UDP)
1742 opts2 |= transport_offset << TCPHO_SHIFT;
1745 desc->opts2 = cpu_to_le32(opts2);
1746 desc->opts1 = cpu_to_le32(opts1);
1752 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1754 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1758 __skb_queue_head_init(&skb_head);
1759 spin_lock(&tx_queue->lock);
1760 skb_queue_splice_init(tx_queue, &skb_head);
1761 spin_unlock(&tx_queue->lock);
1763 tx_data = agg->head;
1766 remain = agg_buf_sz;
1768 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
1769 struct tx_desc *tx_desc;
1770 struct sk_buff *skb;
1774 skb = __skb_dequeue(&skb_head);
1778 len = skb->len + sizeof(*tx_desc);
1781 __skb_queue_head(&skb_head, skb);
1785 tx_data = tx_agg_align(tx_data);
1786 tx_desc = (struct tx_desc *)tx_data;
1788 offset = (u32)skb_transport_offset(skb);
1790 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1791 r8152_csum_workaround(tp, skb, &skb_head);
1795 rtl_tx_vlan_tag(tx_desc, skb);
1797 tx_data += sizeof(*tx_desc);
1800 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1801 struct net_device_stats *stats = &tp->netdev->stats;
1803 stats->tx_dropped++;
1804 dev_kfree_skb_any(skb);
1805 tx_data -= sizeof(*tx_desc);
1810 agg->skb_len += len;
1811 agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
1813 dev_kfree_skb_any(skb);
1815 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
1817 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
1821 if (!skb_queue_empty(&skb_head)) {
1822 spin_lock(&tx_queue->lock);
1823 skb_queue_splice(&skb_head, tx_queue);
1824 spin_unlock(&tx_queue->lock);
1827 netif_tx_lock(tp->netdev);
1829 if (netif_queue_stopped(tp->netdev) &&
1830 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1831 netif_wake_queue(tp->netdev);
1833 netif_tx_unlock(tp->netdev);
1835 ret = usb_autopm_get_interface_async(tp->intf);
1839 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1840 agg->head, (int)(tx_data - (u8 *)agg->head),
1841 (usb_complete_t)write_bulk_callback, agg);
1843 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
1845 usb_autopm_put_interface_async(tp->intf);
1851 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1853 u8 checksum = CHECKSUM_NONE;
1856 if (!(tp->netdev->features & NETIF_F_RXCSUM))
1859 opts2 = le32_to_cpu(rx_desc->opts2);
1860 opts3 = le32_to_cpu(rx_desc->opts3);
1862 if (opts2 & RD_IPV4_CS) {
1864 checksum = CHECKSUM_NONE;
1865 else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1866 checksum = CHECKSUM_UNNECESSARY;
1867 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1868 checksum = CHECKSUM_UNNECESSARY;
1869 } else if (opts2 & RD_IPV6_CS) {
1870 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1871 checksum = CHECKSUM_UNNECESSARY;
1872 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1873 checksum = CHECKSUM_UNNECESSARY;
1880 static int rx_bottom(struct r8152 *tp, int budget)
1882 unsigned long flags;
1883 struct list_head *cursor, *next, rx_queue;
1884 int ret = 0, work_done = 0;
1885 struct napi_struct *napi = &tp->napi;
1887 if (!skb_queue_empty(&tp->rx_queue)) {
1888 while (work_done < budget) {
1889 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
1890 struct net_device *netdev = tp->netdev;
1891 struct net_device_stats *stats = &netdev->stats;
1892 unsigned int pkt_len;
1898 napi_gro_receive(napi, skb);
1900 stats->rx_packets++;
1901 stats->rx_bytes += pkt_len;
1905 if (list_empty(&tp->rx_done))
1908 INIT_LIST_HEAD(&rx_queue);
1909 spin_lock_irqsave(&tp->rx_lock, flags);
1910 list_splice_init(&tp->rx_done, &rx_queue);
1911 spin_unlock_irqrestore(&tp->rx_lock, flags);
1913 list_for_each_safe(cursor, next, &rx_queue) {
1914 struct rx_desc *rx_desc;
1920 list_del_init(cursor);
1922 agg = list_entry(cursor, struct rx_agg, list);
1924 if (urb->actual_length < ETH_ZLEN)
1927 rx_desc = agg->head;
1928 rx_data = agg->head;
1929 len_used += sizeof(struct rx_desc);
1931 while (urb->actual_length > len_used) {
1932 struct net_device *netdev = tp->netdev;
1933 struct net_device_stats *stats = &netdev->stats;
1934 unsigned int pkt_len;
1935 struct sk_buff *skb;
1937 /* limite the skb numbers for rx_queue */
1938 if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
1941 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1942 if (pkt_len < ETH_ZLEN)
1945 len_used += pkt_len;
1946 if (urb->actual_length < len_used)
1949 pkt_len -= ETH_FCS_LEN;
1950 rx_data += sizeof(struct rx_desc);
1952 skb = napi_alloc_skb(napi, pkt_len);
1954 stats->rx_dropped++;
1958 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
1959 memcpy(skb->data, rx_data, pkt_len);
1960 skb_put(skb, pkt_len);
1961 skb->protocol = eth_type_trans(skb, netdev);
1962 rtl_rx_vlan_tag(rx_desc, skb);
1963 if (work_done < budget) {
1964 napi_gro_receive(napi, skb);
1966 stats->rx_packets++;
1967 stats->rx_bytes += pkt_len;
1969 __skb_queue_tail(&tp->rx_queue, skb);
1973 rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN);
1974 rx_desc = (struct rx_desc *)rx_data;
1975 len_used = (int)(rx_data - (u8 *)agg->head);
1976 len_used += sizeof(struct rx_desc);
1981 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1983 urb->actual_length = 0;
1984 list_add_tail(&agg->list, next);
1988 if (!list_empty(&rx_queue)) {
1989 spin_lock_irqsave(&tp->rx_lock, flags);
1990 list_splice_tail(&rx_queue, &tp->rx_done);
1991 spin_unlock_irqrestore(&tp->rx_lock, flags);
1998 static void tx_bottom(struct r8152 *tp)
2005 if (skb_queue_empty(&tp->tx_queue))
2008 agg = r8152_get_tx_agg(tp);
2012 res = r8152_tx_agg_fill(tp, agg);
2014 struct net_device *netdev = tp->netdev;
2016 if (res == -ENODEV) {
2017 set_bit(RTL8152_UNPLUG, &tp->flags);
2018 netif_device_detach(netdev);
2020 struct net_device_stats *stats = &netdev->stats;
2021 unsigned long flags;
2023 netif_warn(tp, tx_err, netdev,
2024 "failed tx_urb %d\n", res);
2025 stats->tx_dropped += agg->skb_num;
2027 spin_lock_irqsave(&tp->tx_lock, flags);
2028 list_add_tail(&agg->list, &tp->tx_free);
2029 spin_unlock_irqrestore(&tp->tx_lock, flags);
2035 static void bottom_half(struct r8152 *tp)
2037 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2040 if (!test_bit(WORK_ENABLE, &tp->flags))
2043 /* When link down, the driver would cancel all bulks. */
2044 /* This avoid the re-submitting bulk */
2045 if (!netif_carrier_ok(tp->netdev))
2048 clear_bit(SCHEDULE_NAPI, &tp->flags);
2053 static int r8152_poll(struct napi_struct *napi, int budget)
2055 struct r8152 *tp = container_of(napi, struct r8152, napi);
2058 work_done = rx_bottom(tp, budget);
2061 if (work_done < budget) {
2062 if (!napi_complete_done(napi, work_done))
2064 if (!list_empty(&tp->rx_done))
2065 napi_schedule(napi);
2066 else if (!skb_queue_empty(&tp->tx_queue) &&
2067 !list_empty(&tp->tx_free))
2068 napi_schedule(napi);
2076 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
2080 /* The rx would be stopped, so skip submitting */
2081 if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
2082 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
2085 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
2086 agg->head, agg_buf_sz,
2087 (usb_complete_t)read_bulk_callback, agg);
2089 ret = usb_submit_urb(agg->urb, mem_flags);
2090 if (ret == -ENODEV) {
2091 set_bit(RTL8152_UNPLUG, &tp->flags);
2092 netif_device_detach(tp->netdev);
2094 struct urb *urb = agg->urb;
2095 unsigned long flags;
2097 urb->actual_length = 0;
2098 spin_lock_irqsave(&tp->rx_lock, flags);
2099 list_add_tail(&agg->list, &tp->rx_done);
2100 spin_unlock_irqrestore(&tp->rx_lock, flags);
2102 netif_err(tp, rx_err, tp->netdev,
2103 "Couldn't submit rx[%p], ret = %d\n", agg, ret);
2105 napi_schedule(&tp->napi);
2111 static void rtl_drop_queued_tx(struct r8152 *tp)
2113 struct net_device_stats *stats = &tp->netdev->stats;
2114 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2115 struct sk_buff *skb;
2117 if (skb_queue_empty(tx_queue))
2120 __skb_queue_head_init(&skb_head);
2121 spin_lock_bh(&tx_queue->lock);
2122 skb_queue_splice_init(tx_queue, &skb_head);
2123 spin_unlock_bh(&tx_queue->lock);
2125 while ((skb = __skb_dequeue(&skb_head))) {
2127 stats->tx_dropped++;
2131 static void rtl8152_tx_timeout(struct net_device *netdev)
2133 struct r8152 *tp = netdev_priv(netdev);
2135 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
2137 usb_queue_reset_device(tp->intf);
2140 static void rtl8152_set_rx_mode(struct net_device *netdev)
2142 struct r8152 *tp = netdev_priv(netdev);
2144 if (netif_carrier_ok(netdev)) {
2145 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2146 schedule_delayed_work(&tp->schedule, 0);
2150 static void _rtl8152_set_rx_mode(struct net_device *netdev)
2152 struct r8152 *tp = netdev_priv(netdev);
2153 u32 mc_filter[2]; /* Multicast hash filter */
2157 netif_stop_queue(netdev);
2158 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2159 ocp_data &= ~RCR_ACPT_ALL;
2160 ocp_data |= RCR_AB | RCR_APM;
2162 if (netdev->flags & IFF_PROMISC) {
2163 /* Unconditionally log net taps. */
2164 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2165 ocp_data |= RCR_AM | RCR_AAP;
2166 mc_filter[1] = 0xffffffff;
2167 mc_filter[0] = 0xffffffff;
2168 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
2169 (netdev->flags & IFF_ALLMULTI)) {
2170 /* Too many to filter perfectly -- accept all multicasts. */
2172 mc_filter[1] = 0xffffffff;
2173 mc_filter[0] = 0xffffffff;
2175 struct netdev_hw_addr *ha;
2179 netdev_for_each_mc_addr(ha, netdev) {
2180 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2182 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2187 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2188 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2190 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
2191 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2192 netif_wake_queue(netdev);
2195 static netdev_features_t
2196 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2197 netdev_features_t features)
2199 u32 mss = skb_shinfo(skb)->gso_size;
2200 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2201 int offset = skb_transport_offset(skb);
2203 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
2204 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2205 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2206 features &= ~NETIF_F_GSO_MASK;
2211 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2212 struct net_device *netdev)
2214 struct r8152 *tp = netdev_priv(netdev);
2216 skb_tx_timestamp(skb);
2218 skb_queue_tail(&tp->tx_queue, skb);
2220 if (!list_empty(&tp->tx_free)) {
2221 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2222 set_bit(SCHEDULE_NAPI, &tp->flags);
2223 schedule_delayed_work(&tp->schedule, 0);
2225 usb_mark_last_busy(tp->udev);
2226 napi_schedule(&tp->napi);
2228 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2229 netif_stop_queue(netdev);
2232 return NETDEV_TX_OK;
2235 static void r8152b_reset_packet_filter(struct r8152 *tp)
2239 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2240 ocp_data &= ~FMC_FCR_MCU_EN;
2241 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2242 ocp_data |= FMC_FCR_MCU_EN;
2243 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2246 static void rtl8152_nic_reset(struct r8152 *tp)
2250 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2252 for (i = 0; i < 1000; i++) {
2253 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2255 usleep_range(100, 400);
2259 static void set_tx_qlen(struct r8152 *tp)
2261 struct net_device *netdev = tp->netdev;
2263 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN +
2264 sizeof(struct tx_desc));
2267 static inline u8 rtl8152_get_speed(struct r8152 *tp)
2269 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2272 static void rtl_set_eee_plus(struct r8152 *tp)
2277 speed = rtl8152_get_speed(tp);
2278 if (speed & _10bps) {
2279 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2280 ocp_data |= EEEP_CR_EEEP_TX;
2281 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2283 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2284 ocp_data &= ~EEEP_CR_EEEP_TX;
2285 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2289 static void rxdy_gated_en(struct r8152 *tp, bool enable)
2293 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2295 ocp_data |= RXDY_GATED_EN;
2297 ocp_data &= ~RXDY_GATED_EN;
2298 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2301 static int rtl_start_rx(struct r8152 *tp)
2305 INIT_LIST_HEAD(&tp->rx_done);
2306 for (i = 0; i < RTL8152_MAX_RX; i++) {
2307 INIT_LIST_HEAD(&tp->rx_info[i].list);
2308 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
2313 if (ret && ++i < RTL8152_MAX_RX) {
2314 struct list_head rx_queue;
2315 unsigned long flags;
2317 INIT_LIST_HEAD(&rx_queue);
2320 struct rx_agg *agg = &tp->rx_info[i++];
2321 struct urb *urb = agg->urb;
2323 urb->actual_length = 0;
2324 list_add_tail(&agg->list, &rx_queue);
2325 } while (i < RTL8152_MAX_RX);
2327 spin_lock_irqsave(&tp->rx_lock, flags);
2328 list_splice_tail(&rx_queue, &tp->rx_done);
2329 spin_unlock_irqrestore(&tp->rx_lock, flags);
2335 static int rtl_stop_rx(struct r8152 *tp)
2339 for (i = 0; i < RTL8152_MAX_RX; i++)
2340 usb_kill_urb(tp->rx_info[i].urb);
2342 while (!skb_queue_empty(&tp->rx_queue))
2343 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2348 static int rtl_enable(struct r8152 *tp)
2352 r8152b_reset_packet_filter(tp);
2354 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2355 ocp_data |= CR_RE | CR_TE;
2356 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2358 rxdy_gated_en(tp, false);
2363 static int rtl8152_enable(struct r8152 *tp)
2365 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2369 rtl_set_eee_plus(tp);
2371 return rtl_enable(tp);
2374 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
2376 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
2377 OWN_UPDATE | OWN_CLEAR);
2380 static void r8153_set_rx_early_timeout(struct r8152 *tp)
2382 u32 ocp_data = tp->coalesce / 8;
2384 switch (tp->version) {
2389 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2395 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
2396 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
2398 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2400 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
2402 r8153b_rx_agg_chg_indicate(tp);
2410 static void r8153_set_rx_early_size(struct r8152 *tp)
2412 u32 ocp_data = agg_buf_sz - rx_reserved_size(tp->netdev->mtu);
2414 switch (tp->version) {
2419 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2424 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2426 r8153b_rx_agg_chg_indicate(tp);
2434 static int rtl8153_enable(struct r8152 *tp)
2436 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2440 rtl_set_eee_plus(tp);
2441 r8153_set_rx_early_timeout(tp);
2442 r8153_set_rx_early_size(tp);
2444 return rtl_enable(tp);
2447 static void rtl_disable(struct r8152 *tp)
2452 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2453 rtl_drop_queued_tx(tp);
2457 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2458 ocp_data &= ~RCR_ACPT_ALL;
2459 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2461 rtl_drop_queued_tx(tp);
2463 for (i = 0; i < RTL8152_MAX_TX; i++)
2464 usb_kill_urb(tp->tx_info[i].urb);
2466 rxdy_gated_en(tp, true);
2468 for (i = 0; i < 1000; i++) {
2469 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2470 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2472 usleep_range(1000, 2000);
2475 for (i = 0; i < 1000; i++) {
2476 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2478 usleep_range(1000, 2000);
2483 rtl8152_nic_reset(tp);
2486 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2490 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2492 ocp_data |= POWER_CUT;
2494 ocp_data &= ~POWER_CUT;
2495 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2497 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2498 ocp_data &= ~RESUME_INDICATE;
2499 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2502 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2506 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2508 ocp_data |= CPCR_RX_VLAN;
2510 ocp_data &= ~CPCR_RX_VLAN;
2511 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2514 static int rtl8152_set_features(struct net_device *dev,
2515 netdev_features_t features)
2517 netdev_features_t changed = features ^ dev->features;
2518 struct r8152 *tp = netdev_priv(dev);
2521 ret = usb_autopm_get_interface(tp->intf);
2525 mutex_lock(&tp->control);
2527 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2528 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2529 rtl_rx_vlan_en(tp, true);
2531 rtl_rx_vlan_en(tp, false);
2534 mutex_unlock(&tp->control);
2536 usb_autopm_put_interface(tp->intf);
2542 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2544 static u32 __rtl_get_wol(struct r8152 *tp)
2549 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2550 if (ocp_data & LINK_ON_WAKE_EN)
2551 wolopts |= WAKE_PHY;
2553 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2554 if (ocp_data & UWF_EN)
2555 wolopts |= WAKE_UCAST;
2556 if (ocp_data & BWF_EN)
2557 wolopts |= WAKE_BCAST;
2558 if (ocp_data & MWF_EN)
2559 wolopts |= WAKE_MCAST;
2561 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2562 if (ocp_data & MAGIC_EN)
2563 wolopts |= WAKE_MAGIC;
2568 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2572 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2574 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2575 ocp_data &= ~LINK_ON_WAKE_EN;
2576 if (wolopts & WAKE_PHY)
2577 ocp_data |= LINK_ON_WAKE_EN;
2578 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2580 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2581 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
2582 if (wolopts & WAKE_UCAST)
2584 if (wolopts & WAKE_BCAST)
2586 if (wolopts & WAKE_MCAST)
2588 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2590 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2592 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2593 ocp_data &= ~MAGIC_EN;
2594 if (wolopts & WAKE_MAGIC)
2595 ocp_data |= MAGIC_EN;
2596 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2598 if (wolopts & WAKE_ANY)
2599 device_set_wakeup_enable(&tp->udev->dev, true);
2601 device_set_wakeup_enable(&tp->udev->dev, false);
2604 static void r8153_mac_clk_spd(struct r8152 *tp, bool enable)
2606 /* MAC clock speed down */
2608 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL,
2610 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2,
2612 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
2613 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
2614 U1U2_SPDWN_EN | L1_SPDWN_EN);
2615 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
2616 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
2617 TP100_SPDWN_EN | TP500_SPDWN_EN | EEE_SPDWN_EN |
2620 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0);
2621 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0);
2622 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);
2623 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);
2627 static void r8153_u1u2en(struct r8152 *tp, bool enable)
2632 memset(u1u2, 0xff, sizeof(u1u2));
2634 memset(u1u2, 0x00, sizeof(u1u2));
2636 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2639 static void r8153b_u1u2en(struct r8152 *tp, bool enable)
2643 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
2645 ocp_data |= LPM_U1U2_EN;
2647 ocp_data &= ~LPM_U1U2_EN;
2649 ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
2652 static void r8153_u2p3en(struct r8152 *tp, bool enable)
2656 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2658 ocp_data |= U2P3_ENABLE;
2660 ocp_data &= ~U2P3_ENABLE;
2661 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2664 static void r8153b_ups_flags_w1w0(struct r8152 *tp, u32 set, u32 clear)
2668 ocp_data = ocp_read_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS);
2671 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ocp_data);
2674 static void r8153b_green_en(struct r8152 *tp, bool enable)
2679 sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */
2680 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */
2681 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */
2683 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */
2684 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */
2685 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */
2688 data = sram_read(tp, SRAM_GREEN_CFG);
2689 data |= GREEN_ETH_EN;
2690 sram_write(tp, SRAM_GREEN_CFG, data);
2692 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_GREEN, 0);
2695 static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
2700 for (i = 0; i < 500; i++) {
2701 data = ocp_reg_read(tp, OCP_PHY_STATUS);
2702 data &= PHY_STAT_MASK;
2704 if (data == desired)
2706 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
2707 data == PHY_STAT_EXT_INIT) {
2717 static void r8153b_ups_en(struct r8152 *tp, bool enable)
2719 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
2722 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
2723 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2725 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
2727 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
2731 ocp_data &= ~(UPS_EN | USP_PREWAKE);
2732 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2734 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
2735 ocp_data &= ~BIT(0);
2736 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
2738 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2739 ocp_data &= ~PCUT_STATUS;
2740 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2742 data = r8153_phy_status(tp, 0);
2745 case PHY_STAT_PWRDN:
2746 case PHY_STAT_EXT_INIT:
2748 test_bit(GREEN_ETHERNET, &tp->flags));
2750 data = r8152_mdio_read(tp, MII_BMCR);
2751 data &= ~BMCR_PDOWN;
2753 r8152_mdio_write(tp, MII_BMCR, data);
2755 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
2759 if (data != PHY_STAT_LAN_ON)
2760 netif_warn(tp, link, tp->netdev,
2767 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
2771 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2773 ocp_data |= PWR_EN | PHASE2_EN;
2775 ocp_data &= ~(PWR_EN | PHASE2_EN);
2776 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2778 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2779 ocp_data &= ~PCUT_STATUS;
2780 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2783 static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
2787 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2789 ocp_data |= PWR_EN | PHASE2_EN;
2791 ocp_data &= ~PWR_EN;
2792 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2794 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2795 ocp_data &= ~PCUT_STATUS;
2796 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2799 static void r8153b_queue_wake(struct r8152 *tp, bool enable)
2803 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 0xd38a);
2807 ocp_data &= ~BIT(0);
2808 ocp_write_byte(tp, MCU_TYPE_PLA, 0xd38a, ocp_data);
2810 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 0xd38c);
2811 ocp_data &= ~BIT(0);
2812 ocp_write_byte(tp, MCU_TYPE_PLA, 0xd38c, ocp_data);
2815 static bool rtl_can_wakeup(struct r8152 *tp)
2817 struct usb_device *udev = tp->udev;
2819 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
2822 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2827 __rtl_set_wol(tp, WAKE_ANY);
2829 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2831 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2832 ocp_data |= LINK_OFF_WAKE_EN;
2833 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2835 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2839 __rtl_set_wol(tp, tp->saved_wolopts);
2841 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2843 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2844 ocp_data &= ~LINK_OFF_WAKE_EN;
2845 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2847 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2851 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
2854 r8153_u1u2en(tp, false);
2855 r8153_u2p3en(tp, false);
2856 r8153_mac_clk_spd(tp, true);
2857 rtl_runtime_suspend_enable(tp, true);
2859 rtl_runtime_suspend_enable(tp, false);
2860 r8153_mac_clk_spd(tp, false);
2862 switch (tp->version) {
2869 r8153_u2p3en(tp, true);
2873 r8153_u1u2en(tp, true);
2877 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
2880 r8153b_queue_wake(tp, true);
2881 r8153b_u1u2en(tp, false);
2882 r8153_u2p3en(tp, false);
2883 rtl_runtime_suspend_enable(tp, true);
2884 r8153b_ups_en(tp, true);
2886 r8153b_ups_en(tp, false);
2887 r8153b_queue_wake(tp, false);
2888 rtl_runtime_suspend_enable(tp, false);
2889 r8153_u2p3en(tp, true);
2890 r8153b_u1u2en(tp, true);
2894 static void r8153_teredo_off(struct r8152 *tp)
2898 switch (tp->version) {
2906 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2907 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
2909 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2914 /* The bit 0 ~ 7 are relative with teredo settings. They are
2915 * W1C (write 1 to clear), so set all 1 to disable it.
2917 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
2924 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2925 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2926 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2929 static void rtl_reset_bmu(struct r8152 *tp)
2933 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
2934 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
2935 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2936 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
2937 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2940 static void r8152_aldps_en(struct r8152 *tp, bool enable)
2943 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2944 LINKENA | DIS_SDSAVE);
2946 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
2952 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
2954 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
2955 ocp_reg_write(tp, OCP_EEE_DATA, reg);
2956 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
2959 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
2963 r8152_mmd_indirect(tp, dev, reg);
2964 data = ocp_reg_read(tp, OCP_EEE_DATA);
2965 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2970 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
2972 r8152_mmd_indirect(tp, dev, reg);
2973 ocp_reg_write(tp, OCP_EEE_DATA, data);
2974 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2977 static void r8152_eee_en(struct r8152 *tp, bool enable)
2979 u16 config1, config2, config3;
2982 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
2983 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
2984 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
2985 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
2988 ocp_data |= EEE_RX_EN | EEE_TX_EN;
2989 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
2990 config1 |= sd_rise_time(1);
2991 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
2992 config3 |= fast_snr(42);
2994 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
2995 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
2997 config1 |= sd_rise_time(7);
2998 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
2999 config3 |= fast_snr(511);
3002 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3003 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
3004 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
3005 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
3008 static void r8152b_enable_eee(struct r8152 *tp)
3010 r8152_eee_en(tp, true);
3011 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
3014 static void r8152b_enable_fc(struct r8152 *tp)
3018 anar = r8152_mdio_read(tp, MII_ADVERTISE);
3019 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3020 r8152_mdio_write(tp, MII_ADVERTISE, anar);
3023 static void rtl8152_disable(struct r8152 *tp)
3025 r8152_aldps_en(tp, false);
3027 r8152_aldps_en(tp, true);
3030 static void r8152b_hw_phy_cfg(struct r8152 *tp)
3032 r8152b_enable_eee(tp);
3033 r8152_aldps_en(tp, true);
3034 r8152b_enable_fc(tp);
3036 set_bit(PHY_RESET, &tp->flags);
3039 static void r8152b_exit_oob(struct r8152 *tp)
3044 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3045 ocp_data &= ~RCR_ACPT_ALL;
3046 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3048 rxdy_gated_en(tp, true);
3049 r8153_teredo_off(tp);
3050 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3051 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
3053 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3054 ocp_data &= ~NOW_IS_OOB;
3055 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3057 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3058 ocp_data &= ~MCU_BORW_EN;
3059 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3061 for (i = 0; i < 1000; i++) {
3062 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3063 if (ocp_data & LINK_LIST_READY)
3065 usleep_range(1000, 2000);
3068 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3069 ocp_data |= RE_INIT_LL;
3070 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3072 for (i = 0; i < 1000; i++) {
3073 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3074 if (ocp_data & LINK_LIST_READY)
3076 usleep_range(1000, 2000);
3079 rtl8152_nic_reset(tp);
3081 /* rx share fifo credit full threshold */
3082 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
3084 if (tp->udev->speed == USB_SPEED_FULL ||
3085 tp->udev->speed == USB_SPEED_LOW) {
3086 /* rx share fifo credit near full threshold */
3087 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
3089 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
3092 /* rx share fifo credit near full threshold */
3093 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
3095 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
3099 /* TX share fifo free credit full threshold */
3100 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
3102 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
3103 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
3104 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
3105 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
3107 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
3109 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
3111 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
3112 ocp_data |= TCR0_AUTO_FIFO;
3113 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
3116 static void r8152b_enter_oob(struct r8152 *tp)
3121 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3122 ocp_data &= ~NOW_IS_OOB;
3123 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3125 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
3126 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
3127 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
3131 for (i = 0; i < 1000; i++) {
3132 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3133 if (ocp_data & LINK_LIST_READY)
3135 usleep_range(1000, 2000);
3138 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3139 ocp_data |= RE_INIT_LL;
3140 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3142 for (i = 0; i < 1000; i++) {
3143 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3144 if (ocp_data & LINK_LIST_READY)
3146 usleep_range(1000, 2000);
3149 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
3151 rtl_rx_vlan_en(tp, true);
3153 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
3154 ocp_data |= ALDPS_PROXY_MODE;
3155 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
3157 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3158 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
3159 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3161 rxdy_gated_en(tp, false);
3163 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3164 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
3165 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3168 static int r8153_patch_request(struct r8152 *tp, bool request)
3173 data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
3175 data |= PATCH_REQUEST;
3177 data &= ~PATCH_REQUEST;
3178 ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
3180 for (i = 0; request && i < 5000; i++) {
3181 usleep_range(1000, 2000);
3182 if (ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)
3186 if (request && !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
3187 netif_err(tp, drv, tp->netdev, "patch request fail\n");
3188 r8153_patch_request(tp, false);
3195 static void r8153_aldps_en(struct r8152 *tp, bool enable)
3199 data = ocp_reg_read(tp, OCP_POWER_CFG);
3202 ocp_reg_write(tp, OCP_POWER_CFG, data);
3207 ocp_reg_write(tp, OCP_POWER_CFG, data);
3208 for (i = 0; i < 20; i++) {
3209 usleep_range(1000, 2000);
3210 if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
3216 static void r8153b_aldps_en(struct r8152 *tp, bool enable)
3218 r8153_aldps_en(tp, enable);
3221 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_ALDPS, 0);
3223 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_ALDPS);
3226 static void r8153_eee_en(struct r8152 *tp, bool enable)
3231 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3232 config = ocp_reg_read(tp, OCP_EEE_CFG);
3235 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3238 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3239 config &= ~EEE10_EN;
3242 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3243 ocp_reg_write(tp, OCP_EEE_CFG, config);
3246 static void r8153b_eee_en(struct r8152 *tp, bool enable)
3248 r8153_eee_en(tp, enable);
3251 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_EEE, 0);
3253 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_EEE);
3256 static void r8153b_enable_fc(struct r8152 *tp)
3258 r8152b_enable_fc(tp);
3259 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_FLOW_CTR, 0);
3262 static void r8153_hw_phy_cfg(struct r8152 *tp)
3267 /* disable ALDPS before updating the PHY parameters */
3268 r8153_aldps_en(tp, false);
3270 /* disable EEE before updating the PHY parameters */
3271 r8153_eee_en(tp, false);
3272 ocp_reg_write(tp, OCP_EEE_ADV, 0);
3274 if (tp->version == RTL_VER_03) {
3275 data = ocp_reg_read(tp, OCP_EEE_CFG);
3276 data &= ~CTAP_SHORT_EN;
3277 ocp_reg_write(tp, OCP_EEE_CFG, data);
3280 data = ocp_reg_read(tp, OCP_POWER_CFG);
3281 data |= EEE_CLKDIV_EN;
3282 ocp_reg_write(tp, OCP_POWER_CFG, data);
3284 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
3285 data |= EN_10M_BGOFF;
3286 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
3287 data = ocp_reg_read(tp, OCP_POWER_CFG);
3288 data |= EN_10M_PLLOFF;
3289 ocp_reg_write(tp, OCP_POWER_CFG, data);
3290 sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
3292 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3293 ocp_data |= PFM_PWM_SWITCH;
3294 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3296 /* Enable LPF corner auto tune */
3297 sram_write(tp, SRAM_LPF_CFG, 0xf70f);
3299 /* Adjust 10M Amplitude */
3300 sram_write(tp, SRAM_10M_AMP1, 0x00af);
3301 sram_write(tp, SRAM_10M_AMP2, 0x0208);
3303 r8153_eee_en(tp, true);
3304 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
3306 r8153_aldps_en(tp, true);
3307 r8152b_enable_fc(tp);
3309 switch (tp->version) {
3316 r8153_u2p3en(tp, true);
3320 set_bit(PHY_RESET, &tp->flags);
3323 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
3327 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
3328 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
3329 ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */
3330 ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
3335 static void r8153b_hw_phy_cfg(struct r8152 *tp)
3337 u32 ocp_data, ups_flags = 0;
3340 /* disable ALDPS before updating the PHY parameters */
3341 r8153b_aldps_en(tp, false);
3343 /* disable EEE before updating the PHY parameters */
3344 r8153b_eee_en(tp, false);
3345 ocp_reg_write(tp, OCP_EEE_ADV, 0);
3347 r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
3349 data = sram_read(tp, SRAM_GREEN_CFG);
3351 sram_write(tp, SRAM_GREEN_CFG, data);
3352 data = ocp_reg_read(tp, OCP_NCTL_CFG);
3353 data |= PGA_RETURN_EN;
3354 ocp_reg_write(tp, OCP_NCTL_CFG, data);
3356 /* ADC Bias Calibration:
3357 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
3358 * bit (bit3) to rebuild the real 16-bit data. Write the data to the
3361 ocp_data = r8152_efuse_read(tp, 0x7d);
3362 data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
3364 ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
3366 /* ups mode tx-link-pulse timing adjustment:
3367 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
3368 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
3370 ocp_data = ocp_reg_read(tp, 0xc426);
3373 u32 swr_cnt_1ms_ini;
3375 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
3376 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
3377 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
3378 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
3381 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3382 ocp_data |= PFM_PWM_SWITCH;
3383 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3386 if (!r8153_patch_request(tp, true)) {
3387 data = ocp_reg_read(tp, OCP_POWER_CFG);
3388 data |= EEE_CLKDIV_EN;
3389 ocp_reg_write(tp, OCP_POWER_CFG, data);
3391 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
3392 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
3393 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
3395 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
3396 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
3398 ups_flags |= UPS_FLAGS_EN_10M_CKDIV | UPS_FLAGS_250M_CKDIV |
3399 UPS_FLAGS_EN_EEE_CKDIV | UPS_FLAGS_EEE_CMOD_LV_EN |
3400 UPS_FLAGS_EEE_PLLOFF_GIGA;
3402 r8153_patch_request(tp, false);
3405 r8153b_ups_flags_w1w0(tp, ups_flags, 0);
3407 r8153b_eee_en(tp, true);
3408 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
3410 r8153b_aldps_en(tp, true);
3411 r8153b_enable_fc(tp);
3412 r8153_u2p3en(tp, true);
3414 set_bit(PHY_RESET, &tp->flags);
3417 static void r8153_first_init(struct r8152 *tp)
3422 r8153_mac_clk_spd(tp, false);
3423 rxdy_gated_en(tp, true);
3424 r8153_teredo_off(tp);
3426 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3427 ocp_data &= ~RCR_ACPT_ALL;
3428 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3430 rtl8152_nic_reset(tp);
3433 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3434 ocp_data &= ~NOW_IS_OOB;
3435 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3437 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3438 ocp_data &= ~MCU_BORW_EN;
3439 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3441 for (i = 0; i < 1000; i++) {
3442 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3443 if (ocp_data & LINK_LIST_READY)
3445 usleep_range(1000, 2000);
3448 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3449 ocp_data |= RE_INIT_LL;
3450 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3452 for (i = 0; i < 1000; i++) {
3453 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3454 if (ocp_data & LINK_LIST_READY)
3456 usleep_range(1000, 2000);
3459 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
3461 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
3462 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
3463 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
3465 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
3466 ocp_data |= TCR0_AUTO_FIFO;
3467 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
3469 rtl8152_nic_reset(tp);
3471 /* rx share fifo credit full threshold */
3472 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
3473 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
3474 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
3475 /* TX share fifo free credit full threshold */
3476 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
3479 static void r8153_enter_oob(struct r8152 *tp)
3484 r8153_mac_clk_spd(tp, true);
3486 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3487 ocp_data &= ~NOW_IS_OOB;
3488 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3493 for (i = 0; i < 1000; i++) {
3494 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3495 if (ocp_data & LINK_LIST_READY)
3497 usleep_range(1000, 2000);
3500 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3501 ocp_data |= RE_INIT_LL;
3502 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3504 for (i = 0; i < 1000; i++) {
3505 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3506 if (ocp_data & LINK_LIST_READY)
3508 usleep_range(1000, 2000);
3511 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
3512 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
3514 switch (tp->version) {
3519 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
3520 ocp_data &= ~TEREDO_WAKE_MASK;
3521 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
3526 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
3527 * type. Set it to zero. bits[7:0] are the W1C bits about
3528 * the events. Set them to all 1 to clear them.
3530 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
3537 rtl_rx_vlan_en(tp, true);
3539 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
3540 ocp_data |= ALDPS_PROXY_MODE;
3541 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
3543 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3544 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
3545 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3547 rxdy_gated_en(tp, false);
3549 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3550 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
3551 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3554 static void rtl8153_disable(struct r8152 *tp)
3556 r8153_aldps_en(tp, false);
3559 r8153_aldps_en(tp, true);
3562 static void rtl8153b_disable(struct r8152 *tp)
3564 r8153b_aldps_en(tp, false);
3567 r8153b_aldps_en(tp, true);
3570 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
3572 u16 bmcr, anar, gbcr;
3573 enum spd_duplex speed_duplex;
3576 anar = r8152_mdio_read(tp, MII_ADVERTISE);
3577 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
3578 ADVERTISE_100HALF | ADVERTISE_100FULL);
3579 if (tp->mii.supports_gmii) {
3580 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
3581 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
3586 if (autoneg == AUTONEG_DISABLE) {
3587 if (speed == SPEED_10) {
3589 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3590 speed_duplex = FORCE_10M_HALF;
3591 } else if (speed == SPEED_100) {
3592 bmcr = BMCR_SPEED100;
3593 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3594 speed_duplex = FORCE_100M_HALF;
3595 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
3596 bmcr = BMCR_SPEED1000;
3597 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
3598 speed_duplex = NWAY_1000M_FULL;
3604 if (duplex == DUPLEX_FULL) {
3605 bmcr |= BMCR_FULLDPLX;
3606 if (speed != SPEED_1000)
3610 if (speed == SPEED_10) {
3611 if (duplex == DUPLEX_FULL) {
3612 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3613 speed_duplex = NWAY_10M_FULL;
3615 anar |= ADVERTISE_10HALF;
3616 speed_duplex = NWAY_10M_HALF;
3618 } else if (speed == SPEED_100) {
3619 if (duplex == DUPLEX_FULL) {
3620 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3621 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3622 speed_duplex = NWAY_100M_FULL;
3624 anar |= ADVERTISE_10HALF;
3625 anar |= ADVERTISE_100HALF;
3626 speed_duplex = NWAY_100M_HALF;
3628 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
3629 if (duplex == DUPLEX_FULL) {
3630 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3631 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3632 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
3634 anar |= ADVERTISE_10HALF;
3635 anar |= ADVERTISE_100HALF;
3636 gbcr |= ADVERTISE_1000HALF;
3638 speed_duplex = NWAY_1000M_FULL;
3644 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
3647 if (test_and_clear_bit(PHY_RESET, &tp->flags))
3650 if (tp->mii.supports_gmii)
3651 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
3653 r8152_mdio_write(tp, MII_ADVERTISE, anar);
3654 r8152_mdio_write(tp, MII_BMCR, bmcr);
3656 switch (tp->version) {
3659 r8153b_ups_flags_w1w0(tp, ups_flags_speed(speed_duplex),
3660 UPS_FLAGS_SPEED_MASK);
3667 if (bmcr & BMCR_RESET) {
3670 for (i = 0; i < 50; i++) {
3672 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
3681 static void rtl8152_up(struct r8152 *tp)
3683 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3686 r8152_aldps_en(tp, false);
3687 r8152b_exit_oob(tp);
3688 r8152_aldps_en(tp, true);
3691 static void rtl8152_down(struct r8152 *tp)
3693 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3694 rtl_drop_queued_tx(tp);
3698 r8152_power_cut_en(tp, false);
3699 r8152_aldps_en(tp, false);
3700 r8152b_enter_oob(tp);
3701 r8152_aldps_en(tp, true);
3704 static void rtl8153_up(struct r8152 *tp)
3706 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3709 r8153_u1u2en(tp, false);
3710 r8153_u2p3en(tp, false);
3711 r8153_aldps_en(tp, false);
3712 r8153_first_init(tp);
3713 r8153_aldps_en(tp, true);
3715 switch (tp->version) {
3722 r8153_u2p3en(tp, true);
3726 r8153_u1u2en(tp, true);
3729 static void rtl8153_down(struct r8152 *tp)
3731 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3732 rtl_drop_queued_tx(tp);
3736 r8153_u1u2en(tp, false);
3737 r8153_u2p3en(tp, false);
3738 r8153_power_cut_en(tp, false);
3739 r8153_aldps_en(tp, false);
3740 r8153_enter_oob(tp);
3741 r8153_aldps_en(tp, true);
3744 static void rtl8153b_up(struct r8152 *tp)
3746 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3749 r8153b_u1u2en(tp, false);
3750 r8153_u2p3en(tp, false);
3751 r8153b_aldps_en(tp, false);
3753 r8153_first_init(tp);
3754 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
3756 r8153b_aldps_en(tp, true);
3757 r8153_u2p3en(tp, true);
3758 r8153b_u1u2en(tp, true);
3761 static void rtl8153b_down(struct r8152 *tp)
3763 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3764 rtl_drop_queued_tx(tp);
3768 r8153b_u1u2en(tp, false);
3769 r8153_u2p3en(tp, false);
3770 r8153b_power_cut_en(tp, false);
3771 r8153b_aldps_en(tp, false);
3772 r8153_enter_oob(tp);
3773 r8153b_aldps_en(tp, true);
3776 static bool rtl8152_in_nway(struct r8152 *tp)
3780 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
3781 tp->ocp_base = 0x2000;
3782 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */
3783 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
3785 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
3786 if (nway_state & 0xc000)
3792 static bool rtl8153_in_nway(struct r8152 *tp)
3794 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
3796 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
3802 static void set_carrier(struct r8152 *tp)
3804 struct net_device *netdev = tp->netdev;
3805 struct napi_struct *napi = &tp->napi;
3808 speed = rtl8152_get_speed(tp);
3810 if (speed & LINK_STATUS) {
3811 if (!netif_carrier_ok(netdev)) {
3812 tp->rtl_ops.enable(tp);
3813 netif_stop_queue(netdev);
3815 netif_carrier_on(netdev);
3817 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
3818 _rtl8152_set_rx_mode(netdev);
3819 napi_enable(&tp->napi);
3820 netif_wake_queue(netdev);
3821 netif_info(tp, link, netdev, "carrier on\n");
3822 } else if (netif_queue_stopped(netdev) &&
3823 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
3824 netif_wake_queue(netdev);
3827 if (netif_carrier_ok(netdev)) {
3828 netif_carrier_off(netdev);
3830 tp->rtl_ops.disable(tp);
3832 netif_info(tp, link, netdev, "carrier off\n");
3837 static void rtl_work_func_t(struct work_struct *work)
3839 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
3841 /* If the device is unplugged or !netif_running(), the workqueue
3842 * doesn't need to wake the device, and could return directly.
3844 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
3847 if (usb_autopm_get_interface(tp->intf) < 0)
3850 if (!test_bit(WORK_ENABLE, &tp->flags))
3853 if (!mutex_trylock(&tp->control)) {
3854 schedule_delayed_work(&tp->schedule, 0);
3858 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
3861 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
3862 _rtl8152_set_rx_mode(tp->netdev);
3864 /* don't schedule napi before linking */
3865 if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) &&
3866 netif_carrier_ok(tp->netdev))
3867 napi_schedule(&tp->napi);
3869 mutex_unlock(&tp->control);
3872 usb_autopm_put_interface(tp->intf);
3875 static void rtl_hw_phy_work_func_t(struct work_struct *work)
3877 struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
3879 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3882 if (usb_autopm_get_interface(tp->intf) < 0)
3885 mutex_lock(&tp->control);
3887 tp->rtl_ops.hw_phy_cfg(tp);
3889 rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex);
3891 mutex_unlock(&tp->control);
3893 usb_autopm_put_interface(tp->intf);
3896 #ifdef CONFIG_PM_SLEEP
3897 static int rtl_notifier(struct notifier_block *nb, unsigned long action,
3900 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
3903 case PM_HIBERNATION_PREPARE:
3904 case PM_SUSPEND_PREPARE:
3905 usb_autopm_get_interface(tp->intf);
3908 case PM_POST_HIBERNATION:
3909 case PM_POST_SUSPEND:
3910 usb_autopm_put_interface(tp->intf);
3913 case PM_POST_RESTORE:
3914 case PM_RESTORE_PREPARE:
3923 static int rtl8152_open(struct net_device *netdev)
3925 struct r8152 *tp = netdev_priv(netdev);
3928 res = alloc_all_mem(tp);
3932 res = usb_autopm_get_interface(tp->intf);
3936 mutex_lock(&tp->control);
3940 netif_carrier_off(netdev);
3941 netif_start_queue(netdev);
3942 set_bit(WORK_ENABLE, &tp->flags);
3944 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3947 netif_device_detach(tp->netdev);
3948 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
3952 napi_enable(&tp->napi);
3954 mutex_unlock(&tp->control);
3956 usb_autopm_put_interface(tp->intf);
3957 #ifdef CONFIG_PM_SLEEP
3958 tp->pm_notifier.notifier_call = rtl_notifier;
3959 register_pm_notifier(&tp->pm_notifier);
3964 mutex_unlock(&tp->control);
3965 usb_autopm_put_interface(tp->intf);
3972 static int rtl8152_close(struct net_device *netdev)
3974 struct r8152 *tp = netdev_priv(netdev);
3977 #ifdef CONFIG_PM_SLEEP
3978 unregister_pm_notifier(&tp->pm_notifier);
3980 if (!test_bit(RTL8152_UNPLUG, &tp->flags))
3981 napi_disable(&tp->napi);
3982 clear_bit(WORK_ENABLE, &tp->flags);
3983 usb_kill_urb(tp->intr_urb);
3984 cancel_delayed_work_sync(&tp->schedule);
3985 netif_stop_queue(netdev);
3987 res = usb_autopm_get_interface(tp->intf);
3988 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
3989 rtl_drop_queued_tx(tp);
3992 mutex_lock(&tp->control);
3994 tp->rtl_ops.down(tp);
3996 mutex_unlock(&tp->control);
3998 usb_autopm_put_interface(tp->intf);
4006 static void rtl_tally_reset(struct r8152 *tp)
4010 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
4011 ocp_data |= TALLY_RESET;
4012 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
4015 static void r8152b_init(struct r8152 *tp)
4020 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4023 data = r8152_mdio_read(tp, MII_BMCR);
4024 if (data & BMCR_PDOWN) {
4025 data &= ~BMCR_PDOWN;
4026 r8152_mdio_write(tp, MII_BMCR, data);
4029 r8152_aldps_en(tp, false);
4031 if (tp->version == RTL_VER_01) {
4032 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
4033 ocp_data &= ~LED_MODE_MASK;
4034 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
4037 r8152_power_cut_en(tp, false);
4039 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
4040 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
4041 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
4042 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
4043 ocp_data &= ~MCU_CLK_RATIO_MASK;
4044 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
4045 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
4046 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
4047 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
4048 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
4050 rtl_tally_reset(tp);
4052 /* enable rx aggregation */
4053 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4054 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4055 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4058 static void r8153_init(struct r8152 *tp)
4064 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4067 r8153_u1u2en(tp, false);
4069 for (i = 0; i < 500; i++) {
4070 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
4076 data = r8153_phy_status(tp, 0);
4078 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
4079 tp->version == RTL_VER_05)
4080 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
4082 data = r8152_mdio_read(tp, MII_BMCR);
4083 if (data & BMCR_PDOWN) {
4084 data &= ~BMCR_PDOWN;
4085 r8152_mdio_write(tp, MII_BMCR, data);
4088 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
4090 r8153_u2p3en(tp, false);
4092 if (tp->version == RTL_VER_04) {
4093 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
4094 ocp_data &= ~pwd_dn_scale_mask;
4095 ocp_data |= pwd_dn_scale(96);
4096 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
4098 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
4099 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
4100 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
4101 } else if (tp->version == RTL_VER_05) {
4102 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
4103 ocp_data &= ~ECM_ALDPS;
4104 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
4106 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
4107 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
4108 ocp_data &= ~DYNAMIC_BURST;
4110 ocp_data |= DYNAMIC_BURST;
4111 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
4112 } else if (tp->version == RTL_VER_06) {
4113 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
4114 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
4115 ocp_data &= ~DYNAMIC_BURST;
4117 ocp_data |= DYNAMIC_BURST;
4118 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
4121 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
4122 ocp_data |= EP4_FULL_FC;
4123 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
4125 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
4126 ocp_data &= ~TIMER11_EN;
4127 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
4129 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
4130 ocp_data &= ~LED_MODE_MASK;
4131 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
4133 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
4134 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
4135 ocp_data |= LPM_TIMER_500MS;
4137 ocp_data |= LPM_TIMER_500US;
4138 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
4140 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
4141 ocp_data &= ~SEN_VAL_MASK;
4142 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
4143 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
4145 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
4147 r8153_power_cut_en(tp, false);
4148 r8153_u1u2en(tp, true);
4149 r8153_mac_clk_spd(tp, false);
4150 usb_enable_lpm(tp->udev);
4152 /* rx aggregation */
4153 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4154 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4155 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
4156 ocp_data |= RX_AGG_DISABLE;
4158 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4160 rtl_tally_reset(tp);
4162 switch (tp->udev->speed) {
4163 case USB_SPEED_SUPER:
4164 case USB_SPEED_SUPER_PLUS:
4165 tp->coalesce = COALESCE_SUPER;
4167 case USB_SPEED_HIGH:
4168 tp->coalesce = COALESCE_HIGH;
4171 tp->coalesce = COALESCE_SLOW;
4176 static void r8153b_init(struct r8152 *tp)
4182 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4185 r8153b_u1u2en(tp, false);
4187 for (i = 0; i < 500; i++) {
4188 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
4194 data = r8153_phy_status(tp, 0);
4196 data = r8152_mdio_read(tp, MII_BMCR);
4197 if (data & BMCR_PDOWN) {
4198 data &= ~BMCR_PDOWN;
4199 r8152_mdio_write(tp, MII_BMCR, data);
4202 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
4204 r8153_u2p3en(tp, false);
4206 /* MSC timer = 0xfff * 8ms = 32760 ms */
4207 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
4209 /* U1/U2/L1 idle timer. 500 us */
4210 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
4212 r8153b_power_cut_en(tp, false);
4213 r8153b_ups_en(tp, false);
4214 r8153b_queue_wake(tp, false);
4215 rtl_runtime_suspend_enable(tp, false);
4216 r8153b_u1u2en(tp, true);
4217 usb_enable_lpm(tp->udev);
4219 /* MAC clock speed down */
4220 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
4221 ocp_data |= MAC_CLK_SPDWN_EN;
4222 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
4224 set_bit(GREEN_ETHERNET, &tp->flags);
4226 /* rx aggregation */
4227 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4228 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4229 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4231 rtl_tally_reset(tp);
4233 tp->coalesce = 15000; /* 15 us */
4236 static int rtl8152_pre_reset(struct usb_interface *intf)
4238 struct r8152 *tp = usb_get_intfdata(intf);
4239 struct net_device *netdev;
4244 netdev = tp->netdev;
4245 if (!netif_running(netdev))
4248 netif_stop_queue(netdev);
4249 napi_disable(&tp->napi);
4250 clear_bit(WORK_ENABLE, &tp->flags);
4251 usb_kill_urb(tp->intr_urb);
4252 cancel_delayed_work_sync(&tp->schedule);
4253 if (netif_carrier_ok(netdev)) {
4254 mutex_lock(&tp->control);
4255 tp->rtl_ops.disable(tp);
4256 mutex_unlock(&tp->control);
4262 static int rtl8152_post_reset(struct usb_interface *intf)
4264 struct r8152 *tp = usb_get_intfdata(intf);
4265 struct net_device *netdev;
4270 netdev = tp->netdev;
4271 if (!netif_running(netdev))
4274 set_bit(WORK_ENABLE, &tp->flags);
4275 if (netif_carrier_ok(netdev)) {
4276 mutex_lock(&tp->control);
4277 tp->rtl_ops.enable(tp);
4279 _rtl8152_set_rx_mode(netdev);
4280 mutex_unlock(&tp->control);
4283 napi_enable(&tp->napi);
4284 netif_wake_queue(netdev);
4285 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
4287 if (!list_empty(&tp->rx_done))
4288 napi_schedule(&tp->napi);
4293 static bool delay_autosuspend(struct r8152 *tp)
4295 bool sw_linking = !!netif_carrier_ok(tp->netdev);
4296 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
4298 /* This means a linking change occurs and the driver doesn't detect it,
4299 * yet. If the driver has disabled tx/rx and hw is linking on, the
4300 * device wouldn't wake up by receiving any packet.
4302 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
4305 /* If the linking down is occurred by nway, the device may miss the
4306 * linking change event. And it wouldn't wake when linking on.
4308 if (!sw_linking && tp->rtl_ops.in_nway(tp))
4310 else if (!skb_queue_empty(&tp->tx_queue))
4316 static int rtl8152_runtime_resume(struct r8152 *tp)
4318 struct net_device *netdev = tp->netdev;
4320 if (netif_running(netdev) && netdev->flags & IFF_UP) {
4321 struct napi_struct *napi = &tp->napi;
4323 tp->rtl_ops.autosuspend_en(tp, false);
4325 set_bit(WORK_ENABLE, &tp->flags);
4327 if (netif_carrier_ok(netdev)) {
4328 if (rtl8152_get_speed(tp) & LINK_STATUS) {
4331 netif_carrier_off(netdev);
4332 tp->rtl_ops.disable(tp);
4333 netif_info(tp, link, netdev, "linking down\n");
4338 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4339 smp_mb__after_atomic();
4341 if (!list_empty(&tp->rx_done))
4342 napi_schedule(&tp->napi);
4344 usb_submit_urb(tp->intr_urb, GFP_NOIO);
4346 if (netdev->flags & IFF_UP)
4347 tp->rtl_ops.autosuspend_en(tp, false);
4349 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4355 static int rtl8152_system_resume(struct r8152 *tp)
4357 struct net_device *netdev = tp->netdev;
4359 netif_device_attach(netdev);
4361 if (netif_running(netdev) && netdev->flags & IFF_UP) {
4363 netif_carrier_off(netdev);
4364 set_bit(WORK_ENABLE, &tp->flags);
4365 usb_submit_urb(tp->intr_urb, GFP_NOIO);
4371 static int rtl8152_runtime_suspend(struct r8152 *tp)
4373 struct net_device *netdev = tp->netdev;
4376 set_bit(SELECTIVE_SUSPEND, &tp->flags);
4377 smp_mb__after_atomic();
4379 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
4382 if (netif_carrier_ok(netdev)) {
4385 rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4386 ocp_data = rcr & ~RCR_ACPT_ALL;
4387 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4388 rxdy_gated_en(tp, true);
4389 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
4391 if (!(ocp_data & RXFIFO_EMPTY)) {
4392 rxdy_gated_en(tp, false);
4393 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
4394 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4395 smp_mb__after_atomic();
4401 clear_bit(WORK_ENABLE, &tp->flags);
4402 usb_kill_urb(tp->intr_urb);
4404 tp->rtl_ops.autosuspend_en(tp, true);
4406 if (netif_carrier_ok(netdev)) {
4407 struct napi_struct *napi = &tp->napi;
4411 rxdy_gated_en(tp, false);
4412 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
4416 if (delay_autosuspend(tp)) {
4417 rtl8152_runtime_resume(tp);
4426 static int rtl8152_system_suspend(struct r8152 *tp)
4428 struct net_device *netdev = tp->netdev;
4430 netif_device_detach(netdev);
4432 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
4433 struct napi_struct *napi = &tp->napi;
4435 clear_bit(WORK_ENABLE, &tp->flags);
4436 usb_kill_urb(tp->intr_urb);
4438 cancel_delayed_work_sync(&tp->schedule);
4439 tp->rtl_ops.down(tp);
4446 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
4448 struct r8152 *tp = usb_get_intfdata(intf);
4451 mutex_lock(&tp->control);
4453 if (PMSG_IS_AUTO(message))
4454 ret = rtl8152_runtime_suspend(tp);
4456 ret = rtl8152_system_suspend(tp);
4458 mutex_unlock(&tp->control);
4463 static int rtl8152_resume(struct usb_interface *intf)
4465 struct r8152 *tp = usb_get_intfdata(intf);
4468 mutex_lock(&tp->control);
4470 if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
4471 ret = rtl8152_runtime_resume(tp);
4473 ret = rtl8152_system_resume(tp);
4475 mutex_unlock(&tp->control);
4480 static int rtl8152_reset_resume(struct usb_interface *intf)
4482 struct r8152 *tp = usb_get_intfdata(intf);
4484 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4485 mutex_lock(&tp->control);
4486 tp->rtl_ops.init(tp);
4487 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
4488 mutex_unlock(&tp->control);
4489 return rtl8152_resume(intf);
4492 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4494 struct r8152 *tp = netdev_priv(dev);
4496 if (usb_autopm_get_interface(tp->intf) < 0)
4499 if (!rtl_can_wakeup(tp)) {
4503 mutex_lock(&tp->control);
4504 wol->supported = WAKE_ANY;
4505 wol->wolopts = __rtl_get_wol(tp);
4506 mutex_unlock(&tp->control);
4509 usb_autopm_put_interface(tp->intf);
4512 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4514 struct r8152 *tp = netdev_priv(dev);
4517 if (!rtl_can_wakeup(tp))
4520 if (wol->wolopts & ~WAKE_ANY)
4523 ret = usb_autopm_get_interface(tp->intf);
4527 mutex_lock(&tp->control);
4529 __rtl_set_wol(tp, wol->wolopts);
4530 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
4532 mutex_unlock(&tp->control);
4534 usb_autopm_put_interface(tp->intf);
4540 static u32 rtl8152_get_msglevel(struct net_device *dev)
4542 struct r8152 *tp = netdev_priv(dev);
4544 return tp->msg_enable;
4547 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
4549 struct r8152 *tp = netdev_priv(dev);
4551 tp->msg_enable = value;
4554 static void rtl8152_get_drvinfo(struct net_device *netdev,
4555 struct ethtool_drvinfo *info)
4557 struct r8152 *tp = netdev_priv(netdev);
4559 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
4560 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
4561 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
4565 int rtl8152_get_link_ksettings(struct net_device *netdev,
4566 struct ethtool_link_ksettings *cmd)
4568 struct r8152 *tp = netdev_priv(netdev);
4571 if (!tp->mii.mdio_read)
4574 ret = usb_autopm_get_interface(tp->intf);
4578 mutex_lock(&tp->control);
4580 mii_ethtool_get_link_ksettings(&tp->mii, cmd);
4582 mutex_unlock(&tp->control);
4584 usb_autopm_put_interface(tp->intf);
4590 static int rtl8152_set_link_ksettings(struct net_device *dev,
4591 const struct ethtool_link_ksettings *cmd)
4593 struct r8152 *tp = netdev_priv(dev);
4596 ret = usb_autopm_get_interface(tp->intf);
4600 mutex_lock(&tp->control);
4602 ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
4605 tp->autoneg = cmd->base.autoneg;
4606 tp->speed = cmd->base.speed;
4607 tp->duplex = cmd->base.duplex;
4610 mutex_unlock(&tp->control);
4612 usb_autopm_put_interface(tp->intf);
4618 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
4625 "tx_single_collisions",
4626 "tx_multi_collisions",
4634 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
4638 return ARRAY_SIZE(rtl8152_gstrings);
4644 static void rtl8152_get_ethtool_stats(struct net_device *dev,
4645 struct ethtool_stats *stats, u64 *data)
4647 struct r8152 *tp = netdev_priv(dev);
4648 struct tally_counter tally;
4650 if (usb_autopm_get_interface(tp->intf) < 0)
4653 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
4655 usb_autopm_put_interface(tp->intf);
4657 data[0] = le64_to_cpu(tally.tx_packets);
4658 data[1] = le64_to_cpu(tally.rx_packets);
4659 data[2] = le64_to_cpu(tally.tx_errors);
4660 data[3] = le32_to_cpu(tally.rx_errors);
4661 data[4] = le16_to_cpu(tally.rx_missed);
4662 data[5] = le16_to_cpu(tally.align_errors);
4663 data[6] = le32_to_cpu(tally.tx_one_collision);
4664 data[7] = le32_to_cpu(tally.tx_multi_collision);
4665 data[8] = le64_to_cpu(tally.rx_unicast);
4666 data[9] = le64_to_cpu(tally.rx_broadcast);
4667 data[10] = le32_to_cpu(tally.rx_multicast);
4668 data[11] = le16_to_cpu(tally.tx_aborted);
4669 data[12] = le16_to_cpu(tally.tx_underrun);
4672 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
4674 switch (stringset) {
4676 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
4681 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
4683 u32 ocp_data, lp, adv, supported = 0;
4686 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
4687 supported = mmd_eee_cap_to_ethtool_sup_t(val);
4689 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
4690 adv = mmd_eee_adv_to_ethtool_adv_t(val);
4692 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
4693 lp = mmd_eee_adv_to_ethtool_adv_t(val);
4695 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4696 ocp_data &= EEE_RX_EN | EEE_TX_EN;
4698 eee->eee_enabled = !!ocp_data;
4699 eee->eee_active = !!(supported & adv & lp);
4700 eee->supported = supported;
4701 eee->advertised = adv;
4702 eee->lp_advertised = lp;
4707 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4709 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4711 r8152_eee_en(tp, eee->eee_enabled);
4713 if (!eee->eee_enabled)
4716 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4721 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
4723 u32 ocp_data, lp, adv, supported = 0;
4726 val = ocp_reg_read(tp, OCP_EEE_ABLE);
4727 supported = mmd_eee_cap_to_ethtool_sup_t(val);
4729 val = ocp_reg_read(tp, OCP_EEE_ADV);
4730 adv = mmd_eee_adv_to_ethtool_adv_t(val);
4732 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
4733 lp = mmd_eee_adv_to_ethtool_adv_t(val);
4735 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4736 ocp_data &= EEE_RX_EN | EEE_TX_EN;
4738 eee->eee_enabled = !!ocp_data;
4739 eee->eee_active = !!(supported & adv & lp);
4740 eee->supported = supported;
4741 eee->advertised = adv;
4742 eee->lp_advertised = lp;
4747 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4749 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4751 r8153_eee_en(tp, eee->eee_enabled);
4753 if (!eee->eee_enabled)
4756 ocp_reg_write(tp, OCP_EEE_ADV, val);
4761 static int r8153b_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4763 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4765 r8153b_eee_en(tp, eee->eee_enabled);
4767 if (!eee->eee_enabled)
4770 ocp_reg_write(tp, OCP_EEE_ADV, val);
4776 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
4778 struct r8152 *tp = netdev_priv(net);
4781 ret = usb_autopm_get_interface(tp->intf);
4785 mutex_lock(&tp->control);
4787 ret = tp->rtl_ops.eee_get(tp, edata);
4789 mutex_unlock(&tp->control);
4791 usb_autopm_put_interface(tp->intf);
4798 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
4800 struct r8152 *tp = netdev_priv(net);
4803 ret = usb_autopm_get_interface(tp->intf);
4807 mutex_lock(&tp->control);
4809 ret = tp->rtl_ops.eee_set(tp, edata);
4811 ret = mii_nway_restart(&tp->mii);
4813 mutex_unlock(&tp->control);
4815 usb_autopm_put_interface(tp->intf);
4821 static int rtl8152_nway_reset(struct net_device *dev)
4823 struct r8152 *tp = netdev_priv(dev);
4826 ret = usb_autopm_get_interface(tp->intf);
4830 mutex_lock(&tp->control);
4832 ret = mii_nway_restart(&tp->mii);
4834 mutex_unlock(&tp->control);
4836 usb_autopm_put_interface(tp->intf);
4842 static int rtl8152_get_coalesce(struct net_device *netdev,
4843 struct ethtool_coalesce *coalesce)
4845 struct r8152 *tp = netdev_priv(netdev);
4847 switch (tp->version) {
4856 coalesce->rx_coalesce_usecs = tp->coalesce;
4861 static int rtl8152_set_coalesce(struct net_device *netdev,
4862 struct ethtool_coalesce *coalesce)
4864 struct r8152 *tp = netdev_priv(netdev);
4867 switch (tp->version) {
4876 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
4879 ret = usb_autopm_get_interface(tp->intf);
4883 mutex_lock(&tp->control);
4885 if (tp->coalesce != coalesce->rx_coalesce_usecs) {
4886 tp->coalesce = coalesce->rx_coalesce_usecs;
4888 if (netif_running(tp->netdev) && netif_carrier_ok(netdev))
4889 r8153_set_rx_early_timeout(tp);
4892 mutex_unlock(&tp->control);
4894 usb_autopm_put_interface(tp->intf);
4899 static const struct ethtool_ops ops = {
4900 .get_drvinfo = rtl8152_get_drvinfo,
4901 .get_link = ethtool_op_get_link,
4902 .nway_reset = rtl8152_nway_reset,
4903 .get_msglevel = rtl8152_get_msglevel,
4904 .set_msglevel = rtl8152_set_msglevel,
4905 .get_wol = rtl8152_get_wol,
4906 .set_wol = rtl8152_set_wol,
4907 .get_strings = rtl8152_get_strings,
4908 .get_sset_count = rtl8152_get_sset_count,
4909 .get_ethtool_stats = rtl8152_get_ethtool_stats,
4910 .get_coalesce = rtl8152_get_coalesce,
4911 .set_coalesce = rtl8152_set_coalesce,
4912 .get_eee = rtl_ethtool_get_eee,
4913 .set_eee = rtl_ethtool_set_eee,
4914 .get_link_ksettings = rtl8152_get_link_ksettings,
4915 .set_link_ksettings = rtl8152_set_link_ksettings,
4918 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
4920 struct r8152 *tp = netdev_priv(netdev);
4921 struct mii_ioctl_data *data = if_mii(rq);
4924 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4927 res = usb_autopm_get_interface(tp->intf);
4933 data->phy_id = R8152_PHY_ID; /* Internal PHY */
4937 mutex_lock(&tp->control);
4938 data->val_out = r8152_mdio_read(tp, data->reg_num);
4939 mutex_unlock(&tp->control);
4943 if (!capable(CAP_NET_ADMIN)) {
4947 mutex_lock(&tp->control);
4948 r8152_mdio_write(tp, data->reg_num, data->val_in);
4949 mutex_unlock(&tp->control);
4956 usb_autopm_put_interface(tp->intf);
4962 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
4964 struct r8152 *tp = netdev_priv(dev);
4967 switch (tp->version) {
4977 ret = usb_autopm_get_interface(tp->intf);
4981 mutex_lock(&tp->control);
4985 if (netif_running(dev)) {
4986 u32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4988 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms);
4990 if (netif_carrier_ok(dev))
4991 r8153_set_rx_early_size(tp);
4994 mutex_unlock(&tp->control);
4996 usb_autopm_put_interface(tp->intf);
5001 static const struct net_device_ops rtl8152_netdev_ops = {
5002 .ndo_open = rtl8152_open,
5003 .ndo_stop = rtl8152_close,
5004 .ndo_do_ioctl = rtl8152_ioctl,
5005 .ndo_start_xmit = rtl8152_start_xmit,
5006 .ndo_tx_timeout = rtl8152_tx_timeout,
5007 .ndo_set_features = rtl8152_set_features,
5008 .ndo_set_rx_mode = rtl8152_set_rx_mode,
5009 .ndo_set_mac_address = rtl8152_set_mac_address,
5010 .ndo_change_mtu = rtl8152_change_mtu,
5011 .ndo_validate_addr = eth_validate_addr,
5012 .ndo_features_check = rtl8152_features_check,
5015 static void rtl8152_unload(struct r8152 *tp)
5017 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5020 if (tp->version != RTL_VER_01)
5021 r8152_power_cut_en(tp, true);
5024 static void rtl8153_unload(struct r8152 *tp)
5026 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5029 r8153_power_cut_en(tp, false);
5032 static void rtl8153b_unload(struct r8152 *tp)
5034 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5037 r8153b_power_cut_en(tp, false);
5040 static int rtl_ops_init(struct r8152 *tp)
5042 struct rtl_ops *ops = &tp->rtl_ops;
5045 switch (tp->version) {
5049 ops->init = r8152b_init;
5050 ops->enable = rtl8152_enable;
5051 ops->disable = rtl8152_disable;
5052 ops->up = rtl8152_up;
5053 ops->down = rtl8152_down;
5054 ops->unload = rtl8152_unload;
5055 ops->eee_get = r8152_get_eee;
5056 ops->eee_set = r8152_set_eee;
5057 ops->in_nway = rtl8152_in_nway;
5058 ops->hw_phy_cfg = r8152b_hw_phy_cfg;
5059 ops->autosuspend_en = rtl_runtime_suspend_enable;
5066 ops->init = r8153_init;
5067 ops->enable = rtl8153_enable;
5068 ops->disable = rtl8153_disable;
5069 ops->up = rtl8153_up;
5070 ops->down = rtl8153_down;
5071 ops->unload = rtl8153_unload;
5072 ops->eee_get = r8153_get_eee;
5073 ops->eee_set = r8153_set_eee;
5074 ops->in_nway = rtl8153_in_nway;
5075 ops->hw_phy_cfg = r8153_hw_phy_cfg;
5076 ops->autosuspend_en = rtl8153_runtime_enable;
5081 ops->init = r8153b_init;
5082 ops->enable = rtl8153_enable;
5083 ops->disable = rtl8153b_disable;
5084 ops->up = rtl8153b_up;
5085 ops->down = rtl8153b_down;
5086 ops->unload = rtl8153b_unload;
5087 ops->eee_get = r8153_get_eee;
5088 ops->eee_set = r8153b_set_eee;
5089 ops->in_nway = rtl8153_in_nway;
5090 ops->hw_phy_cfg = r8153b_hw_phy_cfg;
5091 ops->autosuspend_en = rtl8153b_runtime_enable;
5096 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
5103 static u8 rtl_get_version(struct usb_interface *intf)
5105 struct usb_device *udev = interface_to_usbdev(intf);
5111 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
5115 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
5116 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
5117 PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500);
5119 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
5125 version = RTL_VER_01;
5128 version = RTL_VER_02;
5131 version = RTL_VER_03;
5134 version = RTL_VER_04;
5137 version = RTL_VER_05;
5140 version = RTL_VER_06;
5143 version = RTL_VER_07;
5146 version = RTL_VER_08;
5149 version = RTL_VER_09;
5152 version = RTL_VER_UNKNOWN;
5153 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
5157 dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
5162 static int rtl8152_probe(struct usb_interface *intf,
5163 const struct usb_device_id *id)
5165 struct usb_device *udev = interface_to_usbdev(intf);
5166 u8 version = rtl_get_version(intf);
5168 struct net_device *netdev;
5171 if (version == RTL_VER_UNKNOWN)
5174 if (udev->actconfig->desc.bConfigurationValue != 1) {
5175 usb_driver_set_configuration(udev, 1);
5179 usb_reset_device(udev);
5180 netdev = alloc_etherdev(sizeof(struct r8152));
5182 dev_err(&intf->dev, "Out of memory\n");
5186 SET_NETDEV_DEV(netdev, &intf->dev);
5187 tp = netdev_priv(netdev);
5188 tp->msg_enable = 0x7FFF;
5191 tp->netdev = netdev;
5193 tp->version = version;
5199 tp->mii.supports_gmii = 0;
5202 tp->mii.supports_gmii = 1;
5206 ret = rtl_ops_init(tp);
5210 mutex_init(&tp->control);
5211 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
5212 INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
5214 netdev->netdev_ops = &rtl8152_netdev_ops;
5215 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
5217 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
5218 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
5219 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
5220 NETIF_F_HW_VLAN_CTAG_TX;
5221 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
5222 NETIF_F_TSO | NETIF_F_FRAGLIST |
5223 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
5224 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
5225 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
5226 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
5227 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
5229 if (tp->version == RTL_VER_01) {
5230 netdev->features &= ~NETIF_F_RXCSUM;
5231 netdev->hw_features &= ~NETIF_F_RXCSUM;
5234 if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial &&
5235 (!strcmp(udev->serial, "000001000000") || !strcmp(udev->serial, "000002000000"))) {
5236 dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation");
5237 set_bit(DELL_TB_RX_AGG_BUG, &tp->flags);
5240 netdev->ethtool_ops = &ops;
5241 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
5243 /* MTU range: 68 - 1500 or 9194 */
5244 netdev->min_mtu = ETH_MIN_MTU;
5245 switch (tp->version) {
5248 netdev->max_mtu = ETH_DATA_LEN;
5251 netdev->max_mtu = RTL8153_MAX_MTU;
5255 tp->mii.dev = netdev;
5256 tp->mii.mdio_read = read_mii_word;
5257 tp->mii.mdio_write = write_mii_word;
5258 tp->mii.phy_id_mask = 0x3f;
5259 tp->mii.reg_num_mask = 0x1f;
5260 tp->mii.phy_id = R8152_PHY_ID;
5262 tp->autoneg = AUTONEG_ENABLE;
5263 tp->speed = tp->mii.supports_gmii ? SPEED_1000 : SPEED_100;
5264 tp->duplex = DUPLEX_FULL;
5266 intf->needs_remote_wakeup = 1;
5268 tp->rtl_ops.init(tp);
5269 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
5270 set_ethernet_addr(tp);
5272 usb_set_intfdata(intf, tp);
5273 netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
5275 ret = register_netdev(netdev);
5277 netif_err(tp, probe, netdev, "couldn't register the device\n");
5281 if (!rtl_can_wakeup(tp))
5282 __rtl_set_wol(tp, 0);
5284 tp->saved_wolopts = __rtl_get_wol(tp);
5285 if (tp->saved_wolopts)
5286 device_set_wakeup_enable(&udev->dev, true);
5288 device_set_wakeup_enable(&udev->dev, false);
5290 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
5295 netif_napi_del(&tp->napi);
5296 usb_set_intfdata(intf, NULL);
5298 free_netdev(netdev);
5302 static void rtl8152_disconnect(struct usb_interface *intf)
5304 struct r8152 *tp = usb_get_intfdata(intf);
5306 usb_set_intfdata(intf, NULL);
5308 struct usb_device *udev = tp->udev;
5310 if (udev->state == USB_STATE_NOTATTACHED)
5311 set_bit(RTL8152_UNPLUG, &tp->flags);
5313 netif_napi_del(&tp->napi);
5314 unregister_netdev(tp->netdev);
5315 cancel_delayed_work_sync(&tp->hw_phy_work);
5316 tp->rtl_ops.unload(tp);
5317 free_netdev(tp->netdev);
5321 #define REALTEK_USB_DEVICE(vend, prod) \
5322 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
5323 USB_DEVICE_ID_MATCH_INT_CLASS, \
5324 .idVendor = (vend), \
5325 .idProduct = (prod), \
5326 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
5329 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
5330 USB_DEVICE_ID_MATCH_DEVICE, \
5331 .idVendor = (vend), \
5332 .idProduct = (prod), \
5333 .bInterfaceClass = USB_CLASS_COMM, \
5334 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
5335 .bInterfaceProtocol = USB_CDC_PROTO_NONE
5337 /* table of devices that work with this driver */
5338 static const struct usb_device_id rtl8152_table[] = {
5339 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)},
5340 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
5341 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
5342 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)},
5343 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)},
5344 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
5345 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)},
5346 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062)},
5347 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069)},
5348 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)},
5349 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c)},
5350 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214)},
5351 {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)},
5352 {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)},
5353 {REALTEK_USB_DEVICE(VENDOR_ID_TPLINK, 0x0601)},
5357 MODULE_DEVICE_TABLE(usb, rtl8152_table);
5359 static struct usb_driver rtl8152_driver = {
5361 .id_table = rtl8152_table,
5362 .probe = rtl8152_probe,
5363 .disconnect = rtl8152_disconnect,
5364 .suspend = rtl8152_suspend,
5365 .resume = rtl8152_resume,
5366 .reset_resume = rtl8152_reset_resume,
5367 .pre_reset = rtl8152_pre_reset,
5368 .post_reset = rtl8152_post_reset,
5369 .supports_autosuspend = 1,
5370 .disable_hub_initiated_lpm = 1,
5373 module_usb_driver(rtl8152_driver);
5375 MODULE_AUTHOR(DRIVER_AUTHOR);
5376 MODULE_DESCRIPTION(DRIVER_DESC);
5377 MODULE_LICENSE("GPL");
5378 MODULE_VERSION(DRIVER_VERSION);