Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next-2.6
[sfrench/cifs-2.6.git] / drivers / net / ucc_geth.c
1 /*
2  * Copyright (C) 2006-2009 Freescale Semicondutor, Inc. All rights reserved.
3  *
4  * Author: Shlomi Gridish <gridish@freescale.com>
5  *         Li Yang <leoli@freescale.com>
6  *
7  * Description:
8  * QE UCC Gigabit Ethernet Driver
9  *
10  * This program is free software; you can redistribute  it and/or modify it
11  * under  the terms of  the GNU General  Public License as published by the
12  * Free Software Foundation;  either version 2 of the  License, or (at your
13  * option) any later version.
14  */
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/errno.h>
18 #include <linux/slab.h>
19 #include <linux/stddef.h>
20 #include <linux/interrupt.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/skbuff.h>
24 #include <linux/spinlock.h>
25 #include <linux/mm.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/mii.h>
28 #include <linux/phy.h>
29 #include <linux/workqueue.h>
30 #include <linux/of_mdio.h>
31 #include <linux/of_platform.h>
32
33 #include <asm/uaccess.h>
34 #include <asm/irq.h>
35 #include <asm/io.h>
36 #include <asm/immap_qe.h>
37 #include <asm/qe.h>
38 #include <asm/ucc.h>
39 #include <asm/ucc_fast.h>
40
41 #include "ucc_geth.h"
42 #include "fsl_pq_mdio.h"
43
44 #undef DEBUG
45
46 #define ugeth_printk(level, format, arg...)  \
47         printk(level format "\n", ## arg)
48
49 #define ugeth_dbg(format, arg...)            \
50         ugeth_printk(KERN_DEBUG , format , ## arg)
51 #define ugeth_err(format, arg...)            \
52         ugeth_printk(KERN_ERR , format , ## arg)
53 #define ugeth_info(format, arg...)           \
54         ugeth_printk(KERN_INFO , format , ## arg)
55 #define ugeth_warn(format, arg...)           \
56         ugeth_printk(KERN_WARNING , format , ## arg)
57
58 #ifdef UGETH_VERBOSE_DEBUG
59 #define ugeth_vdbg ugeth_dbg
60 #else
61 #define ugeth_vdbg(fmt, args...) do { } while (0)
62 #endif                          /* UGETH_VERBOSE_DEBUG */
63 #define UGETH_MSG_DEFAULT       (NETIF_MSG_IFUP << 1 ) - 1
64
65
66 static DEFINE_SPINLOCK(ugeth_lock);
67
68 static void uec_configure_serdes(struct net_device *dev);
69
70 static struct {
71         u32 msg_enable;
72 } debug = { -1 };
73
74 module_param_named(debug, debug.msg_enable, int, 0);
75 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 0xffff=all)");
76
77 static struct ucc_geth_info ugeth_primary_info = {
78         .uf_info = {
79                     .bd_mem_part = MEM_PART_SYSTEM,
80                     .rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES,
81                     .max_rx_buf_length = 1536,
82                     /* adjusted at startup if max-speed 1000 */
83                     .urfs = UCC_GETH_URFS_INIT,
84                     .urfet = UCC_GETH_URFET_INIT,
85                     .urfset = UCC_GETH_URFSET_INIT,
86                     .utfs = UCC_GETH_UTFS_INIT,
87                     .utfet = UCC_GETH_UTFET_INIT,
88                     .utftt = UCC_GETH_UTFTT_INIT,
89                     .ufpt = 256,
90                     .mode = UCC_FAST_PROTOCOL_MODE_ETHERNET,
91                     .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
92                     .tenc = UCC_FAST_TX_ENCODING_NRZ,
93                     .renc = UCC_FAST_RX_ENCODING_NRZ,
94                     .tcrc = UCC_FAST_16_BIT_CRC,
95                     .synl = UCC_FAST_SYNC_LEN_NOT_USED,
96                     },
97         .numQueuesTx = 1,
98         .numQueuesRx = 1,
99         .extendedFilteringChainPointer = ((uint32_t) NULL),
100         .typeorlen = 3072 /*1536 */ ,
101         .nonBackToBackIfgPart1 = 0x40,
102         .nonBackToBackIfgPart2 = 0x60,
103         .miminumInterFrameGapEnforcement = 0x50,
104         .backToBackInterFrameGap = 0x60,
105         .mblinterval = 128,
106         .nortsrbytetime = 5,
107         .fracsiz = 1,
108         .strictpriorityq = 0xff,
109         .altBebTruncation = 0xa,
110         .excessDefer = 1,
111         .maxRetransmission = 0xf,
112         .collisionWindow = 0x37,
113         .receiveFlowControl = 1,
114         .transmitFlowControl = 1,
115         .maxGroupAddrInHash = 4,
116         .maxIndAddrInHash = 4,
117         .prel = 7,
118         .maxFrameLength = 1518,
119         .minFrameLength = 64,
120         .maxD1Length = 1520,
121         .maxD2Length = 1520,
122         .vlantype = 0x8100,
123         .ecamptr = ((uint32_t) NULL),
124         .eventRegMask = UCCE_OTHER,
125         .pausePeriod = 0xf000,
126         .interruptcoalescingmaxvalue = {1, 1, 1, 1, 1, 1, 1, 1},
127         .bdRingLenTx = {
128                         TX_BD_RING_LEN,
129                         TX_BD_RING_LEN,
130                         TX_BD_RING_LEN,
131                         TX_BD_RING_LEN,
132                         TX_BD_RING_LEN,
133                         TX_BD_RING_LEN,
134                         TX_BD_RING_LEN,
135                         TX_BD_RING_LEN},
136
137         .bdRingLenRx = {
138                         RX_BD_RING_LEN,
139                         RX_BD_RING_LEN,
140                         RX_BD_RING_LEN,
141                         RX_BD_RING_LEN,
142                         RX_BD_RING_LEN,
143                         RX_BD_RING_LEN,
144                         RX_BD_RING_LEN,
145                         RX_BD_RING_LEN},
146
147         .numStationAddresses = UCC_GETH_NUM_OF_STATION_ADDRESSES_1,
148         .largestexternallookupkeysize =
149             QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE,
150         .statisticsMode = UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE |
151                 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX |
152                 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX,
153         .vlanOperationTagged = UCC_GETH_VLAN_OPERATION_TAGGED_NOP,
154         .vlanOperationNonTagged = UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP,
155         .rxQoSMode = UCC_GETH_QOS_MODE_DEFAULT,
156         .aufc = UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE,
157         .padAndCrc = MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC,
158         .numThreadsTx = UCC_GETH_NUM_OF_THREADS_1,
159         .numThreadsRx = UCC_GETH_NUM_OF_THREADS_1,
160         .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
161         .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
162 };
163
164 static struct ucc_geth_info ugeth_info[8];
165
166 #ifdef DEBUG
167 static void mem_disp(u8 *addr, int size)
168 {
169         u8 *i;
170         int size16Aling = (size >> 4) << 4;
171         int size4Aling = (size >> 2) << 2;
172         int notAlign = 0;
173         if (size % 16)
174                 notAlign = 1;
175
176         for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16)
177                 printk("0x%08x: %08x %08x %08x %08x\r\n",
178                        (u32) i,
179                        *((u32 *) (i)),
180                        *((u32 *) (i + 4)),
181                        *((u32 *) (i + 8)), *((u32 *) (i + 12)));
182         if (notAlign == 1)
183                 printk("0x%08x: ", (u32) i);
184         for (; (u32) i < (u32) addr + size4Aling; i += 4)
185                 printk("%08x ", *((u32 *) (i)));
186         for (; (u32) i < (u32) addr + size; i++)
187                 printk("%02x", *((u8 *) (i)));
188         if (notAlign == 1)
189                 printk("\r\n");
190 }
191 #endif /* DEBUG */
192
193 static struct list_head *dequeue(struct list_head *lh)
194 {
195         unsigned long flags;
196
197         spin_lock_irqsave(&ugeth_lock, flags);
198         if (!list_empty(lh)) {
199                 struct list_head *node = lh->next;
200                 list_del(node);
201                 spin_unlock_irqrestore(&ugeth_lock, flags);
202                 return node;
203         } else {
204                 spin_unlock_irqrestore(&ugeth_lock, flags);
205                 return NULL;
206         }
207 }
208
209 static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth,
210                 u8 __iomem *bd)
211 {
212         struct sk_buff *skb = NULL;
213
214         skb = dev_alloc_skb(ugeth->ug_info->uf_info.max_rx_buf_length +
215                                   UCC_GETH_RX_DATA_BUF_ALIGNMENT);
216
217         if (skb == NULL)
218                 return NULL;
219
220         /* We need the data buffer to be aligned properly.  We will reserve
221          * as many bytes as needed to align the data properly
222          */
223         skb_reserve(skb,
224                     UCC_GETH_RX_DATA_BUF_ALIGNMENT -
225                     (((unsigned)skb->data) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT -
226                                               1)));
227
228         skb->dev = ugeth->ndev;
229
230         out_be32(&((struct qe_bd __iomem *)bd)->buf,
231                       dma_map_single(ugeth->dev,
232                                      skb->data,
233                                      ugeth->ug_info->uf_info.max_rx_buf_length +
234                                      UCC_GETH_RX_DATA_BUF_ALIGNMENT,
235                                      DMA_FROM_DEVICE));
236
237         out_be32((u32 __iomem *)bd,
238                         (R_E | R_I | (in_be32((u32 __iomem*)bd) & R_W)));
239
240         return skb;
241 }
242
243 static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ)
244 {
245         u8 __iomem *bd;
246         u32 bd_status;
247         struct sk_buff *skb;
248         int i;
249
250         bd = ugeth->p_rx_bd_ring[rxQ];
251         i = 0;
252
253         do {
254                 bd_status = in_be32((u32 __iomem *)bd);
255                 skb = get_new_skb(ugeth, bd);
256
257                 if (!skb)       /* If can not allocate data buffer,
258                                 abort. Cleanup will be elsewhere */
259                         return -ENOMEM;
260
261                 ugeth->rx_skbuff[rxQ][i] = skb;
262
263                 /* advance the BD pointer */
264                 bd += sizeof(struct qe_bd);
265                 i++;
266         } while (!(bd_status & R_W));
267
268         return 0;
269 }
270
271 static int fill_init_enet_entries(struct ucc_geth_private *ugeth,
272                                   u32 *p_start,
273                                   u8 num_entries,
274                                   u32 thread_size,
275                                   u32 thread_alignment,
276                                   unsigned int risc,
277                                   int skip_page_for_first_entry)
278 {
279         u32 init_enet_offset;
280         u8 i;
281         int snum;
282
283         for (i = 0; i < num_entries; i++) {
284                 if ((snum = qe_get_snum()) < 0) {
285                         if (netif_msg_ifup(ugeth))
286                                 ugeth_err("fill_init_enet_entries: Can not get SNUM.");
287                         return snum;
288                 }
289                 if ((i == 0) && skip_page_for_first_entry)
290                 /* First entry of Rx does not have page */
291                         init_enet_offset = 0;
292                 else {
293                         init_enet_offset =
294                             qe_muram_alloc(thread_size, thread_alignment);
295                         if (IS_ERR_VALUE(init_enet_offset)) {
296                                 if (netif_msg_ifup(ugeth))
297                                         ugeth_err("fill_init_enet_entries: Can not allocate DPRAM memory.");
298                                 qe_put_snum((u8) snum);
299                                 return -ENOMEM;
300                         }
301                 }
302                 *(p_start++) =
303                     ((u8) snum << ENET_INIT_PARAM_SNUM_SHIFT) | init_enet_offset
304                     | risc;
305         }
306
307         return 0;
308 }
309
310 static int return_init_enet_entries(struct ucc_geth_private *ugeth,
311                                     u32 *p_start,
312                                     u8 num_entries,
313                                     unsigned int risc,
314                                     int skip_page_for_first_entry)
315 {
316         u32 init_enet_offset;
317         u8 i;
318         int snum;
319
320         for (i = 0; i < num_entries; i++) {
321                 u32 val = *p_start;
322
323                 /* Check that this entry was actually valid --
324                 needed in case failed in allocations */
325                 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
326                         snum =
327                             (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
328                             ENET_INIT_PARAM_SNUM_SHIFT;
329                         qe_put_snum((u8) snum);
330                         if (!((i == 0) && skip_page_for_first_entry)) {
331                         /* First entry of Rx does not have page */
332                                 init_enet_offset =
333                                     (val & ENET_INIT_PARAM_PTR_MASK);
334                                 qe_muram_free(init_enet_offset);
335                         }
336                         *p_start++ = 0;
337                 }
338         }
339
340         return 0;
341 }
342
343 #ifdef DEBUG
344 static int dump_init_enet_entries(struct ucc_geth_private *ugeth,
345                                   u32 __iomem *p_start,
346                                   u8 num_entries,
347                                   u32 thread_size,
348                                   unsigned int risc,
349                                   int skip_page_for_first_entry)
350 {
351         u32 init_enet_offset;
352         u8 i;
353         int snum;
354
355         for (i = 0; i < num_entries; i++) {
356                 u32 val = in_be32(p_start);
357
358                 /* Check that this entry was actually valid --
359                 needed in case failed in allocations */
360                 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
361                         snum =
362                             (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
363                             ENET_INIT_PARAM_SNUM_SHIFT;
364                         qe_put_snum((u8) snum);
365                         if (!((i == 0) && skip_page_for_first_entry)) {
366                         /* First entry of Rx does not have page */
367                                 init_enet_offset =
368                                     (in_be32(p_start) &
369                                      ENET_INIT_PARAM_PTR_MASK);
370                                 ugeth_info("Init enet entry %d:", i);
371                                 ugeth_info("Base address: 0x%08x",
372                                            (u32)
373                                            qe_muram_addr(init_enet_offset));
374                                 mem_disp(qe_muram_addr(init_enet_offset),
375                                          thread_size);
376                         }
377                         p_start++;
378                 }
379         }
380
381         return 0;
382 }
383 #endif
384
385 static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont)
386 {
387         kfree(enet_addr_cont);
388 }
389
390 static void set_mac_addr(__be16 __iomem *reg, u8 *mac)
391 {
392         out_be16(&reg[0], ((u16)mac[5] << 8) | mac[4]);
393         out_be16(&reg[1], ((u16)mac[3] << 8) | mac[2]);
394         out_be16(&reg[2], ((u16)mac[1] << 8) | mac[0]);
395 }
396
397 static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num)
398 {
399         struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
400
401         if (!(paddr_num < NUM_OF_PADDRS)) {
402                 ugeth_warn("%s: Illagel paddr_num.", __func__);
403                 return -EINVAL;
404         }
405
406         p_82xx_addr_filt =
407             (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
408             addressfiltering;
409
410         /* Writing address ff.ff.ff.ff.ff.ff disables address
411         recognition for this register */
412         out_be16(&p_82xx_addr_filt->paddr[paddr_num].h, 0xffff);
413         out_be16(&p_82xx_addr_filt->paddr[paddr_num].m, 0xffff);
414         out_be16(&p_82xx_addr_filt->paddr[paddr_num].l, 0xffff);
415
416         return 0;
417 }
418
419 static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth,
420                                 u8 *p_enet_addr)
421 {
422         struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
423         u32 cecr_subblock;
424
425         p_82xx_addr_filt =
426             (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
427             addressfiltering;
428
429         cecr_subblock =
430             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
431
432         /* Ethernet frames are defined in Little Endian mode,
433         therefor to insert */
434         /* the address to the hash (Big Endian mode), we reverse the bytes.*/
435
436         set_mac_addr(&p_82xx_addr_filt->taddr.h, p_enet_addr);
437
438         qe_issue_cmd(QE_SET_GROUP_ADDRESS, cecr_subblock,
439                      QE_CR_PROTOCOL_ETHERNET, 0);
440 }
441
442 #ifdef CONFIG_UGETH_MAGIC_PACKET
443 static void magic_packet_detection_enable(struct ucc_geth_private *ugeth)
444 {
445         struct ucc_fast_private *uccf;
446         struct ucc_geth __iomem *ug_regs;
447
448         uccf = ugeth->uccf;
449         ug_regs = ugeth->ug_regs;
450
451         /* Enable interrupts for magic packet detection */
452         setbits32(uccf->p_uccm, UCC_GETH_UCCE_MPD);
453
454         /* Enable magic packet detection */
455         setbits32(&ug_regs->maccfg2, MACCFG2_MPE);
456 }
457
458 static void magic_packet_detection_disable(struct ucc_geth_private *ugeth)
459 {
460         struct ucc_fast_private *uccf;
461         struct ucc_geth __iomem *ug_regs;
462
463         uccf = ugeth->uccf;
464         ug_regs = ugeth->ug_regs;
465
466         /* Disable interrupts for magic packet detection */
467         clrbits32(uccf->p_uccm, UCC_GETH_UCCE_MPD);
468
469         /* Disable magic packet detection */
470         clrbits32(&ug_regs->maccfg2, MACCFG2_MPE);
471 }
472 #endif /* MAGIC_PACKET */
473
474 static inline int compare_addr(u8 **addr1, u8 **addr2)
475 {
476         return memcmp(addr1, addr2, ENET_NUM_OCTETS_PER_ADDRESS);
477 }
478
479 #ifdef DEBUG
480 static void get_statistics(struct ucc_geth_private *ugeth,
481                            struct ucc_geth_tx_firmware_statistics *
482                            tx_firmware_statistics,
483                            struct ucc_geth_rx_firmware_statistics *
484                            rx_firmware_statistics,
485                            struct ucc_geth_hardware_statistics *hardware_statistics)
486 {
487         struct ucc_fast __iomem *uf_regs;
488         struct ucc_geth __iomem *ug_regs;
489         struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram;
490         struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram;
491
492         ug_regs = ugeth->ug_regs;
493         uf_regs = (struct ucc_fast __iomem *) ug_regs;
494         p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram;
495         p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram;
496
497         /* Tx firmware only if user handed pointer and driver actually
498         gathers Tx firmware statistics */
499         if (tx_firmware_statistics && p_tx_fw_statistics_pram) {
500                 tx_firmware_statistics->sicoltx =
501                     in_be32(&p_tx_fw_statistics_pram->sicoltx);
502                 tx_firmware_statistics->mulcoltx =
503                     in_be32(&p_tx_fw_statistics_pram->mulcoltx);
504                 tx_firmware_statistics->latecoltxfr =
505                     in_be32(&p_tx_fw_statistics_pram->latecoltxfr);
506                 tx_firmware_statistics->frabortduecol =
507                     in_be32(&p_tx_fw_statistics_pram->frabortduecol);
508                 tx_firmware_statistics->frlostinmactxer =
509                     in_be32(&p_tx_fw_statistics_pram->frlostinmactxer);
510                 tx_firmware_statistics->carriersenseertx =
511                     in_be32(&p_tx_fw_statistics_pram->carriersenseertx);
512                 tx_firmware_statistics->frtxok =
513                     in_be32(&p_tx_fw_statistics_pram->frtxok);
514                 tx_firmware_statistics->txfrexcessivedefer =
515                     in_be32(&p_tx_fw_statistics_pram->txfrexcessivedefer);
516                 tx_firmware_statistics->txpkts256 =
517                     in_be32(&p_tx_fw_statistics_pram->txpkts256);
518                 tx_firmware_statistics->txpkts512 =
519                     in_be32(&p_tx_fw_statistics_pram->txpkts512);
520                 tx_firmware_statistics->txpkts1024 =
521                     in_be32(&p_tx_fw_statistics_pram->txpkts1024);
522                 tx_firmware_statistics->txpktsjumbo =
523                     in_be32(&p_tx_fw_statistics_pram->txpktsjumbo);
524         }
525
526         /* Rx firmware only if user handed pointer and driver actually
527          * gathers Rx firmware statistics */
528         if (rx_firmware_statistics && p_rx_fw_statistics_pram) {
529                 int i;
530                 rx_firmware_statistics->frrxfcser =
531                     in_be32(&p_rx_fw_statistics_pram->frrxfcser);
532                 rx_firmware_statistics->fraligner =
533                     in_be32(&p_rx_fw_statistics_pram->fraligner);
534                 rx_firmware_statistics->inrangelenrxer =
535                     in_be32(&p_rx_fw_statistics_pram->inrangelenrxer);
536                 rx_firmware_statistics->outrangelenrxer =
537                     in_be32(&p_rx_fw_statistics_pram->outrangelenrxer);
538                 rx_firmware_statistics->frtoolong =
539                     in_be32(&p_rx_fw_statistics_pram->frtoolong);
540                 rx_firmware_statistics->runt =
541                     in_be32(&p_rx_fw_statistics_pram->runt);
542                 rx_firmware_statistics->verylongevent =
543                     in_be32(&p_rx_fw_statistics_pram->verylongevent);
544                 rx_firmware_statistics->symbolerror =
545                     in_be32(&p_rx_fw_statistics_pram->symbolerror);
546                 rx_firmware_statistics->dropbsy =
547                     in_be32(&p_rx_fw_statistics_pram->dropbsy);
548                 for (i = 0; i < 0x8; i++)
549                         rx_firmware_statistics->res0[i] =
550                             p_rx_fw_statistics_pram->res0[i];
551                 rx_firmware_statistics->mismatchdrop =
552                     in_be32(&p_rx_fw_statistics_pram->mismatchdrop);
553                 rx_firmware_statistics->underpkts =
554                     in_be32(&p_rx_fw_statistics_pram->underpkts);
555                 rx_firmware_statistics->pkts256 =
556                     in_be32(&p_rx_fw_statistics_pram->pkts256);
557                 rx_firmware_statistics->pkts512 =
558                     in_be32(&p_rx_fw_statistics_pram->pkts512);
559                 rx_firmware_statistics->pkts1024 =
560                     in_be32(&p_rx_fw_statistics_pram->pkts1024);
561                 rx_firmware_statistics->pktsjumbo =
562                     in_be32(&p_rx_fw_statistics_pram->pktsjumbo);
563                 rx_firmware_statistics->frlossinmacer =
564                     in_be32(&p_rx_fw_statistics_pram->frlossinmacer);
565                 rx_firmware_statistics->pausefr =
566                     in_be32(&p_rx_fw_statistics_pram->pausefr);
567                 for (i = 0; i < 0x4; i++)
568                         rx_firmware_statistics->res1[i] =
569                             p_rx_fw_statistics_pram->res1[i];
570                 rx_firmware_statistics->removevlan =
571                     in_be32(&p_rx_fw_statistics_pram->removevlan);
572                 rx_firmware_statistics->replacevlan =
573                     in_be32(&p_rx_fw_statistics_pram->replacevlan);
574                 rx_firmware_statistics->insertvlan =
575                     in_be32(&p_rx_fw_statistics_pram->insertvlan);
576         }
577
578         /* Hardware only if user handed pointer and driver actually
579         gathers hardware statistics */
580         if (hardware_statistics &&
581             (in_be32(&uf_regs->upsmr) & UCC_GETH_UPSMR_HSE)) {
582                 hardware_statistics->tx64 = in_be32(&ug_regs->tx64);
583                 hardware_statistics->tx127 = in_be32(&ug_regs->tx127);
584                 hardware_statistics->tx255 = in_be32(&ug_regs->tx255);
585                 hardware_statistics->rx64 = in_be32(&ug_regs->rx64);
586                 hardware_statistics->rx127 = in_be32(&ug_regs->rx127);
587                 hardware_statistics->rx255 = in_be32(&ug_regs->rx255);
588                 hardware_statistics->txok = in_be32(&ug_regs->txok);
589                 hardware_statistics->txcf = in_be16(&ug_regs->txcf);
590                 hardware_statistics->tmca = in_be32(&ug_regs->tmca);
591                 hardware_statistics->tbca = in_be32(&ug_regs->tbca);
592                 hardware_statistics->rxfok = in_be32(&ug_regs->rxfok);
593                 hardware_statistics->rxbok = in_be32(&ug_regs->rxbok);
594                 hardware_statistics->rbyt = in_be32(&ug_regs->rbyt);
595                 hardware_statistics->rmca = in_be32(&ug_regs->rmca);
596                 hardware_statistics->rbca = in_be32(&ug_regs->rbca);
597         }
598 }
599
600 static void dump_bds(struct ucc_geth_private *ugeth)
601 {
602         int i;
603         int length;
604
605         for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
606                 if (ugeth->p_tx_bd_ring[i]) {
607                         length =
608                             (ugeth->ug_info->bdRingLenTx[i] *
609                              sizeof(struct qe_bd));
610                         ugeth_info("TX BDs[%d]", i);
611                         mem_disp(ugeth->p_tx_bd_ring[i], length);
612                 }
613         }
614         for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
615                 if (ugeth->p_rx_bd_ring[i]) {
616                         length =
617                             (ugeth->ug_info->bdRingLenRx[i] *
618                              sizeof(struct qe_bd));
619                         ugeth_info("RX BDs[%d]", i);
620                         mem_disp(ugeth->p_rx_bd_ring[i], length);
621                 }
622         }
623 }
624
625 static void dump_regs(struct ucc_geth_private *ugeth)
626 {
627         int i;
628
629         ugeth_info("UCC%d Geth registers:", ugeth->ug_info->uf_info.ucc_num);
630         ugeth_info("Base address: 0x%08x", (u32) ugeth->ug_regs);
631
632         ugeth_info("maccfg1    : addr - 0x%08x, val - 0x%08x",
633                    (u32) & ugeth->ug_regs->maccfg1,
634                    in_be32(&ugeth->ug_regs->maccfg1));
635         ugeth_info("maccfg2    : addr - 0x%08x, val - 0x%08x",
636                    (u32) & ugeth->ug_regs->maccfg2,
637                    in_be32(&ugeth->ug_regs->maccfg2));
638         ugeth_info("ipgifg     : addr - 0x%08x, val - 0x%08x",
639                    (u32) & ugeth->ug_regs->ipgifg,
640                    in_be32(&ugeth->ug_regs->ipgifg));
641         ugeth_info("hafdup     : addr - 0x%08x, val - 0x%08x",
642                    (u32) & ugeth->ug_regs->hafdup,
643                    in_be32(&ugeth->ug_regs->hafdup));
644         ugeth_info("ifctl      : addr - 0x%08x, val - 0x%08x",
645                    (u32) & ugeth->ug_regs->ifctl,
646                    in_be32(&ugeth->ug_regs->ifctl));
647         ugeth_info("ifstat     : addr - 0x%08x, val - 0x%08x",
648                    (u32) & ugeth->ug_regs->ifstat,
649                    in_be32(&ugeth->ug_regs->ifstat));
650         ugeth_info("macstnaddr1: addr - 0x%08x, val - 0x%08x",
651                    (u32) & ugeth->ug_regs->macstnaddr1,
652                    in_be32(&ugeth->ug_regs->macstnaddr1));
653         ugeth_info("macstnaddr2: addr - 0x%08x, val - 0x%08x",
654                    (u32) & ugeth->ug_regs->macstnaddr2,
655                    in_be32(&ugeth->ug_regs->macstnaddr2));
656         ugeth_info("uempr      : addr - 0x%08x, val - 0x%08x",
657                    (u32) & ugeth->ug_regs->uempr,
658                    in_be32(&ugeth->ug_regs->uempr));
659         ugeth_info("utbipar    : addr - 0x%08x, val - 0x%08x",
660                    (u32) & ugeth->ug_regs->utbipar,
661                    in_be32(&ugeth->ug_regs->utbipar));
662         ugeth_info("uescr      : addr - 0x%08x, val - 0x%04x",
663                    (u32) & ugeth->ug_regs->uescr,
664                    in_be16(&ugeth->ug_regs->uescr));
665         ugeth_info("tx64       : addr - 0x%08x, val - 0x%08x",
666                    (u32) & ugeth->ug_regs->tx64,
667                    in_be32(&ugeth->ug_regs->tx64));
668         ugeth_info("tx127      : addr - 0x%08x, val - 0x%08x",
669                    (u32) & ugeth->ug_regs->tx127,
670                    in_be32(&ugeth->ug_regs->tx127));
671         ugeth_info("tx255      : addr - 0x%08x, val - 0x%08x",
672                    (u32) & ugeth->ug_regs->tx255,
673                    in_be32(&ugeth->ug_regs->tx255));
674         ugeth_info("rx64       : addr - 0x%08x, val - 0x%08x",
675                    (u32) & ugeth->ug_regs->rx64,
676                    in_be32(&ugeth->ug_regs->rx64));
677         ugeth_info("rx127      : addr - 0x%08x, val - 0x%08x",
678                    (u32) & ugeth->ug_regs->rx127,
679                    in_be32(&ugeth->ug_regs->rx127));
680         ugeth_info("rx255      : addr - 0x%08x, val - 0x%08x",
681                    (u32) & ugeth->ug_regs->rx255,
682                    in_be32(&ugeth->ug_regs->rx255));
683         ugeth_info("txok       : addr - 0x%08x, val - 0x%08x",
684                    (u32) & ugeth->ug_regs->txok,
685                    in_be32(&ugeth->ug_regs->txok));
686         ugeth_info("txcf       : addr - 0x%08x, val - 0x%04x",
687                    (u32) & ugeth->ug_regs->txcf,
688                    in_be16(&ugeth->ug_regs->txcf));
689         ugeth_info("tmca       : addr - 0x%08x, val - 0x%08x",
690                    (u32) & ugeth->ug_regs->tmca,
691                    in_be32(&ugeth->ug_regs->tmca));
692         ugeth_info("tbca       : addr - 0x%08x, val - 0x%08x",
693                    (u32) & ugeth->ug_regs->tbca,
694                    in_be32(&ugeth->ug_regs->tbca));
695         ugeth_info("rxfok      : addr - 0x%08x, val - 0x%08x",
696                    (u32) & ugeth->ug_regs->rxfok,
697                    in_be32(&ugeth->ug_regs->rxfok));
698         ugeth_info("rxbok      : addr - 0x%08x, val - 0x%08x",
699                    (u32) & ugeth->ug_regs->rxbok,
700                    in_be32(&ugeth->ug_regs->rxbok));
701         ugeth_info("rbyt       : addr - 0x%08x, val - 0x%08x",
702                    (u32) & ugeth->ug_regs->rbyt,
703                    in_be32(&ugeth->ug_regs->rbyt));
704         ugeth_info("rmca       : addr - 0x%08x, val - 0x%08x",
705                    (u32) & ugeth->ug_regs->rmca,
706                    in_be32(&ugeth->ug_regs->rmca));
707         ugeth_info("rbca       : addr - 0x%08x, val - 0x%08x",
708                    (u32) & ugeth->ug_regs->rbca,
709                    in_be32(&ugeth->ug_regs->rbca));
710         ugeth_info("scar       : addr - 0x%08x, val - 0x%08x",
711                    (u32) & ugeth->ug_regs->scar,
712                    in_be32(&ugeth->ug_regs->scar));
713         ugeth_info("scam       : addr - 0x%08x, val - 0x%08x",
714                    (u32) & ugeth->ug_regs->scam,
715                    in_be32(&ugeth->ug_regs->scam));
716
717         if (ugeth->p_thread_data_tx) {
718                 int numThreadsTxNumerical;
719                 switch (ugeth->ug_info->numThreadsTx) {
720                 case UCC_GETH_NUM_OF_THREADS_1:
721                         numThreadsTxNumerical = 1;
722                         break;
723                 case UCC_GETH_NUM_OF_THREADS_2:
724                         numThreadsTxNumerical = 2;
725                         break;
726                 case UCC_GETH_NUM_OF_THREADS_4:
727                         numThreadsTxNumerical = 4;
728                         break;
729                 case UCC_GETH_NUM_OF_THREADS_6:
730                         numThreadsTxNumerical = 6;
731                         break;
732                 case UCC_GETH_NUM_OF_THREADS_8:
733                         numThreadsTxNumerical = 8;
734                         break;
735                 default:
736                         numThreadsTxNumerical = 0;
737                         break;
738                 }
739
740                 ugeth_info("Thread data TXs:");
741                 ugeth_info("Base address: 0x%08x",
742                            (u32) ugeth->p_thread_data_tx);
743                 for (i = 0; i < numThreadsTxNumerical; i++) {
744                         ugeth_info("Thread data TX[%d]:", i);
745                         ugeth_info("Base address: 0x%08x",
746                                    (u32) & ugeth->p_thread_data_tx[i]);
747                         mem_disp((u8 *) & ugeth->p_thread_data_tx[i],
748                                  sizeof(struct ucc_geth_thread_data_tx));
749                 }
750         }
751         if (ugeth->p_thread_data_rx) {
752                 int numThreadsRxNumerical;
753                 switch (ugeth->ug_info->numThreadsRx) {
754                 case UCC_GETH_NUM_OF_THREADS_1:
755                         numThreadsRxNumerical = 1;
756                         break;
757                 case UCC_GETH_NUM_OF_THREADS_2:
758                         numThreadsRxNumerical = 2;
759                         break;
760                 case UCC_GETH_NUM_OF_THREADS_4:
761                         numThreadsRxNumerical = 4;
762                         break;
763                 case UCC_GETH_NUM_OF_THREADS_6:
764                         numThreadsRxNumerical = 6;
765                         break;
766                 case UCC_GETH_NUM_OF_THREADS_8:
767                         numThreadsRxNumerical = 8;
768                         break;
769                 default:
770                         numThreadsRxNumerical = 0;
771                         break;
772                 }
773
774                 ugeth_info("Thread data RX:");
775                 ugeth_info("Base address: 0x%08x",
776                            (u32) ugeth->p_thread_data_rx);
777                 for (i = 0; i < numThreadsRxNumerical; i++) {
778                         ugeth_info("Thread data RX[%d]:", i);
779                         ugeth_info("Base address: 0x%08x",
780                                    (u32) & ugeth->p_thread_data_rx[i]);
781                         mem_disp((u8 *) & ugeth->p_thread_data_rx[i],
782                                  sizeof(struct ucc_geth_thread_data_rx));
783                 }
784         }
785         if (ugeth->p_exf_glbl_param) {
786                 ugeth_info("EXF global param:");
787                 ugeth_info("Base address: 0x%08x",
788                            (u32) ugeth->p_exf_glbl_param);
789                 mem_disp((u8 *) ugeth->p_exf_glbl_param,
790                          sizeof(*ugeth->p_exf_glbl_param));
791         }
792         if (ugeth->p_tx_glbl_pram) {
793                 ugeth_info("TX global param:");
794                 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_tx_glbl_pram);
795                 ugeth_info("temoder      : addr - 0x%08x, val - 0x%04x",
796                            (u32) & ugeth->p_tx_glbl_pram->temoder,
797                            in_be16(&ugeth->p_tx_glbl_pram->temoder));
798                 ugeth_info("sqptr        : addr - 0x%08x, val - 0x%08x",
799                            (u32) & ugeth->p_tx_glbl_pram->sqptr,
800                            in_be32(&ugeth->p_tx_glbl_pram->sqptr));
801                 ugeth_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x",
802                            (u32) & ugeth->p_tx_glbl_pram->schedulerbasepointer,
803                            in_be32(&ugeth->p_tx_glbl_pram->
804                                    schedulerbasepointer));
805                 ugeth_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x",
806                            (u32) & ugeth->p_tx_glbl_pram->txrmonbaseptr,
807                            in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr));
808                 ugeth_info("tstate       : addr - 0x%08x, val - 0x%08x",
809                            (u32) & ugeth->p_tx_glbl_pram->tstate,
810                            in_be32(&ugeth->p_tx_glbl_pram->tstate));
811                 ugeth_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x",
812                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[0],
813                            ugeth->p_tx_glbl_pram->iphoffset[0]);
814                 ugeth_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x",
815                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[1],
816                            ugeth->p_tx_glbl_pram->iphoffset[1]);
817                 ugeth_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x",
818                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[2],
819                            ugeth->p_tx_glbl_pram->iphoffset[2]);
820                 ugeth_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x",
821                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[3],
822                            ugeth->p_tx_glbl_pram->iphoffset[3]);
823                 ugeth_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x",
824                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[4],
825                            ugeth->p_tx_glbl_pram->iphoffset[4]);
826                 ugeth_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x",
827                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[5],
828                            ugeth->p_tx_glbl_pram->iphoffset[5]);
829                 ugeth_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x",
830                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[6],
831                            ugeth->p_tx_glbl_pram->iphoffset[6]);
832                 ugeth_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x",
833                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[7],
834                            ugeth->p_tx_glbl_pram->iphoffset[7]);
835                 ugeth_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x",
836                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[0],
837                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0]));
838                 ugeth_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x",
839                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[1],
840                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1]));
841                 ugeth_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x",
842                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[2],
843                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2]));
844                 ugeth_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x",
845                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[3],
846                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3]));
847                 ugeth_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x",
848                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[4],
849                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4]));
850                 ugeth_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x",
851                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[5],
852                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5]));
853                 ugeth_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x",
854                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[6],
855                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6]));
856                 ugeth_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x",
857                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[7],
858                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7]));
859                 ugeth_info("tqptr        : addr - 0x%08x, val - 0x%08x",
860                            (u32) & ugeth->p_tx_glbl_pram->tqptr,
861                            in_be32(&ugeth->p_tx_glbl_pram->tqptr));
862         }
863         if (ugeth->p_rx_glbl_pram) {
864                 ugeth_info("RX global param:");
865                 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_glbl_pram);
866                 ugeth_info("remoder         : addr - 0x%08x, val - 0x%08x",
867                            (u32) & ugeth->p_rx_glbl_pram->remoder,
868                            in_be32(&ugeth->p_rx_glbl_pram->remoder));
869                 ugeth_info("rqptr           : addr - 0x%08x, val - 0x%08x",
870                            (u32) & ugeth->p_rx_glbl_pram->rqptr,
871                            in_be32(&ugeth->p_rx_glbl_pram->rqptr));
872                 ugeth_info("typeorlen       : addr - 0x%08x, val - 0x%04x",
873                            (u32) & ugeth->p_rx_glbl_pram->typeorlen,
874                            in_be16(&ugeth->p_rx_glbl_pram->typeorlen));
875                 ugeth_info("rxgstpack       : addr - 0x%08x, val - 0x%02x",
876                            (u32) & ugeth->p_rx_glbl_pram->rxgstpack,
877                            ugeth->p_rx_glbl_pram->rxgstpack);
878                 ugeth_info("rxrmonbaseptr   : addr - 0x%08x, val - 0x%08x",
879                            (u32) & ugeth->p_rx_glbl_pram->rxrmonbaseptr,
880                            in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr));
881                 ugeth_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x",
882                            (u32) & ugeth->p_rx_glbl_pram->intcoalescingptr,
883                            in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr));
884                 ugeth_info("rstate          : addr - 0x%08x, val - 0x%02x",
885                            (u32) & ugeth->p_rx_glbl_pram->rstate,
886                            ugeth->p_rx_glbl_pram->rstate);
887                 ugeth_info("mrblr           : addr - 0x%08x, val - 0x%04x",
888                            (u32) & ugeth->p_rx_glbl_pram->mrblr,
889                            in_be16(&ugeth->p_rx_glbl_pram->mrblr));
890                 ugeth_info("rbdqptr         : addr - 0x%08x, val - 0x%08x",
891                            (u32) & ugeth->p_rx_glbl_pram->rbdqptr,
892                            in_be32(&ugeth->p_rx_glbl_pram->rbdqptr));
893                 ugeth_info("mflr            : addr - 0x%08x, val - 0x%04x",
894                            (u32) & ugeth->p_rx_glbl_pram->mflr,
895                            in_be16(&ugeth->p_rx_glbl_pram->mflr));
896                 ugeth_info("minflr          : addr - 0x%08x, val - 0x%04x",
897                            (u32) & ugeth->p_rx_glbl_pram->minflr,
898                            in_be16(&ugeth->p_rx_glbl_pram->minflr));
899                 ugeth_info("maxd1           : addr - 0x%08x, val - 0x%04x",
900                            (u32) & ugeth->p_rx_glbl_pram->maxd1,
901                            in_be16(&ugeth->p_rx_glbl_pram->maxd1));
902                 ugeth_info("maxd2           : addr - 0x%08x, val - 0x%04x",
903                            (u32) & ugeth->p_rx_glbl_pram->maxd2,
904                            in_be16(&ugeth->p_rx_glbl_pram->maxd2));
905                 ugeth_info("ecamptr         : addr - 0x%08x, val - 0x%08x",
906                            (u32) & ugeth->p_rx_glbl_pram->ecamptr,
907                            in_be32(&ugeth->p_rx_glbl_pram->ecamptr));
908                 ugeth_info("l2qt            : addr - 0x%08x, val - 0x%08x",
909                            (u32) & ugeth->p_rx_glbl_pram->l2qt,
910                            in_be32(&ugeth->p_rx_glbl_pram->l2qt));
911                 ugeth_info("l3qt[0]         : addr - 0x%08x, val - 0x%08x",
912                            (u32) & ugeth->p_rx_glbl_pram->l3qt[0],
913                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[0]));
914                 ugeth_info("l3qt[1]         : addr - 0x%08x, val - 0x%08x",
915                            (u32) & ugeth->p_rx_glbl_pram->l3qt[1],
916                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[1]));
917                 ugeth_info("l3qt[2]         : addr - 0x%08x, val - 0x%08x",
918                            (u32) & ugeth->p_rx_glbl_pram->l3qt[2],
919                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[2]));
920                 ugeth_info("l3qt[3]         : addr - 0x%08x, val - 0x%08x",
921                            (u32) & ugeth->p_rx_glbl_pram->l3qt[3],
922                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[3]));
923                 ugeth_info("l3qt[4]         : addr - 0x%08x, val - 0x%08x",
924                            (u32) & ugeth->p_rx_glbl_pram->l3qt[4],
925                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[4]));
926                 ugeth_info("l3qt[5]         : addr - 0x%08x, val - 0x%08x",
927                            (u32) & ugeth->p_rx_glbl_pram->l3qt[5],
928                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[5]));
929                 ugeth_info("l3qt[6]         : addr - 0x%08x, val - 0x%08x",
930                            (u32) & ugeth->p_rx_glbl_pram->l3qt[6],
931                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[6]));
932                 ugeth_info("l3qt[7]         : addr - 0x%08x, val - 0x%08x",
933                            (u32) & ugeth->p_rx_glbl_pram->l3qt[7],
934                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[7]));
935                 ugeth_info("vlantype        : addr - 0x%08x, val - 0x%04x",
936                            (u32) & ugeth->p_rx_glbl_pram->vlantype,
937                            in_be16(&ugeth->p_rx_glbl_pram->vlantype));
938                 ugeth_info("vlantci         : addr - 0x%08x, val - 0x%04x",
939                            (u32) & ugeth->p_rx_glbl_pram->vlantci,
940                            in_be16(&ugeth->p_rx_glbl_pram->vlantci));
941                 for (i = 0; i < 64; i++)
942                         ugeth_info
943                     ("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x",
944                              i,
945                              (u32) & ugeth->p_rx_glbl_pram->addressfiltering[i],
946                              ugeth->p_rx_glbl_pram->addressfiltering[i]);
947                 ugeth_info("exfGlobalParam  : addr - 0x%08x, val - 0x%08x",
948                            (u32) & ugeth->p_rx_glbl_pram->exfGlobalParam,
949                            in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam));
950         }
951         if (ugeth->p_send_q_mem_reg) {
952                 ugeth_info("Send Q memory registers:");
953                 ugeth_info("Base address: 0x%08x",
954                            (u32) ugeth->p_send_q_mem_reg);
955                 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
956                         ugeth_info("SQQD[%d]:", i);
957                         ugeth_info("Base address: 0x%08x",
958                                    (u32) & ugeth->p_send_q_mem_reg->sqqd[i]);
959                         mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i],
960                                  sizeof(struct ucc_geth_send_queue_qd));
961                 }
962         }
963         if (ugeth->p_scheduler) {
964                 ugeth_info("Scheduler:");
965                 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_scheduler);
966                 mem_disp((u8 *) ugeth->p_scheduler,
967                          sizeof(*ugeth->p_scheduler));
968         }
969         if (ugeth->p_tx_fw_statistics_pram) {
970                 ugeth_info("TX FW statistics pram:");
971                 ugeth_info("Base address: 0x%08x",
972                            (u32) ugeth->p_tx_fw_statistics_pram);
973                 mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram,
974                          sizeof(*ugeth->p_tx_fw_statistics_pram));
975         }
976         if (ugeth->p_rx_fw_statistics_pram) {
977                 ugeth_info("RX FW statistics pram:");
978                 ugeth_info("Base address: 0x%08x",
979                            (u32) ugeth->p_rx_fw_statistics_pram);
980                 mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram,
981                          sizeof(*ugeth->p_rx_fw_statistics_pram));
982         }
983         if (ugeth->p_rx_irq_coalescing_tbl) {
984                 ugeth_info("RX IRQ coalescing tables:");
985                 ugeth_info("Base address: 0x%08x",
986                            (u32) ugeth->p_rx_irq_coalescing_tbl);
987                 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
988                         ugeth_info("RX IRQ coalescing table entry[%d]:", i);
989                         ugeth_info("Base address: 0x%08x",
990                                    (u32) & ugeth->p_rx_irq_coalescing_tbl->
991                                    coalescingentry[i]);
992                         ugeth_info
993                 ("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x",
994                              (u32) & ugeth->p_rx_irq_coalescing_tbl->
995                              coalescingentry[i].interruptcoalescingmaxvalue,
996                              in_be32(&ugeth->p_rx_irq_coalescing_tbl->
997                                      coalescingentry[i].
998                                      interruptcoalescingmaxvalue));
999                         ugeth_info
1000                 ("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x",
1001                              (u32) & ugeth->p_rx_irq_coalescing_tbl->
1002                              coalescingentry[i].interruptcoalescingcounter,
1003                              in_be32(&ugeth->p_rx_irq_coalescing_tbl->
1004                                      coalescingentry[i].
1005                                      interruptcoalescingcounter));
1006                 }
1007         }
1008         if (ugeth->p_rx_bd_qs_tbl) {
1009                 ugeth_info("RX BD QS tables:");
1010                 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_bd_qs_tbl);
1011                 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1012                         ugeth_info("RX BD QS table[%d]:", i);
1013                         ugeth_info("Base address: 0x%08x",
1014                                    (u32) & ugeth->p_rx_bd_qs_tbl[i]);
1015                         ugeth_info
1016                             ("bdbaseptr        : addr - 0x%08x, val - 0x%08x",
1017                              (u32) & ugeth->p_rx_bd_qs_tbl[i].bdbaseptr,
1018                              in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr));
1019                         ugeth_info
1020                             ("bdptr            : addr - 0x%08x, val - 0x%08x",
1021                              (u32) & ugeth->p_rx_bd_qs_tbl[i].bdptr,
1022                              in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr));
1023                         ugeth_info
1024                             ("externalbdbaseptr: addr - 0x%08x, val - 0x%08x",
1025                              (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
1026                              in_be32(&ugeth->p_rx_bd_qs_tbl[i].
1027                                      externalbdbaseptr));
1028                         ugeth_info
1029                             ("externalbdptr    : addr - 0x%08x, val - 0x%08x",
1030                              (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdptr,
1031                              in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr));
1032                         ugeth_info("ucode RX Prefetched BDs:");
1033                         ugeth_info("Base address: 0x%08x",
1034                                    (u32)
1035                                    qe_muram_addr(in_be32
1036                                                  (&ugeth->p_rx_bd_qs_tbl[i].
1037                                                   bdbaseptr)));
1038                         mem_disp((u8 *)
1039                                  qe_muram_addr(in_be32
1040                                                (&ugeth->p_rx_bd_qs_tbl[i].
1041                                                 bdbaseptr)),
1042                                  sizeof(struct ucc_geth_rx_prefetched_bds));
1043                 }
1044         }
1045         if (ugeth->p_init_enet_param_shadow) {
1046                 int size;
1047                 ugeth_info("Init enet param shadow:");
1048                 ugeth_info("Base address: 0x%08x",
1049                            (u32) ugeth->p_init_enet_param_shadow);
1050                 mem_disp((u8 *) ugeth->p_init_enet_param_shadow,
1051                          sizeof(*ugeth->p_init_enet_param_shadow));
1052
1053                 size = sizeof(struct ucc_geth_thread_rx_pram);
1054                 if (ugeth->ug_info->rxExtendedFiltering) {
1055                         size +=
1056                             THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
1057                         if (ugeth->ug_info->largestexternallookupkeysize ==
1058                             QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
1059                                 size +=
1060                         THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
1061                         if (ugeth->ug_info->largestexternallookupkeysize ==
1062                             QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
1063                                 size +=
1064                         THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
1065                 }
1066
1067                 dump_init_enet_entries(ugeth,
1068                                        &(ugeth->p_init_enet_param_shadow->
1069                                          txthread[0]),
1070                                        ENET_INIT_PARAM_MAX_ENTRIES_TX,
1071                                        sizeof(struct ucc_geth_thread_tx_pram),
1072                                        ugeth->ug_info->riscTx, 0);
1073                 dump_init_enet_entries(ugeth,
1074                                        &(ugeth->p_init_enet_param_shadow->
1075                                          rxthread[0]),
1076                                        ENET_INIT_PARAM_MAX_ENTRIES_RX, size,
1077                                        ugeth->ug_info->riscRx, 1);
1078         }
1079 }
1080 #endif /* DEBUG */
1081
1082 static void init_default_reg_vals(u32 __iomem *upsmr_register,
1083                                   u32 __iomem *maccfg1_register,
1084                                   u32 __iomem *maccfg2_register)
1085 {
1086         out_be32(upsmr_register, UCC_GETH_UPSMR_INIT);
1087         out_be32(maccfg1_register, UCC_GETH_MACCFG1_INIT);
1088         out_be32(maccfg2_register, UCC_GETH_MACCFG2_INIT);
1089 }
1090
1091 static int init_half_duplex_params(int alt_beb,
1092                                    int back_pressure_no_backoff,
1093                                    int no_backoff,
1094                                    int excess_defer,
1095                                    u8 alt_beb_truncation,
1096                                    u8 max_retransmissions,
1097                                    u8 collision_window,
1098                                    u32 __iomem *hafdup_register)
1099 {
1100         u32 value = 0;
1101
1102         if ((alt_beb_truncation > HALFDUP_ALT_BEB_TRUNCATION_MAX) ||
1103             (max_retransmissions > HALFDUP_MAX_RETRANSMISSION_MAX) ||
1104             (collision_window > HALFDUP_COLLISION_WINDOW_MAX))
1105                 return -EINVAL;
1106
1107         value = (u32) (alt_beb_truncation << HALFDUP_ALT_BEB_TRUNCATION_SHIFT);
1108
1109         if (alt_beb)
1110                 value |= HALFDUP_ALT_BEB;
1111         if (back_pressure_no_backoff)
1112                 value |= HALFDUP_BACK_PRESSURE_NO_BACKOFF;
1113         if (no_backoff)
1114                 value |= HALFDUP_NO_BACKOFF;
1115         if (excess_defer)
1116                 value |= HALFDUP_EXCESSIVE_DEFER;
1117
1118         value |= (max_retransmissions << HALFDUP_MAX_RETRANSMISSION_SHIFT);
1119
1120         value |= collision_window;
1121
1122         out_be32(hafdup_register, value);
1123         return 0;
1124 }
1125
1126 static int init_inter_frame_gap_params(u8 non_btb_cs_ipg,
1127                                        u8 non_btb_ipg,
1128                                        u8 min_ifg,
1129                                        u8 btb_ipg,
1130                                        u32 __iomem *ipgifg_register)
1131 {
1132         u32 value = 0;
1133
1134         /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back
1135         IPG part 2 */
1136         if (non_btb_cs_ipg > non_btb_ipg)
1137                 return -EINVAL;
1138
1139         if ((non_btb_cs_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX) ||
1140             (non_btb_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX) ||
1141             /*(min_ifg        > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */
1142             (btb_ipg > IPGIFG_BACK_TO_BACK_IFG_MAX))
1143                 return -EINVAL;
1144
1145         value |=
1146             ((non_btb_cs_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT) &
1147              IPGIFG_NBTB_CS_IPG_MASK);
1148         value |=
1149             ((non_btb_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT) &
1150              IPGIFG_NBTB_IPG_MASK);
1151         value |=
1152             ((min_ifg << IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT) &
1153              IPGIFG_MIN_IFG_MASK);
1154         value |= (btb_ipg & IPGIFG_BTB_IPG_MASK);
1155
1156         out_be32(ipgifg_register, value);
1157         return 0;
1158 }
1159
1160 int init_flow_control_params(u32 automatic_flow_control_mode,
1161                                     int rx_flow_control_enable,
1162                                     int tx_flow_control_enable,
1163                                     u16 pause_period,
1164                                     u16 extension_field,
1165                                     u32 __iomem *upsmr_register,
1166                                     u32 __iomem *uempr_register,
1167                                     u32 __iomem *maccfg1_register)
1168 {
1169         u32 value = 0;
1170
1171         /* Set UEMPR register */
1172         value = (u32) pause_period << UEMPR_PAUSE_TIME_VALUE_SHIFT;
1173         value |= (u32) extension_field << UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT;
1174         out_be32(uempr_register, value);
1175
1176         /* Set UPSMR register */
1177         setbits32(upsmr_register, automatic_flow_control_mode);
1178
1179         value = in_be32(maccfg1_register);
1180         if (rx_flow_control_enable)
1181                 value |= MACCFG1_FLOW_RX;
1182         if (tx_flow_control_enable)
1183                 value |= MACCFG1_FLOW_TX;
1184         out_be32(maccfg1_register, value);
1185
1186         return 0;
1187 }
1188
1189 static int init_hw_statistics_gathering_mode(int enable_hardware_statistics,
1190                                              int auto_zero_hardware_statistics,
1191                                              u32 __iomem *upsmr_register,
1192                                              u16 __iomem *uescr_register)
1193 {
1194         u16 uescr_value = 0;
1195
1196         /* Enable hardware statistics gathering if requested */
1197         if (enable_hardware_statistics)
1198                 setbits32(upsmr_register, UCC_GETH_UPSMR_HSE);
1199
1200         /* Clear hardware statistics counters */
1201         uescr_value = in_be16(uescr_register);
1202         uescr_value |= UESCR_CLRCNT;
1203         /* Automatically zero hardware statistics counters on read,
1204         if requested */
1205         if (auto_zero_hardware_statistics)
1206                 uescr_value |= UESCR_AUTOZ;
1207         out_be16(uescr_register, uescr_value);
1208
1209         return 0;
1210 }
1211
1212 static int init_firmware_statistics_gathering_mode(int
1213                 enable_tx_firmware_statistics,
1214                 int enable_rx_firmware_statistics,
1215                 u32 __iomem *tx_rmon_base_ptr,
1216                 u32 tx_firmware_statistics_structure_address,
1217                 u32 __iomem *rx_rmon_base_ptr,
1218                 u32 rx_firmware_statistics_structure_address,
1219                 u16 __iomem *temoder_register,
1220                 u32 __iomem *remoder_register)
1221 {
1222         /* Note: this function does not check if */
1223         /* the parameters it receives are NULL   */
1224
1225         if (enable_tx_firmware_statistics) {
1226                 out_be32(tx_rmon_base_ptr,
1227                          tx_firmware_statistics_structure_address);
1228                 setbits16(temoder_register, TEMODER_TX_RMON_STATISTICS_ENABLE);
1229         }
1230
1231         if (enable_rx_firmware_statistics) {
1232                 out_be32(rx_rmon_base_ptr,
1233                          rx_firmware_statistics_structure_address);
1234                 setbits32(remoder_register, REMODER_RX_RMON_STATISTICS_ENABLE);
1235         }
1236
1237         return 0;
1238 }
1239
1240 static int init_mac_station_addr_regs(u8 address_byte_0,
1241                                       u8 address_byte_1,
1242                                       u8 address_byte_2,
1243                                       u8 address_byte_3,
1244                                       u8 address_byte_4,
1245                                       u8 address_byte_5,
1246                                       u32 __iomem *macstnaddr1_register,
1247                                       u32 __iomem *macstnaddr2_register)
1248 {
1249         u32 value = 0;
1250
1251         /* Example: for a station address of 0x12345678ABCD, */
1252         /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */
1253
1254         /* MACSTNADDR1 Register: */
1255
1256         /* 0                      7   8                      15  */
1257         /* station address byte 5     station address byte 4     */
1258         /* 16                     23  24                     31  */
1259         /* station address byte 3     station address byte 2     */
1260         value |= (u32) ((address_byte_2 << 0) & 0x000000FF);
1261         value |= (u32) ((address_byte_3 << 8) & 0x0000FF00);
1262         value |= (u32) ((address_byte_4 << 16) & 0x00FF0000);
1263         value |= (u32) ((address_byte_5 << 24) & 0xFF000000);
1264
1265         out_be32(macstnaddr1_register, value);
1266
1267         /* MACSTNADDR2 Register: */
1268
1269         /* 0                      7   8                      15  */
1270         /* station address byte 1     station address byte 0     */
1271         /* 16                     23  24                     31  */
1272         /*         reserved                   reserved           */
1273         value = 0;
1274         value |= (u32) ((address_byte_0 << 16) & 0x00FF0000);
1275         value |= (u32) ((address_byte_1 << 24) & 0xFF000000);
1276
1277         out_be32(macstnaddr2_register, value);
1278
1279         return 0;
1280 }
1281
1282 static int init_check_frame_length_mode(int length_check,
1283                                         u32 __iomem *maccfg2_register)
1284 {
1285         u32 value = 0;
1286
1287         value = in_be32(maccfg2_register);
1288
1289         if (length_check)
1290                 value |= MACCFG2_LC;
1291         else
1292                 value &= ~MACCFG2_LC;
1293
1294         out_be32(maccfg2_register, value);
1295         return 0;
1296 }
1297
1298 static int init_preamble_length(u8 preamble_length,
1299                                 u32 __iomem *maccfg2_register)
1300 {
1301         if ((preamble_length < 3) || (preamble_length > 7))
1302                 return -EINVAL;
1303
1304         clrsetbits_be32(maccfg2_register, MACCFG2_PREL_MASK,
1305                         preamble_length << MACCFG2_PREL_SHIFT);
1306
1307         return 0;
1308 }
1309
1310 static int init_rx_parameters(int reject_broadcast,
1311                               int receive_short_frames,
1312                               int promiscuous, u32 __iomem *upsmr_register)
1313 {
1314         u32 value = 0;
1315
1316         value = in_be32(upsmr_register);
1317
1318         if (reject_broadcast)
1319                 value |= UCC_GETH_UPSMR_BRO;
1320         else
1321                 value &= ~UCC_GETH_UPSMR_BRO;
1322
1323         if (receive_short_frames)
1324                 value |= UCC_GETH_UPSMR_RSH;
1325         else
1326                 value &= ~UCC_GETH_UPSMR_RSH;
1327
1328         if (promiscuous)
1329                 value |= UCC_GETH_UPSMR_PRO;
1330         else
1331                 value &= ~UCC_GETH_UPSMR_PRO;
1332
1333         out_be32(upsmr_register, value);
1334
1335         return 0;
1336 }
1337
1338 static int init_max_rx_buff_len(u16 max_rx_buf_len,
1339                                 u16 __iomem *mrblr_register)
1340 {
1341         /* max_rx_buf_len value must be a multiple of 128 */
1342         if ((max_rx_buf_len == 0)
1343             || (max_rx_buf_len % UCC_GETH_MRBLR_ALIGNMENT))
1344                 return -EINVAL;
1345
1346         out_be16(mrblr_register, max_rx_buf_len);
1347         return 0;
1348 }
1349
1350 static int init_min_frame_len(u16 min_frame_length,
1351                               u16 __iomem *minflr_register,
1352                               u16 __iomem *mrblr_register)
1353 {
1354         u16 mrblr_value = 0;
1355
1356         mrblr_value = in_be16(mrblr_register);
1357         if (min_frame_length >= (mrblr_value - 4))
1358                 return -EINVAL;
1359
1360         out_be16(minflr_register, min_frame_length);
1361         return 0;
1362 }
1363
1364 static int adjust_enet_interface(struct ucc_geth_private *ugeth)
1365 {
1366         struct ucc_geth_info *ug_info;
1367         struct ucc_geth __iomem *ug_regs;
1368         struct ucc_fast __iomem *uf_regs;
1369         int ret_val;
1370         u32 upsmr, maccfg2, tbiBaseAddress;
1371         u16 value;
1372
1373         ugeth_vdbg("%s: IN", __func__);
1374
1375         ug_info = ugeth->ug_info;
1376         ug_regs = ugeth->ug_regs;
1377         uf_regs = ugeth->uccf->uf_regs;
1378
1379         /*                    Set MACCFG2                    */
1380         maccfg2 = in_be32(&ug_regs->maccfg2);
1381         maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
1382         if ((ugeth->max_speed == SPEED_10) ||
1383             (ugeth->max_speed == SPEED_100))
1384                 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
1385         else if (ugeth->max_speed == SPEED_1000)
1386                 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
1387         maccfg2 |= ug_info->padAndCrc;
1388         out_be32(&ug_regs->maccfg2, maccfg2);
1389
1390         /*                    Set UPSMR                      */
1391         upsmr = in_be32(&uf_regs->upsmr);
1392         upsmr &= ~(UCC_GETH_UPSMR_RPM | UCC_GETH_UPSMR_R10M |
1393                    UCC_GETH_UPSMR_TBIM | UCC_GETH_UPSMR_RMM);
1394         if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1395             (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1396             (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1397             (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1398             (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
1399             (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1400                 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RMII)
1401                         upsmr |= UCC_GETH_UPSMR_RPM;
1402                 switch (ugeth->max_speed) {
1403                 case SPEED_10:
1404                         upsmr |= UCC_GETH_UPSMR_R10M;
1405                         /* FALLTHROUGH */
1406                 case SPEED_100:
1407                         if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI)
1408                                 upsmr |= UCC_GETH_UPSMR_RMM;
1409                 }
1410         }
1411         if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1412             (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1413                 upsmr |= UCC_GETH_UPSMR_TBIM;
1414         }
1415         if ((ugeth->phy_interface == PHY_INTERFACE_MODE_SGMII))
1416                 upsmr |= UCC_GETH_UPSMR_SGMM;
1417
1418         out_be32(&uf_regs->upsmr, upsmr);
1419
1420         /* Disable autonegotiation in tbi mode, because by default it
1421         comes up in autonegotiation mode. */
1422         /* Note that this depends on proper setting in utbipar register. */
1423         if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1424             (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1425                 tbiBaseAddress = in_be32(&ug_regs->utbipar);
1426                 tbiBaseAddress &= UTBIPAR_PHY_ADDRESS_MASK;
1427                 tbiBaseAddress >>= UTBIPAR_PHY_ADDRESS_SHIFT;
1428                 value = ugeth->phydev->bus->read(ugeth->phydev->bus,
1429                                 (u8) tbiBaseAddress, ENET_TBI_MII_CR);
1430                 value &= ~0x1000;       /* Turn off autonegotiation */
1431                 ugeth->phydev->bus->write(ugeth->phydev->bus,
1432                                 (u8) tbiBaseAddress, ENET_TBI_MII_CR, value);
1433         }
1434
1435         init_check_frame_length_mode(ug_info->lengthCheckRx, &ug_regs->maccfg2);
1436
1437         ret_val = init_preamble_length(ug_info->prel, &ug_regs->maccfg2);
1438         if (ret_val != 0) {
1439                 if (netif_msg_probe(ugeth))
1440                         ugeth_err("%s: Preamble length must be between 3 and 7 inclusive.",
1441                              __func__);
1442                 return ret_val;
1443         }
1444
1445         return 0;
1446 }
1447
1448 /* Called every time the controller might need to be made
1449  * aware of new link state.  The PHY code conveys this
1450  * information through variables in the ugeth structure, and this
1451  * function converts those variables into the appropriate
1452  * register values, and can bring down the device if needed.
1453  */
1454
1455 static void adjust_link(struct net_device *dev)
1456 {
1457         struct ucc_geth_private *ugeth = netdev_priv(dev);
1458         struct ucc_geth __iomem *ug_regs;
1459         struct ucc_fast __iomem *uf_regs;
1460         struct phy_device *phydev = ugeth->phydev;
1461         unsigned long flags;
1462         int new_state = 0;
1463
1464         ug_regs = ugeth->ug_regs;
1465         uf_regs = ugeth->uccf->uf_regs;
1466
1467         spin_lock_irqsave(&ugeth->lock, flags);
1468
1469         if (phydev->link) {
1470                 u32 tempval = in_be32(&ug_regs->maccfg2);
1471                 u32 upsmr = in_be32(&uf_regs->upsmr);
1472                 /* Now we make sure that we can be in full duplex mode.
1473                  * If not, we operate in half-duplex mode. */
1474                 if (phydev->duplex != ugeth->oldduplex) {
1475                         new_state = 1;
1476                         if (!(phydev->duplex))
1477                                 tempval &= ~(MACCFG2_FDX);
1478                         else
1479                                 tempval |= MACCFG2_FDX;
1480                         ugeth->oldduplex = phydev->duplex;
1481                 }
1482
1483                 if (phydev->speed != ugeth->oldspeed) {
1484                         new_state = 1;
1485                         switch (phydev->speed) {
1486                         case SPEED_1000:
1487                                 tempval = ((tempval &
1488                                             ~(MACCFG2_INTERFACE_MODE_MASK)) |
1489                                             MACCFG2_INTERFACE_MODE_BYTE);
1490                                 break;
1491                         case SPEED_100:
1492                         case SPEED_10:
1493                                 tempval = ((tempval &
1494                                             ~(MACCFG2_INTERFACE_MODE_MASK)) |
1495                                             MACCFG2_INTERFACE_MODE_NIBBLE);
1496                                 /* if reduced mode, re-set UPSMR.R10M */
1497                                 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1498                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1499                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1500                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1501                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
1502                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1503                                         if (phydev->speed == SPEED_10)
1504                                                 upsmr |= UCC_GETH_UPSMR_R10M;
1505                                         else
1506                                                 upsmr &= ~UCC_GETH_UPSMR_R10M;
1507                                 }
1508                                 break;
1509                         default:
1510                                 if (netif_msg_link(ugeth))
1511                                         ugeth_warn(
1512                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!",
1513                                                 dev->name, phydev->speed);
1514                                 break;
1515                         }
1516                         ugeth->oldspeed = phydev->speed;
1517                 }
1518
1519                 out_be32(&ug_regs->maccfg2, tempval);
1520                 out_be32(&uf_regs->upsmr, upsmr);
1521
1522                 if (!ugeth->oldlink) {
1523                         new_state = 1;
1524                         ugeth->oldlink = 1;
1525                 }
1526         } else if (ugeth->oldlink) {
1527                         new_state = 1;
1528                         ugeth->oldlink = 0;
1529                         ugeth->oldspeed = 0;
1530                         ugeth->oldduplex = -1;
1531         }
1532
1533         if (new_state && netif_msg_link(ugeth))
1534                 phy_print_status(phydev);
1535
1536         spin_unlock_irqrestore(&ugeth->lock, flags);
1537 }
1538
1539 /* Configure the PHY for dev.
1540  * returns 0 if success.  -1 if failure
1541  */
1542 static int init_phy(struct net_device *dev)
1543 {
1544         struct ucc_geth_private *priv = netdev_priv(dev);
1545         struct ucc_geth_info *ug_info = priv->ug_info;
1546         struct phy_device *phydev;
1547
1548         priv->oldlink = 0;
1549         priv->oldspeed = 0;
1550         priv->oldduplex = -1;
1551
1552         if (!ug_info->phy_node)
1553                 return 0;
1554
1555         phydev = of_phy_connect(dev, ug_info->phy_node, &adjust_link, 0,
1556                                 priv->phy_interface);
1557         if (!phydev) {
1558                 printk("%s: Could not attach to PHY\n", dev->name);
1559                 return -ENODEV;
1560         }
1561
1562         if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII)
1563                 uec_configure_serdes(dev);
1564
1565         phydev->supported &= (ADVERTISED_10baseT_Half |
1566                                  ADVERTISED_10baseT_Full |
1567                                  ADVERTISED_100baseT_Half |
1568                                  ADVERTISED_100baseT_Full);
1569
1570         if (priv->max_speed == SPEED_1000)
1571                 phydev->supported |= ADVERTISED_1000baseT_Full;
1572
1573         phydev->advertising = phydev->supported;
1574
1575         priv->phydev = phydev;
1576
1577         return 0;
1578 }
1579
1580 /* Initialize TBI PHY interface for communicating with the
1581  * SERDES lynx PHY on the chip.  We communicate with this PHY
1582  * through the MDIO bus on each controller, treating it as a
1583  * "normal" PHY at the address found in the UTBIPA register.  We assume
1584  * that the UTBIPA register is valid.  Either the MDIO bus code will set
1585  * it to a value that doesn't conflict with other PHYs on the bus, or the
1586  * value doesn't matter, as there are no other PHYs on the bus.
1587  */
1588 static void uec_configure_serdes(struct net_device *dev)
1589 {
1590         struct ucc_geth_private *ugeth = netdev_priv(dev);
1591
1592         if (!ugeth->tbiphy) {
1593                 printk(KERN_WARNING "SGMII mode requires that the device "
1594                         "tree specify a tbi-handle\n");
1595         return;
1596         }
1597
1598         /*
1599          * If the link is already up, we must already be ok, and don't need to
1600          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1601          * everything for us?  Resetting it takes the link down and requires
1602          * several seconds for it to come back.
1603          */
1604         if (phy_read(ugeth->tbiphy, ENET_TBI_MII_SR) & TBISR_LSTATUS)
1605                 return;
1606
1607         /* Single clk mode, mii mode off(for serdes communication) */
1608         phy_write(ugeth->tbiphy, ENET_TBI_MII_ANA, TBIANA_SETTINGS);
1609
1610         phy_write(ugeth->tbiphy, ENET_TBI_MII_TBICON, TBICON_CLK_SELECT);
1611
1612         phy_write(ugeth->tbiphy, ENET_TBI_MII_CR, TBICR_SETTINGS);
1613
1614 }
1615
1616 static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth)
1617 {
1618         struct ucc_fast_private *uccf;
1619         u32 cecr_subblock;
1620         u32 temp;
1621         int i = 10;
1622
1623         uccf = ugeth->uccf;
1624
1625         /* Mask GRACEFUL STOP TX interrupt bit and clear it */
1626         clrbits32(uccf->p_uccm, UCC_GETH_UCCE_GRA);
1627         out_be32(uccf->p_ucce, UCC_GETH_UCCE_GRA);  /* clear by writing 1 */
1628
1629         /* Issue host command */
1630         cecr_subblock =
1631             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1632         qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
1633                      QE_CR_PROTOCOL_ETHERNET, 0);
1634
1635         /* Wait for command to complete */
1636         do {
1637                 msleep(10);
1638                 temp = in_be32(uccf->p_ucce);
1639         } while (!(temp & UCC_GETH_UCCE_GRA) && --i);
1640
1641         uccf->stopped_tx = 1;
1642
1643         return 0;
1644 }
1645
1646 static int ugeth_graceful_stop_rx(struct ucc_geth_private * ugeth)
1647 {
1648         struct ucc_fast_private *uccf;
1649         u32 cecr_subblock;
1650         u8 temp;
1651         int i = 10;
1652
1653         uccf = ugeth->uccf;
1654
1655         /* Clear acknowledge bit */
1656         temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1657         temp &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
1658         out_8(&ugeth->p_rx_glbl_pram->rxgstpack, temp);
1659
1660         /* Keep issuing command and checking acknowledge bit until
1661         it is asserted, according to spec */
1662         do {
1663                 /* Issue host command */
1664                 cecr_subblock =
1665                     ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.
1666                                                 ucc_num);
1667                 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
1668                              QE_CR_PROTOCOL_ETHERNET, 0);
1669                 msleep(10);
1670                 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1671         } while (!(temp & GRACEFUL_STOP_ACKNOWLEDGE_RX) && --i);
1672
1673         uccf->stopped_rx = 1;
1674
1675         return 0;
1676 }
1677
1678 static int ugeth_restart_tx(struct ucc_geth_private *ugeth)
1679 {
1680         struct ucc_fast_private *uccf;
1681         u32 cecr_subblock;
1682
1683         uccf = ugeth->uccf;
1684
1685         cecr_subblock =
1686             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1687         qe_issue_cmd(QE_RESTART_TX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 0);
1688         uccf->stopped_tx = 0;
1689
1690         return 0;
1691 }
1692
1693 static int ugeth_restart_rx(struct ucc_geth_private *ugeth)
1694 {
1695         struct ucc_fast_private *uccf;
1696         u32 cecr_subblock;
1697
1698         uccf = ugeth->uccf;
1699
1700         cecr_subblock =
1701             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1702         qe_issue_cmd(QE_RESTART_RX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
1703                      0);
1704         uccf->stopped_rx = 0;
1705
1706         return 0;
1707 }
1708
1709 static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1710 {
1711         struct ucc_fast_private *uccf;
1712         int enabled_tx, enabled_rx;
1713
1714         uccf = ugeth->uccf;
1715
1716         /* check if the UCC number is in range. */
1717         if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1718                 if (netif_msg_probe(ugeth))
1719                         ugeth_err("%s: ucc_num out of range.", __func__);
1720                 return -EINVAL;
1721         }
1722
1723         enabled_tx = uccf->enabled_tx;
1724         enabled_rx = uccf->enabled_rx;
1725
1726         /* Get Tx and Rx going again, in case this channel was actively
1727         disabled. */
1728         if ((mode & COMM_DIR_TX) && (!enabled_tx) && uccf->stopped_tx)
1729                 ugeth_restart_tx(ugeth);
1730         if ((mode & COMM_DIR_RX) && (!enabled_rx) && uccf->stopped_rx)
1731                 ugeth_restart_rx(ugeth);
1732
1733         ucc_fast_enable(uccf, mode);    /* OK to do even if not disabled */
1734
1735         return 0;
1736
1737 }
1738
1739 static int ugeth_disable(struct ucc_geth_private * ugeth, enum comm_dir mode)
1740 {
1741         struct ucc_fast_private *uccf;
1742
1743         uccf = ugeth->uccf;
1744
1745         /* check if the UCC number is in range. */
1746         if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1747                 if (netif_msg_probe(ugeth))
1748                         ugeth_err("%s: ucc_num out of range.", __func__);
1749                 return -EINVAL;
1750         }
1751
1752         /* Stop any transmissions */
1753         if ((mode & COMM_DIR_TX) && uccf->enabled_tx && !uccf->stopped_tx)
1754                 ugeth_graceful_stop_tx(ugeth);
1755
1756         /* Stop any receptions */
1757         if ((mode & COMM_DIR_RX) && uccf->enabled_rx && !uccf->stopped_rx)
1758                 ugeth_graceful_stop_rx(ugeth);
1759
1760         ucc_fast_disable(ugeth->uccf, mode); /* OK to do even if not enabled */
1761
1762         return 0;
1763 }
1764
1765 static void ugeth_dump_regs(struct ucc_geth_private *ugeth)
1766 {
1767 #ifdef DEBUG
1768         ucc_fast_dump_regs(ugeth->uccf);
1769         dump_regs(ugeth);
1770         dump_bds(ugeth);
1771 #endif
1772 }
1773
1774 static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private *
1775                                                        ugeth,
1776                                                        enum enet_addr_type
1777                                                        enet_addr_type)
1778 {
1779         struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
1780         struct ucc_fast_private *uccf;
1781         enum comm_dir comm_dir;
1782         struct list_head *p_lh;
1783         u16 i, num;
1784         u32 __iomem *addr_h;
1785         u32 __iomem *addr_l;
1786         u8 *p_counter;
1787
1788         uccf = ugeth->uccf;
1789
1790         p_82xx_addr_filt =
1791             (struct ucc_geth_82xx_address_filtering_pram __iomem *)
1792             ugeth->p_rx_glbl_pram->addressfiltering;
1793
1794         if (enet_addr_type == ENET_ADDR_TYPE_GROUP) {
1795                 addr_h = &(p_82xx_addr_filt->gaddr_h);
1796                 addr_l = &(p_82xx_addr_filt->gaddr_l);
1797                 p_lh = &ugeth->group_hash_q;
1798                 p_counter = &(ugeth->numGroupAddrInHash);
1799         } else if (enet_addr_type == ENET_ADDR_TYPE_INDIVIDUAL) {
1800                 addr_h = &(p_82xx_addr_filt->iaddr_h);
1801                 addr_l = &(p_82xx_addr_filt->iaddr_l);
1802                 p_lh = &ugeth->ind_hash_q;
1803                 p_counter = &(ugeth->numIndAddrInHash);
1804         } else
1805                 return -EINVAL;
1806
1807         comm_dir = 0;
1808         if (uccf->enabled_tx)
1809                 comm_dir |= COMM_DIR_TX;
1810         if (uccf->enabled_rx)
1811                 comm_dir |= COMM_DIR_RX;
1812         if (comm_dir)
1813                 ugeth_disable(ugeth, comm_dir);
1814
1815         /* Clear the hash table. */
1816         out_be32(addr_h, 0x00000000);
1817         out_be32(addr_l, 0x00000000);
1818
1819         if (!p_lh)
1820                 return 0;
1821
1822         num = *p_counter;
1823
1824         /* Delete all remaining CQ elements */
1825         for (i = 0; i < num; i++)
1826                 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh)));
1827
1828         *p_counter = 0;
1829
1830         if (comm_dir)
1831                 ugeth_enable(ugeth, comm_dir);
1832
1833         return 0;
1834 }
1835
1836 static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth,
1837                                                     u8 paddr_num)
1838 {
1839         ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */
1840         return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */
1841 }
1842
1843 static void ucc_geth_memclean(struct ucc_geth_private *ugeth)
1844 {
1845         u16 i, j;
1846         u8 __iomem *bd;
1847
1848         if (!ugeth)
1849                 return;
1850
1851         if (ugeth->uccf) {
1852                 ucc_fast_free(ugeth->uccf);
1853                 ugeth->uccf = NULL;
1854         }
1855
1856         if (ugeth->p_thread_data_tx) {
1857                 qe_muram_free(ugeth->thread_dat_tx_offset);
1858                 ugeth->p_thread_data_tx = NULL;
1859         }
1860         if (ugeth->p_thread_data_rx) {
1861                 qe_muram_free(ugeth->thread_dat_rx_offset);
1862                 ugeth->p_thread_data_rx = NULL;
1863         }
1864         if (ugeth->p_exf_glbl_param) {
1865                 qe_muram_free(ugeth->exf_glbl_param_offset);
1866                 ugeth->p_exf_glbl_param = NULL;
1867         }
1868         if (ugeth->p_rx_glbl_pram) {
1869                 qe_muram_free(ugeth->rx_glbl_pram_offset);
1870                 ugeth->p_rx_glbl_pram = NULL;
1871         }
1872         if (ugeth->p_tx_glbl_pram) {
1873                 qe_muram_free(ugeth->tx_glbl_pram_offset);
1874                 ugeth->p_tx_glbl_pram = NULL;
1875         }
1876         if (ugeth->p_send_q_mem_reg) {
1877                 qe_muram_free(ugeth->send_q_mem_reg_offset);
1878                 ugeth->p_send_q_mem_reg = NULL;
1879         }
1880         if (ugeth->p_scheduler) {
1881                 qe_muram_free(ugeth->scheduler_offset);
1882                 ugeth->p_scheduler = NULL;
1883         }
1884         if (ugeth->p_tx_fw_statistics_pram) {
1885                 qe_muram_free(ugeth->tx_fw_statistics_pram_offset);
1886                 ugeth->p_tx_fw_statistics_pram = NULL;
1887         }
1888         if (ugeth->p_rx_fw_statistics_pram) {
1889                 qe_muram_free(ugeth->rx_fw_statistics_pram_offset);
1890                 ugeth->p_rx_fw_statistics_pram = NULL;
1891         }
1892         if (ugeth->p_rx_irq_coalescing_tbl) {
1893                 qe_muram_free(ugeth->rx_irq_coalescing_tbl_offset);
1894                 ugeth->p_rx_irq_coalescing_tbl = NULL;
1895         }
1896         if (ugeth->p_rx_bd_qs_tbl) {
1897                 qe_muram_free(ugeth->rx_bd_qs_tbl_offset);
1898                 ugeth->p_rx_bd_qs_tbl = NULL;
1899         }
1900         if (ugeth->p_init_enet_param_shadow) {
1901                 return_init_enet_entries(ugeth,
1902                                          &(ugeth->p_init_enet_param_shadow->
1903                                            rxthread[0]),
1904                                          ENET_INIT_PARAM_MAX_ENTRIES_RX,
1905                                          ugeth->ug_info->riscRx, 1);
1906                 return_init_enet_entries(ugeth,
1907                                          &(ugeth->p_init_enet_param_shadow->
1908                                            txthread[0]),
1909                                          ENET_INIT_PARAM_MAX_ENTRIES_TX,
1910                                          ugeth->ug_info->riscTx, 0);
1911                 kfree(ugeth->p_init_enet_param_shadow);
1912                 ugeth->p_init_enet_param_shadow = NULL;
1913         }
1914         for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
1915                 bd = ugeth->p_tx_bd_ring[i];
1916                 if (!bd)
1917                         continue;
1918                 for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) {
1919                         if (ugeth->tx_skbuff[i][j]) {
1920                                 dma_unmap_single(ugeth->dev,
1921                                                  in_be32(&((struct qe_bd __iomem *)bd)->buf),
1922                                                  (in_be32((u32 __iomem *)bd) &
1923                                                   BD_LENGTH_MASK),
1924                                                  DMA_TO_DEVICE);
1925                                 dev_kfree_skb_any(ugeth->tx_skbuff[i][j]);
1926                                 ugeth->tx_skbuff[i][j] = NULL;
1927                         }
1928                 }
1929
1930                 kfree(ugeth->tx_skbuff[i]);
1931
1932                 if (ugeth->p_tx_bd_ring[i]) {
1933                         if (ugeth->ug_info->uf_info.bd_mem_part ==
1934                             MEM_PART_SYSTEM)
1935                                 kfree((void *)ugeth->tx_bd_ring_offset[i]);
1936                         else if (ugeth->ug_info->uf_info.bd_mem_part ==
1937                                  MEM_PART_MURAM)
1938                                 qe_muram_free(ugeth->tx_bd_ring_offset[i]);
1939                         ugeth->p_tx_bd_ring[i] = NULL;
1940                 }
1941         }
1942         for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1943                 if (ugeth->p_rx_bd_ring[i]) {
1944                         /* Return existing data buffers in ring */
1945                         bd = ugeth->p_rx_bd_ring[i];
1946                         for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) {
1947                                 if (ugeth->rx_skbuff[i][j]) {
1948                                         dma_unmap_single(ugeth->dev,
1949                                                 in_be32(&((struct qe_bd __iomem *)bd)->buf),
1950                                                 ugeth->ug_info->
1951                                                 uf_info.max_rx_buf_length +
1952                                                 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
1953                                                 DMA_FROM_DEVICE);
1954                                         dev_kfree_skb_any(
1955                                                 ugeth->rx_skbuff[i][j]);
1956                                         ugeth->rx_skbuff[i][j] = NULL;
1957                                 }
1958                                 bd += sizeof(struct qe_bd);
1959                         }
1960
1961                         kfree(ugeth->rx_skbuff[i]);
1962
1963                         if (ugeth->ug_info->uf_info.bd_mem_part ==
1964                             MEM_PART_SYSTEM)
1965                                 kfree((void *)ugeth->rx_bd_ring_offset[i]);
1966                         else if (ugeth->ug_info->uf_info.bd_mem_part ==
1967                                  MEM_PART_MURAM)
1968                                 qe_muram_free(ugeth->rx_bd_ring_offset[i]);
1969                         ugeth->p_rx_bd_ring[i] = NULL;
1970                 }
1971         }
1972         while (!list_empty(&ugeth->group_hash_q))
1973                 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1974                                         (dequeue(&ugeth->group_hash_q)));
1975         while (!list_empty(&ugeth->ind_hash_q))
1976                 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1977                                         (dequeue(&ugeth->ind_hash_q)));
1978         if (ugeth->ug_regs) {
1979                 iounmap(ugeth->ug_regs);
1980                 ugeth->ug_regs = NULL;
1981         }
1982 }
1983
1984 static void ucc_geth_set_multi(struct net_device *dev)
1985 {
1986         struct ucc_geth_private *ugeth;
1987         struct dev_mc_list *dmi;
1988         struct ucc_fast __iomem *uf_regs;
1989         struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
1990         int i;
1991
1992         ugeth = netdev_priv(dev);
1993
1994         uf_regs = ugeth->uccf->uf_regs;
1995
1996         if (dev->flags & IFF_PROMISC) {
1997                 setbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
1998         } else {
1999                 clrbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
2000
2001                 p_82xx_addr_filt =
2002                     (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
2003                     p_rx_glbl_pram->addressfiltering;
2004
2005                 if (dev->flags & IFF_ALLMULTI) {
2006                         /* Catch all multicast addresses, so set the
2007                          * filter to all 1's.
2008                          */
2009                         out_be32(&p_82xx_addr_filt->gaddr_h, 0xffffffff);
2010                         out_be32(&p_82xx_addr_filt->gaddr_l, 0xffffffff);
2011                 } else {
2012                         /* Clear filter and add the addresses in the list.
2013                          */
2014                         out_be32(&p_82xx_addr_filt->gaddr_h, 0x0);
2015                         out_be32(&p_82xx_addr_filt->gaddr_l, 0x0);
2016
2017                         dmi = dev->mc_list;
2018
2019                         for (i = 0; i < dev->mc_count; i++, dmi = dmi->next) {
2020
2021                                 /* Only support group multicast for now.
2022                                  */
2023                                 if (!(dmi->dmi_addr[0] & 1))
2024                                         continue;
2025
2026                                 /* Ask CPM to run CRC and set bit in
2027                                  * filter mask.
2028                                  */
2029                                 hw_add_addr_in_hash(ugeth, dmi->dmi_addr);
2030                         }
2031                 }
2032         }
2033 }
2034
2035 static void ucc_geth_stop(struct ucc_geth_private *ugeth)
2036 {
2037         struct ucc_geth __iomem *ug_regs = ugeth->ug_regs;
2038         struct phy_device *phydev = ugeth->phydev;
2039
2040         ugeth_vdbg("%s: IN", __func__);
2041
2042         /* Disable the controller */
2043         ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
2044
2045         /* Tell the kernel the link is down */
2046         phy_stop(phydev);
2047
2048         /* Mask all interrupts */
2049         out_be32(ugeth->uccf->p_uccm, 0x00000000);
2050
2051         /* Clear all interrupts */
2052         out_be32(ugeth->uccf->p_ucce, 0xffffffff);
2053
2054         /* Disable Rx and Tx */
2055         clrbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2056
2057         phy_disconnect(ugeth->phydev);
2058         ugeth->phydev = NULL;
2059
2060         ucc_geth_memclean(ugeth);
2061 }
2062
2063 static int ucc_struct_init(struct ucc_geth_private *ugeth)
2064 {
2065         struct ucc_geth_info *ug_info;
2066         struct ucc_fast_info *uf_info;
2067         int i;
2068
2069         ug_info = ugeth->ug_info;
2070         uf_info = &ug_info->uf_info;
2071
2072         if (!((uf_info->bd_mem_part == MEM_PART_SYSTEM) ||
2073               (uf_info->bd_mem_part == MEM_PART_MURAM))) {
2074                 if (netif_msg_probe(ugeth))
2075                         ugeth_err("%s: Bad memory partition value.",
2076                                         __func__);
2077                 return -EINVAL;
2078         }
2079
2080         /* Rx BD lengths */
2081         for (i = 0; i < ug_info->numQueuesRx; i++) {
2082                 if ((ug_info->bdRingLenRx[i] < UCC_GETH_RX_BD_RING_SIZE_MIN) ||
2083                     (ug_info->bdRingLenRx[i] %
2084                      UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT)) {
2085                         if (netif_msg_probe(ugeth))
2086                                 ugeth_err
2087                                     ("%s: Rx BD ring length must be multiple of 4, no smaller than 8.",
2088                                         __func__);
2089                         return -EINVAL;
2090                 }
2091         }
2092
2093         /* Tx BD lengths */
2094         for (i = 0; i < ug_info->numQueuesTx; i++) {
2095                 if (ug_info->bdRingLenTx[i] < UCC_GETH_TX_BD_RING_SIZE_MIN) {
2096                         if (netif_msg_probe(ugeth))
2097                                 ugeth_err
2098                                     ("%s: Tx BD ring length must be no smaller than 2.",
2099                                      __func__);
2100                         return -EINVAL;
2101                 }
2102         }
2103
2104         /* mrblr */
2105         if ((uf_info->max_rx_buf_length == 0) ||
2106             (uf_info->max_rx_buf_length % UCC_GETH_MRBLR_ALIGNMENT)) {
2107                 if (netif_msg_probe(ugeth))
2108                         ugeth_err
2109                             ("%s: max_rx_buf_length must be non-zero multiple of 128.",
2110                              __func__);
2111                 return -EINVAL;
2112         }
2113
2114         /* num Tx queues */
2115         if (ug_info->numQueuesTx > NUM_TX_QUEUES) {
2116                 if (netif_msg_probe(ugeth))
2117                         ugeth_err("%s: number of tx queues too large.", __func__);
2118                 return -EINVAL;
2119         }
2120
2121         /* num Rx queues */
2122         if (ug_info->numQueuesRx > NUM_RX_QUEUES) {
2123                 if (netif_msg_probe(ugeth))
2124                         ugeth_err("%s: number of rx queues too large.", __func__);
2125                 return -EINVAL;
2126         }
2127
2128         /* l2qt */
2129         for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) {
2130                 if (ug_info->l2qt[i] >= ug_info->numQueuesRx) {
2131                         if (netif_msg_probe(ugeth))
2132                                 ugeth_err
2133                                     ("%s: VLAN priority table entry must not be"
2134                                         " larger than number of Rx queues.",
2135                                      __func__);
2136                         return -EINVAL;
2137                 }
2138         }
2139
2140         /* l3qt */
2141         for (i = 0; i < UCC_GETH_IP_PRIORITY_MAX; i++) {
2142                 if (ug_info->l3qt[i] >= ug_info->numQueuesRx) {
2143                         if (netif_msg_probe(ugeth))
2144                                 ugeth_err
2145                                     ("%s: IP priority table entry must not be"
2146                                         " larger than number of Rx queues.",
2147                                      __func__);
2148                         return -EINVAL;
2149                 }
2150         }
2151
2152         if (ug_info->cam && !ug_info->ecamptr) {
2153                 if (netif_msg_probe(ugeth))
2154                         ugeth_err("%s: If cam mode is chosen, must supply cam ptr.",
2155                                   __func__);
2156                 return -EINVAL;
2157         }
2158
2159         if ((ug_info->numStationAddresses !=
2160              UCC_GETH_NUM_OF_STATION_ADDRESSES_1)
2161             && ug_info->rxExtendedFiltering) {
2162                 if (netif_msg_probe(ugeth))
2163                         ugeth_err("%s: Number of station addresses greater than 1 "
2164                                   "not allowed in extended parsing mode.",
2165                                   __func__);
2166                 return -EINVAL;
2167         }
2168
2169         /* Generate uccm_mask for receive */
2170         uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */
2171         for (i = 0; i < ug_info->numQueuesRx; i++)
2172                 uf_info->uccm_mask |= (UCC_GETH_UCCE_RXF0 << i);
2173
2174         for (i = 0; i < ug_info->numQueuesTx; i++)
2175                 uf_info->uccm_mask |= (UCC_GETH_UCCE_TXB0 << i);
2176         /* Initialize the general fast UCC block. */
2177         if (ucc_fast_init(uf_info, &ugeth->uccf)) {
2178                 if (netif_msg_probe(ugeth))
2179                         ugeth_err("%s: Failed to init uccf.", __func__);
2180                 return -ENOMEM;
2181         }
2182
2183         /* read the number of risc engines, update the riscTx and riscRx
2184          * if there are 4 riscs in QE
2185          */
2186         if (qe_get_num_of_risc() == 4) {
2187                 ug_info->riscTx = QE_RISC_ALLOCATION_FOUR_RISCS;
2188                 ug_info->riscRx = QE_RISC_ALLOCATION_FOUR_RISCS;
2189         }
2190
2191         ugeth->ug_regs = ioremap(uf_info->regs, sizeof(*ugeth->ug_regs));
2192         if (!ugeth->ug_regs) {
2193                 if (netif_msg_probe(ugeth))
2194                         ugeth_err("%s: Failed to ioremap regs.", __func__);
2195                 return -ENOMEM;
2196         }
2197
2198         return 0;
2199 }
2200
2201 static int ucc_geth_startup(struct ucc_geth_private *ugeth)
2202 {
2203         struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
2204         struct ucc_geth_init_pram __iomem *p_init_enet_pram;
2205         struct ucc_fast_private *uccf;
2206         struct ucc_geth_info *ug_info;
2207         struct ucc_fast_info *uf_info;
2208         struct ucc_fast __iomem *uf_regs;
2209         struct ucc_geth __iomem *ug_regs;
2210         int ret_val = -EINVAL;
2211         u32 remoder = UCC_GETH_REMODER_INIT;
2212         u32 init_enet_pram_offset, cecr_subblock, command;
2213         u32 ifstat, i, j, size, l2qt, l3qt, length;
2214         u16 temoder = UCC_GETH_TEMODER_INIT;
2215         u16 test;
2216         u8 function_code = 0;
2217         u8 __iomem *bd;
2218         u8 __iomem *endOfRing;
2219         u8 numThreadsRxNumerical, numThreadsTxNumerical;
2220
2221         ugeth_vdbg("%s: IN", __func__);
2222         uccf = ugeth->uccf;
2223         ug_info = ugeth->ug_info;
2224         uf_info = &ug_info->uf_info;
2225         uf_regs = uccf->uf_regs;
2226         ug_regs = ugeth->ug_regs;
2227
2228         switch (ug_info->numThreadsRx) {
2229         case UCC_GETH_NUM_OF_THREADS_1:
2230                 numThreadsRxNumerical = 1;
2231                 break;
2232         case UCC_GETH_NUM_OF_THREADS_2:
2233                 numThreadsRxNumerical = 2;
2234                 break;
2235         case UCC_GETH_NUM_OF_THREADS_4:
2236                 numThreadsRxNumerical = 4;
2237                 break;
2238         case UCC_GETH_NUM_OF_THREADS_6:
2239                 numThreadsRxNumerical = 6;
2240                 break;
2241         case UCC_GETH_NUM_OF_THREADS_8:
2242                 numThreadsRxNumerical = 8;
2243                 break;
2244         default:
2245                 if (netif_msg_ifup(ugeth))
2246                         ugeth_err("%s: Bad number of Rx threads value.",
2247                                         __func__);
2248                 return -EINVAL;
2249                 break;
2250         }
2251
2252         switch (ug_info->numThreadsTx) {
2253         case UCC_GETH_NUM_OF_THREADS_1:
2254                 numThreadsTxNumerical = 1;
2255                 break;
2256         case UCC_GETH_NUM_OF_THREADS_2:
2257                 numThreadsTxNumerical = 2;
2258                 break;
2259         case UCC_GETH_NUM_OF_THREADS_4:
2260                 numThreadsTxNumerical = 4;
2261                 break;
2262         case UCC_GETH_NUM_OF_THREADS_6:
2263                 numThreadsTxNumerical = 6;
2264                 break;
2265         case UCC_GETH_NUM_OF_THREADS_8:
2266                 numThreadsTxNumerical = 8;
2267                 break;
2268         default:
2269                 if (netif_msg_ifup(ugeth))
2270                         ugeth_err("%s: Bad number of Tx threads value.",
2271                                         __func__);
2272                 return -EINVAL;
2273                 break;
2274         }
2275
2276         /* Calculate rx_extended_features */
2277         ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck ||
2278             ug_info->ipAddressAlignment ||
2279             (ug_info->numStationAddresses !=
2280              UCC_GETH_NUM_OF_STATION_ADDRESSES_1);
2281
2282         ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features ||
2283             (ug_info->vlanOperationTagged != UCC_GETH_VLAN_OPERATION_TAGGED_NOP)
2284             || (ug_info->vlanOperationNonTagged !=
2285                 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP);
2286
2287         init_default_reg_vals(&uf_regs->upsmr,
2288                               &ug_regs->maccfg1, &ug_regs->maccfg2);
2289
2290         /*                    Set UPSMR                      */
2291         /* For more details see the hardware spec.           */
2292         init_rx_parameters(ug_info->bro,
2293                            ug_info->rsh, ug_info->pro, &uf_regs->upsmr);
2294
2295         /* We're going to ignore other registers for now, */
2296         /* except as needed to get up and running         */
2297
2298         /*                    Set MACCFG1                    */
2299         /* For more details see the hardware spec.           */
2300         init_flow_control_params(ug_info->aufc,
2301                                  ug_info->receiveFlowControl,
2302                                  ug_info->transmitFlowControl,
2303                                  ug_info->pausePeriod,
2304                                  ug_info->extensionField,
2305                                  &uf_regs->upsmr,
2306                                  &ug_regs->uempr, &ug_regs->maccfg1);
2307
2308         setbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2309
2310         /*                    Set IPGIFG                     */
2311         /* For more details see the hardware spec.           */
2312         ret_val = init_inter_frame_gap_params(ug_info->nonBackToBackIfgPart1,
2313                                               ug_info->nonBackToBackIfgPart2,
2314                                               ug_info->
2315                                               miminumInterFrameGapEnforcement,
2316                                               ug_info->backToBackInterFrameGap,
2317                                               &ug_regs->ipgifg);
2318         if (ret_val != 0) {
2319                 if (netif_msg_ifup(ugeth))
2320                         ugeth_err("%s: IPGIFG initialization parameter too large.",
2321                                   __func__);
2322                 return ret_val;
2323         }
2324
2325         /*                    Set HAFDUP                     */
2326         /* For more details see the hardware spec.           */
2327         ret_val = init_half_duplex_params(ug_info->altBeb,
2328                                           ug_info->backPressureNoBackoff,
2329                                           ug_info->noBackoff,
2330                                           ug_info->excessDefer,
2331                                           ug_info->altBebTruncation,
2332                                           ug_info->maxRetransmission,
2333                                           ug_info->collisionWindow,
2334                                           &ug_regs->hafdup);
2335         if (ret_val != 0) {
2336                 if (netif_msg_ifup(ugeth))
2337                         ugeth_err("%s: Half Duplex initialization parameter too large.",
2338                           __func__);
2339                 return ret_val;
2340         }
2341
2342         /*                    Set IFSTAT                     */
2343         /* For more details see the hardware spec.           */
2344         /* Read only - resets upon read                      */
2345         ifstat = in_be32(&ug_regs->ifstat);
2346
2347         /*                    Clear UEMPR                    */
2348         /* For more details see the hardware spec.           */
2349         out_be32(&ug_regs->uempr, 0);
2350
2351         /*                    Set UESCR                      */
2352         /* For more details see the hardware spec.           */
2353         init_hw_statistics_gathering_mode((ug_info->statisticsMode &
2354                                 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE),
2355                                 0, &uf_regs->upsmr, &ug_regs->uescr);
2356
2357         /* Allocate Tx bds */
2358         for (j = 0; j < ug_info->numQueuesTx; j++) {
2359                 /* Allocate in multiple of
2360                    UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT,
2361                    according to spec */
2362                 length = ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd))
2363                           / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2364                     * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2365                 if ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) %
2366                     UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2367                         length += UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2368                 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2369                         u32 align = 4;
2370                         if (UCC_GETH_TX_BD_RING_ALIGNMENT > 4)
2371                                 align = UCC_GETH_TX_BD_RING_ALIGNMENT;
2372                         ugeth->tx_bd_ring_offset[j] =
2373                                 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
2374
2375                         if (ugeth->tx_bd_ring_offset[j] != 0)
2376                                 ugeth->p_tx_bd_ring[j] =
2377                                         (u8 __iomem *)((ugeth->tx_bd_ring_offset[j] +
2378                                         align) & ~(align - 1));
2379                 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2380                         ugeth->tx_bd_ring_offset[j] =
2381                             qe_muram_alloc(length,
2382                                            UCC_GETH_TX_BD_RING_ALIGNMENT);
2383                         if (!IS_ERR_VALUE(ugeth->tx_bd_ring_offset[j]))
2384                                 ugeth->p_tx_bd_ring[j] =
2385                                     (u8 __iomem *) qe_muram_addr(ugeth->
2386                                                          tx_bd_ring_offset[j]);
2387                 }
2388                 if (!ugeth->p_tx_bd_ring[j]) {
2389                         if (netif_msg_ifup(ugeth))
2390                                 ugeth_err
2391                                     ("%s: Can not allocate memory for Tx bd rings.",
2392                                      __func__);
2393                         return -ENOMEM;
2394                 }
2395                 /* Zero unused end of bd ring, according to spec */
2396                 memset_io((void __iomem *)(ugeth->p_tx_bd_ring[j] +
2397                        ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)), 0,
2398                        length - ug_info->bdRingLenTx[j] * sizeof(struct qe_bd));
2399         }
2400
2401         /* Allocate Rx bds */
2402         for (j = 0; j < ug_info->numQueuesRx; j++) {
2403                 length = ug_info->bdRingLenRx[j] * sizeof(struct qe_bd);
2404                 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2405                         u32 align = 4;
2406                         if (UCC_GETH_RX_BD_RING_ALIGNMENT > 4)
2407                                 align = UCC_GETH_RX_BD_RING_ALIGNMENT;
2408                         ugeth->rx_bd_ring_offset[j] =
2409                                 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
2410                         if (ugeth->rx_bd_ring_offset[j] != 0)
2411                                 ugeth->p_rx_bd_ring[j] =
2412                                         (u8 __iomem *)((ugeth->rx_bd_ring_offset[j] +
2413                                         align) & ~(align - 1));
2414                 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2415                         ugeth->rx_bd_ring_offset[j] =
2416                             qe_muram_alloc(length,
2417                                            UCC_GETH_RX_BD_RING_ALIGNMENT);
2418                         if (!IS_ERR_VALUE(ugeth->rx_bd_ring_offset[j]))
2419                                 ugeth->p_rx_bd_ring[j] =
2420                                     (u8 __iomem *) qe_muram_addr(ugeth->
2421                                                          rx_bd_ring_offset[j]);
2422                 }
2423                 if (!ugeth->p_rx_bd_ring[j]) {
2424                         if (netif_msg_ifup(ugeth))
2425                                 ugeth_err
2426                                     ("%s: Can not allocate memory for Rx bd rings.",
2427                                      __func__);
2428                         return -ENOMEM;
2429                 }
2430         }
2431
2432         /* Init Tx bds */
2433         for (j = 0; j < ug_info->numQueuesTx; j++) {
2434                 /* Setup the skbuff rings */
2435                 ugeth->tx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2436                                               ugeth->ug_info->bdRingLenTx[j],
2437                                               GFP_KERNEL);
2438
2439                 if (ugeth->tx_skbuff[j] == NULL) {
2440                         if (netif_msg_ifup(ugeth))
2441                                 ugeth_err("%s: Could not allocate tx_skbuff",
2442                                           __func__);
2443                         return -ENOMEM;
2444                 }
2445
2446                 for (i = 0; i < ugeth->ug_info->bdRingLenTx[j]; i++)
2447                         ugeth->tx_skbuff[j][i] = NULL;
2448
2449                 ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0;
2450                 bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j];
2451                 for (i = 0; i < ug_info->bdRingLenTx[j]; i++) {
2452                         /* clear bd buffer */
2453                         out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
2454                         /* set bd status and length */
2455                         out_be32((u32 __iomem *)bd, 0);
2456                         bd += sizeof(struct qe_bd);
2457                 }
2458                 bd -= sizeof(struct qe_bd);
2459                 /* set bd status and length */
2460                 out_be32((u32 __iomem *)bd, T_W); /* for last BD set Wrap bit */
2461         }
2462
2463         /* Init Rx bds */
2464         for (j = 0; j < ug_info->numQueuesRx; j++) {
2465                 /* Setup the skbuff rings */
2466                 ugeth->rx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2467                                               ugeth->ug_info->bdRingLenRx[j],
2468                                               GFP_KERNEL);
2469
2470                 if (ugeth->rx_skbuff[j] == NULL) {
2471                         if (netif_msg_ifup(ugeth))
2472                                 ugeth_err("%s: Could not allocate rx_skbuff",
2473                                           __func__);
2474                         return -ENOMEM;
2475                 }
2476
2477                 for (i = 0; i < ugeth->ug_info->bdRingLenRx[j]; i++)
2478                         ugeth->rx_skbuff[j][i] = NULL;
2479
2480                 ugeth->skb_currx[j] = 0;
2481                 bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j];
2482                 for (i = 0; i < ug_info->bdRingLenRx[j]; i++) {
2483                         /* set bd status and length */
2484                         out_be32((u32 __iomem *)bd, R_I);
2485                         /* clear bd buffer */
2486                         out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
2487                         bd += sizeof(struct qe_bd);
2488                 }
2489                 bd -= sizeof(struct qe_bd);
2490                 /* set bd status and length */
2491                 out_be32((u32 __iomem *)bd, R_W); /* for last BD set Wrap bit */
2492         }
2493
2494         /*
2495          * Global PRAM
2496          */
2497         /* Tx global PRAM */
2498         /* Allocate global tx parameter RAM page */
2499         ugeth->tx_glbl_pram_offset =
2500             qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram),
2501                            UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT);
2502         if (IS_ERR_VALUE(ugeth->tx_glbl_pram_offset)) {
2503                 if (netif_msg_ifup(ugeth))
2504                         ugeth_err
2505                             ("%s: Can not allocate DPRAM memory for p_tx_glbl_pram.",
2506                              __func__);
2507                 return -ENOMEM;
2508         }
2509         ugeth->p_tx_glbl_pram =
2510             (struct ucc_geth_tx_global_pram __iomem *) qe_muram_addr(ugeth->
2511                                                         tx_glbl_pram_offset);
2512         /* Zero out p_tx_glbl_pram */
2513         memset_io((void __iomem *)ugeth->p_tx_glbl_pram, 0, sizeof(struct ucc_geth_tx_global_pram));
2514
2515         /* Fill global PRAM */
2516
2517         /* TQPTR */
2518         /* Size varies with number of Tx threads */
2519         ugeth->thread_dat_tx_offset =
2520             qe_muram_alloc(numThreadsTxNumerical *
2521                            sizeof(struct ucc_geth_thread_data_tx) +
2522                            32 * (numThreadsTxNumerical == 1),
2523                            UCC_GETH_THREAD_DATA_ALIGNMENT);
2524         if (IS_ERR_VALUE(ugeth->thread_dat_tx_offset)) {
2525                 if (netif_msg_ifup(ugeth))
2526                         ugeth_err
2527                             ("%s: Can not allocate DPRAM memory for p_thread_data_tx.",
2528                              __func__);
2529                 return -ENOMEM;
2530         }
2531
2532         ugeth->p_thread_data_tx =
2533             (struct ucc_geth_thread_data_tx __iomem *) qe_muram_addr(ugeth->
2534                                                         thread_dat_tx_offset);
2535         out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset);
2536
2537         /* vtagtable */
2538         for (i = 0; i < UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX; i++)
2539                 out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i],
2540                          ug_info->vtagtable[i]);
2541
2542         /* iphoffset */
2543         for (i = 0; i < TX_IP_OFFSET_ENTRY_MAX; i++)
2544                 out_8(&ugeth->p_tx_glbl_pram->iphoffset[i],
2545                                 ug_info->iphoffset[i]);
2546
2547         /* SQPTR */
2548         /* Size varies with number of Tx queues */
2549         ugeth->send_q_mem_reg_offset =
2550             qe_muram_alloc(ug_info->numQueuesTx *
2551                            sizeof(struct ucc_geth_send_queue_qd),
2552                            UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
2553         if (IS_ERR_VALUE(ugeth->send_q_mem_reg_offset)) {
2554                 if (netif_msg_ifup(ugeth))
2555                         ugeth_err
2556                             ("%s: Can not allocate DPRAM memory for p_send_q_mem_reg.",
2557                              __func__);
2558                 return -ENOMEM;
2559         }
2560
2561         ugeth->p_send_q_mem_reg =
2562             (struct ucc_geth_send_queue_mem_region __iomem *) qe_muram_addr(ugeth->
2563                         send_q_mem_reg_offset);
2564         out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset);
2565
2566         /* Setup the table */
2567         /* Assume BD rings are already established */
2568         for (i = 0; i < ug_info->numQueuesTx; i++) {
2569                 endOfRing =
2570                     ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] -
2571                                               1) * sizeof(struct qe_bd);
2572                 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2573                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2574                                  (u32) virt_to_phys(ugeth->p_tx_bd_ring[i]));
2575                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2576                                  last_bd_completed_address,
2577                                  (u32) virt_to_phys(endOfRing));
2578                 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2579                            MEM_PART_MURAM) {
2580                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2581                                  (u32) immrbar_virt_to_phys(ugeth->
2582                                                             p_tx_bd_ring[i]));
2583                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2584                                  last_bd_completed_address,
2585                                  (u32) immrbar_virt_to_phys(endOfRing));
2586                 }
2587         }
2588
2589         /* schedulerbasepointer */
2590
2591         if (ug_info->numQueuesTx > 1) {
2592         /* scheduler exists only if more than 1 tx queue */
2593                 ugeth->scheduler_offset =
2594                     qe_muram_alloc(sizeof(struct ucc_geth_scheduler),
2595                                    UCC_GETH_SCHEDULER_ALIGNMENT);
2596                 if (IS_ERR_VALUE(ugeth->scheduler_offset)) {
2597                         if (netif_msg_ifup(ugeth))
2598                                 ugeth_err
2599                                  ("%s: Can not allocate DPRAM memory for p_scheduler.",
2600                                      __func__);
2601                         return -ENOMEM;
2602                 }
2603
2604                 ugeth->p_scheduler =
2605                     (struct ucc_geth_scheduler __iomem *) qe_muram_addr(ugeth->
2606                                                            scheduler_offset);
2607                 out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer,
2608                          ugeth->scheduler_offset);
2609                 /* Zero out p_scheduler */
2610                 memset_io((void __iomem *)ugeth->p_scheduler, 0, sizeof(struct ucc_geth_scheduler));
2611
2612                 /* Set values in scheduler */
2613                 out_be32(&ugeth->p_scheduler->mblinterval,
2614                          ug_info->mblinterval);
2615                 out_be16(&ugeth->p_scheduler->nortsrbytetime,
2616                          ug_info->nortsrbytetime);
2617                 out_8(&ugeth->p_scheduler->fracsiz, ug_info->fracsiz);
2618                 out_8(&ugeth->p_scheduler->strictpriorityq,
2619                                 ug_info->strictpriorityq);
2620                 out_8(&ugeth->p_scheduler->txasap, ug_info->txasap);
2621                 out_8(&ugeth->p_scheduler->extrabw, ug_info->extrabw);
2622                 for (i = 0; i < NUM_TX_QUEUES; i++)
2623                         out_8(&ugeth->p_scheduler->weightfactor[i],
2624                             ug_info->weightfactor[i]);
2625
2626                 /* Set pointers to cpucount registers in scheduler */
2627                 ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0);
2628                 ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1);
2629                 ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2);
2630                 ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3);
2631                 ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4);
2632                 ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5);
2633                 ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6);
2634                 ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7);
2635         }
2636
2637         /* schedulerbasepointer */
2638         /* TxRMON_PTR (statistics) */
2639         if (ug_info->
2640             statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) {
2641                 ugeth->tx_fw_statistics_pram_offset =
2642                     qe_muram_alloc(sizeof
2643                                    (struct ucc_geth_tx_firmware_statistics_pram),
2644                                    UCC_GETH_TX_STATISTICS_ALIGNMENT);
2645                 if (IS_ERR_VALUE(ugeth->tx_fw_statistics_pram_offset)) {
2646                         if (netif_msg_ifup(ugeth))
2647                                 ugeth_err
2648                                     ("%s: Can not allocate DPRAM memory for"
2649                                         " p_tx_fw_statistics_pram.",
2650                                         __func__);
2651                         return -ENOMEM;
2652                 }
2653                 ugeth->p_tx_fw_statistics_pram =
2654                     (struct ucc_geth_tx_firmware_statistics_pram __iomem *)
2655                     qe_muram_addr(ugeth->tx_fw_statistics_pram_offset);
2656                 /* Zero out p_tx_fw_statistics_pram */
2657                 memset_io((void __iomem *)ugeth->p_tx_fw_statistics_pram,
2658                        0, sizeof(struct ucc_geth_tx_firmware_statistics_pram));
2659         }
2660
2661         /* temoder */
2662         /* Already has speed set */
2663
2664         if (ug_info->numQueuesTx > 1)
2665                 temoder |= TEMODER_SCHEDULER_ENABLE;
2666         if (ug_info->ipCheckSumGenerate)
2667                 temoder |= TEMODER_IP_CHECKSUM_GENERATE;
2668         temoder |= ((ug_info->numQueuesTx - 1) << TEMODER_NUM_OF_QUEUES_SHIFT);
2669         out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder);
2670
2671         test = in_be16(&ugeth->p_tx_glbl_pram->temoder);
2672
2673         /* Function code register value to be used later */
2674         function_code = UCC_BMR_BO_BE | UCC_BMR_GBL;
2675         /* Required for QE */
2676
2677         /* function code register */
2678         out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24);
2679
2680         /* Rx global PRAM */
2681         /* Allocate global rx parameter RAM page */
2682         ugeth->rx_glbl_pram_offset =
2683             qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram),
2684                            UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT);
2685         if (IS_ERR_VALUE(ugeth->rx_glbl_pram_offset)) {
2686                 if (netif_msg_ifup(ugeth))
2687                         ugeth_err
2688                             ("%s: Can not allocate DPRAM memory for p_rx_glbl_pram.",
2689                              __func__);
2690                 return -ENOMEM;
2691         }
2692         ugeth->p_rx_glbl_pram =
2693             (struct ucc_geth_rx_global_pram __iomem *) qe_muram_addr(ugeth->
2694                                                         rx_glbl_pram_offset);
2695         /* Zero out p_rx_glbl_pram */
2696         memset_io((void __iomem *)ugeth->p_rx_glbl_pram, 0, sizeof(struct ucc_geth_rx_global_pram));
2697
2698         /* Fill global PRAM */
2699
2700         /* RQPTR */
2701         /* Size varies with number of Rx threads */
2702         ugeth->thread_dat_rx_offset =
2703             qe_muram_alloc(numThreadsRxNumerical *
2704                            sizeof(struct ucc_geth_thread_data_rx),
2705                            UCC_GETH_THREAD_DATA_ALIGNMENT);
2706         if (IS_ERR_VALUE(ugeth->thread_dat_rx_offset)) {
2707                 if (netif_msg_ifup(ugeth))
2708                         ugeth_err
2709                             ("%s: Can not allocate DPRAM memory for p_thread_data_rx.",
2710                              __func__);
2711                 return -ENOMEM;
2712         }
2713
2714         ugeth->p_thread_data_rx =
2715             (struct ucc_geth_thread_data_rx __iomem *) qe_muram_addr(ugeth->
2716                                                         thread_dat_rx_offset);
2717         out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset);
2718
2719         /* typeorlen */
2720         out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen);
2721
2722         /* rxrmonbaseptr (statistics) */
2723         if (ug_info->
2724             statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) {
2725                 ugeth->rx_fw_statistics_pram_offset =
2726                     qe_muram_alloc(sizeof
2727                                    (struct ucc_geth_rx_firmware_statistics_pram),
2728                                    UCC_GETH_RX_STATISTICS_ALIGNMENT);
2729                 if (IS_ERR_VALUE(ugeth->rx_fw_statistics_pram_offset)) {
2730                         if (netif_msg_ifup(ugeth))
2731                                 ugeth_err
2732                                         ("%s: Can not allocate DPRAM memory for"
2733                                         " p_rx_fw_statistics_pram.", __func__);
2734                         return -ENOMEM;
2735                 }
2736                 ugeth->p_rx_fw_statistics_pram =
2737                     (struct ucc_geth_rx_firmware_statistics_pram __iomem *)
2738                     qe_muram_addr(ugeth->rx_fw_statistics_pram_offset);
2739                 /* Zero out p_rx_fw_statistics_pram */
2740                 memset_io((void __iomem *)ugeth->p_rx_fw_statistics_pram, 0,
2741                        sizeof(struct ucc_geth_rx_firmware_statistics_pram));
2742         }
2743
2744         /* intCoalescingPtr */
2745
2746         /* Size varies with number of Rx queues */
2747         ugeth->rx_irq_coalescing_tbl_offset =
2748             qe_muram_alloc(ug_info->numQueuesRx *
2749                            sizeof(struct ucc_geth_rx_interrupt_coalescing_entry)
2750                            + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT);
2751         if (IS_ERR_VALUE(ugeth->rx_irq_coalescing_tbl_offset)) {
2752                 if (netif_msg_ifup(ugeth))
2753                         ugeth_err
2754                             ("%s: Can not allocate DPRAM memory for"
2755                                 " p_rx_irq_coalescing_tbl.", __func__);
2756                 return -ENOMEM;
2757         }
2758
2759         ugeth->p_rx_irq_coalescing_tbl =
2760             (struct ucc_geth_rx_interrupt_coalescing_table __iomem *)
2761             qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset);
2762         out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr,
2763                  ugeth->rx_irq_coalescing_tbl_offset);
2764
2765         /* Fill interrupt coalescing table */
2766         for (i = 0; i < ug_info->numQueuesRx; i++) {
2767                 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2768                          interruptcoalescingmaxvalue,
2769                          ug_info->interruptcoalescingmaxvalue[i]);
2770                 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2771                          interruptcoalescingcounter,
2772                          ug_info->interruptcoalescingmaxvalue[i]);
2773         }
2774
2775         /* MRBLR */
2776         init_max_rx_buff_len(uf_info->max_rx_buf_length,
2777                              &ugeth->p_rx_glbl_pram->mrblr);
2778         /* MFLR */
2779         out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength);
2780         /* MINFLR */
2781         init_min_frame_len(ug_info->minFrameLength,
2782                            &ugeth->p_rx_glbl_pram->minflr,
2783                            &ugeth->p_rx_glbl_pram->mrblr);
2784         /* MAXD1 */
2785         out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length);
2786         /* MAXD2 */
2787         out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length);
2788
2789         /* l2qt */
2790         l2qt = 0;
2791         for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++)
2792                 l2qt |= (ug_info->l2qt[i] << (28 - 4 * i));
2793         out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt);
2794
2795         /* l3qt */
2796         for (j = 0; j < UCC_GETH_IP_PRIORITY_MAX; j += 8) {
2797                 l3qt = 0;
2798                 for (i = 0; i < 8; i++)
2799                         l3qt |= (ug_info->l3qt[j + i] << (28 - 4 * i));
2800                 out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt);
2801         }
2802
2803         /* vlantype */
2804         out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype);
2805
2806         /* vlantci */
2807         out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci);
2808
2809         /* ecamptr */
2810         out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr);
2811
2812         /* RBDQPTR */
2813         /* Size varies with number of Rx queues */
2814         ugeth->rx_bd_qs_tbl_offset =
2815             qe_muram_alloc(ug_info->numQueuesRx *
2816                            (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2817                             sizeof(struct ucc_geth_rx_prefetched_bds)),
2818                            UCC_GETH_RX_BD_QUEUES_ALIGNMENT);
2819         if (IS_ERR_VALUE(ugeth->rx_bd_qs_tbl_offset)) {
2820                 if (netif_msg_ifup(ugeth))
2821                         ugeth_err
2822                             ("%s: Can not allocate DPRAM memory for p_rx_bd_qs_tbl.",
2823                              __func__);
2824                 return -ENOMEM;
2825         }
2826
2827         ugeth->p_rx_bd_qs_tbl =
2828             (struct ucc_geth_rx_bd_queues_entry __iomem *) qe_muram_addr(ugeth->
2829                                     rx_bd_qs_tbl_offset);
2830         out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset);
2831         /* Zero out p_rx_bd_qs_tbl */
2832         memset_io((void __iomem *)ugeth->p_rx_bd_qs_tbl,
2833                0,
2834                ug_info->numQueuesRx * (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2835                                        sizeof(struct ucc_geth_rx_prefetched_bds)));
2836
2837         /* Setup the table */
2838         /* Assume BD rings are already established */
2839         for (i = 0; i < ug_info->numQueuesRx; i++) {
2840                 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2841                         out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2842                                  (u32) virt_to_phys(ugeth->p_rx_bd_ring[i]));
2843                 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2844                            MEM_PART_MURAM) {
2845                         out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2846                                  (u32) immrbar_virt_to_phys(ugeth->
2847                                                             p_rx_bd_ring[i]));
2848                 }
2849                 /* rest of fields handled by QE */
2850         }
2851
2852         /* remoder */
2853         /* Already has speed set */
2854
2855         if (ugeth->rx_extended_features)
2856                 remoder |= REMODER_RX_EXTENDED_FEATURES;
2857         if (ug_info->rxExtendedFiltering)
2858                 remoder |= REMODER_RX_EXTENDED_FILTERING;
2859         if (ug_info->dynamicMaxFrameLength)
2860                 remoder |= REMODER_DYNAMIC_MAX_FRAME_LENGTH;
2861         if (ug_info->dynamicMinFrameLength)
2862                 remoder |= REMODER_DYNAMIC_MIN_FRAME_LENGTH;
2863         remoder |=
2864             ug_info->vlanOperationTagged << REMODER_VLAN_OPERATION_TAGGED_SHIFT;
2865         remoder |=
2866             ug_info->
2867             vlanOperationNonTagged << REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT;
2868         remoder |= ug_info->rxQoSMode << REMODER_RX_QOS_MODE_SHIFT;
2869         remoder |= ((ug_info->numQueuesRx - 1) << REMODER_NUM_OF_QUEUES_SHIFT);
2870         if (ug_info->ipCheckSumCheck)
2871                 remoder |= REMODER_IP_CHECKSUM_CHECK;
2872         if (ug_info->ipAddressAlignment)
2873                 remoder |= REMODER_IP_ADDRESS_ALIGNMENT;
2874         out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder);
2875
2876         /* Note that this function must be called */
2877         /* ONLY AFTER p_tx_fw_statistics_pram */
2878         /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */
2879         init_firmware_statistics_gathering_mode((ug_info->
2880                 statisticsMode &
2881                 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX),
2882                 (ug_info->statisticsMode &
2883                 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX),
2884                 &ugeth->p_tx_glbl_pram->txrmonbaseptr,
2885                 ugeth->tx_fw_statistics_pram_offset,
2886                 &ugeth->p_rx_glbl_pram->rxrmonbaseptr,
2887                 ugeth->rx_fw_statistics_pram_offset,
2888                 &ugeth->p_tx_glbl_pram->temoder,
2889                 &ugeth->p_rx_glbl_pram->remoder);
2890
2891         /* function code register */
2892         out_8(&ugeth->p_rx_glbl_pram->rstate, function_code);
2893
2894         /* initialize extended filtering */
2895         if (ug_info->rxExtendedFiltering) {
2896                 if (!ug_info->extendedFilteringChainPointer) {
2897                         if (netif_msg_ifup(ugeth))
2898                                 ugeth_err("%s: Null Extended Filtering Chain Pointer.",
2899                                           __func__);
2900                         return -EINVAL;
2901                 }
2902
2903                 /* Allocate memory for extended filtering Mode Global
2904                 Parameters */
2905                 ugeth->exf_glbl_param_offset =
2906                     qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram),
2907                 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT);
2908                 if (IS_ERR_VALUE(ugeth->exf_glbl_param_offset)) {
2909                         if (netif_msg_ifup(ugeth))
2910                                 ugeth_err
2911                                         ("%s: Can not allocate DPRAM memory for"
2912                                         " p_exf_glbl_param.", __func__);
2913                         return -ENOMEM;
2914                 }
2915
2916                 ugeth->p_exf_glbl_param =
2917                     (struct ucc_geth_exf_global_pram __iomem *) qe_muram_addr(ugeth->
2918                                  exf_glbl_param_offset);
2919                 out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam,
2920                          ugeth->exf_glbl_param_offset);
2921                 out_be32(&ugeth->p_exf_glbl_param->l2pcdptr,
2922                          (u32) ug_info->extendedFilteringChainPointer);
2923
2924         } else {  &nbs