Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[sfrench/cifs-2.6.git] / drivers / net / tg3.c
1 /*
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  * Copyright (C) 2005 Broadcom Corporation.
8  *
9  * Firmware is:
10  *      Derived from proprietary unpublished source code,
11  *      Copyright (C) 2000-2003 Broadcom Corporation.
12  *
13  *      Permission is hereby granted for the distribution of this firmware
14  *      data in hexadecimal or equivalent format, provided this copyright
15  *      notice is accompanying it.
16  */
17
18 #include <linux/config.h>
19
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/if_vlan.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/workqueue.h>
39 #include <linux/prefetch.h>
40
41 #include <net/checksum.h>
42
43 #include <asm/system.h>
44 #include <asm/io.h>
45 #include <asm/byteorder.h>
46 #include <asm/uaccess.h>
47
48 #ifdef CONFIG_SPARC64
49 #include <asm/idprom.h>
50 #include <asm/oplib.h>
51 #include <asm/pbm.h>
52 #endif
53
54 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
55 #define TG3_VLAN_TAG_USED 1
56 #else
57 #define TG3_VLAN_TAG_USED 0
58 #endif
59
60 #ifdef NETIF_F_TSO
61 #define TG3_TSO_SUPPORT 1
62 #else
63 #define TG3_TSO_SUPPORT 0
64 #endif
65
66 #include "tg3.h"
67
68 #define DRV_MODULE_NAME         "tg3"
69 #define PFX DRV_MODULE_NAME     ": "
70 #define DRV_MODULE_VERSION      "3.39"
71 #define DRV_MODULE_RELDATE      "September 5, 2005"
72
73 #define TG3_DEF_MAC_MODE        0
74 #define TG3_DEF_RX_MODE         0
75 #define TG3_DEF_TX_MODE         0
76 #define TG3_DEF_MSG_ENABLE        \
77         (NETIF_MSG_DRV          | \
78          NETIF_MSG_PROBE        | \
79          NETIF_MSG_LINK         | \
80          NETIF_MSG_TIMER        | \
81          NETIF_MSG_IFDOWN       | \
82          NETIF_MSG_IFUP         | \
83          NETIF_MSG_RX_ERR       | \
84          NETIF_MSG_TX_ERR)
85
86 /* length of time before we decide the hardware is borked,
87  * and dev->tx_timeout() should be called to fix the problem
88  */
89 #define TG3_TX_TIMEOUT                  (5 * HZ)
90
91 /* hardware minimum and maximum for a single frame's data payload */
92 #define TG3_MIN_MTU                     60
93 #define TG3_MAX_MTU(tp) \
94         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
95
96 /* These numbers seem to be hard coded in the NIC firmware somehow.
97  * You can't change the ring sizes, but you can change where you place
98  * them in the NIC onboard memory.
99  */
100 #define TG3_RX_RING_SIZE                512
101 #define TG3_DEF_RX_RING_PENDING         200
102 #define TG3_RX_JUMBO_RING_SIZE          256
103 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
104
105 /* Do not place this n-ring entries value into the tp struct itself,
106  * we really want to expose these constants to GCC so that modulo et
107  * al.  operations are done with shifts and masks instead of with
108  * hw multiply/modulo instructions.  Another solution would be to
109  * replace things like '% foo' with '& (foo - 1)'.
110  */
111 #define TG3_RX_RCB_RING_SIZE(tp)        \
112         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
113
114 #define TG3_TX_RING_SIZE                512
115 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
116
117 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
118                                  TG3_RX_RING_SIZE)
119 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
120                                  TG3_RX_JUMBO_RING_SIZE)
121 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
122                                    TG3_RX_RCB_RING_SIZE(tp))
123 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
124                                  TG3_TX_RING_SIZE)
125 #define TX_BUFFS_AVAIL(TP)                                              \
126         ((TP)->tx_pending -                                             \
127          (((TP)->tx_prod - (TP)->tx_cons) & (TG3_TX_RING_SIZE - 1)))
128 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
129
130 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
131 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
132
133 /* minimum number of free TX descriptors required to wake up TX process */
134 #define TG3_TX_WAKEUP_THRESH            (TG3_TX_RING_SIZE / 4)
135
136 /* number of ETHTOOL_GSTATS u64's */
137 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
138
139 #define TG3_NUM_TEST            6
140
141 static char version[] __devinitdata =
142         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
143
144 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
145 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
146 MODULE_LICENSE("GPL");
147 MODULE_VERSION(DRV_MODULE_VERSION);
148
149 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
150 module_param(tg3_debug, int, 0);
151 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
152
153 static struct pci_device_id tg3_pci_tbl[] = {
154         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700,
155           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
156         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701,
157           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
158         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702,
159           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
160         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703,
161           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
162         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704,
163           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
164         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE,
165           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
166         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705,
167           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
168         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2,
169           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
170         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M,
171           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
172         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2,
173           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
174         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X,
175           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
176         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X,
177           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
178         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S,
179           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
180         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3,
181           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
182         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3,
183           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
184         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782,
185           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
186         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788,
187           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
188         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789,
189           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
190         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901,
191           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
192         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2,
193           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
194         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2,
195           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
196         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F,
197           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
198         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720,
199           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
200         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721,
201           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
202         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750,
203           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
204         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751,
205           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
206         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M,
207           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
208         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M,
209           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
210         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F,
211           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
212         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752,
213           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
214         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M,
215           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
216         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753,
217           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
218         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M,
219           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
220         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F,
221           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
222         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780,
223           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
224         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S,
225           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
226         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781,
227           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
228         { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX,
229           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
230         { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX,
231           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
232         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000,
233           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
234         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001,
235           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
236         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003,
237           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
238         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100,
239           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
240         { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3,
241           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
242         { 0, }
243 };
244
245 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
246
247 static struct {
248         const char string[ETH_GSTRING_LEN];
249 } ethtool_stats_keys[TG3_NUM_STATS] = {
250         { "rx_octets" },
251         { "rx_fragments" },
252         { "rx_ucast_packets" },
253         { "rx_mcast_packets" },
254         { "rx_bcast_packets" },
255         { "rx_fcs_errors" },
256         { "rx_align_errors" },
257         { "rx_xon_pause_rcvd" },
258         { "rx_xoff_pause_rcvd" },
259         { "rx_mac_ctrl_rcvd" },
260         { "rx_xoff_entered" },
261         { "rx_frame_too_long_errors" },
262         { "rx_jabbers" },
263         { "rx_undersize_packets" },
264         { "rx_in_length_errors" },
265         { "rx_out_length_errors" },
266         { "rx_64_or_less_octet_packets" },
267         { "rx_65_to_127_octet_packets" },
268         { "rx_128_to_255_octet_packets" },
269         { "rx_256_to_511_octet_packets" },
270         { "rx_512_to_1023_octet_packets" },
271         { "rx_1024_to_1522_octet_packets" },
272         { "rx_1523_to_2047_octet_packets" },
273         { "rx_2048_to_4095_octet_packets" },
274         { "rx_4096_to_8191_octet_packets" },
275         { "rx_8192_to_9022_octet_packets" },
276
277         { "tx_octets" },
278         { "tx_collisions" },
279
280         { "tx_xon_sent" },
281         { "tx_xoff_sent" },
282         { "tx_flow_control" },
283         { "tx_mac_errors" },
284         { "tx_single_collisions" },
285         { "tx_mult_collisions" },
286         { "tx_deferred" },
287         { "tx_excessive_collisions" },
288         { "tx_late_collisions" },
289         { "tx_collide_2times" },
290         { "tx_collide_3times" },
291         { "tx_collide_4times" },
292         { "tx_collide_5times" },
293         { "tx_collide_6times" },
294         { "tx_collide_7times" },
295         { "tx_collide_8times" },
296         { "tx_collide_9times" },
297         { "tx_collide_10times" },
298         { "tx_collide_11times" },
299         { "tx_collide_12times" },
300         { "tx_collide_13times" },
301         { "tx_collide_14times" },
302         { "tx_collide_15times" },
303         { "tx_ucast_packets" },
304         { "tx_mcast_packets" },
305         { "tx_bcast_packets" },
306         { "tx_carrier_sense_errors" },
307         { "tx_discards" },
308         { "tx_errors" },
309
310         { "dma_writeq_full" },
311         { "dma_write_prioq_full" },
312         { "rxbds_empty" },
313         { "rx_discards" },
314         { "rx_errors" },
315         { "rx_threshold_hit" },
316
317         { "dma_readq_full" },
318         { "dma_read_prioq_full" },
319         { "tx_comp_queue_full" },
320
321         { "ring_set_send_prod_index" },
322         { "ring_status_update" },
323         { "nic_irqs" },
324         { "nic_avoided_irqs" },
325         { "nic_tx_threshold_hit" }
326 };
327
328 static struct {
329         const char string[ETH_GSTRING_LEN];
330 } ethtool_test_keys[TG3_NUM_TEST] = {
331         { "nvram test     (online) " },
332         { "link test      (online) " },
333         { "register test  (offline)" },
334         { "memory test    (offline)" },
335         { "loopback test  (offline)" },
336         { "interrupt test (offline)" },
337 };
338
339 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
340 {
341         unsigned long flags;
342
343         spin_lock_irqsave(&tp->indirect_lock, flags);
344         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
345         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
346         spin_unlock_irqrestore(&tp->indirect_lock, flags);
347 }
348
349 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
350 {
351         writel(val, tp->regs + off);
352         readl(tp->regs + off);
353 }
354
355 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
356 {
357         unsigned long flags;
358         u32 val;
359
360         spin_lock_irqsave(&tp->indirect_lock, flags);
361         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
362         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
363         spin_unlock_irqrestore(&tp->indirect_lock, flags);
364         return val;
365 }
366
367 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
368 {
369         unsigned long flags;
370
371         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
372                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
373                                        TG3_64BIT_REG_LOW, val);
374                 return;
375         }
376         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
377                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
378                                        TG3_64BIT_REG_LOW, val);
379                 return;
380         }
381
382         spin_lock_irqsave(&tp->indirect_lock, flags);
383         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
384         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
385         spin_unlock_irqrestore(&tp->indirect_lock, flags);
386
387         /* In indirect mode when disabling interrupts, we also need
388          * to clear the interrupt bit in the GRC local ctrl register.
389          */
390         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
391             (val == 0x1)) {
392                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
393                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
394         }
395 }
396
397 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
398 {
399         unsigned long flags;
400         u32 val;
401
402         spin_lock_irqsave(&tp->indirect_lock, flags);
403         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
404         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
405         spin_unlock_irqrestore(&tp->indirect_lock, flags);
406         return val;
407 }
408
409 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val)
410 {
411         tp->write32(tp, off, val);
412         if (!(tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) &&
413             !(tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG) &&
414             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
415                 tp->read32(tp, off);    /* flush */
416 }
417
418 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
419 {
420         tp->write32_mbox(tp, off, val);
421         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
422             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
423                 tp->read32_mbox(tp, off);
424 }
425
426 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
427 {
428         void __iomem *mbox = tp->regs + off;
429         writel(val, mbox);
430         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
431                 writel(val, mbox);
432         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
433                 readl(mbox);
434 }
435
436 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
437 {
438         writel(val, tp->regs + off);
439 }
440
441 static u32 tg3_read32(struct tg3 *tp, u32 off)
442 {
443         return (readl(tp->regs + off)); 
444 }
445
446 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
447 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
448 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
449 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
450 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
451
452 #define tw32(reg,val)           tp->write32(tp, reg, val)
453 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val))
454 #define tr32(reg)               tp->read32(tp, reg)
455
456 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
457 {
458         unsigned long flags;
459
460         spin_lock_irqsave(&tp->indirect_lock, flags);
461         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
462         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
463
464         /* Always leave this as zero. */
465         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
466         spin_unlock_irqrestore(&tp->indirect_lock, flags);
467 }
468
469 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
470 {
471         unsigned long flags;
472
473         spin_lock_irqsave(&tp->indirect_lock, flags);
474         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
475         pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
476
477         /* Always leave this as zero. */
478         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
479         spin_unlock_irqrestore(&tp->indirect_lock, flags);
480 }
481
482 static void tg3_disable_ints(struct tg3 *tp)
483 {
484         tw32(TG3PCI_MISC_HOST_CTRL,
485              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
486         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
487 }
488
489 static inline void tg3_cond_int(struct tg3 *tp)
490 {
491         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
492             (tp->hw_status->status & SD_STATUS_UPDATED))
493                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
494 }
495
496 static void tg3_enable_ints(struct tg3 *tp)
497 {
498         tp->irq_sync = 0;
499         wmb();
500
501         tw32(TG3PCI_MISC_HOST_CTRL,
502              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
503         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
504                        (tp->last_tag << 24));
505         tg3_cond_int(tp);
506 }
507
508 static inline unsigned int tg3_has_work(struct tg3 *tp)
509 {
510         struct tg3_hw_status *sblk = tp->hw_status;
511         unsigned int work_exists = 0;
512
513         /* check for phy events */
514         if (!(tp->tg3_flags &
515               (TG3_FLAG_USE_LINKCHG_REG |
516                TG3_FLAG_POLL_SERDES))) {
517                 if (sblk->status & SD_STATUS_LINK_CHG)
518                         work_exists = 1;
519         }
520         /* check for RX/TX work to do */
521         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
522             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
523                 work_exists = 1;
524
525         return work_exists;
526 }
527
528 /* tg3_restart_ints
529  *  similar to tg3_enable_ints, but it accurately determines whether there
530  *  is new work pending and can return without flushing the PIO write
531  *  which reenables interrupts 
532  */
533 static void tg3_restart_ints(struct tg3 *tp)
534 {
535         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
536                      tp->last_tag << 24);
537         mmiowb();
538
539         /* When doing tagged status, this work check is unnecessary.
540          * The last_tag we write above tells the chip which piece of
541          * work we've completed.
542          */
543         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
544             tg3_has_work(tp))
545                 tw32(HOSTCC_MODE, tp->coalesce_mode |
546                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
547 }
548
549 static inline void tg3_netif_stop(struct tg3 *tp)
550 {
551         tp->dev->trans_start = jiffies; /* prevent tx timeout */
552         netif_poll_disable(tp->dev);
553         netif_tx_disable(tp->dev);
554 }
555
556 static inline void tg3_netif_start(struct tg3 *tp)
557 {
558         netif_wake_queue(tp->dev);
559         /* NOTE: unconditional netif_wake_queue is only appropriate
560          * so long as all callers are assured to have free tx slots
561          * (such as after tg3_init_hw)
562          */
563         netif_poll_enable(tp->dev);
564         tp->hw_status->status |= SD_STATUS_UPDATED;
565         tg3_enable_ints(tp);
566 }
567
568 static void tg3_switch_clocks(struct tg3 *tp)
569 {
570         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
571         u32 orig_clock_ctrl;
572
573         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
574                 return;
575
576         orig_clock_ctrl = clock_ctrl;
577         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
578                        CLOCK_CTRL_CLKRUN_OENABLE |
579                        0x1f);
580         tp->pci_clock_ctrl = clock_ctrl;
581
582         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
583                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
584                         tw32_f(TG3PCI_CLOCK_CTRL,
585                                clock_ctrl | CLOCK_CTRL_625_CORE);
586                         udelay(40);
587                 }
588         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
589                 tw32_f(TG3PCI_CLOCK_CTRL,
590                      clock_ctrl |
591                      (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK));
592                 udelay(40);
593                 tw32_f(TG3PCI_CLOCK_CTRL,
594                      clock_ctrl | (CLOCK_CTRL_ALTCLK));
595                 udelay(40);
596         }
597         tw32_f(TG3PCI_CLOCK_CTRL, clock_ctrl);
598         udelay(40);
599 }
600
601 #define PHY_BUSY_LOOPS  5000
602
603 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
604 {
605         u32 frame_val;
606         unsigned int loops;
607         int ret;
608
609         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
610                 tw32_f(MAC_MI_MODE,
611                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
612                 udelay(80);
613         }
614
615         *val = 0x0;
616
617         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
618                       MI_COM_PHY_ADDR_MASK);
619         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
620                       MI_COM_REG_ADDR_MASK);
621         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
622         
623         tw32_f(MAC_MI_COM, frame_val);
624
625         loops = PHY_BUSY_LOOPS;
626         while (loops != 0) {
627                 udelay(10);
628                 frame_val = tr32(MAC_MI_COM);
629
630                 if ((frame_val & MI_COM_BUSY) == 0) {
631                         udelay(5);
632                         frame_val = tr32(MAC_MI_COM);
633                         break;
634                 }
635                 loops -= 1;
636         }
637
638         ret = -EBUSY;
639         if (loops != 0) {
640                 *val = frame_val & MI_COM_DATA_MASK;
641                 ret = 0;
642         }
643
644         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
645                 tw32_f(MAC_MI_MODE, tp->mi_mode);
646                 udelay(80);
647         }
648
649         return ret;
650 }
651
652 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
653 {
654         u32 frame_val;
655         unsigned int loops;
656         int ret;
657
658         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
659                 tw32_f(MAC_MI_MODE,
660                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
661                 udelay(80);
662         }
663
664         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
665                       MI_COM_PHY_ADDR_MASK);
666         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
667                       MI_COM_REG_ADDR_MASK);
668         frame_val |= (val & MI_COM_DATA_MASK);
669         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
670         
671         tw32_f(MAC_MI_COM, frame_val);
672
673         loops = PHY_BUSY_LOOPS;
674         while (loops != 0) {
675                 udelay(10);
676                 frame_val = tr32(MAC_MI_COM);
677                 if ((frame_val & MI_COM_BUSY) == 0) {
678                         udelay(5);
679                         frame_val = tr32(MAC_MI_COM);
680                         break;
681                 }
682                 loops -= 1;
683         }
684
685         ret = -EBUSY;
686         if (loops != 0)
687                 ret = 0;
688
689         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
690                 tw32_f(MAC_MI_MODE, tp->mi_mode);
691                 udelay(80);
692         }
693
694         return ret;
695 }
696
697 static void tg3_phy_set_wirespeed(struct tg3 *tp)
698 {
699         u32 val;
700
701         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
702                 return;
703
704         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
705             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
706                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
707                              (val | (1 << 15) | (1 << 4)));
708 }
709
710 static int tg3_bmcr_reset(struct tg3 *tp)
711 {
712         u32 phy_control;
713         int limit, err;
714
715         /* OK, reset it, and poll the BMCR_RESET bit until it
716          * clears or we time out.
717          */
718         phy_control = BMCR_RESET;
719         err = tg3_writephy(tp, MII_BMCR, phy_control);
720         if (err != 0)
721                 return -EBUSY;
722
723         limit = 5000;
724         while (limit--) {
725                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
726                 if (err != 0)
727                         return -EBUSY;
728
729                 if ((phy_control & BMCR_RESET) == 0) {
730                         udelay(40);
731                         break;
732                 }
733                 udelay(10);
734         }
735         if (limit <= 0)
736                 return -EBUSY;
737
738         return 0;
739 }
740
741 static int tg3_wait_macro_done(struct tg3 *tp)
742 {
743         int limit = 100;
744
745         while (limit--) {
746                 u32 tmp32;
747
748                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
749                         if ((tmp32 & 0x1000) == 0)
750                                 break;
751                 }
752         }
753         if (limit <= 0)
754                 return -EBUSY;
755
756         return 0;
757 }
758
759 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
760 {
761         static const u32 test_pat[4][6] = {
762         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
763         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
764         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
765         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
766         };
767         int chan;
768
769         for (chan = 0; chan < 4; chan++) {
770                 int i;
771
772                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
773                              (chan * 0x2000) | 0x0200);
774                 tg3_writephy(tp, 0x16, 0x0002);
775
776                 for (i = 0; i < 6; i++)
777                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
778                                      test_pat[chan][i]);
779
780                 tg3_writephy(tp, 0x16, 0x0202);
781                 if (tg3_wait_macro_done(tp)) {
782                         *resetp = 1;
783                         return -EBUSY;
784                 }
785
786                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
787                              (chan * 0x2000) | 0x0200);
788                 tg3_writephy(tp, 0x16, 0x0082);
789                 if (tg3_wait_macro_done(tp)) {
790                         *resetp = 1;
791                         return -EBUSY;
792                 }
793
794                 tg3_writephy(tp, 0x16, 0x0802);
795                 if (tg3_wait_macro_done(tp)) {
796                         *resetp = 1;
797                         return -EBUSY;
798                 }
799
800                 for (i = 0; i < 6; i += 2) {
801                         u32 low, high;
802
803                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
804                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
805                             tg3_wait_macro_done(tp)) {
806                                 *resetp = 1;
807                                 return -EBUSY;
808                         }
809                         low &= 0x7fff;
810                         high &= 0x000f;
811                         if (low != test_pat[chan][i] ||
812                             high != test_pat[chan][i+1]) {
813                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
814                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
815                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
816
817                                 return -EBUSY;
818                         }
819                 }
820         }
821
822         return 0;
823 }
824
825 static int tg3_phy_reset_chanpat(struct tg3 *tp)
826 {
827         int chan;
828
829         for (chan = 0; chan < 4; chan++) {
830                 int i;
831
832                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
833                              (chan * 0x2000) | 0x0200);
834                 tg3_writephy(tp, 0x16, 0x0002);
835                 for (i = 0; i < 6; i++)
836                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
837                 tg3_writephy(tp, 0x16, 0x0202);
838                 if (tg3_wait_macro_done(tp))
839                         return -EBUSY;
840         }
841
842         return 0;
843 }
844
845 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
846 {
847         u32 reg32, phy9_orig;
848         int retries, do_phy_reset, err;
849
850         retries = 10;
851         do_phy_reset = 1;
852         do {
853                 if (do_phy_reset) {
854                         err = tg3_bmcr_reset(tp);
855                         if (err)
856                                 return err;
857                         do_phy_reset = 0;
858                 }
859
860                 /* Disable transmitter and interrupt.  */
861                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
862                         continue;
863
864                 reg32 |= 0x3000;
865                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
866
867                 /* Set full-duplex, 1000 mbps.  */
868                 tg3_writephy(tp, MII_BMCR,
869                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
870
871                 /* Set to master mode.  */
872                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
873                         continue;
874
875                 tg3_writephy(tp, MII_TG3_CTRL,
876                              (MII_TG3_CTRL_AS_MASTER |
877                               MII_TG3_CTRL_ENABLE_AS_MASTER));
878
879                 /* Enable SM_DSP_CLOCK and 6dB.  */
880                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
881
882                 /* Block the PHY control access.  */
883                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
884                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
885
886                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
887                 if (!err)
888                         break;
889         } while (--retries);
890
891         err = tg3_phy_reset_chanpat(tp);
892         if (err)
893                 return err;
894
895         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
896         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
897
898         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
899         tg3_writephy(tp, 0x16, 0x0000);
900
901         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
902             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
903                 /* Set Extended packet length bit for jumbo frames */
904                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
905         }
906         else {
907                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
908         }
909
910         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
911
912         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
913                 reg32 &= ~0x3000;
914                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
915         } else if (!err)
916                 err = -EBUSY;
917
918         return err;
919 }
920
921 /* This will reset the tigon3 PHY if there is no valid
922  * link unless the FORCE argument is non-zero.
923  */
924 static int tg3_phy_reset(struct tg3 *tp)
925 {
926         u32 phy_status;
927         int err;
928
929         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
930         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
931         if (err != 0)
932                 return -EBUSY;
933
934         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
935             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
936             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
937                 err = tg3_phy_reset_5703_4_5(tp);
938                 if (err)
939                         return err;
940                 goto out;
941         }
942
943         err = tg3_bmcr_reset(tp);
944         if (err)
945                 return err;
946
947 out:
948         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
949                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
950                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
951                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
952                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
953                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
954                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
955         }
956         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
957                 tg3_writephy(tp, 0x1c, 0x8d68);
958                 tg3_writephy(tp, 0x1c, 0x8d68);
959         }
960         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
961                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
962                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
963                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
964                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
965                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
966                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
967                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
968                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
969         }
970         /* Set Extended packet length bit (bit 14) on all chips that */
971         /* support jumbo frames */
972         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
973                 /* Cannot do read-modify-write on 5401 */
974                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
975         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
976                 u32 phy_reg;
977
978                 /* Set bit 14 with read-modify-write to preserve other bits */
979                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
980                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
981                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
982         }
983
984         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
985          * jumbo frames transmission.
986          */
987         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
988                 u32 phy_reg;
989
990                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
991                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
992                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
993         }
994
995         tg3_phy_set_wirespeed(tp);
996         return 0;
997 }
998
999 static void tg3_frob_aux_power(struct tg3 *tp)
1000 {
1001         struct tg3 *tp_peer = tp;
1002
1003         if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0)
1004                 return;
1005
1006         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1007                 tp_peer = pci_get_drvdata(tp->pdev_peer);
1008                 if (!tp_peer)
1009                         BUG();
1010         }
1011
1012
1013         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1014             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0) {
1015                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1016                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1017                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1018                              (GRC_LCLCTRL_GPIO_OE0 |
1019                               GRC_LCLCTRL_GPIO_OE1 |
1020                               GRC_LCLCTRL_GPIO_OE2 |
1021                               GRC_LCLCTRL_GPIO_OUTPUT0 |
1022                               GRC_LCLCTRL_GPIO_OUTPUT1));
1023                         udelay(100);
1024                 } else {
1025                         u32 no_gpio2;
1026                         u32 grc_local_ctrl;
1027
1028                         if (tp_peer != tp &&
1029                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1030                                 return;
1031
1032                         /* On 5753 and variants, GPIO2 cannot be used. */
1033                         no_gpio2 = tp->nic_sram_data_cfg &
1034                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
1035
1036                         grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1037                                          GRC_LCLCTRL_GPIO_OE1 |
1038                                          GRC_LCLCTRL_GPIO_OE2 |
1039                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
1040                                          GRC_LCLCTRL_GPIO_OUTPUT2;
1041                         if (no_gpio2) {
1042                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1043                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
1044                         }
1045                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1046                                                 grc_local_ctrl);
1047                         udelay(100);
1048
1049                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1050
1051                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1052                                                 grc_local_ctrl);
1053                         udelay(100);
1054
1055                         if (!no_gpio2) {
1056                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1057                                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1058                                        grc_local_ctrl);
1059                                 udelay(100);
1060                         }
1061                 }
1062         } else {
1063                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1064                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1065                         if (tp_peer != tp &&
1066                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1067                                 return;
1068
1069                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1070                              (GRC_LCLCTRL_GPIO_OE1 |
1071                               GRC_LCLCTRL_GPIO_OUTPUT1));
1072                         udelay(100);
1073
1074                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1075                              (GRC_LCLCTRL_GPIO_OE1));
1076                         udelay(100);
1077
1078                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1079                              (GRC_LCLCTRL_GPIO_OE1 |
1080                               GRC_LCLCTRL_GPIO_OUTPUT1));
1081                         udelay(100);
1082                 }
1083         }
1084 }
1085
1086 static int tg3_setup_phy(struct tg3 *, int);
1087
1088 #define RESET_KIND_SHUTDOWN     0
1089 #define RESET_KIND_INIT         1
1090 #define RESET_KIND_SUSPEND      2
1091
1092 static void tg3_write_sig_post_reset(struct tg3 *, int);
1093 static int tg3_halt_cpu(struct tg3 *, u32);
1094
1095 static int tg3_set_power_state(struct tg3 *tp, int state)
1096 {
1097         u32 misc_host_ctrl;
1098         u16 power_control, power_caps;
1099         int pm = tp->pm_cap;
1100
1101         /* Make sure register accesses (indirect or otherwise)
1102          * will function correctly.
1103          */
1104         pci_write_config_dword(tp->pdev,
1105                                TG3PCI_MISC_HOST_CTRL,
1106                                tp->misc_host_ctrl);
1107
1108         pci_read_config_word(tp->pdev,
1109                              pm + PCI_PM_CTRL,
1110                              &power_control);
1111         power_control |= PCI_PM_CTRL_PME_STATUS;
1112         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1113         switch (state) {
1114         case 0:
1115                 power_control |= 0;
1116                 pci_write_config_word(tp->pdev,
1117                                       pm + PCI_PM_CTRL,
1118                                       power_control);
1119                 udelay(100);    /* Delay after power state change */
1120
1121                 /* Switch out of Vaux if it is not a LOM */
1122                 if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)) {
1123                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1124                         udelay(100);
1125                 }
1126
1127                 return 0;
1128
1129         case 1:
1130                 power_control |= 1;
1131                 break;
1132
1133         case 2:
1134                 power_control |= 2;
1135                 break;
1136
1137         case 3:
1138                 power_control |= 3;
1139                 break;
1140
1141         default:
1142                 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1143                        "requested.\n",
1144                        tp->dev->name, state);
1145                 return -EINVAL;
1146         };
1147
1148         power_control |= PCI_PM_CTRL_PME_ENABLE;
1149
1150         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1151         tw32(TG3PCI_MISC_HOST_CTRL,
1152              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1153
1154         if (tp->link_config.phy_is_low_power == 0) {
1155                 tp->link_config.phy_is_low_power = 1;
1156                 tp->link_config.orig_speed = tp->link_config.speed;
1157                 tp->link_config.orig_duplex = tp->link_config.duplex;
1158                 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1159         }
1160
1161         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1162                 tp->link_config.speed = SPEED_10;
1163                 tp->link_config.duplex = DUPLEX_HALF;
1164                 tp->link_config.autoneg = AUTONEG_ENABLE;
1165                 tg3_setup_phy(tp, 0);
1166         }
1167
1168         pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1169
1170         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1171                 u32 mac_mode;
1172
1173                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1174                         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1175                         udelay(40);
1176
1177                         mac_mode = MAC_MODE_PORT_MODE_MII;
1178
1179                         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1180                             !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1181                                 mac_mode |= MAC_MODE_LINK_POLARITY;
1182                 } else {
1183                         mac_mode = MAC_MODE_PORT_MODE_TBI;
1184                 }
1185
1186                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1187                         tw32(MAC_LED_CTRL, tp->led_ctrl);
1188
1189                 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1190                      (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1191                         mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1192
1193                 tw32_f(MAC_MODE, mac_mode);
1194                 udelay(100);
1195
1196                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1197                 udelay(10);
1198         }
1199
1200         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1201             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1202              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1203                 u32 base_val;
1204
1205                 base_val = tp->pci_clock_ctrl;
1206                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1207                              CLOCK_CTRL_TXCLK_DISABLE);
1208
1209                 tw32_f(TG3PCI_CLOCK_CTRL, base_val |
1210                      CLOCK_CTRL_ALTCLK |
1211                      CLOCK_CTRL_PWRDOWN_PLL133);
1212                 udelay(40);
1213         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
1214                 /* do nothing */
1215         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1216                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1217                 u32 newbits1, newbits2;
1218
1219                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1220                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1221                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1222                                     CLOCK_CTRL_TXCLK_DISABLE |
1223                                     CLOCK_CTRL_ALTCLK);
1224                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1225                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1226                         newbits1 = CLOCK_CTRL_625_CORE;
1227                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1228                 } else {
1229                         newbits1 = CLOCK_CTRL_ALTCLK;
1230                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1231                 }
1232
1233                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1);
1234                 udelay(40);
1235
1236                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2);
1237                 udelay(40);
1238
1239                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1240                         u32 newbits3;
1241
1242                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1243                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1244                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1245                                             CLOCK_CTRL_TXCLK_DISABLE |
1246                                             CLOCK_CTRL_44MHZ_CORE);
1247                         } else {
1248                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1249                         }
1250
1251                         tw32_f(TG3PCI_CLOCK_CTRL,
1252                                          tp->pci_clock_ctrl | newbits3);
1253                         udelay(40);
1254                 }
1255         }
1256
1257         tg3_frob_aux_power(tp);
1258
1259         /* Workaround for unstable PLL clock */
1260         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1261             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1262                 u32 val = tr32(0x7d00);
1263
1264                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1265                 tw32(0x7d00, val);
1266                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1267                         tg3_halt_cpu(tp, RX_CPU_BASE);
1268         }
1269
1270         /* Finally, set the new power state. */
1271         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1272         udelay(100);    /* Delay after power state change */
1273
1274         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1275
1276         return 0;
1277 }
1278
1279 static void tg3_link_report(struct tg3 *tp)
1280 {
1281         if (!netif_carrier_ok(tp->dev)) {
1282                 printk(KERN_INFO PFX "%s: Link is down.\n", tp->dev->name);
1283         } else {
1284                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1285                        tp->dev->name,
1286                        (tp->link_config.active_speed == SPEED_1000 ?
1287                         1000 :
1288                         (tp->link_config.active_speed == SPEED_100 ?
1289                          100 : 10)),
1290                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1291                         "full" : "half"));
1292
1293                 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1294                        "%s for RX.\n",
1295                        tp->dev->name,
1296                        (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1297                        (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1298         }
1299 }
1300
1301 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1302 {
1303         u32 new_tg3_flags = 0;
1304         u32 old_rx_mode = tp->rx_mode;
1305         u32 old_tx_mode = tp->tx_mode;
1306
1307         if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1308
1309                 /* Convert 1000BaseX flow control bits to 1000BaseT
1310                  * bits before resolving flow control.
1311                  */
1312                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1313                         local_adv &= ~(ADVERTISE_PAUSE_CAP |
1314                                        ADVERTISE_PAUSE_ASYM);
1315                         remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1316
1317                         if (local_adv & ADVERTISE_1000XPAUSE)
1318                                 local_adv |= ADVERTISE_PAUSE_CAP;
1319                         if (local_adv & ADVERTISE_1000XPSE_ASYM)
1320                                 local_adv |= ADVERTISE_PAUSE_ASYM;
1321                         if (remote_adv & LPA_1000XPAUSE)
1322                                 remote_adv |= LPA_PAUSE_CAP;
1323                         if (remote_adv & LPA_1000XPAUSE_ASYM)
1324                                 remote_adv |= LPA_PAUSE_ASYM;
1325                 }
1326
1327                 if (local_adv & ADVERTISE_PAUSE_CAP) {
1328                         if (local_adv & ADVERTISE_PAUSE_ASYM) {
1329                                 if (remote_adv & LPA_PAUSE_CAP)
1330                                         new_tg3_flags |=
1331                                                 (TG3_FLAG_RX_PAUSE |
1332                                                 TG3_FLAG_TX_PAUSE);
1333                                 else if (remote_adv & LPA_PAUSE_ASYM)
1334                                         new_tg3_flags |=
1335                                                 (TG3_FLAG_RX_PAUSE);
1336                         } else {
1337                                 if (remote_adv & LPA_PAUSE_CAP)
1338                                         new_tg3_flags |=
1339                                                 (TG3_FLAG_RX_PAUSE |
1340                                                 TG3_FLAG_TX_PAUSE);
1341                         }
1342                 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1343                         if ((remote_adv & LPA_PAUSE_CAP) &&
1344                         (remote_adv & LPA_PAUSE_ASYM))
1345                                 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1346                 }
1347
1348                 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1349                 tp->tg3_flags |= new_tg3_flags;
1350         } else {
1351                 new_tg3_flags = tp->tg3_flags;
1352         }
1353
1354         if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1355                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1356         else
1357                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1358
1359         if (old_rx_mode != tp->rx_mode) {
1360                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1361         }
1362         
1363         if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1364                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1365         else
1366                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1367
1368         if (old_tx_mode != tp->tx_mode) {
1369                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1370         }
1371 }
1372
1373 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1374 {
1375         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1376         case MII_TG3_AUX_STAT_10HALF:
1377                 *speed = SPEED_10;
1378                 *duplex = DUPLEX_HALF;
1379                 break;
1380
1381         case MII_TG3_AUX_STAT_10FULL:
1382                 *speed = SPEED_10;
1383                 *duplex = DUPLEX_FULL;
1384                 break;
1385
1386         case MII_TG3_AUX_STAT_100HALF:
1387                 *speed = SPEED_100;
1388                 *duplex = DUPLEX_HALF;
1389                 break;
1390
1391         case MII_TG3_AUX_STAT_100FULL:
1392                 *speed = SPEED_100;
1393                 *duplex = DUPLEX_FULL;
1394                 break;
1395
1396         case MII_TG3_AUX_STAT_1000HALF:
1397                 *speed = SPEED_1000;
1398                 *duplex = DUPLEX_HALF;
1399                 break;
1400
1401         case MII_TG3_AUX_STAT_1000FULL:
1402                 *speed = SPEED_1000;
1403                 *duplex = DUPLEX_FULL;
1404                 break;
1405
1406         default:
1407                 *speed = SPEED_INVALID;
1408                 *duplex = DUPLEX_INVALID;
1409                 break;
1410         };
1411 }
1412
1413 static void tg3_phy_copper_begin(struct tg3 *tp)
1414 {
1415         u32 new_adv;
1416         int i;
1417
1418         if (tp->link_config.phy_is_low_power) {
1419                 /* Entering low power mode.  Disable gigabit and
1420                  * 100baseT advertisements.
1421                  */
1422                 tg3_writephy(tp, MII_TG3_CTRL, 0);
1423
1424                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1425                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1426                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1427                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1428
1429                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1430         } else if (tp->link_config.speed == SPEED_INVALID) {
1431                 tp->link_config.advertising =
1432                         (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
1433                          ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
1434                          ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
1435                          ADVERTISED_Autoneg | ADVERTISED_MII);
1436
1437                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1438                         tp->link_config.advertising &=
1439                                 ~(ADVERTISED_1000baseT_Half |
1440                                   ADVERTISED_1000baseT_Full);
1441
1442                 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1443                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1444                         new_adv |= ADVERTISE_10HALF;
1445                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1446                         new_adv |= ADVERTISE_10FULL;
1447                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1448                         new_adv |= ADVERTISE_100HALF;
1449                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1450                         new_adv |= ADVERTISE_100FULL;
1451                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1452
1453                 if (tp->link_config.advertising &
1454                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1455                         new_adv = 0;
1456                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1457                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1458                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1459                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1460                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1461                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1462                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1463                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1464                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1465                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1466                 } else {
1467                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1468                 }
1469         } else {
1470                 /* Asking for a specific link mode. */
1471                 if (tp->link_config.speed == SPEED_1000) {
1472                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1473                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1474
1475                         if (tp->link_config.duplex == DUPLEX_FULL)
1476                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1477                         else
1478                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1479                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1480                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1481                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1482                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1483                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1484                 } else {
1485                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1486
1487                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1488                         if (tp->link_config.speed == SPEED_100) {
1489                                 if (tp->link_config.duplex == DUPLEX_FULL)
1490                                         new_adv |= ADVERTISE_100FULL;
1491                                 else
1492                                         new_adv |= ADVERTISE_100HALF;
1493                         } else {
1494                                 if (tp->link_config.duplex == DUPLEX_FULL)
1495                                         new_adv |= ADVERTISE_10FULL;
1496                                 else
1497                                         new_adv |= ADVERTISE_10HALF;
1498                         }
1499                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1500                 }
1501         }
1502
1503         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1504             tp->link_config.speed != SPEED_INVALID) {
1505                 u32 bmcr, orig_bmcr;
1506
1507                 tp->link_config.active_speed = tp->link_config.speed;
1508                 tp->link_config.active_duplex = tp->link_config.duplex;
1509
1510                 bmcr = 0;
1511                 switch (tp->link_config.speed) {
1512                 default:
1513                 case SPEED_10:
1514                         break;
1515
1516                 case SPEED_100:
1517                         bmcr |= BMCR_SPEED100;
1518                         break;
1519
1520                 case SPEED_1000:
1521                         bmcr |= TG3_BMCR_SPEED1000;
1522                         break;
1523                 };
1524
1525                 if (tp->link_config.duplex == DUPLEX_FULL)
1526                         bmcr |= BMCR_FULLDPLX;
1527
1528                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1529                     (bmcr != orig_bmcr)) {
1530                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1531                         for (i = 0; i < 1500; i++) {
1532                                 u32 tmp;
1533
1534                                 udelay(10);
1535                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1536                                     tg3_readphy(tp, MII_BMSR, &tmp))
1537                                         continue;
1538                                 if (!(tmp & BMSR_LSTATUS)) {
1539                                         udelay(40);
1540                                         break;
1541                                 }
1542                         }
1543                         tg3_writephy(tp, MII_BMCR, bmcr);
1544                         udelay(40);
1545                 }
1546         } else {
1547                 tg3_writephy(tp, MII_BMCR,
1548                              BMCR_ANENABLE | BMCR_ANRESTART);
1549         }
1550 }
1551
1552 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1553 {
1554         int err;
1555
1556         /* Turn off tap power management. */
1557         /* Set Extended packet length bit */
1558         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1559
1560         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1561         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1562
1563         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1564         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1565
1566         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1567         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1568
1569         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1570         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1571
1572         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1573         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1574
1575         udelay(40);
1576
1577         return err;
1578 }
1579
1580 static int tg3_copper_is_advertising_all(struct tg3 *tp)
1581 {
1582         u32 adv_reg, all_mask;
1583
1584         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1585                 return 0;
1586
1587         all_mask = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1588                     ADVERTISE_100HALF | ADVERTISE_100FULL);
1589         if ((adv_reg & all_mask) != all_mask)
1590                 return 0;
1591         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1592                 u32 tg3_ctrl;
1593
1594                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1595                         return 0;
1596
1597                 all_mask = (MII_TG3_CTRL_ADV_1000_HALF |
1598                             MII_TG3_CTRL_ADV_1000_FULL);
1599                 if ((tg3_ctrl & all_mask) != all_mask)
1600                         return 0;
1601         }
1602         return 1;
1603 }
1604
1605 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1606 {
1607         int current_link_up;
1608         u32 bmsr, dummy;
1609         u16 current_speed;
1610         u8 current_duplex;
1611         int i, err;
1612
1613         tw32(MAC_EVENT, 0);
1614
1615         tw32_f(MAC_STATUS,
1616              (MAC_STATUS_SYNC_CHANGED |
1617               MAC_STATUS_CFG_CHANGED |
1618               MAC_STATUS_MI_COMPLETION |
1619               MAC_STATUS_LNKSTATE_CHANGED));
1620         udelay(40);
1621
1622         tp->mi_mode = MAC_MI_MODE_BASE;
1623         tw32_f(MAC_MI_MODE, tp->mi_mode);
1624         udelay(80);
1625
1626         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1627
1628         /* Some third-party PHYs need to be reset on link going
1629          * down.
1630          */
1631         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1632              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1633              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1634             netif_carrier_ok(tp->dev)) {
1635                 tg3_readphy(tp, MII_BMSR, &bmsr);
1636                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1637                     !(bmsr & BMSR_LSTATUS))
1638                         force_reset = 1;
1639         }
1640         if (force_reset)
1641                 tg3_phy_reset(tp);
1642
1643         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1644                 tg3_readphy(tp, MII_BMSR, &bmsr);
1645                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1646                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1647                         bmsr = 0;
1648
1649                 if (!(bmsr & BMSR_LSTATUS)) {
1650                         err = tg3_init_5401phy_dsp(tp);
1651                         if (err)
1652                                 return err;
1653
1654                         tg3_readphy(tp, MII_BMSR, &bmsr);
1655                         for (i = 0; i < 1000; i++) {
1656                                 udelay(10);
1657                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1658                                     (bmsr & BMSR_LSTATUS)) {
1659                                         udelay(40);
1660                                         break;
1661                                 }
1662                         }
1663
1664                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1665                             !(bmsr & BMSR_LSTATUS) &&
1666                             tp->link_config.active_speed == SPEED_1000) {
1667                                 err = tg3_phy_reset(tp);
1668                                 if (!err)
1669                                         err = tg3_init_5401phy_dsp(tp);
1670                                 if (err)
1671                                         return err;
1672                         }
1673                 }
1674         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1675                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1676                 /* 5701 {A0,B0} CRC bug workaround */
1677                 tg3_writephy(tp, 0x15, 0x0a75);
1678                 tg3_writephy(tp, 0x1c, 0x8c68);
1679                 tg3_writephy(tp, 0x1c, 0x8d68);
1680                 tg3_writephy(tp, 0x1c, 0x8c68);
1681         }
1682
1683         /* Clear pending interrupts... */
1684         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1685         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1686
1687         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1688                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1689         else
1690                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1691
1692         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1693             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1694                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1695                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
1696                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1697                 else
1698                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1699         }
1700
1701         current_link_up = 0;
1702         current_speed = SPEED_INVALID;
1703         current_duplex = DUPLEX_INVALID;
1704
1705         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1706                 u32 val;
1707
1708                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1709                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1710                 if (!(val & (1 << 10))) {
1711                         val |= (1 << 10);
1712                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1713                         goto relink;
1714                 }
1715         }
1716
1717         bmsr = 0;
1718         for (i = 0; i < 100; i++) {
1719                 tg3_readphy(tp, MII_BMSR, &bmsr);
1720                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1721                     (bmsr & BMSR_LSTATUS))
1722                         break;
1723                 udelay(40);
1724         }
1725
1726         if (bmsr & BMSR_LSTATUS) {
1727                 u32 aux_stat, bmcr;
1728
1729                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1730                 for (i = 0; i < 2000; i++) {
1731                         udelay(10);
1732                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1733                             aux_stat)
1734                                 break;
1735                 }
1736
1737                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1738                                              &current_speed,
1739                                              &current_duplex);
1740
1741                 bmcr = 0;
1742                 for (i = 0; i < 200; i++) {
1743                         tg3_readphy(tp, MII_BMCR, &bmcr);
1744                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
1745                                 continue;
1746                         if (bmcr && bmcr != 0x7fff)
1747                                 break;
1748                         udelay(10);
1749                 }
1750
1751                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1752                         if (bmcr & BMCR_ANENABLE) {
1753                                 current_link_up = 1;
1754
1755                                 /* Force autoneg restart if we are exiting
1756                                  * low power mode.
1757                                  */
1758                                 if (!tg3_copper_is_advertising_all(tp))
1759                                         current_link_up = 0;
1760                         } else {
1761                                 current_link_up = 0;
1762                         }
1763                 } else {
1764                         if (!(bmcr & BMCR_ANENABLE) &&
1765                             tp->link_config.speed == current_speed &&
1766                             tp->link_config.duplex == current_duplex) {
1767                                 current_link_up = 1;
1768                         } else {
1769                                 current_link_up = 0;
1770                         }
1771                 }
1772
1773                 tp->link_config.active_speed = current_speed;
1774                 tp->link_config.active_duplex = current_duplex;
1775         }
1776
1777         if (current_link_up == 1 &&
1778             (tp->link_config.active_duplex == DUPLEX_FULL) &&
1779             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1780                 u32 local_adv, remote_adv;
1781
1782                 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1783                         local_adv = 0;
1784                 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1785
1786                 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1787                         remote_adv = 0;
1788
1789                 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1790
1791                 /* If we are not advertising full pause capability,
1792                  * something is wrong.  Bring the link down and reconfigure.
1793                  */
1794                 if (local_adv != ADVERTISE_PAUSE_CAP) {
1795                         current_link_up = 0;
1796                 } else {
1797                         tg3_setup_flow_control(tp, local_adv, remote_adv);
1798                 }
1799         }
1800 relink:
1801         if (current_link_up == 0) {
1802                 u32 tmp;
1803
1804                 tg3_phy_copper_begin(tp);
1805
1806                 tg3_readphy(tp, MII_BMSR, &tmp);
1807                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1808                     (tmp & BMSR_LSTATUS))
1809                         current_link_up = 1;
1810         }
1811
1812         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1813         if (current_link_up == 1) {
1814                 if (tp->link_config.active_speed == SPEED_100 ||
1815                     tp->link_config.active_speed == SPEED_10)
1816                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1817                 else
1818                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1819         } else
1820                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1821
1822         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1823         if (tp->link_config.active_duplex == DUPLEX_HALF)
1824                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1825
1826         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1827         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1828                 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1829                     (current_link_up == 1 &&
1830                      tp->link_config.active_speed == SPEED_10))
1831                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1832         } else {
1833                 if (current_link_up == 1)
1834                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1835         }
1836
1837         /* ??? Without this setting Netgear GA302T PHY does not
1838          * ??? send/receive packets...
1839          */
1840         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
1841             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
1842                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
1843                 tw32_f(MAC_MI_MODE, tp->mi_mode);
1844                 udelay(80);
1845         }
1846
1847         tw32_f(MAC_MODE, tp->mac_mode);
1848         udelay(40);
1849
1850         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
1851                 /* Polled via timer. */
1852                 tw32_f(MAC_EVENT, 0);
1853         } else {
1854                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
1855         }
1856         udelay(40);
1857
1858         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
1859             current_link_up == 1 &&
1860             tp->link_config.active_speed == SPEED_1000 &&
1861             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
1862              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
1863                 udelay(120);
1864                 tw32_f(MAC_STATUS,
1865                      (MAC_STATUS_SYNC_CHANGED |
1866                       MAC_STATUS_CFG_CHANGED));
1867                 udelay(40);
1868                 tg3_write_mem(tp,
1869                               NIC_SRAM_FIRMWARE_MBOX,
1870                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
1871         }
1872
1873         if (current_link_up != netif_carrier_ok(tp->dev)) {
1874                 if (current_link_up)
1875                         netif_carrier_on(tp->dev);
1876                 else
1877                         netif_carrier_off(tp->dev);
1878                 tg3_link_report(tp);
1879         }
1880
1881         return 0;
1882 }
1883
1884 struct tg3_fiber_aneginfo {
1885         int state;
1886 #define ANEG_STATE_UNKNOWN              0
1887 #define ANEG_STATE_AN_ENABLE            1
1888 #define ANEG_STATE_RESTART_INIT         2
1889 #define ANEG_STATE_RESTART              3
1890 #define ANEG_STATE_DISABLE_LINK_OK      4
1891 #define ANEG_STATE_ABILITY_DETECT_INIT  5
1892 #define ANEG_STATE_ABILITY_DETECT       6
1893 #define ANEG_STATE_ACK_DETECT_INIT      7
1894 #define ANEG_STATE_ACK_DETECT           8
1895 #define ANEG_STATE_COMPLETE_ACK_INIT    9
1896 #define ANEG_STATE_COMPLETE_ACK         10
1897 #define ANEG_STATE_IDLE_DETECT_INIT     11
1898 #define ANEG_STATE_IDLE_DETECT          12
1899 #define ANEG_STATE_LINK_OK              13
1900 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
1901 #define ANEG_STATE_NEXT_PAGE_WAIT       15
1902
1903         u32 flags;
1904 #define MR_AN_ENABLE            0x00000001
1905 #define MR_RESTART_AN           0x00000002
1906 #define MR_AN_COMPLETE          0x00000004
1907 #define MR_PAGE_RX              0x00000008
1908 #define MR_NP_LOADED            0x00000010
1909 #define MR_TOGGLE_TX            0x00000020
1910 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
1911 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
1912 #define MR_LP_ADV_SYM_PAUSE     0x00000100
1913 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
1914 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
1915 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
1916 #define MR_LP_ADV_NEXT_PAGE     0x00001000
1917 #define MR_TOGGLE_RX            0x00002000
1918 #define MR_NP_RX                0x00004000
1919
1920 #define MR_LINK_OK              0x80000000
1921
1922         unsigned long link_time, cur_time;
1923
1924         u32 ability_match_cfg;
1925         int ability_match_count;
1926
1927         char ability_match, idle_match, ack_match;
1928
1929         u32 txconfig, rxconfig;
1930 #define ANEG_CFG_NP             0x00000080
1931 #define ANEG_CFG_ACK            0x00000040
1932 #define ANEG_CFG_RF2            0x00000020
1933 #define ANEG_CFG_RF1            0x00000010
1934 #define ANEG_CFG_PS2            0x00000001
1935 #define ANEG_CFG_PS1            0x00008000
1936 #define ANEG_CFG_HD             0x00004000
1937 #define ANEG_CFG_FD             0x00002000
1938 #define ANEG_CFG_INVAL          0x00001f06
1939
1940 };
1941 #define ANEG_OK         0
1942 #define ANEG_DONE       1
1943 #define ANEG_TIMER_ENAB 2
1944 #define ANEG_FAILED     -1
1945
1946 #define ANEG_STATE_SETTLE_TIME  10000
1947
1948 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
1949                                    struct tg3_fiber_aneginfo *ap)
1950 {
1951         unsigned long delta;
1952         u32 rx_cfg_reg;
1953         int ret;
1954
1955         if (ap->state == ANEG_STATE_UNKNOWN) {
1956                 ap->rxconfig = 0;
1957                 ap->link_time = 0;
1958                 ap->cur_time = 0;
1959                 ap->ability_match_cfg = 0;
1960                 ap->ability_match_count = 0;
1961                 ap->ability_match = 0;
1962                 ap->idle_match = 0;
1963                 ap->ack_match = 0;
1964         }
1965         ap->cur_time++;
1966
1967         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
1968                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
1969
1970                 if (rx_cfg_reg != ap->ability_match_cfg) {
1971                         ap->ability_match_cfg = rx_cfg_reg;
1972                         ap->ability_match = 0;
1973                         ap->ability_match_count = 0;
1974                 } else {
1975                         if (++ap->ability_match_count > 1) {
1976                                 ap->ability_match = 1;
1977                                 ap->ability_match_cfg = rx_cfg_reg;
1978                         }
1979                 }
1980                 if (rx_cfg_reg & ANEG_CFG_ACK)
1981                         ap->ack_match = 1;
1982                 else
1983                         ap->ack_match = 0;
1984
1985                 ap->idle_match = 0;
1986         } else {
1987                 ap->idle_match = 1;
1988                 ap->ability_match_cfg = 0;
1989                 ap->ability_match_count = 0;
1990                 ap->ability_match = 0;
1991                 ap->ack_match = 0;
1992
1993                 rx_cfg_reg = 0;
1994         }
1995
1996         ap->rxconfig = rx_cfg_reg;
1997         ret = ANEG_OK;
1998
1999         switch(ap->state) {
2000         case ANEG_STATE_UNKNOWN:
2001                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2002                         ap->state = ANEG_STATE_AN_ENABLE;
2003
2004                 /* fallthru */
2005         case ANEG_STATE_AN_ENABLE:
2006                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2007                 if (ap->flags & MR_AN_ENABLE) {
2008                         ap->link_time = 0;
2009                         ap->cur_time = 0;
2010                         ap->ability_match_cfg = 0;
2011                         ap->ability_match_count = 0;
2012                         ap->ability_match = 0;
2013                         ap->idle_match = 0;
2014                         ap->ack_match = 0;
2015
2016                         ap->state = ANEG_STATE_RESTART_INIT;
2017                 } else {
2018                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
2019                 }
2020                 break;
2021
2022         case ANEG_STATE_RESTART_INIT:
2023                 ap->link_time = ap->cur_time;
2024                 ap->flags &= ~(MR_NP_LOADED);
2025                 ap->txconfig = 0;
2026                 tw32(MAC_TX_AUTO_NEG, 0);
2027                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2028                 tw32_f(MAC_MODE, tp->mac_mode);
2029                 udelay(40);
2030
2031                 ret = ANEG_TIMER_ENAB;
2032                 ap->state = ANEG_STATE_RESTART;
2033
2034                 /* fallthru */
2035         case ANEG_STATE_RESTART:
2036                 delta = ap->cur_time - ap->link_time;
2037                 if (delta > ANEG_STATE_SETTLE_TIME) {
2038                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2039                 } else {
2040                         ret = ANEG_TIMER_ENAB;
2041                 }
2042                 break;
2043
2044         case ANEG_STATE_DISABLE_LINK_OK:
2045                 ret = ANEG_DONE;
2046                 break;
2047
2048         case ANEG_STATE_ABILITY_DETECT_INIT:
2049                 ap->flags &= ~(MR_TOGGLE_TX);
2050                 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2051                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2052                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2053                 tw32_f(MAC_MODE, tp->mac_mode);
2054                 udelay(40);
2055
2056                 ap->state = ANEG_STATE_ABILITY_DETECT;
2057                 break;
2058
2059         case ANEG_STATE_ABILITY_DETECT:
2060                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2061                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
2062                 }
2063                 break;
2064
2065         case ANEG_STATE_ACK_DETECT_INIT:
2066                 ap->txconfig |= ANEG_CFG_ACK;
2067                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2068                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2069                 tw32_f(MAC_MODE, tp->mac_mode);
2070                 udelay(40);
2071
2072                 ap->state = ANEG_STATE_ACK_DETECT;
2073
2074                 /* fallthru */
2075         case ANEG_STATE_ACK_DETECT:
2076                 if (ap->ack_match != 0) {
2077                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2078                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2079                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2080                         } else {
2081                                 ap->state = ANEG_STATE_AN_ENABLE;
2082                         }
2083                 } else if (ap->ability_match != 0 &&
2084                            ap->rxconfig == 0) {
2085                         ap->state = ANEG_STATE_AN_ENABLE;
2086                 }
2087                 break;
2088
2089         case ANEG_STATE_COMPLETE_ACK_INIT:
2090                 if (ap->rxconfig & ANEG_CFG_INVAL) {
2091                         ret = ANEG_FAILED;
2092                         break;
2093                 }
2094                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2095                                MR_LP_ADV_HALF_DUPLEX |
2096                                MR_LP_ADV_SYM_PAUSE |
2097                                MR_LP_ADV_ASYM_PAUSE |
2098                                MR_LP_ADV_REMOTE_FAULT1 |
2099                                MR_LP_ADV_REMOTE_FAULT2 |
2100                                MR_LP_ADV_NEXT_PAGE |
2101                                MR_TOGGLE_RX |
2102                                MR_NP_RX);
2103                 if (ap->rxconfig & ANEG_CFG_FD)
2104                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2105                 if (ap->rxconfig & ANEG_CFG_HD)
2106                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2107                 if (ap->rxconfig & ANEG_CFG_PS1)
2108                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
2109                 if (ap->rxconfig & ANEG_CFG_PS2)
2110                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2111                 if (ap->rxconfig & ANEG_CFG_RF1)
2112                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2113                 if (ap->rxconfig & ANEG_CFG_RF2)
2114                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2115                 if (ap->rxconfig & ANEG_CFG_NP)
2116                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
2117
2118                 ap->link_time = ap->cur_time;
2119
2120                 ap->flags ^= (MR_TOGGLE_TX);
2121                 if (ap->rxconfig & 0x0008)
2122                         ap->flags |= MR_TOGGLE_RX;
2123                 if (ap->rxconfig & ANEG_CFG_NP)
2124                         ap->flags |= MR_NP_RX;
2125                 ap->flags |= MR_PAGE_RX;
2126
2127                 ap->state = ANEG_STATE_COMPLETE_ACK;
2128                 ret = ANEG_TIMER_ENAB;
2129                 break;
2130
2131         case ANEG_STATE_COMPLETE_ACK:
2132                 if (ap->ability_match != 0 &&
2133                     ap->rxconfig == 0) {
2134                         ap->state = ANEG_STATE_AN_ENABLE;
2135                         break;
2136                 }
2137                 delta = ap->cur_time - ap->link_time;
2138                 if (delta > ANEG_STATE_SETTLE_TIME) {
2139                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2140                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2141                         } else {
2142                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2143                                     !(ap->flags & MR_NP_RX)) {
2144                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2145                                 } else {
2146                                         ret = ANEG_FAILED;
2147                                 }
2148                         }
2149                 }
2150                 break;
2151
2152         case ANEG_STATE_IDLE_DETECT_INIT:
2153                 ap->link_time = ap->cur_time;
2154                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2155                 tw32_f(MAC_MODE, tp->mac_mode);
2156                 udelay(40);
2157
2158                 ap->state = ANEG_STATE_IDLE_DETECT;
2159                 ret = ANEG_TIMER_ENAB;
2160                 break;
2161
2162         case ANEG_STATE_IDLE_DETECT:
2163                 if (ap->ability_match != 0 &&
2164                     ap->rxconfig == 0) {
2165                         ap->state = ANEG_STATE_AN_ENABLE;
2166                         break;
2167                 }
2168                 delta = ap->cur_time - ap->link_time;
2169                 if (delta > ANEG_STATE_SETTLE_TIME) {
2170                         /* XXX another gem from the Broadcom driver :( */
2171                         ap->state = ANEG_STATE_LINK_OK;
2172                 }
2173                 break;
2174
2175         case ANEG_STATE_LINK_OK:
2176                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2177                 ret = ANEG_DONE;
2178                 break;
2179
2180         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2181                 /* ??? unimplemented */
2182                 break;
2183
2184         case ANEG_STATE_NEXT_PAGE_WAIT:
2185                 /* ??? unimplemented */
2186                 break;
2187
2188         default:
2189                 ret = ANEG_FAILED;
2190                 break;
2191         };
2192
2193         return ret;
2194 }
2195
2196 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2197 {
2198         int res = 0;
2199         struct tg3_fiber_aneginfo aninfo;
2200         int status = ANEG_FAILED;
2201         unsigned int tick;
2202         u32 tmp;
2203
2204         tw32_f(MAC_TX_AUTO_NEG, 0);
2205
2206         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2207         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2208         udelay(40);
2209
2210         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2211         udelay(40);
2212
2213         memset(&aninfo, 0, sizeof(aninfo));
2214         aninfo.flags |= MR_AN_ENABLE;
2215         aninfo.state = ANEG_STATE_UNKNOWN;
2216         aninfo.cur_time = 0;
2217         tick = 0;
2218         while (++tick < 195000) {
2219                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2220                 if (status == ANEG_DONE || status == ANEG_FAILED)
2221                         break;
2222
2223                 udelay(1);
2224         }
2225
2226         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2227         tw32_f(MAC_MODE, tp->mac_mode);
2228         udelay(40);
2229
2230         *flags = aninfo.flags;
2231
2232         if (status == ANEG_DONE &&
2233             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2234                              MR_LP_ADV_FULL_DUPLEX)))
2235                 res = 1;
2236
2237         return res;
2238 }
2239
2240 static void tg3_init_bcm8002(struct tg3 *tp)
2241 {
2242         u32 mac_status = tr32(MAC_STATUS);
2243         int i;
2244
2245         /* Reset when initting first time or we have a link. */
2246         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2247             !(mac_status & MAC_STATUS_PCS_SYNCED))
2248                 return;
2249
2250         /* Set PLL lock range. */
2251         tg3_writephy(tp, 0x16, 0x8007);
2252
2253         /* SW reset */
2254         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2255
2256         /* Wait for reset to complete. */
2257         /* XXX schedule_timeout() ... */
2258         for (i = 0; i < 500; i++)
2259                 udelay(10);
2260
2261         /* Config mode; select PMA/Ch 1 regs. */
2262         tg3_writephy(tp, 0x10, 0x8411);
2263
2264         /* Enable auto-lock and comdet, select txclk for tx. */
2265         tg3_writephy(tp, 0x11, 0x0a10);
2266
2267         tg3_writephy(tp, 0x18, 0x00a0);
2268         tg3_writephy(tp, 0x16, 0x41ff);
2269
2270         /* Assert and deassert POR. */
2271         tg3_writephy(tp, 0x13, 0x0400);
2272         udelay(40);
2273         tg3_writephy(tp, 0x13, 0x0000);
2274
2275         tg3_writephy(tp, 0x11, 0x0a50);
2276         udelay(40);
2277         tg3_writephy(tp, 0x11, 0x0a10);
2278
2279         /* Wait for signal to stabilize */
2280         /* XXX schedule_timeout() ... */
2281         for (i = 0; i < 15000; i++)
2282                 udelay(10);
2283
2284         /* Deselect the channel register so we can read the PHYID
2285          * later.
2286          */
2287         tg3_writephy(tp, 0x10, 0x8011);
2288 }
2289
2290 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2291 {
2292         u32 sg_dig_ctrl, sg_dig_status;
2293         u32 serdes_cfg, expected_sg_dig_ctrl;
2294         int workaround, port_a;
2295         int current_link_up;
2296
2297         serdes_cfg = 0;
2298         expected_sg_dig_ctrl = 0;
2299         workaround = 0;
2300         port_a = 1;
2301         current_link_up = 0;
2302
2303         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2304             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2305                 workaround = 1;
2306                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2307                         port_a = 0;
2308
2309                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2310                 /* preserve bits 20-23 for voltage regulator */
2311                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2312         }
2313
2314         sg_dig_ctrl = tr32(SG_DIG_CTRL);
2315
2316         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2317                 if (sg_dig_ctrl & (1 << 31)) {
2318                         if (workaround) {
2319                                 u32 val = serdes_cfg;
2320
2321                                 if (port_a)
2322                                         val |= 0xc010000;
2323                                 else
2324                                         val |= 0x4010000;
2325                                 tw32_f(MAC_SERDES_CFG, val);
2326                         }
2327                         tw32_f(SG_DIG_CTRL, 0x01388400);
2328                 }
2329                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2330                         tg3_setup_flow_control(tp, 0, 0);
2331                         current_link_up = 1;
2332                 }
2333                 goto out;
2334         }
2335
2336         /* Want auto-negotiation.  */
2337         expected_sg_dig_ctrl = 0x81388400;
2338
2339         /* Pause capability */
2340         expected_sg_dig_ctrl |= (1 << 11);
2341
2342         /* Asymettric pause */
2343         expected_sg_dig_ctrl |= (1 << 12);
2344
2345         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2346                 if (workaround)
2347                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2348                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2349                 udelay(5);
2350                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2351
2352                 tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2353         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2354                                  MAC_STATUS_SIGNAL_DET)) {
2355                 int i;
2356
2357                 /* Giver time to negotiate (~200ms) */
2358                 for (i = 0; i < 40000; i++) {
2359                         sg_dig_status = tr32(SG_DIG_STATUS);
2360                         if (sg_dig_status & (0x3))
2361                                 break;
2362                         udelay(5);
2363                 }
2364                 mac_status = tr32(MAC_STATUS);
2365
2366                 if ((sg_dig_status & (1 << 1)) &&
2367                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
2368                         u32 local_adv, remote_adv;
2369
2370                         local_adv = ADVERTISE_PAUSE_CAP;
2371                         remote_adv = 0;
2372                         if (sg_dig_status & (1 << 19))
2373                                 remote_adv |= LPA_PAUSE_CAP;
2374                         if (sg_dig_status & (1 << 20))
2375                                 remote_adv |= LPA_PAUSE_ASYM;
2376
2377                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2378                         current_link_up = 1;
2379                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2380                 } else if (!(sg_dig_status & (1 << 1))) {
2381                         if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED)
2382                                 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2383                         else {
2384                                 if (workaround) {
2385                                         u32 val = serdes_cfg;
2386
2387                                         if (port_a)
2388                                                 val |= 0xc010000;
2389                                         else
2390                                                 val |= 0x4010000;
2391
2392                                         tw32_f(MAC_SERDES_CFG, val);
2393                                 }
2394
2395                                 tw32_f(SG_DIG_CTRL, 0x01388400);
2396                                 udelay(40);
2397
2398                                 /* Link parallel detection - link is up */
2399                                 /* only if we have PCS_SYNC and not */
2400                                 /* receiving config code words */
2401                                 mac_status = tr32(MAC_STATUS);
2402                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2403                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
2404                                         tg3_setup_flow_control(tp, 0, 0);
2405                                         current_link_up = 1;
2406                                 }
2407                         }
2408                 }
2409         }
2410
2411 out:
2412         return current_link_up;
2413 }
2414
2415 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2416 {
2417         int current_link_up = 0;
2418
2419         if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2420                 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2421                 goto out;
2422         }
2423
2424         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2425                 u32 flags;
2426                 int i;
2427   
2428                 if (fiber_autoneg(tp, &flags)) {
2429                         u32 local_adv, remote_adv;
2430
2431                         local_adv = ADVERTISE_PAUSE_CAP;
2432                         remote_adv = 0;
2433                         if (flags & MR_LP_ADV_SYM_PAUSE)
2434                                 remote_adv |= LPA_PAUSE_CAP;
2435                         if (flags & MR_LP_ADV_ASYM_PAUSE)
2436                                 remote_adv |= LPA_PAUSE_ASYM;
2437
2438                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2439
2440                         tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2441                         current_link_up = 1;
2442                 }
2443                 for (i = 0; i < 30; i++) {
2444                         udelay(20);
2445                         tw32_f(MAC_STATUS,
2446                                (MAC_STATUS_SYNC_CHANGED |
2447                                 MAC_STATUS_CFG_CHANGED));
2448                         udelay(40);
2449                         if ((tr32(MAC_STATUS) &
2450                              (MAC_STATUS_SYNC_CHANGED |
2451                               MAC_STATUS_CFG_CHANGED)) == 0)
2452                                 break;
2453                 }
2454
2455                 mac_status = tr32(MAC_STATUS);
2456                 if (current_link_up == 0 &&
2457                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
2458                     !(mac_status & MAC_STATUS_RCVD_CFG))
2459                         current_link_up = 1;
2460         } else {
2461                 /* Forcing 1000FD link up. */
2462                 current_link_up = 1;
2463                 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2464
2465                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2466                 udelay(40);
2467         }
2468
2469 out:
2470         return current_link_up;
2471 }
2472
2473 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2474 {
2475         u32 orig_pause_cfg;
2476         u16 orig_active_speed;
2477         u8 orig_active_duplex;
2478         u32 mac_status;
2479         int current_link_up;
2480         int i;
2481
2482         orig_pause_cfg =
2483                 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2484                                   TG3_FLAG_TX_PAUSE));
2485         orig_active_speed = tp->link_config.active_speed;
2486         orig_active_duplex = tp->link_config.active_duplex;
2487
2488         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2489             netif_carrier_ok(tp->dev) &&
2490             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2491                 mac_status = tr32(MAC_STATUS);
2492                 mac_status &= (MAC_STATUS_PCS_SYNCED |
2493                                MAC_STATUS_SIGNAL_DET |
2494                                MAC_STATUS_CFG_CHANGED |
2495                                MAC_STATUS_RCVD_CFG);
2496                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2497                                    MAC_STATUS_SIGNAL_DET)) {
2498                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2499                                             MAC_STATUS_CFG_CHANGED));
2500                         return 0;
2501                 }
2502         }
2503
2504         tw32_f(MAC_TX_AUTO_NEG, 0);
2505
2506         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2507         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2508         tw32_f(MAC_MODE, tp->mac_mode);
2509         udelay(40);
2510
2511         if (tp->phy_id == PHY_ID_BCM8002)
2512                 tg3_init_bcm8002(tp);
2513
2514         /* Enable link change event even when serdes polling.  */
2515         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2516         udelay(40);
2517
2518         current_link_up = 0;
2519         mac_status = tr32(MAC_STATUS);
2520
2521         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2522                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2523         else
2524                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2525
2526         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2527         tw32_f(MAC_MODE, tp->mac_mode);
2528         udelay(40);
2529
2530         tp->hw_status->status =
2531                 (SD_STATUS_UPDATED |
2532                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2533
2534         for (i = 0; i < 100; i++) {
2535                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2536                                     MAC_STATUS_CFG_CHANGED));
2537                 udelay(5);
2538                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2539                                          MAC_STATUS_CFG_CHANGED)) == 0)
2540                         break;
2541         }
2542
2543         mac_status = tr32(MAC_STATUS);
2544         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2545                 current_link_up = 0;
2546                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2547                         tw32_f(MAC_MODE, (tp->mac_mode |
2548                                           MAC_MODE_SEND_CONFIGS));
2549                         udelay(1);
2550                         tw32_f(MAC_MODE, tp->mac_mode);
2551                 }
2552         }
2553
2554         if (current_link_up == 1) {
2555                 tp->link_config.active_speed = SPEED_1000;
2556                 tp->link_config.active_duplex = DUPLEX_FULL;
2557                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2558                                     LED_CTRL_LNKLED_OVERRIDE |
2559                                     LED_CTRL_1000MBPS_ON));
2560         } else {
2561                 tp->link_config.active_speed = SPEED_INVALID;
2562                 tp->link_config.active_duplex = DUPLEX_INVALID;
2563                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2564                                     LED_CTRL_LNKLED_OVERRIDE |
2565                                     LED_CTRL_TRAFFIC_OVERRIDE));
2566         }
2567
2568         if (current_link_up != netif_carrier_ok(tp->dev)) {
2569                 if (current_link_up)
2570                         netif_carrier_on(tp->dev);
2571                 else
2572                         netif_carrier_off(tp->dev);
2573                 tg3_link_report(tp);
2574         } else {
2575                 u32 now_pause_cfg =
2576                         tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2577                                          TG3_FLAG_TX_PAUSE);
2578                 if (orig_pause_cfg != now_pause_cfg ||
2579                     orig_active_speed != tp->link_config.active_speed ||
2580                     orig_active_duplex != tp->link_config.active_duplex)
2581                         tg3_link_report(tp);
2582         }
2583
2584         return 0;
2585 }
2586
2587 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2588 {
2589         int current_link_up, err = 0;
2590         u32 bmsr, bmcr;
2591         u16 current_speed;
2592         u8 current_duplex;
2593
2594         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2595         tw32_f(MAC_MODE, tp->mac_mode);
2596         udelay(40);
2597
2598         tw32(MAC_EVENT, 0);
2599
2600         tw32_f(MAC_STATUS,
2601              (MAC_STATUS_SYNC_CHANGED |
2602               MAC_STATUS_CFG_CHANGED |
2603               MAC_STATUS_MI_COMPLETION |
2604               MAC_STATUS_LNKSTATE_CHANGED));
2605         udelay(40);
2606
2607         if (force_reset)
2608                 tg3_phy_reset(tp);
2609
2610         current_link_up = 0;
2611         current_speed = SPEED_INVALID;
2612         current_duplex = DUPLEX_INVALID;
2613
2614         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2615         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2616
2617         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2618
2619         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2620             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2621                 /* do nothing, just check for link up at the end */
2622         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2623                 u32 adv, new_adv;
2624
2625                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2626                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2627                                   ADVERTISE_1000XPAUSE |
2628                                   ADVERTISE_1000XPSE_ASYM |
2629                                   ADVERTISE_SLCT);
2630
2631                 /* Always advertise symmetric PAUSE just like copper */
2632                 new_adv |= ADVERTISE_1000XPAUSE;
2633
2634                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2635                         new_adv |= ADVERTISE_1000XHALF;
2636                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2637                         new_adv |= ADVERTISE_1000XFULL;
2638
2639                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2640                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2641                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2642                         tg3_writephy(tp, MII_BMCR, bmcr);
2643
2644                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2645                         tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2646                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2647
2648                         return err;
2649                 }
2650         } else {
2651                 u32 new_bmcr;
2652
2653                 bmcr &= ~BMCR_SPEED1000;
2654                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2655
2656                 if (tp->link_config.duplex == DUPLEX_FULL)
2657                         new_bmcr |= BMCR_FULLDPLX;
2658
2659                 if (new_bmcr != bmcr) {
2660                         /* BMCR_SPEED1000 is a reserved bit that needs
2661                          * to be set on write.
2662                          */
2663                         new_bmcr |= BMCR_SPEED1000;
2664
2665                         /* Force a linkdown */
2666                         if (netif_carrier_ok(tp->dev)) {
2667                                 u32 adv;
2668
2669                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2670                                 adv &= ~(ADVERTISE_1000XFULL |
2671                                          ADVERTISE_1000XHALF |
2672                                          ADVERTISE_SLCT);
2673                                 tg3_writephy(tp, MII_ADVERTISE, adv);
2674                                 tg3_writephy(tp, MII_BMCR, bmcr |
2675                                                            BMCR_ANRESTART |
2676                                                            BMCR_ANENABLE);
2677                                 udelay(10);
2678                                 netif_carrier_off(tp->dev);
2679                         }
2680                         tg3_writephy(tp, MII_BMCR, new_bmcr);
2681                         bmcr = new_bmcr;
2682                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2683                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2684                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2685                 }
2686         }
2687
2688         if (bmsr & BMSR_LSTATUS) {
2689                 current_speed = SPEED_1000;
2690                 current_link_up = 1;
2691                 if (bmcr & BMCR_FULLDPLX)
2692                         current_duplex = DUPLEX_FULL;
2693                 else
2694                         current_duplex = DUPLEX_HALF;
2695
2696                 if (bmcr & BMCR_ANENABLE) {
2697                         u32 local_adv, remote_adv, common;
2698
2699                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2700                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2701                         common = local_adv & remote_adv;
2702                         if (common & (ADVERTISE_1000XHALF |
2703                                       ADVERTISE_1000XFULL)) {
2704                                 if (common & ADVERTISE_1000XFULL)
2705                                         current_duplex = DUPLEX_FULL;
2706                                 else
2707                                         current_duplex = DUPLEX_HALF;
2708
2709                                 tg3_setup_flow_control(tp, local_adv,
2710                                                        remote_adv);
2711                         }
2712                         else
2713                                 current_link_up = 0;
2714                 }
2715         }
2716
2717         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2718         if (tp->link_config.active_duplex == DUPLEX_HALF)
2719                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2720
2721         tw32_f(MAC_MODE, tp->mac_mode);
2722         udelay(40);
2723
2724         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2725
2726         tp->link_config.active_speed = current_speed;
2727         tp->link_config.active_duplex = current_duplex;
2728
2729         if (current_link_up != netif_carrier_ok(tp->dev)) {
2730                 if (current_link_up)
2731                         netif_carrier_on(tp->dev);
2732                 else {
2733                         netif_carrier_off(tp->dev);
2734                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2735                 }
2736                 tg3_link_report(tp);
2737         }
2738         return err;
2739 }
2740
2741 static void tg3_serdes_parallel_detect(struct tg3 *tp)
2742 {
2743         if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED) {
2744                 /* Give autoneg time to complete. */
2745                 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2746                 return;
2747         }
2748         if (!netif_carrier_ok(tp->dev) &&
2749             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2750                 u32 bmcr;
2751
2752                 tg3_readphy(tp, MII_BMCR, &bmcr);
2753                 if (bmcr & BMCR_ANENABLE) {
2754                         u32 phy1, phy2;
2755
2756                         /* Select shadow register 0x1f */
2757                         tg3_writephy(tp, 0x1c, 0x7c00);
2758                         tg3_readphy(tp, 0x1c, &phy1);
2759
2760                         /* Select expansion interrupt status register */
2761                         tg3_writephy(tp, 0x17, 0x0f01);
2762                         tg3_readphy(tp, 0x15, &phy2);
2763                         tg3_readphy(tp, 0x15, &phy2);
2764
2765                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2766                                 /* We have signal detect and not receiving
2767                                  * config code words, link is up by parallel
2768                                  * detection.
2769                                  */
2770
2771                                 bmcr &= ~BMCR_ANENABLE;
2772                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
2773                                 tg3_writephy(tp, MII_BMCR, bmcr);
2774                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
2775                         }
2776                 }
2777         }
2778         else if (netif_carrier_ok(tp->dev) &&
2779                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
2780                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2781                 u32 phy2;
2782
2783                 /* Select expansion interrupt status register */
2784                 tg3_writephy(tp, 0x17, 0x0f01);
2785                 tg3_readphy(tp, 0x15, &phy2);
2786                 if (phy2 & 0x20) {
2787                         u32 bmcr;
2788
2789                         /* Config code words received, turn on autoneg. */
2790                         tg3_readphy(tp, MII_BMCR, &bmcr);
2791                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
2792
2793                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2794
2795                 }
2796         }
2797 }
2798
2799 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2800 {
2801         int err;
2802
2803         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2804                 err = tg3_setup_fiber_phy(tp, force_reset);
2805         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
2806                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
2807         } else {
2808                 err = tg3_setup_copper_phy(tp, force_reset);
2809         }
2810
2811         if (tp->link_config.active_speed == SPEED_1000 &&
2812             tp->link_config.active_duplex == DUPLEX_HALF)
2813                 tw32(MAC_TX_LENGTHS,
2814                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2815                       (6 << TX_LENGTHS_IPG_SHIFT) |
2816                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2817         else
2818                 tw32(MAC_TX_LENGTHS,
2819                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2820                       (6 << TX_LENGTHS_IPG_SHIFT) |
2821                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2822
2823         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2824                 if (netif_carrier_ok(tp->dev)) {
2825                         tw32(HOSTCC_STAT_COAL_TICKS,
2826                              tp->coal.stats_block_coalesce_usecs);
2827                 } else {
2828                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
2829                 }
2830         }
2831
2832         return err;
2833 }
2834
2835 /* Tigon3 never reports partial packet sends.  So we do not
2836  * need special logic to handle SKBs that have not had all
2837  * of their frags sent yet, like SunGEM does.
2838  */
2839 static void tg3_tx(struct tg3 *tp)
2840 {
2841         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
2842         u32 sw_idx = tp->tx_cons;
2843
2844         while (sw_idx != hw_idx) {
2845                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
2846                 struct sk_buff *skb = ri->skb;
2847                 int i;
2848
2849                 if (unlikely(skb == NULL))
2850                         BUG();
2851
2852                 pci_unmap_single(tp->pdev,
2853                                  pci_unmap_addr(ri, mapping),
2854                                  skb_headlen(skb),
2855                                  PCI_DMA_TODEVICE);
2856
2857                 ri->skb = NULL;
2858
2859                 sw_idx = NEXT_TX(sw_idx);
2860
2861                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2862                         if (unlikely(sw_idx == hw_idx))
2863                                 BUG();
2864
2865                         ri = &tp->tx_buffers[sw_idx];
2866                         if (unlikely(ri->skb != NULL))
2867                                 BUG();
2868
2869                         pci_unmap_page(tp->pdev,
2870                                        pci_unmap_addr(ri, mapping),
2871                                        skb_shinfo(skb)->frags[i].size,
2872                                        PCI_DMA_TODEVICE);
2873
2874                         sw_idx = NEXT_TX(sw_idx);
2875                 }
2876
2877                 dev_kfree_skb(skb);
2878         }
2879
2880         tp->tx_cons = sw_idx;
2881
2882         if (unlikely(netif_queue_stopped(tp->dev))) {
2883                 spin_lock(&tp->tx_lock);
2884                 if (netif_queue_stopped(tp->dev) &&
2885                     (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH))
2886                         netif_wake_queue(tp->dev);
2887                 spin_unlock(&tp->tx_lock);
2888         }
2889 }
2890
2891 /* Returns size of skb allocated or < 0 on error.
2892  *
2893  * We only need to fill in the address because the other members
2894  * of the RX descriptor are invariant, see tg3_init_rings.
2895  *
2896  * Note the purposeful assymetry of cpu vs. chip accesses.  For
2897  * posting buffers we only dirty the first cache line of the RX
2898  * descriptor (containing the address).  Whereas for the RX status
2899  * buffers the cpu only reads the last cacheline of the RX descriptor
2900  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
2901  */
2902 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
2903                             int src_idx, u32 dest_idx_unmasked)
2904 {
2905         struct tg3_rx_buffer_desc *desc;
2906         struct ring_info *map, *src_map;
2907         struct sk_buff *skb;
2908         dma_addr_t mapping;
2909         int skb_size, dest_idx;
2910
2911         src_map = NULL;
2912         switch (opaque_key) {
2913         case RXD_OPAQUE_RING_STD:
2914                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
2915                 desc = &tp->rx_std[dest_idx];
2916                 map = &tp->rx_std_buffers[dest_idx];
2917                 if (src_idx >= 0)
2918                         src_map = &tp->rx_std_buffers[src_idx];
2919                 skb_size = tp->rx_pkt_buf_sz;
2920                 break;
2921
2922         case RXD_OPAQUE_RING_JUMBO:
2923                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
2924                 desc = &tp->rx_jumbo[dest_idx];
2925                 map = &tp->rx_jumbo_buffers[dest_idx];
2926                 if (src_idx >= 0)
2927                         src_map = &tp->rx_jumbo_buffers[src_idx];
2928                 skb_size = RX_JUMBO_PKT_BUF_SZ;
2929                 break;
2930
2931         default:
2932                 return -EINVAL;
2933         };
2934
2935         /* Do not overwrite any of the map or rp information
2936          * until we are sure we can commit to a new buffer.
2937          *
2938          * Callers depend upon this behavior and assume that
2939          * we leave everything unchanged if we fail.
2940          */
2941         skb = dev_alloc_skb(skb_size);
2942         if (skb == NULL)
2943                 return -ENOMEM;
2944
2945         skb->dev = tp->dev;
2946         skb_reserve(skb, tp->rx_offset);
2947
2948         mapping = pci_map_single(tp->pdev, skb->data,
2949                                  skb_size - tp->rx_offset,
2950                                  PCI_DMA_FROMDEVICE);
2951
2952         map->skb = skb;
2953         pci_unmap_addr_set(map, mapping, mapping);
2954
2955         if (src_map != NULL)
2956                 src_map->skb = NULL;
2957
2958         desc->addr_hi = ((u64)mapping >> 32);
2959         desc->addr_lo = ((u64)mapping & 0xffffffff);
2960
2961         return skb_size;
2962 }
2963
2964 /* We only need to move over in the address because the other
2965  * members of the RX descriptor are invariant.  See notes above
2966  * tg3_alloc_rx_skb for full details.
2967  */
2968 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
2969                            int src_idx, u32 dest_idx_unmasked)
2970 {
2971         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
2972         struct ring_info *src_map, *dest_map;
2973         int dest_idx;
2974
2975         switch (opaque_key) {
2976         case RXD_OPAQUE_RING_STD:
2977                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
2978                 dest_desc = &tp->rx_std[dest_idx];
2979                 dest_map = &tp->rx_std_buffers[dest_idx];
2980                 src_desc = &tp->rx_std[src_idx];
2981                 src_map = &tp->rx_std_buffers[src_idx];
2982                 break;
2983
2984         case RXD_OPAQUE_RING_JUMBO:
2985                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
2986                 dest_desc = &tp->rx_jumbo[dest_idx];
2987                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
2988                 src_desc = &tp->rx_jumbo[src_idx];
2989                 src_map = &tp->rx_jumbo_buffers[src_idx];
2990                 break;
2991
2992         default:
2993                 return;
2994         };
2995
2996         dest_map->skb = src_map->skb;
2997         pci_unmap_addr_set(dest_map, mapping,
2998                            pci_unmap_addr(src_map, mapping));
2999         dest_desc->addr_hi = src_desc->addr_hi;
3000         dest_desc->addr_lo = src_desc->addr_lo;
3001
3002         src_map->skb = NULL;
3003 }
3004
3005 #if TG3_VLAN_TAG_USED
3006 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3007 {
3008         return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3009 }
3010 #endif
3011
3012 /* The RX ring scheme is composed of multiple rings which post fresh
3013  * buffers to the chip, and one special ring the chip uses to report
3014  * status back to the host.
3015  *
3016  * The special ring reports the status of received packets to the
3017  * host.  The chip does not write into the original descriptor the
3018  * RX buffer was obtained from.  The chip simply takes the original
3019  * descriptor as provided by the host, updates the status and length
3020  * field, then writes this into the next status ring entry.
3021  *
3022  * Each ring the host uses to post buffers to the chip is described
3023  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
3024  * it is first placed into the on-chip ram.  When the packet's length
3025  * is known, it walks down the TG3_BDINFO entries to select the ring.
3026  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3027  * which is within the range of the new packet's length is chosen.
3028  *
3029  * The "separate ring for rx status" scheme may sound queer, but it makes
3030  * sense from a cache coherency perspective.  If only the host writes
3031  * to the buffer post rings, and only the chip writes to the rx status
3032  * rings, then cache lines never move beyond shared-modified state.
3033  * If both the host and chip were to write into the same ring, cache line
3034  * eviction could occur since both entities want it in an exclusive state.
3035  */
3036 static int tg3_rx(struct tg3 *tp, int budget)
3037 {
3038         u32 work_mask;
3039         u32 sw_idx = tp->rx_rcb_ptr;
3040         u16 hw_idx;
3041         int received;
3042
3043         hw_idx = tp->hw_status->idx[0].rx_producer;
3044         /*
3045          * We need to order the read of hw_idx and the read of
3046          * the opaque cookie.
3047          */
3048         rmb();
3049         work_mask = 0;
3050         received = 0;
3051         while (sw_idx != hw_idx && budget > 0) {
3052                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3053                 unsigned int len;
3054                 struct sk_buff *skb;
3055                 dma_addr_t dma_addr;
3056                 u32 opaque_key, desc_idx, *post_ptr;
3057
3058                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3059                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3060                 if (opaque_key == RXD_OPAQUE_RING_STD) {
3061                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3062                                                   mapping);
3063                         skb = tp->rx_std_buffers[desc_idx].skb;
3064                         post_ptr = &tp->rx_std_ptr;
3065                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3066                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3067                                                   mapping);
3068                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
3069                         post_ptr = &tp->rx_jumbo_ptr;
3070                 }
3071                 else {
3072                         goto next_pkt_nopost;
3073                 }
3074
3075                 work_mask |= opaque_key;
3076
3077                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3078                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3079                 drop_it:
3080                         tg3_recycle_rx(tp, opaque_key,
3081                                        desc_idx, *post_ptr);
3082                 drop_it_no_recycle:
3083                         /* Other statistics kept track of by card. */
3084                         tp->net_stats.rx_dropped++;
3085                         goto next_pkt;
3086                 }
3087
3088                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3089
3090                 if (len > RX_COPY_THRESHOLD 
3091                         && tp->rx_offset == 2
3092                         /* rx_offset != 2 iff this is a 5701 card running
3093                          * in PCI-X mode [see tg3_get_invariants()] */
3094                 ) {
3095                         int skb_size;
3096
3097                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3098                                                     desc_idx, *post_ptr);
3099                         if (skb_size < 0)
3100                                 goto drop_it;
3101
3102                         pci_unmap_single(tp->pdev, dma_addr,
3103                                          skb_size - tp->rx_offset,
3104                                          PCI_DMA_FROMDEVICE);
3105
3106                         skb_put(skb, len);
3107                 } else {
3108                         struct sk_buff *copy_skb;
3109
3110                         tg3_recycle_rx(tp, opaque_key,
3111                                        desc_idx, *post_ptr);
3112
3113                         copy_skb = dev_alloc_skb(len + 2);
3114                         if (copy_skb == NULL)
3115                                 goto drop_it_no_recycle;
3116
3117                         copy_skb->dev = tp->dev;
3118                         skb_reserve(copy_skb, 2);
3119                         skb_put(copy_skb, len);
3120                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3121                         memcpy(copy_skb->data, skb->data, len);
3122                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3123
3124                         /* We'll reuse the original ring buffer. */
3125                         skb = copy_skb;
3126                 }
3127
3128                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3129                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3130                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3131                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
3132                         skb->ip_summed = CHECKSUM_UNNECESSARY;
3133                 else
3134                         skb->ip_summed = CHECKSUM_NONE;
3135
3136                 skb->protocol = eth_type_trans(skb, tp->dev);
3137 #if TG3_VLAN_TAG_USED
3138                 if (tp->vlgrp != NULL &&
3139                     desc->type_flags & RXD_FLAG_VLAN) {
3140                         tg3_vlan_rx(tp, skb,
3141                        &nb