drivers/net/sfc/falcon.c

   1 /****************************************************************************
   2  * Driver for Solarflare Solarstorm network controllers and boards
   3  * Copyright 2005-2006 Fen Systems Ltd.
   4  * Copyright 2006-2008 Solarflare Communications Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation, incorporated herein by reference.
   9  */
  10
  11 #include <linux/bitops.h>
  12 #include <linux/delay.h>
  13 #include <linux/pci.h>
  14 #include <linux/module.h>
  15 #include <linux/seq_file.h>
  16 #include <linux/i2c.h>
  17 #include <linux/i2c-algo-bit.h>
  18 #include <linux/mii.h>
  19 #include "net_driver.h"
  20 #include "bitfield.h"
  21 #include "efx.h"
  22 #include "mac.h"
  23 #include "spi.h"
  24 #include "falcon.h"
  25 #include "falcon_hwdefs.h"
  26 #include "falcon_io.h"
  27 #include "mdio_10g.h"
  28 #include "phy.h"
  29 #include "boards.h"
  30 #include "workarounds.h"
  31
  32 /* Falcon hardware control.
  33  * Falcon is the internal codename for the SFC4000 controller that is
  34  * present in SFE400X evaluation boards
  35  */
  36
  37 /**
  38  * struct falcon_nic_data - Falcon NIC state
  39  * @next_buffer_table: First available buffer table id
  40  * @pci_dev2: The secondary PCI device if present
  41  * @i2c_data: Operations and state for I2C bit-bashing algorithm
  42  */
  43 struct falcon_nic_data {
  44         unsigned next_buffer_table;
  45         struct pci_dev *pci_dev2;
  46         struct i2c_algo_bit_data i2c_data;
  47 };
  48
  49 /**************************************************************************
  50  *
  51  * Configurable values
  52  *
  53  **************************************************************************
  54  */
  55
  56 static int disable_dma_stats;
  57
  58 /* This is set to 16 for a good reason.  In summary, if larger than
  59  * 16, the descriptor cache holds more than a default socket
  60  * buffer's worth of packets (for UDP we can only have at most one
  61  * socket buffer's worth outstanding).  This combined with the fact
  62  * that we only get 1 TX event per descriptor cache means the NIC
  63  * goes idle.
  64  */
  65 #define TX_DC_ENTRIES 16
  66 #define TX_DC_ENTRIES_ORDER 0
  67 #define TX_DC_BASE 0x130000
  68
  69 #define RX_DC_ENTRIES 64
  70 #define RX_DC_ENTRIES_ORDER 2
  71 #define RX_DC_BASE 0x100000
  72
  73 static const unsigned int
  74 /* "Large" EEPROM device: Atmel AT25640 or similar
  75  * 8 KB, 16-bit address, 32 B write block */
  76 large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN)
  77                      | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
  78                      | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)),
  79 /* Default flash device: Atmel AT25F1024
  80  * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */
  81 default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN)
  82                       | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
  83                       | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
  84                       | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
  85                       | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN));
  86
  87 /* RX FIFO XOFF watermark
  88  *
  89  * When the amount of the RX FIFO increases used increases past this
  90  * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
  91  * This also has an effect on RX/TX arbitration
  92  */
  93 static int rx_xoff_thresh_bytes = -1;
  94 module_param(rx_xoff_thresh_bytes, int, 0644);
  95 MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold");
  96
  97 /* RX FIFO XON watermark
  98  *
  99  * When the amount of the RX FIFO used decreases below this
 100  * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
 101  * This also has an effect on RX/TX arbitration
 102  */
 103 static int rx_xon_thresh_bytes = -1;
 104 module_param(rx_xon_thresh_bytes, int, 0644);
 105 MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
 106
 107 /* TX descriptor ring size - min 512 max 4k */
 108 #define FALCON_TXD_RING_ORDER TX_DESCQ_SIZE_1K
 109 #define FALCON_TXD_RING_SIZE 1024
 110 #define FALCON_TXD_RING_MASK (FALCON_TXD_RING_SIZE - 1)
 111
 112 /* RX descriptor ring size - min 512 max 4k */
 113 #define FALCON_RXD_RING_ORDER RX_DESCQ_SIZE_1K
 114 #define FALCON_RXD_RING_SIZE 1024
 115 #define FALCON_RXD_RING_MASK (FALCON_RXD_RING_SIZE - 1)
 116
 117 /* Event queue size - max 32k */
 118 #define FALCON_EVQ_ORDER EVQ_SIZE_4K
 119 #define FALCON_EVQ_SIZE 4096
 120 #define FALCON_EVQ_MASK (FALCON_EVQ_SIZE - 1)
 121
 122 /* Max number of internal errors. After this resets will not be performed */
 123 #define FALCON_MAX_INT_ERRORS 4
 124
 125 /* We poll for events every FLUSH_INTERVAL ms, and check FLUSH_POLL_COUNT times
 126  */
 127 #define FALCON_FLUSH_INTERVAL 10
 128 #define FALCON_FLUSH_POLL_COUNT 100
 129
 130 /**************************************************************************
 131  *
 132  * Falcon constants
 133  *
 134  **************************************************************************
 135  */
 136
 137 /* DMA address mask */
 138 #define FALCON_DMA_MASK DMA_BIT_MASK(46)
 139
 140 /* TX DMA length mask (13-bit) */
 141 #define FALCON_TX_DMA_MASK (4096 - 1)
 142
 143 /* Size and alignment of special buffers (4KB) */
 144 #define FALCON_BUF_SIZE 4096
 145
 146 /* Dummy SRAM size code */
 147 #define SRM_NB_BSZ_ONCHIP_ONLY (-1)
 148
 149 /* Be nice if these (or equiv.) were in linux/pci_regs.h, but they're not. */
 150 #define PCI_EXP_DEVCAP_PWR_VAL_LBN      18
 151 #define PCI_EXP_DEVCAP_PWR_SCL_LBN      26
 152 #define PCI_EXP_DEVCTL_PAYLOAD_LBN      5
 153 #define PCI_EXP_LNKSTA_LNK_WID          0x3f0
 154 #define PCI_EXP_LNKSTA_LNK_WID_LBN      4
 155
 156 #define FALCON_IS_DUAL_FUNC(efx)                \
 157         (falcon_rev(efx) < FALCON_REV_B0)
 158
 159 /**************************************************************************
 160  *
 161  * Falcon hardware access
 162  *
 163  **************************************************************************/
 164
 165 /* Read the current event from the event queue */
 166 static inline efx_qword_t *falcon_event(struct efx_channel *channel,
 167                                         unsigned int index)
 168 {
 169         return (((efx_qword_t *) (channel->eventq.addr)) + index);
 170 }
 171
 172 /* See if an event is present
 173  *
 174  * We check both the high and low dword of the event for all ones.  We
 175  * wrote all ones when we cleared the event, and no valid event can
 176  * have all ones in either its high or low dwords.  This approach is
 177  * robust against reordering.
 178  *
 179  * Note that using a single 64-bit comparison is incorrect; even
 180  * though the CPU read will be atomic, the DMA write may not be.
 181  */
 182 static inline int falcon_event_present(efx_qword_t *event)
 183 {
 184         return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
 185                   EFX_DWORD_IS_ALL_ONES(event->dword[1])));
 186 }
 187
 188 /**************************************************************************
 189  *
 190  * I2C bus - this is a bit-bashing interface using GPIO pins
 191  * Note that it uses the output enables to tristate the outputs
 192  * SDA is the data pin and SCL is the clock
 193  *
 194  **************************************************************************
 195  */
 196 static void falcon_setsda(void *data, int state)
 197 {
 198         struct efx_nic *efx = (struct efx_nic *)data;
 199         efx_oword_t reg;
 200
 201         falcon_read(efx, &reg, GPIO_CTL_REG_KER);
 202         EFX_SET_OWORD_FIELD(reg, GPIO3_OEN, !state);
 203         falcon_write(efx, &reg, GPIO_CTL_REG_KER);
 204 }
 205
 206 static void falcon_setscl(void *data, int state)
 207 {
 208         struct efx_nic *efx = (struct efx_nic *)data;
 209         efx_oword_t reg;
 210
 211         falcon_read(efx, &reg, GPIO_CTL_REG_KER);
 212         EFX_SET_OWORD_FIELD(reg, GPIO0_OEN, !state);
 213         falcon_write(efx, &reg, GPIO_CTL_REG_KER);
 214 }
 215
 216 static int falcon_getsda(void *data)
 217 {
 218         struct efx_nic *efx = (struct efx_nic *)data;
 219         efx_oword_t reg;
 220
 221         falcon_read(efx, &reg, GPIO_CTL_REG_KER);
 222         return EFX_OWORD_FIELD(reg, GPIO3_IN);
 223 }
 224
 225 static int falcon_getscl(void *data)
 226 {
 227         struct efx_nic *efx = (struct efx_nic *)data;
 228         efx_oword_t reg;
 229
 230         falcon_read(efx, &reg, GPIO_CTL_REG_KER);
 231         return EFX_OWORD_FIELD(reg, GPIO0_IN);
 232 }
 233
 234 static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
 235         .setsda         = falcon_setsda,
 236         .setscl         = falcon_setscl,
 237         .getsda         = falcon_getsda,
 238         .getscl         = falcon_getscl,
 239         .udelay         = 5,
 240         /* Wait up to 50 ms for slave to let us pull SCL high */
 241         .timeout        = DIV_ROUND_UP(HZ, 20),
 242 };
 243
 244 /**************************************************************************
 245  *
 246  * Falcon special buffer handling
 247  * Special buffers are used for event queues and the TX and RX
 248  * descriptor rings.
 249  *
 250  *************************************************************************/
 251
 252 /*
 253  * Initialise a Falcon special buffer
 254  *
 255  * This will define a buffer (previously allocated via
 256  * falcon_alloc_special_buffer()) in Falcon's buffer table, allowing
 257  * it to be used for event queues, descriptor rings etc.
 258  */
 259 static void
 260 falcon_init_special_buffer(struct efx_nic *efx,
 261                            struct efx_special_buffer *buffer)
 262 {
 263         efx_qword_t buf_desc;
 264         int index;
 265         dma_addr_t dma_addr;
 266         int i;
 267
 268         EFX_BUG_ON_PARANOID(!buffer->addr);
 269
 270         /* Write buffer descriptors to NIC */
 271         for (i = 0; i < buffer->entries; i++) {
 272                 index = buffer->index + i;
 273                 dma_addr = buffer->dma_addr + (i * 4096);
 274                 EFX_LOG(efx, "mapping special buffer %d at %llx\n",
 275                         index, (unsigned long long)dma_addr);
 276                 EFX_POPULATE_QWORD_4(buf_desc,
 277                                      IP_DAT_BUF_SIZE, IP_DAT_BUF_SIZE_4K,
 278                                      BUF_ADR_REGION, 0,
 279                                      BUF_ADR_FBUF, (dma_addr >> 12),
 280                                      BUF_OWNER_ID_FBUF, 0);
 281                 falcon_write_sram(efx, &buf_desc, index);
 282         }
 283 }
 284
 285 /* Unmaps a buffer from Falcon and clears the buffer table entries */
 286 static void
 287 falcon_fini_special_buffer(struct efx_nic *efx,
 288                            struct efx_special_buffer *buffer)
 289 {
 290         efx_oword_t buf_tbl_upd;
 291         unsigned int start = buffer->index;
 292         unsigned int end = (buffer->index + buffer->entries - 1);
 293
 294         if (!buffer->entries)
 295                 return;
 296
 297         EFX_LOG(efx, "unmapping special buffers %d-%d\n",
 298                 buffer->index, buffer->index + buffer->entries - 1);
 299
 300         EFX_POPULATE_OWORD_4(buf_tbl_upd,
 301                              BUF_UPD_CMD, 0,
 302                              BUF_CLR_CMD, 1,
 303                              BUF_CLR_END_ID, end,
 304                              BUF_CLR_START_ID, start);
 305         falcon_write(efx, &buf_tbl_upd, BUF_TBL_UPD_REG_KER);
 306 }
 307
 308 /*
 309  * Allocate a new Falcon special buffer
 310  *
 311  * This allocates memory for a new buffer, clears it and allocates a
 312  * new buffer ID range.  It does not write into Falcon's buffer table.
 313  *
 314  * This call will allocate 4KB buffers, since Falcon can't use 8KB
 315  * buffers for event queues and descriptor rings.
 316  */
 317 static int falcon_alloc_special_buffer(struct efx_nic *efx,
 318                                        struct efx_special_buffer *buffer,
 319                                        unsigned int len)
 320 {
 321         struct falcon_nic_data *nic_data = efx->nic_data;
 322
 323         len = ALIGN(len, FALCON_BUF_SIZE);
 324
 325         buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
 326                                             &buffer->dma_addr);
 327         if (!buffer->addr)
 328                 return -ENOMEM;
 329         buffer->len = len;
 330         buffer->entries = len / FALCON_BUF_SIZE;
 331         BUG_ON(buffer->dma_addr & (FALCON_BUF_SIZE - 1));
 332
 333         /* All zeros is a potentially valid event so memset to 0xff */
 334         memset(buffer->addr, 0xff, len);
 335
 336         /* Select new buffer ID */
 337         buffer->index = nic_data->next_buffer_table;
 338         nic_data->next_buffer_table += buffer->entries;
 339
 340         EFX_LOG(efx, "allocating special buffers %d-%d at %llx+%x "
 341                 "(virt %p phys %lx)\n", buffer->index,
 342                 buffer->index + buffer->entries - 1,
 343                 (unsigned long long)buffer->dma_addr, len,
 344                 buffer->addr, virt_to_phys(buffer->addr));
 345
 346         return 0;
 347 }
 348
 349 static void falcon_free_special_buffer(struct efx_nic *efx,
 350                                        struct efx_special_buffer *buffer)
 351 {
 352         if (!buffer->addr)
 353                 return;
 354
 355         EFX_LOG(efx, "deallocating special buffers %d-%d at %llx+%x "
 356                 "(virt %p phys %lx)\n", buffer->index,
 357                 buffer->index + buffer->entries - 1,
 358                 (unsigned long long)buffer->dma_addr, buffer->len,
 359                 buffer->addr, virt_to_phys(buffer->addr));
 360
 361         pci_free_consistent(efx->pci_dev, buffer->len, buffer->addr,
 362                             buffer->dma_addr);
 363         buffer->addr = NULL;
 364         buffer->entries = 0;
 365 }
 366
 367 /**************************************************************************
 368  *
 369  * Falcon generic buffer handling
 370  * These buffers are used for interrupt status and MAC stats
 371  *
 372  **************************************************************************/
 373
 374 static int falcon_alloc_buffer(struct efx_nic *efx,
 375                                struct efx_buffer *buffer, unsigned int len)
 376 {
 377         buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
 378                                             &buffer->dma_addr);
 379         if (!buffer->addr)
 380                 return -ENOMEM;
 381         buffer->len = len;
 382         memset(buffer->addr, 0, len);
 383         return 0;
 384 }
 385
 386 static void falcon_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
 387 {
 388         if (buffer->addr) {
 389                 pci_free_consistent(efx->pci_dev, buffer->len,
 390                                     buffer->addr, buffer->dma_addr);
 391                 buffer->addr = NULL;
 392         }
 393 }
 394
 395 /**************************************************************************
 396  *
 397  * Falcon TX path
 398  *
 399  **************************************************************************/
 400
 401 /* Returns a pointer to the specified transmit descriptor in the TX
 402  * descriptor queue belonging to the specified channel.
 403  */
 404 static inline efx_qword_t *falcon_tx_desc(struct efx_tx_queue *tx_queue,
 405                                                unsigned int index)
 406 {
 407         return (((efx_qword_t *) (tx_queue->txd.addr)) + index);
 408 }
 409
 410 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
 411 static inline void falcon_notify_tx_desc(struct efx_tx_queue *tx_queue)
 412 {
 413         unsigned write_ptr;
 414         efx_dword_t reg;
 415
 416         write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
 417         EFX_POPULATE_DWORD_1(reg, TX_DESC_WPTR_DWORD, write_ptr);
 418         falcon_writel_page(tx_queue->efx, &reg,
 419                            TX_DESC_UPD_REG_KER_DWORD, tx_queue->queue);
 420 }
 421
 422
 423 /* For each entry inserted into the software descriptor ring, create a
 424  * descriptor in the hardware TX descriptor ring (in host memory), and
 425  * write a doorbell.
 426  */
 427 void falcon_push_buffers(struct efx_tx_queue *tx_queue)
 428 {
 429
 430         struct efx_tx_buffer *buffer;
 431         efx_qword_t *txd;
 432         unsigned write_ptr;
 433
 434         BUG_ON(tx_queue->write_count == tx_queue->insert_count);
 435
 436         do {
 437                 write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
 438                 buffer = &tx_queue->buffer[write_ptr];
 439                 txd = falcon_tx_desc(tx_queue, write_ptr);
 440                 ++tx_queue->write_count;
 441
 442                 /* Create TX descriptor ring entry */
 443                 EFX_POPULATE_QWORD_5(*txd,
 444                                      TX_KER_PORT, 0,
 445                                      TX_KER_CONT, buffer->continuation,
 446                                      TX_KER_BYTE_CNT, buffer->len,
 447                                      TX_KER_BUF_REGION, 0,
 448                                      TX_KER_BUF_ADR, buffer->dma_addr);
 449         } while (tx_queue->write_count != tx_queue->insert_count);
 450
 451         wmb(); /* Ensure descriptors are written before they are fetched */
 452         falcon_notify_tx_desc(tx_queue);
 453 }
 454
 455 /* Allocate hardware resources for a TX queue */
 456 int falcon_probe_tx(struct efx_tx_queue *tx_queue)
 457 {
 458         struct efx_nic *efx = tx_queue->efx;
 459         return falcon_alloc_special_buffer(efx, &tx_queue->txd,
 460                                            FALCON_TXD_RING_SIZE *
 461                                            sizeof(efx_qword_t));
 462 }
 463
 464 void falcon_init_tx(struct efx_tx_queue *tx_queue)
 465 {
 466         efx_oword_t tx_desc_ptr;
 467         struct efx_nic *efx = tx_queue->efx;
 468
 469         tx_queue->flushed = false;
 470
 471         /* Pin TX descriptor ring */
 472         falcon_init_special_buffer(efx, &tx_queue->txd);
 473
 474         /* Push TX descriptor ring to card */
 475         EFX_POPULATE_OWORD_10(tx_desc_ptr,
 476                               TX_DESCQ_EN, 1,
 477                               TX_ISCSI_DDIG_EN, 0,
 478                               TX_ISCSI_HDIG_EN, 0,
 479                               TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
 480                               TX_DESCQ_EVQ_ID, tx_queue->channel->channel,
 481                               TX_DESCQ_OWNER_ID, 0,
 482                               TX_DESCQ_LABEL, tx_queue->queue,
 483                               TX_DESCQ_SIZE, FALCON_TXD_RING_ORDER,
 484                               TX_DESCQ_TYPE, 0,
 485                               TX_NON_IP_DROP_DIS_B0, 1);
 486
 487         if (falcon_rev(efx) >= FALCON_REV_B0) {
 488                 int csum = tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM;
 489                 EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_IP_CHKSM_DIS_B0, !csum);
 490                 EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_TCP_CHKSM_DIS_B0, !csum);
 491         }
 492
 493         falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
 494                            tx_queue->queue);
 495
 496         if (falcon_rev(efx) < FALCON_REV_B0) {
 497                 efx_oword_t reg;
 498
 499                 /* Only 128 bits in this register */
 500                 BUILD_BUG_ON(EFX_TX_QUEUE_COUNT >= 128);
 501
 502                 falcon_read(efx, &reg, TX_CHKSM_CFG_REG_KER_A1);
 503                 if (tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM)
 504                         clear_bit_le(tx_queue->queue, (void *)&reg);
 505                 else
 506                         set_bit_le(tx_queue->queue, (void *)&reg);
 507                 falcon_write(efx, &reg, TX_CHKSM_CFG_REG_KER_A1);
 508         }
 509 }
 510
 511 static void falcon_flush_tx_queue(struct efx_tx_queue *tx_queue)
 512 {
 513         struct efx_nic *efx = tx_queue->efx;
 514         efx_oword_t tx_flush_descq;
 515
 516         /* Post a flush command */
 517         EFX_POPULATE_OWORD_2(tx_flush_descq,
 518                              TX_FLUSH_DESCQ_CMD, 1,
 519                              TX_FLUSH_DESCQ, tx_queue->queue);
 520         falcon_write(efx, &tx_flush_descq, TX_FLUSH_DESCQ_REG_KER);
 521 }
 522
 523 void falcon_fini_tx(struct efx_tx_queue *tx_queue)
 524 {
 525         struct efx_nic *efx = tx_queue->efx;
 526         efx_oword_t tx_desc_ptr;
 527
 528         /* The queue should have been flushed */
 529         WARN_ON(!tx_queue->flushed);
 530
 531         /* Remove TX descriptor ring from card */
 532         EFX_ZERO_OWORD(tx_desc_ptr);
 533         falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
 534                            tx_queue->queue);
 535
 536         /* Unpin TX descriptor ring */
 537         falcon_fini_special_buffer(efx, &tx_queue->txd);
 538 }
 539
 540 /* Free buffers backing TX queue */
 541 void falcon_remove_tx(struct efx_tx_queue *tx_queue)
 542 {
 543         falcon_free_special_buffer(tx_queue->efx, &tx_queue->txd);
 544 }
 545
 546 /**************************************************************************
 547  *
 548  * Falcon RX path
 549  *
 550  **************************************************************************/
 551
 552 /* Returns a pointer to the specified descriptor in the RX descriptor queue */
 553 static inline efx_qword_t *falcon_rx_desc(struct efx_rx_queue *rx_queue,
 554                                                unsigned int index)
 555 {
 556         return (((efx_qword_t *) (rx_queue->rxd.addr)) + index);
 557 }
 558
 559 /* This creates an entry in the RX descriptor queue */
 560 static inline void falcon_build_rx_desc(struct efx_rx_queue *rx_queue,
 561                                         unsigned index)
 562 {
 563         struct efx_rx_buffer *rx_buf;
 564         efx_qword_t *rxd;
 565
 566         rxd = falcon_rx_desc(rx_queue, index);
 567         rx_buf = efx_rx_buffer(rx_queue, index);
 568         EFX_POPULATE_QWORD_3(*rxd,
 569                              RX_KER_BUF_SIZE,
 570                              rx_buf->len -
 571                              rx_queue->efx->type->rx_buffer_padding,
 572                              RX_KER_BUF_REGION, 0,
 573                              RX_KER_BUF_ADR, rx_buf->dma_addr);
 574 }
 575
 576 /* This writes to the RX_DESC_WPTR register for the specified receive
 577  * descriptor ring.
 578  */
 579 void falcon_notify_rx_desc(struct efx_rx_queue *rx_queue)
 580 {
 581         efx_dword_t reg;
 582         unsigned write_ptr;
 583
 584         while (rx_queue->notified_count != rx_queue->added_count) {
 585                 falcon_build_rx_desc(rx_queue,
 586                                      rx_queue->notified_count &
 587                                      FALCON_RXD_RING_MASK);
 588                 ++rx_queue->notified_count;
 589         }
 590
 591         wmb();
 592         write_ptr = rx_queue->added_count & FALCON_RXD_RING_MASK;
 593         EFX_POPULATE_DWORD_1(reg, RX_DESC_WPTR_DWORD, write_ptr);
 594         falcon_writel_page(rx_queue->efx, &reg,
 595                            RX_DESC_UPD_REG_KER_DWORD, rx_queue->queue);
 596 }
 597
 598 int falcon_probe_rx(struct efx_rx_queue *rx_queue)
 599 {
 600         struct efx_nic *efx = rx_queue->efx;
 601         return falcon_alloc_special_buffer(efx, &rx_queue->rxd,
 602                                            FALCON_RXD_RING_SIZE *
 603                                            sizeof(efx_qword_t));
 604 }
 605
 606 void falcon_init_rx(struct efx_rx_queue *rx_queue)
 607 {
 608         efx_oword_t rx_desc_ptr;
 609         struct efx_nic *efx = rx_queue->efx;
 610         bool is_b0 = falcon_rev(efx) >= FALCON_REV_B0;
 611         bool iscsi_digest_en = is_b0;
 612
 613         EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n",
 614                 rx_queue->queue, rx_queue->rxd.index,
 615                 rx_queue->rxd.index + rx_queue->rxd.entries - 1);
 616
 617         rx_queue->flushed = false;
 618
 619         /* Pin RX descriptor ring */
 620         falcon_init_special_buffer(efx, &rx_queue->rxd);
 621
 622         /* Push RX descriptor ring to card */
 623         EFX_POPULATE_OWORD_10(rx_desc_ptr,
 624                               RX_ISCSI_DDIG_EN, iscsi_digest_en,
 625                               RX_ISCSI_HDIG_EN, iscsi_digest_en,
 626                               RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
 627                               RX_DESCQ_EVQ_ID, rx_queue->channel->channel,
 628                               RX_DESCQ_OWNER_ID, 0,
 629                               RX_DESCQ_LABEL, rx_queue->queue,
 630                               RX_DESCQ_SIZE, FALCON_RXD_RING_ORDER,
 631                               RX_DESCQ_TYPE, 0 /* kernel queue */ ,
 632                               /* For >=B0 this is scatter so disable */
 633                               RX_DESCQ_JUMBO, !is_b0,
 634                               RX_DESCQ_EN, 1);
 635         falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
 636                            rx_queue->queue);
 637 }
 638
 639 static void falcon_flush_rx_queue(struct efx_rx_queue *rx_queue)
 640 {
 641         struct efx_nic *efx = rx_queue->efx;
 642         efx_oword_t rx_flush_descq;
 643
 644         /* Post a flush command */
 645         EFX_POPULATE_OWORD_2(rx_flush_descq,
 646                              RX_FLUSH_DESCQ_CMD, 1,
 647                              RX_FLUSH_DESCQ, rx_queue->queue);
 648         falcon_write(efx, &rx_flush_descq, RX_FLUSH_DESCQ_REG_KER);
 649 }
 650
 651 void falcon_fini_rx(struct efx_rx_queue *rx_queue)
 652 {
 653         efx_oword_t rx_desc_ptr;
 654         struct efx_nic *efx = rx_queue->efx;
 655
 656         /* The queue should already have been flushed */
 657         WARN_ON(!rx_queue->flushed);
 658
 659         /* Remove RX descriptor ring from card */
 660         EFX_ZERO_OWORD(rx_desc_ptr);
 661         falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
 662                            rx_queue->queue);
 663
 664         /* Unpin RX descriptor ring */
 665         falcon_fini_special_buffer(efx, &rx_queue->rxd);
 666 }
 667
 668 /* Free buffers backing RX queue */
 669 void falcon_remove_rx(struct efx_rx_queue *rx_queue)
 670 {
 671         falcon_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
 672 }
 673
 674 /**************************************************************************
 675  *
 676  * Falcon event queue processing
 677  * Event queues are processed by per-channel tasklets.
 678  *
 679  **************************************************************************/
 680
 681 /* Update a channel's event queue's read pointer (RPTR) register
 682  *
 683  * This writes the EVQ_RPTR_REG register for the specified channel's
 684  * event queue.
 685  *
 686  * Note that EVQ_RPTR_REG contains the index of the "last read" event,
 687  * whereas channel->eventq_read_ptr contains the index of the "next to
 688  * read" event.
 689  */
 690 void falcon_eventq_read_ack(struct efx_channel *channel)
 691 {
 692         efx_dword_t reg;
 693         struct efx_nic *efx = channel->efx;
 694
 695         EFX_POPULATE_DWORD_1(reg, EVQ_RPTR_DWORD, channel->eventq_read_ptr);
 696         falcon_writel_table(efx, &reg, efx->type->evq_rptr_tbl_base,
 697                             channel->channel);
 698 }
 699
 700 /* Use HW to insert a SW defined event */
 701 void falcon_generate_event(struct efx_channel *channel, efx_qword_t *event)
 702 {
 703         efx_oword_t drv_ev_reg;
 704
 705         EFX_POPULATE_OWORD_2(drv_ev_reg,
 706                              DRV_EV_QID, channel->channel,
 707                              DRV_EV_DATA,
 708                              EFX_QWORD_FIELD64(*event, WHOLE_EVENT));
 709         falcon_write(channel->efx, &drv_ev_reg, DRV_EV_REG_KER);
 710 }
 711
 712 /* Handle a transmit completion event
 713  *
 714  * Falcon batches TX completion events; the message we receive is of
 715  * the form "complete all TX events up to this index".
 716  */
 717 static void falcon_handle_tx_event(struct efx_channel *channel,
 718                                    efx_qword_t *event)
 719 {
 720         unsigned int tx_ev_desc_ptr;
 721         unsigned int tx_ev_q_label;
 722         struct efx_tx_queue *tx_queue;
 723         struct efx_nic *efx = channel->efx;
 724
 725         if (likely(EFX_QWORD_FIELD(*event, TX_EV_COMP))) {
 726                 /* Transmit completion */
 727                 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, TX_EV_DESC_PTR);
 728                 tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL);
 729                 tx_queue = &efx->tx_queue[tx_ev_q_label];
 730                 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
 731         } else if (EFX_QWORD_FIELD(*event, TX_EV_WQ_FF_FULL)) {
 732                 /* Rewrite the FIFO write pointer */
 733                 tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL);
 734                 tx_queue = &efx->tx_queue[tx_ev_q_label];
 735
 736                 if (efx_dev_registered(efx))
 737                         netif_tx_lock(efx->net_dev);
 738                 falcon_notify_tx_desc(tx_queue);
 739                 if (efx_dev_registered(efx))
 740                         netif_tx_unlock(efx->net_dev);
 741         } else if (EFX_QWORD_FIELD(*event, TX_EV_PKT_ERR) &&
 742                    EFX_WORKAROUND_10727(efx)) {
 743                 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
 744         } else {
 745                 EFX_ERR(efx, "channel %d unexpected TX event "
 746                         EFX_QWORD_FMT"\n", channel->channel,
 747                         EFX_QWORD_VAL(*event));
 748         }
 749 }
 750
 751 /* Detect errors included in the rx_evt_pkt_ok bit. */
 752 static void falcon_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
 753                                     const efx_qword_t *event,
 754                                     bool *rx_ev_pkt_ok,
 755                                     bool *discard)
 756 {
 757         struct efx_nic *efx = rx_queue->efx;
 758         bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
 759         bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
 760         bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
 761         bool rx_ev_other_err, rx_ev_pause_frm;
 762         bool rx_ev_ip_frag_err, rx_ev_hdr_type, rx_ev_mcast_pkt;
 763         unsigned rx_ev_pkt_type;
 764
 765         rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE);
 766         rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT);
 767         rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, RX_EV_TOBE_DISC);
 768         rx_ev_pkt_type = EFX_QWORD_FIELD(*event, RX_EV_PKT_TYPE);
 769         rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
 770                                                  RX_EV_BUF_OWNER_ID_ERR);
 771         rx_ev_ip_frag_err = EFX_QWORD_FIELD(*event, RX_EV_IF_FRAG_ERR);
 772         rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
 773                                                   RX_EV_IP_HDR_CHKSUM_ERR);
 774         rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
 775                                                    RX_EV_TCP_UDP_CHKSUM_ERR);
 776         rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, RX_EV_ETH_CRC_ERR);
 777         rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, RX_EV_FRM_TRUNC);
 778         rx_ev_drib_nib = ((falcon_rev(efx) >= FALCON_REV_B0) ?
 779                           0 : EFX_QWORD_FIELD(*event, RX_EV_DRIB_NIB));
 780         rx_ev_pause_frm = EFX_QWORD_FIELD(*event, RX_EV_PAUSE_FRM_ERR);
 781
 782         /* Every error apart from tobe_disc and pause_frm */
 783         rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
 784                            rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
 785                            rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
 786
 787         /* Count errors that are not in MAC stats.  Ignore expected
 788          * checksum errors during self-test. */
 789         if (rx_ev_frm_trunc)
 790                 ++rx_queue->channel->n_rx_frm_trunc;
 791         else if (rx_ev_tobe_disc)
 792                 ++rx_queue->channel->n_rx_tobe_disc;
 793         else if (!efx->loopback_selftest) {
 794                 if (rx_ev_ip_hdr_chksum_err)
 795                         ++rx_queue->channel->n_rx_ip_hdr_chksum_err;
 796                 else if (rx_ev_tcp_udp_chksum_err)
 797                         ++rx_queue->channel->n_rx_tcp_udp_chksum_err;
 798         }
 799         if (rx_ev_ip_frag_err)
 800                 ++rx_queue->channel->n_rx_ip_frag_err;
 801
 802         /* The frame must be discarded if any of these are true. */
 803         *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
 804                     rx_ev_tobe_disc | rx_ev_pause_frm);
 805
 806         /* TOBE_DISC is expected on unicast mismatches; don't print out an
 807          * error message.  FRM_TRUNC indicates RXDP dropped the packet due
 808          * to a FIFO overflow.
 809          */
 810 #ifdef EFX_ENABLE_DEBUG
 811         if (rx_ev_other_err) {
 812                 EFX_INFO_RL(efx, " RX queue %d unexpected RX event "
 813                             EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n",
 814                             rx_queue->queue, EFX_QWORD_VAL(*event),
 815                             rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
 816                             rx_ev_ip_hdr_chksum_err ?
 817                             " [IP_HDR_CHKSUM_ERR]" : "",
 818                             rx_ev_tcp_udp_chksum_err ?
 819                             " [TCP_UDP_CHKSUM_ERR]" : "",
 820                             rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
 821                             rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
 822                             rx_ev_drib_nib ? " [DRIB_NIB]" : "",
 823                             rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
 824                             rx_ev_pause_frm ? " [PAUSE]" : "");
 825         }
 826 #endif
 827 }
 828
 829 /* Handle receive events that are not in-order. */
 830 static void falcon_handle_rx_bad_index(struct efx_rx_queue *rx_queue,
 831                                        unsigned index)
 832 {
 833         struct efx_nic *efx = rx_queue->efx;
 834         unsigned expected, dropped;
 835
 836         expected = rx_queue->removed_count & FALCON_RXD_RING_MASK;
 837         dropped = ((index + FALCON_RXD_RING_SIZE - expected) &
 838                    FALCON_RXD_RING_MASK);
 839         EFX_INFO(efx, "dropped %d events (index=%d expected=%d)\n",
 840                 dropped, index, expected);
 841
 842         efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
 843                            RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
 844 }
 845
 846 /* Handle a packet received event
 847  *
 848  * Falcon silicon gives a "discard" flag if it's a unicast packet with the
 849  * wrong destination address
 850  * Also "is multicast" and "matches multicast filter" flags can be used to
 851  * discard non-matching multicast packets.
 852  */
 853 static void falcon_handle_rx_event(struct efx_channel *channel,
 854                                    const efx_qword_t *event)
 855 {
 856         unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt;
 857         unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt;
 858         unsigned expected_ptr;
 859         bool rx_ev_pkt_ok, discard = false, checksummed;
 860         struct efx_rx_queue *rx_queue;
 861         struct efx_nic *efx = channel->efx;
 862
 863         /* Basic packet information */
 864         rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, RX_EV_BYTE_CNT);
 865         rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, RX_EV_PKT_OK);
 866         rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE);
 867         WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_JUMBO_CONT));
 868         WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_SOP) != 1);
 869         WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_Q_LABEL) != channel->channel);
 870
 871         rx_queue = &efx->rx_queue[channel->channel];
 872
 873         rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, RX_EV_DESC_PTR);
 874         expected_ptr = rx_queue->removed_count & FALCON_RXD_RING_MASK;
 875         if (unlikely(rx_ev_desc_ptr != expected_ptr))
 876                 falcon_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr);
 877
 878         if (likely(rx_ev_pkt_ok)) {
 879                 /* If packet is marked as OK and packet type is TCP/IPv4 or
 880                  * UDP/IPv4, then we can rely on the hardware checksum.
 881                  */
 882                 checksummed = RX_EV_HDR_TYPE_HAS_CHECKSUMS(rx_ev_hdr_type);
 883         } else {
 884                 falcon_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok,
 885                                         &discard);
 886                 checksummed = false;
 887         }
 888
 889         /* Detect multicast packets that didn't match the filter */
 890         rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT);
 891         if (rx_ev_mcast_pkt) {
 892                 unsigned int rx_ev_mcast_hash_match =
 893                         EFX_QWORD_FIELD(*event, RX_EV_MCAST_HASH_MATCH);
 894
 895                 if (unlikely(!rx_ev_mcast_hash_match))
 896                         discard = true;
 897         }
 898
 899         /* Handle received packet */
 900         efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt,
 901                       checksummed, discard);
 902 }
 903
 904 /* Global events are basically PHY events */
 905 static void falcon_handle_global_event(struct efx_channel *channel,
 906                                        efx_qword_t *event)
 907 {
 908         struct efx_nic *efx = channel->efx;
 909         bool handled = false;
 910
 911         if (EFX_QWORD_FIELD(*event, G_PHY0_INTR) ||
 912             EFX_QWORD_FIELD(*event, G_PHY1_INTR) ||
 913             EFX_QWORD_FIELD(*event, XG_PHY_INTR) ||
 914             EFX_QWORD_FIELD(*event, XFP_PHY_INTR)) {
 915                 efx->phy_op->clear_interrupt(efx);
 916                 queue_work(efx->workqueue, &efx->phy_work);
 917                 handled = true;
 918         }
 919
 920         if ((falcon_rev(efx) >= FALCON_REV_B0) &&
 921             EFX_QWORD_FIELD(*event, XG_MNT_INTR_B0)) {
 922                 queue_work(efx->workqueue, &efx->mac_work);
 923                 handled = true;
 924         }
 925
 926         if (EFX_QWORD_FIELD_VER(efx, *event, RX_RECOVERY)) {
 927                 EFX_ERR(efx, "channel %d seen global RX_RESET "
 928                         "event. Resetting.\n", channel->channel);
 929
 930                 atomic_inc(&efx->rx_reset);
 931                 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
 932                                    RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
 933                 handled = true;
 934         }
 935
 936         if (!handled)
 937                 EFX_ERR(efx, "channel %d unknown global event "
 938                         EFX_QWORD_FMT "\n", channel->channel,
 939                         EFX_QWORD_VAL(*event));
 940 }
 941
 942 static void falcon_handle_driver_event(struct efx_channel *channel,
 943                                        efx_qword_t *event)
 944 {
 945         struct efx_nic *efx = channel->efx;
 946         unsigned int ev_sub_code;
 947         unsigned int ev_sub_data;
 948
 949         ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
 950         ev_sub_data = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_DATA);
 951
 952         switch (ev_sub_code) {
 953         case TX_DESCQ_FLS_DONE_EV_DECODE:
 954                 EFX_TRACE(efx, "channel %d TXQ %d flushed\n",
 955                           channel->channel, ev_sub_data);
 956                 break;
 957         case RX_DESCQ_FLS_DONE_EV_DECODE:
 958                 EFX_TRACE(efx, "channel %d RXQ %d flushed\n",
 959                           channel->channel, ev_sub_data);
 960                 break;
 961         case EVQ_INIT_DONE_EV_DECODE:
 962                 EFX_LOG(efx, "channel %d EVQ %d initialised\n",
 963                         channel->channel, ev_sub_data);
 964                 break;
 965         case SRM_UPD_DONE_EV_DECODE:
 966                 EFX_TRACE(efx, "channel %d SRAM update done\n",
 967                           channel->channel);
 968                 break;
 969         case WAKE_UP_EV_DECODE:
 970                 EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n",
 971                           channel->channel, ev_sub_data);
 972                 break;
 973         case TIMER_EV_DECODE:
 974                 EFX_TRACE(efx, "channel %d RX queue %d timer expired\n",
 975                           channel->channel, ev_sub_data);
 976                 break;
 977         case RX_RECOVERY_EV_DECODE:
 978                 EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. "
 979                         "Resetting.\n", channel->channel);
 980                 atomic_inc(&efx->rx_reset);
 981                 efx_schedule_reset(efx,
 982                                    EFX_WORKAROUND_6555(efx) ?
 983                                    RESET_TYPE_RX_RECOVERY :
 984                                    RESET_TYPE_DISABLE);
 985                 break;
 986         case RX_DSC_ERROR_EV_DECODE:
 987                 EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error."
 988                         " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
 989                 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH);
 990                 break;
 991         case TX_DSC_ERROR_EV_DECODE:
 992                 EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error."
 993                         " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
 994                 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
 995                 break;
 996         default:
 997                 EFX_TRACE(efx, "channel %d unknown driver event code %d "
 998                           "data %04x\n", channel->channel, ev_sub_code,
 999                           ev_sub_data);
1000                 break;
1001         }
1002 }
1003
1004 int falcon_process_eventq(struct efx_channel *channel, int rx_quota)
1005 {
1006         unsigned int read_ptr;
1007         efx_qword_t event, *p_event;
1008         int ev_code;
1009         int rx_packets = 0;
1010
1011         read_ptr = channel->eventq_read_ptr;
1012
1013         do {
1014                 p_event = falcon_event(channel, read_ptr);
1015                 event = *p_event;
1016
1017                 if (!falcon_event_present(&event))
1018                         /* End of events */
1019                         break;
1020
1021                 EFX_TRACE(channel->efx, "channel %d event is "EFX_QWORD_FMT"\n",
1022                           channel->channel, EFX_QWORD_VAL(event));
1023
1024                 /* Clear this event by marking it all ones */
1025                 EFX_SET_QWORD(*p_event);
1026
1027                 ev_code = EFX_QWORD_FIELD(event, EV_CODE);
1028
1029                 switch (ev_code) {
1030                 case RX_IP_EV_DECODE:
1031                         falcon_handle_rx_event(channel, &event);
1032                         ++rx_packets;
1033                         break;
1034                 case TX_IP_EV_DECODE:
1035                         falcon_handle_tx_event(channel, &event);
1036                         break;
1037                 case DRV_GEN_EV_DECODE:
1038                         channel->eventq_magic
1039                                 = EFX_QWORD_FIELD(event, EVQ_MAGIC);
1040                         EFX_LOG(channel->efx, "channel %d received generated "
1041                                 "event "EFX_QWORD_FMT"\n", channel->channel,
1042                                 EFX_QWORD_VAL(event));
1043                         break;
1044                 case GLOBAL_EV_DECODE:
1045                         falcon_handle_global_event(channel, &event);
1046                         break;
1047                 case DRIVER_EV_DECODE:
1048                         falcon_handle_driver_event(channel, &event);
1049                         break;
1050                 default:
1051                         EFX_ERR(channel->efx, "channel %d unknown event type %d"
1052                                 " (data " EFX_QWORD_FMT ")\n", channel->channel,
1053                                 ev_code, EFX_QWORD_VAL(event));
1054                 }
1055
1056                 /* Increment read pointer */
1057                 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
1058
1059         } while (rx_packets < rx_quota);
1060
1061         channel->eventq_read_ptr = read_ptr;
1062         return rx_packets;
1063 }
1064
1065 void falcon_set_int_moderation(struct efx_channel *channel)
1066 {
1067         efx_dword_t timer_cmd;
1068         struct efx_nic *efx = channel->efx;
1069
1070         /* Set timer register */
1071         if (channel->irq_moderation) {
1072                 /* Round to resolution supported by hardware.  The value we
1073                  * program is based at 0.  So actual interrupt moderation
1074                  * achieved is ((x + 1) * res).
1075                  */
1076                 unsigned int res = 5;
1077                 channel->irq_moderation -= (channel->irq_moderation % res);
1078                 if (channel->irq_moderation < res)
1079                         channel->irq_moderation = res;
1080                 EFX_POPULATE_DWORD_2(timer_cmd,
1081                                      TIMER_MODE, TIMER_MODE_INT_HLDOFF,
1082                                      TIMER_VAL,
1083                                      (channel->irq_moderation / res) - 1);
1084         } else {
1085                 EFX_POPULATE_DWORD_2(timer_cmd,
1086                                      TIMER_MODE, TIMER_MODE_DIS,
1087                                      TIMER_VAL, 0);
1088         }
1089         falcon_writel_page_locked(efx, &timer_cmd, TIMER_CMD_REG_KER,
1090                                   channel->channel);
1091
1092 }
1093
1094 /* Allocate buffer table entries for event queue */
1095 int falcon_probe_eventq(struct efx_channel *channel)
1096 {
1097         struct efx_nic *efx = channel->efx;
1098         unsigned int evq_size;
1099
1100         evq_size = FALCON_EVQ_SIZE * sizeof(efx_qword_t);
1101         return falcon_alloc_special_buffer(efx, &channel->eventq, evq_size);
1102 }
1103
1104 void falcon_init_eventq(struct efx_channel *channel)
1105 {
1106         efx_oword_t evq_ptr;
1107         struct efx_nic *efx = channel->efx;
1108
1109         EFX_LOG(efx, "channel %d event queue in special buffers %d-%d\n",
1110                 channel->channel, channel->eventq.index,
1111                 channel->eventq.index + channel->eventq.entries - 1);
1112
1113         /* Pin event queue buffer */
1114         falcon_init_special_buffer(efx, &channel->eventq);
1115
1116         /* Fill event queue with all ones (i.e. empty events) */
1117         memset(channel->eventq.addr, 0xff, channel->eventq.len);
1118
1119         /* Push event queue to card */
1120         EFX_POPULATE_OWORD_3(evq_ptr,
1121                              EVQ_EN, 1,
1122                              EVQ_SIZE, FALCON_EVQ_ORDER,
1123                              EVQ_BUF_BASE_ID, channel->eventq.index);
1124         falcon_write_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base,
1125                            channel->channel);
1126
1127         falcon_set_int_moderation(channel);
1128 }
1129
1130 void falcon_fini_eventq(struct efx_channel *channel)
1131 {
1132         efx_oword_t eventq_ptr;
1133         struct efx_nic *efx = channel->efx;
1134
1135         /* Remove event queue from card */
1136         EFX_ZERO_OWORD(eventq_ptr);
1137         falcon_write_table(efx, &eventq_ptr, efx->type->evq_ptr_tbl_base,
1138                            channel->channel);
1139
1140         /* Unpin event queue */
1141         falcon_fini_special_buffer(efx, &channel->eventq);
1142 }
1143
1144 /* Free buffers backing event queue */
1145 void falcon_remove_eventq(struct efx_channel *channel)
1146 {
1147         falcon_free_special_buffer(channel->efx, &channel->eventq);
1148 }
1149
1150
1151 /* Generates a test event on the event queue.  A subsequent call to
1152  * process_eventq() should pick up the event and place the value of
1153  * "magic" into channel->eventq_magic;
1154  */
1155 void falcon_generate_test_event(struct efx_channel *channel, unsigned int magic)
1156 {
1157         efx_qword_t test_event;
1158
1159         EFX_POPULATE_QWORD_2(test_event,
1160                              EV_CODE, DRV_GEN_EV_DECODE,
1161                              EVQ_MAGIC, magic);
1162         falcon_generate_event(channel, &test_event);
1163 }
1164
1165 void falcon_sim_phy_event(struct efx_nic *efx)
1166 {
1167         efx_qword_t phy_event;
1168
1169         EFX_POPULATE_QWORD_1(phy_event, EV_CODE, GLOBAL_EV_DECODE);
1170         if (EFX_IS10G(efx))
1171                 EFX_SET_OWORD_FIELD(phy_event, XG_PHY_INTR, 1);
1172         else
1173                 EFX_SET_OWORD_FIELD(phy_event, G_PHY0_INTR, 1);
1174
1175         falcon_generate_event(&efx->channel[0], &phy_event);
1176 }
1177
1178 /**************************************************************************
1179  *
1180  * Flush handling
1181  *
1182  **************************************************************************/
1183
1184
1185 static void falcon_poll_flush_events(struct efx_nic *efx)
1186 {
1187         struct efx_channel *channel = &efx->channel[0];
1188         struct efx_tx_queue *tx_queue;
1189         struct efx_rx_queue *rx_queue;
1190         unsigned int read_ptr, i;
1191
1192         read_ptr = channel->eventq_read_ptr;
1193         for (i = 0; i < FALCON_EVQ_SIZE; ++i) {
1194                 efx_qword_t *event = falcon_event(channel, read_ptr);
1195                 int ev_code, ev_sub_code, ev_queue;
1196                 bool ev_failed;
1197                 if (!falcon_event_present(event))
1198                         break;
1199
1200                 ev_code = EFX_QWORD_FIELD(*event, EV_CODE);
1201                 if (ev_code != DRIVER_EV_DECODE)
1202                         continue;
1203
1204                 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
1205                 switch (ev_sub_code) {
1206                 case TX_DESCQ_FLS_DONE_EV_DECODE:
1207                         ev_queue = EFX_QWORD_FIELD(*event,
1208                                                    DRIVER_EV_TX_DESCQ_ID);
1209                         if (ev_queue < EFX_TX_QUEUE_COUNT) {
1210                                 tx_queue = efx->tx_queue + ev_queue;
1211                                 tx_queue->flushed = true;
1212                         }
1213                         break;
1214                 case RX_DESCQ_FLS_DONE_EV_DECODE:
1215                         ev_queue = EFX_QWORD_FIELD(*event,
1216                                                    DRIVER_EV_RX_DESCQ_ID);
1217                         ev_failed = EFX_QWORD_FIELD(*event,
1218                                                     DRIVER_EV_RX_FLUSH_FAIL);
1219                         if (ev_queue < efx->n_rx_queues) {
1220                                 rx_queue = efx->rx_queue + ev_queue;
1221
1222                                 /* retry the rx flush */
1223                                 if (ev_failed)
1224                                         falcon_flush_rx_queue(rx_queue);
1225                                 else
1226                                         rx_queue->flushed = true;
1227                         }
1228                         break;
1229                 }
1230
1231                 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
1232         }
1233 }
1234
1235 /* Handle tx and rx flushes at the same time, since they run in
1236  * parallel in the hardware and there's no reason for us to
1237  * serialise them */
1238 int falcon_flush_queues(struct efx_nic *efx)
1239 {
1240         struct efx_rx_queue *rx_queue;
1241         struct efx_tx_queue *tx_queue;
1242         int i;
1243         bool outstanding;
1244
1245         /* Issue flush requests */
1246         efx_for_each_tx_queue(tx_queue, efx) {
1247                 tx_queue->flushed = false;
1248                 falcon_flush_tx_queue(tx_queue);
1249         }
1250         efx_for_each_rx_queue(rx_queue, efx) {
1251                 rx_queue->flushed = false;
1252                 falcon_flush_rx_queue(rx_queue);
1253         }
1254
1255         /* Poll the evq looking for flush completions. Since we're not pushing
1256          * any more rx or tx descriptors at this point, we're in no danger of
1257          * overflowing the evq whilst we wait */
1258         for (i = 0; i < FALCON_FLUSH_POLL_COUNT; ++i) {
1259                 msleep(FALCON_FLUSH_INTERVAL);
1260                 falcon_poll_flush_events(efx);
1261
1262                 /* Check if every queue has been succesfully flushed */
1263                 outstanding = false;
1264                 efx_for_each_tx_queue(tx_queue, efx)
1265                         outstanding |= !tx_queue->flushed;
1266                 efx_for_each_rx_queue(rx_queue, efx)
1267                         outstanding |= !rx_queue->flushed;
1268                 if (!outstanding)
1269                         return 0;
1270         }
1271
1272         /* Mark the queues as all flushed. We're going to return failure
1273          * leading to a reset, or fake up success anyway. "flushed" now
1274          * indicates that we tried to flush. */
1275         efx_for_each_tx_queue(tx_queue, efx) {
1276                 if (!tx_queue->flushed)
1277                         EFX_ERR(efx, "tx queue %d flush command timed out\n",
1278                                 tx_queue->queue);
1279                 tx_queue->flushed = true;
1280         }
1281         efx_for_each_rx_queue(rx_queue, efx) {
1282                 if (!rx_queue->flushed)
1283                         EFX_ERR(efx, "rx queue %d flush command timed out\n",
1284                                 rx_queue->queue);
1285                 rx_queue->flushed = true;
1286         }
1287
1288         if (EFX_WORKAROUND_7803(efx))
1289                 return 0;
1290
1291         return -ETIMEDOUT;
1292 }
1293
1294 /**************************************************************************
1295  *
1296  * Falcon hardware interrupts
1297  * The hardware interrupt handler does very little work; all the event
1298  * queue processing is carried out by per-channel tasklets.
1299  *
1300  **************************************************************************/
1301
1302 /* Enable/disable/generate Falcon interrupts */
1303 static inline void falcon_interrupts(struct efx_nic *efx, int enabled,
1304                                      int force)
1305 {
1306         efx_oword_t int_en_reg_ker;
1307
1308         EFX_POPULATE_OWORD_2(int_en_reg_ker,
1309                              KER_INT_KER, force,
1310                              DRV_INT_EN_KER, enabled);
1311         falcon_write(efx, &int_en_reg_ker, INT_EN_REG_KER);
1312 }
1313
1314 void falcon_enable_interrupts(struct efx_nic *efx)
1315 {
1316         efx_oword_t int_adr_reg_ker;
1317         struct efx_channel *channel;
1318
1319         EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1320         wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1321
1322         /* Program address */
1323         EFX_POPULATE_OWORD_2(int_adr_reg_ker,
1324                              NORM_INT_VEC_DIS_KER, EFX_INT_MODE_USE_MSI(efx),
1325                              INT_ADR_KER, efx->irq_status.dma_addr);
1326         falcon_write(efx, &int_adr_reg_ker, INT_ADR_REG_KER);
1327
1328         /* Enable interrupts */
1329         falcon_interrupts(efx, 1, 0);
1330
1331         /* Force processing of all the channels to get the EVQ RPTRs up to
1332            date */
1333         efx_for_each_channel(channel, efx)
1334                 efx_schedule_channel(channel);
1335 }
1336
1337 void falcon_disable_interrupts(struct efx_nic *efx)
1338 {
1339         /* Disable interrupts */
1340         falcon_interrupts(efx, 0, 0);
1341 }
1342
1343 /* Generate a Falcon test interrupt
1344  * Interrupt must already have been enabled, otherwise nasty things
1345  * may happen.
1346  */
1347 void falcon_generate_interrupt(struct efx_nic *efx)
1348 {
1349         falcon_interrupts(efx, 1, 1);
1350 }
1351
1352 /* Acknowledge a legacy interrupt from Falcon
1353  *
1354  * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
1355  *
1356  * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
1357  * BIU. Interrupt acknowledge is read sensitive so must write instead
1358  * (then read to ensure the BIU collector is flushed)
1359  *
1360  * NB most hardware supports MSI interrupts
1361  */
1362 static inline void falcon_irq_ack_a1(struct efx_nic *efx)
1363 {
1364         efx_dword_t reg;
1365
1366         EFX_POPULATE_DWORD_1(reg, INT_ACK_DUMMY_DATA, 0xb7eb7e);
1367         falcon_writel(efx, &reg, INT_ACK_REG_KER_A1);
1368         falcon_readl(efx, &reg, WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1);
1369 }
1370
1371 /* Process a fatal interrupt
1372  * Disable bus mastering ASAP and schedule a reset
1373  */
1374 static irqreturn_t falcon_fatal_interrupt(struct efx_nic *efx)
1375 {
1376         struct falcon_nic_data *nic_data = efx->nic_data;
1377         efx_oword_t *int_ker = efx->irq_status.addr;
1378         efx_oword_t fatal_intr;
1379         int error, mem_perr;
1380         static int n_int_errors;
1381
1382         falcon_read(efx, &fatal_intr, FATAL_INTR_REG_KER);
1383         error = EFX_OWORD_FIELD(fatal_intr, INT_KER_ERROR);
1384
1385         EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status "
1386                 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1387                 EFX_OWORD_VAL(fatal_intr),
1388                 error ? "disabling bus mastering" : "no recognised error");
1389         if (error == 0)
1390                 goto out;
1391
1392         /* If this is a memory parity error dump which blocks are offending */
1393         mem_perr = EFX_OWORD_FIELD(fatal_intr, MEM_PERR_INT_KER);
1394         if (mem_perr) {
1395                 efx_oword_t reg;
1396                 falcon_read(efx, &reg, MEM_STAT_REG_KER);
1397                 EFX_ERR(efx, "SYSTEM ERROR: memory parity error "
1398                         EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg));
1399         }
1400
1401         /* Disable both devices */
1402         pci_clear_master(efx->pci_dev);
1403         if (FALCON_IS_DUAL_FUNC(efx))
1404                 pci_clear_master(nic_data->pci_dev2);
1405         falcon_disable_interrupts(efx);
1406
1407         if (++n_int_errors < FALCON_MAX_INT_ERRORS) {
1408                 EFX_ERR(efx, "SYSTEM ERROR - reset scheduled\n");
1409                 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1410         } else {
1411                 EFX_ERR(efx, "SYSTEM ERROR - max number of errors seen."
1412                         "NIC will be disabled\n");
1413                 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1414         }
1415 out:
1416         return IRQ_HANDLED;
1417 }
1418
1419 /* Handle a legacy interrupt from Falcon
1420  * Acknowledges the interrupt and schedule event queue processing.
1421  */
1422 static irqreturn_t falcon_legacy_interrupt_b0(int irq, void *dev_id)
1423 {
1424         struct efx_nic *efx = dev_id;
1425         efx_oword_t *int_ker = efx->irq_status.addr;
1426         struct efx_channel *channel;
1427         efx_dword_t reg;
1428         u32 queues;
1429         int syserr;
1430
1431         /* Read the ISR which also ACKs the interrupts */
1432         falcon_readl(efx, &reg, INT_ISR0_B0);
1433         queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1434
1435         /* Check to see if we have a serious error condition */
1436         syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1437         if (unlikely(syserr))
1438                 return falcon_fatal_interrupt(efx);
1439
1440         if (queues == 0)
1441                 return IRQ_NONE;
1442
1443         efx->last_irq_cpu = raw_smp_processor_id();
1444         EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1445                   irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1446
1447         /* Schedule processing of any interrupting queues */
1448         channel = &efx->channel[0];
1449         while (queues) {
1450                 if (queues & 0x01)
1451                         efx_schedule_channel(channel);
1452                 channel++;
1453                 queues >>= 1;
1454         }
1455
1456         return IRQ_HANDLED;
1457 }
1458
1459
1460 static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
1461 {
1462         struct efx_nic *efx = dev_id;
1463         efx_oword_t *int_ker = efx->irq_status.addr;
1464         struct efx_channel *channel;
1465         int syserr;
1466         int queues;
1467
1468         /* Check to see if this is our interrupt.  If it isn't, we
1469          * exit without having touched the hardware.
1470          */
1471         if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
1472                 EFX_TRACE(efx, "IRQ %d on CPU %d not for me\n", irq,
1473                           raw_smp_processor_id());
1474                 return IRQ_NONE;
1475         }
1476         efx->last_irq_cpu = raw_smp_processor_id();
1477         EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1478                   irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1479
1480         /* Check to see if we have a serious error condition */
1481         syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1482         if (unlikely(syserr))
1483                 return falcon_fatal_interrupt(efx);
1484
1485         /* Determine interrupting queues, clear interrupt status
1486          * register and acknowledge the device interrupt.
1487          */
1488         BUILD_BUG_ON(INT_EVQS_WIDTH > EFX_MAX_CHANNELS);
1489         queues = EFX_OWORD_FIELD(*int_ker, INT_EVQS);
1490         EFX_ZERO_OWORD(*int_ker);
1491         wmb(); /* Ensure the vector is cleared before interrupt ack */
1492         falcon_irq_ack_a1(efx);
1493
1494         /* Schedule processing of any interrupting queues */
1495         channel = &efx->channel[0];
1496         while (queues) {
1497                 if (queues & 0x01)
1498                         efx_schedule_channel(channel);
1499                 channel++;
1500                 queues >>= 1;
1501         }
1502
1503         return IRQ_HANDLED;
1504 }
1505
1506 /* Handle an MSI interrupt from Falcon
1507  *
1508  * Handle an MSI hardware interrupt.  This routine schedules event
1509  * queue processing.  No interrupt acknowledgement cycle is necessary.
1510  * Also, we never need to check that the interrupt is for us, since
1511  * MSI interrupts cannot be shared.
1512  */
1513 static irqreturn_t falcon_msi_interrupt(int irq, void *dev_id)
1514 {
1515         struct efx_channel *channel = dev_id;
1516         struct efx_nic *efx = channel->efx;
1517         efx_oword_t *int_ker = efx->irq_status.addr;
1518         int syserr;
1519
1520         efx->last_irq_cpu = raw_smp_processor_id();
1521         EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1522                   irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1523
1524         /* Check to see if we have a serious error condition */
1525         syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1526         if (unlikely(syserr))
1527                 return falcon_fatal_interrupt(efx);
1528
1529         /* Schedule processing of the channel */
1530         efx_schedule_channel(channel);
1531
1532         return IRQ_HANDLED;
1533 }
1534
1535
1536 /* Setup RSS indirection table.
1537  * This maps from the hash value of the packet to RXQ
1538  */
1539 static void falcon_setup_rss_indir_table(struct efx_nic *efx)
1540 {
1541         int i = 0;
1542         unsigned long offset;
1543         efx_dword_t dword;
1544
1545         if (falcon_rev(efx) < FALCON_REV_B0)
1546                 return;
1547
1548         for (offset = RX_RSS_INDIR_TBL_B0;
1549              offset < RX_RSS_INDIR_TBL_B0 + 0x800;
1550              offset += 0x10) {
1551                 EFX_POPULATE_DWORD_1(dword, RX_RSS_INDIR_ENT_B0,
1552                                      i % efx->n_rx_queues);
1553                 falcon_writel(efx, &dword, offset);
1554                 i++;
1555         }
1556 }
1557
1558 /* Hook interrupt handler(s)
1559  * Try MSI and then legacy interrupts.
1560  */
1561 int falcon_init_interrupt(struct efx_nic *efx)
1562 {
1563         struct efx_channel *channel;
1564         int rc;
1565
1566         if (!EFX_INT_MODE_USE_MSI(efx)) {
1567                 irq_handler_t handler;
1568                 if (falcon_rev(efx) >= FALCON_REV_B0)
1569                         handler = falcon_legacy_interrupt_b0;
1570                 else
1571                         handler = falcon_legacy_interrupt_a1;
1572
1573                 rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED,
1574                                  efx->name, efx);
1575                 if (rc) {
1576                         EFX_ERR(efx, "failed to hook legacy IRQ %d\n",
1577                                 efx->pci_dev->irq);
1578                         goto fail1;
1579                 }
1580                 return 0;
1581         }
1582
1583         /* Hook MSI or MSI-X interrupt */
1584         efx_for_each_channel(channel, efx) {
1585                 rc = request_irq(channel->irq, falcon_msi_interrupt,
1586                                  IRQF_PROBE_SHARED, /* Not shared */
1587                                  channel->name, channel);
1588                 if (rc) {
1589                         EFX_ERR(efx, "failed to hook IRQ %d\n", channel->irq);
1590                         goto fail2;
1591                 }
1592         }
1593
1594         return 0;
1595
1596  fail2:
1597         efx_for_each_channel(channel, efx)
1598                 free_irq(channel->irq, channel);
1599  fail1:
1600         return rc;
1601 }
1602
1603 void falcon_fini_interrupt(struct efx_nic *efx)
1604 {
1605         struct efx_channel *channel;
1606         efx_oword_t reg;
1607
1608         /* Disable MSI/MSI-X interrupts */
1609         efx_for_each_channel(channel, efx) {
1610                 if (channel->irq)
1611                         free_irq(channel->irq, channel);
1612         }
1613
1614         /* ACK legacy interrupt */
1615         if (falcon_rev(efx) >= FALCON_REV_B0)
1616                 falcon_read(efx, &reg, INT_ISR0_B0);
1617         else
1618                 falcon_irq_ack_a1(efx);
1619
1620         /* Disable legacy interrupt */
1621         if (efx->legacy_irq)
1622                 free_irq(efx->legacy_irq, efx);
1623 }
1624
1625 /**************************************************************************
1626  *
1627  * EEPROM/flash
1628  *
1629  **************************************************************************
1630  */
1631
1632 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
1633
1634 static int falcon_spi_poll(struct efx_nic *efx)
1635 {
1636         efx_oword_t reg;
1637         falcon_read(efx, &reg, EE_SPI_HCMD_REG_KER);
1638         return EFX_OWORD_FIELD(reg, EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0;
1639 }
1640
1641 /* Wait for SPI command completion */
1642 static int falcon_spi_wait(struct efx_nic *efx)
1643 {
1644         /* Most commands will finish quickly, so we start polling at
1645          * very short intervals.  Sometimes the command may have to
1646          * wait for VPD or expansion ROM access outside of our
1647          * control, so we allow up to 100 ms. */
1648         unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10);
1649         int i;
1650
1651         for (i = 0; i < 10; i++) {
1652                 if (!falcon_spi_poll(efx))
1653                         return 0;
1654                 udelay(10);
1655         }
1656
1657         for (;;) {
1658                 if (!falcon_spi_poll(efx))
1659                         return 0;
1660                 if (time_after_eq(jiffies, timeout)) {
1661                         EFX_ERR(efx, "timed out waiting for SPI\n");
1662                         return -ETIMEDOUT;
1663                 }
1664                 schedule_timeout_uninterruptible(1);
1665         }
1666 }
1667
1668 int falcon_spi_cmd(const struct efx_spi_device *spi,
1669                    unsigned int command, int address,
1670                    const void *in, void *out, size_t len)
1671 {
1672         struct efx_nic *efx = spi->efx;
1673         bool addressed = (address >= 0);
1674         bool reading = (out != NULL);
1675         efx_oword_t reg;
1676         int rc;
1677
1678         /* Input validation */
1679         if (len > FALCON_SPI_MAX_LEN)
1680                 return -EINVAL;
1681         BUG_ON(!mutex_is_locked(&efx->spi_lock));
1682
1683         /* Check that previous command is not still running */
1684         rc = falcon_spi_poll(efx);
1685         if (rc)
1686                 return rc;
1687
1688         /* Program address register, if we have an address */
1689         if (addressed) {
1690                 EFX_POPULATE_OWORD_1(reg, EE_SPI_HADR_ADR, address);
1691                 falcon_write(efx, &reg, EE_SPI_HADR_REG_KER);
1692         }
1693
1694         /* Program data register, if we have data */
1695         if (in != NULL) {
1696                 memcpy(&reg, in, len);
1697                 falcon_write(efx, &reg, EE_SPI_HDATA_REG_KER);
1698         }
1699
1700         /* Issue read/write command */
1701         EFX_POPULATE_OWORD_7(reg,
1702                              EE_SPI_HCMD_CMD_EN, 1,
1703                              EE_SPI_HCMD_SF_SEL, spi->device_id,
1704                              EE_SPI_HCMD_DABCNT, len,
1705                              EE_SPI_HCMD_READ, reading,
1706                              EE_SPI_HCMD_DUBCNT, 0,
1707                              EE_SPI_HCMD_ADBCNT,
1708                              (addressed ? spi->addr_len : 0),
1709                              EE_SPI_HCMD_ENC, command);
1710         falcon_write(efx, &reg, EE_SPI_HCMD_REG_KER);
1711
1712         /* Wait for read/write to complete */
1713         rc = falcon_spi_wait(efx);
1714         if (rc)
1715                 return rc;
1716
1717         /* Read data */
1718         if (out != NULL) {
1719                 falcon_read(efx, &reg, EE_SPI_HDATA_REG_KER);
1720                 memcpy(out, &reg, len);
1721         }
1722
1723         return 0;
1724 }
1725
1726 static size_t
1727 falcon_spi_write_limit(const struct efx_spi_device *spi, size_t start)
1728 {
1729         return min(FALCON_SPI_MAX_LEN,
1730                    (spi->block_size - (start & (spi->block_size - 1))));
1731 }
1732
1733 static inline u8
1734 efx_spi_munge_command(const struct efx_spi_device *spi,
1735                       const u8 command, const unsigned int address)
1736 {
1737         return command | (((address >> 8) & spi->munge_address) << 3);
1738 }
1739
1740 /* Wait up to 10 ms for buffered write completion */
1741 int falcon_spi_wait_write(const struct efx_spi_device *spi)
1742 {
1743         struct efx_nic *efx = spi->efx;
1744         unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100);
1745         u8 status;
1746         int rc;
1747
1748         for (;;) {
1749                 rc = falcon_spi_cmd(spi, SPI_RDSR, -1, NULL,
1750                                     &status, sizeof(status));
1751                 if (rc)
1752                         return rc;
1753                 if (!(status & SPI_STATUS_NRDY))
1754                         return 0;
1755                 if (time_after_eq(jiffies, timeout)) {
1756                         EFX_ERR(efx, "SPI write timeout on device %d"
1757                                 " last status=0x%02x\n",
1758                                 spi->device_id, status);
1759                         return -ETIMEDOUT;
1760                 }
1761                 schedule_timeout_uninterruptible(1);
1762         }
1763 }
1764
1765 int falcon_spi_read(const struct efx_spi_device *spi, loff_t start,
1766                     size_t len, size_t *retlen, u8 *buffer)
1767 {
1768         size_t block_len, pos = 0;
1769         unsigned int command;
1770         int rc = 0;
1771
1772         while (pos < len) {
1773                 block_len = min(len - pos, FALCON_SPI_MAX_LEN);
1774
1775                 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1776                 rc = falcon_spi_cmd(spi, command, start + pos, NULL,
1777                                     buffer + pos, block_len);
1778                 if (rc)
1779                         break;
1780                 pos += block_len;
1781
1782                 /* Avoid locking up the system */
1783                 cond_resched();
1784                 if (signal_pending(current)) {
1785                         rc = -EINTR;
1786                         break;
1787                 }
1788         }
1789
1790         if (retlen)
1791                 *retlen = pos;
1792         return rc;
1793 }
1794
1795 int falcon_spi_write(const struct efx_spi_device *spi, loff_t start,
1796                      size_t len, size_t *retlen, const u8 *buffer)
1797 {
1798         u8 verify_buffer[FALCON_SPI_MAX_LEN];
1799         size_t block_len, pos = 0;
1800         unsigned int command;
1801         int rc = 0;
1802
1803         while (pos < len) {
1804                 rc = falcon_spi_cmd(spi, SPI_WREN, -1, NULL, NULL, 0);
1805                 if (rc)
1806                         break;
1807
1808                 block_len = min(len - pos,
1809                                 falcon_spi_write_limit(spi, start + pos));
1810                 command = efx_spi_munge_command(spi, SPI_WRITE, start + pos);
1811                 rc = falcon_spi_cmd(spi, command, start + pos,
1812                                     buffer + pos, NULL, block_len);
1813                 if (rc)
1814                         break;
1815
1816                 rc = falcon_spi_wait_write(spi);
1817                 if (rc)
1818                         break;
1819
1820                 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1821                 rc = falcon_spi_cmd(spi, command, start + pos,
1822                                     NULL, verify_buffer, block_len);
1823                 if (memcmp(verify_buffer, buffer + pos, block_len)) {
1824                         rc = -EIO;
1825                         break;
1826                 }
1827
1828                 pos += block_len;
1829
1830                 /* Avoid locking up the system */
1831                 cond_resched();
1832                 if (signal_pending(current)) {
1833                         rc = -EINTR;
1834                         break;
1835                 }
1836         }
1837
1838         if (retlen)
1839                 *retlen = pos;
1840         return rc;
1841 }
1842
1843 /**************************************************************************
1844  *
1845  * MAC wrapper
1846  *
1847  **************************************************************************
1848  */
1849
1850 static int falcon_reset_macs(struct efx_nic *efx)
1851 {
1852         efx_oword_t reg;
1853         int count;
1854
1855         if (falcon_rev(efx) < FALCON_REV_B0) {
1856                 /* It's not safe to use GLB_CTL_REG to reset the
1857                  * macs, so instead use the internal MAC resets
1858                  */
1859                 if (!EFX_IS10G(efx)) {
1860                         EFX_POPULATE_OWORD_1(reg, GM_SW_RST, 1);
1861                         falcon_write(efx, &reg, GM_CFG1_REG);
1862                         udelay(1000);
1863
1864                         EFX_POPULATE_OWORD_1(reg, GM_SW_RST, 0);
1865                         falcon_write(efx, &reg, GM_CFG1_REG);
1866                         udelay(1000);
1867                         return 0;
1868                 } else {
1869                         EFX_POPULATE_OWORD_1(reg, XM_CORE_RST, 1);
1870                         falcon_write(efx, &reg, XM_GLB_CFG_REG);
1871
1872                         for (count = 0; count < 10000; count++) {
1873                                 falcon_read(efx, &reg, XM_GLB_CFG_REG);
1874                                 if (EFX_OWORD_FIELD(reg, XM_CORE_RST) == 0)
1875                                         return 0;
1876                                 udelay(10);
1877                         }
1878
1879                         EFX_ERR(efx, "timed out waiting for XMAC core reset\n");
1880                         return -ETIMEDOUT;
1881                 }
1882         }
1883
1884         /* MAC stats will fail whilst the TX fifo is draining. Serialise
1885          * the drain sequence with the statistics fetch */
1886         efx_stats_disable(efx);
1887
1888         falcon_read(efx, &reg, MAC0_CTRL_REG_KER);
1889         EFX_SET_OWORD_FIELD(reg, TXFIFO_DRAIN_EN_B0, 1);
1890         falcon_write(efx, &reg, MAC0_CTRL_REG_KER);
1891
1892         falcon_read(efx, &reg, GLB_CTL_REG_KER);
1893         EFX_SET_OWORD_FIELD(reg, RST_XGTX, 1);
1894         EFX_SET_OWORD_FIELD(reg, RST_XGRX, 1);
1895         EFX_SET_OWORD_FIELD(reg, RST_EM, 1);
1896         falcon_write(efx, &reg, GLB_CTL_REG_KER);
1897
1898         count = 0;
1899         while (1) {
1900                 falcon_read(efx, &reg, GLB_CTL_REG_KER);
1901                 if (!EFX_OWORD_FIELD(reg, RST_XGTX) &&
1902                     !EFX_OWORD_FIELD(reg, RST_XGRX) &&
1903                     !EFX_OWORD_FIELD(reg, RST_EM)) {
1904                         EFX_LOG(efx, "Completed MAC reset after %d loops\n",
1905                                 count);
1906                         break;
1907                 }
1908                 if (count > 20) {
1909                         EFX_ERR(efx, "MAC reset failed\n");
1910                         break;
1911                 }
1912                 count++;
1913                 udelay(10);
1914         }
1915
1916         efx_stats_enable(efx);
1917
1918         /* If we've reset the EM block and the link is up, then
1919          * we'll have to kick the XAUI link so the PHY can recover */
1920         if (efx->link_up && EFX_IS10G(efx) && EFX_WORKAROUND_5147(efx))
1921                 falcon_reset_xaui(efx);
1922
1923         return 0;
1924 }
1925
1926 void falcon_drain_tx_fifo(struct efx_nic *efx)
1927 {
1928         efx_oword_t reg;
1929
1930         if ((falcon_rev(efx) < FALCON_REV_B0) ||
1931             (efx->loopback_mode != LOOPBACK_NONE))
1932                 return;
1933
1934         falcon_read(efx, &reg, MAC0_CTRL_REG_KER);
1935         /* There is no point in draining more than once */
1936         if (EFX_OWORD_FIELD(reg, TXFIFO_DRAIN_EN_B0))
1937                 return;
1938
1939         falcon_reset_macs(efx);
1940 }
1941
1942 void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
1943 {
1944         efx_oword_t reg;
1945
1946         if (falcon_rev(efx) < FALCON_REV_B0)
1947                 return;
1948
1949         /* Isolate the MAC -> RX */
1950         falcon_read(efx, &reg, RX_CFG_REG_KER);
1951         EFX_SET_OWORD_FIELD(reg, RX_INGR_EN_B0, 0);
1952         falcon_write(efx, &reg, RX_CFG_REG_KER);
1953
1954         if (!efx->link_up)
1955                 falcon_drain_tx_fifo(efx);
1956 }
1957
1958 void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
1959 {
1960         efx_oword_t reg;
1961         int link_speed;
1962         bool tx_fc;
1963
1964         switch (efx->link_speed) {
1965         case 10000: link_speed = 3; break;
1966         case 1000:  link_speed = 2; break;
1967         case 100:   link_speed = 1; break;
1968         default:    link_speed = 0; break;
1969         }
1970         /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
1971          * as advertised.  Disable to ensure packets are not
1972          * indefinitely held and TX queue can be flushed at any point
1973          * while the link is down. */
1974         EFX_POPULATE_OWORD_5(reg,
1975                              MAC_XOFF_VAL, 0xffff /* max pause time */,
1976                              MAC_BCAD_ACPT, 1,
1977                              MAC_UC_PROM, efx->promiscuous,
1978                              MAC_LINK_STATUS, 1, /* always set */
1979                              MAC_SPEED, link_speed);
1980         /* On B0, MAC backpressure can be disabled and packets get
1981          * discarded. */
1982         if (falcon_rev(efx) >= FALCON_REV_B0) {
1983                 EFX_SET_OWORD_FIELD(reg, TXFIFO_DRAIN_EN_B0,
1984                                     !efx->link_up);
1985         }
1986
1987         falcon_write(efx, &reg, MAC0_CTRL_REG_KER);
1988
1989         /* Restore the multicast hash registers. */
1990         falcon_set_multicast_hash(efx);
1991
1992         /* Transmission of pause frames when RX crosses the threshold is
1993          * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL.
1994          * Action on receipt of pause frames is controller by XM_DIS_FCNTL */
1995         tx_fc = !!(efx->link_fc & EFX_FC_TX);
1996         falcon_read(efx, &reg, RX_CFG_REG_KER);
1997         EFX_SET_OWORD_FIELD_VER(efx, reg, RX_XOFF_MAC_EN, tx_fc);
1998
1999         /* Unisolate the MAC -> RX */
2000         if (falcon_rev(efx) >= FALCON_REV_B0)
2001                 EFX_SET_OWORD_FIELD(reg, RX_INGR_EN_B0, 1);
2002         falcon_write(efx, &reg, RX_CFG_REG_KER);
2003 }
2004
2005 int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset)
2006 {
2007         efx_oword_t reg;
2008         u32 *dma_done;
2009         int i;
2010
2011         if (disable_dma_stats)
2012                 return 0;
2013
2014         /* Statistics fetch will fail if the MAC is in TX drain */
2015         if (falcon_rev(efx) >= FALCON_REV_B0) {
2016                 efx_oword_t temp;
2017                 falcon_read(efx, &temp, MAC0_CTRL_REG_KER);
2018                 if (EFX_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0))
2019                         return 0;
2020         }
2021
2022         dma_done = (efx->stats_buffer.addr + done_offset);
2023         *dma_done = FALCON_STATS_NOT_DONE;
2024         wmb(); /* ensure done flag is clear */
2025
2026         /* Initiate DMA transfer of stats */
2027         EFX_POPULATE_OWORD_2(reg,
2028                              MAC_STAT_DMA_CMD, 1,
2029                              MAC_STAT_DMA_ADR,
2030                              efx->stats_buffer.dma_addr);
2031         falcon_write(efx, &reg, MAC0_STAT_DMA_REG_KER);
2032
2033         /* Wait for transfer to complete */
2034         for (i = 0; i < 400; i++) {
2035                 if (*(volatile u32 *)dma_done == FALCON_STATS_DONE) {
2036                         rmb(); /* Ensure the stats are valid. */
2037                         return 0;
2038                 }
2039                 udelay(10);
2040         }
2041
2042         EFX_ERR(efx, "timed out waiting for statistics\n");
2043         return -ETIMEDOUT;
2044 }
2045
2046 /**************************************************************************
2047  *
2048  * PHY access via GMII
2049  *
2050  **************************************************************************
2051  */
2052
2053 /* Use the top bit of the MII PHY id to indicate the PHY type
2054  * (1G/10G), with the remaining bits as the actual PHY id.
2055  *
2056  * This allows us to avoid leaking information from the mii_if_info
2057  * structure into other data structures.
2058  */
2059 #define FALCON_PHY_ID_ID_WIDTH  EFX_WIDTH(MD_PRT_DEV_ADR)
2060 #define FALCON_PHY_ID_ID_MASK   ((1 << FALCON_PHY_ID_ID_WIDTH) - 1)
2061 #define FALCON_PHY_ID_WIDTH     (FALCON_PHY_ID_ID_WIDTH + 1)
2062 #define FALCON_PHY_ID_MASK      ((1 << FALCON_PHY_ID_WIDTH) - 1)
2063 #define FALCON_PHY_ID_10G       (1 << (FALCON_PHY_ID_WIDTH - 1))
2064
2065
2066 /* Packing the clause 45 port and device fields into a single value */
2067 #define MD_PRT_ADR_COMP_LBN   (MD_PRT_ADR_LBN - MD_DEV_ADR_LBN)
2068 #define MD_PRT_ADR_COMP_WIDTH  MD_PRT_ADR_WIDTH
2069 #define MD_DEV_ADR_COMP_LBN    0
2070 #define MD_DEV_ADR_COMP_WIDTH  MD_DEV_ADR_WIDTH
2071
2072
2073 /* Wait for GMII access to complete */
2074 static int falcon_gmii_wait(struct efx_nic *efx)
2075 {
2076         efx_dword_t md_stat;
2077         int count;
2078
2079         /* wait upto 50ms - taken max from datasheet */
2080         for (count = 0; count < 5000; count++) {
2081                 falcon_readl(efx, &md_stat, MD_STAT_REG_KER);
2082                 if (EFX_DWORD_FIELD(md_stat, MD_BSY) == 0) {
2083                         if (EFX_DWORD_FIELD(md_stat, MD_LNFL) != 0 ||
2084                             EFX_DWORD_FIELD(md_stat, MD_BSERR) != 0) {
2085                                 EFX_ERR(efx, "error from GMII access "
2086                                         EFX_DWORD_FMT"\n",
2087                                         EFX_DWORD_VAL(md_stat));
2088                                 return -EIO;
2089                         }
2090                         return 0;
2091                 }
2092                 udelay(10);
2093         }
2094         EFX_ERR(efx, "timed out waiting for GMII\n");
2095         return -ETIMEDOUT;
2096 }
2097
2098 /* Writes a GMII register of a PHY connected to Falcon using MDIO. */
2099 static void falcon_mdio_write(struct net_device *net_dev, int phy_id,
2100                               int addr, int value)
2101 {
2102         struct efx_nic *efx = netdev_priv(net_dev);
2103         unsigned int phy_id2 = phy_id & FALCON_PHY_ID_ID_MASK;
2104         efx_oword_t reg;
2105
2106         /* The 'generic' prt/dev packing in mdio_10g.h is conveniently
2107          * chosen so that the only current user, Falcon, can take the
2108          * packed value and use them directly.
2109          * Fail to build if this assumption is broken.
2110          */
2111         BUILD_BUG_ON(FALCON_PHY_ID_10G != MDIO45_XPRT_ID_IS10G);
2112         BUILD_BUG_ON(FALCON_PHY_ID_ID_WIDTH != MDIO45_PRT_DEV_WIDTH);
2113         BUILD_BUG_ON(MD_PRT_ADR_COMP_LBN != MDIO45_PRT_ID_COMP_LBN);
2114         BUILD_BUG_ON(MD_DEV_ADR_COMP_LBN != MDIO45_DEV_ID_COMP_LBN);
2115
2116         if (phy_id2 == PHY_ADDR_INVALID)
2117                 return;
2118
2119         /* See falcon_mdio_read for an explanation. */
2120         if (!(phy_id & FALCON_PHY_ID_10G)) {
2121                 int mmd = ffs(efx->phy_op->mmds) - 1;
2122                 EFX_TRACE(efx, "Fixing erroneous clause22 write\n");
2123                 phy_id2 = mdio_clause45_pack(phy_id2, mmd)
2124                         & FALCON_PHY_ID_ID_MASK;
2125         }
2126
2127         EFX_REGDUMP(efx, "writing GMII %d register %02x with %04x\n", phy_id,
2128                     addr, value);
2129
2130         spin_lock_bh(&efx->phy_lock);
2131
2132         /* Check MII not currently being accessed */
2133         if (falcon_gmii_wait(efx) != 0)
2134                 goto out;
2135
2136         /* Write the address/ID register */
2137         EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr);
2138         falcon_write(efx, &reg, MD_PHY_ADR_REG_KER);
2139
2140         EFX_POPULATE_OWORD_1(reg, MD_PRT_DEV_ADR, phy_id2);
2141         falcon_write(efx, &reg, MD_ID_REG_KER);
2142
2143         /* Write data */
2144         EFX_POPULATE_OWORD_1(reg, MD_TXD, value);
2145         falcon_write(efx, &reg, MD_TXD_REG_KER);
2146
2147         EFX_POPULATE_OWORD_2(reg,
2148                              MD_WRC, 1,
2149                              MD_GC, 0);
2150         falcon_write(efx, &reg, MD_CS_REG_KER);
2151
2152         /* Wait for data to be written */
2153         if (falcon_gmii_wait(efx) != 0) {
2154                 /* Abort the write operation */
2155                 EFX_POPULATE_OWORD_2(reg,
2156                                      MD_WRC, 0,
2157                                      MD_GC, 1);
2158                 falcon_write(efx, &reg, MD_CS_REG_KER);
2159                 udelay(10);
2160         }
2161
2162  out:
2163         spin_unlock_bh(&efx->phy_lock);
2164 }
2165
2166 /* Reads a GMII register from a PHY connected to Falcon.  If no value
2167  * could be read, -1 will be returned. */
2168 static int falcon_mdio_read(struct net_device *net_dev, int phy_id, int addr)
2169 {
2170         struct efx_nic *efx = netdev_priv(net_dev);
2171         unsigned int phy_addr = phy_id & FALCON_PHY_ID_ID_MASK;
2172         efx_oword_t reg;
2173         int value = -1;
2174
2175         if (phy_addr == PHY_ADDR_INVALID)
2176                 return -1;
2177
2178         /* Our PHY code knows whether it needs to talk clause 22(1G) or 45(10G)
2179          * but the generic Linux code does not make any distinction or have
2180          * any state for this.
2181          * We spot the case where someone tried to talk 22 to a 45 PHY and
2182          * redirect the request to the lowest numbered MMD as a clause45
2183          * request. This is enough to allow simple queries like id and link
2184          * state to succeed. TODO: We may need to do more in future.
2185          */
2186         if (!(phy_id & FALCON_PHY_ID_10G)) {
2187                 int mmd = ffs(efx->phy_op->mmds) - 1;
2188                 EFX_TRACE(efx, "Fixing erroneous clause22 read\n");
2189                 phy_addr = mdio_clause45_pack(phy_addr, mmd)
2190                         & FALCON_PHY_ID_ID_MASK;
2191         }
2192
2193         spin_lock_bh(&efx->phy_lock);
2194
2195         /* Check MII not currently being accessed */
2196         if (falcon_gmii_wait(efx) != 0)
2197                 goto out;
2198
2199         EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr);
2200         falcon_write(efx, &reg, MD_PHY_ADR_REG_KER);
2201
2202         EFX_POPULATE_OWORD_1(reg, MD_PRT_DEV_ADR, phy_addr);
2203         falcon_write(efx, &reg, MD_ID_REG_KER);
2204
2205         /* Request data to be read */
2206         EFX_POPULATE_OWORD_2(reg, MD_RDC, 1, MD_GC, 0);
2207         falcon_write(efx, &reg, MD_CS_REG_KER);
2208
2209         /* Wait for data to become available */
2210         value = falcon_gmii_wait(efx);
2211         if (value == 0) {
2212                 falcon_read(efx, &reg, MD_RXD_REG_KER);
2213                 value = EFX_OWORD_FIELD(reg, MD_RXD);
2214                 EFX_REGDUMP(efx, "read from GMII %d register %02x, got %04x\n",
2215                             phy_id, addr, value);
2216         } else {
2217                 /* Abort the read operation */
2218                 EFX_POPULATE_OWORD_2(reg,
2219                                      MD_RIC, 0,
2220                                      MD_GC, 1);
2221                 falcon_write(efx, &reg, MD_CS_REG_KER);
2222
2223                 EFX_LOG(efx, "read from GMII 0x%x register %02x, got "
2224                         "error %d\n", phy_id, addr, value);
2225         }
2226
2227  out:
2228         spin_unlock_bh(&efx->phy_lock);
2229
2230         return value;
2231 }
2232
2233 static void falcon_init_mdio(struct mii_if_info *gmii)
2234 {
2235         gmii->mdio_read = falcon_mdio_read;
2236         gmii->mdio_write = falcon_mdio_write;
2237         gmii->phy_id_mask = FALCON_PHY_ID_MASK;
2238         gmii->reg_num_mask = ((1 << EFX_WIDTH(MD_PHY_ADR)) - 1);
2239 }
2240
2241 static int falcon_probe_phy(struct efx_nic *efx)
2242 {
2243         switch (efx->phy_type) {
2244         case PHY_TYPE_SFX7101:
2245                 efx->phy_op = &falcon_sfx7101_phy_ops;
2246                 break;
2247         case PHY_TYPE_SFT9001A:
2248         case PHY_TYPE_SFT9001B:
2249                 efx->phy_op = &falcon_sft9001_phy_ops;
2250                 break;
2251         case PHY_TYPE_QT2022C2:
2252                 efx->phy_op = &falcon_xfp_phy_ops;
2253                 break;
2254         default:
2255                 EFX_ERR(efx, "Unknown PHY type %d\n",
2256                         efx->phy_type);
2257                 return -1;
2258         }
2259
2260         if (efx->phy_op->macs & EFX_XMAC)
2261                 efx->loopback_modes |= ((1 << LOOPBACK_XGMII) |
2262                                         (1 << LOOPBACK_XGXS) |
2263                                         (1 << LOOPBACK_XAUI));
2264         if (efx->phy_op->macs & EFX_GMAC)
2265                 efx->loopback_modes |= (1 << LOOPBACK_GMAC);
2266         efx->loopback_modes |= efx->phy_op->loopbacks;
2267
2268         return 0;
2269 }
2270
2271 int falcon_switch_mac(struct efx_nic *efx)
2272 {
2273         struct efx_mac_operations *old_mac_op = efx->mac_op;
2274         efx_oword_t nic_stat;
2275         unsigned strap_val;
2276         int rc = 0;
2277
2278         /* Don't try to fetch MAC stats while we're switching MACs */
2279         efx_stats_disable(efx);
2280
2281         /* Internal loopbacks override the phy speed setting */
2282         if (efx->loopback_mode == LOOPBACK_GMAC) {
2283                 efx->link_speed = 1000;
2284                 efx->link_fd = true;
2285         } else if (LOOPBACK_INTERNAL(efx)) {
2286                 efx->link_speed = 10000;
2287                 efx->link_fd = true;
2288         }
2289
2290         WARN_ON(!mutex_is_locked(&efx->mac_lock));
2291         efx->mac_op = (EFX_IS10G(efx) ?
2292                        &falcon_xmac_operations : &falcon_gmac_operations);
2293
2294         /* Always push the NIC_STAT_REG setting even if the mac hasn't
2295          * changed, because this function is run post online reset */
2296         falcon_read(efx, &nic_stat, NIC_STAT_REG);
2297         strap_val = EFX_IS10G(efx) ? 5 : 3;
2298         if (falcon_rev(efx) >= FALCON_REV_B0) {
2299                 EFX_SET_OWORD_FIELD(nic_stat, EE_STRAP_EN, 1);
2300                 EFX_SET_OWORD_FIELD(nic_stat, EE_STRAP_OVR, strap_val);
2301                 falcon_write(efx, &nic_stat, NIC_STAT_REG);
2302         } else {
2303                 /* Falcon A1 does not support 1G/10G speed switching
2304                  * and must not be used with a PHY that does. */
2305                 BUG_ON(EFX_OWORD_FIELD(nic_stat, STRAP_PINS) != strap_val);
2306         }
2307
2308         if (old_mac_op == efx->mac_op)
2309                 goto out;
2310
2311         EFX_LOG(efx, "selected %cMAC\n", EFX_IS10G(efx) ? 'X' : 'G');
2312         /* Not all macs support a mac-level link state */
2313         efx->mac_up = true;
2314
2315         rc = falcon_reset_macs(efx);
2316 out:
2317         efx_stats_enable(efx);
2318         return rc;
2319 }
2320
2321 /* This call is responsible for hooking in the MAC and PHY operations */
2322 int falcon_probe_port(struct efx_nic *efx)
2323 {
2324         int rc;
2325
2326         /* Hook in PHY operations table */
2327         rc = falcon_probe_phy(efx);
2328         if (rc)
2329                 return rc;
2330
2331         /* Set up GMII structure for PHY */
2332         efx->mii.supports_gmii = true;
2333         falcon_init_mdio(&efx->mii);
2334
2335         /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
2336         if (falcon_rev(efx) >= FALCON_REV_B0)
2337                 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
2338         else
2339                 efx->wanted_fc = EFX_FC_RX;
2340
2341         /* Allocate buffer for stats */
2342         rc = falcon_alloc_buffer(efx, &efx->stats_buffer,
2343                                  FALCON_MAC_STATS_SIZE);
2344         if (rc)
2345                 return rc;
2346         EFX_LOG(efx, "stats buffer at %llx (virt %p phys %lx)\n",
2347                 (unsigned long long)efx->stats_buffer.dma_addr,
2348                 efx->stats_buffer.addr,
2349                 virt_to_phys(efx->stats_buffer.addr));
2350
2351         return 0;
2352 }
2353
2354 void falcon_remove_port(struct efx_nic *efx)
2355 {
2356         falcon_free_buffer(efx, &efx->stats_buffer);
2357 }
2358
2359 /**************************************************************************
2360  *
2361  * Multicast filtering
2362  *
2363  **************************************************************************
2364  */
2365
2366 void falcon_set_multicast_hash(struct efx_nic *efx)
2367 {
2368         union efx_multicast_hash *mc_hash = &efx->multicast_hash;
2369
2370         /* Broadcast packets go through the multicast hash filter.
2371          * ether_crc_le() of the broadcast address is 0xbe2612ff
2372          * so we always add bit 0xff to the mask.
2373          */
2374         set_bit_le(0xff, mc_hash->byte);
2375
2376         falcon_write(efx, &mc_hash->oword[0], MAC_MCAST_HASH_REG0_KER);
2377         falcon_write(efx, &mc_hash->oword[1], MAC_MCAST_HASH_REG1_KER);
2378 }
2379
2380
2381 /**************************************************************************
2382  *
2383  * Falcon test code
2384  *
2385  **************************************************************************/
2386
2387 int falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
2388 {
2389         struct falcon_nvconfig *nvconfig;
2390         struct efx_spi_device *spi;
2391         void *region;
2392         int rc, magic_num, struct_ver;
2393         __le16 *word, *limit;
2394         u32 csum;
2395
2396         spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom;
2397         if (!spi)
2398                 return -EINVAL;
2399
2400         region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL);
2401         if (!region)
2402                 return -ENOMEM;
2403         nvconfig = region + NVCONFIG_OFFSET;
2404
2405         mutex_lock(&efx->spi_lock);
2406         rc = falcon_spi_read(spi, 0, FALCON_NVCONFIG_END, NULL, region);
2407         mutex_unlock(&efx->spi_lock);
2408         if (rc) {
2409                 EFX_ERR(efx, "Failed to read %s\n",
2410                         efx->spi_flash ? "flash" : "EEPROM");
2411                 rc = -EIO;
2412                 goto out;
2413         }
2414
2415         magic_num = le16_to_cpu(nvconfig->board_magic_num);
2416         struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
2417
2418         rc = -EINVAL;
2419         if (magic_num != NVCONFIG_BOARD_MAGIC_NUM) {
2420                 EFX_ERR(efx, "NVRAM bad magic 0x%x\n", magic_num);
2421                 goto out;
2422         }
2423         if (struct_ver < 2) {
2424                 EFX_ERR(efx, "NVRAM has ancient version 0x%x\n", struct_ver);
2425                 goto out;
2426         } else if (struct_ver < 4) {
2427                 word = &nvconfig->board_magic_num;
2428                 limit = (__le16 *) (nvconfig + 1);
2429         } else {
2430                 word = region;
2431                 limit = region + FALCON_NVCONFIG_END;
2432         }
2433         for (csum = 0; word < limit; ++word)
2434                 csum += le16_to_cpu(*word);
2435
2436         if (~csum & 0xffff) {
2437                 EFX_ERR(efx, "NVRAM has incorrect checksum\n");
2438                 goto out;
2439         }
2440
2441         rc = 0;
2442         if (nvconfig_out)
2443                 memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig));
2444
2445  out:
2446         kfree(region);
2447         return rc;
2448 }
2449
2450 /* Registers tested in the falcon register test */
2451 static struct {
2452         unsigned address;
2453         efx_oword_t mask;
2454 } efx_test_registers[] = {
2455         { ADR_REGION_REG_KER,
2456           EFX_OWORD32(0x0001FFFF, 0x0001FFFF, 0x0001FFFF, 0x0001FFFF) },
2457         { RX_CFG_REG_KER,
2458           EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
2459         { TX_CFG_REG_KER,
2460           EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
2461         { TX_CFG2_REG_KER,
2462           EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
2463         { MAC0_CTRL_REG_KER,
2464           EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
2465         { SRM_TX_DC_CFG_REG_KER,
2466           EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
2467         { RX_DC_CFG_REG_KER,
2468           EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
2469         { RX_DC_PF_WM_REG_KER,
2470           EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
2471         { DP_CTRL_REG,
2472           EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
2473         { GM_CFG2_REG,
2474           EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) },
2475         { GMF_CFG0_REG,
2476           EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) },
2477         { XM_GLB_CFG_REG,
2478           EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
2479         { XM_TX_CFG_REG,
2480           EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
2481         { XM_RX_CFG_REG,
2482           EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
2483         { XM_RX_PARAM_REG,
2484           EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
2485         { XM_FC_REG,
2486           EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
2487         { XM_ADR_LO_REG,
2488           EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
2489         { XX_SD_CTL_REG,
2490           EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
2491 };
2492
2493 static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b,
2494                                      const efx_oword_t *mask)
2495 {
2496         return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) ||
2497                 ((a->u64[1] ^ b->u64[1]) & mask->u64[1]);
2498 }
2499
2500 int falcon_test_registers(struct efx_nic *efx)
2501 {
2502         unsigned address = 0, i, j;
2503         efx_oword_t mask, imask, original, reg, buf;
2504
2505         /* Falcon should be in loopback to isolate the XMAC from the PHY */
2506         WARN_ON(!LOOPBACK_INTERNAL(efx));
2507
2508         for (i = 0; i < ARRAY_SIZE(efx_test_registers); ++i) {
2509                 address = efx_test_registers[i].address;
2510                 mask = imask = efx_test_registers[i].mask;
2511                 EFX_INVERT_OWORD(imask);
2512
2513                 falcon_read(efx, &original, address);
2514
2515                 /* bit sweep on and off */
2516                 for (j = 0; j < 128; j++) {
2517                         if (!EFX_EXTRACT_OWORD32(mask, j, j))
2518                                 continue;
2519
2520                         /* Test this testable bit can be set in isolation */
2521                         EFX_AND_OWORD(reg, original, mask);
2522                         EFX_SET_OWORD32(reg, j, j, 1);
2523
2524                         falcon_write(efx, &reg, address);
2525                         falcon_read(efx, &buf, address);
2526
2527                         if (efx_masked_compare_oword(&reg, &buf, &mask))
2528                                 goto fail;
2529
2530                         /* Test this testable bit can be cleared in isolation */
2531                         EFX_OR_OWORD(reg, original, mask);
2532                         EFX_SET_OWORD32(reg, j, j, 0);
2533
2534                         falcon_write(efx, &reg, address);
2535                         falcon_read(efx, &buf, address);
2536
2537                         if (efx_masked_compare_oword(&reg, &buf, &mask))
2538                                 goto fail;
2539                 }
2540
2541                 falcon_write(efx, &original, address);
2542         }
2543
2544         return 0;
2545
2546 fail:
2547         EFX_ERR(efx, "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT
2548                 " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg),
2549                 EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask));
2550         return -EIO;
2551 }
2552
2553 /**************************************************************************
2554  *
2555  * Device reset
2556  *
2557  **************************************************************************
2558  */
2559
2560 /* Resets NIC to known state.  This routine must be called in process
2561  * context and is allowed to sleep. */
2562 int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2563 {
2564         struct falcon_nic_data *nic_data = efx->nic_data;
2565         efx_oword_t glb_ctl_reg_ker;
2566         int rc;
2567
2568         EFX_LOG(efx, "performing hardware reset (%d)\n", method);
2569
2570         /* Initiate device reset */
2571         if (method == RESET_TYPE_WORLD) {
2572                 rc = pci_save_state(efx->pci_dev);
2573                 if (rc) {
2574                         EFX_ERR(efx, "failed to backup PCI state of primary "
2575                                 "function prior to hardware reset\n");
2576                         goto fail1;
2577                 }
2578                 if (FALCON_IS_DUAL_FUNC(efx)) {
2579                         rc = pci_save_state(nic_data->pci_dev2);
2580                         if (rc) {
2581                                 EFX_ERR(efx, "failed to backup PCI state of "
2582                                         "secondary function prior to "
2583                                         "hardware reset\n");
2584                                 goto fail2;
2585                         }
2586                 }
2587
2588                 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
2589                                      EXT_PHY_RST_DUR, 0x7,
2590                                      SWRST, 1);
2591         } else {
2592                 int reset_phy = (method == RESET_TYPE_INVISIBLE ?
2593                                  EXCLUDE_FROM_RESET : 0);
2594
2595                 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
2596                                      EXT_PHY_RST_CTL, reset_phy,
2597                                      PCIE_CORE_RST_CTL, EXCLUDE_FROM_RESET,
2598                                      PCIE_NSTCK_RST_CTL, EXCLUDE_FROM_RESET,
2599                                      PCIE_SD_RST_CTL, EXCLUDE_FROM_RESET,
2600                                      EE_RST_CTL, EXCLUDE_FROM_RESET,
2601                                      EXT_PHY_RST_DUR, 0x7 /* 10ms */,
2602                                      SWRST, 1);
2603         }
2604         falcon_write(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER);
2605
2606         EFX_LOG(efx, "waiting for hardware reset\n");
2607         schedule_timeout_uninterruptible(HZ / 20);
2608
2609         /* Restore PCI configuration if needed */
2610         if (method == RESET_TYPE_WORLD) {
2611                 if (FALCON_IS_DUAL_FUNC(efx)) {
2612                         rc = pci_restore_state(nic_data->pci_dev2);
2613                         if (rc) {
2614                                 EFX_ERR(efx, "failed to restore PCI config for "
2615                                         "the secondary function\n");
2616                                 goto fail3;
2617                         }
2618                 }
2619                 rc = pci_restore_state(efx->pci_dev);
2620                 if (rc) {
2621                         EFX_ERR(efx, "failed to restore PCI config for the "
2622                                 "primary function\n");
2623                         goto fail4;
2624                 }
2625                 EFX_LOG(efx, "successfully restored PCI config\n");
2626         }
2627
2628         /* Assert that reset complete */
2629         falcon_read(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER);
2630         if (EFX_OWORD_FIELD(glb_ctl_reg_ker, SWRST) != 0) {
2631                 rc = -ETIMEDOUT;
2632                 EFX_ERR(efx, "timed out waiting for hardware reset\n");
2633                 goto fail5;
2634         }
2635         EFX_LOG(efx, "hardware reset complete\n");
2636
2637         return 0;
2638
2639         /* pci_save_state() and pci_restore_state() MUST be called in pairs */
2640 fail2:
2641 fail3:
2642         pci_restore_state(efx->pci_dev);
2643 fail1:
2644 fail4:
2645 fail5:
2646         return rc;
2647 }
2648
2649 /* Zeroes out the SRAM contents.  This routine must be called in
2650  * process context and is allowed to sleep.
2651  */
2652 static int falcon_reset_sram(struct efx_nic *efx)
2653 {
2654         efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
2655         int count;
2656
2657         /* Set the SRAM wake/sleep GPIO appropriately. */
2658         falcon_read(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER);
2659         EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OEN, 1);
2660         EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OUT, 1);
2661         falcon_write(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER);
2662
2663         /* Initiate SRAM reset */
2664         EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
2665                              SRAM_OOB_BT_INIT_EN, 1,
2666                              SRM_NUM_BANKS_AND_BANK_SIZE, 0);
2667         falcon_write(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER);
2668
2669         /* Wait for SRAM reset to complete */
2670         count = 0;
2671         do {
2672                 EFX_LOG(efx, "waiting for SRAM reset (attempt %d)...\n", count);
2673
2674                 /* SRAM reset is slow; expect around 16ms */
2675                 schedule_timeout_uninterruptible(HZ / 50);
2676
2677                 /* Check for reset complete */
2678                 falcon_read(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER);
2679                 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, SRAM_OOB_BT_INIT_EN)) {
2680                         EFX_LOG(efx, "SRAM reset complete\n");
2681
2682                         return 0;
2683                 }
2684         } while (++count < 20); /* wait upto 0.4 sec */
2685
2686         EFX_ERR(efx, "timed out waiting for SRAM reset\n");
2687         return -ETIMEDOUT;
2688 }
2689
2690 static int falcon_spi_device_init(struct efx_nic *efx,
2691                                   struct efx_spi_device **spi_device_ret,
2692                                   unsigned int device_id, u32 device_type)
2693 {
2694         struct efx_spi_device *spi_device;
2695
2696         if (device_type != 0) {
2697                 spi_device = kzalloc(sizeof(*spi_device), GFP_KERNEL);
2698                 if (!spi_device)
2699                         return -ENOMEM;
2700                 spi_device->device_id = device_id;
2701                 spi_device->size =
2702                         1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
2703                 spi_device->addr_len =
2704                         SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
2705                 spi_device->munge_address = (spi_device->size == 1 << 9 &&
2706                                              spi_device->addr_len == 1);
2707                 spi_device->erase_command =
2708                         SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD);
2709                 spi_device->erase_size =
2710                         1 << SPI_DEV_TYPE_FIELD(device_type,
2711                                                 SPI_DEV_TYPE_ERASE_SIZE);
2712                 spi_device->block_size =
2713                         1 << SPI_DEV_TYPE_FIELD(device_type,
2714                                                 SPI_DEV_TYPE_BLOCK_SIZE);
2715
2716                 spi_device->efx = efx;
2717         } else {
2718                 spi_device = NULL;
2719         }
2720
2721         kfree(*spi_device_ret);
2722         *spi_device_ret = spi_device;
2723         return 0;
2724 }
2725
2726
2727 static void falcon_remove_spi_devices(struct efx_nic *efx)
2728 {
2729         kfree(efx->spi_eeprom);
2730         efx->spi_eeprom = NULL;
2731         kfree(efx->spi_flash);
2732         efx->spi_flash = NULL;
2733 }
2734
2735 /* Extract non-volatile configuration */
2736 static int falcon_probe_nvconfig(struct efx_nic *efx)
2737 {
2738         struct falcon_nvconfig *nvconfig;
2739         int board_rev;
2740         int rc;
2741
2742         nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
2743         if (!nvconfig)
2744                 return -ENOMEM;
2745
2746         rc = falcon_read_nvram(efx, nvconfig);
2747         if (rc == -EINVAL) {
2748                 EFX_ERR(efx, "NVRAM is invalid therefore using defaults\n");
2749                 efx->phy_type = PHY_TYPE_NONE;
2750                 efx->mii.phy_id = PHY_ADDR_INVALID;
2751                 board_rev = 0;
2752                 rc = 0;
2753         } else if (rc) {
2754                 goto fail1;
2755         } else {
2756                 struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2;
2757                 struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3;
2758
2759                 efx->phy_type = v2->port0_phy_type;
2760                 efx->mii.phy_id = v2->port0_phy_addr;
2761                 board_rev = le16_to_cpu(v2->board_revision);
2762
2763                 if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
2764                         __le32 fl = v3->spi_device_type[EE_SPI_FLASH];
2765                         __le32 ee = v3->spi_device_type[EE_SPI_EEPROM];
2766                         rc = falcon_spi_device_init(efx, &efx->spi_flash,
2767                                                     EE_SPI_FLASH,
2768                                                     le32_to_cpu(fl));
2769                         if (rc)
2770                                 goto fail2;
2771                         rc = falcon_spi_device_init(efx, &efx->spi_eeprom,
2772                                                     EE_SPI_EEPROM,
2773                                                     le32_to_cpu(ee));
2774                         if (rc)
2775                                 goto fail2;
2776                 }
2777         }
2778
2779         /* Read the MAC addresses */
2780         memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
2781
2782         EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mii.phy_id);
2783
2784         efx_set_board_info(efx, board_rev);
2785
2786         kfree(nvconfig);
2787         return 0;
2788
2789  fail2:
2790         falcon_remove_spi_devices(efx);
2791  fail1:
2792         kfree(nvconfig);
2793         return rc;
2794 }
2795
2796 /* Probe the NIC variant (revision, ASIC vs FPGA, function count, port
2797  * count, port speed).  Set workaround and feature flags accordingly.
2798  */
2799 static int falcon_probe_nic_variant(struct efx_nic *efx)
2800 {
2801         efx_oword_t altera_build;
2802         efx_oword_t nic_stat;
2803
2804         falcon_read(efx, &altera_build, ALTERA_BUILD_REG_KER);
2805         if (EFX_OWORD_FIELD(altera_build, VER_ALL)) {
2806                 EFX_ERR(efx, "Falcon FPGA not supported\n");
2807                 return -ENODEV;
2808         }
2809
2810         falcon_read(efx, &nic_stat, NIC_STAT_REG);
2811
2812         switch (falcon_rev(efx)) {
2813         case FALCON_REV_A0:
2814         case 0xff:
2815                 EFX_ERR(efx, "Falcon rev A0 not supported\n");
2816                 return -ENODEV;
2817
2818         case FALCON_REV_A1:
2819                 if (EFX_OWORD_FIELD(nic_stat, STRAP_PCIE) == 0) {
2820                         EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n");
2821                         return -ENODEV;
2822                 }
2823                 break;
2824
2825         case FALCON_REV_B0:
2826                 break;
2827
2828         default:
2829                 EFX_ERR(efx, "Unknown Falcon rev %d\n", falcon_rev(efx));
2830                 return -ENODEV;
2831         }
2832
2833         /* Initial assumed speed */
2834         efx->link_speed = EFX_OWORD_FIELD(nic_stat, STRAP_10G) ? 10000 : 1000;
2835
2836         return 0;
2837 }
2838
2839 /* Probe all SPI devices on the NIC */
2840 static void falcon_probe_spi_devices(struct efx_nic *efx)
2841 {
2842         efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
2843         int boot_dev;
2844
2845         falcon_read(efx, &gpio_ctl, GPIO_CTL_REG_KER);
2846         falcon_read(efx, &nic_stat, NIC_STAT_REG);
2847         falcon_read(efx, &ee_vpd_cfg, EE_VPD_CFG_REG_KER);
2848
2849         if (EFX_OWORD_FIELD(gpio_ctl, BOOTED_USING_NVDEVICE)) {
2850                 boot_dev = (EFX_OWORD_FIELD(nic_stat, SF_PRST) ?
2851                             EE_SPI_FLASH : EE_SPI_EEPROM);
2852                 EFX_LOG(efx, "Booted from %s\n",
2853                         boot_dev == EE_SPI_FLASH ? "flash" : "EEPROM");
2854         } else {
2855                 /* Disable VPD and set clock dividers to safe
2856                  * values for initial programming. */
2857                 boot_dev = -1;
2858                 EFX_LOG(efx, "Booted from internal ASIC settings;"
2859                         " setting SPI config\n");
2860                 EFX_POPULATE_OWORD_3(ee_vpd_cfg, EE_VPD_EN, 0,
2861                                      /* 125 MHz / 7 ~= 20 MHz */
2862                                      EE_SF_CLOCK_DIV, 7,
2863                                      /* 125 MHz / 63 ~= 2 MHz */
2864                                      EE_EE_CLOCK_DIV, 63);
2865                 falcon_write(efx, &ee_vpd_cfg, EE_VPD_CFG_REG_KER);
2866         }
2867
2868         if (boot_dev == EE_SPI_FLASH)
2869                 falcon_spi_device_init(efx, &efx->spi_flash, EE_SPI_FLASH,
2870                                        default_flash_type);
2871         if (boot_dev == EE_SPI_EEPROM)
2872                 falcon_spi_device_init(efx, &efx->spi_eeprom, EE_SPI_EEPROM,
2873                                        large_eeprom_type);
2874 }
2875
2876 int falcon_probe_nic(struct efx_nic *efx)
2877 {
2878         struct falcon_nic_data *nic_data;
2879         int rc;
2880
2881         /* Allocate storage for hardware specific data */
2882         nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
2883         if (!nic_data)
2884                 return -ENOMEM;
2885         efx->nic_data = nic_data;
2886
2887         /* Determine number of ports etc. */
2888         rc = falcon_probe_nic_variant(efx);
2889         if (rc)
2890                 goto fail1;
2891
2892         /* Probe secondary function if expected */
2893         if (FALCON_IS_DUAL_FUNC(efx)) {
2894                 struct pci_dev *dev = pci_dev_get(efx->pci_dev);
2895
2896                 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
2897                                              dev))) {
2898                         if (dev->bus == efx->pci_dev->bus &&
2899                             dev->devfn == efx->pci_dev->devfn + 1) {
2900                                 nic_data->pci_dev2 = dev;
2901                                 break;
2902                         }
2903                 }
2904                 if (!nic_data->pci_dev2) {
2905                         EFX_ERR(efx, "failed to find secondary function\n");
2906                         rc = -ENODEV;
2907                         goto fail2;
2908                 }
2909         }
2910
2911         /* Now we can reset the NIC */
2912         rc = falcon_reset_hw(efx, RESET_TYPE_ALL);
2913         if (rc) {
2914                 EFX_ERR(efx, "failed to reset NIC\n");
2915                 goto fail3;
2916         }
2917
2918         /* Allocate memory for INT_KER */
2919         rc = falcon_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
2920         if (rc)
2921                 goto fail4;
2922         BUG_ON(efx->irq_status.dma_addr & 0x0f);
2923
2924         EFX_LOG(efx, "INT_KER at %llx (virt %p phys %lx)\n",
2925                 (unsigned long long)efx->irq_status.dma_addr,
2926                 efx->irq_status.addr, virt_to_phys(efx->irq_status.addr));
2927
2928         falcon_probe_spi_devices(efx);
2929
2930         /* Read in the non-volatile configuration */
2931         rc = falcon_probe_nvconfig(efx);
2932         if (rc)
2933                 goto fail5;
2934
2935         /* Initialise I2C adapter */
2936         efx->i2c_adap.owner = THIS_MODULE;
2937         nic_data->i2c_data = falcon_i2c_bit_operations;
2938         nic_data->i2c_data.data = efx;
2939         efx->i2c_adap.algo_data = &nic_data->i2c_data;
2940         efx->i2c_adap.dev.parent = &efx->pci_dev->dev;
2941         strlcpy(efx->i2c_adap.name, "SFC4000 GPIO", sizeof(efx->i2c_adap.name));
2942         rc = i2c_bit_add_bus(&efx->i2c_adap);
2943         if (rc)
2944                 goto fail5;
2945
2946         return 0;
2947
2948  fail5:
2949         falcon_remove_spi_devices(efx);
2950         falcon_free_buffer(efx, &efx->irq_status);
2951  fail4:
2952  fail3:
2953         if (nic_data->pci_dev2) {
2954                 pci_dev_put(nic_data->pci_dev2);
2955                 nic_data->pci_dev2 = NULL;
2956         }
2957  fail2:
2958  fail1:
2959         kfree(efx->nic_data);
2960         return rc;
2961 }
2962
2963 /* This call performs hardware-specific global initialisation, such as
2964  * defining the descriptor cache sizes and number of RSS channels.
2965  * It does not set up any buffers, descriptor rings or event queues.
2966  */
2967 int falcon_init_nic(struct efx_nic *efx)
2968 {
2969         efx_oword_t temp;
2970         unsigned thresh;
2971         int rc;
2972
2973         /* Use on-chip SRAM */
2974         falcon_read(efx, &temp, NIC_STAT_REG);
2975         EFX_SET_OWORD_FIELD(temp, ONCHIP_SRAM, 1);
2976         falcon_write(efx, &temp, NIC_STAT_REG);
2977
2978         /* Set the source of the GMAC clock */
2979         if (falcon_rev(efx) == FALCON_REV_B0) {
2980                 falcon_read(efx, &temp, GPIO_CTL_REG_KER);
2981                 EFX_SET_OWORD_FIELD(temp, GPIO_USE_NIC_CLK, true);
2982                 falcon_write(efx, &temp, GPIO_CTL_REG_KER);
2983         }
2984
2985         /* Set buffer table mode */
2986         EFX_POPULATE_OWORD_1(temp, BUF_TBL_MODE, BUF_TBL_MODE_FULL);
2987         falcon_write(efx, &temp, BUF_TBL_CFG_REG_KER);
2988
2989         rc = falcon_reset_sram(efx);
2990         if (rc)
2991                 return rc;
2992
2993         /* Set positions of descriptor caches in SRAM. */
2994         EFX_POPULATE_OWORD_1(temp, SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8);
2995         falcon_write(efx, &temp, SRM_TX_DC_CFG_REG_KER);
2996         EFX_POPULATE_OWORD_1(temp, SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8);
2997         falcon_write(efx, &temp, SRM_RX_DC_CFG_REG_KER);
2998
2999         /* Set TX descriptor cache size. */
3000         BUILD_BUG_ON(TX_DC_ENTRIES != (16 << TX_DC_ENTRIES_ORDER));
3001         EFX_POPULATE_OWORD_1(temp, TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
3002         falcon_write(efx, &temp, TX_DC_CFG_REG_KER);
3003
3004         /* Set RX descriptor cache size.  Set low watermark to size-8, as
3005          * this allows most efficient prefetching.
3006          */
3007         BUILD_BUG_ON(RX_DC_ENTRIES != (16 << RX_DC_ENTRIES_ORDER));
3008         EFX_POPULATE_OWORD_1(temp, RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
3009         falcon_write(efx, &temp, RX_DC_CFG_REG_KER);
3010         EFX_POPULATE_OWORD_1(temp, RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
3011         falcon_write(efx, &temp, RX_DC_PF_WM_REG_KER);
3012
3013         /* Clear the parity enables on the TX data fifos as
3014          * they produce false parity errors because of timing issues
3015          */
3016         if (EFX_WORKAROUND_5129(efx)) {
3017                 falcon_read(efx, &temp, SPARE_REG_KER);
3018                 EFX_SET_OWORD_FIELD(temp, MEM_PERR_EN_TX_DATA, 0);
3019                 falcon_write(efx, &temp, SPARE_REG_KER);
3020         }
3021
3022         /* Enable all the genuinely fatal interrupts.  (They are still
3023          * masked by the overall interrupt mask, controlled by
3024          * falcon_interrupts()).
3025          *
3026          * Note: All other fatal interrupts are enabled
3027          */
3028         EFX_POPULATE_OWORD_3(temp,
3029                              ILL_ADR_INT_KER_EN, 1,
3030                              RBUF_OWN_INT_KER_EN, 1,
3031                              TBUF_OWN_INT_KER_EN, 1);
3032         EFX_INVERT_OWORD(temp);
3033         falcon_write(efx, &temp, FATAL_INTR_REG_KER);
3034
3035         if (EFX_WORKAROUND_7244(efx)) {
3036                 falcon_read(efx, &temp, RX_FILTER_CTL_REG);
3037                 EFX_SET_OWORD_FIELD(temp, UDP_FULL_SRCH_LIMIT, 8);
3038                 EFX_SET_OWORD_FIELD(temp, UDP_WILD_SRCH_LIMIT, 8);
3039                 EFX_SET_OWORD_FIELD(temp, TCP_FULL_SRCH_LIMIT, 8);
3040                 EFX_SET_OWORD_FIELD(temp, TCP_WILD_SRCH_LIMIT, 8);
3041                 falcon_write(efx, &temp, RX_FILTER_CTL_REG);
3042         }
3043
3044         falcon_setup_rss_indir_table(efx);
3045
3046         /* Setup RX.  Wait for descriptor is broken and must
3047          * be disabled.  RXDP recovery shouldn't be needed, but is.
3048          */
3049         falcon_read(efx, &temp, RX_SELF_RST_REG_KER);
3050         EFX_SET_OWORD_FIELD(temp, RX_NODESC_WAIT_DIS, 1);
3051         EFX_SET_OWORD_FIELD(temp, RX_RECOVERY_EN, 1);
3052         if (EFX_WORKAROUND_5583(efx))
3053                 EFX_SET_OWORD_FIELD(temp, RX_ISCSI_DIS, 1);
3054         falcon_write(efx, &temp, RX_SELF_RST_REG_KER);
3055
3056         /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
3057          * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
3058          */
3059         falcon_read(efx, &temp, TX_CFG2_REG_KER);
3060         EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER, 0xfe);
3061         EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER_EN, 1);
3062         EFX_SET_OWORD_FIELD(temp, TX_ONE_PKT_PER_Q, 1);
3063         EFX_SET_OWORD_FIELD(temp, TX_CSR_PUSH_EN, 0);
3064         EFX_SET_OWORD_FIELD(temp, TX_DIS_NON_IP_EV, 1);
3065         /* Enable SW_EV to inherit in char driver - assume harmless here */
3066         EFX_SET_OWORD_FIELD(temp, TX_SW_EV_EN, 1);
3067         /* Prefetch threshold 2 => fetch when descriptor cache half empty */
3068         EFX_SET_OWORD_FIELD(temp, TX_PREF_THRESHOLD, 2);
3069         /* Squash TX of packets of 16 bytes or less */
3070         if (falcon_rev(efx) >= FALCON_REV_B0 && EFX_WORKAROUND_9141(efx))
3071                 EFX_SET_OWORD_FIELD(temp, TX_FLUSH_MIN_LEN_EN_B0, 1);
3072         falcon_write(efx, &temp, TX_CFG2_REG_KER);
3073
3074         /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
3075          * descriptors (which is bad).
3076          */
3077         falcon_read(efx, &temp, TX_CFG_REG_KER);
3078         EFX_SET_OWORD_FIELD(temp, TX_NO_EOP_DISC_EN, 0);
3079         falcon_write(efx, &temp, TX_CFG_REG_KER);
3080
3081         /* RX config */
3082         falcon_read(efx, &temp, RX_CFG_REG_KER);
3083         EFX_SET_OWORD_FIELD_VER(efx, temp, RX_DESC_PUSH_EN, 0);
3084         if (EFX_WORKAROUND_7575(efx))
3085                 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_USR_BUF_SIZE,
3086                                         (3 * 4096) / 32);
3087         if (falcon_rev(efx) >= FALCON_REV_B0)
3088                 EFX_SET_OWORD_FIELD(temp, RX_INGR_EN_B0, 1);
3089
3090         /* RX FIFO flow control thresholds */
3091         thresh = ((rx_xon_thresh_bytes >= 0) ?
3092                   rx_xon_thresh_bytes : efx->type->rx_xon_thresh);
3093         EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_MAC_TH, thresh / 256);
3094         thresh = ((rx_xoff_thresh_bytes >= 0) ?
3095                   rx_xoff_thresh_bytes : efx->type->rx_xoff_thresh);
3096         EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_MAC_TH, thresh / 256);
3097         /* RX control FIFO thresholds [32 entries] */
3098         EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_TX_TH, 20);
3099         EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_TX_TH, 25);
3100         falcon_write(efx, &temp, RX_CFG_REG_KER);
3101
3102         /* Set destination of both TX and RX Flush events */
3103         if (falcon_rev(efx) >= FALCON_REV_B0) {
3104                 EFX_POPULATE_OWORD_1(temp, FLS_EVQ_ID, 0);
3105                 falcon_write(efx, &temp, DP_CTRL_REG);
3106         }
3107
3108         return 0;
3109 }
3110
3111 void falcon_remove_nic(struct efx_nic *efx)
3112 {
3113         struct falcon_nic_data *nic_data = efx->nic_data;
3114         int rc;
3115
3116         rc = i2c_del_adapter(&efx->i2c_adap);
3117         BUG_ON(rc);
3118
3119         falcon_remove_spi_devices(efx);
3120         falcon_free_buffer(efx, &efx->irq_status);
3121
3122         falcon_reset_hw(efx, RESET_TYPE_ALL);
3123
3124         /* Release the second function after the reset */
3125         if (nic_data->pci_dev2) {
3126                 pci_dev_put(nic_data->pci_dev2);
3127                 nic_data->pci_dev2 = NULL;
3128         }
3129
3130         /* Tear down the private nic state */
3131         kfree(efx->nic_data);
3132         efx->nic_data = NULL;
3133 }
3134
3135 void falcon_update_nic_stats(struct efx_nic *efx)
3136 {
3137         efx_oword_t cnt;
3138
3139         falcon_read(efx, &cnt, RX_NODESC_DROP_REG_KER);
3140         efx->n_rx_nodesc_drop_cnt += EFX_OWORD_FIELD(cnt, RX_NODESC_DROP_CNT);
3141 }
3142
3143 /**************************************************************************
3144  *
3145  * Revision-dependent attributes used by efx.c
3146  *
3147  **************************************************************************
3148  */
3149
3150 struct efx_nic_type falcon_a_nic_type = {
3151         .mem_bar = 2,
3152         .mem_map_size = 0x20000,
3153         .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_A1,
3154         .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_A1,
3155         .buf_tbl_base = BUF_TBL_KER_A1,
3156         .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_A1,
3157         .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_A1,
3158         .txd_ring_mask = FALCON_TXD_RING_MASK,
3159         .rxd_ring_mask = FALCON_RXD_RING_MASK,
3160         .evq_size = FALCON_EVQ_SIZE,
3161         .max_dma_mask = FALCON_DMA_MASK,
3162         .tx_dma_mask = FALCON_TX_DMA_MASK,
3163         .bug5391_mask = 0xf,
3164         .rx_xoff_thresh = 2048,
3165         .rx_xon_thresh = 512,
3166         .rx_buffer_padding = 0x24,
3167         .max_interrupt_mode = EFX_INT_MODE_MSI,
3168         .phys_addr_channels = 4,
3169 };
3170
3171 struct efx_nic_type falcon_b_nic_type = {
3172         .mem_bar = 2,
3173         /* Map everything up to and including the RSS indirection
3174          * table.  Don't map MSI-X table, MSI-X PBA since Linux
3175          * requires that they not be mapped.  */
3176         .mem_map_size = RX_RSS_INDIR_TBL_B0 + 0x800,
3177         .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_B0,
3178         .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_B0,
3179         .buf_tbl_base = BUF_TBL_KER_B0,
3180         .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_B0,
3181         .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_B0,
3182         .txd_ring_mask = FALCON_TXD_RING_MASK,
3183         .rxd_ring_mask = FALCON_RXD_RING_MASK,
3184         .evq_size = FALCON_EVQ_SIZE,
3185         .max_dma_mask = FALCON_DMA_MASK,
3186         .tx_dma_mask = FALCON_TX_DMA_MASK,
3187         .bug5391_mask = 0,
3188         .rx_xoff_thresh = 54272, /* ~80Kb - 3*max MTU */
3189         .rx_xon_thresh = 27648,  /* ~3*max MTU */
3190         .rx_buffer_padding = 0,
3191         .max_interrupt_mode = EFX_INT_MODE_MSIX,
3192         .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
3193                                    * interrupt handler only supports 32
3194                                    * channels */
3195 };
3196