drivers/net/sb1250-mac.c

   1 /*
   2  * Copyright (C) 2001,2002,2003,2004 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version 2
   7  * of the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  17  *
  18  *
  19  * This driver is designed for the Broadcom SiByte SOC built-in
  20  * Ethernet controllers. Written by Mitch Lichtenberg at Broadcom Corp.
  21  */
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/string.h>
  25 #include <linux/timer.h>
  26 #include <linux/errno.h>
  27 #include <linux/ioport.h>
  28 #include <linux/slab.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/init.h>
  34 #include <linux/bitops.h>
  35 #include <asm/processor.h>              /* Processor type for cache alignment. */
  36 #include <asm/io.h>
  37 #include <asm/cache.h>
  38
  39 /* This is only here until the firmware is ready.  In that case,
  40    the firmware leaves the ethernet address in the register for us. */
  41 #ifdef CONFIG_SIBYTE_STANDALONE
  42 #define SBMAC_ETH0_HWADDR "40:00:00:00:01:00"
  43 #define SBMAC_ETH1_HWADDR "40:00:00:00:01:01"
  44 #define SBMAC_ETH2_HWADDR "40:00:00:00:01:02"
  45 #define SBMAC_ETH3_HWADDR "40:00:00:00:01:03"
  46 #endif
  47
  48
  49 /* These identify the driver base version and may not be removed. */
  50 #if 0
  51 static char version1[] __devinitdata =
  52 "sb1250-mac.c:1.00 1/11/2001 Written by Mitch Lichtenberg\n";
  53 #endif
  54
  55
  56 /* Operational parameters that usually are not changed. */
  57
  58 #define CONFIG_SBMAC_COALESCE
  59
  60 #define MAX_UNITS 4             /* More are supported, limit only on options */
  61
  62 /* Time in jiffies before concluding the transmitter is hung. */
  63 #define TX_TIMEOUT  (2*HZ)
  64
  65
  66 MODULE_AUTHOR("Mitch Lichtenberg (Broadcom Corp.)");
  67 MODULE_DESCRIPTION("Broadcom SiByte SOC GB Ethernet driver");
  68
  69 /* A few user-configurable values which may be modified when a driver
  70    module is loaded. */
  71
  72 /* 1 normal messages, 0 quiet .. 7 verbose. */
  73 static int debug = 1;
  74 module_param(debug, int, S_IRUGO);
  75 MODULE_PARM_DESC(debug, "Debug messages");
  76
  77 /* mii status msgs */
  78 static int noisy_mii = 1;
  79 module_param(noisy_mii, int, S_IRUGO);
  80 MODULE_PARM_DESC(noisy_mii, "MII status messages");
  81
  82 /* Used to pass the media type, etc.
  83    Both 'options[]' and 'full_duplex[]' should exist for driver
  84    interoperability.
  85    The media type is usually passed in 'options[]'.
  86 */
  87 #ifdef MODULE
  88 static int options[MAX_UNITS] = {-1, -1, -1, -1};
  89 module_param_array(options, int, NULL, S_IRUGO);
  90 MODULE_PARM_DESC(options, "1-" __MODULE_STRING(MAX_UNITS));
  91
  92 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1};
  93 module_param_array(full_duplex, int, NULL, S_IRUGO);
  94 MODULE_PARM_DESC(full_duplex, "1-" __MODULE_STRING(MAX_UNITS));
  95 #endif
  96
  97 #ifdef CONFIG_SBMAC_COALESCE
  98 static int int_pktcnt_tx = 255;
  99 module_param(int_pktcnt_tx, int, S_IRUGO);
 100 MODULE_PARM_DESC(int_pktcnt_tx, "TX packet count");
 101
 102 static int int_timeout_tx = 255;
 103 module_param(int_timeout_tx, int, S_IRUGO);
 104 MODULE_PARM_DESC(int_timeout_tx, "TX timeout value");
 105
 106 static int int_pktcnt_rx = 64;
 107 module_param(int_pktcnt_rx, int, S_IRUGO);
 108 MODULE_PARM_DESC(int_pktcnt_rx, "RX packet count");
 109
 110 static int int_timeout_rx = 64;
 111 module_param(int_timeout_rx, int, S_IRUGO);
 112 MODULE_PARM_DESC(int_timeout_rx, "RX timeout value");
 113 #endif
 114
 115 #include <asm/sibyte/sb1250.h>
 116 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
 117 #include <asm/sibyte/bcm1480_regs.h>
 118 #include <asm/sibyte/bcm1480_int.h>
 119 #define R_MAC_DMA_OODPKTLOST_RX R_MAC_DMA_OODPKTLOST
 120 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
 121 #include <asm/sibyte/sb1250_regs.h>
 122 #include <asm/sibyte/sb1250_int.h>
 123 #else
 124 #error invalid SiByte MAC configuation
 125 #endif
 126 #include <asm/sibyte/sb1250_scd.h>
 127 #include <asm/sibyte/sb1250_mac.h>
 128 #include <asm/sibyte/sb1250_dma.h>
 129
 130 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
 131 #define UNIT_INT(n)             (K_BCM1480_INT_MAC_0 + ((n) * 2))
 132 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
 133 #define UNIT_INT(n)             (K_INT_MAC_0 + (n))
 134 #else
 135 #error invalid SiByte MAC configuation
 136 #endif
 137
 138 /**********************************************************************
 139  *  Simple types
 140  ********************************************************************* */
 141
 142
 143 typedef enum { sbmac_speed_auto, sbmac_speed_10,
 144                sbmac_speed_100, sbmac_speed_1000 } sbmac_speed_t;
 145
 146 typedef enum { sbmac_duplex_auto, sbmac_duplex_half,
 147                sbmac_duplex_full } sbmac_duplex_t;
 148
 149 typedef enum { sbmac_fc_auto, sbmac_fc_disabled, sbmac_fc_frame,
 150                sbmac_fc_collision, sbmac_fc_carrier } sbmac_fc_t;
 151
 152 typedef enum { sbmac_state_uninit, sbmac_state_off, sbmac_state_on,
 153                sbmac_state_broken } sbmac_state_t;
 154
 155
 156 /**********************************************************************
 157  *  Macros
 158  ********************************************************************* */
 159
 160
 161 #define SBDMA_NEXTBUF(d,f) ((((d)->f+1) == (d)->sbdma_dscrtable_end) ? \
 162                           (d)->sbdma_dscrtable : (d)->f+1)
 163
 164
 165 #define NUMCACHEBLKS(x) (((x)+SMP_CACHE_BYTES-1)/SMP_CACHE_BYTES)
 166
 167 #define SBMAC_MAX_TXDESCR       256
 168 #define SBMAC_MAX_RXDESCR       256
 169
 170 #define ETHER_ALIGN     2
 171 #define ETHER_ADDR_LEN  6
 172 #define ENET_PACKET_SIZE        1518
 173 /*#define ENET_PACKET_SIZE      9216 */
 174
 175 /**********************************************************************
 176  *  DMA Descriptor structure
 177  ********************************************************************* */
 178
 179 typedef struct sbdmadscr_s {
 180         uint64_t  dscr_a;
 181         uint64_t  dscr_b;
 182 } sbdmadscr_t;
 183
 184 typedef unsigned long paddr_t;
 185
 186 /**********************************************************************
 187  *  DMA Controller structure
 188  ********************************************************************* */
 189
 190 typedef struct sbmacdma_s {
 191
 192         /*
 193          * This stuff is used to identify the channel and the registers
 194          * associated with it.
 195          */
 196
 197         struct sbmac_softc *sbdma_eth;      /* back pointer to associated MAC */
 198         int              sbdma_channel;     /* channel number */
 199         int              sbdma_txdir;       /* direction (1=transmit) */
 200         int              sbdma_maxdescr;    /* total # of descriptors in ring */
 201 #ifdef CONFIG_SBMAC_COALESCE
 202         int              sbdma_int_pktcnt;  /* # descriptors rx/tx before interrupt*/
 203         int              sbdma_int_timeout; /* # usec rx/tx interrupt */
 204 #endif
 205
 206         volatile void __iomem *sbdma_config0;   /* DMA config register 0 */
 207         volatile void __iomem *sbdma_config1;   /* DMA config register 1 */
 208         volatile void __iomem *sbdma_dscrbase;  /* Descriptor base address */
 209         volatile void __iomem *sbdma_dscrcnt;   /* Descriptor count register */
 210         volatile void __iomem *sbdma_curdscr;   /* current descriptor address */
 211         volatile void __iomem *sbdma_oodpktlost;/* pkt drop (rx only) */
 212
 213
 214         /*
 215          * This stuff is for maintenance of the ring
 216          */
 217
 218         sbdmadscr_t     *sbdma_dscrtable_unaligned;
 219         sbdmadscr_t     *sbdma_dscrtable;       /* base of descriptor table */
 220         sbdmadscr_t     *sbdma_dscrtable_end; /* end of descriptor table */
 221
 222         struct sk_buff **sbdma_ctxtable;    /* context table, one per descr */
 223
 224         paddr_t          sbdma_dscrtable_phys; /* and also the phys addr */
 225         sbdmadscr_t     *sbdma_addptr;  /* next dscr for sw to add */
 226         sbdmadscr_t     *sbdma_remptr;  /* next dscr for sw to remove */
 227 } sbmacdma_t;
 228
 229
 230 /**********************************************************************
 231  *  Ethernet softc structure
 232  ********************************************************************* */
 233
 234 struct sbmac_softc {
 235
 236         /*
 237          * Linux-specific things
 238          */
 239
 240         struct net_device *sbm_dev;             /* pointer to linux device */
 241         spinlock_t sbm_lock;            /* spin lock */
 242         struct timer_list sbm_timer;            /* for monitoring MII */
 243         struct net_device_stats sbm_stats;
 244         int sbm_devflags;                       /* current device flags */
 245
 246         int          sbm_phy_oldbmsr;
 247         int          sbm_phy_oldanlpar;
 248         int          sbm_phy_oldk1stsr;
 249         int          sbm_phy_oldlinkstat;
 250         int sbm_buffersize;
 251
 252         unsigned char sbm_phys[2];
 253
 254         /*
 255          * Controller-specific things
 256          */
 257
 258         void __iomem            *sbm_base;          /* MAC's base address */
 259         sbmac_state_t    sbm_state;         /* current state */
 260
 261         volatile void __iomem   *sbm_macenable; /* MAC Enable Register */
 262         volatile void __iomem   *sbm_maccfg;    /* MAC Configuration Register */
 263         volatile void __iomem   *sbm_fifocfg;   /* FIFO configuration register */
 264         volatile void __iomem   *sbm_framecfg;  /* Frame configuration register */
 265         volatile void __iomem   *sbm_rxfilter;  /* receive filter register */
 266         volatile void __iomem   *sbm_isr;       /* Interrupt status register */
 267         volatile void __iomem   *sbm_imr;       /* Interrupt mask register */
 268         volatile void __iomem   *sbm_mdio;      /* MDIO register */
 269
 270         sbmac_speed_t    sbm_speed;             /* current speed */
 271         sbmac_duplex_t   sbm_duplex;    /* current duplex */
 272         sbmac_fc_t       sbm_fc;                /* current flow control setting */
 273
 274         unsigned char    sbm_hwaddr[ETHER_ADDR_LEN];
 275
 276         sbmacdma_t       sbm_txdma;             /* for now, only use channel 0 */
 277         sbmacdma_t       sbm_rxdma;
 278         int              rx_hw_checksum;
 279         int              sbe_idx;
 280 };
 281
 282
 283 /**********************************************************************
 284  *  Externs
 285  ********************************************************************* */
 286
 287 /**********************************************************************
 288  *  Prototypes
 289  ********************************************************************* */
 290
 291 static void sbdma_initctx(sbmacdma_t *d,
 292                           struct sbmac_softc *s,
 293                           int chan,
 294                           int txrx,
 295                           int maxdescr);
 296 static void sbdma_channel_start(sbmacdma_t *d, int rxtx);
 297 static int sbdma_add_rcvbuffer(sbmacdma_t *d,struct sk_buff *m);
 298 static int sbdma_add_txbuffer(sbmacdma_t *d,struct sk_buff *m);
 299 static void sbdma_emptyring(sbmacdma_t *d);
 300 static void sbdma_fillring(sbmacdma_t *d);
 301 static int sbdma_rx_process(struct sbmac_softc *sc,sbmacdma_t *d, int work_to_do, int poll);
 302 static void sbdma_tx_process(struct sbmac_softc *sc,sbmacdma_t *d, int poll);
 303 static int sbmac_initctx(struct sbmac_softc *s);
 304 static void sbmac_channel_start(struct sbmac_softc *s);
 305 static void sbmac_channel_stop(struct sbmac_softc *s);
 306 static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *,sbmac_state_t);
 307 static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff);
 308 static uint64_t sbmac_addr2reg(unsigned char *ptr);
 309 static irqreturn_t sbmac_intr(int irq,void *dev_instance);
 310 static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev);
 311 static void sbmac_setmulti(struct sbmac_softc *sc);
 312 static int sbmac_init(struct net_device *dev, int idx);
 313 static int sbmac_set_speed(struct sbmac_softc *s,sbmac_speed_t speed);
 314 static int sbmac_set_duplex(struct sbmac_softc *s,sbmac_duplex_t duplex,sbmac_fc_t fc);
 315
 316 static int sbmac_open(struct net_device *dev);
 317 static void sbmac_timer(unsigned long data);
 318 static void sbmac_tx_timeout (struct net_device *dev);
 319 static struct net_device_stats *sbmac_get_stats(struct net_device *dev);
 320 static void sbmac_set_rx_mode(struct net_device *dev);
 321 static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 322 static int sbmac_close(struct net_device *dev);
 323 static int sbmac_poll(struct net_device *poll_dev, int *budget);
 324
 325 static int sbmac_mii_poll(struct sbmac_softc *s,int noisy);
 326 static int sbmac_mii_probe(struct net_device *dev);
 327
 328 static void sbmac_mii_sync(struct sbmac_softc *s);
 329 static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitcnt);
 330 static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx);
 331 static void sbmac_mii_write(struct sbmac_softc *s,int phyaddr,int regidx,
 332                             unsigned int regval);
 333
 334
 335 /**********************************************************************
 336  *  Globals
 337  ********************************************************************* */
 338
 339 static uint64_t sbmac_orig_hwaddr[MAX_UNITS];
 340
 341
 342 /**********************************************************************
 343  *  MDIO constants
 344  ********************************************************************* */
 345
 346 #define MII_COMMAND_START       0x01
 347 #define MII_COMMAND_READ        0x02
 348 #define MII_COMMAND_WRITE       0x01
 349 #define MII_COMMAND_ACK         0x02
 350
 351 #define BMCR_RESET     0x8000
 352 #define BMCR_LOOPBACK  0x4000
 353 #define BMCR_SPEED0    0x2000
 354 #define BMCR_ANENABLE  0x1000
 355 #define BMCR_POWERDOWN 0x0800
 356 #define BMCR_ISOLATE   0x0400
 357 #define BMCR_RESTARTAN 0x0200
 358 #define BMCR_DUPLEX    0x0100
 359 #define BMCR_COLTEST   0x0080
 360 #define BMCR_SPEED1    0x0040
 361 #define BMCR_SPEED1000  BMCR_SPEED1
 362 #define BMCR_SPEED100   BMCR_SPEED0
 363 #define BMCR_SPEED10    0
 364
 365 #define BMSR_100BT4     0x8000
 366 #define BMSR_100BT_FDX  0x4000
 367 #define BMSR_100BT_HDX  0x2000
 368 #define BMSR_10BT_FDX   0x1000
 369 #define BMSR_10BT_HDX   0x0800
 370 #define BMSR_100BT2_FDX 0x0400
 371 #define BMSR_100BT2_HDX 0x0200
 372 #define BMSR_1000BT_XSR 0x0100
 373 #define BMSR_PRESUP     0x0040
 374 #define BMSR_ANCOMPLT   0x0020
 375 #define BMSR_REMFAULT   0x0010
 376 #define BMSR_AUTONEG    0x0008
 377 #define BMSR_LINKSTAT   0x0004
 378 #define BMSR_JABDETECT  0x0002
 379 #define BMSR_EXTCAPAB   0x0001
 380
 381 #define PHYIDR1         0x2000
 382 #define PHYIDR2         0x5C60
 383
 384 #define ANAR_NP         0x8000
 385 #define ANAR_RF         0x2000
 386 #define ANAR_ASYPAUSE   0x0800
 387 #define ANAR_PAUSE      0x0400
 388 #define ANAR_T4         0x0200
 389 #define ANAR_TXFD       0x0100
 390 #define ANAR_TXHD       0x0080
 391 #define ANAR_10FD       0x0040
 392 #define ANAR_10HD       0x0020
 393 #define ANAR_PSB        0x0001
 394
 395 #define ANLPAR_NP       0x8000
 396 #define ANLPAR_ACK      0x4000
 397 #define ANLPAR_RF       0x2000
 398 #define ANLPAR_ASYPAUSE 0x0800
 399 #define ANLPAR_PAUSE    0x0400
 400 #define ANLPAR_T4       0x0200
 401 #define ANLPAR_TXFD     0x0100
 402 #define ANLPAR_TXHD     0x0080
 403 #define ANLPAR_10FD     0x0040
 404 #define ANLPAR_10HD     0x0020
 405 #define ANLPAR_PSB      0x0001  /* 802.3 */
 406
 407 #define ANER_PDF        0x0010
 408 #define ANER_LPNPABLE   0x0008
 409 #define ANER_NPABLE     0x0004
 410 #define ANER_PAGERX     0x0002
 411 #define ANER_LPANABLE   0x0001
 412
 413 #define ANNPTR_NP       0x8000
 414 #define ANNPTR_MP       0x2000
 415 #define ANNPTR_ACK2     0x1000
 416 #define ANNPTR_TOGTX    0x0800
 417 #define ANNPTR_CODE     0x0008
 418
 419 #define ANNPRR_NP       0x8000
 420 #define ANNPRR_MP       0x2000
 421 #define ANNPRR_ACK3     0x1000
 422 #define ANNPRR_TOGTX    0x0800
 423 #define ANNPRR_CODE     0x0008
 424
 425 #define K1TCR_TESTMODE  0x0000
 426 #define K1TCR_MSMCE     0x1000
 427 #define K1TCR_MSCV      0x0800
 428 #define K1TCR_RPTR      0x0400
 429 #define K1TCR_1000BT_FDX 0x200
 430 #define K1TCR_1000BT_HDX 0x100
 431
 432 #define K1STSR_MSMCFLT  0x8000
 433 #define K1STSR_MSCFGRES 0x4000
 434 #define K1STSR_LRSTAT   0x2000
 435 #define K1STSR_RRSTAT   0x1000
 436 #define K1STSR_LP1KFD   0x0800
 437 #define K1STSR_LP1KHD   0x0400
 438 #define K1STSR_LPASMDIR 0x0200
 439
 440 #define K1SCR_1KX_FDX   0x8000
 441 #define K1SCR_1KX_HDX   0x4000
 442 #define K1SCR_1KT_FDX   0x2000
 443 #define K1SCR_1KT_HDX   0x1000
 444
 445 #define STRAP_PHY1      0x0800
 446 #define STRAP_NCMODE    0x0400
 447 #define STRAP_MANMSCFG  0x0200
 448 #define STRAP_ANENABLE  0x0100
 449 #define STRAP_MSVAL     0x0080
 450 #define STRAP_1KHDXADV  0x0010
 451 #define STRAP_1KFDXADV  0x0008
 452 #define STRAP_100ADV    0x0004
 453 #define STRAP_SPEEDSEL  0x0000
 454 #define STRAP_SPEED100  0x0001
 455
 456 #define PHYSUP_SPEED1000 0x10
 457 #define PHYSUP_SPEED100  0x08
 458 #define PHYSUP_SPEED10   0x00
 459 #define PHYSUP_LINKUP    0x04
 460 #define PHYSUP_FDX       0x02
 461
 462 #define MII_BMCR        0x00    /* Basic mode control register (rw) */
 463 #define MII_BMSR        0x01    /* Basic mode status register (ro) */
 464 #define MII_PHYIDR1     0x02
 465 #define MII_PHYIDR2     0x03
 466
 467 #define MII_K1STSR      0x0A    /* 1K Status Register (ro) */
 468 #define MII_ANLPAR      0x05    /* Autonegotiation lnk partner abilities (rw) */
 469
 470
 471 #define M_MAC_MDIO_DIR_OUTPUT   0               /* for clarity */
 472
 473 #define ENABLE          1
 474 #define DISABLE         0
 475
 476 /**********************************************************************
 477  *  SBMAC_MII_SYNC(s)
 478  *
 479  *  Synchronize with the MII - send a pattern of bits to the MII
 480  *  that will guarantee that it is ready to accept a command.
 481  *
 482  *  Input parameters:
 483  *         s - sbmac structure
 484  *
 485  *  Return value:
 486  *         nothing
 487  ********************************************************************* */
 488
 489 static void sbmac_mii_sync(struct sbmac_softc *s)
 490 {
 491         int cnt;
 492         uint64_t bits;
 493         int mac_mdio_genc;
 494
 495         mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC;
 496
 497         bits = M_MAC_MDIO_DIR_OUTPUT | M_MAC_MDIO_OUT;
 498
 499         __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
 500
 501         for (cnt = 0; cnt < 32; cnt++) {
 502                 __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
 503                 __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
 504         }
 505 }
 506
 507 /**********************************************************************
 508  *  SBMAC_MII_SENDDATA(s,data,bitcnt)
 509  *
 510  *  Send some bits to the MII.  The bits to be sent are right-
 511  *  justified in the 'data' parameter.
 512  *
 513  *  Input parameters:
 514  *         s - sbmac structure
 515  *         data - data to send
 516  *         bitcnt - number of bits to send
 517  ********************************************************************* */
 518
 519 static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitcnt)
 520 {
 521         int i;
 522         uint64_t bits;
 523         unsigned int curmask;
 524         int mac_mdio_genc;
 525
 526         mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC;
 527
 528         bits = M_MAC_MDIO_DIR_OUTPUT;
 529         __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
 530
 531         curmask = 1 << (bitcnt - 1);
 532
 533         for (i = 0; i < bitcnt; i++) {
 534                 if (data & curmask)
 535                         bits |= M_MAC_MDIO_OUT;
 536                 else bits &= ~M_MAC_MDIO_OUT;
 537                 __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
 538                 __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
 539                 __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
 540                 curmask >>= 1;
 541         }
 542 }
 543
 544
 545
 546 /**********************************************************************
 547  *  SBMAC_MII_READ(s,phyaddr,regidx)
 548  *
 549  *  Read a PHY register.
 550  *
 551  *  Input parameters:
 552  *         s - sbmac structure
 553  *         phyaddr - PHY's address
 554  *         regidx = index of register to read
 555  *
 556  *  Return value:
 557  *         value read, or 0 if an error occurred.
 558  ********************************************************************* */
 559
 560 static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx)
 561 {
 562         int idx;
 563         int error;
 564         int regval;
 565         int mac_mdio_genc;
 566
 567         /*
 568          * Synchronize ourselves so that the PHY knows the next
 569          * thing coming down is a command
 570          */
 571
 572         sbmac_mii_sync(s);
 573
 574         /*
 575          * Send the data to the PHY.  The sequence is
 576          * a "start" command (2 bits)
 577          * a "read" command (2 bits)
 578          * the PHY addr (5 bits)
 579          * the register index (5 bits)
 580          */
 581
 582         sbmac_mii_senddata(s,MII_COMMAND_START, 2);
 583         sbmac_mii_senddata(s,MII_COMMAND_READ, 2);
 584         sbmac_mii_senddata(s,phyaddr, 5);
 585         sbmac_mii_senddata(s,regidx, 5);
 586
 587         mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC;
 588
 589         /*
 590          * Switch the port around without a clock transition.
 591          */
 592         __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio);
 593
 594         /*
 595          * Send out a clock pulse to signal we want the status
 596          */
 597
 598         __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
 599         __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio);
 600
 601         /*
 602          * If an error occurred, the PHY will signal '1' back
 603          */
 604         error = __raw_readq(s->sbm_mdio) & M_MAC_MDIO_IN;
 605
 606         /*
 607          * Issue an 'idle' clock pulse, but keep the direction
 608          * the same.
 609          */
 610         __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
 611         __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio);
 612
 613         regval = 0;
 614
 615         for (idx = 0; idx < 16; idx++) {
 616                 regval <<= 1;
 617
 618                 if (error == 0) {
 619                         if (__raw_readq(s->sbm_mdio) & M_MAC_MDIO_IN)
 620                                 regval |= 1;
 621                 }
 622
 623                 __raw_writeq(M_MAC_MDIO_DIR_INPUT|M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
 624                 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio);
 625         }
 626
 627         /* Switch back to output */
 628         __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, s->sbm_mdio);
 629
 630         if (error == 0)
 631                 return regval;
 632         return 0;
 633 }
 634
 635
 636 /**********************************************************************
 637  *  SBMAC_MII_WRITE(s,phyaddr,regidx,regval)
 638  *
 639  *  Write a value to a PHY register.
 640  *
 641  *  Input parameters:
 642  *         s - sbmac structure
 643  *         phyaddr - PHY to use
 644  *         regidx - register within the PHY
 645  *         regval - data to write to register
 646  *
 647  *  Return value:
 648  *         nothing
 649  ********************************************************************* */
 650
 651 static void sbmac_mii_write(struct sbmac_softc *s,int phyaddr,int regidx,
 652                             unsigned int regval)
 653 {
 654         int mac_mdio_genc;
 655
 656         sbmac_mii_sync(s);
 657
 658         sbmac_mii_senddata(s,MII_COMMAND_START,2);
 659         sbmac_mii_senddata(s,MII_COMMAND_WRITE,2);
 660         sbmac_mii_senddata(s,phyaddr, 5);
 661         sbmac_mii_senddata(s,regidx, 5);
 662         sbmac_mii_senddata(s,MII_COMMAND_ACK,2);
 663         sbmac_mii_senddata(s,regval,16);
 664
 665         mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC;
 666
 667         __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, s->sbm_mdio);
 668 }
 669
 670
 671
 672 /**********************************************************************
 673  *  SBDMA_INITCTX(d,s,chan,txrx,maxdescr)
 674  *
 675  *  Initialize a DMA channel context.  Since there are potentially
 676  *  eight DMA channels per MAC, it's nice to do this in a standard
 677  *  way.
 678  *
 679  *  Input parameters:
 680  *         d - sbmacdma_t structure (DMA channel context)
 681  *         s - sbmac_softc structure (pointer to a MAC)
 682  *         chan - channel number (0..1 right now)
 683  *         txrx - Identifies DMA_TX or DMA_RX for channel direction
 684  *      maxdescr - number of descriptors
 685  *
 686  *  Return value:
 687  *         nothing
 688  ********************************************************************* */
 689
 690 static void sbdma_initctx(sbmacdma_t *d,
 691                           struct sbmac_softc *s,
 692                           int chan,
 693                           int txrx,
 694                           int maxdescr)
 695 {
 696 #ifdef CONFIG_SBMAC_COALESCE
 697         int int_pktcnt, int_timeout;
 698 #endif
 699
 700         /*
 701          * Save away interesting stuff in the structure
 702          */
 703
 704         d->sbdma_eth       = s;
 705         d->sbdma_channel   = chan;
 706         d->sbdma_txdir     = txrx;
 707
 708 #if 0
 709         /* RMON clearing */
 710         s->sbe_idx =(s->sbm_base - A_MAC_BASE_0)/MAC_SPACING;
 711 #endif
 712
 713         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BYTES)));
 714         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_COLLISIONS)));
 715         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_LATE_COL)));
 716         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_EX_COL)));
 717         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_FCS_ERROR)));
 718         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_ABORT)));
 719         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BAD)));
 720         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_GOOD)));
 721         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_RUNT)));
 722         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_OVERSIZE)));
 723         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BYTES)));
 724         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_MCAST)));
 725         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BCAST)));
 726         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BAD)));
 727         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_GOOD)));
 728         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_RUNT)));
 729         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_OVERSIZE)));
 730         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_FCS_ERROR)));
 731         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_LENGTH_ERROR)));
 732         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_CODE_ERROR)));
 733         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_ALIGN_ERROR)));
 734
 735         /*
 736          * initialize register pointers
 737          */
 738
 739         d->sbdma_config0 =
 740                 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG0);
 741         d->sbdma_config1 =
 742                 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG1);
 743         d->sbdma_dscrbase =
 744                 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_BASE);
 745         d->sbdma_dscrcnt =
 746                 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_CNT);
 747         d->sbdma_curdscr =
 748                 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CUR_DSCRADDR);
 749         if (d->sbdma_txdir)
 750                 d->sbdma_oodpktlost = NULL;
 751         else
 752                 d->sbdma_oodpktlost =
 753                         s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_OODPKTLOST_RX);
 754
 755         /*
 756          * Allocate memory for the ring
 757          */
 758
 759         d->sbdma_maxdescr = maxdescr;
 760
 761         d->sbdma_dscrtable_unaligned =
 762         d->sbdma_dscrtable = (sbdmadscr_t *)
 763                 kmalloc((d->sbdma_maxdescr+1)*sizeof(sbdmadscr_t), GFP_KERNEL);
 764
 765         /*
 766          * The descriptor table must be aligned to at least 16 bytes or the
 767          * MAC will corrupt it.
 768          */
 769         d->sbdma_dscrtable = (sbdmadscr_t *)
 770                 ALIGN((unsigned long)d->sbdma_dscrtable, sizeof(sbdmadscr_t));
 771
 772         memset(d->sbdma_dscrtable,0,d->sbdma_maxdescr*sizeof(sbdmadscr_t));
 773
 774         d->sbdma_dscrtable_end = d->sbdma_dscrtable + d->sbdma_maxdescr;
 775
 776         d->sbdma_dscrtable_phys = virt_to_phys(d->sbdma_dscrtable);
 777
 778         /*
 779          * And context table
 780          */
 781
 782         d->sbdma_ctxtable = (struct sk_buff **)
 783                 kmalloc(d->sbdma_maxdescr*sizeof(struct sk_buff *), GFP_KERNEL);
 784
 785         memset(d->sbdma_ctxtable,0,d->sbdma_maxdescr*sizeof(struct sk_buff *));
 786
 787 #ifdef CONFIG_SBMAC_COALESCE
 788         /*
 789          * Setup Rx/Tx DMA coalescing defaults
 790          */
 791
 792         int_pktcnt = (txrx == DMA_TX) ? int_pktcnt_tx : int_pktcnt_rx;
 793         if ( int_pktcnt ) {
 794                 d->sbdma_int_pktcnt = int_pktcnt;
 795         } else {
 796                 d->sbdma_int_pktcnt = 1;
 797         }
 798
 799         int_timeout = (txrx == DMA_TX) ? int_timeout_tx : int_timeout_rx;
 800         if ( int_timeout ) {
 801                 d->sbdma_int_timeout = int_timeout;
 802         } else {
 803                 d->sbdma_int_timeout = 0;
 804         }
 805 #endif
 806
 807 }
 808
 809 /**********************************************************************
 810  *  SBDMA_CHANNEL_START(d)
 811  *
 812  *  Initialize the hardware registers for a DMA channel.
 813  *
 814  *  Input parameters:
 815  *         d - DMA channel to init (context must be previously init'd
 816  *         rxtx - DMA_RX or DMA_TX depending on what type of channel
 817  *
 818  *  Return value:
 819  *         nothing
 820  ********************************************************************* */
 821
 822 static void sbdma_channel_start(sbmacdma_t *d, int rxtx )
 823 {
 824         /*
 825          * Turn on the DMA channel
 826          */
 827
 828 #ifdef CONFIG_SBMAC_COALESCE
 829         __raw_writeq(V_DMA_INT_TIMEOUT(d->sbdma_int_timeout) |
 830                        0, d->sbdma_config1);
 831         __raw_writeq(M_DMA_EOP_INT_EN |
 832                        V_DMA_RINGSZ(d->sbdma_maxdescr) |
 833                        V_DMA_INT_PKTCNT(d->sbdma_int_pktcnt) |
 834                        0, d->sbdma_config0);
 835 #else
 836         __raw_writeq(0, d->sbdma_config1);
 837         __raw_writeq(V_DMA_RINGSZ(d->sbdma_maxdescr) |
 838                        0, d->sbdma_config0);
 839 #endif
 840
 841         __raw_writeq(d->sbdma_dscrtable_phys, d->sbdma_dscrbase);
 842
 843         /*
 844          * Initialize ring pointers
 845          */
 846
 847         d->sbdma_addptr = d->sbdma_dscrtable;
 848         d->sbdma_remptr = d->sbdma_dscrtable;
 849 }
 850
 851 /**********************************************************************
 852  *  SBDMA_CHANNEL_STOP(d)
 853  *
 854  *  Initialize the hardware registers for a DMA channel.
 855  *
 856  *  Input parameters:
 857  *         d - DMA channel to init (context must be previously init'd
 858  *
 859  *  Return value:
 860  *         nothing
 861  ********************************************************************* */
 862
 863 static void sbdma_channel_stop(sbmacdma_t *d)
 864 {
 865         /*
 866          * Turn off the DMA channel
 867          */
 868
 869         __raw_writeq(0, d->sbdma_config1);
 870
 871         __raw_writeq(0, d->sbdma_dscrbase);
 872
 873         __raw_writeq(0, d->sbdma_config0);
 874
 875         /*
 876          * Zero ring pointers
 877          */
 878
 879         d->sbdma_addptr = NULL;
 880         d->sbdma_remptr = NULL;
 881 }
 882
 883 static void sbdma_align_skb(struct sk_buff *skb,int power2,int offset)
 884 {
 885         unsigned long addr;
 886         unsigned long newaddr;
 887
 888         addr = (unsigned long) skb->data;
 889
 890         newaddr = (addr + power2 - 1) & ~(power2 - 1);
 891
 892         skb_reserve(skb,newaddr-addr+offset);
 893 }
 894
 895
 896 /**********************************************************************
 897  *  SBDMA_ADD_RCVBUFFER(d,sb)
 898  *
 899  *  Add a buffer to the specified DMA channel.   For receive channels,
 900  *  this queues a buffer for inbound packets.
 901  *
 902  *  Input parameters:
 903  *         d - DMA channel descriptor
 904  *         sb - sk_buff to add, or NULL if we should allocate one
 905  *
 906  *  Return value:
 907  *         0 if buffer could not be added (ring is full)
 908  *         1 if buffer added successfully
 909  ********************************************************************* */
 910
 911
 912 static int sbdma_add_rcvbuffer(sbmacdma_t *d,struct sk_buff *sb)
 913 {
 914         sbdmadscr_t *dsc;
 915         sbdmadscr_t *nextdsc;
 916         struct sk_buff *sb_new = NULL;
 917         int pktsize = ENET_PACKET_SIZE;
 918
 919         /* get pointer to our current place in the ring */
 920
 921         dsc = d->sbdma_addptr;
 922         nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
 923
 924         /*
 925          * figure out if the ring is full - if the next descriptor
 926          * is the same as the one that we're going to remove from
 927          * the ring, the ring is full
 928          */
 929
 930         if (nextdsc == d->sbdma_remptr) {
 931                 return -ENOSPC;
 932         }
 933
 934         /*
 935          * Allocate a sk_buff if we don't already have one.
 936          * If we do have an sk_buff, reset it so that it's empty.
 937          *
 938          * Note: sk_buffs don't seem to be guaranteed to have any sort
 939          * of alignment when they are allocated.  Therefore, allocate enough
 940          * extra space to make sure that:
 941          *
 942          *    1. the data does not start in the middle of a cache line.
 943          *    2. The data does not end in the middle of a cache line
 944          *    3. The buffer can be aligned such that the IP addresses are
 945          *       naturally aligned.
 946          *
 947          *  Remember, the SOCs MAC writes whole cache lines at a time,
 948          *  without reading the old contents first.  So, if the sk_buff's
 949          *  data portion starts in the middle of a cache line, the SOC
 950          *  DMA will trash the beginning (and ending) portions.
 951          */
 952
 953         if (sb == NULL) {
 954                 sb_new = dev_alloc_skb(ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN);
 955                 if (sb_new == NULL) {
 956                         printk(KERN_INFO "%s: sk_buff allocation failed\n",
 957                                d->sbdma_eth->sbm_dev->name);
 958                         return -ENOBUFS;
 959                 }
 960
 961                 sbdma_align_skb(sb_new, SMP_CACHE_BYTES, ETHER_ALIGN);
 962         }
 963         else {
 964                 sb_new = sb;
 965                 /*
 966                  * nothing special to reinit buffer, it's already aligned
 967                  * and sb->data already points to a good place.
 968                  */
 969         }
 970
 971         /*
 972          * fill in the descriptor
 973          */
 974
 975 #ifdef CONFIG_SBMAC_COALESCE
 976         /*
 977          * Do not interrupt per DMA transfer.
 978          */
 979         dsc->dscr_a = virt_to_phys(sb_new->data) |
 980                 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) | 0;
 981 #else
 982         dsc->dscr_a = virt_to_phys(sb_new->data) |
 983                 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) |
 984                 M_DMA_DSCRA_INTERRUPT;
 985 #endif
 986
 987         /* receiving: no options */
 988         dsc->dscr_b = 0;
 989
 990         /*
 991          * fill in the context
 992          */
 993
 994         d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb_new;
 995
 996         /*
 997          * point at next packet
 998          */
 999
1000         d->sbdma_addptr = nextdsc;
1001
1002         /*
1003          * Give the buffer to the DMA engine.
1004          */
1005
1006         __raw_writeq(1, d->sbdma_dscrcnt);
1007
1008         return 0;                                       /* we did it */
1009 }
1010
1011 /**********************************************************************
1012  *  SBDMA_ADD_TXBUFFER(d,sb)
1013  *
1014  *  Add a transmit buffer to the specified DMA channel, causing a
1015  *  transmit to start.
1016  *
1017  *  Input parameters:
1018  *         d - DMA channel descriptor
1019  *         sb - sk_buff to add
1020  *
1021  *  Return value:
1022  *         0 transmit queued successfully
1023  *         otherwise error code
1024  ********************************************************************* */
1025
1026
1027 static int sbdma_add_txbuffer(sbmacdma_t *d,struct sk_buff *sb)
1028 {
1029         sbdmadscr_t *dsc;
1030         sbdmadscr_t *nextdsc;
1031         uint64_t phys;
1032         uint64_t ncb;
1033         int length;
1034
1035         /* get pointer to our current place in the ring */
1036
1037         dsc = d->sbdma_addptr;
1038         nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
1039
1040         /*
1041          * figure out if the ring is full - if the next descriptor
1042          * is the same as the one that we're going to remove from
1043          * the ring, the ring is full
1044          */
1045
1046         if (nextdsc == d->sbdma_remptr) {
1047                 return -ENOSPC;
1048         }
1049
1050         /*
1051          * Under Linux, it's not necessary to copy/coalesce buffers
1052          * like it is on NetBSD.  We think they're all contiguous,
1053          * but that may not be true for GBE.
1054          */
1055
1056         length = sb->len;
1057
1058         /*
1059          * fill in the descriptor.  Note that the number of cache
1060          * blocks in the descriptor is the number of blocks
1061          * *spanned*, so we need to add in the offset (if any)
1062          * while doing the calculation.
1063          */
1064
1065         phys = virt_to_phys(sb->data);
1066         ncb = NUMCACHEBLKS(length+(phys & (SMP_CACHE_BYTES - 1)));
1067
1068         dsc->dscr_a = phys |
1069                 V_DMA_DSCRA_A_SIZE(ncb) |
1070 #ifndef CONFIG_SBMAC_COALESCE
1071                 M_DMA_DSCRA_INTERRUPT |
1072 #endif
1073                 M_DMA_ETHTX_SOP;
1074
1075         /* transmitting: set outbound options and length */
1076
1077         dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) |
1078                 V_DMA_DSCRB_PKT_SIZE(length);
1079
1080         /*
1081          * fill in the context
1082          */
1083
1084         d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb;
1085
1086         /*
1087          * point at next packet
1088          */
1089
1090         d->sbdma_addptr = nextdsc;
1091
1092         /*
1093          * Give the buffer to the DMA engine.
1094          */
1095
1096         __raw_writeq(1, d->sbdma_dscrcnt);
1097
1098         return 0;                                       /* we did it */
1099 }
1100
1101
1102
1103
1104 /**********************************************************************
1105  *  SBDMA_EMPTYRING(d)
1106  *
1107  *  Free all allocated sk_buffs on the specified DMA channel;
1108  *
1109  *  Input parameters:
1110  *         d  - DMA channel
1111  *
1112  *  Return value:
1113  *         nothing
1114  ********************************************************************* */
1115
1116 static void sbdma_emptyring(sbmacdma_t *d)
1117 {
1118         int idx;
1119         struct sk_buff *sb;
1120
1121         for (idx = 0; idx < d->sbdma_maxdescr; idx++) {
1122                 sb = d->sbdma_ctxtable[idx];
1123                 if (sb) {
1124                         dev_kfree_skb(sb);
1125                         d->sbdma_ctxtable[idx] = NULL;
1126                 }
1127         }
1128 }
1129
1130
1131 /**********************************************************************
1132  *  SBDMA_FILLRING(d)
1133  *
1134  *  Fill the specified DMA channel (must be receive channel)
1135  *  with sk_buffs
1136  *
1137  *  Input parameters:
1138  *         d - DMA channel
1139  *
1140  *  Return value:
1141  *         nothing
1142  ********************************************************************* */
1143
1144 static void sbdma_fillring(sbmacdma_t *d)
1145 {
1146         int idx;
1147
1148         for (idx = 0; idx < SBMAC_MAX_RXDESCR-1; idx++) {
1149                 if (sbdma_add_rcvbuffer(d,NULL) != 0)
1150                         break;
1151         }
1152 }
1153
1154 #ifdef CONFIG_NET_POLL_CONTROLLER
1155 static void sbmac_netpoll(struct net_device *netdev)
1156 {
1157         struct sbmac_softc *sc = netdev_priv(netdev);
1158         int irq = sc->sbm_dev->irq;
1159
1160         __raw_writeq(0, sc->sbm_imr);
1161
1162         sbmac_intr(irq, netdev);
1163
1164 #ifdef CONFIG_SBMAC_COALESCE
1165         __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
1166         ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0),
1167         sc->sbm_imr);
1168 #else
1169         __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
1170         (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), sc->sbm_imr);
1171 #endif
1172 }
1173 #endif
1174
1175 /**********************************************************************
1176  *  SBDMA_RX_PROCESS(sc,d,work_to_do,poll)
1177  *
1178  *  Process "completed" receive buffers on the specified DMA channel.
1179  *
1180  *  Input parameters:
1181  *            sc - softc structure
1182  *             d - DMA channel context
1183  *    work_to_do - no. of packets to process before enabling interrupt
1184  *                 again (for NAPI)
1185  *          poll - 1: using polling (for NAPI)
1186  *
1187  *  Return value:
1188  *         nothing
1189  ********************************************************************* */
1190
1191 static int sbdma_rx_process(struct sbmac_softc *sc,sbmacdma_t *d,
1192                              int work_to_do, int poll)
1193 {
1194         int curidx;
1195         int hwidx;
1196         sbdmadscr_t *dsc;
1197         struct sk_buff *sb;
1198         int len;
1199         int work_done = 0;
1200         int dropped = 0;
1201
1202         prefetch(d);
1203
1204 again:
1205         /* Check if the HW dropped any frames */
1206         sc->sbm_stats.rx_fifo_errors
1207             += __raw_readq(sc->sbm_rxdma.sbdma_oodpktlost) & 0xffff;
1208         __raw_writeq(0, sc->sbm_rxdma.sbdma_oodpktlost);
1209
1210         while (work_to_do-- > 0) {
1211                 /*
1212                  * figure out where we are (as an index) and where
1213                  * the hardware is (also as an index)
1214                  *
1215                  * This could be done faster if (for example) the
1216                  * descriptor table was page-aligned and contiguous in
1217                  * both virtual and physical memory -- you could then
1218                  * just compare the low-order bits of the virtual address
1219                  * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1220                  */
1221
1222                 dsc = d->sbdma_remptr;
1223                 curidx = dsc - d->sbdma_dscrtable;
1224
1225                 prefetch(dsc);
1226                 prefetch(&d->sbdma_ctxtable[curidx]);
1227
1228                 hwidx = (int) (((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
1229                                 d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t));
1230
1231                 /*
1232                  * If they're the same, that means we've processed all
1233                  * of the descriptors up to (but not including) the one that
1234                  * the hardware is working on right now.
1235                  */
1236
1237                 if (curidx == hwidx)
1238                         goto done;
1239
1240                 /*
1241                  * Otherwise, get the packet's sk_buff ptr back
1242                  */
1243
1244                 sb = d->sbdma_ctxtable[curidx];
1245                 d->sbdma_ctxtable[curidx] = NULL;
1246
1247                 len = (int)G_DMA_DSCRB_PKT_SIZE(dsc->dscr_b) - 4;
1248
1249                 /*
1250                  * Check packet status.  If good, process it.
1251                  * If not, silently drop it and put it back on the
1252                  * receive ring.
1253                  */
1254
1255                 if (likely (!(dsc->dscr_a & M_DMA_ETHRX_BAD))) {
1256
1257                         /*
1258                          * Add a new buffer to replace the old one.  If we fail
1259                          * to allocate a buffer, we're going to drop this
1260                          * packet and put it right back on the receive ring.
1261                          */
1262
1263                         if (unlikely (sbdma_add_rcvbuffer(d,NULL) ==
1264                                       -ENOBUFS)) {
1265                                 sc->sbm_stats.rx_dropped++;
1266                                 sbdma_add_rcvbuffer(d,sb); /* re-add old buffer */
1267                                 /* No point in continuing at the moment */
1268                                 printk(KERN_ERR "dropped packet (1)\n");
1269                                 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1270                                 goto done;
1271                         } else {
1272                                 /*
1273                                  * Set length into the packet
1274                                  */
1275                                 skb_put(sb,len);
1276
1277                                 /*
1278                                  * Buffer has been replaced on the
1279                                  * receive ring.  Pass the buffer to
1280                                  * the kernel
1281                                  */
1282                                 sb->protocol = eth_type_trans(sb,d->sbdma_eth->sbm_dev);
1283                                 /* Check hw IPv4/TCP checksum if supported */
1284                                 if (sc->rx_hw_checksum == ENABLE) {
1285                                         if (!((dsc->dscr_a) & M_DMA_ETHRX_BADIP4CS) &&
1286                                             !((dsc->dscr_a) & M_DMA_ETHRX_BADTCPCS)) {
1287                                                 sb->ip_summed = CHECKSUM_UNNECESSARY;
1288                                                 /* don't need to set sb->csum */
1289                                         } else {
1290                                                 sb->ip_summed = CHECKSUM_NONE;
1291                                         }
1292                                 }
1293                                 prefetch(sb->data);
1294                                 prefetch((const void *)(((char *)sb->data)+32));
1295                                 if (poll)
1296                                         dropped = netif_receive_skb(sb);
1297                                 else
1298                                         dropped = netif_rx(sb);
1299
1300                                 if (dropped == NET_RX_DROP) {
1301                                         sc->sbm_stats.rx_dropped++;
1302                                         d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1303                                         goto done;
1304                                 }
1305                                 else {
1306                                         sc->sbm_stats.rx_bytes += len;
1307                                         sc->sbm_stats.rx_packets++;
1308                                 }
1309                         }
1310                 } else {
1311                         /*
1312                          * Packet was mangled somehow.  Just drop it and
1313                          * put it back on the receive ring.
1314                          */
1315                         sc->sbm_stats.rx_errors++;
1316                         sbdma_add_rcvbuffer(d,sb);
1317                 }
1318
1319
1320                 /*
1321                  * .. and advance to the next buffer.
1322                  */
1323
1324                 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1325                 work_done++;
1326         }
1327         if (!poll) {
1328                 work_to_do = 32;
1329                 goto again; /* collect fifo drop statistics again */
1330         }
1331 done:
1332         return work_done;
1333 }
1334
1335 /**********************************************************************
1336  *  SBDMA_TX_PROCESS(sc,d)
1337  *
1338  *  Process "completed" transmit buffers on the specified DMA channel.
1339  *  This is normally called within the interrupt service routine.
1340  *  Note that this isn't really ideal for priority channels, since
1341  *  it processes all of the packets on a given channel before
1342  *  returning.
1343  *
1344  *  Input parameters:
1345  *      sc - softc structure
1346  *       d - DMA channel context
1347  *    poll - 1: using polling (for NAPI)
1348  *
1349  *  Return value:
1350  *         nothing
1351  ********************************************************************* */
1352
1353 static void sbdma_tx_process(struct sbmac_softc *sc,sbmacdma_t *d, int poll)
1354 {
1355         int curidx;
1356         int hwidx;
1357         sbdmadscr_t *dsc;
1358         struct sk_buff *sb;
1359         unsigned long flags;
1360         int packets_handled = 0;
1361
1362         spin_lock_irqsave(&(sc->sbm_lock), flags);
1363
1364         if (d->sbdma_remptr == d->sbdma_addptr)
1365           goto end_unlock;
1366
1367         hwidx = (int) (((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
1368                         d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t));
1369
1370         for (;;) {
1371                 /*
1372                  * figure out where we are (as an index) and where
1373                  * the hardware is (also as an index)
1374                  *
1375                  * This could be done faster if (for example) the
1376                  * descriptor table was page-aligned and contiguous in
1377                  * both virtual and physical memory -- you could then
1378                  * just compare the low-order bits of the virtual address
1379                  * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1380                  */
1381
1382                 curidx = d->sbdma_remptr - d->sbdma_dscrtable;
1383
1384                 /*
1385                  * If they're the same, that means we've processed all
1386                  * of the descriptors up to (but not including) the one that
1387                  * the hardware is working on right now.
1388                  */
1389
1390                 if (curidx == hwidx)
1391                         break;
1392
1393                 /*
1394                  * Otherwise, get the packet's sk_buff ptr back
1395                  */
1396
1397                 dsc = &(d->sbdma_dscrtable[curidx]);
1398                 sb = d->sbdma_ctxtable[curidx];
1399                 d->sbdma_ctxtable[curidx] = NULL;
1400
1401                 /*
1402                  * Stats
1403                  */
1404
1405                 sc->sbm_stats.tx_bytes += sb->len;
1406                 sc->sbm_stats.tx_packets++;
1407
1408                 /*
1409                  * for transmits, we just free buffers.
1410                  */
1411
1412                 dev_kfree_skb_irq(sb);
1413
1414                 /*
1415                  * .. and advance to the next buffer.
1416                  */
1417
1418                 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1419
1420                 packets_handled++;
1421
1422         }
1423
1424         /*
1425          * Decide if we should wake up the protocol or not.
1426          * Other drivers seem to do this when we reach a low
1427          * watermark on the transmit queue.
1428          */
1429
1430         if (packets_handled)
1431                 netif_wake_queue(d->sbdma_eth->sbm_dev);
1432
1433 end_unlock:
1434         spin_unlock_irqrestore(&(sc->sbm_lock), flags);
1435
1436 }
1437
1438
1439
1440 /**********************************************************************
1441  *  SBMAC_INITCTX(s)
1442  *
1443  *  Initialize an Ethernet context structure - this is called
1444  *  once per MAC on the 1250.  Memory is allocated here, so don't
1445  *  call it again from inside the ioctl routines that bring the
1446  *  interface up/down
1447  *
1448  *  Input parameters:
1449  *         s - sbmac context structure
1450  *
1451  *  Return value:
1452  *         0
1453  ********************************************************************* */
1454
1455 static int sbmac_initctx(struct sbmac_softc *s)
1456 {
1457
1458         /*
1459          * figure out the addresses of some ports
1460          */
1461
1462         s->sbm_macenable = s->sbm_base + R_MAC_ENABLE;
1463         s->sbm_maccfg    = s->sbm_base + R_MAC_CFG;
1464         s->sbm_fifocfg   = s->sbm_base + R_MAC_THRSH_CFG;
1465         s->sbm_framecfg  = s->sbm_base + R_MAC_FRAMECFG;
1466         s->sbm_rxfilter  = s->sbm_base + R_MAC_ADFILTER_CFG;
1467         s->sbm_isr       = s->sbm_base + R_MAC_STATUS;
1468         s->sbm_imr       = s->sbm_base + R_MAC_INT_MASK;
1469         s->sbm_mdio      = s->sbm_base + R_MAC_MDIO;
1470
1471         s->sbm_phys[0]   = 1;
1472         s->sbm_phys[1]   = 0;
1473
1474         s->sbm_phy_oldbmsr = 0;
1475         s->sbm_phy_oldanlpar = 0;
1476         s->sbm_phy_oldk1stsr = 0;
1477         s->sbm_phy_oldlinkstat = 0;
1478
1479         /*
1480          * Initialize the DMA channels.  Right now, only one per MAC is used
1481          * Note: Only do this _once_, as it allocates memory from the kernel!
1482          */
1483
1484         sbdma_initctx(&(s->sbm_txdma),s,0,DMA_TX,SBMAC_MAX_TXDESCR);
1485         sbdma_initctx(&(s->sbm_rxdma),s,0,DMA_RX,SBMAC_MAX_RXDESCR);
1486
1487         /*
1488          * initial state is OFF
1489          */
1490
1491         s->sbm_state = sbmac_state_off;
1492
1493         /*
1494          * Initial speed is (XXX TEMP) 10MBit/s HDX no FC
1495          */
1496
1497         s->sbm_speed = sbmac_speed_10;
1498         s->sbm_duplex = sbmac_duplex_half;
1499         s->sbm_fc = sbmac_fc_disabled;
1500
1501         return 0;
1502 }
1503
1504
1505 static void sbdma_uninitctx(struct sbmacdma_s *d)
1506 {
1507         if (d->sbdma_dscrtable_unaligned) {
1508                 kfree(d->sbdma_dscrtable_unaligned);
1509                 d->sbdma_dscrtable_unaligned = d->sbdma_dscrtable = NULL;
1510         }
1511
1512         if (d->sbdma_ctxtable) {
1513                 kfree(d->sbdma_ctxtable);
1514                 d->sbdma_ctxtable = NULL;
1515         }
1516 }
1517
1518
1519 static void sbmac_uninitctx(struct sbmac_softc *sc)
1520 {
1521         sbdma_uninitctx(&(sc->sbm_txdma));
1522         sbdma_uninitctx(&(sc->sbm_rxdma));
1523 }
1524
1525
1526 /**********************************************************************
1527  *  SBMAC_CHANNEL_START(s)
1528  *
1529  *  Start packet processing on this MAC.
1530  *
1531  *  Input parameters:
1532  *         s - sbmac structure
1533  *
1534  *  Return value:
1535  *         nothing
1536  ********************************************************************* */
1537
1538 static void sbmac_channel_start(struct sbmac_softc *s)
1539 {
1540         uint64_t reg;
1541         volatile void __iomem *port;
1542         uint64_t cfg,fifo,framecfg;
1543         int idx, th_value;
1544
1545         /*
1546          * Don't do this if running
1547          */
1548
1549         if (s->sbm_state == sbmac_state_on)
1550                 return;
1551
1552         /*
1553          * Bring the controller out of reset, but leave it off.
1554          */
1555
1556         __raw_writeq(0, s->sbm_macenable);
1557
1558         /*
1559          * Ignore all received packets
1560          */
1561
1562         __raw_writeq(0, s->sbm_rxfilter);
1563
1564         /*
1565          * Calculate values for various control registers.
1566          */
1567
1568         cfg = M_MAC_RETRY_EN |
1569                 M_MAC_TX_HOLD_SOP_EN |
1570                 V_MAC_TX_PAUSE_CNT_16K |
1571                 M_MAC_AP_STAT_EN |
1572                 M_MAC_FAST_SYNC |
1573                 M_MAC_SS_EN |
1574                 0;
1575
1576         /*
1577          * Be sure that RD_THRSH+WR_THRSH <= 32 for pass1 pars
1578          * and make sure that RD_THRSH + WR_THRSH <=128 for pass2 and above
1579          * Use a larger RD_THRSH for gigabit
1580          */
1581         if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2)
1582                 th_value = 28;
1583         else
1584                 th_value = 64;
1585
1586         fifo = V_MAC_TX_WR_THRSH(4) |   /* Must be '4' or '8' */
1587                 ((s->sbm_speed == sbmac_speed_1000)
1588                  ? V_MAC_TX_RD_THRSH(th_value) : V_MAC_TX_RD_THRSH(4)) |
1589                 V_MAC_TX_RL_THRSH(4) |
1590                 V_MAC_RX_PL_THRSH(4) |
1591                 V_MAC_RX_RD_THRSH(4) |  /* Must be '4' */
1592                 V_MAC_RX_PL_THRSH(4) |
1593                 V_MAC_RX_RL_THRSH(8) |
1594                 0;
1595
1596         framecfg = V_MAC_MIN_FRAMESZ_DEFAULT |
1597                 V_MAC_MAX_FRAMESZ_DEFAULT |
1598                 V_MAC_BACKOFF_SEL(1);
1599
1600         /*
1601          * Clear out the hash address map
1602          */
1603
1604         port = s->sbm_base + R_MAC_HASH_BASE;
1605         for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
1606                 __raw_writeq(0, port);
1607                 port += sizeof(uint64_t);
1608         }
1609
1610         /*
1611          * Clear out the exact-match table
1612          */
1613
1614         port = s->sbm_base + R_MAC_ADDR_BASE;
1615         for (idx = 0; idx < MAC_ADDR_COUNT; idx++) {
1616                 __raw_writeq(0, port);
1617                 port += sizeof(uint64_t);
1618         }
1619
1620         /*
1621          * Clear out the DMA Channel mapping table registers
1622          */
1623
1624         port = s->sbm_base + R_MAC_CHUP0_BASE;
1625         for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1626                 __raw_writeq(0, port);
1627                 port += sizeof(uint64_t);
1628         }
1629
1630
1631         port = s->sbm_base + R_MAC_CHLO0_BASE;
1632         for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1633                 __raw_writeq(0, port);
1634                 port += sizeof(uint64_t);
1635         }
1636
1637         /*
1638          * Program the hardware address.  It goes into the hardware-address
1639          * register as well as the first filter register.
1640          */
1641
1642         reg = sbmac_addr2reg(s->sbm_hwaddr);
1643
1644         port = s->sbm_base + R_MAC_ADDR_BASE;
1645         __raw_writeq(reg, port);
1646         port = s->sbm_base + R_MAC_ETHERNET_ADDR;
1647
1648 #ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
1649         /*
1650          * Pass1 SOCs do not receive packets addressed to the
1651          * destination address in the R_MAC_ETHERNET_ADDR register.
1652          * Set the value to zero.
1653          */
1654         __raw_writeq(0, port);
1655 #else
1656         __raw_writeq(reg, port);
1657 #endif
1658
1659         /*
1660          * Set the receive filter for no packets, and write values
1661          * to the various config registers
1662          */
1663
1664         __raw_writeq(0, s->sbm_rxfilter);
1665         __raw_writeq(0, s->sbm_imr);
1666         __raw_writeq(framecfg, s->sbm_framecfg);
1667         __raw_writeq(fifo, s->sbm_fifocfg);
1668         __raw_writeq(cfg, s->sbm_maccfg);
1669
1670         /*
1671          * Initialize DMA channels (rings should be ok now)
1672          */
1673
1674         sbdma_channel_start(&(s->sbm_rxdma), DMA_RX);
1675         sbdma_channel_start(&(s->sbm_txdma), DMA_TX);
1676
1677         /*
1678          * Configure the speed, duplex, and flow control
1679          */
1680
1681         sbmac_set_speed(s,s->sbm_speed);
1682         sbmac_set_duplex(s,s->sbm_duplex,s->sbm_fc);
1683
1684         /*
1685          * Fill the receive ring
1686          */
1687
1688         sbdma_fillring(&(s->sbm_rxdma));
1689
1690         /*
1691          * Turn on the rest of the bits in the enable register
1692          */
1693
1694 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
1695         __raw_writeq(M_MAC_RXDMA_EN0 |
1696                        M_MAC_TXDMA_EN0, s->sbm_macenable);
1697 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
1698         __raw_writeq(M_MAC_RXDMA_EN0 |
1699                        M_MAC_TXDMA_EN0 |
1700                        M_MAC_RX_ENABLE |
1701                        M_MAC_TX_ENABLE, s->sbm_macenable);
1702 #else
1703 #error invalid SiByte MAC configuation
1704 #endif
1705
1706 #ifdef CONFIG_SBMAC_COALESCE
1707         __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
1708                        ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0), s->sbm_imr);
1709 #else
1710         __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
1711                        (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), s->sbm_imr);
1712 #endif
1713
1714         /*
1715          * Enable receiving unicasts and broadcasts
1716          */
1717
1718         __raw_writeq(M_MAC_UCAST_EN | M_MAC_BCAST_EN, s->sbm_rxfilter);
1719
1720         /*
1721          * we're running now.
1722          */
1723
1724         s->sbm_state = sbmac_state_on;
1725
1726         /*
1727          * Program multicast addresses
1728          */
1729
1730         sbmac_setmulti(s);
1731
1732         /*
1733          * If channel was in promiscuous mode before, turn that on
1734          */
1735
1736         if (s->sbm_devflags & IFF_PROMISC) {
1737                 sbmac_promiscuous_mode(s,1);
1738         }
1739
1740 }
1741
1742
1743 /**********************************************************************
1744  *  SBMAC_CHANNEL_STOP(s)
1745  *
1746  *  Stop packet processing on this MAC.
1747  *
1748  *  Input parameters:
1749  *         s - sbmac structure
1750  *
1751  *  Return value:
1752  *         nothing
1753  ********************************************************************* */
1754
1755 static void sbmac_channel_stop(struct sbmac_softc *s)
1756 {
1757         /* don't do this if already stopped */
1758
1759         if (s->sbm_state == sbmac_state_off)
1760                 return;
1761
1762         /* don't accept any packets, disable all interrupts */
1763
1764         __raw_writeq(0, s->sbm_rxfilter);
1765         __raw_writeq(0, s->sbm_imr);
1766
1767         /* Turn off ticker */
1768
1769         /* XXX */
1770
1771         /* turn off receiver and transmitter */
1772
1773         __raw_writeq(0, s->sbm_macenable);
1774
1775         /* We're stopped now. */
1776
1777         s->sbm_state = sbmac_state_off;
1778
1779         /*
1780          * Stop DMA channels (rings should be ok now)
1781          */
1782
1783         sbdma_channel_stop(&(s->sbm_rxdma));
1784         sbdma_channel_stop(&(s->sbm_txdma));
1785
1786         /* Empty the receive and transmit rings */
1787
1788         sbdma_emptyring(&(s->sbm_rxdma));
1789         sbdma_emptyring(&(s->sbm_txdma));
1790
1791 }
1792
1793 /**********************************************************************
1794  *  SBMAC_SET_CHANNEL_STATE(state)
1795  *
1796  *  Set the channel's state ON or OFF
1797  *
1798  *  Input parameters:
1799  *         state - new state
1800  *
1801  *  Return value:
1802  *         old state
1803  ********************************************************************* */
1804 static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *sc,
1805                                              sbmac_state_t state)
1806 {
1807         sbmac_state_t oldstate = sc->sbm_state;
1808
1809         /*
1810          * If same as previous state, return
1811          */
1812
1813         if (state == oldstate) {
1814                 return oldstate;
1815         }
1816
1817         /*
1818          * If new state is ON, turn channel on
1819          */
1820
1821         if (state == sbmac_state_on) {
1822                 sbmac_channel_start(sc);
1823         }
1824         else {
1825                 sbmac_channel_stop(sc);
1826         }
1827
1828         /*
1829          * Return previous state
1830          */
1831
1832         return oldstate;
1833 }
1834
1835
1836 /**********************************************************************
1837  *  SBMAC_PROMISCUOUS_MODE(sc,onoff)
1838  *
1839  *  Turn on or off promiscuous mode
1840  *
1841  *  Input parameters:
1842  *         sc - softc
1843  *      onoff - 1 to turn on, 0 to turn off
1844  *
1845  *  Return value:
1846  *         nothing
1847  ********************************************************************* */
1848
1849 static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff)
1850 {
1851         uint64_t reg;
1852
1853         if (sc->sbm_state != sbmac_state_on)
1854                 return;
1855
1856         if (onoff) {
1857                 reg = __raw_readq(sc->sbm_rxfilter);
1858                 reg |= M_MAC_ALLPKT_EN;
1859                 __raw_writeq(reg, sc->sbm_rxfilter);
1860         }
1861         else {
1862                 reg = __raw_readq(sc->sbm_rxfilter);
1863                 reg &= ~M_MAC_ALLPKT_EN;
1864                 __raw_writeq(reg, sc->sbm_rxfilter);
1865         }
1866 }
1867
1868 /**********************************************************************
1869  *  SBMAC_SETIPHDR_OFFSET(sc,onoff)
1870  *
1871  *  Set the iphdr offset as 15 assuming ethernet encapsulation
1872  *
1873  *  Input parameters:
1874  *         sc - softc
1875  *
1876  *  Return value:
1877  *         nothing
1878  ********************************************************************* */
1879
1880 static void sbmac_set_iphdr_offset(struct sbmac_softc *sc)
1881 {
1882         uint64_t reg;
1883
1884         /* Hard code the off set to 15 for now */
1885         reg = __raw_readq(sc->sbm_rxfilter);
1886         reg &= ~M_MAC_IPHDR_OFFSET | V_MAC_IPHDR_OFFSET(15);
1887         __raw_writeq(reg, sc->sbm_rxfilter);
1888
1889         /* BCM1250 pass1 didn't have hardware checksum.  Everything
1890            later does.  */
1891         if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2) {
1892                 sc->rx_hw_checksum = DISABLE;
1893         } else {
1894                 sc->rx_hw_checksum = ENABLE;
1895         }
1896 }
1897
1898
1899 /**********************************************************************
1900  *  SBMAC_ADDR2REG(ptr)
1901  *
1902  *  Convert six bytes into the 64-bit register value that
1903  *  we typically write into the SBMAC's address/mcast registers
1904  *
1905  *  Input parameters:
1906  *         ptr - pointer to 6 bytes
1907  *
1908  *  Return value:
1909  *         register value
1910  ********************************************************************* */
1911
1912 static uint64_t sbmac_addr2reg(unsigned char *ptr)
1913 {
1914         uint64_t reg = 0;
1915
1916         ptr += 6;
1917
1918         reg |= (uint64_t) *(--ptr);
1919         reg <<= 8;
1920         reg |= (uint64_t) *(--ptr);
1921         reg <<= 8;
1922         reg |= (uint64_t) *(--ptr);
1923         reg <<= 8;
1924         reg |= (uint64_t) *(--ptr);
1925         reg <<= 8;
1926         reg |= (uint64_t) *(--ptr);
1927         reg <<= 8;
1928         reg |= (uint64_t) *(--ptr);
1929
1930         return reg;
1931 }
1932
1933
1934 /**********************************************************************
1935  *  SBMAC_SET_SPEED(s,speed)
1936  *
1937  *  Configure LAN speed for the specified MAC.
1938  *  Warning: must be called when MAC is off!
1939  *
1940  *  Input parameters:
1941  *         s - sbmac structure
1942  *         speed - speed to set MAC to (see sbmac_speed_t enum)
1943  *
1944  *  Return value:
1945  *         1 if successful
1946  *      0 indicates invalid parameters
1947  ********************************************************************* */
1948
1949 static int sbmac_set_speed(struct sbmac_softc *s,sbmac_speed_t speed)
1950 {
1951         uint64_t cfg;
1952         uint64_t framecfg;
1953
1954         /*
1955          * Save new current values
1956          */
1957
1958         s->sbm_speed = speed;
1959
1960         if (s->sbm_state == sbmac_state_on)
1961                 return 0;       /* save for next restart */
1962
1963         /*
1964          * Read current register values
1965          */
1966
1967         cfg = __raw_readq(s->sbm_maccfg);
1968         framecfg = __raw_readq(s->sbm_framecfg);
1969
1970         /*
1971          * Mask out the stuff we want to change
1972          */
1973
1974         cfg &= ~(M_MAC_BURST_EN | M_MAC_SPEED_SEL);
1975         framecfg &= ~(M_MAC_IFG_RX | M_MAC_IFG_TX | M_MAC_IFG_THRSH |
1976                       M_MAC_SLOT_SIZE);
1977
1978         /*
1979          * Now add in the new bits
1980          */
1981
1982         switch (speed) {
1983         case sbmac_speed_10:
1984                 framecfg |= V_MAC_IFG_RX_10 |
1985                         V_MAC_IFG_TX_10 |
1986                         K_MAC_IFG_THRSH_10 |
1987                         V_MAC_SLOT_SIZE_10;
1988                 cfg |= V_MAC_SPEED_SEL_10MBPS;
1989                 break;
1990
1991         case sbmac_speed_100:
1992                 framecfg |= V_MAC_IFG_RX_100 |
1993                         V_MAC_IFG_TX_100 |
1994                         V_MAC_IFG_THRSH_100 |
1995                         V_MAC_SLOT_SIZE_100;
1996                 cfg |= V_MAC_SPEED_SEL_100MBPS ;
1997                 break;
1998
1999         case sbmac_speed_1000:
2000                 framecfg |= V_MAC_IFG_RX_1000 |
2001                         V_MAC_IFG_TX_1000 |
2002                         V_MAC_IFG_THRSH_1000 |
2003                         V_MAC_SLOT_SIZE_1000;
2004                 cfg |= V_MAC_SPEED_SEL_1000MBPS | M_MAC_BURST_EN;
2005                 break;
2006
2007         case sbmac_speed_auto:          /* XXX not implemented */
2008                 /* fall through */
2009         default:
2010                 return 0;
2011         }
2012
2013         /*
2014          * Send the bits back to the hardware
2015          */
2016
2017         __raw_writeq(framecfg, s->sbm_framecfg);
2018         __raw_writeq(cfg, s->sbm_maccfg);
2019
2020         return 1;
2021 }
2022
2023 /**********************************************************************
2024  *  SBMAC_SET_DUPLEX(s,duplex,fc)
2025  *
2026  *  Set Ethernet duplex and flow control options for this MAC
2027  *  Warning: must be called when MAC is off!
2028  *
2029  *  Input parameters:
2030  *         s - sbmac structure
2031  *         duplex - duplex setting (see sbmac_duplex_t)
2032  *         fc - flow control setting (see sbmac_fc_t)
2033  *
2034  *  Return value:
2035  *         1 if ok
2036  *         0 if an invalid parameter combination was specified
2037  ********************************************************************* */
2038
2039 static int sbmac_set_duplex(struct sbmac_softc *s,sbmac_duplex_t duplex,sbmac_fc_t fc)
2040 {
2041         uint64_t cfg;
2042
2043         /*
2044          * Save new current values
2045          */
2046
2047         s->sbm_duplex = duplex;
2048         s->sbm_fc = fc;
2049
2050         if (s->sbm_state == sbmac_state_on)
2051                 return 0;       /* save for next restart */
2052
2053         /*
2054          * Read current register values
2055          */
2056
2057         cfg = __raw_readq(s->sbm_maccfg);
2058
2059         /*
2060          * Mask off the stuff we're about to change
2061          */
2062
2063         cfg &= ~(M_MAC_FC_SEL | M_MAC_FC_CMD | M_MAC_HDX_EN);
2064
2065
2066         switch (duplex) {
2067         case sbmac_duplex_half:
2068                 switch (fc) {
2069                 case sbmac_fc_disabled:
2070                         cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_DISABLED;
2071                         break;
2072
2073                 case sbmac_fc_collision:
2074                         cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENABLED;
2075                         break;
2076
2077                 case sbmac_fc_carrier:
2078                         cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENAB_FALSECARR;
2079                         break;
2080
2081                 case sbmac_fc_auto:             /* XXX not implemented */
2082                         /* fall through */
2083                 case sbmac_fc_frame:            /* not valid in half duplex */
2084                 default:                        /* invalid selection */
2085                         return 0;
2086                 }
2087                 break;
2088
2089         case sbmac_duplex_full:
2090                 switch (fc) {
2091                 case sbmac_fc_disabled:
2092                         cfg |= V_MAC_FC_CMD_DISABLED;
2093                         break;
2094
2095                 case sbmac_fc_frame:
2096                         cfg |= V_MAC_FC_CMD_ENABLED;
2097                         break;
2098
2099                 case sbmac_fc_collision:        /* not valid in full duplex */
2100                 case sbmac_fc_carrier:          /* not valid in full duplex */
2101                 case sbmac_fc_auto:             /* XXX not implemented */
2102                         /* fall through */
2103                 default:
2104                         return 0;
2105                 }
2106                 break;
2107         case sbmac_duplex_auto:
2108                 /* XXX not implemented */
2109                 break;
2110         }
2111
2112         /*
2113          * Send the bits back to the hardware
2114          */
2115
2116         __raw_writeq(cfg, s->sbm_maccfg);
2117
2118         return 1;
2119 }
2120
2121
2122
2123
2124 /**********************************************************************
2125  *  SBMAC_INTR()
2126  *
2127  *  Interrupt handler for MAC interrupts
2128  *
2129  *  Input parameters:
2130  *         MAC structure
2131  *
2132  *  Return value:
2133  *         nothing
2134  ********************************************************************* */
2135 static irqreturn_t sbmac_intr(int irq,void *dev_instance)
2136 {
2137         struct net_device *dev = (struct net_device *) dev_instance;
2138         struct sbmac_softc *sc = netdev_priv(dev);
2139         uint64_t isr;
2140         int handled = 0;
2141
2142         /*
2143          * Read the ISR (this clears the bits in the real
2144          * register, except for counter addr)
2145          */
2146
2147         isr = __raw_readq(sc->sbm_isr) & ~M_MAC_COUNTER_ADDR;
2148
2149         if (isr == 0)
2150                 return IRQ_RETVAL(0);
2151         handled = 1;
2152
2153         /*
2154          * Transmits on channel 0
2155          */
2156
2157         if (isr & (M_MAC_INT_CHANNEL << S_MAC_TX_CH0)) {
2158                 sbdma_tx_process(sc,&(sc->sbm_txdma), 0);
2159 #ifdef CONFIG_NETPOLL_TRAP
2160                 if (netpoll_trap()) {
2161                         if (test_and_clear_bit(__LINK_STATE_XOFF, &dev->state))
2162                                 __netif_schedule(dev);
2163                 }
2164 #endif
2165         }
2166
2167         if (isr & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)) {
2168                 if (netif_rx_schedule_prep(dev)) {
2169                         __raw_writeq(0, sc->sbm_imr);
2170                         __netif_rx_schedule(dev);
2171                         /* Depend on the exit from poll to reenable intr */
2172                 }
2173                 else {
2174                         /* may leave some packets behind */
2175                         sbdma_rx_process(sc,&(sc->sbm_rxdma),
2176                                          SBMAC_MAX_RXDESCR * 2, 0);
2177                 }
2178         }
2179         return IRQ_RETVAL(handled);
2180 }
2181
2182 /**********************************************************************
2183  *  SBMAC_START_TX(skb,dev)
2184  *
2185  *  Start output on the specified interface.  Basically, we
2186  *  queue as many buffers as we can until the ring fills up, or
2187  *  we run off the end of the queue, whichever comes first.
2188  *
2189  *  Input parameters:
2190  *
2191  *
2192  *  Return value:
2193  *         nothing
2194  ********************************************************************* */
2195 static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev)
2196 {
2197         struct sbmac_softc *sc = netdev_priv(dev);
2198
2199         /* lock eth irq */
2200         spin_lock_irq (&sc->sbm_lock);
2201
2202         /*
2203          * Put the buffer on the transmit ring.  If we
2204          * don't have room, stop the queue.
2205          */
2206
2207         if (sbdma_add_txbuffer(&(sc->sbm_txdma),skb)) {
2208                 /* XXX save skb that we could not send */
2209                 netif_stop_queue(dev);
2210                 spin_unlock_irq(&sc->sbm_lock);
2211
2212                 return 1;
2213         }
2214
2215         dev->trans_start = jiffies;
2216
2217         spin_unlock_irq (&sc->sbm_lock);
2218
2219         return 0;
2220 }
2221
2222 /**********************************************************************
2223  *  SBMAC_SETMULTI(sc)
2224  *
2225  *  Reprogram the multicast table into the hardware, given
2226  *  the list of multicasts associated with the interface
2227  *  structure.
2228  *
2229  *  Input parameters:
2230  *         sc - softc
2231  *
2232  *  Return value:
2233  *         nothing
2234  ********************************************************************* */
2235
2236 static void sbmac_setmulti(struct sbmac_softc *sc)
2237 {
2238         uint64_t reg;
2239         volatile void __iomem *port;
2240         int idx;
2241         struct dev_mc_list *mclist;
2242         struct net_device *dev = sc->sbm_dev;
2243
2244         /*
2245          * Clear out entire multicast table.  We do this by nuking
2246          * the entire hash table and all the direct matches except
2247          * the first one, which is used for our station address
2248          */
2249
2250         for (idx = 1; idx < MAC_ADDR_COUNT; idx++) {
2251                 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx*sizeof(uint64_t));
2252                 __raw_writeq(0, port);
2253         }
2254
2255         for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
2256                 port = sc->sbm_base + R_MAC_HASH_BASE+(idx*sizeof(uint64_t));
2257                 __raw_writeq(0, port);
2258         }
2259
2260         /*
2261          * Clear the filter to say we don't want any multicasts.
2262          */
2263
2264         reg = __raw_readq(sc->sbm_rxfilter);
2265         reg &= ~(M_MAC_MCAST_INV | M_MAC_MCAST_EN);
2266         __raw_writeq(reg, sc->sbm_rxfilter);
2267
2268         if (dev->flags & IFF_ALLMULTI) {
2269                 /*
2270                  * Enable ALL multicasts.  Do this by inverting the
2271                  * multicast enable bit.
2272                  */
2273                 reg = __raw_readq(sc->sbm_rxfilter);
2274                 reg |= (M_MAC_MCAST_INV | M_MAC_MCAST_EN);
2275                 __raw_writeq(reg, sc->sbm_rxfilter);
2276                 return;
2277         }
2278
2279
2280         /*
2281          * Progam new multicast entries.  For now, only use the
2282          * perfect filter.  In the future we'll need to use the
2283          * hash filter if the perfect filter overflows
2284          */
2285
2286         /* XXX only using perfect filter for now, need to use hash
2287          * XXX if the table overflows */
2288
2289         idx = 1;                /* skip station address */
2290         mclist = dev->mc_list;
2291         while (mclist && (idx < MAC_ADDR_COUNT)) {
2292                 reg = sbmac_addr2reg(mclist->dmi_addr);
2293                 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx * sizeof(uint64_t));
2294                 __raw_writeq(reg, port);
2295                 idx++;
2296                 mclist = mclist->next;
2297         }
2298
2299         /*
2300          * Enable the "accept multicast bits" if we programmed at least one
2301          * multicast.
2302          */
2303
2304         if (idx > 1) {
2305                 reg = __raw_readq(sc->sbm_rxfilter);
2306                 reg |= M_MAC_MCAST_EN;
2307                 __raw_writeq(reg, sc->sbm_rxfilter);
2308         }
2309 }
2310
2311 #if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR) || defined(SBMAC_ETH3_HWADDR)
2312 /**********************************************************************
2313  *  SBMAC_PARSE_XDIGIT(str)
2314  *
2315  *  Parse a hex digit, returning its value
2316  *
2317  *  Input parameters:
2318  *         str - character
2319  *
2320  *  Return value:
2321  *         hex value, or -1 if invalid
2322  ********************************************************************* */
2323
2324 static int sbmac_parse_xdigit(char str)
2325 {
2326         int digit;
2327
2328         if ((str >= '0') && (str <= '9'))
2329                 digit = str - '0';
2330         else if ((str >= 'a') && (str <= 'f'))
2331                 digit = str - 'a' + 10;
2332         else if ((str >= 'A') && (str <= 'F'))
2333                 digit = str - 'A' + 10;
2334         else
2335                 return -1;
2336
2337         return digit;
2338 }
2339
2340 /**********************************************************************
2341  *  SBMAC_PARSE_HWADDR(str,hwaddr)
2342  *
2343  *  Convert a string in the form xx:xx:xx:xx:xx:xx into a 6-byte
2344  *  Ethernet address.
2345  *
2346  *  Input parameters:
2347  *         str - string
2348  *         hwaddr - pointer to hardware address
2349  *
2350  *  Return value:
2351  *         0 if ok, else -1
2352  ********************************************************************* */
2353
2354 static int sbmac_parse_hwaddr(char *str, unsigned char *hwaddr)
2355 {
2356         int digit1,digit2;
2357         int idx = 6;
2358
2359         while (*str && (idx > 0)) {
2360                 digit1 = sbmac_parse_xdigit(*str);
2361                 if (digit1 < 0)
2362                         return -1;
2363                 str++;
2364                 if (!*str)
2365                         return -1;
2366
2367                 if ((*str == ':') || (*str == '-')) {
2368                         digit2 = digit1;
2369                         digit1 = 0;
2370                 }
2371                 else {
2372                         digit2 = sbmac_parse_xdigit(*str);
2373                         if (digit2 < 0)
2374                                 return -1;
2375                         str++;
2376                 }
2377
2378                 *hwaddr++ = (digit1 << 4) | digit2;
2379                 idx--;
2380
2381                 if (*str == '-')
2382                         str++;
2383                 if (*str == ':')
2384                         str++;
2385         }
2386         return 0;
2387 }
2388 #endif
2389
2390 static int sb1250_change_mtu(struct net_device *_dev, int new_mtu)
2391 {
2392         if (new_mtu >  ENET_PACKET_SIZE)
2393                 return -EINVAL;
2394         _dev->mtu = new_mtu;
2395         printk(KERN_INFO "changing the mtu to %d\n", new_mtu);
2396         return 0;
2397 }
2398
2399 /**********************************************************************
2400  *  SBMAC_INIT(dev)
2401  *
2402  *  Attach routine - init hardware and hook ourselves into linux
2403  *
2404  *  Input parameters:
2405  *         dev - net_device structure
2406  *
2407  *  Return value:
2408  *         status
2409  ********************************************************************* */
2410
2411 static int sbmac_init(struct net_device *dev, int idx)
2412 {
2413         struct sbmac_softc *sc;
2414         unsigned char *eaddr;
2415         uint64_t ea_reg;
2416         int i;
2417         int err;
2418
2419         sc = netdev_priv(dev);
2420
2421         /* Determine controller base address */
2422
2423         sc->sbm_base = IOADDR(dev->base_addr);
2424         sc->sbm_dev = dev;
2425         sc->sbe_idx = idx;
2426
2427         eaddr = sc->sbm_hwaddr;
2428
2429         /*
2430          * Read the ethernet address.  The firwmare left this programmed
2431          * for us in the ethernet address register for each mac.
2432          */
2433
2434         ea_reg = __raw_readq(sc->sbm_base + R_MAC_ETHERNET_ADDR);
2435         __raw_writeq(0, sc->sbm_base + R_MAC_ETHERNET_ADDR);
2436         for (i = 0; i < 6; i++) {
2437                 eaddr[i] = (uint8_t) (ea_reg & 0xFF);
2438                 ea_reg >>= 8;
2439         }
2440
2441         for (i = 0; i < 6; i++) {
2442                 dev->dev_addr[i] = eaddr[i];
2443         }
2444
2445
2446         /*
2447          * Init packet size
2448          */
2449
2450         sc->sbm_buffersize = ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN;
2451
2452         /*
2453          * Initialize context (get pointers to registers and stuff), then
2454          * allocate the memory for the descriptor tables.
2455          */
2456
2457         sbmac_initctx(sc);
2458
2459         /*
2460          * Set up Linux device callins
2461          */
2462
2463         spin_lock_init(&(sc->sbm_lock));
2464
2465         dev->open               = sbmac_open;
2466         dev->hard_start_xmit    = sbmac_start_tx;
2467         dev->stop               = sbmac_close;
2468         dev->get_stats          = sbmac_get_stats;
2469         dev->set_multicast_list = sbmac_set_rx_mode;
2470         dev->do_ioctl           = sbmac_mii_ioctl;
2471         dev->tx_timeout         = sbmac_tx_timeout;
2472         dev->watchdog_timeo     = TX_TIMEOUT;
2473         dev->poll               = sbmac_poll;
2474         dev->weight             = 16;
2475
2476         dev->change_mtu         = sb1250_change_mtu;
2477 #ifdef CONFIG_NET_POLL_CONTROLLER
2478         dev->poll_controller = sbmac_netpoll;
2479 #endif
2480
2481         /* This is needed for PASS2 for Rx H/W checksum feature */
2482         sbmac_set_iphdr_offset(sc);
2483
2484         err = register_netdev(dev);
2485         if (err)
2486                 goto out_uninit;
2487
2488         if (sc->rx_hw_checksum == ENABLE) {
2489                 printk(KERN_INFO "%s: enabling TCP rcv checksum\n",
2490                         sc->sbm_dev->name);
2491         }
2492
2493         /*
2494          * Display Ethernet address (this is called during the config
2495          * process so we need to finish off the config message that
2496          * was being displayed)
2497          */
2498         printk(KERN_INFO
2499                "%s: SiByte Ethernet at 0x%08lX, address: %02X:%02X:%02X:%02X:%02X:%02X\n",
2500                dev->name, dev->base_addr,
2501                eaddr[0],eaddr[1],eaddr[2],eaddr[3],eaddr[4],eaddr[5]);
2502
2503
2504         return 0;
2505
2506 out_uninit:
2507         sbmac_uninitctx(sc);
2508
2509         return err;
2510 }
2511
2512
2513 static int sbmac_open(struct net_device *dev)
2514 {
2515         struct sbmac_softc *sc = netdev_priv(dev);
2516
2517         if (debug > 1) {
2518                 printk(KERN_DEBUG "%s: sbmac_open() irq %d.\n", dev->name, dev->irq);
2519         }
2520
2521         /*
2522          * map/route interrupt (clear status first, in case something
2523          * weird is pending; we haven't initialized the mac registers
2524          * yet)
2525          */
2526
2527         __raw_readq(sc->sbm_isr);
2528         if (request_irq(dev->irq, &sbmac_intr, IRQF_SHARED, dev->name, dev))
2529                 return -EBUSY;
2530
2531         /*
2532          * Probe phy address
2533          */
2534
2535         if(sbmac_mii_probe(dev) == -1) {
2536                 printk("%s: failed to probe PHY.\n", dev->name);
2537                 return -EINVAL;
2538         }
2539
2540         /*
2541          * Configure default speed
2542          */
2543
2544         sbmac_mii_poll(sc,noisy_mii);
2545
2546         /*
2547          * Turn on the channel
2548          */
2549
2550         sbmac_set_channel_state(sc,sbmac_state_on);
2551
2552         /*
2553          * XXX Station address is in dev->dev_addr
2554          */
2555
2556         if (dev->if_port == 0)
2557                 dev->if_port = 0;
2558
2559         netif_start_queue(dev);
2560
2561         sbmac_set_rx_mode(dev);
2562
2563         /* Set the timer to check for link beat. */
2564         init_timer(&sc->sbm_timer);
2565         sc->sbm_timer.expires = jiffies + 2 * HZ/100;
2566         sc->sbm_timer.data = (unsigned long)dev;
2567         sc->sbm_timer.function = &sbmac_timer;
2568         add_timer(&sc->sbm_timer);
2569
2570         return 0;
2571 }
2572
2573 static int sbmac_mii_probe(struct net_device *dev)
2574 {
2575         int i;
2576         struct sbmac_softc *s = netdev_priv(dev);
2577         u16 bmsr, id1, id2;
2578         u32 vendor, device;
2579
2580         for (i=1; i<31; i++) {
2581         bmsr = sbmac_mii_read(s, i, MII_BMSR);
2582                 if (bmsr != 0) {
2583                         s->sbm_phys[0] = i;
2584                         id1 = sbmac_mii_read(s, i, MII_PHYIDR1);
2585                         id2 = sbmac_mii_read(s, i, MII_PHYIDR2);
2586                         vendor = ((u32)id1 << 6) | ((id2 >> 10) & 0x3f);
2587                         device = (id2 >> 4) & 0x3f;
2588
2589                         printk(KERN_INFO "%s: found phy %d, vendor %06x part %02x\n",
2590                                 dev->name, i, vendor, device);
2591                         return i;
2592                 }
2593         }
2594         return -1;
2595 }
2596
2597
2598 static int sbmac_mii_poll(struct sbmac_softc *s,int noisy)
2599 {
2600     int bmsr,bmcr,k1stsr,anlpar;
2601     int chg;
2602     char buffer[100];
2603     char *p = buffer;
2604
2605     /* Read the mode status and mode control registers. */
2606     bmsr = sbmac_mii_read(s,s->sbm_phys[0],MII_BMSR);
2607     bmcr = sbmac_mii_read(s,s->sbm_phys[0],MII_BMCR);
2608
2609     /* get the link partner status */
2610     anlpar = sbmac_mii_read(s,s->sbm_phys[0],MII_ANLPAR);
2611
2612     /* if supported, read the 1000baseT register */
2613     if (bmsr & BMSR_1000BT_XSR) {
2614         k1stsr = sbmac_mii_read(s,s->sbm_phys[0],MII_K1STSR);
2615         }
2616     else {
2617         k1stsr = 0;
2618         }
2619
2620     chg = 0;
2621
2622     if ((bmsr & BMSR_LINKSTAT) == 0) {
2623         /*
2624          * If link status is down, clear out old info so that when
2625          * it comes back up it will force us to reconfigure speed
2626          */
2627         s->sbm_phy_oldbmsr = 0;
2628         s->sbm_phy_oldanlpar = 0;
2629         s->sbm_phy_oldk1stsr = 0;
2630         return 0;
2631         }
2632
2633     if ((s->sbm_phy_oldbmsr != bmsr) ||
2634         (s->sbm_phy_oldanlpar != anlpar) ||
2635         (s->sbm_phy_oldk1stsr != k1stsr)) {
2636         if (debug > 1) {
2637             printk(KERN_DEBUG "%s: bmsr:%x/%x anlpar:%x/%x  k1stsr:%x/%x\n",
2638                s->sbm_dev->name,
2639                s->sbm_phy_oldbmsr,bmsr,
2640                s->sbm_phy_oldanlpar,anlpar,
2641                s->sbm_phy_oldk1stsr,k1stsr);
2642             }
2643         s->sbm_phy_oldbmsr = bmsr;
2644         s->sbm_phy_oldanlpar = anlpar;
2645         s->sbm_phy_oldk1stsr = k1stsr;
2646         chg = 1;
2647         }
2648
2649     if (chg == 0)
2650             return 0;
2651
2652     p += sprintf(p,"Link speed: ");
2653
2654     if (k1stsr & K1STSR_LP1KFD) {
2655         s->sbm_speed = sbmac_speed_1000;
2656         s->sbm_duplex = sbmac_duplex_full;
2657         s->sbm_fc = sbmac_fc_frame;
2658         p += sprintf(p,"1000BaseT FDX");
2659         }
2660     else if (k1stsr & K1STSR_LP1KHD) {
2661         s->sbm_speed = sbmac_speed_1000;
2662         s->sbm_duplex = sbmac_duplex_half;
2663         s->sbm_fc = sbmac_fc_disabled;
2664         p += sprintf(p,"1000BaseT HDX");
2665         }
2666     else if (anlpar & ANLPAR_TXFD) {
2667         s->sbm_speed = sbmac_speed_100;
2668         s->sbm_duplex = sbmac_duplex_full;
2669         s->sbm_fc = (anlpar & ANLPAR_PAUSE) ? sbmac_fc_frame : sbmac_fc_disabled;
2670         p += sprintf(p,"100BaseT FDX");
2671         }
2672     else if (anlpar & ANLPAR_TXHD) {
2673         s->sbm_speed = sbmac_speed_100;
2674         s->sbm_duplex = sbmac_duplex_half;
2675         s->sbm_fc = sbmac_fc_disabled;
2676         p += sprintf(p,"100BaseT HDX");
2677         }
2678     else if (anlpar & ANLPAR_10FD) {
2679         s->sbm_speed = sbmac_speed_10;
2680         s->sbm_duplex = sbmac_duplex_full;
2681         s->sbm_fc = sbmac_fc_frame;
2682         p += sprintf(p,"10BaseT FDX");
2683         }
2684     else if (anlpar & ANLPAR_10HD) {
2685         s->sbm_speed = sbmac_speed_10;
2686         s->sbm_duplex = sbmac_duplex_half;
2687         s->sbm_fc = sbmac_fc_collision;
2688         p += sprintf(p,"10BaseT HDX");
2689         }
2690     else {
2691         p += sprintf(p,"Unknown");
2692         }
2693
2694     if (noisy) {
2695             printk(KERN_INFO "%s: %s\n",s->sbm_dev->name,buffer);
2696             }
2697
2698     return 1;
2699 }
2700
2701
2702 static void sbmac_timer(unsigned long data)
2703 {
2704         struct net_device *dev = (struct net_device *)data;
2705         struct sbmac_softc *sc = netdev_priv(dev);
2706         int next_tick = HZ;
2707         int mii_status;
2708
2709         spin_lock_irq (&sc->sbm_lock);
2710
2711         /* make IFF_RUNNING follow the MII status bit "Link established" */
2712         mii_status = sbmac_mii_read(sc, sc->sbm_phys[0], MII_BMSR);
2713
2714         if ( (mii_status & BMSR_LINKSTAT) != (sc->sbm_phy_oldlinkstat) ) {
2715                 sc->sbm_phy_oldlinkstat = mii_status & BMSR_LINKSTAT;
2716                 if (mii_status & BMSR_LINKSTAT) {
2717                         netif_carrier_on(dev);
2718                 }
2719                 else {
2720                         netif_carrier_off(dev);
2721                 }
2722         }
2723
2724         /*
2725          * Poll the PHY to see what speed we should be running at
2726          */
2727
2728         if (sbmac_mii_poll(sc,noisy_mii)) {
2729                 if (sc->sbm_state != sbmac_state_off) {
2730                         /*
2731                          * something changed, restart the channel
2732                          */
2733                         if (debug > 1) {
2734                                 printk("%s: restarting channel because speed changed\n",
2735                                        sc->sbm_dev->name);
2736                         }
2737                         sbmac_channel_stop(sc);
2738                         sbmac_channel_start(sc);
2739                 }
2740         }
2741
2742         spin_unlock_irq (&sc->sbm_lock);
2743
2744         sc->sbm_timer.expires = jiffies + next_tick;
2745         add_timer(&sc->sbm_timer);
2746 }
2747
2748
2749 static void sbmac_tx_timeout (struct net_device *dev)
2750 {
2751         struct sbmac_softc *sc = netdev_priv(dev);
2752
2753         spin_lock_irq (&sc->sbm_lock);
2754
2755
2756         dev->trans_start = jiffies;
2757         sc->sbm_stats.tx_errors++;
2758
2759         spin_unlock_irq (&sc->sbm_lock);
2760
2761         printk (KERN_WARNING "%s: Transmit timed out\n",dev->name);
2762 }
2763
2764
2765
2766
2767 static struct net_device_stats *sbmac_get_stats(struct net_device *dev)
2768 {
2769         struct sbmac_softc *sc = netdev_priv(dev);
2770         unsigned long flags;
2771
2772         spin_lock_irqsave(&sc->sbm_lock, flags);
2773
2774         /* XXX update other stats here */
2775
2776         spin_unlock_irqrestore(&sc->sbm_lock, flags);
2777
2778         return &sc->sbm_stats;
2779 }
2780
2781
2782
2783 static void sbmac_set_rx_mode(struct net_device *dev)
2784 {
2785         unsigned long flags;
2786         struct sbmac_softc *sc = netdev_priv(dev);
2787
2788         spin_lock_irqsave(&sc->sbm_lock, flags);
2789         if ((dev->flags ^ sc->sbm_devflags) & IFF_PROMISC) {
2790                 /*
2791                  * Promiscuous changed.
2792                  */
2793
2794                 if (dev->flags & IFF_PROMISC) {
2795                         sbmac_promiscuous_mode(sc,1);
2796                 }
2797                 else {
2798                         sbmac_promiscuous_mode(sc,0);
2799                 }
2800         }
2801         spin_unlock_irqrestore(&sc->sbm_lock, flags);
2802
2803         /*
2804          * Program the multicasts.  Do this every time.
2805          */
2806
2807         sbmac_setmulti(sc);
2808
2809 }
2810
2811 static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2812 {
2813         struct sbmac_softc *sc = netdev_priv(dev);
2814         u16 *data = (u16 *)&rq->ifr_ifru;
2815         unsigned long flags;
2816         int retval;
2817
2818         spin_lock_irqsave(&sc->sbm_lock, flags);
2819         retval = 0;
2820
2821         switch(cmd) {
2822         case SIOCDEVPRIVATE:            /* Get the address of the PHY in use. */
2823                 data[0] = sc->sbm_phys[0] & 0x1f;
2824                 /* Fall Through */
2825         case SIOCDEVPRIVATE+1:          /* Read the specified MII register. */
2826                 data[3] = sbmac_mii_read(sc, data[0] & 0x1f, data[1] & 0x1f);
2827                 break;
2828         case SIOCDEVPRIVATE+2:          /* Write the specified MII register */
2829                 if (!capable(CAP_NET_ADMIN)) {
2830                         retval = -EPERM;
2831                         break;
2832                 }
2833                 if (debug > 1) {
2834                     printk(KERN_DEBUG "%s: sbmac_mii_ioctl: write %02X %02X %02X\n",dev->name,
2835                        data[0],data[1],data[2]);
2836                     }
2837                 sbmac_mii_write(sc, data[0] & 0x1f, data[1] & 0x1f, data[2]);
2838                 break;
2839         default:
2840                 retval = -EOPNOTSUPP;
2841         }
2842
2843         spin_unlock_irqrestore(&sc->sbm_lock, flags);
2844         return retval;
2845 }
2846
2847 static int sbmac_close(struct net_device *dev)
2848 {
2849         struct sbmac_softc *sc = netdev_priv(dev);
2850         unsigned long flags;
2851         int irq;
2852
2853         sbmac_set_channel_state(sc,sbmac_state_off);
2854
2855         del_timer_sync(&sc->sbm_timer);
2856
2857         spin_lock_irqsave(&sc->sbm_lock, flags);
2858
2859         netif_stop_queue(dev);
2860
2861         if (debug > 1) {
2862                 printk(KERN_DEBUG "%s: Shutting down ethercard\n",dev->name);
2863         }
2864
2865         spin_unlock_irqrestore(&sc->sbm_lock, flags);
2866
2867         irq = dev->irq;
2868         synchronize_irq(irq);
2869         free_irq(irq, dev);
2870
2871         sbdma_emptyring(&(sc->sbm_txdma));
2872         sbdma_emptyring(&(sc->sbm_rxdma));
2873
2874         return 0;
2875 }
2876
2877 static int sbmac_poll(struct net_device *dev, int *budget)
2878 {
2879         int work_to_do;
2880         int work_done;
2881         struct sbmac_softc *sc = netdev_priv(dev);
2882
2883         work_to_do = min(*budget, dev->quota);
2884         work_done = sbdma_rx_process(sc, &(sc->sbm_rxdma), work_to_do, 1);
2885
2886         if (work_done > work_to_do)
2887                 printk(KERN_ERR "%s exceeded work_to_do budget=%d quota=%d work-done=%d\n",
2888                        sc->sbm_dev->name, *budget, dev->quota, work_done);
2889
2890         sbdma_tx_process(sc, &(sc->sbm_txdma), 1);
2891
2892         *budget -= work_done;
2893         dev->quota -= work_done;
2894
2895         if (work_done < work_to_do) {
2896                 netif_rx_complete(dev);
2897
2898 #ifdef CONFIG_SBMAC_COALESCE
2899                 __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
2900                              ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0),
2901                              sc->sbm_imr);
2902 #else
2903                 __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
2904                              (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), sc->sbm_imr);
2905 #endif
2906         }
2907
2908         return (work_done >= work_to_do);
2909 }
2910
2911 #if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR) || defined(SBMAC_ETH3_HWADDR)
2912 static void
2913 sbmac_setup_hwaddr(int chan,char *addr)
2914 {
2915         uint8_t eaddr[6];
2916         uint64_t val;
2917         unsigned long port;
2918
2919         port = A_MAC_CHANNEL_BASE(chan);
2920         sbmac_parse_hwaddr(addr,eaddr);
2921         val = sbmac_addr2reg(eaddr);
2922         __raw_writeq(val, IOADDR(port+R_MAC_ETHERNET_ADDR));
2923         val = __raw_readq(IOADDR(port+R_MAC_ETHERNET_ADDR));
2924 }
2925 #endif
2926
2927 static struct net_device *dev_sbmac[MAX_UNITS];
2928
2929 static int __init
2930 sbmac_init_module(void)
2931 {
2932         int idx;
2933         struct net_device *dev;
2934         unsigned long port;
2935         int chip_max_units;
2936
2937         /* Set the number of available units based on the SOC type.  */
2938         switch (soc_type) {
2939         case K_SYS_SOC_TYPE_BCM1250:
2940         case K_SYS_SOC_TYPE_BCM1250_ALT:
2941                 chip_max_units = 3;
2942                 break;
2943         case K_SYS_SOC_TYPE_BCM1120:
2944         case K_SYS_SOC_TYPE_BCM1125:
2945         case K_SYS_SOC_TYPE_BCM1125H:
2946         case K_SYS_SOC_TYPE_BCM1250_ALT2: /* Hybrid */
2947                 chip_max_units = 2;
2948                 break;
2949         case K_SYS_SOC_TYPE_BCM1x55:
2950         case K_SYS_SOC_TYPE_BCM1x80:
2951                 chip_max_units = 4;
2952                 break;
2953         default:
2954                 chip_max_units = 0;
2955                 break;
2956         }
2957         if (chip_max_units > MAX_UNITS)
2958                 chip_max_units = MAX_UNITS;
2959
2960         /*
2961          * For bringup when not using the firmware, we can pre-fill
2962          * the MAC addresses using the environment variables
2963          * specified in this file (or maybe from the config file?)
2964          */
2965 #ifdef SBMAC_ETH0_HWADDR
2966         if (chip_max_units > 0)
2967           sbmac_setup_hwaddr(0,SBMAC_ETH0_HWADDR);
2968 #endif
2969 #ifdef SBMAC_ETH1_HWADDR
2970         if (chip_max_units > 1)
2971           sbmac_setup_hwaddr(1,SBMAC_ETH1_HWADDR);
2972 #endif
2973 #ifdef SBMAC_ETH2_HWADDR
2974         if (chip_max_units > 2)
2975           sbmac_setup_hwaddr(2,SBMAC_ETH2_HWADDR);
2976 #endif
2977 #ifdef SBMAC_ETH3_HWADDR
2978         if (chip_max_units > 3)
2979           sbmac_setup_hwaddr(3,SBMAC_ETH3_HWADDR);
2980 #endif
2981
2982         /*
2983          * Walk through the Ethernet controllers and find
2984          * those who have their MAC addresses set.
2985          */
2986         for (idx = 0; idx < chip_max_units; idx++) {
2987
2988                 /*
2989                  * This is the base address of the MAC.
2990                  */
2991
2992                 port = A_MAC_CHANNEL_BASE(idx);
2993
2994                 /*
2995                  * The R_MAC_ETHERNET_ADDR register will be set to some nonzero
2996                  * value for us by the firmware if we are going to use this MAC.
2997                  * If we find a zero, skip this MAC.
2998                  */
2999
3000                 sbmac_orig_hwaddr[idx] = __raw_readq(IOADDR(port+R_MAC_ETHERNET_ADDR));
3001                 if (sbmac_orig_hwaddr[idx] == 0) {
3002                         printk(KERN_DEBUG "sbmac: not configuring MAC at "
3003                                "%lx\n", port);
3004                     continue;
3005                 }
3006
3007                 /*
3008                  * Okay, cool.  Initialize this MAC.
3009                  */
3010
3011                 dev = alloc_etherdev(sizeof(struct sbmac_softc));
3012                 if (!dev)
3013                         return -ENOMEM;
3014
3015                 printk(KERN_DEBUG "sbmac: configuring MAC at %lx\n", port);
3016
3017                 dev->irq = UNIT_INT(idx);
3018                 dev->base_addr = port;
3019                 dev->mem_end = 0;
3020                 if (sbmac_init(dev, idx)) {
3021                         port = A_MAC_CHANNEL_BASE(idx);
3022                         __raw_writeq(sbmac_orig_hwaddr[idx], IOADDR(port+R_MAC_ETHERNET_ADDR));
3023                         free_netdev(dev);
3024                         continue;
3025                 }
3026                 dev_sbmac[idx] = dev;
3027         }
3028         return 0;
3029 }
3030
3031
3032 static void __exit
3033 sbmac_cleanup_module(void)
3034 {
3035         struct net_device *dev;
3036         int idx;
3037
3038         for (idx = 0; idx < MAX_UNITS; idx++) {
3039                 struct sbmac_softc *sc;
3040                 dev = dev_sbmac[idx];
3041                 if (!dev)
3042                         continue;
3043
3044                 sc = netdev_priv(dev);
3045                 unregister_netdev(dev);
3046                 sbmac_uninitctx(sc);
3047                 free_netdev(dev);
3048         }
3049 }
3050
3051 module_init(sbmac_init_module);
3052 module_exit(sbmac_cleanup_module);