drivers/net/s2io.c

   1 /************************************************************************
   2  * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
   3  * Copyright(c) 2002-2007 Neterion Inc.
   4
   5  * This software may be used and distributed according to the terms of
   6  * the GNU General Public License (GPL), incorporated herein by reference.
   7  * Drivers based on or derived from this code fall under the GPL and must
   8  * retain the authorship, copyright and license notice.  This file is not
   9  * a complete program and may only be used when the entire operating
  10  * system is licensed under the GPL.
  11  * See the file COPYING in this distribution for more information.
  12  *
  13  * Credits:
  14  * Jeff Garzik          : For pointing out the improper error condition
  15  *                        check in the s2io_xmit routine and also some
  16  *                        issues in the Tx watch dog function. Also for
  17  *                        patiently answering all those innumerable
  18  *                        questions regaring the 2.6 porting issues.
  19  * Stephen Hemminger    : Providing proper 2.6 porting mechanism for some
  20  *                        macros available only in 2.6 Kernel.
  21  * Francois Romieu      : For pointing out all code part that were
  22  *                        deprecated and also styling related comments.
  23  * Grant Grundler       : For helping me get rid of some Architecture
  24  *                        dependent code.
  25  * Christopher Hellwig  : Some more 2.6 specific issues in the driver.
  26  *
  27  * The module loadable parameters that are supported by the driver and a brief
  28  * explaination of all the variables.
  29  *
  30  * rx_ring_num : This can be used to program the number of receive rings used
  31  * in the driver.
  32  * rx_ring_sz: This defines the number of receive blocks each ring can have.
  33  *     This is also an array of size 8.
  34  * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
  35  *              values are 1, 2 and 3.
  36  * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
  37  * tx_fifo_len: This too is an array of 8. Each element defines the number of
  38  * Tx descriptors that can be associated with each corresponding FIFO.
  39  * intr_type: This defines the type of interrupt. The values can be 0(INTA),
  40  *     1(MSI), 2(MSI_X). Default value is '0(INTA)'
  41  * lro: Specifies whether to enable Large Receive Offload (LRO) or not.
  42  *     Possible values '1' for enable '0' for disable. Default is '0'
  43  * lro_max_pkts: This parameter defines maximum number of packets can be
  44  *     aggregated as a single large packet
  45  * napi: This parameter used to enable/disable NAPI (polling Rx)
  46  *     Possible values '1' for enable and '0' for disable. Default is '1'
  47  * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
  48  *      Possible values '1' for enable and '0' for disable. Default is '0'
  49  * vlan_tag_strip: This can be used to enable or disable vlan stripping.
  50  *                 Possible values '1' for enable , '0' for disable.
  51  *                 Default is '2' - which means disable in promisc mode
  52  *                 and enable in non-promiscuous mode.
  53  ************************************************************************/
  54
  55 #include <linux/module.h>
  56 #include <linux/types.h>
  57 #include <linux/errno.h>
  58 #include <linux/ioport.h>
  59 #include <linux/pci.h>
  60 #include <linux/dma-mapping.h>
  61 #include <linux/kernel.h>
  62 #include <linux/netdevice.h>
  63 #include <linux/etherdevice.h>
  64 #include <linux/skbuff.h>
  65 #include <linux/init.h>
  66 #include <linux/delay.h>
  67 #include <linux/stddef.h>
  68 #include <linux/ioctl.h>
  69 #include <linux/timex.h>
  70 #include <linux/ethtool.h>
  71 #include <linux/workqueue.h>
  72 #include <linux/if_vlan.h>
  73 #include <linux/ip.h>
  74 #include <linux/tcp.h>
  75 #include <net/tcp.h>
  76
  77 #include <asm/system.h>
  78 #include <asm/uaccess.h>
  79 #include <asm/io.h>
  80 #include <asm/div64.h>
  81 #include <asm/irq.h>
  82
  83 /* local include */
  84 #include "s2io.h"
  85 #include "s2io-regs.h"
  86
  87 #define DRV_VERSION "2.0.23.1"
  88
  89 /* S2io Driver name & version. */
  90 static char s2io_driver_name[] = "Neterion";
  91 static char s2io_driver_version[] = DRV_VERSION;
  92
  93 static int rxd_size[4] = {32,48,48,64};
  94 static int rxd_count[4] = {127,85,85,63};
  95
  96 static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
  97 {
  98         int ret;
  99
 100         ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
 101                 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
 102
 103         return ret;
 104 }
 105
 106 /*
 107  * Cards with following subsystem_id have a link state indication
 108  * problem, 600B, 600C, 600D, 640B, 640C and 640D.
 109  * macro below identifies these cards given the subsystem_id.
 110  */
 111 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
 112         (dev_type == XFRAME_I_DEVICE) ?                 \
 113                 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
 114                  ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
 115
 116 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
 117                                       ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
 118 #define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
 119 #define PANIC   1
 120 #define LOW     2
 121 static inline int rx_buffer_level(struct s2io_nic * sp, int rxb_size, int ring)
 122 {
 123         struct mac_info *mac_control;
 124
 125         mac_control = &sp->mac_control;
 126         if (rxb_size <= rxd_count[sp->rxd_mode])
 127                 return PANIC;
 128         else if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16)
 129                 return  LOW;
 130         return 0;
 131 }
 132
 133 /* Ethtool related variables and Macros. */
 134 static char s2io_gstrings[][ETH_GSTRING_LEN] = {
 135         "Register test\t(offline)",
 136         "Eeprom test\t(offline)",
 137         "Link test\t(online)",
 138         "RLDRAM test\t(offline)",
 139         "BIST Test\t(offline)"
 140 };
 141
 142 static char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
 143         {"tmac_frms"},
 144         {"tmac_data_octets"},
 145         {"tmac_drop_frms"},
 146         {"tmac_mcst_frms"},
 147         {"tmac_bcst_frms"},
 148         {"tmac_pause_ctrl_frms"},
 149         {"tmac_ttl_octets"},
 150         {"tmac_ucst_frms"},
 151         {"tmac_nucst_frms"},
 152         {"tmac_any_err_frms"},
 153         {"tmac_ttl_less_fb_octets"},
 154         {"tmac_vld_ip_octets"},
 155         {"tmac_vld_ip"},
 156         {"tmac_drop_ip"},
 157         {"tmac_icmp"},
 158         {"tmac_rst_tcp"},
 159         {"tmac_tcp"},
 160         {"tmac_udp"},
 161         {"rmac_vld_frms"},
 162         {"rmac_data_octets"},
 163         {"rmac_fcs_err_frms"},
 164         {"rmac_drop_frms"},
 165         {"rmac_vld_mcst_frms"},
 166         {"rmac_vld_bcst_frms"},
 167         {"rmac_in_rng_len_err_frms"},
 168         {"rmac_out_rng_len_err_frms"},
 169         {"rmac_long_frms"},
 170         {"rmac_pause_ctrl_frms"},
 171         {"rmac_unsup_ctrl_frms"},
 172         {"rmac_ttl_octets"},
 173         {"rmac_accepted_ucst_frms"},
 174         {"rmac_accepted_nucst_frms"},
 175         {"rmac_discarded_frms"},
 176         {"rmac_drop_events"},
 177         {"rmac_ttl_less_fb_octets"},
 178         {"rmac_ttl_frms"},
 179         {"rmac_usized_frms"},
 180         {"rmac_osized_frms"},
 181         {"rmac_frag_frms"},
 182         {"rmac_jabber_frms"},
 183         {"rmac_ttl_64_frms"},
 184         {"rmac_ttl_65_127_frms"},
 185         {"rmac_ttl_128_255_frms"},
 186         {"rmac_ttl_256_511_frms"},
 187         {"rmac_ttl_512_1023_frms"},
 188         {"rmac_ttl_1024_1518_frms"},
 189         {"rmac_ip"},
 190         {"rmac_ip_octets"},
 191         {"rmac_hdr_err_ip"},
 192         {"rmac_drop_ip"},
 193         {"rmac_icmp"},
 194         {"rmac_tcp"},
 195         {"rmac_udp"},
 196         {"rmac_err_drp_udp"},
 197         {"rmac_xgmii_err_sym"},
 198         {"rmac_frms_q0"},
 199         {"rmac_frms_q1"},
 200         {"rmac_frms_q2"},
 201         {"rmac_frms_q3"},
 202         {"rmac_frms_q4"},
 203         {"rmac_frms_q5"},
 204         {"rmac_frms_q6"},
 205         {"rmac_frms_q7"},
 206         {"rmac_full_q0"},
 207         {"rmac_full_q1"},
 208         {"rmac_full_q2"},
 209         {"rmac_full_q3"},
 210         {"rmac_full_q4"},
 211         {"rmac_full_q5"},
 212         {"rmac_full_q6"},
 213         {"rmac_full_q7"},
 214         {"rmac_pause_cnt"},
 215         {"rmac_xgmii_data_err_cnt"},
 216         {"rmac_xgmii_ctrl_err_cnt"},
 217         {"rmac_accepted_ip"},
 218         {"rmac_err_tcp"},
 219         {"rd_req_cnt"},
 220         {"new_rd_req_cnt"},
 221         {"new_rd_req_rtry_cnt"},
 222         {"rd_rtry_cnt"},
 223         {"wr_rtry_rd_ack_cnt"},
 224         {"wr_req_cnt"},
 225         {"new_wr_req_cnt"},
 226         {"new_wr_req_rtry_cnt"},
 227         {"wr_rtry_cnt"},
 228         {"wr_disc_cnt"},
 229         {"rd_rtry_wr_ack_cnt"},
 230         {"txp_wr_cnt"},
 231         {"txd_rd_cnt"},
 232         {"txd_wr_cnt"},
 233         {"rxd_rd_cnt"},
 234         {"rxd_wr_cnt"},
 235         {"txf_rd_cnt"},
 236         {"rxf_wr_cnt"}
 237 };
 238
 239 static char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
 240         {"rmac_ttl_1519_4095_frms"},
 241         {"rmac_ttl_4096_8191_frms"},
 242         {"rmac_ttl_8192_max_frms"},
 243         {"rmac_ttl_gt_max_frms"},
 244         {"rmac_osized_alt_frms"},
 245         {"rmac_jabber_alt_frms"},
 246         {"rmac_gt_max_alt_frms"},
 247         {"rmac_vlan_frms"},
 248         {"rmac_len_discard"},
 249         {"rmac_fcs_discard"},
 250         {"rmac_pf_discard"},
 251         {"rmac_da_discard"},
 252         {"rmac_red_discard"},
 253         {"rmac_rts_discard"},
 254         {"rmac_ingm_full_discard"},
 255         {"link_fault_cnt"}
 256 };
 257
 258 static char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
 259         {"\n DRIVER STATISTICS"},
 260         {"single_bit_ecc_errs"},
 261         {"double_bit_ecc_errs"},
 262         {"parity_err_cnt"},
 263         {"serious_err_cnt"},
 264         {"soft_reset_cnt"},
 265         {"fifo_full_cnt"},
 266         {"ring_full_cnt"},
 267         ("alarm_transceiver_temp_high"),
 268         ("alarm_transceiver_temp_low"),
 269         ("alarm_laser_bias_current_high"),
 270         ("alarm_laser_bias_current_low"),
 271         ("alarm_laser_output_power_high"),
 272         ("alarm_laser_output_power_low"),
 273         ("warn_transceiver_temp_high"),
 274         ("warn_transceiver_temp_low"),
 275         ("warn_laser_bias_current_high"),
 276         ("warn_laser_bias_current_low"),
 277         ("warn_laser_output_power_high"),
 278         ("warn_laser_output_power_low"),
 279         ("lro_aggregated_pkts"),
 280         ("lro_flush_both_count"),
 281         ("lro_out_of_sequence_pkts"),
 282         ("lro_flush_due_to_max_pkts"),
 283         ("lro_avg_aggr_pkts"),
 284         ("mem_alloc_fail_cnt"),
 285         ("watchdog_timer_cnt"),
 286         ("mem_allocated"),
 287         ("mem_freed"),
 288         ("link_up_cnt"),
 289         ("link_down_cnt"),
 290         ("link_up_time"),
 291         ("link_down_time"),
 292         ("tx_tcode_buf_abort_cnt"),
 293         ("tx_tcode_desc_abort_cnt"),
 294         ("tx_tcode_parity_err_cnt"),
 295         ("tx_tcode_link_loss_cnt"),
 296         ("tx_tcode_list_proc_err_cnt"),
 297         ("rx_tcode_parity_err_cnt"),
 298         ("rx_tcode_abort_cnt"),
 299         ("rx_tcode_parity_abort_cnt"),
 300         ("rx_tcode_rda_fail_cnt"),
 301         ("rx_tcode_unkn_prot_cnt"),
 302         ("rx_tcode_fcs_err_cnt"),
 303         ("rx_tcode_buf_size_err_cnt"),
 304         ("rx_tcode_rxd_corrupt_cnt"),
 305         ("rx_tcode_unkn_err_cnt")
 306 };
 307
 308 #define S2IO_XENA_STAT_LEN sizeof(ethtool_xena_stats_keys)/ ETH_GSTRING_LEN
 309 #define S2IO_ENHANCED_STAT_LEN sizeof(ethtool_enhanced_stats_keys)/ \
 310                                         ETH_GSTRING_LEN
 311 #define S2IO_DRIVER_STAT_LEN sizeof(ethtool_driver_stats_keys)/ ETH_GSTRING_LEN
 312
 313 #define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN )
 314 #define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN )
 315
 316 #define XFRAME_I_STAT_STRINGS_LEN ( XFRAME_I_STAT_LEN * ETH_GSTRING_LEN )
 317 #define XFRAME_II_STAT_STRINGS_LEN ( XFRAME_II_STAT_LEN * ETH_GSTRING_LEN )
 318
 319 #define S2IO_TEST_LEN   sizeof(s2io_gstrings) / ETH_GSTRING_LEN
 320 #define S2IO_STRINGS_LEN        S2IO_TEST_LEN * ETH_GSTRING_LEN
 321
 322 #define S2IO_TIMER_CONF(timer, handle, arg, exp)                \
 323                         init_timer(&timer);                     \
 324                         timer.function = handle;                \
 325                         timer.data = (unsigned long) arg;       \
 326                         mod_timer(&timer, (jiffies + exp))      \
 327
 328 /* Add the vlan */
 329 static void s2io_vlan_rx_register(struct net_device *dev,
 330                                         struct vlan_group *grp)
 331 {
 332         struct s2io_nic *nic = dev->priv;
 333         unsigned long flags;
 334
 335         spin_lock_irqsave(&nic->tx_lock, flags);
 336         nic->vlgrp = grp;
 337         spin_unlock_irqrestore(&nic->tx_lock, flags);
 338 }
 339
 340 /* A flag indicating whether 'RX_PA_CFG_STRIP_VLAN_TAG' bit is set or not */
 341 static int vlan_strip_flag;
 342
 343 /* Unregister the vlan */
 344 static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid)
 345 {
 346         struct s2io_nic *nic = dev->priv;
 347         unsigned long flags;
 348
 349         spin_lock_irqsave(&nic->tx_lock, flags);
 350         vlan_group_set_device(nic->vlgrp, vid, NULL);
 351         spin_unlock_irqrestore(&nic->tx_lock, flags);
 352 }
 353
 354 /*
 355  * Constants to be programmed into the Xena's registers, to configure
 356  * the XAUI.
 357  */
 358
 359 #define END_SIGN        0x0
 360 static const u64 herc_act_dtx_cfg[] = {
 361         /* Set address */
 362         0x8000051536750000ULL, 0x80000515367500E0ULL,
 363         /* Write data */
 364         0x8000051536750004ULL, 0x80000515367500E4ULL,
 365         /* Set address */
 366         0x80010515003F0000ULL, 0x80010515003F00E0ULL,
 367         /* Write data */
 368         0x80010515003F0004ULL, 0x80010515003F00E4ULL,
 369         /* Set address */
 370         0x801205150D440000ULL, 0x801205150D4400E0ULL,
 371         /* Write data */
 372         0x801205150D440004ULL, 0x801205150D4400E4ULL,
 373         /* Set address */
 374         0x80020515F2100000ULL, 0x80020515F21000E0ULL,
 375         /* Write data */
 376         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
 377         /* Done */
 378         END_SIGN
 379 };
 380
 381 static const u64 xena_dtx_cfg[] = {
 382         /* Set address */
 383         0x8000051500000000ULL, 0x80000515000000E0ULL,
 384         /* Write data */
 385         0x80000515D9350004ULL, 0x80000515D93500E4ULL,
 386         /* Set address */
 387         0x8001051500000000ULL, 0x80010515000000E0ULL,
 388         /* Write data */
 389         0x80010515001E0004ULL, 0x80010515001E00E4ULL,
 390         /* Set address */
 391         0x8002051500000000ULL, 0x80020515000000E0ULL,
 392         /* Write data */
 393         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
 394         END_SIGN
 395 };
 396
 397 /*
 398  * Constants for Fixing the MacAddress problem seen mostly on
 399  * Alpha machines.
 400  */
 401 static const u64 fix_mac[] = {
 402         0x0060000000000000ULL, 0x0060600000000000ULL,
 403         0x0040600000000000ULL, 0x0000600000000000ULL,
 404         0x0020600000000000ULL, 0x0060600000000000ULL,
 405         0x0020600000000000ULL, 0x0060600000000000ULL,
 406         0x0020600000000000ULL, 0x0060600000000000ULL,
 407         0x0020600000000000ULL, 0x0060600000000000ULL,
 408         0x0020600000000000ULL, 0x0060600000000000ULL,
 409         0x0020600000000000ULL, 0x0060600000000000ULL,
 410         0x0020600000000000ULL, 0x0060600000000000ULL,
 411         0x0020600000000000ULL, 0x0060600000000000ULL,
 412         0x0020600000000000ULL, 0x0060600000000000ULL,
 413         0x0020600000000000ULL, 0x0060600000000000ULL,
 414         0x0020600000000000ULL, 0x0000600000000000ULL,
 415         0x0040600000000000ULL, 0x0060600000000000ULL,
 416         END_SIGN
 417 };
 418
 419 MODULE_LICENSE("GPL");
 420 MODULE_VERSION(DRV_VERSION);
 421
 422
 423 /* Module Loadable parameters. */
 424 S2IO_PARM_INT(tx_fifo_num, 1);
 425 S2IO_PARM_INT(rx_ring_num, 1);
 426
 427
 428 S2IO_PARM_INT(rx_ring_mode, 1);
 429 S2IO_PARM_INT(use_continuous_tx_intrs, 1);
 430 S2IO_PARM_INT(rmac_pause_time, 0x100);
 431 S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
 432 S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
 433 S2IO_PARM_INT(shared_splits, 0);
 434 S2IO_PARM_INT(tmac_util_period, 5);
 435 S2IO_PARM_INT(rmac_util_period, 5);
 436 S2IO_PARM_INT(bimodal, 0);
 437 S2IO_PARM_INT(l3l4hdr_size, 128);
 438 /* Frequency of Rx desc syncs expressed as power of 2 */
 439 S2IO_PARM_INT(rxsync_frequency, 3);
 440 /* Interrupt type. Values can be 0(INTA), 1(MSI), 2(MSI_X) */
 441 S2IO_PARM_INT(intr_type, 0);
 442 /* Large receive offload feature */
 443 S2IO_PARM_INT(lro, 0);
 444 /* Max pkts to be aggregated by LRO at one time. If not specified,
 445  * aggregation happens until we hit max IP pkt size(64K)
 446  */
 447 S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
 448 S2IO_PARM_INT(indicate_max_pkts, 0);
 449
 450 S2IO_PARM_INT(napi, 1);
 451 S2IO_PARM_INT(ufo, 0);
 452 S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
 453
 454 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
 455     {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
 456 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
 457     {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
 458 static unsigned int rts_frm_len[MAX_RX_RINGS] =
 459     {[0 ...(MAX_RX_RINGS - 1)] = 0 };
 460
 461 module_param_array(tx_fifo_len, uint, NULL, 0);
 462 module_param_array(rx_ring_sz, uint, NULL, 0);
 463 module_param_array(rts_frm_len, uint, NULL, 0);
 464
 465 /*
 466  * S2IO device table.
 467  * This table lists all the devices that this driver supports.
 468  */
 469 static struct pci_device_id s2io_tbl[] __devinitdata = {
 470         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
 471          PCI_ANY_ID, PCI_ANY_ID},
 472         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
 473          PCI_ANY_ID, PCI_ANY_ID},
 474         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
 475          PCI_ANY_ID, PCI_ANY_ID},
 476         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
 477          PCI_ANY_ID, PCI_ANY_ID},
 478         {0,}
 479 };
 480
 481 MODULE_DEVICE_TABLE(pci, s2io_tbl);
 482
 483 static struct pci_driver s2io_driver = {
 484       .name = "S2IO",
 485       .id_table = s2io_tbl,
 486       .probe = s2io_init_nic,
 487       .remove = __devexit_p(s2io_rem_nic),
 488 };
 489
 490 /* A simplifier macro used both by init and free shared_mem Fns(). */
 491 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
 492
 493 /**
 494  * init_shared_mem - Allocation and Initialization of Memory
 495  * @nic: Device private variable.
 496  * Description: The function allocates all the memory areas shared
 497  * between the NIC and the driver. This includes Tx descriptors,
 498  * Rx descriptors and the statistics block.
 499  */
 500
 501 static int init_shared_mem(struct s2io_nic *nic)
 502 {
 503         u32 size;
 504         void *tmp_v_addr, *tmp_v_addr_next;
 505         dma_addr_t tmp_p_addr, tmp_p_addr_next;
 506         struct RxD_block *pre_rxd_blk = NULL;
 507         int i, j, blk_cnt;
 508         int lst_size, lst_per_page;
 509         struct net_device *dev = nic->dev;
 510         unsigned long tmp;
 511         struct buffAdd *ba;
 512
 513         struct mac_info *mac_control;
 514         struct config_param *config;
 515         unsigned long long mem_allocated = 0;
 516
 517         mac_control = &nic->mac_control;
 518         config = &nic->config;
 519
 520
 521         /* Allocation and initialization of TXDLs in FIOFs */
 522         size = 0;
 523         for (i = 0; i < config->tx_fifo_num; i++) {
 524                 size += config->tx_cfg[i].fifo_len;
 525         }
 526         if (size > MAX_AVAILABLE_TXDS) {
 527                 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
 528                 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
 529                 return -EINVAL;
 530         }
 531
 532         lst_size = (sizeof(struct TxD) * config->max_txds);
 533         lst_per_page = PAGE_SIZE / lst_size;
 534
 535         for (i = 0; i < config->tx_fifo_num; i++) {
 536                 int fifo_len = config->tx_cfg[i].fifo_len;
 537                 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
 538                 mac_control->fifos[i].list_info = kmalloc(list_holder_size,
 539                                                           GFP_KERNEL);
 540                 if (!mac_control->fifos[i].list_info) {
 541                         DBG_PRINT(INFO_DBG,
 542                                   "Malloc failed for list_info\n");
 543                         return -ENOMEM;
 544                 }
 545                 mem_allocated += list_holder_size;
 546                 memset(mac_control->fifos[i].list_info, 0, list_holder_size);
 547         }
 548         for (i = 0; i < config->tx_fifo_num; i++) {
 549                 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
 550                                                 lst_per_page);
 551                 mac_control->fifos[i].tx_curr_put_info.offset = 0;
 552                 mac_control->fifos[i].tx_curr_put_info.fifo_len =
 553                     config->tx_cfg[i].fifo_len - 1;
 554                 mac_control->fifos[i].tx_curr_get_info.offset = 0;
 555                 mac_control->fifos[i].tx_curr_get_info.fifo_len =
 556                     config->tx_cfg[i].fifo_len - 1;
 557                 mac_control->fifos[i].fifo_no = i;
 558                 mac_control->fifos[i].nic = nic;
 559                 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
 560
 561                 for (j = 0; j < page_num; j++) {
 562                         int k = 0;
 563                         dma_addr_t tmp_p;
 564                         void *tmp_v;
 565                         tmp_v = pci_alloc_consistent(nic->pdev,
 566                                                      PAGE_SIZE, &tmp_p);
 567                         if (!tmp_v) {
 568                                 DBG_PRINT(INFO_DBG,
 569                                           "pci_alloc_consistent ");
 570                                 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
 571                                 return -ENOMEM;
 572                         }
 573                         /* If we got a zero DMA address(can happen on
 574                          * certain platforms like PPC), reallocate.
 575                          * Store virtual address of page we don't want,
 576                          * to be freed later.
 577                          */
 578                         if (!tmp_p) {
 579                                 mac_control->zerodma_virt_addr = tmp_v;
 580                                 DBG_PRINT(INIT_DBG,
 581                                 "%s: Zero DMA address for TxDL. ", dev->name);
 582                                 DBG_PRINT(INIT_DBG,
 583                                 "Virtual address %p\n", tmp_v);
 584                                 tmp_v = pci_alloc_consistent(nic->pdev,
 585                                                      PAGE_SIZE, &tmp_p);
 586                                 if (!tmp_v) {
 587                                         DBG_PRINT(INFO_DBG,
 588                                           "pci_alloc_consistent ");
 589                                         DBG_PRINT(INFO_DBG, "failed for TxDL\n");
 590                                         return -ENOMEM;
 591                                 }
 592                                 mem_allocated += PAGE_SIZE;
 593                         }
 594                         while (k < lst_per_page) {
 595                                 int l = (j * lst_per_page) + k;
 596                                 if (l == config->tx_cfg[i].fifo_len)
 597                                         break;
 598                                 mac_control->fifos[i].list_info[l].list_virt_addr =
 599                                     tmp_v + (k * lst_size);
 600                                 mac_control->fifos[i].list_info[l].list_phy_addr =
 601                                     tmp_p + (k * lst_size);
 602                                 k++;
 603                         }
 604                 }
 605         }
 606
 607         nic->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
 608         if (!nic->ufo_in_band_v)
 609                 return -ENOMEM;
 610          mem_allocated += (size * sizeof(u64));
 611
 612         /* Allocation and initialization of RXDs in Rings */
 613         size = 0;
 614         for (i = 0; i < config->rx_ring_num; i++) {
 615                 if (config->rx_cfg[i].num_rxd %
 616                     (rxd_count[nic->rxd_mode] + 1)) {
 617                         DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
 618                         DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
 619                                   i);
 620                         DBG_PRINT(ERR_DBG, "RxDs per Block");
 621                         return FAILURE;
 622                 }
 623                 size += config->rx_cfg[i].num_rxd;
 624                 mac_control->rings[i].block_count =
 625                         config->rx_cfg[i].num_rxd /
 626                         (rxd_count[nic->rxd_mode] + 1 );
 627                 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
 628                         mac_control->rings[i].block_count;
 629         }
 630         if (nic->rxd_mode == RXD_MODE_1)
 631                 size = (size * (sizeof(struct RxD1)));
 632         else
 633                 size = (size * (sizeof(struct RxD3)));
 634
 635         for (i = 0; i < config->rx_ring_num; i++) {
 636                 mac_control->rings[i].rx_curr_get_info.block_index = 0;
 637                 mac_control->rings[i].rx_curr_get_info.offset = 0;
 638                 mac_control->rings[i].rx_curr_get_info.ring_len =
 639                     config->rx_cfg[i].num_rxd - 1;
 640                 mac_control->rings[i].rx_curr_put_info.block_index = 0;
 641                 mac_control->rings[i].rx_curr_put_info.offset = 0;
 642                 mac_control->rings[i].rx_curr_put_info.ring_len =
 643                     config->rx_cfg[i].num_rxd - 1;
 644                 mac_control->rings[i].nic = nic;
 645                 mac_control->rings[i].ring_no = i;
 646
 647                 blk_cnt = config->rx_cfg[i].num_rxd /
 648                                 (rxd_count[nic->rxd_mode] + 1);
 649                 /*  Allocating all the Rx blocks */
 650                 for (j = 0; j < blk_cnt; j++) {
 651                         struct rx_block_info *rx_blocks;
 652                         int l;
 653
 654                         rx_blocks = &mac_control->rings[i].rx_blocks[j];
 655                         size = SIZE_OF_BLOCK; //size is always page size
 656                         tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
 657                                                           &tmp_p_addr);
 658                         if (tmp_v_addr == NULL) {
 659                                 /*
 660                                  * In case of failure, free_shared_mem()
 661                                  * is called, which should free any
 662                                  * memory that was alloced till the
 663                                  * failure happened.
 664                                  */
 665                                 rx_blocks->block_virt_addr = tmp_v_addr;
 666                                 return -ENOMEM;
 667                         }
 668                         mem_allocated += size;
 669                         memset(tmp_v_addr, 0, size);
 670                         rx_blocks->block_virt_addr = tmp_v_addr;
 671                         rx_blocks->block_dma_addr = tmp_p_addr;
 672                         rx_blocks->rxds = kmalloc(sizeof(struct rxd_info)*
 673                                                   rxd_count[nic->rxd_mode],
 674                                                   GFP_KERNEL);
 675                         if (!rx_blocks->rxds)
 676                                 return -ENOMEM;
 677                         mem_allocated +=
 678                         (sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
 679                         for (l=0; l<rxd_count[nic->rxd_mode];l++) {
 680                                 rx_blocks->rxds[l].virt_addr =
 681                                         rx_blocks->block_virt_addr +
 682                                         (rxd_size[nic->rxd_mode] * l);
 683                                 rx_blocks->rxds[l].dma_addr =
 684                                         rx_blocks->block_dma_addr +
 685                                         (rxd_size[nic->rxd_mode] * l);
 686                         }
 687                 }
 688                 /* Interlinking all Rx Blocks */
 689                 for (j = 0; j < blk_cnt; j++) {
 690                         tmp_v_addr =
 691                                 mac_control->rings[i].rx_blocks[j].block_virt_addr;
 692                         tmp_v_addr_next =
 693                                 mac_control->rings[i].rx_blocks[(j + 1) %
 694                                               blk_cnt].block_virt_addr;
 695                         tmp_p_addr =
 696                                 mac_control->rings[i].rx_blocks[j].block_dma_addr;
 697                         tmp_p_addr_next =
 698                                 mac_control->rings[i].rx_blocks[(j + 1) %
 699                                               blk_cnt].block_dma_addr;
 700
 701                         pre_rxd_blk = (struct RxD_block *) tmp_v_addr;
 702                         pre_rxd_blk->reserved_2_pNext_RxD_block =
 703                             (unsigned long) tmp_v_addr_next;
 704                         pre_rxd_blk->pNext_RxD_Blk_physical =
 705                             (u64) tmp_p_addr_next;
 706                 }
 707         }
 708         if (nic->rxd_mode >= RXD_MODE_3A) {
 709                 /*
 710                  * Allocation of Storages for buffer addresses in 2BUFF mode
 711                  * and the buffers as well.
 712                  */
 713                 for (i = 0; i < config->rx_ring_num; i++) {
 714                         blk_cnt = config->rx_cfg[i].num_rxd /
 715                            (rxd_count[nic->rxd_mode]+ 1);
 716                         mac_control->rings[i].ba =
 717                                 kmalloc((sizeof(struct buffAdd *) * blk_cnt),
 718                                      GFP_KERNEL);
 719                         if (!mac_control->rings[i].ba)
 720                                 return -ENOMEM;
 721                         mem_allocated +=(sizeof(struct buffAdd *) * blk_cnt);
 722                         for (j = 0; j < blk_cnt; j++) {
 723                                 int k = 0;
 724                                 mac_control->rings[i].ba[j] =
 725                                         kmalloc((sizeof(struct buffAdd) *
 726                                                 (rxd_count[nic->rxd_mode] + 1)),
 727                                                 GFP_KERNEL);
 728                                 if (!mac_control->rings[i].ba[j])
 729                                         return -ENOMEM;
 730                                 mem_allocated += (sizeof(struct buffAdd) *  \
 731                                         (rxd_count[nic->rxd_mode] + 1));
 732                                 while (k != rxd_count[nic->rxd_mode]) {
 733                                         ba = &mac_control->rings[i].ba[j][k];
 734
 735                                         ba->ba_0_org = (void *) kmalloc
 736                                             (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
 737                                         if (!ba->ba_0_org)
 738                                                 return -ENOMEM;
 739                                         mem_allocated +=
 740                                                 (BUF0_LEN + ALIGN_SIZE);
 741                                         tmp = (unsigned long)ba->ba_0_org;
 742                                         tmp += ALIGN_SIZE;
 743                                         tmp &= ~((unsigned long) ALIGN_SIZE);
 744                                         ba->ba_0 = (void *) tmp;
 745
 746                                         ba->ba_1_org = (void *) kmalloc
 747                                             (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
 748                                         if (!ba->ba_1_org)
 749                                                 return -ENOMEM;
 750                                         mem_allocated
 751                                                 += (BUF1_LEN + ALIGN_SIZE);
 752                                         tmp = (unsigned long) ba->ba_1_org;
 753                                         tmp += ALIGN_SIZE;
 754                                         tmp &= ~((unsigned long) ALIGN_SIZE);
 755                                         ba->ba_1 = (void *) tmp;
 756                                         k++;
 757                                 }
 758                         }
 759                 }
 760         }
 761
 762         /* Allocation and initialization of Statistics block */
 763         size = sizeof(struct stat_block);
 764         mac_control->stats_mem = pci_alloc_consistent
 765             (nic->pdev, size, &mac_control->stats_mem_phy);
 766
 767         if (!mac_control->stats_mem) {
 768                 /*
 769                  * In case of failure, free_shared_mem() is called, which
 770                  * should free any memory that was alloced till the
 771                  * failure happened.
 772                  */
 773                 return -ENOMEM;
 774         }
 775         mem_allocated += size;
 776         mac_control->stats_mem_sz = size;
 777
 778         tmp_v_addr = mac_control->stats_mem;
 779         mac_control->stats_info = (struct stat_block *) tmp_v_addr;
 780         memset(tmp_v_addr, 0, size);
 781         DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
 782                   (unsigned long long) tmp_p_addr);
 783         mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
 784         return SUCCESS;
 785 }
 786
 787 /**
 788  * free_shared_mem - Free the allocated Memory
 789  * @nic:  Device private variable.
 790  * Description: This function is to free all memory locations allocated by
 791  * the init_shared_mem() function and return it to the kernel.
 792  */
 793
 794 static void free_shared_mem(struct s2io_nic *nic)
 795 {
 796         int i, j, blk_cnt, size;
 797         u32 ufo_size = 0;
 798         void *tmp_v_addr;
 799         dma_addr_t tmp_p_addr;
 800         struct mac_info *mac_control;
 801         struct config_param *config;
 802         int lst_size, lst_per_page;
 803         struct net_device *dev = nic->dev;
 804         int page_num = 0;
 805
 806         if (!nic)
 807                 return;
 808
 809         mac_control = &nic->mac_control;
 810         config = &nic->config;
 811
 812         lst_size = (sizeof(struct TxD) * config->max_txds);
 813         lst_per_page = PAGE_SIZE / lst_size;
 814
 815         for (i = 0; i < config->tx_fifo_num; i++) {
 816                 ufo_size += config->tx_cfg[i].fifo_len;
 817                 page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
 818                                                         lst_per_page);
 819                 for (j = 0; j < page_num; j++) {
 820                         int mem_blks = (j * lst_per_page);
 821                         if (!mac_control->fifos[i].list_info)
 822                                 return;
 823                         if (!mac_control->fifos[i].list_info[mem_blks].
 824                                  list_virt_addr)
 825                                 break;
 826                         pci_free_consistent(nic->pdev, PAGE_SIZE,
 827                                             mac_control->fifos[i].
 828                                             list_info[mem_blks].
 829                                             list_virt_addr,
 830                                             mac_control->fifos[i].
 831                                             list_info[mem_blks].
 832                                             list_phy_addr);
 833                         nic->mac_control.stats_info->sw_stat.mem_freed
 834                                                 += PAGE_SIZE;
 835                 }
 836                 /* If we got a zero DMA address during allocation,
 837                  * free the page now
 838                  */
 839                 if (mac_control->zerodma_virt_addr) {
 840                         pci_free_consistent(nic->pdev, PAGE_SIZE,
 841                                             mac_control->zerodma_virt_addr,
 842                                             (dma_addr_t)0);
 843                         DBG_PRINT(INIT_DBG,
 844                                 "%s: Freeing TxDL with zero DMA addr. ",
 845                                 dev->name);
 846                         DBG_PRINT(INIT_DBG, "Virtual address %p\n",
 847                                 mac_control->zerodma_virt_addr);
 848                         nic->mac_control.stats_info->sw_stat.mem_freed
 849                                                 += PAGE_SIZE;
 850                 }
 851                 kfree(mac_control->fifos[i].list_info);
 852                 nic->mac_control.stats_info->sw_stat.mem_freed +=
 853                 (nic->config.tx_cfg[i].fifo_len *sizeof(struct list_info_hold));
 854         }
 855
 856         size = SIZE_OF_BLOCK;
 857         for (i = 0; i < config->rx_ring_num; i++) {
 858                 blk_cnt = mac_control->rings[i].block_count;
 859                 for (j = 0; j < blk_cnt; j++) {
 860                         tmp_v_addr = mac_control->rings[i].rx_blocks[j].
 861                                 block_virt_addr;
 862                         tmp_p_addr = mac_control->rings[i].rx_blocks[j].
 863                                 block_dma_addr;
 864                         if (tmp_v_addr == NULL)
 865                                 break;
 866                         pci_free_consistent(nic->pdev, size,
 867                                             tmp_v_addr, tmp_p_addr);
 868                         nic->mac_control.stats_info->sw_stat.mem_freed += size;
 869                         kfree(mac_control->rings[i].rx_blocks[j].rxds);
 870                         nic->mac_control.stats_info->sw_stat.mem_freed +=
 871                         ( sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
 872                 }
 873         }
 874
 875         if (nic->rxd_mode >= RXD_MODE_3A) {
 876                 /* Freeing buffer storage addresses in 2BUFF mode. */
 877                 for (i = 0; i < config->rx_ring_num; i++) {
 878                         blk_cnt = config->rx_cfg[i].num_rxd /
 879                             (rxd_count[nic->rxd_mode] + 1);
 880                         for (j = 0; j < blk_cnt; j++) {
 881                                 int k = 0;
 882                                 if (!mac_control->rings[i].ba[j])
 883                                         continue;
 884                                 while (k != rxd_count[nic->rxd_mode]) {
 885                                         struct buffAdd *ba =
 886                                                 &mac_control->rings[i].ba[j][k];
 887                                         kfree(ba->ba_0_org);
 888                                         nic->mac_control.stats_info->sw_stat.\
 889                                         mem_freed += (BUF0_LEN + ALIGN_SIZE);
 890                                         kfree(ba->ba_1_org);
 891                                         nic->mac_control.stats_info->sw_stat.\
 892                                         mem_freed += (BUF1_LEN + ALIGN_SIZE);
 893                                         k++;
 894                                 }
 895                                 kfree(mac_control->rings[i].ba[j]);
 896                                 nic->mac_control.stats_info->sw_stat.mem_freed                          += (sizeof(struct buffAdd) *
 897                                 (rxd_count[nic->rxd_mode] + 1));
 898                         }
 899                         kfree(mac_control->rings[i].ba);
 900                         nic->mac_control.stats_info->sw_stat.mem_freed +=
 901                         (sizeof(struct buffAdd *) * blk_cnt);
 902                 }
 903         }
 904
 905         if (mac_control->stats_mem) {
 906                 pci_free_consistent(nic->pdev,
 907                                     mac_control->stats_mem_sz,
 908                                     mac_control->stats_mem,
 909                                     mac_control->stats_mem_phy);
 910                 nic->mac_control.stats_info->sw_stat.mem_freed +=
 911                         mac_control->stats_mem_sz;
 912         }
 913         if (nic->ufo_in_band_v) {
 914                 kfree(nic->ufo_in_band_v);
 915                 nic->mac_control.stats_info->sw_stat.mem_freed
 916                         += (ufo_size * sizeof(u64));
 917         }
 918 }
 919
 920 /**
 921  * s2io_verify_pci_mode -
 922  */
 923
 924 static int s2io_verify_pci_mode(struct s2io_nic *nic)
 925 {
 926         struct XENA_dev_config __iomem *bar0 = nic->bar0;
 927         register u64 val64 = 0;
 928         int     mode;
 929
 930         val64 = readq(&bar0->pci_mode);
 931         mode = (u8)GET_PCI_MODE(val64);
 932
 933         if ( val64 & PCI_MODE_UNKNOWN_MODE)
 934                 return -1;      /* Unknown PCI mode */
 935         return mode;
 936 }
 937
 938 #define NEC_VENID   0x1033
 939 #define NEC_DEVID   0x0125
 940 static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
 941 {
 942         struct pci_dev *tdev = NULL;
 943         while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
 944                 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
 945                         if (tdev->bus == s2io_pdev->bus->parent)
 946                                 pci_dev_put(tdev);
 947                                 return 1;
 948                 }
 949         }
 950         return 0;
 951 }
 952
 953 static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
 954 /**
 955  * s2io_print_pci_mode -
 956  */
 957 static int s2io_print_pci_mode(struct s2io_nic *nic)
 958 {
 959         struct XENA_dev_config __iomem *bar0 = nic->bar0;
 960         register u64 val64 = 0;
 961         int     mode;
 962         struct config_param *config = &nic->config;
 963
 964         val64 = readq(&bar0->pci_mode);
 965         mode = (u8)GET_PCI_MODE(val64);
 966
 967         if ( val64 & PCI_MODE_UNKNOWN_MODE)
 968                 return -1;      /* Unknown PCI mode */
 969
 970         config->bus_speed = bus_speed[mode];
 971
 972         if (s2io_on_nec_bridge(nic->pdev)) {
 973                 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
 974                                                         nic->dev->name);
 975                 return mode;
 976         }
 977
 978         if (val64 & PCI_MODE_32_BITS) {
 979                 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
 980         } else {
 981                 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
 982         }
 983
 984         switch(mode) {
 985                 case PCI_MODE_PCI_33:
 986                         DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
 987                         break;
 988                 case PCI_MODE_PCI_66:
 989                         DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
 990                         break;
 991                 case PCI_MODE_PCIX_M1_66:
 992                         DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
 993                         break;
 994                 case PCI_MODE_PCIX_M1_100:
 995                         DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
 996                         break;
 997                 case PCI_MODE_PCIX_M1_133:
 998                         DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
 999                         break;
1000                 case PCI_MODE_PCIX_M2_66:
1001                         DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
1002                         break;
1003                 case PCI_MODE_PCIX_M2_100:
1004                         DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
1005                         break;
1006                 case PCI_MODE_PCIX_M2_133:
1007                         DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
1008                         break;
1009                 default:
1010                         return -1;      /* Unsupported bus speed */
1011         }
1012
1013         return mode;
1014 }
1015
1016 /**
1017  *  init_nic - Initialization of hardware
1018  *  @nic: device peivate variable
1019  *  Description: The function sequentially configures every block
1020  *  of the H/W from their reset values.
1021  *  Return Value:  SUCCESS on success and
1022  *  '-1' on failure (endian settings incorrect).
1023  */
1024
1025 static int init_nic(struct s2io_nic *nic)
1026 {
1027         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1028         struct net_device *dev = nic->dev;
1029         register u64 val64 = 0;
1030         void __iomem *add;
1031         u32 time;
1032         int i, j;
1033         struct mac_info *mac_control;
1034         struct config_param *config;
1035         int dtx_cnt = 0;
1036         unsigned long long mem_share;
1037         int mem_size;
1038
1039         mac_control = &nic->mac_control;
1040         config = &nic->config;
1041
1042         /* to set the swapper controle on the card */
1043         if(s2io_set_swapper(nic)) {
1044                 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
1045                 return -1;
1046         }
1047
1048         /*
1049          * Herc requires EOI to be removed from reset before XGXS, so..
1050          */
1051         if (nic->device_type & XFRAME_II_DEVICE) {
1052                 val64 = 0xA500000000ULL;
1053                 writeq(val64, &bar0->sw_reset);
1054                 msleep(500);
1055                 val64 = readq(&bar0->sw_reset);
1056         }
1057
1058         /* Remove XGXS from reset state */
1059         val64 = 0;
1060         writeq(val64, &bar0->sw_reset);
1061         msleep(500);
1062         val64 = readq(&bar0->sw_reset);
1063
1064         /*  Enable Receiving broadcasts */
1065         add = &bar0->mac_cfg;
1066         val64 = readq(&bar0->mac_cfg);
1067         val64 |= MAC_RMAC_BCAST_ENABLE;
1068         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1069         writel((u32) val64, add);
1070         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1071         writel((u32) (val64 >> 32), (add + 4));
1072
1073         /* Read registers in all blocks */
1074         val64 = readq(&bar0->mac_int_mask);
1075         val64 = readq(&bar0->mc_int_mask);
1076         val64 = readq(&bar0->xgxs_int_mask);
1077
1078         /*  Set MTU */
1079         val64 = dev->mtu;
1080         writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1081
1082         if (nic->device_type & XFRAME_II_DEVICE) {
1083                 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
1084                         SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1085                                           &bar0->dtx_control, UF);
1086                         if (dtx_cnt & 0x1)
1087                                 msleep(1); /* Necessary!! */
1088                         dtx_cnt++;
1089                 }
1090         } else {
1091                 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1092                         SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1093                                           &bar0->dtx_control, UF);
1094                         val64 = readq(&bar0->dtx_control);
1095                         dtx_cnt++;
1096                 }
1097         }
1098
1099         /*  Tx DMA Initialization */
1100         val64 = 0;
1101         writeq(val64, &bar0->tx_fifo_partition_0);
1102         writeq(val64, &bar0->tx_fifo_partition_1);
1103         writeq(val64, &bar0->tx_fifo_partition_2);
1104         writeq(val64, &bar0->tx_fifo_partition_3);
1105
1106
1107         for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1108                 val64 |=
1109                     vBIT(config->tx_cfg[i].fifo_len - 1, ((i * 32) + 19),
1110                          13) | vBIT(config->tx_cfg[i].fifo_priority,
1111                                     ((i * 32) + 5), 3);
1112
1113                 if (i == (config->tx_fifo_num - 1)) {
1114                         if (i % 2 == 0)
1115                                 i++;
1116                 }
1117
1118                 switch (i) {
1119                 case 1:
1120                         writeq(val64, &bar0->tx_fifo_partition_0);
1121                         val64 = 0;
1122                         break;
1123                 case 3:
1124                         writeq(val64, &bar0->tx_fifo_partition_1);
1125                         val64 = 0;
1126                         break;
1127                 case 5:
1128                         writeq(val64, &bar0->tx_fifo_partition_2);
1129                         val64 = 0;
1130                         break;
1131                 case 7:
1132                         writeq(val64, &bar0->tx_fifo_partition_3);
1133                         break;
1134                 }
1135         }
1136
1137         /*
1138          * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1139          * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1140          */
1141         if ((nic->device_type == XFRAME_I_DEVICE) &&
1142                 (get_xena_rev_id(nic->pdev) < 4))
1143                 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1144
1145         val64 = readq(&bar0->tx_fifo_partition_0);
1146         DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1147                   &bar0->tx_fifo_partition_0, (unsigned long long) val64);
1148
1149         /*
1150          * Initialization of Tx_PA_CONFIG register to ignore packet
1151          * integrity checking.
1152          */
1153         val64 = readq(&bar0->tx_pa_cfg);
1154         val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1155             TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1156         writeq(val64, &bar0->tx_pa_cfg);
1157
1158         /* Rx DMA intialization. */
1159         val64 = 0;
1160         for (i = 0; i < config->rx_ring_num; i++) {
1161                 val64 |=
1162                     vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
1163                          3);
1164         }
1165         writeq(val64, &bar0->rx_queue_priority);
1166
1167         /*
1168          * Allocating equal share of memory to all the
1169          * configured Rings.
1170          */
1171         val64 = 0;
1172         if (nic->device_type & XFRAME_II_DEVICE)
1173                 mem_size = 32;
1174         else
1175                 mem_size = 64;
1176
1177         for (i = 0; i < config->rx_ring_num; i++) {
1178                 switch (i) {
1179                 case 0:
1180                         mem_share = (mem_size / config->rx_ring_num +
1181                                      mem_size % config->rx_ring_num);
1182                         val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1183                         continue;
1184                 case 1:
1185                         mem_share = (mem_size / config->rx_ring_num);
1186                         val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1187                         continue;
1188                 case 2:
1189                         mem_share = (mem_size / config->rx_ring_num);
1190                         val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1191                         continue;
1192                 case 3:
1193                         mem_share = (mem_size / config->rx_ring_num);
1194                         val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1195                         continue;
1196                 case 4:
1197                         mem_share = (mem_size / config->rx_ring_num);
1198                         val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1199                         continue;
1200                 case 5:
1201                         mem_share = (mem_size / config->rx_ring_num);
1202                         val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1203                         continue;
1204                 case 6:
1205                         mem_share = (mem_size / config->rx_ring_num);
1206                         val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1207                         continue;
1208                 case 7:
1209                         mem_share = (mem_size / config->rx_ring_num);
1210                         val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1211                         continue;
1212                 }
1213         }
1214         writeq(val64, &bar0->rx_queue_cfg);
1215
1216         /*
1217          * Filling Tx round robin registers
1218          * as per the number of FIFOs
1219          */
1220         switch (config->tx_fifo_num) {
1221         case 1:
1222                 val64 = 0x0000000000000000ULL;
1223                 writeq(val64, &bar0->tx_w_round_robin_0);
1224                 writeq(val64, &bar0->tx_w_round_robin_1);
1225                 writeq(val64, &bar0->tx_w_round_robin_2);
1226                 writeq(val64, &bar0->tx_w_round_robin_3);
1227                 writeq(val64, &bar0->tx_w_round_robin_4);
1228                 break;
1229         case 2:
1230                 val64 = 0x0000010000010000ULL;
1231                 writeq(val64, &bar0->tx_w_round_robin_0);
1232                 val64 = 0x0100000100000100ULL;
1233                 writeq(val64, &bar0->tx_w_round_robin_1);
1234                 val64 = 0x0001000001000001ULL;
1235                 writeq(val64, &bar0->tx_w_round_robin_2);
1236                 val64 = 0x0000010000010000ULL;
1237                 writeq(val64, &bar0->tx_w_round_robin_3);
1238                 val64 = 0x0100000000000000ULL;
1239                 writeq(val64, &bar0->tx_w_round_robin_4);
1240                 break;
1241         case 3:
1242                 val64 = 0x0001000102000001ULL;
1243                 writeq(val64, &bar0->tx_w_round_robin_0);
1244                 val64 = 0x0001020000010001ULL;
1245                 writeq(val64, &bar0->tx_w_round_robin_1);
1246                 val64 = 0x0200000100010200ULL;
1247                 writeq(val64, &bar0->tx_w_round_robin_2);
1248                 val64 = 0x0001000102000001ULL;
1249                 writeq(val64, &bar0->tx_w_round_robin_3);
1250                 val64 = 0x0001020000000000ULL;
1251                 writeq(val64, &bar0->tx_w_round_robin_4);
1252                 break;
1253         case 4:
1254                 val64 = 0x0001020300010200ULL;
1255                 writeq(val64, &bar0->tx_w_round_robin_0);
1256                 val64 = 0x0100000102030001ULL;
1257                 writeq(val64, &bar0->tx_w_round_robin_1);
1258                 val64 = 0x0200010000010203ULL;
1259                 writeq(val64, &bar0->tx_w_round_robin_2);
1260                 val64 = 0x0001020001000001ULL;
1261                 writeq(val64, &bar0->tx_w_round_robin_3);
1262                 val64 = 0x0203000100000000ULL;
1263                 writeq(val64, &bar0->tx_w_round_robin_4);
1264                 break;
1265         case 5:
1266                 val64 = 0x0001000203000102ULL;
1267                 writeq(val64, &bar0->tx_w_round_robin_0);
1268                 val64 = 0x0001020001030004ULL;
1269                 writeq(val64, &bar0->tx_w_round_robin_1);
1270                 val64 = 0x0001000203000102ULL;
1271                 writeq(val64, &bar0->tx_w_round_robin_2);
1272                 val64 = 0x0001020001030004ULL;
1273                 writeq(val64, &bar0->tx_w_round_robin_3);
1274                 val64 = 0x0001000000000000ULL;
1275                 writeq(val64, &bar0->tx_w_round_robin_4);
1276                 break;
1277         case 6:
1278                 val64 = 0x0001020304000102ULL;
1279                 writeq(val64, &bar0->tx_w_round_robin_0);
1280                 val64 = 0x0304050001020001ULL;
1281                 writeq(val64, &bar0->tx_w_round_robin_1);
1282                 val64 = 0x0203000100000102ULL;
1283                 writeq(val64, &bar0->tx_w_round_robin_2);
1284                 val64 = 0x0304000102030405ULL;
1285                 writeq(val64, &bar0->tx_w_round_robin_3);
1286                 val64 = 0x0001000200000000ULL;
1287                 writeq(val64, &bar0->tx_w_round_robin_4);
1288                 break;
1289         case 7:
1290                 val64 = 0x0001020001020300ULL;
1291                 writeq(val64, &bar0->tx_w_round_robin_0);
1292                 val64 = 0x0102030400010203ULL;
1293                 writeq(val64, &bar0->tx_w_round_robin_1);
1294                 val64 = 0x0405060001020001ULL;
1295                 writeq(val64, &bar0->tx_w_round_robin_2);
1296                 val64 = 0x0304050000010200ULL;
1297                 writeq(val64, &bar0->tx_w_round_robin_3);
1298                 val64 = 0x0102030000000000ULL;
1299                 writeq(val64, &bar0->tx_w_round_robin_4);
1300                 break;
1301         case 8:
1302                 val64 = 0x0001020300040105ULL;
1303                 writeq(val64, &bar0->tx_w_round_robin_0);
1304                 val64 = 0x0200030106000204ULL;
1305                 writeq(val64, &bar0->tx_w_round_robin_1);
1306                 val64 = 0x0103000502010007ULL;
1307                 writeq(val64, &bar0->tx_w_round_robin_2);
1308                 val64 = 0x0304010002060500ULL;
1309                 writeq(val64, &bar0->tx_w_round_robin_3);
1310                 val64 = 0x0103020400000000ULL;
1311                 writeq(val64, &bar0->tx_w_round_robin_4);
1312                 break;
1313         }
1314
1315         /* Enable all configured Tx FIFO partitions */
1316         val64 = readq(&bar0->tx_fifo_partition_0);
1317         val64 |= (TX_FIFO_PARTITION_EN);
1318         writeq(val64, &bar0->tx_fifo_partition_0);
1319
1320         /* Filling the Rx round robin registers as per the
1321          * number of Rings and steering based on QoS.
1322          */
1323         switch (config->rx_ring_num) {
1324         case 1:
1325                 val64 = 0x8080808080808080ULL;
1326                 writeq(val64, &bar0->rts_qos_steering);
1327                 break;
1328         case 2:
1329                 val64 = 0x0000010000010000ULL;
1330                 writeq(val64, &bar0->rx_w_round_robin_0);
1331                 val64 = 0x0100000100000100ULL;
1332                 writeq(val64, &bar0->rx_w_round_robin_1);
1333                 val64 = 0x0001000001000001ULL;
1334                 writeq(val64, &bar0->rx_w_round_robin_2);
1335                 val64 = 0x0000010000010000ULL;
1336                 writeq(val64, &bar0->rx_w_round_robin_3);
1337                 val64 = 0x0100000000000000ULL;
1338                 writeq(val64, &bar0->rx_w_round_robin_4);
1339
1340                 val64 = 0x8080808040404040ULL;
1341                 writeq(val64, &bar0->rts_qos_steering);
1342                 break;
1343         case 3:
1344                 val64 = 0x0001000102000001ULL;
1345                 writeq(val64, &bar0->rx_w_round_robin_0);
1346                 val64 = 0x0001020000010001ULL;
1347                 writeq(val64, &bar0->rx_w_round_robin_1);
1348                 val64 = 0x0200000100010200ULL;
1349                 writeq(val64, &bar0->rx_w_round_robin_2);
1350                 val64 = 0x0001000102000001ULL;
1351                 writeq(val64, &bar0->rx_w_round_robin_3);
1352                 val64 = 0x0001020000000000ULL;
1353                 writeq(val64, &bar0->rx_w_round_robin_4);
1354
1355                 val64 = 0x8080804040402020ULL;
1356                 writeq(val64, &bar0->rts_qos_steering);
1357                 break;
1358         case 4:
1359                 val64 = 0x0001020300010200ULL;
1360                 writeq(val64, &bar0->rx_w_round_robin_0);
1361                 val64 = 0x0100000102030001ULL;
1362                 writeq(val64, &bar0->rx_w_round_robin_1);
1363                 val64 = 0x0200010000010203ULL;
1364                 writeq(val64, &bar0->rx_w_round_robin_2);
1365                 val64 = 0x0001020001000001ULL;
1366                 writeq(val64, &bar0->rx_w_round_robin_3);
1367                 val64 = 0x0203000100000000ULL;
1368                 writeq(val64, &bar0->rx_w_round_robin_4);
1369
1370                 val64 = 0x8080404020201010ULL;
1371                 writeq(val64, &bar0->rts_qos_steering);
1372                 break;
1373         case 5:
1374                 val64 = 0x0001000203000102ULL;
1375                 writeq(val64, &bar0->rx_w_round_robin_0);
1376                 val64 = 0x0001020001030004ULL;
1377                 writeq(val64, &bar0->rx_w_round_robin_1);
1378                 val64 = 0x0001000203000102ULL;
1379                 writeq(val64, &bar0->rx_w_round_robin_2);
1380                 val64 = 0x0001020001030004ULL;
1381                 writeq(val64, &bar0->rx_w_round_robin_3);
1382                 val64 = 0x0001000000000000ULL;
1383                 writeq(val64, &bar0->rx_w_round_robin_4);
1384
1385                 val64 = 0x8080404020201008ULL;
1386                 writeq(val64, &bar0->rts_qos_steering);
1387                 break;
1388         case 6:
1389                 val64 = 0x0001020304000102ULL;
1390                 writeq(val64, &bar0->rx_w_round_robin_0);
1391                 val64 = 0x0304050001020001ULL;
1392                 writeq(val64, &bar0->rx_w_round_robin_1);
1393                 val64 = 0x0203000100000102ULL;
1394                 writeq(val64, &bar0->rx_w_round_robin_2);
1395                 val64 = 0x0304000102030405ULL;
1396                 writeq(val64, &bar0->rx_w_round_robin_3);
1397                 val64 = 0x0001000200000000ULL;
1398                 writeq(val64, &bar0->rx_w_round_robin_4);
1399
1400                 val64 = 0x8080404020100804ULL;
1401                 writeq(val64, &bar0->rts_qos_steering);
1402                 break;
1403         case 7:
1404                 val64 = 0x0001020001020300ULL;
1405                 writeq(val64, &bar0->rx_w_round_robin_0);
1406                 val64 = 0x0102030400010203ULL;
1407                 writeq(val64, &bar0->rx_w_round_robin_1);
1408                 val64 = 0x0405060001020001ULL;
1409                 writeq(val64, &bar0->rx_w_round_robin_2);
1410                 val64 = 0x0304050000010200ULL;
1411                 writeq(val64, &bar0->rx_w_round_robin_3);
1412                 val64 = 0x0102030000000000ULL;
1413                 writeq(val64, &bar0->rx_w_round_robin_4);
1414
1415                 val64 = 0x8080402010080402ULL;
1416                 writeq(val64, &bar0->rts_qos_steering);
1417                 break;
1418         case 8:
1419                 val64 = 0x0001020300040105ULL;
1420                 writeq(val64, &bar0->rx_w_round_robin_0);
1421                 val64 = 0x0200030106000204ULL;
1422                 writeq(val64, &bar0->rx_w_round_robin_1);
1423                 val64 = 0x0103000502010007ULL;
1424                 writeq(val64, &bar0->rx_w_round_robin_2);
1425                 val64 = 0x0304010002060500ULL;
1426                 writeq(val64, &bar0->rx_w_round_robin_3);
1427                 val64 = 0x0103020400000000ULL;
1428                 writeq(val64, &bar0->rx_w_round_robin_4);
1429
1430                 val64 = 0x8040201008040201ULL;
1431                 writeq(val64, &bar0->rts_qos_steering);
1432                 break;
1433         }
1434
1435         /* UDP Fix */
1436         val64 = 0;
1437         for (i = 0; i < 8; i++)
1438                 writeq(val64, &bar0->rts_frm_len_n[i]);
1439
1440         /* Set the default rts frame length for the rings configured */
1441         val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1442         for (i = 0 ; i < config->rx_ring_num ; i++)
1443                 writeq(val64, &bar0->rts_frm_len_n[i]);
1444
1445         /* Set the frame length for the configured rings
1446          * desired by the user
1447          */
1448         for (i = 0; i < config->rx_ring_num; i++) {
1449                 /* If rts_frm_len[i] == 0 then it is assumed that user not
1450                  * specified frame length steering.
1451                  * If the user provides the frame length then program
1452                  * the rts_frm_len register for those values or else
1453                  * leave it as it is.
1454                  */
1455                 if (rts_frm_len[i] != 0) {
1456                         writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1457                                 &bar0->rts_frm_len_n[i]);
1458                 }
1459         }
1460
1461         /* Disable differentiated services steering logic */
1462         for (i = 0; i < 64; i++) {
1463                 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1464                         DBG_PRINT(ERR_DBG, "%s: failed rts ds steering",
1465                                 dev->name);
1466                         DBG_PRINT(ERR_DBG, "set on codepoint %d\n", i);
1467                         return FAILURE;
1468                 }
1469         }
1470
1471         /* Program statistics memory */
1472         writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1473
1474         if (nic->device_type == XFRAME_II_DEVICE) {
1475                 val64 = STAT_BC(0x320);
1476                 writeq(val64, &bar0->stat_byte_cnt);
1477         }
1478
1479         /*
1480          * Initializing the sampling rate for the device to calculate the
1481          * bandwidth utilization.
1482          */
1483         val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1484             MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1485         writeq(val64, &bar0->mac_link_util);
1486
1487
1488         /*
1489          * Initializing the Transmit and Receive Traffic Interrupt
1490          * Scheme.
1491          */
1492         /*
1493          * TTI Initialization. Default Tx timer gets us about
1494          * 250 interrupts per sec. Continuous interrupts are enabled
1495          * by default.
1496          */
1497         if (nic->device_type == XFRAME_II_DEVICE) {
1498                 int count = (nic->config.bus_speed * 125)/2;
1499                 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1500         } else {
1501
1502                 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1503         }
1504         val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1505             TTI_DATA1_MEM_TX_URNG_B(0x10) |
1506             TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN;
1507                 if (use_continuous_tx_intrs)
1508                         val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1509         writeq(val64, &bar0->tti_data1_mem);
1510
1511         val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1512             TTI_DATA2_MEM_TX_UFC_B(0x20) |
1513             TTI_DATA2_MEM_TX_UFC_C(0x40) | TTI_DATA2_MEM_TX_UFC_D(0x80);
1514         writeq(val64, &bar0->tti_data2_mem);
1515
1516         val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1517         writeq(val64, &bar0->tti_command_mem);
1518
1519         /*
1520          * Once the operation completes, the Strobe bit of the command
1521          * register will be reset. We poll for this particular condition
1522          * We wait for a maximum of 500ms for the operation to complete,
1523          * if it's not complete by then we return error.
1524          */
1525         time = 0;
1526         while (TRUE) {
1527                 val64 = readq(&bar0->tti_command_mem);
1528                 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1529                         break;
1530                 }
1531                 if (time > 10) {
1532                         DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n",
1533                                   dev->name);
1534                         return -1;
1535                 }
1536                 msleep(50);
1537                 time++;
1538         }
1539
1540         if (nic->config.bimodal) {
1541                 int k = 0;
1542                 for (k = 0; k < config->rx_ring_num; k++) {
1543                         val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1544                         val64 |= TTI_CMD_MEM_OFFSET(0x38+k);
1545                         writeq(val64, &bar0->tti_command_mem);
1546
1547                 /*
1548                  * Once the operation completes, the Strobe bit of the command
1549                  * register will be reset. We poll for this particular condition
1550                  * We wait for a maximum of 500ms for the operation to complete,
1551                  * if it's not complete by then we return error.
1552                 */
1553                         time = 0;
1554                         while (TRUE) {
1555                                 val64 = readq(&bar0->tti_command_mem);
1556                                 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1557                                         break;
1558                                 }
1559                                 if (time > 10) {
1560                                         DBG_PRINT(ERR_DBG,
1561                                                 "%s: TTI init Failed\n",
1562                                         dev->name);
1563                                         return -1;
1564                                 }
1565                                 time++;
1566                                 msleep(50);
1567                         }
1568                 }
1569         } else {
1570
1571                 /* RTI Initialization */
1572                 if (nic->device_type == XFRAME_II_DEVICE) {
1573                         /*
1574                          * Programmed to generate Apprx 500 Intrs per
1575                          * second
1576                          */
1577                         int count = (nic->config.bus_speed * 125)/4;
1578                         val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1579                 } else {
1580                         val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1581                 }
1582                 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1583                     RTI_DATA1_MEM_RX_URNG_B(0x10) |
1584                     RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1585
1586                 writeq(val64, &bar0->rti_data1_mem);
1587
1588                 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1589                     RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1590                 if (nic->intr_type == MSI_X)
1591                     val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1592                                 RTI_DATA2_MEM_RX_UFC_D(0x40));
1593                 else
1594                     val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1595                                 RTI_DATA2_MEM_RX_UFC_D(0x80));
1596                 writeq(val64, &bar0->rti_data2_mem);
1597
1598                 for (i = 0; i < config->rx_ring_num; i++) {
1599                         val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1600                                         | RTI_CMD_MEM_OFFSET(i);
1601                         writeq(val64, &bar0->rti_command_mem);
1602
1603                         /*
1604                          * Once the operation completes, the Strobe bit of the
1605                          * command register will be reset. We poll for this
1606                          * particular condition. We wait for a maximum of 500ms
1607                          * for the operation to complete, if it's not complete
1608                          * by then we return error.
1609                          */
1610                         time = 0;
1611                         while (TRUE) {
1612                                 val64 = readq(&bar0->rti_command_mem);
1613                                 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) {
1614                                         break;
1615                                 }
1616                                 if (time > 10) {
1617                                         DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1618                                                   dev->name);
1619                                         return -1;
1620                                 }
1621                                 time++;
1622                                 msleep(50);
1623                         }
1624                 }
1625         }
1626
1627         /*
1628          * Initializing proper values as Pause threshold into all
1629          * the 8 Queues on Rx side.
1630          */
1631         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1632         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1633
1634         /* Disable RMAC PAD STRIPPING */
1635         add = &bar0->mac_cfg;
1636         val64 = readq(&bar0->mac_cfg);
1637         val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1638         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1639         writel((u32) (val64), add);
1640         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1641         writel((u32) (val64 >> 32), (add + 4));
1642         val64 = readq(&bar0->mac_cfg);
1643
1644         /* Enable FCS stripping by adapter */
1645         add = &bar0->mac_cfg;
1646         val64 = readq(&bar0->mac_cfg);
1647         val64 |= MAC_CFG_RMAC_STRIP_FCS;
1648         if (nic->device_type == XFRAME_II_DEVICE)
1649                 writeq(val64, &bar0->mac_cfg);
1650         else {
1651                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1652                 writel((u32) (val64), add);
1653                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1654                 writel((u32) (val64 >> 32), (add + 4));
1655         }
1656
1657         /*
1658          * Set the time value to be inserted in the pause frame
1659          * generated by xena.
1660          */
1661         val64 = readq(&bar0->rmac_pause_cfg);
1662         val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1663         val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1664         writeq(val64, &bar0->rmac_pause_cfg);
1665
1666         /*
1667          * Set the Threshold Limit for Generating the pause frame
1668          * If the amount of data in any Queue exceeds ratio of
1669          * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1670          * pause frame is generated
1671          */
1672         val64 = 0;
1673         for (i = 0; i < 4; i++) {
1674                 val64 |=
1675                     (((u64) 0xFF00 | nic->mac_control.
1676                       mc_pause_threshold_q0q3)
1677                      << (i * 2 * 8));
1678         }
1679         writeq(val64, &bar0->mc_pause_thresh_q0q3);
1680
1681         val64 = 0;
1682         for (i = 0; i < 4; i++) {
1683                 val64 |=
1684                     (((u64) 0xFF00 | nic->mac_control.
1685                       mc_pause_threshold_q4q7)
1686                      << (i * 2 * 8));
1687         }
1688         writeq(val64, &bar0->mc_pause_thresh_q4q7);
1689
1690         /*
1691          * TxDMA will stop Read request if the number of read split has
1692          * exceeded the limit pointed by shared_splits
1693          */
1694         val64 = readq(&bar0->pic_control);
1695         val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1696         writeq(val64, &bar0->pic_control);
1697
1698         if (nic->config.bus_speed == 266) {
1699                 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1700                 writeq(0x0, &bar0->read_retry_delay);
1701                 writeq(0x0, &bar0->write_retry_delay);
1702         }
1703
1704         /*
1705          * Programming the Herc to split every write transaction
1706          * that does not start on an ADB to reduce disconnects.
1707          */
1708         if (nic->device_type == XFRAME_II_DEVICE) {
1709                 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1710                         MISC_LINK_STABILITY_PRD(3);
1711                 writeq(val64, &bar0->misc_control);
1712                 val64 = readq(&bar0->pic_control2);
1713                 val64 &= ~(BIT(13)|BIT(14)|BIT(15));
1714                 writeq(val64, &bar0->pic_control2);
1715         }
1716         if (strstr(nic->product_name, "CX4")) {
1717                 val64 = TMAC_AVG_IPG(0x17);
1718                 writeq(val64, &bar0->tmac_avg_ipg);
1719         }
1720
1721         return SUCCESS;
1722 }
1723 #define LINK_UP_DOWN_INTERRUPT          1
1724 #define MAC_RMAC_ERR_TIMER              2
1725
1726 static int s2io_link_fault_indication(struct s2io_nic *nic)
1727 {
1728         if (nic->intr_type != INTA)
1729                 return MAC_RMAC_ERR_TIMER;
1730         if (nic->device_type == XFRAME_II_DEVICE)
1731                 return LINK_UP_DOWN_INTERRUPT;
1732         else
1733                 return MAC_RMAC_ERR_TIMER;
1734 }
1735
1736 /**
1737  *  en_dis_able_nic_intrs - Enable or Disable the interrupts
1738  *  @nic: device private variable,
1739  *  @mask: A mask indicating which Intr block must be modified and,
1740  *  @flag: A flag indicating whether to enable or disable the Intrs.
1741  *  Description: This function will either disable or enable the interrupts
1742  *  depending on the flag argument. The mask argument can be used to
1743  *  enable/disable any Intr block.
1744  *  Return Value: NONE.
1745  */
1746
1747 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1748 {
1749         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1750         register u64 val64 = 0, temp64 = 0;
1751
1752         /*  Top level interrupt classification */
1753         /*  PIC Interrupts */
1754         if ((mask & (TX_PIC_INTR | RX_PIC_INTR))) {
1755                 /*  Enable PIC Intrs in the general intr mask register */
1756                 val64 = TXPIC_INT_M;
1757                 if (flag == ENABLE_INTRS) {
1758                         temp64 = readq(&bar0->general_int_mask);
1759                         temp64 &= ~((u64) val64);
1760                         writeq(temp64, &bar0->general_int_mask);
1761                         /*
1762                          * If Hercules adapter enable GPIO otherwise
1763                          * disable all PCIX, Flash, MDIO, IIC and GPIO
1764                          * interrupts for now.
1765                          * TODO
1766                          */
1767                         if (s2io_link_fault_indication(nic) ==
1768                                         LINK_UP_DOWN_INTERRUPT ) {
1769                                 temp64 = readq(&bar0->pic_int_mask);
1770                                 temp64 &= ~((u64) PIC_INT_GPIO);
1771                                 writeq(temp64, &bar0->pic_int_mask);
1772                                 temp64 = readq(&bar0->gpio_int_mask);
1773                                 temp64 &= ~((u64) GPIO_INT_MASK_LINK_UP);
1774                                 writeq(temp64, &bar0->gpio_int_mask);
1775                         } else {
1776                                 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1777                         }
1778                         /*
1779                          * No MSI Support is available presently, so TTI and
1780                          * RTI interrupts are also disabled.
1781                          */
1782                 } else if (flag == DISABLE_INTRS) {
1783                         /*
1784                          * Disable PIC Intrs in the general
1785                          * intr mask register
1786                          */
1787                         writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1788                         temp64 = readq(&bar0->general_int_mask);
1789                         val64 |= temp64;
1790                         writeq(val64, &bar0->general_int_mask);
1791                 }
1792         }
1793
1794         /*  MAC Interrupts */
1795         /*  Enabling/Disabling MAC interrupts */
1796         if (mask & (TX_MAC_INTR | RX_MAC_INTR)) {
1797                 val64 = TXMAC_INT_M | RXMAC_INT_M;
1798                 if (flag == ENABLE_INTRS) {
1799                         temp64 = readq(&bar0->general_int_mask);
1800                         temp64 &= ~((u64) val64);
1801                         writeq(temp64, &bar0->general_int_mask);
1802                         /*
1803                          * All MAC block error interrupts are disabled for now
1804                          * TODO
1805                          */
1806                 } else if (flag == DISABLE_INTRS) {
1807                         /*
1808                          * Disable MAC Intrs in the general intr mask register
1809                          */
1810                         writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask);
1811                         writeq(DISABLE_ALL_INTRS,
1812                                &bar0->mac_rmac_err_mask);
1813
1814                         temp64 = readq(&bar0->general_int_mask);
1815                         val64 |= temp64;
1816                         writeq(val64, &bar0->general_int_mask);
1817                 }
1818         }
1819
1820         /*  Tx traffic interrupts */
1821         if (mask & TX_TRAFFIC_INTR) {
1822                 val64 = TXTRAFFIC_INT_M;
1823                 if (flag == ENABLE_INTRS) {
1824                         temp64 = readq(&bar0->general_int_mask);
1825                         temp64 &= ~((u64) val64);
1826                         writeq(temp64, &bar0->general_int_mask);
1827                         /*
1828                          * Enable all the Tx side interrupts
1829                          * writing 0 Enables all 64 TX interrupt levels
1830                          */
1831                         writeq(0x0, &bar0->tx_traffic_mask);
1832                 } else if (flag == DISABLE_INTRS) {
1833                         /*
1834                          * Disable Tx Traffic Intrs in the general intr mask
1835                          * register.
1836                          */
1837                         writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1838                         temp64 = readq(&bar0->general_int_mask);
1839                         val64 |= temp64;
1840                         writeq(val64, &bar0->general_int_mask);
1841                 }
1842         }
1843
1844         /*  Rx traffic interrupts */
1845         if (mask & RX_TRAFFIC_INTR) {
1846                 val64 = RXTRAFFIC_INT_M;
1847                 if (flag == ENABLE_INTRS) {
1848                         temp64 = readq(&bar0->general_int_mask);
1849                         temp64 &= ~((u64) val64);
1850                         writeq(temp64, &bar0->general_int_mask);
1851                         /* writing 0 Enables all 8 RX interrupt levels */
1852                         writeq(0x0, &bar0->rx_traffic_mask);
1853                 } else if (flag == DISABLE_INTRS) {
1854                         /*
1855                          * Disable Rx Traffic Intrs in the general intr mask
1856                          * register.
1857                          */
1858                         writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1859                         temp64 = readq(&bar0->general_int_mask);
1860                         val64 |= temp64;
1861                         writeq(val64, &bar0->general_int_mask);
1862                 }
1863         }
1864 }
1865
1866 /**
1867  *  verify_pcc_quiescent- Checks for PCC quiescent state
1868  *  Return: 1 If PCC is quiescence
1869  *          0 If PCC is not quiescence
1870  */
1871 static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
1872 {
1873         int ret = 0, herc;
1874         struct XENA_dev_config __iomem *bar0 = sp->bar0;
1875         u64 val64 = readq(&bar0->adapter_status);
1876
1877         herc = (sp->device_type == XFRAME_II_DEVICE);
1878
1879         if (flag == FALSE) {
1880                 if ((!herc && (get_xena_rev_id(sp->pdev) >= 4)) || herc) {
1881                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
1882                                 ret = 1;
1883                 } else {
1884                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
1885                                 ret = 1;
1886                 }
1887         } else {
1888                 if ((!herc && (get_xena_rev_id(sp->pdev) >= 4)) || herc) {
1889                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
1890                              ADAPTER_STATUS_RMAC_PCC_IDLE))
1891                                 ret = 1;
1892                 } else {
1893                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
1894                              ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
1895                                 ret = 1;
1896                 }
1897         }
1898
1899         return ret;
1900 }
1901 /**
1902  *  verify_xena_quiescence - Checks whether the H/W is ready
1903  *  Description: Returns whether the H/W is ready to go or not. Depending
1904  *  on whether adapter enable bit was written or not the comparison
1905  *  differs and the calling function passes the input argument flag to
1906  *  indicate this.
1907  *  Return: 1 If xena is quiescence
1908  *          0 If Xena is not quiescence
1909  */
1910
1911 static int verify_xena_quiescence(struct s2io_nic *sp)
1912 {
1913         int  mode;
1914         struct XENA_dev_config __iomem *bar0 = sp->bar0;
1915         u64 val64 = readq(&bar0->adapter_status);
1916         mode = s2io_verify_pci_mode(sp);
1917
1918         if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
1919                 DBG_PRINT(ERR_DBG, "%s", "TDMA is not ready!");
1920                 return 0;
1921         }
1922         if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
1923         DBG_PRINT(ERR_DBG, "%s", "RDMA is not ready!");
1924                 return 0;
1925         }
1926         if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
1927                 DBG_PRINT(ERR_DBG, "%s", "PFC is not ready!");
1928                 return 0;
1929         }
1930         if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
1931                 DBG_PRINT(ERR_DBG, "%s", "TMAC BUF is not empty!");
1932                 return 0;
1933         }
1934         if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
1935                 DBG_PRINT(ERR_DBG, "%s", "PIC is not QUIESCENT!");
1936                 return 0;
1937         }
1938         if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
1939                 DBG_PRINT(ERR_DBG, "%s", "MC_DRAM is not ready!");
1940                 return 0;
1941         }
1942         if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
1943                 DBG_PRINT(ERR_DBG, "%s", "MC_QUEUES is not ready!");
1944                 return 0;
1945         }
1946         if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
1947                 DBG_PRINT(ERR_DBG, "%s", "M_PLL is not locked!");
1948                 return 0;
1949         }
1950
1951         /*
1952          * In PCI 33 mode, the P_PLL is not used, and therefore,
1953          * the the P_PLL_LOCK bit in the adapter_status register will
1954          * not be asserted.
1955          */
1956         if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
1957                 sp->device_type == XFRAME_II_DEVICE && mode !=
1958                 PCI_MODE_PCI_33) {
1959                 DBG_PRINT(ERR_DBG, "%s", "P_PLL is not locked!");
1960                 return 0;
1961         }
1962         if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1963                         ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1964                 DBG_PRINT(ERR_DBG, "%s", "RC_PRC is not QUIESCENT!");
1965                 return 0;
1966         }
1967         return 1;
1968 }
1969
1970 /**
1971  * fix_mac_address -  Fix for Mac addr problem on Alpha platforms
1972  * @sp: Pointer to device specifc structure
1973  * Description :
1974  * New procedure to clear mac address reading  problems on Alpha platforms
1975  *
1976  */
1977
1978 static void fix_mac_address(struct s2io_nic * sp)
1979 {
1980         struct XENA_dev_config __iomem *bar0 = sp->bar0;
1981         u64 val64;
1982         int i = 0;
1983
1984         while (fix_mac[i] != END_SIGN) {
1985                 writeq(fix_mac[i++], &bar0->gpio_control);
1986                 udelay(10);
1987                 val64 = readq(&bar0->gpio_control);
1988         }
1989 }
1990
1991 /**
1992  *  start_nic - Turns the device on
1993  *  @nic : device private variable.
1994  *  Description:
1995  *  This function actually turns the device on. Before this  function is
1996  *  called,all Registers are configured from their reset states
1997  *  and shared memory is allocated but the NIC is still quiescent. On
1998  *  calling this function, the device interrupts are cleared and the NIC is
1999  *  literally switched on by writing into the adapter control register.
2000  *  Return Value:
2001  *  SUCCESS on success and -1 on failure.
2002  */
2003
2004 static int start_nic(struct s2io_nic *nic)
2005 {
2006         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2007         struct net_device *dev = nic->dev;
2008         register u64 val64 = 0;
2009         u16 subid, i;
2010         struct mac_info *mac_control;
2011         struct config_param *config;
2012
2013         mac_control = &nic->mac_control;
2014         config = &nic->config;
2015
2016         /*  PRC Initialization and configuration */
2017         for (i = 0; i < config->rx_ring_num; i++) {
2018                 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
2019                        &bar0->prc_rxd0_n[i]);
2020
2021                 val64 = readq(&bar0->prc_ctrl_n[i]);
2022                 if (nic->config.bimodal)
2023                         val64 |= PRC_CTRL_BIMODAL_INTERRUPT;
2024                 if (nic->rxd_mode == RXD_MODE_1)
2025                         val64 |= PRC_CTRL_RC_ENABLED;
2026                 else
2027                         val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
2028                 if (nic->device_type == XFRAME_II_DEVICE)
2029                         val64 |= PRC_CTRL_GROUP_READS;
2030                 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2031                 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2032                 writeq(val64, &bar0->prc_ctrl_n[i]);
2033         }
2034
2035         if (nic->rxd_mode == RXD_MODE_3B) {
2036                 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2037                 val64 = readq(&bar0->rx_pa_cfg);
2038                 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2039                 writeq(val64, &bar0->rx_pa_cfg);
2040         }
2041
2042         if (vlan_tag_strip == 0) {
2043                 val64 = readq(&bar0->rx_pa_cfg);
2044                 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2045                 writeq(val64, &bar0->rx_pa_cfg);
2046                 vlan_strip_flag = 0;
2047         }
2048
2049         /*
2050          * Enabling MC-RLDRAM. After enabling the device, we timeout
2051          * for around 100ms, which is approximately the time required
2052          * for the device to be ready for operation.
2053          */
2054         val64 = readq(&bar0->mc_rldram_mrs);
2055         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2056         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2057         val64 = readq(&bar0->mc_rldram_mrs);
2058
2059         msleep(100);    /* Delay by around 100 ms. */
2060
2061         /* Enabling ECC Protection. */
2062         val64 = readq(&bar0->adapter_control);
2063         val64 &= ~ADAPTER_ECC_EN;
2064         writeq(val64, &bar0->adapter_control);
2065
2066         /*
2067          * Clearing any possible Link state change interrupts that
2068          * could have popped up just before Enabling the card.
2069          */
2070         val64 = readq(&bar0->mac_rmac_err_reg);
2071         if (val64)
2072                 writeq(val64, &bar0->mac_rmac_err_reg);
2073
2074         /*
2075          * Verify if the device is ready to be enabled, if so enable
2076          * it.
2077          */
2078         val64 = readq(&bar0->adapter_status);
2079         if (!verify_xena_quiescence(nic)) {
2080                 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2081                 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
2082                           (unsigned long long) val64);
2083                 return FAILURE;
2084         }
2085
2086         /*
2087          * With some switches, link might be already up at this point.
2088          * Because of this weird behavior, when we enable laser,
2089          * we may not get link. We need to handle this. We cannot
2090          * figure out which switch is misbehaving. So we are forced to
2091          * make a global change.
2092          */
2093
2094         /* Enabling Laser. */
2095         val64 = readq(&bar0->adapter_control);
2096         val64 |= ADAPTER_EOI_TX_ON;
2097         writeq(val64, &bar0->adapter_control);
2098
2099         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2100                 /*
2101                  * Dont see link state interrupts initally on some switches,
2102                  * so directly scheduling the link state task here.
2103                  */
2104                 schedule_work(&nic->set_link_task);
2105         }
2106         /* SXE-002: Initialize link and activity LED */
2107         subid = nic->pdev->subsystem_device;
2108         if (((subid & 0xFF) >= 0x07) &&
2109             (nic->device_type == XFRAME_I_DEVICE)) {
2110                 val64 = readq(&bar0->gpio_control);
2111                 val64 |= 0x0000800000000000ULL;
2112                 writeq(val64, &bar0->gpio_control);
2113                 val64 = 0x0411040400000000ULL;
2114                 writeq(val64, (void __iomem *)bar0 + 0x2700);
2115         }
2116
2117         return SUCCESS;
2118 }
2119 /**
2120  * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2121  */
2122 static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data, struct \
2123                                         TxD *txdlp, int get_off)
2124 {
2125         struct s2io_nic *nic = fifo_data->nic;
2126         struct sk_buff *skb;
2127         struct TxD *txds;
2128         u16 j, frg_cnt;
2129
2130         txds = txdlp;
2131         if (txds->Host_Control == (u64)(long)nic->ufo_in_band_v) {
2132                 pci_unmap_single(nic->pdev, (dma_addr_t)
2133                         txds->Buffer_Pointer, sizeof(u64),
2134                         PCI_DMA_TODEVICE);
2135                 txds++;
2136         }
2137
2138         skb = (struct sk_buff *) ((unsigned long)
2139                         txds->Host_Control);
2140         if (!skb) {
2141                 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2142                 return NULL;
2143         }
2144         pci_unmap_single(nic->pdev, (dma_addr_t)
2145                          txds->Buffer_Pointer,
2146                          skb->len - skb->data_len,
2147                          PCI_DMA_TODEVICE);
2148         frg_cnt = skb_shinfo(skb)->nr_frags;
2149         if (frg_cnt) {
2150                 txds++;
2151                 for (j = 0; j < frg_cnt; j++, txds++) {
2152                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2153                         if (!txds->Buffer_Pointer)
2154                                 break;
2155                         pci_unmap_page(nic->pdev, (dma_addr_t)
2156                                         txds->Buffer_Pointer,
2157                                        frag->size, PCI_DMA_TODEVICE);
2158                 }
2159         }
2160         memset(txdlp,0, (sizeof(struct TxD) * fifo_data->max_txds));
2161         return(skb);
2162 }
2163
2164 /**
2165  *  free_tx_buffers - Free all queued Tx buffers
2166  *  @nic : device private variable.
2167  *  Description:
2168  *  Free all queued Tx buffers.
2169  *  Return Value: void
2170 */
2171
2172 static void free_tx_buffers(struct s2io_nic *nic)
2173 {
2174         struct net_device *dev = nic->dev;
2175         struct sk_buff *skb;
2176         struct TxD *txdp;
2177         int i, j;
2178         struct mac_info *mac_control;
2179         struct config_param *config;
2180         int cnt = 0;
2181
2182         mac_control = &nic->mac_control;
2183         config = &nic->config;
2184
2185         for (i = 0; i < config->tx_fifo_num; i++) {
2186                 for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) {
2187                         txdp = (struct TxD *) \
2188                         mac_control->fifos[i].list_info[j].list_virt_addr;
2189                         skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2190                         if (skb) {
2191                                 nic->mac_control.stats_info->sw_stat.mem_freed
2192                                         += skb->truesize;
2193                                 dev_kfree_skb(skb);
2194                                 cnt++;
2195                         }
2196                 }
2197                 DBG_PRINT(INTR_DBG,
2198                           "%s:forcibly freeing %d skbs on FIFO%d\n",
2199                           dev->name, cnt, i);
2200                 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2201                 mac_control->fifos[i].tx_curr_put_info.offset = 0;
2202         }
2203 }
2204
2205 /**
2206  *   stop_nic -  To stop the nic
2207  *   @nic ; device private variable.
2208  *   Description:
2209  *   This function does exactly the opposite of what the start_nic()
2210  *   function does. This function is called to stop the device.
2211  *   Return Value:
2212  *   void.
2213  */
2214
2215 static void stop_nic(struct s2io_nic *nic)
2216 {
2217         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2218         register u64 val64 = 0;
2219         u16 interruptible;
2220         struct mac_info *mac_control;
2221         struct config_param *config;
2222
2223         mac_control = &nic->mac_control;
2224         config = &nic->config;
2225
2226         /*  Disable all interrupts */
2227         interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2228         interruptible |= TX_PIC_INTR | RX_PIC_INTR;
2229         interruptible |= TX_MAC_INTR | RX_MAC_INTR;
2230         en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2231
2232         /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2233         val64 = readq(&bar0->adapter_control);
2234         val64 &= ~(ADAPTER_CNTL_EN);
2235         writeq(val64, &bar0->adapter_control);
2236 }
2237
2238 static int fill_rxd_3buf(struct s2io_nic *nic, struct RxD_t *rxdp, struct \
2239                                 sk_buff *skb)
2240 {
2241         struct net_device *dev = nic->dev;
2242         struct sk_buff *frag_list;
2243         void *tmp;
2244
2245         /* Buffer-1 receives L3/L4 headers */
2246         ((struct RxD3*)rxdp)->Buffer1_ptr = pci_map_single
2247                         (nic->pdev, skb->data, l3l4hdr_size + 4,
2248                         PCI_DMA_FROMDEVICE);
2249
2250         /* skb_shinfo(skb)->frag_list will have L4 data payload */
2251         skb_shinfo(skb)->frag_list = dev_alloc_skb(dev->mtu + ALIGN_SIZE);
2252         if (skb_shinfo(skb)->frag_list == NULL) {
2253                 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
2254                 DBG_PRINT(INFO_DBG, "%s: dev_alloc_skb failed\n ", dev->name);
2255                 return -ENOMEM ;
2256         }
2257         frag_list = skb_shinfo(skb)->frag_list;
2258         skb->truesize += frag_list->truesize;
2259         nic->mac_control.stats_info->sw_stat.mem_allocated
2260                 += frag_list->truesize;
2261         frag_list->next = NULL;
2262         tmp = (void *)ALIGN((long)frag_list->data, ALIGN_SIZE + 1);
2263         frag_list->data = tmp;
2264         skb_reset_tail_pointer(frag_list);
2265
2266         /* Buffer-2 receives L4 data payload */
2267         ((struct RxD3*)rxdp)->Buffer2_ptr = pci_map_single(nic->pdev,
2268                                 frag_list->data, dev->mtu,
2269                                 PCI_DMA_FROMDEVICE);
2270         rxdp->Control_2 |= SET_BUFFER1_SIZE_3(l3l4hdr_size + 4);
2271         rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu);
2272
2273         return SUCCESS;
2274 }
2275
2276 /**
2277  *  fill_rx_buffers - Allocates the Rx side skbs
2278  *  @nic:  device private variable
2279  *  @ring_no: ring number
2280  *  Description:
2281  *  The function allocates Rx side skbs and puts the physical
2282  *  address of these buffers into the RxD buffer pointers, so that the NIC
2283  *  can DMA the received frame into these locations.
2284  *  The NIC supports 3 receive modes, viz
2285  *  1. single buffer,
2286  *  2. three buffer and
2287  *  3. Five buffer modes.
2288  *  Each mode defines how many fragments the received frame will be split
2289  *  up into by the NIC. The frame is split into L3 header, L4 Header,
2290  *  L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2291  *  is split into 3 fragments. As of now only single buffer mode is
2292  *  supported.
2293  *   Return Value:
2294  *  SUCCESS on success or an appropriate -ve value on failure.
2295  */
2296
2297 static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
2298 {
2299         struct net_device *dev = nic->dev;
2300         struct sk_buff *skb;
2301         struct RxD_t *rxdp;
2302         int off, off1, size, block_no, block_no1;
2303         u32 alloc_tab = 0;
2304         u32 alloc_cnt;
2305         struct mac_info *mac_control;
2306         struct config_param *config;
2307         u64 tmp;
2308         struct buffAdd *ba;
2309         unsigned long flags;
2310         struct RxD_t *first_rxdp = NULL;
2311         u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
2312
2313         mac_control = &nic->mac_control;
2314         config = &nic->config;
2315         alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
2316             atomic_read(&nic->rx_bufs_left[ring_no]);
2317
2318         block_no1 = mac_control->rings[ring_no].rx_curr_get_info.block_index;
2319         off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
2320         while (alloc_tab < alloc_cnt) {
2321                 block_no = mac_control->rings[ring_no].rx_curr_put_info.
2322                     block_index;
2323                 off = mac_control->rings[ring_no].rx_curr_put_info.offset;
2324
2325                 rxdp = mac_control->rings[ring_no].
2326                                 rx_blocks[block_no].rxds[off].virt_addr;
2327
2328                 if ((block_no == block_no1) && (off == off1) &&
2329                                         (rxdp->Host_Control)) {
2330                         DBG_PRINT(INTR_DBG, "%s: Get and Put",
2331                                   dev->name);
2332                         DBG_PRINT(INTR_DBG, " info equated\n");
2333                         goto end;
2334                 }
2335                 if (off && (off == rxd_count[nic->rxd_mode])) {
2336                         mac_control->rings[ring_no].rx_curr_put_info.
2337                             block_index++;
2338                         if (mac_control->rings[ring_no].rx_curr_put_info.
2339                             block_index == mac_control->rings[ring_no].
2340                                         block_count)
2341                                 mac_control->rings[ring_no].rx_curr_put_info.
2342                                         block_index = 0;
2343                         block_no = mac_control->rings[ring_no].
2344                                         rx_curr_put_info.block_index;
2345                         if (off == rxd_count[nic->rxd_mode])
2346                                 off = 0;
2347                         mac_control->rings[ring_no].rx_curr_put_info.
2348                                 offset = off;
2349                         rxdp = mac_control->rings[ring_no].
2350                                 rx_blocks[block_no].block_virt_addr;
2351                         DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2352                                   dev->name, rxdp);
2353                 }
2354                 if(!napi) {
2355                         spin_lock_irqsave(&nic->put_lock, flags);
2356                         mac_control->rings[ring_no].put_pos =
2357                         (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2358                         spin_unlock_irqrestore(&nic->put_lock, flags);
2359                 } else {
2360                         mac_control->rings[ring_no].put_pos =
2361                         (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2362                 }
2363                 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2364                         ((nic->rxd_mode >= RXD_MODE_3A) &&
2365                                 (rxdp->Control_2 & BIT(0)))) {
2366                         mac_control->rings[ring_no].rx_curr_put_info.
2367                                         offset = off;
2368                         goto end;
2369                 }
2370                 /* calculate size of skb based on ring mode */
2371                 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
2372                                 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2373                 if (nic->rxd_mode == RXD_MODE_1)
2374                         size += NET_IP_ALIGN;
2375                 else if (nic->rxd_mode == RXD_MODE_3B)
2376                         size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2377                 else
2378                         size = l3l4hdr_size + ALIGN_SIZE + BUF0_LEN + 4;
2379
2380                 /* allocate skb */
2381                 skb = dev_alloc_skb(size);
2382                 if(!skb) {
2383                         DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
2384                         DBG_PRINT(INFO_DBG, "memory to allocate SKBs\n");
2385                         if (first_rxdp) {
2386                                 wmb();
2387                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2388                         }
2389                         nic->mac_control.stats_info->sw_stat. \
2390                                 mem_alloc_fail_cnt++;
2391                         return -ENOMEM ;
2392                 }
2393                 nic->mac_control.stats_info->sw_stat.mem_allocated
2394                         += skb->truesize;
2395                 if (nic->rxd_mode == RXD_MODE_1) {
2396                         /* 1 buffer mode - normal operation mode */
2397                         memset(rxdp, 0, sizeof(struct RxD1));
2398                         skb_reserve(skb, NET_IP_ALIGN);
2399                         ((struct RxD1*)rxdp)->Buffer0_ptr = pci_map_single
2400                             (nic->pdev, skb->data, size - NET_IP_ALIGN,
2401                                 PCI_DMA_FROMDEVICE);
2402                         rxdp->Control_2 =
2403                                 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2404
2405                 } else if (nic->rxd_mode >= RXD_MODE_3A) {
2406                         /*
2407                          * 2 or 3 buffer mode -
2408                          * Both 2 buffer mode and 3 buffer mode provides 128
2409                          * byte aligned receive buffers.
2410                          *
2411                          * 3 buffer mode provides header separation where in
2412                          * skb->data will have L3/L4 headers where as
2413                          * skb_shinfo(skb)->frag_list will have the L4 data
2414                          * payload
2415                          */
2416
2417                         /* save buffer pointers to avoid frequent dma mapping */
2418                         Buffer0_ptr = ((struct RxD3*)rxdp)->Buffer0_ptr;
2419                         Buffer1_ptr = ((struct RxD3*)rxdp)->Buffer1_ptr;
2420                         memset(rxdp, 0, sizeof(struct RxD3));
2421                         /* restore the buffer pointers for dma sync*/
2422                         ((struct RxD3*)rxdp)->Buffer0_ptr = Buffer0_ptr;
2423                         ((struct RxD3*)rxdp)->Buffer1_ptr = Buffer1_ptr;
2424
2425                         ba = &mac_control->rings[ring_no].ba[block_no][off];
2426                         skb_reserve(skb, BUF0_LEN);
2427                         tmp = (u64)(unsigned long) skb->data;
2428                         tmp += ALIGN_SIZE;
2429                         tmp &= ~ALIGN_SIZE;
2430                         skb->data = (void *) (unsigned long)tmp;
2431                         skb_reset_tail_pointer(skb);
2432
2433                         if (!(((struct RxD3*)rxdp)->Buffer0_ptr))
2434                                 ((struct RxD3*)rxdp)->Buffer0_ptr =
2435                                    pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
2436                                            PCI_DMA_FROMDEVICE);
2437                         else
2438                                 pci_dma_sync_single_for_device(nic->pdev,
2439                                 (dma_addr_t) ((struct RxD3*)rxdp)->Buffer0_ptr,
2440                                     BUF0_LEN, PCI_DMA_FROMDEVICE);
2441                         rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2442                         if (nic->rxd_mode == RXD_MODE_3B) {
2443                                 /* Two buffer mode */
2444
2445                                 /*
2446                                  * Buffer2 will have L3/L4 header plus
2447                                  * L4 payload
2448                                  */
2449                                 ((struct RxD3*)rxdp)->Buffer2_ptr = pci_map_single
2450                                 (nic->pdev, skb->data, dev->mtu + 4,
2451                                                 PCI_DMA_FROMDEVICE);
2452
2453                                 /* Buffer-1 will be dummy buffer. Not used */
2454                                 if (!(((struct RxD3*)rxdp)->Buffer1_ptr)) {
2455                                         ((struct RxD3*)rxdp)->Buffer1_ptr =
2456                                                 pci_map_single(nic->pdev,
2457                                                 ba->ba_1, BUF1_LEN,
2458                                                 PCI_DMA_FROMDEVICE);
2459                                 }
2460                                 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2461                                 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2462                                                                 (dev->mtu + 4);
2463                         } else {
2464                                 /* 3 buffer mode */
2465                                 if (fill_rxd_3buf(nic, rxdp, skb) == -ENOMEM) {
2466                                         nic->mac_control.stats_info->sw_stat.\
2467                                         mem_freed += skb->truesize;
2468                                         dev_kfree_skb_irq(skb);
2469                                         if (first_rxdp) {
2470                                                 wmb();
2471                                                 first_rxdp->Control_1 |=
2472                                                         RXD_OWN_XENA;
2473                                         }
2474                                         return -ENOMEM ;
2475                                 }
2476                         }
2477                         rxdp->Control_2 |= BIT(0);
2478                 }
2479                 rxdp->Host_Control = (unsigned long) (skb);
2480                 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2481                         rxdp->Control_1 |= RXD_OWN_XENA;
2482                 off++;
2483                 if (off == (rxd_count[nic->rxd_mode] + 1))
2484                         off = 0;
2485                 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
2486
2487                 rxdp->Control_2 |= SET_RXD_MARKER;
2488                 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2489                         if (first_rxdp) {
2490                                 wmb();
2491                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2492                         }
2493                         first_rxdp = rxdp;
2494                 }
2495                 atomic_inc(&nic->rx_bufs_left[ring_no]);
2496                 alloc_tab++;
2497         }
2498
2499       end:
2500         /* Transfer ownership of first descriptor to adapter just before
2501          * exiting. Before that, use memory barrier so that ownership
2502          * and other fields are seen by adapter correctly.
2503          */
2504         if (first_rxdp) {
2505                 wmb();
2506                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2507         }
2508
2509         return SUCCESS;
2510 }
2511
2512 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2513 {
2514         struct net_device *dev = sp->dev;
2515         int j;
2516         struct sk_buff *skb;
2517         struct RxD_t *rxdp;
2518         struct mac_info *mac_control;
2519         struct buffAdd *ba;
2520
2521         mac_control = &sp->mac_control;
2522         for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2523                 rxdp = mac_control->rings[ring_no].
2524                                 rx_blocks[blk].rxds[j].virt_addr;
2525                 skb = (struct sk_buff *)
2526                         ((unsigned long) rxdp->Host_Control);
2527                 if (!skb) {
2528                         continue;
2529                 }
2530                 if (sp->rxd_mode == RXD_MODE_1) {
2531                         pci_unmap_single(sp->pdev, (dma_addr_t)
2532                                  ((struct RxD1*)rxdp)->Buffer0_ptr,
2533                                  dev->mtu +
2534                                  HEADER_ETHERNET_II_802_3_SIZE
2535                                  + HEADER_802_2_SIZE +
2536                                  HEADER_SNAP_SIZE,
2537                                  PCI_DMA_FROMDEVICE);
2538                         memset(rxdp, 0, sizeof(struct RxD1));
2539                 } else if(sp->rxd_mode == RXD_MODE_3B) {
2540                         ba = &mac_control->rings[ring_no].
2541                                 ba[blk][j];
2542                         pci_unmap_single(sp->pdev, (dma_addr_t)
2543                                  ((struct RxD3*)rxdp)->Buffer0_ptr,
2544                                  BUF0_LEN,
2545                                  PCI_DMA_FROMDEVICE);
2546                         pci_unmap_single(sp->pdev, (dma_addr_t)
2547                                  ((struct RxD3*)rxdp)->Buffer1_ptr,
2548                                  BUF1_LEN,
2549                                  PCI_DMA_FROMDEVICE);
2550                         pci_unmap_single(sp->pdev, (dma_addr_t)
2551                                  ((struct RxD3*)rxdp)->Buffer2_ptr,
2552                                  dev->mtu + 4,
2553                                  PCI_DMA_FROMDEVICE);
2554                         memset(rxdp, 0, sizeof(struct RxD3));
2555                 } else {
2556                         pci_unmap_single(sp->pdev, (dma_addr_t)
2557                                 ((struct RxD3*)rxdp)->Buffer0_ptr, BUF0_LEN,
2558                                 PCI_DMA_FROMDEVICE);
2559                         pci_unmap_single(sp->pdev, (dma_addr_t)
2560                                 ((struct RxD3*)rxdp)->Buffer1_ptr,
2561                                 l3l4hdr_size + 4,
2562                                 PCI_DMA_FROMDEVICE);
2563                         pci_unmap_single(sp->pdev, (dma_addr_t)
2564                                 ((struct RxD3*)rxdp)->Buffer2_ptr, dev->mtu,
2565                                 PCI_DMA_FROMDEVICE);
2566                         memset(rxdp, 0, sizeof(struct RxD3));
2567                 }
2568                 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
2569                 dev_kfree_skb(skb);
2570                 atomic_dec(&sp->rx_bufs_left[ring_no]);
2571         }
2572 }
2573
2574 /**
2575  *  free_rx_buffers - Frees all Rx buffers
2576  *  @sp: device private variable.
2577  *  Description:
2578  *  This function will free all Rx buffers allocated by host.
2579  *  Return Value:
2580  *  NONE.
2581  */
2582
2583 static void free_rx_buffers(struct s2io_nic *sp)
2584 {
2585         struct net_device *dev = sp->dev;
2586         int i, blk = 0, buf_cnt = 0;
2587         struct mac_info *mac_control;
2588         struct config_param *config;
2589
2590         mac_control = &sp->mac_control;
2591         config = &sp->config;
2592
2593         for (i = 0; i < config->rx_ring_num; i++) {
2594                 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2595                         free_rxd_blk(sp,i,blk);
2596
2597                 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2598                 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2599                 mac_control->rings[i].rx_curr_put_info.offset = 0;
2600                 mac_control->rings[i].rx_curr_get_info.offset = 0;
2601                 atomic_set(&sp->rx_bufs_left[i], 0);
2602                 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2603                           dev->name, buf_cnt, i);
2604         }
2605 }
2606
2607 /**
2608  * s2io_poll - Rx interrupt handler for NAPI support
2609  * @dev : pointer to the device structure.
2610  * @budget : The number of packets that were budgeted to be processed
2611  * during  one pass through the 'Poll" function.
2612  * Description:
2613  * Comes into picture only if NAPI support has been incorporated. It does
2614  * the same thing that rx_intr_handler does, but not in a interrupt context
2615  * also It will process only a given number of packets.
2616  * Return value:
2617  * 0 on success and 1 if there are No Rx packets to be processed.
2618  */
2619
2620 static int s2io_poll(struct net_device *dev, int *budget)
2621 {
2622         struct s2io_nic *nic = dev->priv;
2623         int pkt_cnt = 0, org_pkts_to_process;
2624         struct mac_info *mac_control;
2625         struct config_param *config;
2626         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2627         int i;
2628
2629         atomic_inc(&nic->isr_cnt);
2630         mac_control = &nic->mac_control;
2631         config = &nic->config;
2632
2633         nic->pkts_to_process = *budget;
2634         if (nic->pkts_to_process > dev->quota)
2635                 nic->pkts_to_process = dev->quota;
2636         org_pkts_to_process = nic->pkts_to_process;
2637
2638         writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
2639         readl(&bar0->rx_traffic_int);
2640
2641         for (i = 0; i < config->rx_ring_num; i++) {
2642                 rx_intr_handler(&mac_control->rings[i]);
2643                 pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
2644                 if (!nic->pkts_to_process) {
2645                         /* Quota for the current iteration has been met */
2646                         goto no_rx;
2647                 }
2648         }
2649         if (!pkt_cnt)
2650                 pkt_cnt = 1;
2651
2652         dev->quota -= pkt_cnt;
2653         *budget -= pkt_cnt;
2654         netif_rx_complete(dev);
2655
2656         for (i = 0; i < config->rx_ring_num; i++) {
2657                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2658                         DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2659                         DBG_PRINT(INFO_DBG, " in Rx Poll!!\n");
2660                         break;
2661                 }
2662         }
2663         /* Re enable the Rx interrupts. */
2664         writeq(0x0, &bar0->rx_traffic_mask);
2665         readl(&bar0->rx_traffic_mask);
2666         atomic_dec(&nic->isr_cnt);
2667         return 0;
2668
2669 no_rx:
2670         dev->quota -= pkt_cnt;
2671         *budget -= pkt_cnt;
2672
2673         for (i = 0; i < config->rx_ring_num; i++) {
2674                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2675                         DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2676                         DBG_PRINT(INFO_DBG, " in Rx Poll!!\n");
2677                         break;
2678                 }
2679         }
2680         atomic_dec(&nic->isr_cnt);
2681         return 1;
2682 }
2683
2684 #ifdef CONFIG_NET_POLL_CONTROLLER
2685 /**
2686  * s2io_netpoll - netpoll event handler entry point
2687  * @dev : pointer to the device structure.
2688  * Description:
2689  *      This function will be called by upper layer to check for events on the
2690  * interface in situations where interrupts are disabled. It is used for
2691  * specific in-kernel networking tasks, such as remote consoles and kernel
2692  * debugging over the network (example netdump in RedHat).
2693  */
2694 static void s2io_netpoll(struct net_device *dev)
2695 {
2696         struct s2io_nic *nic = dev->priv;
2697         struct mac_info *mac_control;
2698         struct config_param *config;
2699         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2700         u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2701         int i;
2702
2703         disable_irq(dev->irq);
2704
2705         atomic_inc(&nic->isr_cnt);
2706         mac_control = &nic->mac_control;
2707         config = &nic->config;
2708
2709         writeq(val64, &bar0->rx_traffic_int);
2710         writeq(val64, &bar0->tx_traffic_int);
2711
2712         /* we need to free up the transmitted skbufs or else netpoll will
2713          * run out of skbs and will fail and eventually netpoll application such
2714          * as netdump will fail.
2715          */
2716         for (i = 0; i < config->tx_fifo_num; i++)
2717                 tx_intr_handler(&mac_control->fifos[i]);
2718
2719         /* check for received packet and indicate up to network */
2720         for (i = 0; i < config->rx_ring_num; i++)
2721                 rx_intr_handler(&mac_control->rings[i]);
2722
2723         for (i = 0; i < config->rx_ring_num; i++) {
2724                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2725                         DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2726                         DBG_PRINT(INFO_DBG, " in Rx Netpoll!!\n");
2727                         break;
2728                 }
2729         }
2730         atomic_dec(&nic->isr_cnt);
2731         enable_irq(dev->irq);
2732         return;
2733 }
2734 #endif
2735
2736 /**
2737  *  rx_intr_handler - Rx interrupt handler
2738  *  @nic: device private variable.
2739  *  Description:
2740  *  If the interrupt is because of a received frame or if the
2741  *  receive ring contains fresh as yet un-processed frames,this function is
2742  *  called. It picks out the RxD at which place the last Rx processing had
2743  *  stopped and sends the skb to the OSM's Rx handler and then increments
2744  *  the offset.
2745  *  Return Value:
2746  *  NONE.
2747  */
2748 static void rx_intr_handler(struct ring_info *ring_data)
2749 {
2750         struct s2io_nic *nic = ring_data->nic;
2751         struct net_device *dev = (struct net_device *) nic->dev;
2752         int get_block, put_block, put_offset;
2753         struct rx_curr_get_info get_info, put_info;
2754         struct RxD_t *rxdp;
2755         struct sk_buff *skb;
2756         int pkt_cnt = 0;
2757         int i;
2758
2759         spin_lock(&nic->rx_lock);
2760         if (atomic_read(&nic->card_state) == CARD_DOWN) {
2761                 DBG_PRINT(INTR_DBG, "%s: %s going down for reset\n",
2762                           __FUNCTION__, dev->name);
2763                 spin_unlock(&nic->rx_lock);
2764                 return;
2765         }
2766
2767         get_info = ring_data->rx_curr_get_info;
2768         get_block = get_info.block_index;
2769         memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
2770         put_block = put_info.block_index;
2771         rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2772         if (!napi) {
2773                 spin_lock(&nic->put_lock);
2774                 put_offset = ring_data->put_pos;
2775                 spin_unlock(&nic->put_lock);
2776         } else
2777                 put_offset = ring_data->put_pos;
2778
2779         while (RXD_IS_UP2DT(rxdp)) {
2780                 /*
2781                  * If your are next to put index then it's
2782                  * FIFO full condition
2783                  */
2784                 if ((get_block == put_block) &&
2785                     (get_info.offset + 1) == put_info.offset) {
2786                         DBG_PRINT(INTR_DBG, "%s: Ring Full\n",dev->name);
2787                         break;
2788                 }
2789                 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2790                 if (skb == NULL) {
2791                         DBG_PRINT(ERR_DBG, "%s: The skb is ",
2792                                   dev->name);
2793                         DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
2794                         spin_unlock(&nic->rx_lock);
2795                         return;
2796                 }
2797                 if (nic->rxd_mode == RXD_MODE_1) {
2798                         pci_unmap_single(nic->pdev, (dma_addr_t)
2799                                  ((struct RxD1*)rxdp)->Buffer0_ptr,
2800                                  dev->mtu +
2801                                  HEADER_ETHERNET_II_802_3_SIZE +
2802                                  HEADER_802_2_SIZE +
2803                                  HEADER_SNAP_SIZE,
2804                                  PCI_DMA_FROMDEVICE);
2805                 } else if (nic->rxd_mode == RXD_MODE_3B) {
2806                         pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
2807                                  ((struct RxD3*)rxdp)->Buffer0_ptr,
2808                                  BUF0_LEN, PCI_DMA_FROMDEVICE);
2809                         pci_unmap_single(nic->pdev, (dma_addr_t)
2810                                  ((struct RxD3*)rxdp)->Buffer2_ptr,
2811                                  dev->mtu + 4,
2812                                  PCI_DMA_FROMDEVICE);
2813                 } else {
2814                         pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
2815                                          ((struct RxD3*)rxdp)->Buffer0_ptr, BUF0_LEN,
2816                                          PCI_DMA_FROMDEVICE);
2817                         pci_unmap_single(nic->pdev, (dma_addr_t)
2818                                          ((struct RxD3*)rxdp)->Buffer1_ptr,
2819                                          l3l4hdr_size + 4,
2820                                          PCI_DMA_FROMDEVICE);
2821                         pci_unmap_single(nic->pdev, (dma_addr_t)
2822                                          ((struct RxD3*)rxdp)->Buffer2_ptr,
2823                                          dev->mtu, PCI_DMA_FROMDEVICE);
2824                 }
2825                 prefetch(skb->data);
2826                 rx_osm_handler(ring_data, rxdp);
2827                 get_info.offset++;
2828                 ring_data->rx_curr_get_info.offset = get_info.offset;
2829                 rxdp = ring_data->rx_blocks[get_block].
2830                                 rxds[get_info.offset].virt_addr;
2831                 if (get_info.offset == rxd_count[nic->rxd_mode]) {
2832                         get_info.offset = 0;
2833                         ring_data->rx_curr_get_info.offset = get_info.offset;
2834                         get_block++;
2835                         if (get_block == ring_data->block_count)
2836                                 get_block = 0;
2837                         ring_data->rx_curr_get_info.block_index = get_block;
2838                         rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2839                 }
2840
2841                 nic->pkts_to_process -= 1;
2842                 if ((napi) && (!nic->pkts_to_process))
2843                         break;
2844                 pkt_cnt++;
2845                 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2846                         break;
2847         }
2848         if (nic->lro) {
2849                 /* Clear all LRO sessions before exiting */
2850                 for (i=0; i<MAX_LRO_SESSIONS; i++) {
2851                         struct lro *lro = &nic->lro0_n[i];
2852                         if (lro->in_use) {
2853                                 update_L3L4_header(nic, lro);
2854                                 queue_rx_frame(lro->parent);
2855                                 clear_lro_session(lro);
2856                         }
2857                 }
2858         }
2859
2860         spin_unlock(&nic->rx_lock);
2861 }
2862
2863 /**
2864  *  tx_intr_handler - Transmit interrupt handler
2865  *  @nic : device private variable
2866  *  Description:
2867  *  If an interrupt was raised to indicate DMA complete of the
2868  *  Tx packet, this function is called. It identifies the last TxD
2869  *  whose buffer was freed and frees all skbs whose data have already
2870  *  DMA'ed into the NICs internal memory.
2871  *  Return Value:
2872  *  NONE
2873  */
2874
2875 static void tx_intr_handler(struct fifo_info *fifo_data)
2876 {
2877         struct s2io_nic *nic = fifo_data->nic;
2878         struct net_device *dev = (struct net_device *) nic->dev;
2879         struct tx_curr_get_info get_info, put_info;
2880         struct sk_buff *skb;
2881         struct TxD *txdlp;
2882
2883         get_info = fifo_data->tx_curr_get_info;
2884         memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
2885         txdlp = (struct TxD *) fifo_data->list_info[get_info.offset].
2886             list_virt_addr;
2887         while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
2888                (get_info.offset != put_info.offset) &&
2889                (txdlp->Host_Control)) {
2890                 /* Check for TxD errors */
2891                 if (txdlp->Control_1 & TXD_T_CODE) {
2892                         unsigned long long err;
2893                         err = txdlp->Control_1 & TXD_T_CODE;
2894                         if (err & 0x1) {
2895                                 nic->mac_control.stats_info->sw_stat.
2896                                                 parity_err_cnt++;
2897                         }
2898
2899                         /* update t_code statistics */
2900                         err >>= 48;
2901                         switch(err) {
2902                                 case 2:
2903                                         nic->mac_control.stats_info->sw_stat.
2904                                                         tx_buf_abort_cnt++;
2905                                 break;
2906
2907                                 case 3:
2908                                         nic->mac_control.stats_info->sw_stat.
2909                                                         tx_desc_abort_cnt++;
2910                                 break;
2911
2912                                 case 7:
2913                                         nic->mac_control.stats_info->sw_stat.
2914                                                         tx_parity_err_cnt++;
2915                                 break;
2916
2917                                 case 10:
2918                                         nic->mac_control.stats_info->sw_stat.
2919                                                         tx_link_loss_cnt++;
2920                                 break;
2921
2922                                 case 15:
2923                                         nic->mac_control.stats_info->sw_stat.
2924                                                         tx_list_proc_err_cnt++;
2925                                 break;
2926                         }
2927                 }
2928
2929                 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
2930                 if (skb == NULL) {
2931                         DBG_PRINT(ERR_DBG, "%s: Null skb ",
2932                         __FUNCTION__);
2933                         DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
2934                         return;
2935                 }
2936
2937                 /* Updating the statistics block */
2938                 nic->stats.tx_bytes += skb->len;
2939                 nic->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
2940                 dev_kfree_skb_irq(skb);
2941
2942                 get_info.offset++;
2943                 if (get_info.offset == get_info.fifo_len + 1)
2944                         get_info.offset = 0;
2945                 txdlp = (struct TxD *) fifo_data->list_info
2946                     [get_info.offset].list_virt_addr;
2947                 fifo_data->tx_curr_get_info.offset =
2948                     get_info.offset;
2949         }
2950
2951         spin_lock(&nic->tx_lock);
2952         if (netif_queue_stopped(dev))
2953                 netif_wake_queue(dev);
2954         spin_unlock(&nic->tx_lock);
2955 }
2956
2957 /**
2958  *  s2io_mdio_write - Function to write in to MDIO registers
2959  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2960  *  @addr     : address value
2961  *  @value    : data value
2962  *  @dev      : pointer to net_device structure
2963  *  Description:
2964  *  This function is used to write values to the MDIO registers
2965  *  NONE
2966  */
2967 static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
2968 {
2969         u64 val64 = 0x0;
2970         struct s2io_nic *sp = dev->priv;
2971         struct XENA_dev_config __iomem *bar0 = sp->bar0;
2972
2973         //address transaction
2974         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2975                         | MDIO_MMD_DEV_ADDR(mmd_type)
2976                         | MDIO_MMS_PRT_ADDR(0x0);
2977         writeq(val64, &bar0->mdio_control);
2978         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2979         writeq(val64, &bar0->mdio_control);
2980         udelay(100);
2981
2982         //Data transaction
2983         val64 = 0x0;
2984         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2985                         | MDIO_MMD_DEV_ADDR(mmd_type)
2986                         | MDIO_MMS_PRT_ADDR(0x0)
2987                         | MDIO_MDIO_DATA(value)
2988                         | MDIO_OP(MDIO_OP_WRITE_TRANS);
2989         writeq(val64, &bar0->mdio_control);
2990         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2991         writeq(val64, &bar0->mdio_control);
2992         udelay(100);
2993
2994         val64 = 0x0;
2995         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2996         | MDIO_MMD_DEV_ADDR(mmd_type)
2997         | MDIO_MMS_PRT_ADDR(0x0)
2998         | MDIO_OP(MDIO_OP_READ_TRANS);
2999         writeq(val64, &bar0->mdio_control);
3000         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3001         writeq(val64, &bar0->mdio_control);
3002         udelay(100);
3003
3004 }
3005
3006 /**
3007  *  s2io_mdio_read - Function to write in to MDIO registers
3008  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3009  *  @addr     : address value
3010  *  @dev      : pointer to net_device structure
3011  *  Description:
3012  *  This function is used to read values to the MDIO registers
3013  *  NONE
3014  */
3015 static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3016 {
3017         u64 val64 = 0x0;
3018         u64 rval64 = 0x0;
3019         struct s2io_nic *sp = dev->priv;
3020         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3021
3022         /* address transaction */
3023         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3024                         | MDIO_MMD_DEV_ADDR(mmd_type)
3025                         | MDIO_MMS_PRT_ADDR(0x0);
3026         writeq(val64, &bar0->mdio_control);
3027         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3028         writeq(val64, &bar0->mdio_control);
3029         udelay(100);
3030
3031         /* Data transaction */
3032         val64 = 0x0;
3033         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3034                         | MDIO_MMD_DEV_ADDR(mmd_type)
3035                         | MDIO_MMS_PRT_ADDR(0x0)
3036                         | MDIO_OP(MDIO_OP_READ_TRANS);
3037         writeq(val64, &bar0->mdio_control);
3038         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3039         writeq(val64, &bar0->mdio_control);
3040         udelay(100);
3041
3042         /* Read the value from regs */
3043         rval64 = readq(&bar0->mdio_control);
3044         rval64 = rval64 & 0xFFFF0000;
3045         rval64 = rval64 >> 16;
3046         return rval64;
3047 }
3048 /**
3049  *  s2io_chk_xpak_counter - Function to check the status of the xpak counters
3050  *  @counter      : couter value to be updated
3051  *  @flag         : flag to indicate the status
3052  *  @type         : counter type
3053  *  Description:
3054  *  This function is to check the status of the xpak counters value
3055  *  NONE
3056  */
3057
3058 static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type)
3059 {
3060         u64 mask = 0x3;
3061         u64 val64;
3062         int i;
3063         for(i = 0; i <index; i++)
3064                 mask = mask << 0x2;
3065
3066         if(flag > 0)
3067         {
3068                 *counter = *counter + 1;
3069                 val64 = *regs_stat & mask;
3070                 val64 = val64 >> (index * 0x2);
3071                 val64 = val64 + 1;
3072                 if(val64 == 3)
3073                 {
3074                         switch(type)
3075                         {
3076                         case 1:
3077                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3078                                           "service. Excessive temperatures may "
3079                                           "result in premature transceiver "
3080                                           "failure \n");
3081                         break;
3082                         case 2:
3083                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3084                                           "service Excessive bias currents may "
3085                                           "indicate imminent laser diode "
3086                                           "failure \n");
3087                         break;
3088                         case 3:
3089                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3090                                           "service Excessive laser output "
3091                                           "power may saturate far-end "
3092                                           "receiver\n");
3093                         break;
3094                         default:
3095                                 DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm "
3096                                           "type \n");
3097                         }
3098                         val64 = 0x0;
3099                 }
3100                 val64 = val64 << (index * 0x2);
3101                 *regs_stat = (*regs_stat & (~mask)) | (val64);
3102
3103         } else {
3104                 *regs_stat = *regs_stat & (~mask);
3105         }
3106 }
3107
3108 /**
3109  *  s2io_updt_xpak_counter - Function to update the xpak counters
3110  *  @dev         : pointer to net_device struct
3111  *  Description:
3112  *  This function is to upate the status of the xpak counters value
3113  *  NONE
3114  */
3115 static void s2io_updt_xpak_counter(struct net_device *dev)
3116 {
3117         u16 flag  = 0x0;
3118         u16 type  = 0x0;
3119         u16 val16 = 0x0;
3120         u64 val64 = 0x0;
3121         u64 addr  = 0x0;
3122
3123         struct s2io_nic *sp = dev->priv;
3124         struct stat_block *stat_info = sp->mac_control.stats_info;
3125
3126         /* Check the communication with the MDIO slave */
3127         addr = 0x0000;
3128         val64 = 0x0;
3129         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3130         if((val64 == 0xFFFF) || (val64 == 0x0000))
3131         {
3132                 DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
3133                           "Returned %llx\n", (unsigned long long)val64);
3134                 return;
3135         }
3136
3137         /* Check for the expecte value of 2040 at PMA address 0x0000 */
3138         if(val64 != 0x2040)
3139         {
3140                 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
3141                 DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x2040\n",
3142                           (unsigned long long)val64);
3143                 return;
3144         }
3145
3146         /* Loading the DOM register to MDIO register */
3147         addr = 0xA100;
3148         s2io_mdio_write(MDIO_MMD_PMA_DEV_ADDR, addr, val16, dev);
3149         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3150
3151         /* Reading the Alarm flags */
3152         addr = 0xA070;
3153         val64 = 0x0;
3154         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3155
3156         flag = CHECKBIT(val64, 0x7);
3157         type = 1;
3158         s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
3159                                 &stat_info->xpak_stat.xpak_regs_stat,
3160                                 0x0, flag, type);
3161
3162         if(CHECKBIT(val64, 0x6))
3163                 stat_info->xpak_stat.alarm_transceiver_temp_low++;
3164
3165         flag = CHECKBIT(val64, 0x3);
3166         type = 2;
3167         s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
3168                                 &stat_info->xpak_stat.xpak_regs_stat,
3169                                 0x2, flag, type);
3170
3171         if(CHECKBIT(val64, 0x2))
3172                 stat_info->xpak_stat.alarm_laser_bias_current_low++;
3173
3174         flag = CHECKBIT(val64, 0x1);
3175         type = 3;
3176         s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
3177                                 &stat_info->xpak_stat.xpak_regs_stat,
3178                                 0x4, flag, type);
3179
3180         if(CHECKBIT(val64, 0x0))
3181                 stat_info->xpak_stat.alarm_laser_output_power_low++;
3182
3183         /* Reading the Warning flags */
3184         addr = 0xA074;
3185         val64 = 0x0;
3186         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3187
3188         if(CHECKBIT(val64, 0x7))
3189                 stat_info->xpak_stat.warn_transceiver_temp_high++;
3190
3191         if(CHECKBIT(val64, 0x6))
3192                 stat_info->xpak_stat.warn_transceiver_temp_low++;
3193
3194         if(CHECKBIT(val64, 0x3))
3195                 stat_info->xpak_stat.warn_laser_bias_current_high++;
3196
3197         if(CHECKBIT(val64, 0x2))
3198                 stat_info->xpak_stat.warn_laser_bias_current_low++;
3199
3200         if(CHECKBIT(val64, 0x1))
3201                 stat_info->xpak_stat.warn_laser_output_power_high++;
3202
3203         if(CHECKBIT(val64, 0x0))
3204                 stat_info->xpak_stat.warn_laser_output_power_low++;
3205 }
3206
3207 /**
3208  *  alarm_intr_handler - Alarm Interrrupt handler
3209  *  @nic: device private variable
3210  *  Description: If the interrupt was neither because of Rx packet or Tx
3211  *  complete, this function is called. If the interrupt was to indicate
3212  *  a loss of link, the OSM link status handler is invoked for any other
3213  *  alarm interrupt the block that raised the interrupt is displayed
3214  *  and a H/W reset is issued.
3215  *  Return Value:
3216  *  NONE
3217 */
3218
3219 static void alarm_intr_handler(struct s2io_nic *nic)
3220 {
3221         struct net_device *dev = (struct net_device *) nic->dev;
3222         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3223         register u64 val64 = 0, err_reg = 0;
3224         u64 cnt;
3225         int i;
3226         if (atomic_read(&nic->card_state) == CARD_DOWN)
3227                 return;
3228         nic->mac_control.stats_info->sw_stat.ring_full_cnt = 0;
3229         /* Handling the XPAK counters update */
3230         if(nic->mac_control.stats_info->xpak_stat.xpak_timer_count < 72000) {
3231                 /* waiting for an hour */
3232                 nic->mac_control.stats_info->xpak_stat.xpak_timer_count++;
3233         } else {
3234                 s2io_updt_xpak_counter(dev);
3235                 /* reset the count to zero */
3236                 nic->mac_control.stats_info->xpak_stat.xpak_timer_count = 0;
3237         }
3238
3239         /* Handling link status change error Intr */
3240         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
3241                 err_reg = readq(&bar0->mac_rmac_err_reg);
3242                 writeq(err_reg, &bar0->mac_rmac_err_reg);
3243                 if (err_reg & RMAC_LINK_STATE_CHANGE_INT) {
3244                         schedule_work(&nic->set_link_task);
3245                 }
3246         }
3247
3248         /* Handling Ecc errors */
3249         val64 = readq(&bar0->mc_err_reg);
3250         writeq(val64, &bar0->mc_err_reg);
3251         if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
3252                 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
3253                         nic->mac_control.stats_info->sw_stat.
3254                                 double_ecc_errs++;
3255                         DBG_PRINT(INIT_DBG, "%s: Device indicates ",
3256                                   dev->name);
3257                         DBG_PRINT(INIT_DBG, "double ECC error!!\n");
3258                         if (nic->device_type != XFRAME_II_DEVICE) {
3259                                 /* Reset XframeI only if critical error */
3260                                 if (val64 & (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
3261                                              MC_ERR_REG_MIRI_ECC_DB_ERR_1)) {
3262                                         netif_stop_queue(dev);
3263                                         schedule_work(&nic->rst_timer_task);
3264                                         nic->mac_control.stats_info->sw_stat.
3265                                                         soft_reset_cnt++;
3266                                 }
3267                         }
3268                 } else {
3269                         nic->mac_control.stats_info->sw_stat.
3270                                 single_ecc_errs++;
3271                 }
3272         }
3273
3274         /* In case of a serious error, the device will be Reset. */
3275         val64 = readq(&bar0->serr_source);
3276         if (val64 & SERR_SOURCE_ANY) {
3277                 nic->mac_control.stats_info->sw_stat.serious_err_cnt++;
3278                 DBG_PRINT(ERR_DBG, "%s: Device indicates ", dev->name);
3279                 DBG_PRINT(ERR_DBG, "serious error %llx!!\n",
3280                           (unsigned long long)val64);
3281                 netif_stop_queue(dev);
3282                 schedule_work(&nic->rst_timer_task);
3283                 nic->mac_control.stats_info->sw_stat.soft_reset_cnt++;
3284         }
3285
3286         /*
3287          * Also as mentioned in the latest Errata sheets if the PCC_FB_ECC
3288          * Error occurs, the adapter will be recycled by disabling the
3289          * adapter enable bit and enabling it again after the device
3290          * becomes Quiescent.
3291          */
3292         val64 = readq(&bar0->pcc_err_reg);
3293         writeq(val64, &bar0->pcc_err_reg);
3294         if (val64 & PCC_FB_ECC_DB_ERR) {
3295                 u64 ac = readq(&bar0->adapter_control);
3296                 ac &= ~(ADAPTER_CNTL_EN);
3297                 writeq(ac, &bar0->adapter_control);
3298                 ac = readq(&bar0->adapter_control);
3299                 schedule_work(&nic->set_link_task);
3300         }
3301         /* Check for data parity error */
3302         val64 = readq(&bar0->pic_int_status);
3303         if (val64 & PIC_INT_GPIO) {
3304                 val64 = readq(&bar0->gpio_int_reg);
3305                 if (val64 & GPIO_INT_REG_DP_ERR_INT) {
3306                         nic->mac_control.stats_info->sw_stat.parity_err_cnt++;
3307                         schedule_work(&nic->rst_timer_task);
3308                         nic->mac_control.stats_info->sw_stat.soft_reset_cnt++;
3309                 }
3310         }
3311
3312         /* Check for ring full counter */
3313         if (nic->device_type & XFRAME_II_DEVICE) {
3314                 val64 = readq(&bar0->ring_bump_counter1);
3315                 for (i=0; i<4; i++) {
3316                         cnt = ( val64 & vBIT(0xFFFF,(i*16),16));
3317                         cnt >>= 64 - ((i+1)*16);
3318                         nic->mac_control.stats_info->sw_stat.ring_full_cnt
3319                                 += cnt;
3320                 }
3321
3322                 val64 = readq(&bar0->ring_bump_counter2);
3323                 for (i=0; i<4; i++) {
3324                         cnt = ( val64 & vBIT(0xFFFF,(i*16),16));
3325                         cnt >>= 64 - ((i+1)*16);
3326                         nic->mac_control.stats_info->sw_stat.ring_full_cnt
3327                                 += cnt;
3328                 }
3329         }
3330
3331         /* Other type of interrupts are not being handled now,  TODO */
3332 }
3333
3334 /**
3335  *  wait_for_cmd_complete - waits for a command to complete.
3336  *  @sp : private member of the device structure, which is a pointer to the
3337  *  s2io_nic structure.
3338  *  Description: Function that waits for a command to Write into RMAC
3339  *  ADDR DATA registers to be completed and returns either success or
3340  *  error depending on whether the command was complete or not.
3341  *  Return value:
3342  *   SUCCESS on success and FAILURE on failure.
3343  */
3344
3345 static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3346                                 int bit_state)
3347 {
3348         int ret = FAILURE, cnt = 0, delay = 1;
3349         u64 val64;
3350
3351         if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3352                 return FAILURE;
3353
3354         do {
3355                 val64 = readq(addr);
3356                 if (bit_state == S2IO_BIT_RESET) {
3357                         if (!(val64 & busy_bit)) {
3358                                 ret = SUCCESS;
3359                                 break;
3360                         }
3361                 } else {
3362                         if (!(val64 & busy_bit)) {
3363                                 ret = SUCCESS;
3364                                 break;
3365                         }
3366                 }
3367
3368                 if(in_interrupt())
3369                         mdelay(delay);
3370                 else
3371                         msleep(delay);
3372
3373                 if (++cnt >= 10)
3374                         delay = 50;
3375         } while (cnt < 20);
3376         return ret;
3377 }
3378 /*
3379  * check_pci_device_id - Checks if the device id is supported
3380  * @id : device id
3381  * Description: Function to check if the pci device id is supported by driver.
3382  * Return value: Actual device id if supported else PCI_ANY_ID
3383  */
3384 static u16 check_pci_device_id(u16 id)
3385 {
3386         switch (id) {
3387         case PCI_DEVICE_ID_HERC_WIN:
3388         case PCI_DEVICE_ID_HERC_UNI:
3389                 return XFRAME_II_DEVICE;
3390         case PCI_DEVICE_ID_S2IO_UNI:
3391         case PCI_DEVICE_ID_S2IO_WIN:
3392                 return XFRAME_I_DEVICE;
3393         default:
3394                 return PCI_ANY_ID;
3395         }
3396 }
3397
3398 /**
3399  *  s2io_reset - Resets the card.
3400  *  @sp : private member of the device structure.
3401  *  Description: Function to Reset the card. This function then also
3402  *  restores the previously saved PCI configuration space registers as
3403  *  the card reset also resets the configuration space.
3404  *  Return value:
3405  *  void.
3406  */
3407
3408 static void s2io_reset(struct s2io_nic * sp)
3409 {
3410         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3411         u64 val64;
3412         u16 subid, pci_cmd;
3413         int i;
3414         u16 val16;
3415         unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3416         unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3417
3418         DBG_PRINT(INIT_DBG,"%s - Resetting XFrame card %s\n",
3419                         __FUNCTION__, sp->dev->name);
3420
3421         /* Back up  the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3422         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
3423
3424         if (sp->device_type == XFRAME_II_DEVICE) {
3425                 int ret;
3426                 ret = pci_set_power_state(sp->pdev, 3);
3427                 if (!ret)
3428                         ret = pci_set_power_state(sp->pdev, 0);
3429                 else {
3430                         DBG_PRINT(ERR_DBG,"%s PME based SW_Reset failed!\n",
3431                                         __FUNCTION__);
3432                         goto old_way;
3433                 }
3434                 msleep(20);
3435                 goto new_way;
3436         }
3437 old_way:
3438         val64 = SW_RESET_ALL;
3439         writeq(val64, &bar0->sw_reset);
3440 new_way:
3441         if (strstr(sp->product_name, "CX4")) {
3442                 msleep(750);
3443         }
3444         msleep(250);
3445         for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
3446
3447                 /* Restore the PCI state saved during initialization. */
3448                 pci_restore_state(sp->pdev);
3449                 pci_read_config_word(sp->pdev, 0x2, &val16);
3450                 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3451                         break;
3452                 msleep(200);
3453         }
3454
3455         if (check_pci_device_id(val16) == (u16)PCI_ANY_ID) {
3456                 DBG_PRINT(ERR_DBG,"%s SW_Reset failed!\n", __FUNCTION__);
3457         }
3458
3459         pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3460
3461         s2io_init_pci(sp);
3462
3463         /* Set swapper to enable I/O register access */
3464         s2io_set_swapper(sp);
3465
3466         /* Restore the MSIX table entries from local variables */
3467         restore_xmsi_data(sp);
3468
3469         /* Clear certain PCI/PCI-X fields after reset */
3470         if (sp->device_type == XFRAME_II_DEVICE) {
3471                 /* Clear "detected parity error" bit */
3472                 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
3473
3474                 /* Clearing PCIX Ecc status register */
3475                 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
3476
3477                 /* Clearing PCI_STATUS error reflected here */
3478                 writeq(BIT(62), &bar0->txpic_int_reg);
3479         }
3480
3481         /* Reset device statistics maintained by OS */
3482         memset(&sp->stats, 0, sizeof (struct net_device_stats));
3483
3484         up_cnt = sp->mac_control.stats_info->sw_stat.link_up_cnt;
3485         down_cnt = sp->mac_control.stats_info->sw_stat.link_down_cnt;
3486         up_time = sp->mac_control.stats_info->sw_stat.link_up_time;
3487         down_time = sp->mac_control.stats_info->sw_stat.link_down_time;
3488         reset_cnt = sp->mac_control.stats_info->sw_stat.soft_reset_cnt;
3489         mem_alloc_cnt = sp->mac_control.stats_info->sw_stat.mem_allocated;
3490         mem_free_cnt = sp->mac_control.stats_info->sw_stat.mem_freed;
3491         watchdog_cnt = sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt;
3492         /* save link up/down time/cnt, reset/memory/watchdog cnt */
3493         memset(sp->mac_control.stats_info, 0, sizeof(struct stat_block));
3494         /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3495         sp->mac_control.stats_info->sw_stat.link_up_cnt = up_cnt;
3496         sp->mac_control.stats_info->sw_stat.link_down_cnt = down_cnt;
3497         sp->mac_control.stats_info->sw_stat.link_up_time = up_time;
3498         sp->mac_control.stats_info->sw_stat.link_down_time = down_time;
3499         sp->mac_control.stats_info->sw_stat.soft_reset_cnt = reset_cnt;
3500         sp->mac_control.stats_info->sw_stat.mem_allocated = mem_alloc_cnt;
3501         sp->mac_control.stats_info->sw_stat.mem_freed = mem_free_cnt;
3502         sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt = watchdog_cnt;
3503
3504         /* SXE-002: Configure link and activity LED to turn it off */
3505         subid = sp->pdev->subsystem_device;
3506         if (((subid & 0xFF) >= 0x07) &&
3507             (sp->device_type == XFRAME_I_DEVICE)) {
3508                 val64 = readq(&bar0->gpio_control);
3509                 val64 |= 0x0000800000000000ULL;
3510                 writeq(val64, &bar0->gpio_control);
3511                 val64 = 0x0411040400000000ULL;
3512                 writeq(val64, (void __iomem *)bar0 + 0x2700);
3513         }
3514
3515         /*
3516          * Clear spurious ECC interrupts that would have occured on
3517          * XFRAME II cards after reset.
3518          */
3519         if (sp->device_type == XFRAME_II_DEVICE) {
3520                 val64 = readq(&bar0->pcc_err_reg);
3521                 writeq(val64, &bar0->pcc_err_reg);
3522         }
3523
3524         /* restore the previously assigned mac address */
3525         s2io_set_mac_addr(sp->dev, (u8 *)&sp->def_mac_addr[0].mac_addr);
3526
3527         sp->device_enabled_once = FALSE;
3528 }
3529
3530 /**
3531  *  s2io_set_swapper - to set the swapper controle on the card
3532  *  @sp : private member of the device structure,
3533  *  pointer to the s2io_nic structure.
3534  *  Description: Function to set the swapper control on the card
3535  *  correctly depending on the 'endianness' of the system.
3536  *  Return value:
3537  *  SUCCESS on success and FAILURE on failure.
3538  */
3539
3540 static int s2io_set_swapper(struct s2io_nic * sp)
3541 {
3542         struct net_device *dev = sp->dev;
3543         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3544         u64 val64, valt, valr;
3545
3546         /*
3547          * Set proper endian settings and verify the same by reading
3548          * the PIF Feed-back register.
3549          */
3550
3551         val64 = readq(&bar0->pif_rd_swapper_fb);
3552         if (val64 != 0x0123456789ABCDEFULL) {
3553                 int i = 0;
3554                 u64 value[] = { 0xC30000C3C30000C3ULL,   /* FE=1, SE=1 */
3555                                 0x8100008181000081ULL,  /* FE=1, SE=0 */
3556                                 0x4200004242000042ULL,  /* FE=0, SE=1 */
3557                                 0};                     /* FE=0, SE=0 */
3558
3559                 while(i<4) {
3560                         writeq(value[i], &bar0->swapper_ctrl);
3561                         val64 = readq(&bar0->pif_rd_swapper_fb);
3562                         if (val64 == 0x0123456789ABCDEFULL)
3563                                 break;
3564                         i++;
3565                 }
3566                 if (i == 4) {
3567                         DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3568                                 dev->name);
3569                         DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3570                                 (unsigned long long) val64);
3571                         return FAILURE;
3572                 }
3573                 valr = value[i];
3574         } else {
3575                 valr = readq(&bar0->swapper_ctrl);
3576         }
3577
3578         valt = 0x0123456789ABCDEFULL;
3579         writeq(valt, &bar0->xmsi_address);
3580         val64 = readq(&bar0->xmsi_address);
3581
3582         if(val64 != valt) {
3583                 int i = 0;
3584                 u64 value[] = { 0x00C3C30000C3C300ULL,  /* FE=1, SE=1 */
3585                                 0x0081810000818100ULL,  /* FE=1, SE=0 */
3586                                 0x0042420000424200ULL,  /* FE=0, SE=1 */
3587                                 0};                     /* FE=0, SE=0 */
3588
3589                 while(i<4) {
3590                         writeq((value[i] | valr), &bar0->swapper_ctrl);
3591                         writeq(valt, &bar0->xmsi_address);
3592                         val64 = readq(&bar0->xmsi_address);
3593                         if(val64 == valt)
3594                                 break;
3595                         i++;
3596                 }
3597                 if(i == 4) {
3598                         unsigned long long x = val64;
3599                         DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
3600                         DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
3601                         return FAILURE;
3602                 }
3603         }
3604         val64 = readq(&bar0->swapper_ctrl);
3605         val64 &= 0xFFFF000000000000ULL;
3606
3607 #ifdef  __BIG_ENDIAN
3608         /*
3609          * The device by default set to a big endian format, so a
3610          * big endian driver need not set anything.
3611          */
3612         val64 |= (SWAPPER_CTRL_TXP_FE |
3613                  SWAPPER_CTRL_TXP_SE |
3614                  SWAPPER_CTRL_TXD_R_FE |
3615                  SWAPPER_CTRL_TXD_W_FE |
3616                  SWAPPER_CTRL_TXF_R_FE |
3617                  SWAPPER_CTRL_RXD_R_FE |
3618                  SWAPPER_CTRL_RXD_W_FE |
3619                  SWAPPER_CTRL_RXF_W_FE |
3620                  SWAPPER_CTRL_XMSI_FE |
3621                  SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3622         if (sp->intr_type == INTA)
3623                 val64 |= SWAPPER_CTRL_XMSI_SE;
3624         writeq(val64, &bar0->swapper_ctrl);
3625 #else
3626         /*
3627          * Initially we enable all bits to make it accessible by the
3628          * driver, then we selectively enable only those bits that
3629          * we want to set.
3630          */
3631         val64 |= (SWAPPER_CTRL_TXP_FE |
3632                  SWAPPER_CTRL_TXP_SE |
3633                  SWAPPER_CTRL_TXD_R_FE |
3634                  SWAPPER_CTRL_TXD_R_SE |
3635                  SWAPPER_CTRL_TXD_W_FE |
3636                  SWAPPER_CTRL_TXD_W_SE |
3637                  SWAPPER_CTRL_TXF_R_FE |
3638                  SWAPPER_CTRL_RXD_R_FE |
3639                  SWAPPER_CTRL_RXD_R_SE |
3640                  SWAPPER_CTRL_RXD_W_FE |
3641                  SWAPPER_CTRL_RXD_W_SE |
3642                  SWAPPER_CTRL_RXF_W_FE |
3643                  SWAPPER_CTRL_XMSI_FE |
3644                  SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3645         if (sp->intr_type == INTA)
3646                 val64 |= SWAPPER_CTRL_XMSI_SE;
3647         writeq(val64, &bar0->swapper_ctrl);
3648 #endif
3649         val64 = readq(&bar0->swapper_ctrl);
3650
3651         /*
3652          * Verifying if endian settings are accurate by reading a
3653          * feedback register.
3654          */
3655         val64 = readq(&bar0->pif_rd_swapper_fb);
3656         if (val64 != 0x0123456789ABCDEFULL) {
3657                 /* Endian settings are incorrect, calls for another dekko. */
3658                 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3659                           dev->name);
3660                 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3661                           (unsigned long long) val64);
3662                 return FAILURE;
3663         }
3664
3665         return SUCCESS;
3666 }
3667
3668 static int wait_for_msix_trans(struct s2io_nic *nic, int i)
3669 {
3670         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3671         u64 val64;
3672         int ret = 0, cnt = 0;
3673
3674         do {
3675                 val64 = readq(&bar0->xmsi_access);
3676                 if (!(val64 & BIT(15)))
3677                         break;
3678                 mdelay(1);
3679                 cnt++;
3680         } while(cnt < 5);
3681         if (cnt == 5) {
3682                 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3683                 ret = 1;
3684         }
3685
3686         return ret;
3687 }
3688
3689 static void restore_xmsi_data(struct s2io_nic *nic)
3690 {
3691         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3692         u64 val64;
3693         int i;
3694
3695         for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
3696                 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3697                 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3698                 val64 = (BIT(7) | BIT(15) | vBIT(i, 26, 6));
3699                 writeq(val64, &bar0->xmsi_access);
3700                 if (wait_for_msix_trans(nic, i)) {
3701                         DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3702                         continue;
3703                 }
3704         }
3705 }
3706
3707 static void store_xmsi_data(struct s2io_nic *nic)
3708 {
3709         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3710         u64 val64, addr, data;
3711         int i;
3712
3713         /* Store and display */
3714         for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
3715                 val64 = (BIT(15) | vBIT(i, 26, 6));
3716                 writeq(val64, &bar0->xmsi_access);
3717                 if (wait_for_msix_trans(nic, i)) {
3718                         DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3719                         continue;
3720                 }
3721                 addr = readq(&bar0->xmsi_address);
3722                 data = readq(&bar0->xmsi_data);
3723                 if (addr && data) {
3724                         nic->msix_info[i].addr = addr;
3725                         nic->msix_info[i].data = data;
3726                 }
3727         }
3728 }
3729
3730 int s2io_enable_msi(struct s2io_nic *nic)
3731 {
3732         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3733         u16 msi_ctrl, msg_val;
3734         struct config_param *config = &nic->config;
3735         struct net_device *dev = nic->dev;
3736         u64 val64, tx_mat, rx_mat;
3737         int i, err;
3738
3739         val64 = readq(&bar0->pic_control);
3740         val64 &= ~BIT(1);
3741         writeq(val64, &bar0->pic_control);
3742
3743         err = pci_enable_msi(nic->pdev);
3744         if (err) {
3745                 DBG_PRINT(ERR_DBG, "%s: enabling MSI failed\n",
3746                           nic->dev->name);
3747                 return err;
3748         }
3749
3750         /*
3751          * Enable MSI and use MSI-1 in stead of the standard MSI-0
3752          * for interrupt handling.
3753          */
3754         pci_read_config_word(nic->pdev, 0x4c, &msg_val);
3755         msg_val ^= 0x1;
3756         pci_write_config_word(nic->pdev, 0x4c, msg_val);
3757         pci_read_config_word(nic->pdev, 0x4c, &msg_val);
3758
3759         pci_read_config_word(nic->pdev, 0x42, &msi_ctrl);
3760         msi_ctrl |= 0x10;
3761         pci_write_config_word(nic->pdev, 0x42, msi_ctrl);
3762
3763         /* program MSI-1 into all usable Tx_Mat and Rx_Mat fields */
3764         tx_mat = readq(&bar0->tx_mat0_n[0]);
3765         for (i=0; i<config->tx_fifo_num; i++) {
3766                 tx_mat |= TX_MAT_SET(i, 1);
3767         }
3768         writeq(tx_mat, &bar0->tx_mat0_n[0]);
3769
3770         rx_mat = readq(&bar0->rx_mat);
3771         for (i=0; i<config->rx_ring_num; i++) {
3772                 rx_mat |= RX_MAT_SET(i, 1);
3773         }
3774         writeq(rx_mat, &bar0->rx_mat);
3775
3776         dev->irq = nic->pdev->irq;
3777         return 0;
3778 }
3779
3780 static int s2io_enable_msi_x(struct s2io_nic *nic)
3781 {
3782         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3783         u64 tx_mat, rx_mat;
3784         u16 msi_control; /* Temp variable */
3785         int ret, i, j, msix_indx = 1;
3786
3787         nic->entries = kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct msix_entry),
3788                                GFP_KERNEL);
3789         if (nic->entries == NULL) {
3790                 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n", \
3791                         __FUNCTION__);
3792                 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
3793                 return -ENOMEM;
3794         }
3795         nic->mac_control.stats_info->sw_stat.mem_allocated
3796                 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3797         memset(nic->entries, 0,MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3798
3799         nic->s2io_entries =
3800                 kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry),
3801                                    GFP_KERNEL);
3802         if (nic->s2io_entries == NULL) {
3803                 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3804                         __FUNCTION__);
3805                 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
3806                 kfree(nic->entries);
3807                 nic->mac_control.stats_info->sw_stat.mem_freed
3808                         += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3809                 return -ENOMEM;
3810         }
3811          nic->mac_control.stats_info->sw_stat.mem_allocated
3812                 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3813         memset(nic->s2io_entries, 0,
3814                MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3815
3816         for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
3817                 nic->entries[i].entry = i;
3818                 nic->s2io_entries[i].entry = i;
3819                 nic->s2io_entries[i].arg = NULL;
3820                 nic->s2io_entries[i].in_use = 0;
3821         }
3822
3823         tx_mat = readq(&bar0->tx_mat0_n[0]);
3824         for (i=0; i<nic->config.tx_fifo_num; i++, msix_indx++) {
3825                 tx_mat |= TX_MAT_SET(i, msix_indx);
3826                 nic->s2io_entries[msix_indx].arg = &nic->mac_control.fifos[i];
3827                 nic->s2io_entries[msix_indx].type = MSIX_FIFO_TYPE;
3828                 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3829         }
3830         writeq(tx_mat, &bar0->tx_mat0_n[0]);
3831
3832         if (!nic->config.bimodal) {
3833                 rx_mat = readq(&bar0->rx_mat);
3834                 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3835                         rx_mat |= RX_MAT_SET(j, msix_indx);
3836                         nic->s2io_entries[msix_indx].arg
3837                                 = &nic->mac_control.rings[j];
3838                         nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3839                         nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3840                 }
3841                 writeq(rx_mat, &bar0->rx_mat);
3842         } else {
3843                 tx_mat = readq(&bar0->tx_mat0_n[7]);
3844                 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3845                         tx_mat |= TX_MAT_SET(i, msix_indx);
3846                         nic->s2io_entries[msix_indx].arg
3847                                 = &nic->mac_control.rings[j];
3848                         nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3849                         nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3850                 }
3851                 writeq(tx_mat, &bar0->tx_mat0_n[7]);
3852         }
3853
3854         nic->avail_msix_vectors = 0;
3855         ret = pci_enable_msix(nic->pdev, nic->entries, MAX_REQUESTED_MSI_X);
3856         /* We fail init if error or we get less vectors than min required */
3857         if (ret >= (nic->config.tx_fifo_num + nic->config.rx_ring_num + 1)) {
3858                 nic->avail_msix_vectors = ret;
3859                 ret = pci_enable_msix(nic->pdev, nic->entries, ret);
3860         }
3861         if (ret) {
3862                 DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name);
3863                 kfree(nic->entries);
3864                 nic->mac_control.stats_info->sw_stat.mem_freed
3865                         += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3866                 kfree(nic->s2io_entries);
3867                 nic->mac_control.stats_info->sw_stat.mem_freed
3868                 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3869                 nic->entries = NULL;
3870                 nic->s2io_entries = NULL;
3871                 nic->avail_msix_vectors = 0;
3872                 return -ENOMEM;
3873         }
3874         if (!nic->avail_msix_vectors)
3875                 nic->avail_msix_vectors = MAX_REQUESTED_MSI_X;
3876
3877         /*
3878          * To enable MSI-X, MSI also needs to be enabled, due to a bug
3879          * in the herc NIC. (Temp change, needs to be removed later)
3880          */
3881         pci_read_config_word(nic->pdev, 0x42, &msi_control);
3882         msi_control |= 0x1; /* Enable MSI */
3883         pci_write_config_word(nic->pdev, 0x42, msi_control);
3884
3885         return 0;
3886 }
3887
3888 /* ********************************************************* *
3889  * Functions defined below concern the OS part of the driver *
3890  * ********************************************************* */
3891
3892 /**
3893  *  s2io_open - open entry point of the driver
3894  *  @dev : pointer to the device structure.
3895  *  Description:
3896  *  This function is the open entry point of the driver. It mainly calls a
3897  *  function to allocate Rx buffers and inserts them into the buffer
3898  *  descriptors and then enables the Rx part of the NIC.
3899  *  Return value:
3900  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3901  *   file on failure.
3902  */
3903
3904 static int s2io_open(struct net_device *dev)
3905 {
3906         struct s2io_nic *sp = dev->priv;
3907         int err = 0;
3908
3909         /*
3910          * Make sure you have link off by default every time
3911          * Nic is initialized
3912          */
3913         netif_carrier_off(dev);
3914         sp->last_link_state = 0;
3915
3916         /* Initialize H/W and enable interrupts */
3917         err = s2io_card_up(sp);
3918         if (err) {
3919                 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3920                           dev->name);
3921                 goto hw_init_failed;
3922         }
3923
3924         if (s2io_set_mac_addr(dev, dev->dev_addr) == FAILURE) {
3925                 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
3926                 s2io_card_down(sp);
3927                 err = -ENODEV;
3928                 goto hw_init_failed;
3929         }
3930
3931         netif_start_queue(dev);
3932         return 0;
3933
3934 hw_init_failed:
3935         if (sp->intr_type == MSI_X) {
3936                 if (sp->entries) {
3937                         kfree(sp->entries);
3938                         sp->mac_control.stats_info->sw_stat.mem_freed
3939                         += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3940                 }
3941                 if (sp->s2io_entries) {
3942                         kfree(sp->s2io_entries);
3943                         sp->mac_control.stats_info->sw_stat.mem_freed
3944                         += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3945                 }
3946         }
3947         return err;
3948 }
3949
3950 /**
3951  *  s2io_close -close entry point of the driver
3952  *  @dev : device pointer.
3953  *  Description:
3954  *  This is the stop entry point of the driver. It needs to undo exactly
3955  *  whatever was done by the open entry point,thus it's usually referred to
3956  *  as the close function.Among other things this function mainly stops the
3957  *  Rx side of the NIC and frees all the Rx buffers in the Rx rings.
3958  *  Return value:
3959  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3960  *  file on failure.
3961  */
3962
3963 static int s2io_close(struct net_device *dev)
3964 {
3965         struct s2io_nic *sp = dev->priv;
3966
3967         netif_stop_queue(dev);
3968         /* Reset card, kill tasklet and free Tx and Rx buffers. */
3969         s2io_card_down(sp);
3970
3971         sp->device_close_flag = TRUE;   /* Device is shut down. */
3972         return 0;
3973 }
3974
3975 /**
3976  *  s2io_xmit - Tx entry point of te driver
3977  *  @skb : the socket buffer containing the Tx data.
3978  *  @dev : device pointer.
3979  *  Description :
3980  *  This function is the Tx entry point of the driver. S2IO NIC supports
3981  *  certain protocol assist features on Tx side, namely  CSO, S/G, LSO.
3982  *  NOTE: when device cant queue the pkt,just the trans_start variable will
3983  *  not be upadted.
3984  *  Return value:
3985  *  0 on success & 1 on failure.
3986  */
3987
3988 static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
3989 {
3990         struct s2io_nic *sp = dev->priv;
3991         u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
3992         register u64 val64;
3993         struct TxD *txdp;
3994         struct TxFIFO_element __iomem *tx_fifo;
3995         unsigned long flags;
3996         u16 vlan_tag = 0;
3997         int vlan_priority = 0;
3998         struct mac_info *mac_control;
3999         struct config_param *config;
4000         int offload_type;
4001
4002         mac_control = &sp->mac_control;
4003         config = &sp->config;
4004
4005         DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
4006
4007         if (unlikely(skb->len <= 0)) {
4008                 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
4009                 dev_kfree_skb_any(skb);
4010                 return 0;
4011 }
4012
4013         spin_lock_irqsave(&sp->tx_lock, flags);
4014         if (atomic_read(&sp->card_state) == CARD_DOWN) {
4015                 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
4016                           dev->name);
4017                 spin_unlock_irqrestore(&sp->tx_lock, flags);
4018                 dev_kfree_skb(skb);
4019                 return 0;
4020         }
4021
4022         queue = 0;
4023         /* Get Fifo number to Transmit based on vlan priority */
4024         if (sp->vlgrp && vlan_tx_tag_present(skb)) {
4025                 vlan_tag = vlan_tx_tag_get(skb);
4026                 vlan_priority = vlan_tag >> 13;
4027                 queue = config->fifo_mapping[vlan_priority];
4028         }
4029
4030         put_off = (u16) mac_control->fifos[queue].tx_curr_put_info.offset;
4031         get_off = (u16) mac_control->fifos[queue].tx_curr_get_info.offset;
4032         txdp = (struct TxD *) mac_control->fifos[queue].list_info[put_off].
4033                 list_virt_addr;
4034
4035         queue_len = mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
4036         /* Avoid "put" pointer going beyond "get" pointer */
4037         if (txdp->Host_Control ||
4038                    ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4039                 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
4040                 netif_stop_queue(dev);
4041                 dev_kfree_skb(skb);
4042                 spin_unlock_irqrestore(&sp->tx_lock, flags);
4043                 return 0;
4044         }
4045
4046         offload_type = s2io_offload_type(skb);
4047         if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
4048                 txdp->Control_1 |= TXD_TCP_LSO_EN;
4049                 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
4050         }
4051         if (skb->ip_summed == CHECKSUM_PARTIAL) {
4052                 txdp->Control_2 |=
4053                     (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
4054                      TXD_TX_CKO_UDP_EN);
4055         }
4056         txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4057         txdp->Control_1 |= TXD_LIST_OWN_XENA;
4058         txdp->Control_2 |= config->tx_intr_type;
4059
4060         if (sp->vlgrp && vlan_tx_tag_present(skb)) {
4061                 txdp->Control_2 |= TXD_VLAN_ENABLE;
4062                 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4063         }
4064
4065         frg_len = skb->len - skb->data_len;
4066         if (offload_type == SKB_GSO_UDP) {
4067                 int ufo_size;
4068
4069                 ufo_size = s2io_udp_mss(skb);
4070                 ufo_size &= ~7;
4071                 txdp->Control_1 |= TXD_UFO_EN;
4072                 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4073                 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4074 #ifdef __BIG_ENDIAN
4075                 sp->ufo_in_band_v[put_off] =
4076                                 (u64)skb_shinfo(skb)->ip6_frag_id;
4077 #else
4078                 sp->ufo_in_band_v[put_off] =
4079                                 (u64)skb_shinfo(skb)->ip6_frag_id << 32;
4080 #endif
4081                 txdp->Host_Control = (unsigned long)sp->ufo_in_band_v;
4082                 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
4083                                         sp->ufo_in_band_v,
4084                                         sizeof(u64), PCI_DMA_TODEVICE);
4085                 txdp++;
4086         }
4087
4088         txdp->Buffer_Pointer = pci_map_single
4089             (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
4090         txdp->Host_Control = (unsigned long) skb;
4091         txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
4092         if (offload_type == SKB_GSO_UDP)
4093                 txdp->Control_1 |= TXD_UFO_EN;
4094
4095         frg_cnt = skb_shinfo(skb)->nr_frags;
4096         /* For fragmented SKB. */
4097         for (i = 0; i < frg_cnt; i++) {
4098                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4099                 /* A '0' length fragment will be ignored */
4100                 if (!frag->size)
4101                         continue;
4102                 txdp++;
4103                 txdp->Buffer_Pointer = (u64) pci_map_page
4104                     (sp->pdev, frag->page, frag->page_offset,
4105                      frag->size, PCI_DMA_TODEVICE);
4106                 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
4107                 if (offload_type == SKB_GSO_UDP)
4108                         txdp->Control_1 |= TXD_UFO_EN;
4109         }
4110         txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4111
4112         if (offload_type == SKB_GSO_UDP)
4113                 frg_cnt++; /* as Txd0 was used for inband header */
4114
4115         tx_fifo = mac_control->tx_FIFO_start[queue];
4116         val64 = mac_control->fifos[queue].list_info[put_off].list_phy_addr;
4117         writeq(val64, &tx_fifo->TxDL_Pointer);
4118
4119         val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4120                  TX_FIFO_LAST_LIST);
4121         if (offload_type)
4122                 val64 |= TX_FIFO_SPECIAL_FUNC;
4123
4124         writeq(val64, &tx_fifo->List_Control);
4125
4126         mmiowb();
4127
4128         put_off++;
4129         if (put_off == mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1)
4130                 put_off = 0;
4131         mac_control->fifos[queue].tx_curr_put_info.offset = put_off;
4132
4133         /* Avoid "put" pointer going beyond "get" pointer */
4134         if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4135                 sp->mac_control.stats_info->sw_stat.fifo_full_cnt++;
4136                 DBG_PRINT(TX_DBG,
4137                           "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4138                           put_off, get_off);
4139                 netif_stop_queue(dev);
4140         }
4141         mac_control->stats_info->sw_stat.mem_allocated += skb->truesize;
4142         dev->trans_start = jiffies;
4143         spin_unlock_irqrestore(&sp->tx_lock, flags);
4144
4145         return 0;
4146 }
4147
4148 static void
4149 s2io_alarm_handle(unsigned long data)
4150 {
4151         struct s2io_nic *sp = (struct s2io_nic *)data;
4152
4153         alarm_intr_handler(sp);
4154         mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4155 }
4156
4157 static int s2io_chk_rx_buffers(struct s2io_nic *sp, int rng_n)
4158 {
4159         int rxb_size, level;
4160
4161         if (!sp->lro) {
4162                 rxb_size = atomic_read(&sp->rx_bufs_left[rng_n]);
4163                 level = rx_buffer_level(sp, rxb_size, rng_n);
4164
4165                 if ((level == PANIC) && (!TASKLET_IN_USE)) {
4166                         int ret;
4167                         DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", __FUNCTION__);
4168                         DBG_PRINT(INTR_DBG, "PANIC levels\n");
4169                         if ((ret = fill_rx_buffers(sp, rng_n)) == -ENOMEM) {
4170                                 DBG_PRINT(INFO_DBG, "Out of memory in %s",
4171                                           __FUNCTION__);
4172                                 clear_bit(0, (&sp->tasklet_status));
4173                                 return -1;
4174                         }
4175                         clear_bit(0, (&sp->tasklet_status));
4176                 } else if (level == LOW)
4177                         tasklet_schedule(&sp->task);
4178
4179         } else if (fill_rx_buffers(sp, rng_n) == -ENOMEM) {
4180                         DBG_PRINT(INFO_DBG, "%s:Out of memory", sp->dev->name);
4181                         DBG_PRINT(INFO_DBG, " in Rx Intr!!\n");
4182         }
4183         return 0;
4184 }
4185
4186 static irqreturn_t s2io_msi_handle(int irq, void *dev_id)
4187 {
4188         struct net_device *dev = (struct net_device *) dev_id;
4189         struct s2io_nic *sp = dev->priv;
4190         int i;
4191         struct mac_info *mac_control;
4192         struct config_param *config;
4193
4194         atomic_inc(&sp->isr_cnt);
4195         mac_control = &sp->mac_control;
4196         config = &sp->config;
4197         DBG_PRINT(INTR_DBG, "%s: MSI handler\n", __FUNCTION__);
4198
4199         /* If Intr is because of Rx Traffic */
4200         for (i = 0; i < config->rx_ring_num; i++)
4201                 rx_intr_handler(&mac_control->rings[i]);
4202
4203         /* If Intr is because of Tx Traffic */
4204         for (i = 0; i < config->tx_fifo_num; i++)
4205                 tx_intr_handler(&mac_control->fifos[i]);
4206
4207         /*
4208          * If the Rx buffer count is below the panic threshold then
4209          * reallocate the buffers from the interrupt handler itself,
4210          * else schedule a tasklet to reallocate the buffers.
4211          */
4212         for (i = 0; i < config->rx_ring_num; i++)
4213                 s2io_chk_rx_buffers(sp, i);
4214
4215         atomic_dec(&sp->isr_cnt);
4216         return IRQ_HANDLED;
4217 }
4218
4219 static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
4220 {
4221         struct ring_info *ring = (struct ring_info *)dev_id;
4222         struct s2io_nic *sp = ring->nic;
4223
4224         atomic_inc(&sp->isr_cnt);
4225
4226         rx_intr_handler(ring);
4227         s2io_chk_rx_buffers(sp, ring->ring_no);
4228
4229         atomic_dec(&sp->isr_cnt);
4230         return IRQ_HANDLED;
4231 }
4232
4233 static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
4234 {
4235         struct fifo_info *fifo = (struct fifo_info *)dev_id;
4236         struct s2io_nic *sp = fifo->nic;
4237
4238         atomic_inc(&sp->isr_cnt);
4239         tx_intr_handler(fifo);
4240         atomic_dec(&sp->isr_cnt);
4241         return IRQ_HANDLED;
4242 }
4243 static void s2io_txpic_intr_handle(struct s2io_nic *sp)
4244 {
4245         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4246         u64 val64;
4247
4248         val64 = readq(&bar0->pic_int_status);
4249         if (val64 & PIC_INT_GPIO) {
4250                 val64 = readq(&bar0->gpio_int_reg);
4251                 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4252                     (val64 & GPIO_INT_REG_LINK_UP)) {
4253                         /*
4254                          * This is unstable state so clear both up/down
4255                          * interrupt and adapter to re-evaluate the link state.
4256                          */
4257                         val64 |=  GPIO_INT_REG_LINK_DOWN;
4258                         val64 |= GPIO_INT_REG_LINK_UP;
4259                         writeq(val64, &bar0->gpio_int_reg);
4260                         val64 = readq(&bar0->gpio_int_mask);
4261                         val64 &= ~(GPIO_INT_MASK_LINK_UP |
4262                                    GPIO_INT_MASK_LINK_DOWN);
4263                         writeq(val64, &bar0->gpio_int_mask);
4264                 }
4265                 else if (val64 & GPIO_INT_REG_LINK_UP) {
4266                         val64 = readq(&bar0->adapter_status);
4267                                 /* Enable Adapter */
4268                         val64 = readq(&bar0->adapter_control);
4269                         val64 |= ADAPTER_CNTL_EN;
4270                         writeq(val64, &bar0->adapter_control);
4271                         val64 |= ADAPTER_LED_ON;
4272                         writeq(val64, &bar0->adapter_control);
4273                         if (!sp->device_enabled_once)
4274                                 sp->device_enabled_once = 1;
4275
4276                         s2io_link(sp, LINK_UP);
4277                         /*
4278                          * unmask link down interrupt and mask link-up
4279                          * intr
4280                          */
4281                         val64 = readq(&bar0->gpio_int_mask);
4282                         val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4283                         val64 |= GPIO_INT_MASK_LINK_UP;
4284                         writeq(val64, &bar0->gpio_int_mask);
4285
4286                 }else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4287                         val64 = readq(&bar0->adapter_status);
4288                         s2io_link(sp, LINK_DOWN);
4289                         /* Link is down so unmaks link up interrupt */
4290                         val64 = readq(&bar0->gpio_int_mask);
4291                         val64 &= ~GPIO_INT_MASK_LINK_UP;
4292                         val64 |= GPIO_INT_MASK_LINK_DOWN;
4293                         writeq(val64, &bar0->gpio_int_mask);
4294
4295                         /* turn off LED */
4296                         val64 = readq(&bar0->adapter_control);
4297                         val64 = val64 &(~ADAPTER_LED_ON);
4298                         writeq(val64, &bar0->adapter_control);
4299                 }
4300         }
4301         val64 = readq(&bar0->gpio_int_mask);
4302 }
4303
4304 /**
4305  *  s2io_isr - ISR handler of the device .
4306  *  @irq: the irq of the device.
4307  *  @dev_id: a void pointer to the dev structure of the NIC.
4308  *  Description:  This function is the ISR handler of the device. It
4309  *  identifies the reason for the interrupt and calls the relevant
4310  *  service routines. As a contongency measure, this ISR allocates the
4311  *  recv buffers, if their numbers are below the panic value which is
4312  *  presently set to 25% of the original number of rcv buffers allocated.
4313  *  Return value:
4314  *   IRQ_HANDLED: will be returned if IRQ was handled by this routine
4315  *   IRQ_NONE: will be returned if interrupt is not from our device
4316  */
4317 static irqreturn_t s2io_isr(int irq, void *dev_id)
4318 {
4319         struct net_device *dev = (struct net_device *) dev_id;
4320         struct s2io_nic *sp = dev->priv;
4321         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4322         int i;
4323         u64 reason = 0;
4324         struct mac_info *mac_control;
4325         struct config_param *config;
4326
4327         atomic_inc(&sp->isr_cnt);
4328         mac_control = &sp->mac_control;
4329         config = &sp->config;
4330
4331         /*
4332          * Identify the cause for interrupt and call the appropriate
4333          * interrupt handler. Causes for the interrupt could be;
4334          * 1. Rx of packet.
4335          * 2. Tx complete.
4336          * 3. Link down.
4337          * 4. Error in any functional blocks of the NIC.
4338          */
4339         reason = readq(&bar0->general_int_status);
4340
4341         if (!reason) {
4342                 /* The interrupt was not raised by us. */
4343                 atomic_dec(&sp->isr_cnt);
4344                 return IRQ_NONE;
4345         }
4346         else if (unlikely(reason == S2IO_MINUS_ONE) ) {
4347                 /* Disable device and get out */
4348                 atomic_dec(&sp->isr_cnt);
4349                 return IRQ_NONE;
4350         }
4351
4352         if (napi) {
4353                 if (reason & GEN_INTR_RXTRAFFIC) {
4354                         if ( likely ( netif_rx_schedule_prep(dev)) ) {
4355                                 __netif_rx_schedule(dev);
4356                                 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4357                         }
4358                         else
4359                                 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4360                 }
4361         } else {
4362                 /*
4363                  * Rx handler is called by default, without checking for the
4364                  * cause of interrupt.
4365                  * rx_traffic_int reg is an R1 register, writing all 1's
4366                  * will ensure that the actual interrupt causing bit get's
4367                  * cleared and hence a read can be avoided.
4368                  */
4369                 if (reason & GEN_INTR_RXTRAFFIC)
4370                         writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4371
4372                 for (i = 0; i < config->rx_ring_num; i++) {
4373                         rx_intr_handler(&mac_control->rings[i]);
4374                 }
4375         }
4376
4377         /*
4378          * tx_traffic_int reg is an R1 register, writing all 1's
4379          * will ensure that the actual interrupt causing bit get's
4380          * cleared and hence a read can be avoided.
4381          */
4382         if (reason & GEN_INTR_TXTRAFFIC)
4383                 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4384
4385         for (i = 0; i < config->tx_fifo_num; i++)
4386                 tx_intr_handler(&mac_control->fifos[i]);
4387
4388         if (reason & GEN_INTR_TXPIC)
4389                 s2io_txpic_intr_handle(sp);
4390         /*
4391          * If the Rx buffer count is below the panic threshold then
4392          * reallocate the buffers from the interrupt handler itself,
4393          * else schedule a tasklet to reallocate the buffers.
4394          */
4395         if (!napi) {
4396                 for (i = 0; i < config->rx_ring_num; i++)
4397                         s2io_chk_rx_buffers(sp, i);
4398         }
4399
4400         writeq(0, &bar0->general_int_mask);
4401         readl(&bar0->general_int_status);
4402
4403         atomic_dec(&sp->isr_cnt);
4404         return IRQ_HANDLED;
4405 }
4406
4407 /**
4408  * s2io_updt_stats -
4409  */
4410 static void s2io_updt_stats(struct s2io_nic *sp)
4411 {
4412         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4413         u64 val64;
4414         int cnt = 0;
4415
4416         if (atomic_read(&sp->card_state) == CARD_UP) {
4417                 /* Apprx 30us on a 133 MHz bus */
4418                 val64 = SET_UPDT_CLICKS(10) |
4419                         STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4420                 writeq(val64, &bar0->stat_cfg);
4421                 do {
4422                         udelay(100);
4423                         val64 = readq(&bar0->stat_cfg);
4424                         if (!(val64 & BIT(0)))
4425                                 break;
4426                         cnt++;
4427                         if (cnt == 5)
4428                                 break; /* Updt failed */
4429                 } while(1);
4430         }
4431 }
4432
4433 /**
4434  *  s2io_get_stats - Updates the device statistics structure.
4435  *  @dev : pointer to the device structure.
4436  *  Description:
4437  *  This function updates the device statistics structure in the s2io_nic
4438  *  structure and returns a pointer to the same.
4439  *  Return value:
4440  *  pointer to the updated net_device_stats structure.
4441  */
4442
4443 static struct net_device_stats *s2io_get_stats(struct net_device *dev)
4444 {
4445         struct s2io_nic *sp = dev->priv;
4446         struct mac_info *mac_control;
4447         struct config_param *config;
4448
4449
4450         mac_control = &sp->mac_control;
4451         config = &sp->config;
4452
4453         /* Configure Stats for immediate updt */
4454         s2io_updt_stats(sp);
4455
4456         sp->stats.tx_packets =
4457                 le32_to_cpu(mac_control->stats_info->tmac_frms);
4458         sp->stats.tx_errors =
4459                 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
4460         sp->stats.rx_errors =
4461                 le64_to_cpu(mac_control->stats_info->rmac_drop_frms);
4462         sp->stats.multicast =
4463                 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
4464         sp->stats.rx_length_errors =
4465                 le64_to_cpu(mac_control->stats_info->rmac_long_frms);
4466
4467         return (&sp->stats);
4468 }
4469
4470 /**
4471  *  s2io_set_multicast - entry point for multicast address enable/disable.
4472  *  @dev : pointer to the device structure
4473  *  Description:
4474  *  This function is a driver entry point which gets called by the kernel
4475  *  whenever multicast addresses must be enabled/disabled. This also gets
4476  *  called to set/reset promiscuous mode. Depending on the deivce flag, we
4477  *  determine, if multicast address must be enabled or if promiscuous mode
4478  *  is to be disabled etc.
4479  *  Return value:
4480  *  void.
4481  */
4482
4483 static void s2io_set_multicast(struct net_device *dev)
4484 {
4485         int i, j, prev_cnt;
4486         struct dev_mc_list *mclist;
4487         struct s2io_nic *sp = dev->priv;
4488         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4489         u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4490             0xfeffffffffffULL;
4491         u64 dis_addr = 0xffffffffffffULL, mac_addr = 0;
4492         void __iomem *add;
4493
4494         if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4495                 /*  Enable all Multicast addresses */
4496                 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4497                        &bar0->rmac_addr_data0_mem);
4498                 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4499                        &bar0->rmac_addr_data1_mem);
4500                 val64 = RMAC_ADDR_CMD_MEM_WE |
4501                     RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4502                     RMAC_ADDR_CMD_MEM_OFFSET(MAC_MC_ALL_MC_ADDR_OFFSET);
4503                 writeq(val64, &bar0->rmac_addr_cmd_mem);
4504                 /* Wait till command completes */
4505                 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4506                                         RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4507                                         S2IO_BIT_RESET);
4508
4509                 sp->m_cast_flg = 1;
4510                 sp->all_multi_pos = MAC_MC_ALL_MC_ADDR_OFFSET;
4511         } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4512                 /*  Disable all Multicast addresses */
4513                 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4514                        &bar0->rmac_addr_data0_mem);
4515                 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4516                        &bar0->rmac_addr_data1_mem);
4517                 val64 = RMAC_ADDR_CMD_MEM_WE |
4518                     RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4519                     RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4520                 writeq(val64, &bar0->rmac_addr_cmd_mem);
4521                 /* Wait till command completes */
4522                 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4523                                         RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4524                                         S2IO_BIT_RESET);
4525
4526                 sp->m_cast_flg = 0;
4527                 sp->all_multi_pos = 0;
4528         }
4529
4530         if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
4531                 /*  Put the NIC into promiscuous mode */
4532                 add = &bar0->mac_cfg;
4533                 val64 = readq(&bar0->mac_cfg);
4534                 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
4535
4536                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4537                 writel((u32) val64, add);
4538                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4539                 writel((u32) (val64 >> 32), (add + 4));
4540
4541                 if (vlan_tag_strip != 1) {
4542                         val64 = readq(&bar0->rx_pa_cfg);
4543                         val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
4544                         writeq(val64, &bar0->rx_pa_cfg);
4545                         vlan_strip_flag = 0;
4546                 }
4547
4548                 val64 = readq(&bar0->mac_cfg);
4549                 sp->promisc_flg = 1;
4550                 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
4551                           dev->name);
4552         } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
4553                 /*  Remove the NIC from promiscuous mode */
4554                 add = &bar0->mac_cfg;
4555                 val64 = readq(&bar0->mac_cfg);
4556                 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
4557
4558                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4559                 writel((u32) val64, add);
4560                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4561                 writel((u32) (val64 >> 32), (add + 4));
4562
4563                 if (vlan_tag_strip != 0) {
4564                         val64 = readq(&bar0->rx_pa_cfg);
4565                         val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
4566                         writeq(val64, &bar0->rx_pa_cfg);
4567                         vlan_strip_flag = 1;
4568                 }
4569
4570                 val64 = readq(&bar0->mac_cfg);
4571                 sp->promisc_flg = 0;
4572                 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
4573                           dev->name);
4574         }
4575
4576         /*  Update individual M_CAST address list */
4577         if ((!sp->m_cast_flg) && dev->mc_count) {
4578                 if (dev->mc_count >
4579                     (MAX_ADDRS_SUPPORTED - MAC_MC_ADDR_START_OFFSET - 1)) {
4580                         DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
4581                                   dev->name);
4582                         DBG_PRINT(ERR_DBG, "can be added, please enable ");
4583                         DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
4584                         return;
4585                 }
4586
4587                 prev_cnt = sp->mc_addr_count;
4588                 sp->mc_addr_count = dev->mc_count;
4589
4590                 /* Clear out the previous list of Mc in the H/W. */
4591                 for (i = 0; i < prev_cnt; i++) {
4592                         writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4593                                &bar0->rmac_addr_data0_mem);
4594                         writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4595                                 &bar0->rmac_addr_data1_mem);
4596                         val64 = RMAC_ADDR_CMD_MEM_WE |
4597                             RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4598                             RMAC_ADDR_CMD_MEM_OFFSET
4599                             (MAC_MC_ADDR_START_OFFSET + i);
4600                         writeq(val64, &bar0->rmac_addr_cmd_mem);
4601
4602                         /* Wait for command completes */
4603                         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4604                                         RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4605                                         S2IO_BIT_RESET)) {
4606                                 DBG_PRINT(ERR_DBG, "%s: Adding ",
4607                                           dev->name);
4608                                 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4609                                 return;
4610                         }
4611                 }
4612
4613                 /* Create the new Rx filter list and update the same in H/W. */
4614                 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
4615                      i++, mclist = mclist->next) {
4616                         memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
4617                                ETH_ALEN);
4618                         mac_addr = 0;
4619                         for (j = 0; j < ETH_ALEN; j++) {
4620                                 mac_addr |= mclist->dmi_addr[j];
4621                                 mac_addr <<= 8;
4622                         }
4623                         mac_addr >>= 8;
4624                         writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4625                                &bar0->rmac_addr_data0_mem);
4626                         writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4627                                 &bar0->rmac_addr_data1_mem);
4628                         val64 = RMAC_ADDR_CMD_MEM_WE |
4629                             RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4630                             RMAC_ADDR_CMD_MEM_OFFSET
4631                             (i + MAC_MC_ADDR_START_OFFSET);
4632                         writeq(val64, &bar0->rmac_addr_cmd_mem);
4633
4634                         /* Wait for command completes */
4635                         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4636                                         RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4637                                         S2IO_BIT_RESET)) {
4638                                 DBG_PRINT(ERR_DBG, "%s: Adding ",
4639                                           dev->name);
4640                                 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4641                                 return;
4642                         }
4643                 }
4644         }
4645 }
4646
4647 /**
4648  *  s2io_set_mac_addr - Programs the Xframe mac address
4649  *  @dev : pointer to the device structure.
4650  *  @addr: a uchar pointer to the new mac address which is to be set.
4651  *  Description : This procedure will program the Xframe to receive
4652  *  frames with new Mac Address
4653  *  Return value: SUCCESS on success and an appropriate (-)ve integer
4654  *  as defined in errno.h file on failure.
4655  */
4656
4657 static int s2io_set_mac_addr(struct net_device *dev, u8 * addr)
4658 {
4659         struct s2io_nic *sp = dev->priv;
4660         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4661         register u64 val64, mac_addr = 0;
4662         int i;
4663         u64 old_mac_addr = 0;
4664
4665         /*
4666          * Set the new MAC address as the new unicast filter and reflect this
4667          * change on the device address registered with the OS. It will be
4668          * at offset 0.
4669          */
4670         for (i = 0; i < ETH_ALEN; i++) {
4671                 mac_addr <<= 8;
4672                 mac_addr |= addr[i];
4673                 old_mac_addr <<= 8;
4674                 old_mac_addr |= sp->def_mac_addr[0].mac_addr[i];
4675         }
4676
4677         if(0 == mac_addr)
4678                 return SUCCESS;
4679
4680         /* Update the internal structure with this new mac address */
4681         if(mac_addr != old_mac_addr) {
4682                 memset(sp->def_mac_addr[0].mac_addr, 0, sizeof(ETH_ALEN));
4683                 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_addr);
4684                 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_addr >> 8);
4685                 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_addr >> 16);
4686                 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_addr >> 24);
4687                 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_addr >> 32);
4688                 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_addr >> 40);
4689         }
4690
4691         writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4692                &bar0->rmac_addr_data0_mem);
4693
4694         val64 =
4695             RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4696             RMAC_ADDR_CMD_MEM_OFFSET(0);
4697         writeq(val64, &bar0->rmac_addr_cmd_mem);
4698         /* Wait till command completes */
4699         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4700                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, S2IO_BIT_RESET)) {
4701                 DBG_PRINT(ERR_DBG, "%s: set_mac_addr failed\n", dev->name);
4702                 return FAILURE;
4703         }
4704
4705         return SUCCESS;
4706 }
4707
4708 /**
4709  * s2io_ethtool_sset - Sets different link parameters.
4710  * @sp : private member of the device structure, which is a pointer to the  * s2io_nic structure.
4711  * @info: pointer to the structure with parameters given by ethtool to set
4712  * link information.
4713  * Description:
4714  * The function sets different link parameters provided by the user onto
4715  * the NIC.
4716  * Return value:
4717  * 0 on success.
4718 */
4719
4720 static int s2io_ethtool_sset(struct net_device *dev,
4721                              struct ethtool_cmd *info)
4722 {
4723         struct s2io_nic *sp = dev->priv;
4724         if ((info->autoneg == AUTONEG_ENABLE) ||
4725             (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
4726                 return -EINVAL;
4727         else {
4728                 s2io_close(sp->dev);
4729                 s2io_open(sp->dev);
4730         }
4731
4732         return 0;
4733 }
4734
4735 /**
4736  * s2io_ethtol_gset - Return link specific information.
4737  * @sp : private member of the device structure, pointer to the
4738  *      s2io_nic structure.
4739  * @info : pointer to the structure with parameters given by ethtool
4740  * to return link information.
4741  * Description:
4742  * Returns link specific information like speed, duplex etc.. to ethtool.
4743  * Return value :
4744  * return 0 on success.
4745  */
4746
4747 static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
4748 {
4749         struct s2io_nic *sp = dev->priv;
4750         info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4751         info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4752         info->port = PORT_FIBRE;
4753         /* info->transceiver?? TODO */
4754
4755         if (netif_carrier_ok(sp->dev)) {
4756                 info->speed = 10000;
4757                 info->duplex = DUPLEX_FULL;
4758         } else {
4759                 info->speed = -1;
4760                 info->duplex = -1;
4761         }
4762
4763         info->autoneg = AUTONEG_DISABLE;
4764         return 0;
4765 }
4766
4767 /**
4768  * s2io_ethtool_gdrvinfo - Returns driver specific information.
4769  * @sp : private member of the device structure, which is a pointer to the
4770  * s2io_nic structure.
4771  * @info : pointer to the structure with parameters given by ethtool to
4772  * return driver information.
4773  * Description:
4774  * Returns driver specefic information like name, version etc.. to ethtool.
4775  * Return value:
4776  *  void
4777  */
4778
4779 static void s2io_ethtool_gdrvinfo(struct net_device *dev,
4780                                   struct ethtool_drvinfo *info)
4781 {
4782         struct s2io_nic *sp = dev->priv;
4783
4784         strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
4785         strncpy(info->version, s2io_driver_version, sizeof(info->version));
4786         strncpy(info->fw_version, "", sizeof(info->fw_version));
4787         strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
4788         info->regdump_len = XENA_REG_SPACE;
4789         info->eedump_len = XENA_EEPROM_SPACE;
4790         info->testinfo_len = S2IO_TEST_LEN;
4791
4792         if (sp->device_type == XFRAME_I_DEVICE)
4793                 info->n_stats = XFRAME_I_STAT_LEN;
4794         else
4795                 info->n_stats = XFRAME_II_STAT_LEN;
4796 }
4797
4798 /**
4799  *  s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
4800  *  @sp: private member of the device structure, which is a pointer to the
4801  *  s2io_nic structure.
4802  *  @regs : pointer to the structure with parameters given by ethtool for
4803  *  dumping the registers.
4804  *  @reg_space: The input argumnet into which all the registers are dumped.
4805  *  Description:
4806  *  Dumps the entire register space of xFrame NIC into the user given
4807  *  buffer area.
4808  * Return value :
4809  * void .
4810 */
4811
4812 static void s2io_ethtool_gregs(struct net_device *dev,
4813                                struct ethtool_regs *regs, void *space)
4814 {
4815         int i;
4816         u64 reg;
4817         u8 *reg_space = (u8 *) space;
4818         struct s2io_nic *sp = dev->priv;
4819
4820         regs->len = XENA_REG_SPACE;
4821         regs->version = sp->pdev->subsystem_device;
4822
4823         for (i = 0; i < regs->len; i += 8) {
4824                 reg = readq(sp->bar0 + i);
4825                 memcpy((reg_space + i), &reg, 8);
4826         }
4827 }
4828
4829 /**
4830  *  s2io_phy_id  - timer function that alternates adapter LED.
4831  *  @data : address of the private member of the device structure, which
4832  *  is a pointer to the s2io_nic structure, provided as an u32.
4833  * Description: This is actually the timer function that alternates the
4834  * adapter LED bit of the adapter control bit to set/reset every time on
4835  * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
4836  *  once every second.
4837 */
4838 static void s2io_phy_id(unsigned long data)
4839 {
4840         struct s2io_nic *sp = (struct s2io_nic *) data;
4841         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4842         u64 val64 = 0;
4843         u16 subid;
4844
4845         subid = sp->pdev->subsystem_device;
4846         if ((sp->device_type == XFRAME_II_DEVICE) ||
4847                    ((subid & 0xFF) >= 0x07)) {
4848                 val64 = readq(&bar0->gpio_control);
4849                 val64 ^= GPIO_CTRL_GPIO_0;
4850                 writeq(val64, &bar0->gpio_control);
4851         } else {
4852                 val64 = readq(&bar0->adapter_control);
4853                 val64 ^= ADAPTER_LED_ON;
4854                 writeq(val64, &bar0->adapter_control);
4855         }
4856
4857         mod_timer(&sp->id_timer, jiffies + HZ / 2);
4858 }
4859
4860 /**
4861  * s2io_ethtool_idnic - To physically identify the nic on the system.
4862  * @sp : private member of the device structure, which is a pointer to the
4863  * s2io_nic structure.
4864  * @id : pointer to the structure with identification parameters given by
4865  * ethtool.
4866  * Description: Used to physically identify the NIC on the system.
4867  * The Link LED will blink for a time specified by the user for
4868  * identification.
4869  * NOTE: The Link has to be Up to be able to blink the LED. Hence
4870  * identification is possible only if it's link is up.
4871  * Return value:
4872  * int , returns 0 on success
4873  */
4874
4875 static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
4876 {
4877         u64 val64 = 0, last_gpio_ctrl_val;
4878         struct s2io_nic *sp = dev->priv;
4879         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4880         u16 subid;
4881
4882         subid = sp->pdev->subsystem_device;
4883         last_gpio_ctrl_val = readq(&bar0->gpio_control);
4884         if ((sp->device_type == XFRAME_I_DEVICE) &&
4885                 ((subid & 0xFF) < 0x07)) {
4886                 val64 = readq(&bar0->adapter_control);
4887                 if (!(val64 & ADAPTER_CNTL_EN)) {
4888                         printk(KERN_ERR
4889                                "Adapter Link down, cannot blink LED\n");
4890                         return -EFAULT;
4891                 }
4892         }
4893         if (sp->id_timer.function == NULL) {
4894                 init_timer(&sp->id_timer);
4895                 sp->id_timer.function = s2io_phy_id;
4896                 sp->id_timer.data = (unsigned long) sp;
4897         }
4898         mod_timer(&sp->id_timer, jiffies);
4899         if (data)
4900                 msleep_interruptible(data * HZ);
4901         else
4902                 msleep_interruptible(MAX_FLICKER_TIME);
4903         del_timer_sync(&sp->id_timer);
4904
4905         if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
4906                 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
4907                 last_gpio_ctrl_val = readq(&bar0->gpio_control);
4908         }
4909
4910         return 0;
4911 }
4912
4913 static void s2io_ethtool_gringparam(struct net_device *dev,
4914                                     struct ethtool_ringparam *ering)
4915 {
4916         struct s2io_nic *sp = dev->priv;
4917         int i,tx_desc_count=0,rx_desc_count=0;
4918
4919         if (sp->rxd_mode == RXD_MODE_1)
4920                 ering->rx_max_pending = MAX_RX_DESC_1;
4921         else if (sp->rxd_mode == RXD_MODE_3B)
4922                 ering->rx_max_pending = MAX_RX_DESC_2;
4923         else if (sp->rxd_mode == RXD_MODE_3A)
4924                 ering->rx_max_pending = MAX_RX_DESC_3;
4925
4926         ering->tx_max_pending = MAX_TX_DESC;
4927         for (i = 0 ; i < sp->config.tx_fifo_num ; i++) {
4928                 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
4929         }
4930         DBG_PRINT(INFO_DBG,"\nmax txds : %d\n",sp->config.max_txds);
4931         ering->tx_pending = tx_desc_count;
4932         rx_desc_count = 0;
4933         for (i = 0 ; i < sp->config.rx_ring_num ; i++) {
4934                 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
4935         }
4936         ering->rx_pending = rx_desc_count;
4937
4938         ering->rx_mini_max_pending = 0;
4939         ering->rx_mini_pending = 0;
4940         if(sp->rxd_mode == RXD_MODE_1)
4941                 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
4942         else if (sp->rxd_mode == RXD_MODE_3B)
4943                 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
4944         ering->rx_jumbo_pending = rx_desc_count;
4945 }
4946
4947 /**
4948  * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
4949  * @sp : private member of the device structure, which is a pointer to the
4950  *      s2io_nic structure.
4951  * @ep : pointer to the structure with pause parameters given by ethtool.
4952  * Description:
4953  * Returns the Pause frame generation and reception capability of the NIC.
4954  * Return value:
4955  *  void
4956  */
4957 static void s2io_ethtool_getpause_data(struct net_device *dev,
4958                                        struct ethtool_pauseparam *ep)
4959 {
4960         u64 val64;
4961         struct s2io_nic *sp = dev->priv;
4962         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4963
4964         val64 = readq(&bar0->rmac_pause_cfg);
4965         if (val64 & RMAC_PAUSE_GEN_ENABLE)
4966                 ep->tx_pause = TRUE;
4967         if (val64 & RMAC_PAUSE_RX_ENABLE)
4968                 ep->rx_pause = TRUE;
4969         ep->autoneg = FALSE;
4970 }
4971
4972 /**
4973  * s2io_ethtool_setpause_data -  set/reset pause frame generation.
4974  * @sp : private member of the device structure, which is a pointer to the
4975  *      s2io_nic structure.
4976  * @ep : pointer to the structure with pause parameters given by ethtool.
4977  * Description:
4978  * It can be used to set or reset Pause frame generation or reception
4979  * support of the NIC.
4980  * Return value:
4981  * int, returns 0 on Success
4982  */
4983
4984 static int s2io_ethtool_setpause_data(struct net_device *dev,
4985                                struct ethtool_pauseparam *ep)
4986 {
4987         u64 val64;
4988         struct s2io_nic *sp = dev->priv;
4989         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4990
4991         val64 = readq(&bar0->rmac_pause_cfg);
4992         if (ep->tx_pause)
4993                 val64 |= RMAC_PAUSE_GEN_ENABLE;
4994         else
4995                 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
4996         if (ep->rx_pause)
4997                 val64 |= RMAC_PAUSE_RX_ENABLE;
4998         else
4999                 val64 &= ~RMAC_PAUSE_RX_ENABLE;
5000         writeq(val64, &bar0->rmac_pause_cfg);
5001         return 0;
5002 }
5003
5004 /**
5005  * read_eeprom - reads 4 bytes of data from user given offset.
5006  * @sp : private member of the device structure, which is a pointer to the
5007  *      s2io_nic structure.
5008  * @off : offset at which the data must be written
5009  * @data : Its an output parameter where the data read at the given
5010  *      offset is stored.
5011  * Description:
5012  * Will read 4 bytes of data from the user given offset and return the
5013  * read data.
5014  * NOTE: Will allow to read only part of the EEPROM visible through the
5015  *   I2C bus.
5016  * Return value:
5017  *  -1 on failure and 0 on success.
5018  */
5019
5020 #define S2IO_DEV_ID             5
5021 static int read_eeprom(struct s2io_nic * sp, int off, u64 * data)
5022 {
5023         int ret = -1;
5024         u32 exit_cnt = 0;
5025         u64 val64;
5026         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5027
5028         if (sp->device_type == XFRAME_I_DEVICE) {
5029                 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
5030                     I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
5031                     I2C_CONTROL_CNTL_START;
5032                 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5033
5034                 while (exit_cnt < 5) {
5035                         val64 = readq(&bar0->i2c_control);
5036                         if (I2C_CONTROL_CNTL_END(val64)) {
5037                                 *data = I2C_CONTROL_GET_DATA(val64);
5038                                 ret = 0;
5039                                 break;
5040                         }
5041                         msleep(50);
5042                         exit_cnt++;
5043                 }
5044         }
5045
5046         if (sp->device_type == XFRAME_II_DEVICE) {
5047                 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5048                         SPI_CONTROL_BYTECNT(0x3) |
5049                         SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5050                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5051                 val64 |= SPI_CONTROL_REQ;
5052                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5053                 while (exit_cnt < 5) {
5054                         val64 = readq(&bar0->spi_control);
5055                         if (val64 & SPI_CONTROL_NACK) {
5056                                 ret = 1;
5057                                 break;
5058                         } else if (val64 & SPI_CONTROL_DONE) {
5059                                 *data = readq(&bar0->spi_data);
5060                                 *data &= 0xffffff;
5061                                 ret = 0;
5062                                 break;
5063                         }
5064                         msleep(50);
5065                         exit_cnt++;
5066                 }
5067         }
5068         return ret;
5069 }
5070
5071 /**
5072  *  write_eeprom - actually writes the relevant part of the data value.
5073  *  @sp : private member of the device structure, which is a pointer to the
5074  *       s2io_nic structure.
5075  *  @off : offset at which the data must be written
5076  *  @data : The data that is to be written
5077  *  @cnt : Number of bytes of the data that are actually to be written into
5078  *  the Eeprom. (max of 3)
5079  * Description:
5080  *  Actually writes the relevant part of the data value into the Eeprom
5081  *  through the I2C bus.
5082  * Return value:
5083  *  0 on success, -1 on failure.
5084  */
5085
5086 static int write_eeprom(struct s2io_nic * sp, int off, u64 data, int cnt)
5087 {
5088         int exit_cnt = 0, ret = -1;
5089         u64 val64;
5090         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5091
5092         if (sp->device_type == XFRAME_I_DEVICE) {
5093                 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
5094                     I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) |
5095                     I2C_CONTROL_CNTL_START;
5096                 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5097
5098                 while (exit_cnt < 5) {
5099                         val64 = readq(&bar0->i2c_control);
5100                         if (I2C_CONTROL_CNTL_END(val64)) {
5101                                 if (!(val64 & I2C_CONTROL_NACK))
5102                                         ret = 0;
5103                                 break;
5104                         }
5105                         msleep(50);
5106                         exit_cnt++;
5107                 }
5108         }
5109
5110         if (sp->device_type == XFRAME_II_DEVICE) {
5111                 int write_cnt = (cnt == 8) ? 0 : cnt;
5112                 writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);
5113
5114                 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5115                         SPI_CONTROL_BYTECNT(write_cnt) |
5116                         SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5117                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5118                 val64 |= SPI_CONTROL_REQ;
5119                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5120                 while (exit_cnt < 5) {
5121                         val64 = readq(&bar0->spi_control);
5122                         if (val64 & SPI_CONTROL_NACK) {
5123                                 ret = 1;
5124                                 break;
5125                         } else if (val64 & SPI_CONTROL_DONE) {
5126                                 ret = 0;
5127                                 break;
5128                         }
5129                         msleep(50);
5130                         exit_cnt++;
5131                 }
5132         }
5133         return ret;
5134 }
5135 static void s2io_vpd_read(struct s2io_nic *nic)
5136 {
5137         u8 *vpd_data;
5138         u8 data;
5139         int i=0, cnt, fail = 0;
5140         int vpd_addr = 0x80;
5141
5142         if (nic->device_type == XFRAME_II_DEVICE) {
5143                 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5144                 vpd_addr = 0x80;
5145         }
5146         else {
5147                 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5148                 vpd_addr = 0x50;
5149         }
5150         strcpy(nic->serial_num, "NOT AVAILABLE");
5151
5152         vpd_data = kmalloc(256, GFP_KERNEL);
5153         if (!vpd_data) {
5154                 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
5155                 return;
5156         }
5157         nic->mac_control.stats_info->sw_stat.mem_allocated += 256;
5158
5159         for (i = 0; i < 256; i +=4 ) {
5160                 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5161                 pci_read_config_byte(nic->pdev,  (vpd_addr + 2), &data);
5162                 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
5163                 for (cnt = 0; cnt <5; cnt++) {
5164                         msleep(2);
5165                         pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5166                         if (data == 0x80)
5167                                 break;
5168                 }
5169                 if (cnt >= 5) {
5170                         DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5171                         fail = 1;
5172                         break;
5173                 }
5174                 pci_read_config_dword(nic->pdev,  (vpd_addr + 4),
5175                                       (u32 *)&vpd_data[i]);
5176         }
5177
5178         if(!fail) {
5179                 /* read serial number of adapter */
5180                 for (cnt = 0; cnt < 256; cnt++) {
5181                 if ((vpd_data[cnt] == 'S') &&
5182                         (vpd_data[cnt+1] == 'N') &&
5183                         (vpd_data[cnt+2] < VPD_STRING_LEN)) {
5184                                 memset(nic->serial_num, 0, VPD_STRING_LEN);
5185                                 memcpy(nic->serial_num, &vpd_data[cnt + 3],
5186                                         vpd_data[cnt+2]);
5187                                 break;
5188                         }
5189                 }
5190         }
5191
5192         if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
5193                 memset(nic->product_name, 0, vpd_data[1]);
5194                 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
5195         }
5196         kfree(vpd_data);
5197         nic->mac_control.stats_info->sw_stat.mem_freed += 256;
5198 }
5199
5200 /**
5201  *  s2io_ethtool_geeprom  - reads the value stored in the Eeprom.
5202  *  @sp : private member of the device structure, which is a pointer to the *       s2io_nic structure.
5203  *  @eeprom : pointer to the user level structure provided by ethtool,
5204  *  containing all relevant information.
5205  *  @data_buf : user defined value to be written into Eeprom.
5206  *  Description: Reads the values stored in the Eeprom at given offset
5207  *  for a given length. Stores these values int the input argument data
5208  *  buffer 'data_buf' and returns these to the caller (ethtool.)
5209  *  Return value:
5210  *  int  0 on success
5211  */
5212
5213 static int s2io_ethtool_geeprom(struct net_device *dev,
5214                          struct ethtool_eeprom *eeprom, u8 * data_buf)
5215 {
5216         u32 i, valid;
5217         u64 data;
5218         struct s2io_nic *sp = dev->priv;
5219
5220         eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5221
5222         if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5223                 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5224
5225         for (i = 0; i < eeprom->len; i += 4) {
5226                 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5227                         DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5228                         return -EFAULT;
5229                 }
5230                 valid = INV(data);
5231                 memcpy((data_buf + i), &valid, 4);
5232         }
5233         return 0;
5234 }
5235
5236 /**
5237  *  s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5238  *  @sp : private member of the device structure, which is a pointer to the
5239  *  s2io_nic structure.
5240  *  @eeprom : pointer to the user level structure provided by ethtool,
5241  *  containing all relevant information.
5242  *  @data_buf ; user defined value to be written into Eeprom.
5243  *  Description:
5244  *  Tries to write the user provided value in the Eeprom, at the offset
5245  *  given by the user.
5246  *  Return value:
5247  *  0 on success, -EFAULT on failure.
5248  */
5249
5250 static int s2io_ethtool_seeprom(struct net_device *dev,
5251                                 struct ethtool_eeprom *eeprom,
5252                                 u8 * data_buf)
5253 {
5254         int len = eeprom->len, cnt = 0;
5255         u64 valid = 0, data;
5256         struct s2io_nic *sp = dev->priv;
5257
5258         if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5259                 DBG_PRINT(ERR_DBG,
5260                           "ETHTOOL_WRITE_EEPROM Err: Magic value ");
5261                 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
5262                           eeprom->magic);
5263                 return -EFAULT;
5264         }
5265
5266         while (len) {
5267                 data = (u32) data_buf[cnt] & 0x000000FF;
5268                 if (data) {
5269                         valid = (u32) (data << 24);
5270                 } else
5271                         valid = data;
5272
5273                 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5274                         DBG_PRINT(ERR_DBG,
5275                                   "ETHTOOL_WRITE_EEPROM Err: Cannot ");
5276                         DBG_PRINT(ERR_DBG,
5277                                   "write into the specified offset\n");
5278                         return -EFAULT;
5279                 }
5280                 cnt++;
5281                 len--;
5282         }
5283
5284         return 0;
5285 }
5286
5287 /**
5288  * s2io_register_test - reads and writes into all clock domains.
5289  * @sp : private member of the device structure, which is a pointer to the
5290  * s2io_nic structure.
5291  * @data : variable that returns the result of each of the test conducted b
5292  * by the driver.
5293  * Description:
5294  * Read and write into all clock domains. The NIC has 3 clock domains,
5295  * see that registers in all the three regions are accessible.
5296  * Return value:
5297  * 0 on success.
5298  */
5299
5300 static int s2io_register_test(struct s2io_nic * sp, uint64_t * data)
5301 {
5302         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5303         u64 val64 = 0, exp_val;
5304         int fail = 0;
5305
5306         val64 = readq(&bar0->pif_rd_swapper_fb);
5307         if (val64 != 0x123456789abcdefULL) {
5308                 fail = 1;
5309                 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
5310         }
5311
5312         val64 = readq(&bar0->rmac_pause_cfg);
5313         if (val64 != 0xc000ffff00000000ULL) {
5314                 fail = 1;
5315                 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
5316         }
5317
5318         val64 = readq(&bar0->rx_queue_cfg);
5319         if (sp->device_type == XFRAME_II_DEVICE)
5320                 exp_val = 0x0404040404040404ULL;
5321         else
5322                 exp_val = 0x0808080808080808ULL;
5323         if (val64 != exp_val) {
5324                 fail = 1;
5325                 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
5326         }
5327
5328         val64 = readq(&bar0->xgxs_efifo_cfg);
5329         if (val64 != 0x000000001923141EULL) {
5330                 fail = 1;
5331                 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
5332         }
5333
5334         val64 = 0x5A5A5A5A5A5A5A5AULL;
5335         writeq(val64, &bar0->xmsi_data);
5336         val64 = readq(&bar0->xmsi_data);
5337         if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5338                 fail = 1;
5339                 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
5340         }
5341
5342         val64 = 0xA5A5A5A5A5A5A5A5ULL;
5343         writeq(val64, &bar0->xmsi_data);
5344         val64 = readq(&bar0->xmsi_data);
5345         if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5346                 fail = 1;
5347                 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
5348         }
5349
5350         *data = fail;
5351         return fail;
5352 }
5353
5354 /**
5355  * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
5356  * @sp : private member of the device structure, which is a pointer to the
5357  * s2io_nic structure.
5358  * @data:variable that returns the result of each of the test conducted by
5359  * the driver.
5360  * Description:
5361  * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
5362  * register.
5363  * Return value:
5364  * 0 on success.
5365  */
5366
5367 static int s2io_eeprom_test(struct s2io_nic * sp, uint64_t * data)
5368 {
5369         int fail = 0;
5370         u64 ret_data, org_4F0, org_7F0;
5371         u8 saved_4F0 = 0, saved_7F0 = 0;
5372         struct net_device *dev = sp->dev;
5373
5374         /* Test Write Error at offset 0 */
5375         /* Note that SPI interface allows write access to all areas
5376          * of EEPROM. Hence doing all negative testing only for Xframe I.
5377          */
5378         if (sp->device_type == XFRAME_I_DEVICE)
5379                 if (!write_eeprom(sp, 0, 0, 3))
5380                         fail = 1;
5381
5382         /* Save current values at offsets 0x4F0 and 0x7F0 */
5383         if (!read_eeprom(sp, 0x4F0, &org_4F0))
5384                 saved_4F0 = 1;
5385         if (!read_eeprom(sp, 0x7F0, &org_7F0))
5386                 saved_7F0 = 1;
5387
5388         /* Test Write at offset 4f0 */
5389         if (write_eeprom(sp, 0x4F0, 0x012345, 3))
5390                 fail = 1;
5391         if (read_eeprom(sp, 0x4F0, &ret_data))
5392                 fail = 1;
5393
5394         if (ret_data != 0x012345) {
5395                 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
5396                         "Data written %llx Data read %llx\n",
5397                         dev->name, (unsigned long long)0x12345,
5398                         (unsigned long long)ret_data);
5399                 fail = 1;
5400         }
5401
5402         /* Reset the EEPROM data go FFFF */
5403         write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
5404
5405         /* Test Write Request Error at offset 0x7c */
5406         if (sp->device_type == XFRAME_I_DEVICE)
5407                 if (!write_eeprom(sp, 0x07C, 0, 3))
5408                         fail = 1;
5409
5410         /* Test Write Request at offset 0x7f0 */
5411         if (write_eeprom(sp, 0x7F0, 0x012345, 3))
5412                 fail = 1;
5413         if (read_eeprom(sp, 0x7F0, &ret_data))
5414                 fail = 1;
5415
5416         if (ret_data != 0x012345) {
5417                 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
5418                         "Data written %llx Data read %llx\n",
5419                         dev->name, (unsigned long long)0x12345,
5420                         (unsigned long long)ret_data);
5421                 fail = 1;
5422         }
5423
5424         /* Reset the EEPROM data go FFFF */
5425         write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
5426
5427         if (sp->device_type == XFRAME_I_DEVICE) {
5428                 /* Test Write Error at offset 0x80 */
5429                 if (!write_eeprom(sp, 0x080, 0, 3))
5430                         fail = 1;
5431
5432                 /* Test Write Error at offset 0xfc */
5433                 if (!write_eeprom(sp, 0x0FC, 0, 3))
5434                         fail = 1;
5435
5436                 /* Test Write Error at offset 0x100 */
5437                 if (!write_eeprom(sp, 0x100, 0, 3))
5438                         fail = 1;
5439
5440                 /* Test Write Error at offset 4ec */
5441                 if (!write_eeprom(sp, 0x4EC, 0, 3))
5442                         fail = 1;
5443         }
5444
5445         /* Restore values at offsets 0x4F0 and 0x7F0 */
5446         if (saved_4F0)
5447                 write_eeprom(sp, 0x4F0, org_4F0, 3);
5448         if (saved_7F0)
5449                 write_eeprom(sp, 0x7F0, org_7F0, 3);
5450
5451         *data = fail;
5452         return fail;
5453 }
5454
5455 /**
5456  * s2io_bist_test - invokes the MemBist test of the card .
5457  * @sp : private member of the device structure, which is a pointer to the
5458  * s2io_nic structure.
5459  * @data:variable that returns the result of each of the test conducted by
5460  * the driver.
5461  * Description:
5462  * This invokes the MemBist test of the card. We give around
5463  * 2 secs time for the Test to complete. If it's still not complete
5464  * within this peiod, we consider that the test failed.
5465  * Return value:
5466  * 0 on success and -1 on failure.
5467  */
5468
5469 static int s2io_bist_test(struct s2io_nic * sp, uint64_t * data)
5470 {
5471         u8 bist = 0;
5472         int cnt = 0, ret = -1;
5473
5474         pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
5475         bist |= PCI_BIST_START;
5476         pci_write_config_word(sp->pdev, PCI_BIST, bist);
5477
5478         while (cnt < 20) {
5479                 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
5480                 if (!(bist & PCI_BIST_START)) {
5481                         *data = (bist & PCI_BIST_CODE_MASK);
5482                         ret = 0;
5483                         break;
5484                 }
5485                 msleep(100);
5486                 cnt++;
5487         }
5488
5489         return ret;
5490 }
5491
5492 /**
5493  * s2io-link_test - verifies the link state of the nic
5494  * @sp ; private member of the device structure, which is a pointer to the
5495  * s2io_nic structure.
5496  * @data: variable that returns the result of each of the test conducted by
5497  * the driver.
5498  * Description:
5499  * The function verifies the link state of the NIC and updates the input
5500  * argument 'data' appropriately.
5501  * Return value:
5502  * 0 on success.
5503  */
5504
5505 static int s2io_link_test(struct s2io_nic * sp, uint64_t * data)
5506 {
5507         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5508         u64 val64;
5509
5510         val64 = readq(&bar0->adapter_status);
5511         if(!(LINK_IS_UP(val64)))
5512                 *data = 1;
5513         else
5514                 *data = 0;
5515
5516         return *data;
5517 }
5518
5519 /**
5520  * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
5521  * @sp - private member of the device structure, which is a pointer to the
5522  * s2io_nic structure.
5523  * @data - variable that returns the result of each of the test
5524  * conducted by the driver.
5525  * Description:
5526  *  This is one of the offline test that tests the read and write
5527  *  access to the RldRam chip on the NIC.
5528  * Return value:
5529  *  0 on success.
5530  */
5531
5532 static int s2io_rldram_test(struct s2io_nic * sp, uint64_t * data)
5533 {
5534         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5535         u64 val64;
5536         int cnt, iteration = 0, test_fail = 0;
5537
5538         val64 = readq(&bar0->adapter_control);
5539         val64 &= ~ADAPTER_ECC_EN;
5540         writeq(val64, &bar0->adapter_control);
5541
5542         val64 = readq(&bar0->mc_rldram_test_ctrl);
5543         val64 |= MC_RLDRAM_TEST_MODE;
5544         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
5545
5546         val64 = readq(&bar0->mc_rldram_mrs);
5547         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
5548         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
5549
5550         val64 |= MC_RLDRAM_MRS_ENABLE;
5551         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
5552
5553         while (iteration < 2) {
5554                 val64 = 0x55555555aaaa0000ULL;
5555                 if (iteration == 1) {
5556                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
5557                 }
5558                 writeq(val64, &bar0->mc_rldram_test_d0);
5559
5560                 val64 = 0xaaaa5a5555550000ULL;
5561                 if (iteration == 1) {
5562                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
5563                 }
5564                 writeq(val64, &bar0->mc_rldram_test_d1);
5565
5566                 val64 = 0x55aaaaaaaa5a0000ULL;
5567                 if (iteration == 1) {
5568                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
5569                 }
5570                 writeq(val64, &bar0->mc_rldram_test_d2);
5571
5572                 val64 = (u64) (0x0000003ffffe0100ULL);
5573                 writeq(val64, &bar0->mc_rldram_test_add);
5574
5575                 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
5576                         MC_RLDRAM_TEST_GO;
5577                 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
5578
5579                 for (cnt = 0; cnt < 5; cnt++) {
5580                         val64 = readq(&bar0->mc_rldram_test_ctrl);
5581                         if (val64 & MC_RLDRAM_TEST_DONE)
5582                                 break;
5583                         msleep(200);
5584                 }
5585
5586                 if (cnt == 5)
5587                         break;
5588
5589                 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
5590                 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
5591
5592                 for (cnt = 0; cnt < 5; cnt++) {
5593                         val64 = readq(&bar0->mc_rldram_test_ctrl);
5594                         if (val64 & MC_RLDRAM_TEST_DONE)
5595                                 break;
5596                         msleep(500);
5597                 }
5598
5599                 if (cnt == 5)
5600                         break;
5601
5602                 val64 = readq(&bar0->mc_rldram_test_ctrl);
5603                 if (!(val64 & MC_RLDRAM_TEST_PASS))
5604                         test_fail = 1;
5605
5606                 iteration++;
5607         }
5608
5609         *data = test_fail;
5610
5611         /* Bring the adapter out of test mode */
5612         SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
5613
5614         return test_fail;
5615 }
5616
5617 /**
5618  *  s2io_ethtool_test - conducts 6 tsets to determine the health of card.
5619  *  @sp : private member of the device structure, which is a pointer to the
5620  *  s2io_nic structure.
5621  *  @ethtest : pointer to a ethtool command specific structure that will be
5622  *  returned to the user.
5623  *  @data : variable that returns the result of each of the test
5624  * conducted by the driver.
5625  * Description:
5626  *  This function conducts 6 tests ( 4 offline and 2 online) to determine
5627  *  the health of the card.
5628  * Return value:
5629  *  void
5630  */
5631
5632 static void s2io_ethtool_test(struct net_device *dev,
5633                               struct ethtool_test *ethtest,
5634                               uint64_t * data)
5635 {
5636         struct s2io_nic *sp = dev->priv;
5637         int orig_state = netif_running(sp->dev);
5638
5639         if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
5640                 /* Offline Tests. */
5641                 if (orig_state)
5642                         s2io_close(sp->dev);
5643
5644                 if (s2io_register_test(sp, &data[0]))
5645                         ethtest->flags |= ETH_TEST_FL_FAILED;
5646
5647                 s2io_reset(sp);
5648
5649                 if (s2io_rldram_test(sp, &data[3]))
5650                         ethtest->flags |= ETH_TEST_FL_FAILED;
5651
5652                 s2io_reset(sp);
5653
5654                 if (s2io_eeprom_test(sp, &data[1]))
5655                         ethtest->flags |= ETH_TEST_FL_FAILED;
5656
5657                 if (s2io_bist_test(sp, &data[4]))
5658                         ethtest->flags |= ETH_TEST_FL_FAILED;
5659
5660                 if (orig_state)
5661                         s2io_open(sp->dev);
5662
5663                 data[2] = 0;
5664         } else {
5665                 /* Online Tests. */
5666                 if (!orig_state) {
5667                         DBG_PRINT(ERR_DBG,
5668                                   "%s: is not up, cannot run test\n",
5669                                   dev->name);
5670                         data[0] = -1;
5671                         data[1] = -1;
5672                         data[2] = -1;
5673                         data[3] = -1;
5674                         data[4] = -1;
5675                 }
5676
5677                 if (s2io_link_test(sp, &data[2]))
5678                         ethtest->flags |= ETH_TEST_FL_FAILED;
5679
5680                 data[0] = 0;
5681                 data[1] = 0;
5682                 data[3] = 0;
5683                 data[4] = 0;
5684         }
5685 }
5686
5687 static void s2io_get_ethtool_stats(struct net_device *dev,
5688                                    struct ethtool_stats *estats,
5689                                    u64 * tmp_stats)
5690 {
5691         int i = 0;
5692         struct s2io_nic *sp = dev->priv;
5693         struct stat_block *stat_info = sp->mac_control.stats_info;
5694
5695         s2io_updt_stats(sp);
5696         tmp_stats[i++] =
5697                 (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32  |
5698                 le32_to_cpu(stat_info->tmac_frms);
5699         tmp_stats[i++] =
5700                 (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
5701                 le32_to_cpu(stat_info->tmac_data_octets);
5702         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
5703         tmp_stats[i++] =
5704                 (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
5705                 le32_to_cpu(stat_info->tmac_mcst_frms);
5706         tmp_stats[i++] =
5707                 (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
5708                 le32_to_cpu(stat_info->tmac_bcst_frms);
5709         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
5710         tmp_stats[i++] =
5711                 (u64)le32_to_cpu(stat_info->tmac_ttl_octets_oflow) << 32 |
5712                 le32_to_cpu(stat_info->tmac_ttl_octets);
5713         tmp_stats[i++] =
5714                 (u64)le32_to_cpu(stat_info->tmac_ucst_frms_oflow) << 32 |
5715                 le32_to_cpu(stat_info->tmac_ucst_frms);
5716         tmp_stats[i++] =
5717                 (u64)le32_to_cpu(stat_info->tmac_nucst_frms_oflow) << 32 |
5718                 le32_to_cpu(stat_info->tmac_nucst_frms);
5719         tmp_stats[i++] =
5720                 (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
5721                 le32_to_cpu(stat_info->tmac_any_err_frms);
5722         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_ttl_less_fb_octets);
5723         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
5724         tmp_stats[i++] =
5725                 (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
5726                 le32_to_cpu(stat_info->tmac_vld_ip);
5727         tmp_stats[i++] =
5728                 (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
5729                 le32_to_cpu(stat_info->tmac_drop_ip);
5730         tmp_stats[i++] =
5731                 (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
5732                 le32_to_cpu(stat_info->tmac_icmp);
5733         tmp_stats[i++] =
5734                 (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
5735                 le32_to_cpu(stat_info->tmac_rst_tcp);
5736         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
5737         tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
5738                 le32_to_cpu(stat_info->tmac_udp);
5739         tmp_stats[i++] =
5740                 (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
5741                 le32_to_cpu(stat_info->rmac_vld_frms);
5742         tmp_stats[i++] =
5743                 (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
5744                 le32_to_cpu(stat_info->rmac_data_octets);
5745         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
5746         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
5747         tmp_stats[i++] =
5748                 (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
5749                 le32_to_cpu(stat_info->rmac_vld_mcst_frms);
5750         tmp_stats[i++] =
5751                 (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
5752                 le32_to_cpu(stat_info->rmac_vld_bcst_frms);
5753         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
5754         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_out_rng_len_err_frms);
5755         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
5756         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
5757         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_unsup_ctrl_frms);
5758         tmp_stats[i++] =
5759                 (u64)le32_to_cpu(stat_info->rmac_ttl_octets_oflow) << 32 |
5760                 le32_to_cpu(stat_info->rmac_ttl_octets);
5761         tmp_stats[i++] =
5762                 (u64)le32_to_cpu(stat_info->rmac_accepted_ucst_frms_oflow)
5763                 << 32 | le32_to_cpu(stat_info->rmac_accepted_ucst_frms);
5764         tmp_stats[i++] =
5765                 (u64)le32_to_cpu(stat_info->rmac_accepted_nucst_frms_oflow)
5766                  << 32 | le32_to_cpu(stat_info->rmac_accepted_nucst_frms);
5767         tmp_stats[i++] =
5768                 (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
5769                 le32_to_cpu(stat_info->rmac_discarded_frms);
5770         tmp_stats[i++] =
5771                 (u64)le32_to_cpu(stat_info->rmac_drop_events_oflow)
5772                  << 32 | le32_to_cpu(stat_info->rmac_drop_events);
5773         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_less_fb_octets);
5774         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_frms);
5775         tmp_stats[i++] =
5776                 (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
5777                 le32_to_cpu(stat_info->rmac_usized_frms);
5778         tmp_stats[i++] =
5779                 (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
5780                 le32_to_cpu(stat_info->rmac_osized_frms);
5781         tmp_stats[i++] =
5782                 (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
5783                 le32_to_cpu(stat_info->rmac_frag_frms);
5784         tmp_stats[i++] =
5785                 (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
5786                 le32_to_cpu(stat_info->rmac_jabber_frms);
5787         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_64_frms);
5788         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_65_127_frms);
5789         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_128_255_frms);
5790         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_256_511_frms);
5791         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_512_1023_frms);
5792         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1024_1518_frms);
5793         tmp_stats[i++] =
5794                 (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
5795                 le32_to_cpu(stat_info->rmac_ip);
5796         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
5797         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
5798         tmp_stats[i++] =
5799                 (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
5800                 le32_to_cpu(stat_info->rmac_drop_ip);
5801         tmp_stats[i++] =
5802                 (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
5803                 le32_to_cpu(stat_info->rmac_icmp);
5804         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
5805         tmp_stats[i++] =
5806                 (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
5807                 le32_to_cpu(stat_info->rmac_udp);
5808         tmp_stats[i++] =
5809                 (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
5810                 le32_to_cpu(stat_info->rmac_err_drp_udp);
5811         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_err_sym);
5812         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q0);
5813         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q1);
5814         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q2);
5815         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q3);
5816         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q4);
5817         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q5);
5818         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q6);
5819         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q7);
5820         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q0);
5821         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q1);
5822         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q2);
5823         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q3);
5824         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q4);
5825         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q5);
5826         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q6);
5827         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q7);
5828         tmp_stats[i++] =
5829                 (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
5830                 le32_to_cpu(stat_info->rmac_pause_cnt);
5831         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_data_err_cnt);
5832         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_ctrl_err_cnt);
5833         tmp_stats[i++] =
5834                 (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
5835                 le32_to_cpu(stat_info->rmac_accepted_ip);
5836         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
5837         tmp_stats[i++] = le32_to_cpu(stat_info->rd_req_cnt);
5838         tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_cnt);
5839         tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_rtry_cnt);
5840         tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_cnt);
5841         tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_rd_ack_cnt);
5842         tmp_stats[i++] = le32_to_cpu(stat_info->wr_req_cnt);
5843         tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_cnt);
5844         tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_rtry_cnt);
5845         tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_cnt);
5846         tmp_stats[i++] = le32_to_cpu(stat_info->wr_disc_cnt);
5847         tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_wr_ack_cnt);
5848         tmp_stats[i++] = le32_to_cpu(stat_info->txp_wr_cnt);
5849         tmp_stats[i++] = le32_to_cpu(stat_info->txd_rd_cnt);
5850         tmp_stats[i++] = le32_to_cpu(stat_info->txd_wr_cnt);
5851         tmp_stats[i++] = le32_to_cpu(stat_info->rxd_rd_cnt);
5852         tmp_stats[i++] = le32_to_cpu(stat_info->rxd_wr_cnt);
5853         tmp_stats[i++] = le32_to_cpu(stat_info->txf_rd_cnt);
5854         tmp_stats[i++] = le32_to_cpu(stat_info->rxf_wr_cnt);
5855
5856         /* Enhanced statistics exist only for Hercules */
5857         if(sp->device_type == XFRAME_II_DEVICE) {
5858                 tmp_stats[i++] =
5859                                 le64_to_cpu(stat_info->rmac_ttl_1519_4095_frms);
5860                 tmp_stats[i++] =
5861                                 le64_to_cpu(stat_info->rmac_ttl_4096_8191_frms);
5862                 tmp_stats[i++] =
5863                                 le64_to_cpu(stat_info->rmac_ttl_8192_max_frms);
5864                 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_gt_max_frms);
5865                 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_osized_alt_frms);
5866                 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_jabber_alt_frms);
5867                 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_gt_max_alt_frms);
5868                 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_vlan_frms);
5869                 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_len_discard);
5870                 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_fcs_discard);
5871                 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_pf_discard);
5872                 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_da_discard);
5873                 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_red_discard);
5874                 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_rts_discard);
5875                 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_ingm_full_discard);
5876                 tmp_stats[i++] = le32_to_cpu(stat_info->link_fault_cnt);
5877         }
5878
5879         tmp_stats[i++] = 0;
5880         tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
5881         tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
5882         tmp_stats[i++] = stat_info->sw_stat.parity_err_cnt;
5883         tmp_stats[i++] = stat_info->sw_stat.serious_err_cnt;
5884         tmp_stats[i++] = stat_info->sw_stat.soft_reset_cnt;
5885         tmp_stats[i++] = stat_info->sw_stat.fifo_full_cnt;
5886         tmp_stats[i++] = stat_info->sw_stat.ring_full_cnt;
5887         tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_high;
5888         tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_low;
5889         tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_high;
5890         tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_low;
5891         tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_high;
5892         tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_low;
5893         tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_high;
5894         tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_low;
5895         tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_high;
5896         tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_low;
5897         tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_high;
5898         tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_low;
5899         tmp_stats[i++] = stat_info->sw_stat.clubbed_frms_cnt;
5900         tmp_stats[i++] = stat_info->sw_stat.sending_both;
5901         tmp_stats[i++] = stat_info->sw_stat.outof_sequence_pkts;
5902         tmp_stats[i++] = stat_info->sw_stat.flush_max_pkts;
5903         if (stat_info->sw_stat.num_aggregations) {
5904                 u64 tmp = stat_info->sw_stat.sum_avg_pkts_aggregated;
5905                 int count = 0;
5906                 /*
5907                  * Since 64-bit divide does not work on all platforms,
5908                  * do repeated subtraction.
5909                  */
5910                 while (tmp >= stat_info->sw_stat.num_aggregations) {
5911                         tmp -= stat_info->sw_stat.num_aggregations;
5912                         count++;
5913                 }
5914                 tmp_stats[i++] = count;
5915         }
5916         else
5917                 tmp_stats[i++] = 0;
5918         tmp_stats[i++] = stat_info->sw_stat.mem_alloc_fail_cnt;
5919         tmp_stats[i++] = stat_info->sw_stat.watchdog_timer_cnt;
5920         tmp_stats[i++] = stat_info->sw_stat.mem_allocated;
5921         tmp_stats[i++] = stat_info->sw_stat.mem_freed;
5922         tmp_stats[i++] = stat_info->sw_stat.link_up_cnt;
5923         tmp_stats[i++] = stat_info->sw_stat.link_down_cnt;
5924         tmp_stats[i++] = stat_info->sw_stat.link_up_time;
5925         tmp_stats[i++] = stat_info->sw_stat.link_down_time;
5926
5927         tmp_stats[i++] = stat_info->sw_stat.tx_buf_abort_cnt;
5928         tmp_stats[i++] = stat_info->sw_stat.tx_desc_abort_cnt;
5929         tmp_stats[i++] = stat_info->sw_stat.tx_parity_err_cnt;
5930         tmp_stats[i++] = stat_info->sw_stat.tx_link_loss_cnt;
5931         tmp_stats[i++] = stat_info->sw_stat.tx_list_proc_err_cnt;
5932
5933         tmp_stats[i++] = stat_info->sw_stat.rx_parity_err_cnt;
5934         tmp_stats[i++] = stat_info->sw_stat.rx_abort_cnt;
5935         tmp_stats[i++] = stat_info->sw_stat.rx_parity_abort_cnt;
5936         tmp_stats[i++] = stat_info->sw_stat.rx_rda_fail_cnt;
5937         tmp_stats[i++] = stat_info->sw_stat.rx_unkn_prot_cnt;
5938         tmp_stats[i++] = stat_info->sw_stat.rx_fcs_err_cnt;
5939         tmp_stats[i++] = stat_info->sw_stat.rx_buf_size_err_cnt;
5940         tmp_stats[i++] = stat_info->sw_stat.rx_rxd_corrupt_cnt;
5941         tmp_stats[i++] = stat_info->sw_stat.rx_unkn_err_cnt;
5942 }
5943
5944 static int s2io_ethtool_get_regs_len(struct net_device *dev)
5945 {
5946         return (XENA_REG_SPACE);
5947 }
5948
5949
5950 static u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
5951 {
5952         struct s2io_nic *sp = dev->priv;
5953
5954         return (sp->rx_csum);
5955 }
5956
5957 static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
5958 {
5959         struct s2io_nic *sp = dev->priv;
5960
5961         if (data)
5962                 sp->rx_csum = 1;
5963         else
5964                 sp->rx_csum = 0;
5965
5966         return 0;
5967 }
5968
5969 static int s2io_get_eeprom_len(struct net_device *dev)
5970 {
5971         return (XENA_EEPROM_SPACE);
5972 }
5973
5974 static int s2io_ethtool_self_test_count(struct net_device *dev)
5975 {
5976         return (S2IO_TEST_LEN);
5977 }
5978
5979 static void s2io_ethtool_get_strings(struct net_device *dev,
5980                                      u32 stringset, u8 * data)
5981 {
5982         int stat_size = 0;
5983         struct s2io_nic *sp = dev->priv;
5984
5985         switch (stringset) {
5986         case ETH_SS_TEST:
5987                 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
5988                 break;
5989         case ETH_SS_STATS:
5990                 stat_size = sizeof(ethtool_xena_stats_keys);
5991                 memcpy(data, &ethtool_xena_stats_keys,stat_size);
5992                 if(sp->device_type == XFRAME_II_DEVICE) {
5993                         memcpy(data + stat_size,
5994                                 &ethtool_enhanced_stats_keys,
5995                                 sizeof(ethtool_enhanced_stats_keys));
5996                         stat_size += sizeof(ethtool_enhanced_stats_keys);
5997                 }
5998
5999                 memcpy(data + stat_size, &ethtool_driver_stats_keys,
6000                         sizeof(ethtool_driver_stats_keys));
6001         }
6002 }
6003 static int s2io_ethtool_get_stats_count(struct net_device *dev)
6004 {
6005         struct s2io_nic *sp = dev->priv;
6006         int stat_count = 0;
6007         switch(sp->device_type) {
6008         case XFRAME_I_DEVICE:
6009                 stat_count = XFRAME_I_STAT_LEN;
6010         break;
6011
6012         case XFRAME_II_DEVICE:
6013                 stat_count = XFRAME_II_STAT_LEN;
6014         break;
6015         }
6016
6017         return stat_count;
6018 }
6019
6020 static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
6021 {
6022         if (data)
6023                 dev->features |= NETIF_F_IP_CSUM;
6024         else
6025                 dev->features &= ~NETIF_F_IP_CSUM;
6026
6027         return 0;
6028 }
6029
6030 static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
6031 {
6032         return (dev->features & NETIF_F_TSO) != 0;
6033 }
6034 static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
6035 {
6036         if (data)
6037                 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
6038         else
6039                 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
6040
6041         return 0;
6042 }
6043
6044 static const struct ethtool_ops netdev_ethtool_ops = {
6045         .get_settings = s2io_ethtool_gset,
6046         .set_settings = s2io_ethtool_sset,
6047         .get_drvinfo = s2io_ethtool_gdrvinfo,
6048         .get_regs_len = s2io_ethtool_get_regs_len,
6049         .get_regs = s2io_ethtool_gregs,
6050         .get_link = ethtool_op_get_link,
6051         .get_eeprom_len = s2io_get_eeprom_len,
6052         .get_eeprom = s2io_ethtool_geeprom,
6053         .set_eeprom = s2io_ethtool_seeprom,
6054         .get_ringparam = s2io_ethtool_gringparam,
6055         .get_pauseparam = s2io_ethtool_getpause_data,
6056         .set_pauseparam = s2io_ethtool_setpause_data,
6057         .get_rx_csum = s2io_ethtool_get_rx_csum,
6058         .set_rx_csum = s2io_ethtool_set_rx_csum,
6059         .get_tx_csum = ethtool_op_get_tx_csum,
6060         .set_tx_csum = s2io_ethtool_op_set_tx_csum,
6061         .get_sg = ethtool_op_get_sg,
6062         .set_sg = ethtool_op_set_sg,
6063         .get_tso = s2io_ethtool_op_get_tso,
6064         .set_tso = s2io_ethtool_op_set_tso,
6065         .get_ufo = ethtool_op_get_ufo,
6066         .set_ufo = ethtool_op_set_ufo,
6067         .self_test_count = s2io_ethtool_self_test_count,
6068         .self_test = s2io_ethtool_test,
6069         .get_strings = s2io_ethtool_get_strings,
6070         .phys_id = s2io_ethtool_idnic,
6071         .get_stats_count = s2io_ethtool_get_stats_count,
6072         .get_ethtool_stats = s2io_get_ethtool_stats
6073 };
6074
6075 /**
6076  *  s2io_ioctl - Entry point for the Ioctl
6077  *  @dev :  Device pointer.
6078  *  @ifr :  An IOCTL specefic structure, that can contain a pointer to
6079  *  a proprietary structure used to pass information to the driver.
6080  *  @cmd :  This is used to distinguish between the different commands that
6081  *  can be passed to the IOCTL functions.
6082  *  Description:
6083  *  Currently there are no special functionality supported in IOCTL, hence
6084  *  function always return EOPNOTSUPPORTED
6085  */
6086
6087 static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
6088 {
6089         return -EOPNOTSUPP;
6090 }
6091
6092 /**
6093  *  s2io_change_mtu - entry point to change MTU size for the device.
6094  *   @dev : device pointer.
6095  *   @new_mtu : the new MTU size for the device.
6096  *   Description: A driver entry point to change MTU size for the device.
6097  *   Before changing the MTU the device must be stopped.
6098  *  Return value:
6099  *   0 on success and an appropriate (-)ve integer as defined in errno.h
6100  *   file on failure.
6101  */
6102
6103 static int s2io_change_mtu(struct net_device *dev, int new_mtu)
6104 {
6105         struct s2io_nic *sp = dev->priv;
6106
6107         if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
6108                 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
6109                           dev->name);
6110                 return -EPERM;
6111         }
6112
6113         dev->mtu = new_mtu;
6114         if (netif_running(dev)) {
6115                 s2io_card_down(sp);
6116                 netif_stop_queue(dev);
6117                 if (s2io_card_up(sp)) {
6118                         DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6119                                   __FUNCTION__);
6120                 }
6121                 if (netif_queue_stopped(dev))
6122                         netif_wake_queue(dev);
6123         } else { /* Device is down */
6124                 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6125                 u64 val64 = new_mtu;
6126
6127                 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6128         }
6129
6130         return 0;
6131 }
6132
6133 /**
6134  *  s2io_tasklet - Bottom half of the ISR.
6135  *  @dev_adr : address of the device structure in dma_addr_t format.
6136  *  Description:
6137  *  This is the tasklet or the bottom half of the ISR. This is
6138  *  an extension of the ISR which is scheduled by the scheduler to be run
6139  *  when the load on the CPU is low. All low priority tasks of the ISR can
6140  *  be pushed into the tasklet. For now the tasklet is used only to
6141  *  replenish the Rx buffers in the Rx buffer descriptors.
6142  *  Return value:
6143  *  void.
6144  */
6145
6146 static void s2io_tasklet(unsigned long dev_addr)
6147 {
6148         struct net_device *dev = (struct net_device *) dev_addr;
6149         struct s2io_nic *sp = dev->priv;
6150         int i, ret;
6151         struct mac_info *mac_control;
6152         struct config_param *config;
6153
6154         mac_control = &sp->mac_control;
6155         config = &sp->config;
6156
6157         if (!TASKLET_IN_USE) {
6158                 for (i = 0; i < config->rx_ring_num; i++) {
6159                         ret = fill_rx_buffers(sp, i);
6160                         if (ret == -ENOMEM) {
6161                                 DBG_PRINT(INFO_DBG, "%s: Out of ",
6162                                           dev->name);
6163                                 DBG_PRINT(INFO_DBG, "memory in tasklet\n");
6164                                 break;
6165                         } else if (ret == -EFILL) {
6166                                 DBG_PRINT(INFO_DBG,
6167                                           "%s: Rx Ring %d is full\n",
6168                                           dev->name, i);
6169                                 break;
6170                         }
6171                 }
6172                 clear_bit(0, (&sp->tasklet_status));
6173         }
6174 }
6175
6176 /**
6177  * s2io_set_link - Set the LInk status
6178  * @data: long pointer to device private structue
6179  * Description: Sets the link status for the adapter
6180  */
6181
6182 static void s2io_set_link(struct work_struct *work)
6183 {
6184         struct s2io_nic *nic = container_of(work, struct s2io_nic, set_link_task);
6185         struct net_device *dev = nic->dev;
6186         struct XENA_dev_config __iomem *bar0 = nic->bar0;
6187         register u64 val64;
6188         u16 subid;
6189
6190         rtnl_lock();
6191
6192         if (!netif_running(dev))
6193                 goto out_unlock;
6194
6195         if (test_and_set_bit(0, &(nic->link_state))) {
6196                 /* The card is being reset, no point doing anything */
6197                 goto out_unlock;
6198         }
6199
6200         subid = nic->pdev->subsystem_device;
6201         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6202                 /*
6203                  * Allow a small delay for the NICs self initiated
6204                  * cleanup to complete.
6205                  */
6206                 msleep(100);
6207         }
6208
6209         val64 = readq(&bar0->adapter_status);
6210         if (LINK_IS_UP(val64)) {
6211                 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6212                         if (verify_xena_quiescence(nic)) {
6213                                 val64 = readq(&bar0->adapter_control);
6214                                 val64 |= ADAPTER_CNTL_EN;
6215                                 writeq(val64, &bar0->adapter_control);
6216                                 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6217                                         nic->device_type, subid)) {
6218                                         val64 = readq(&bar0->gpio_control);
6219                                         val64 |= GPIO_CTRL_GPIO_0;
6220                                         writeq(val64, &bar0->gpio_control);
6221                                         val64 = readq(&bar0->gpio_control);
6222                                 } else {
6223                                         val64 |= ADAPTER_LED_ON;
6224                                         writeq(val64, &bar0->adapter_control);
6225                                 }
6226                                 nic->device_enabled_once = TRUE;
6227                         } else {
6228                                 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
6229                                 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
6230                                 netif_stop_queue(dev);
6231                         }
6232                 }
6233                 val64 = readq(&bar0->adapter_status);
6234                 if (!LINK_IS_UP(val64)) {
6235                         DBG_PRINT(ERR_DBG, "%s:", dev->name);
6236                         DBG_PRINT(ERR_DBG, " Link down after enabling ");
6237                         DBG_PRINT(ERR_DBG, "device \n");
6238                 } else
6239                         s2io_link(nic, LINK_UP);
6240         } else {
6241                 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6242                                                       subid)) {
6243                         val64 = readq(&bar0->gpio_control);
6244                         val64 &= ~GPIO_CTRL_GPIO_0;
6245                         writeq(val64, &bar0->gpio_control);
6246                         val64 = readq(&bar0->gpio_control);
6247                 }
6248                 s2io_link(nic, LINK_DOWN);
6249         }
6250         clear_bit(0, &(nic->link_state));
6251
6252 out_unlock:
6253         rtnl_unlock();
6254 }
6255
6256 static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
6257                                 struct buffAdd *ba,
6258                                 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6259                                 u64 *temp2, int size)
6260 {
6261         struct net_device *dev = sp->dev;
6262         struct sk_buff *frag_list;
6263
6264         if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6265                 /* allocate skb */
6266                 if (*skb) {
6267                         DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6268                         /*
6269                          * As Rx frame are not going to be processed,
6270                          * using same mapped address for the Rxd
6271                          * buffer pointer
6272                          */
6273                         ((struct RxD1*)rxdp)->Buffer0_ptr = *temp0;
6274                 } else {
6275                         *skb = dev_alloc_skb(size);
6276                         if (!(*skb)) {
6277                                 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
6278                                 DBG_PRINT(INFO_DBG, "memory to allocate ");
6279                                 DBG_PRINT(INFO_DBG, "1 buf mode SKBs\n");
6280                                 sp->mac_control.stats_info->sw_stat. \
6281                                         mem_alloc_fail_cnt++;
6282                                 return -ENOMEM ;
6283                         }
6284                         sp->mac_control.stats_info->sw_stat.mem_allocated
6285                                 += (*skb)->truesize;
6286                         /* storing the mapped addr in a temp variable
6287                          * such it will be used for next rxd whose
6288                          * Host Control is NULL
6289                          */
6290                         ((struct RxD1*)rxdp)->Buffer0_ptr = *temp0 =
6291                                 pci_map_single( sp->pdev, (*skb)->data,
6292                                         size - NET_IP_ALIGN,
6293                                         PCI_DMA_FROMDEVICE);
6294                         rxdp->Host_Control = (unsigned long) (*skb);
6295                 }
6296         } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6297                 /* Two buffer Mode */
6298                 if (*skb) {
6299                         ((struct RxD3*)rxdp)->Buffer2_ptr = *temp2;
6300                         ((struct RxD3*)rxdp)->Buffer0_ptr = *temp0;
6301                         ((struct RxD3*)rxdp)->Buffer1_ptr = *temp1;
6302                 } else {
6303                         *skb = dev_alloc_skb(size);
6304                         if (!(*skb)) {
6305                                 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
6306                                 DBG_PRINT(INFO_DBG, "memory to allocate ");
6307                                 DBG_PRINT(INFO_DBG, "2 buf mode SKBs\n");
6308                                 sp->mac_control.stats_info->sw_stat. \
6309                                         mem_alloc_fail_cnt++;
6310                                 return -ENOMEM;
6311                         }
6312                         sp->mac_control.stats_info->sw_stat.mem_allocated
6313                                 += (*skb)->truesize;
6314                         ((struct RxD3*)rxdp)->Buffer2_ptr = *temp2 =
6315                                 pci_map_single(sp->pdev, (*skb)->data,
6316                                                dev->mtu + 4,
6317                                                PCI_DMA_FROMDEVICE);
6318                         ((struct RxD3*)rxdp)->Buffer0_ptr = *temp0 =
6319                                 pci_map_single( sp->pdev, ba->ba_0, BUF0_LEN,
6320                                                 PCI_DMA_FROMDEVICE);
6321                         rxdp->Host_Control = (unsigned long) (*skb);
6322
6323                         /* Buffer-1 will be dummy buffer not used */
6324                         ((struct RxD3*)rxdp)->Buffer1_ptr = *temp1 =
6325                                 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
6326                                                PCI_DMA_FROMDEVICE);
6327                 }
6328         } else if ((rxdp->Host_Control == 0)) {
6329                 /* Three buffer mode */
6330                 if (*skb) {
6331                         ((struct RxD3*)rxdp)->Buffer0_ptr = *temp0;
6332                         ((struct RxD3*)rxdp)->Buffer1_ptr = *temp1;
6333                         ((struct RxD3*)rxdp)->Buffer2_ptr = *temp2;
6334                 } else {
6335                         *skb = dev_alloc_skb(size);
6336                         if (!(*skb)) {
6337                                 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
6338                                 DBG_PRINT(INFO_DBG, "memory to allocate ");
6339                                 DBG_PRINT(INFO_DBG, "3 buf mode SKBs\n");
6340                                 sp->mac_control.stats_info->sw_stat. \
6341                                         mem_alloc_fail_cnt++;
6342                                 return -ENOMEM;
6343                         }
6344                         sp->mac_control.stats_info->sw_stat.mem_allocated
6345                                 += (*skb)->truesize;
6346                         ((struct RxD3*)rxdp)->Buffer0_ptr = *temp0 =
6347                                 pci_map_single(sp->pdev, ba->ba_0, BUF0_LEN,
6348                                                PCI_DMA_FROMDEVICE);
6349                         /* Buffer-1 receives L3/L4 headers */
6350                         ((struct RxD3*)rxdp)->Buffer1_ptr = *temp1 =
6351                                 pci_map_single( sp->pdev, (*skb)->data,
6352                                                 l3l4hdr_size + 4,
6353                                                 PCI_DMA_FROMDEVICE);
6354                         /*
6355                          * skb_shinfo(skb)->frag_list will have L4
6356                          * data payload
6357                          */
6358                         skb_shinfo(*skb)->frag_list = dev_alloc_skb(dev->mtu +
6359                                                                    ALIGN_SIZE);
6360                         if (skb_shinfo(*skb)->frag_list == NULL) {
6361                                 DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb \
6362                                           failed\n ", dev->name);
6363                                 sp->mac_control.stats_info->sw_stat. \
6364                                         mem_alloc_fail_cnt++;
6365                                 return -ENOMEM ;
6366                         }
6367                         frag_list = skb_shinfo(*skb)->frag_list;
6368                         frag_list->next = NULL;
6369                         sp->mac_control.stats_info->sw_stat.mem_allocated
6370                                 += frag_list->truesize;
6371                         /*
6372                          * Buffer-2 receives L4 data payload
6373                          */
6374                         ((struct RxD3*)rxdp)->Buffer2_ptr = *temp2 =
6375                                 pci_map_single( sp->pdev, frag_list->data,
6376                                                 dev->mtu, PCI_DMA_FROMDEVICE);
6377                 }
6378         }
6379         return 0;
6380 }
6381 static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6382                                 int size)
6383 {
6384         struct net_device *dev = sp->dev;
6385         if (sp->rxd_mode == RXD_MODE_1) {
6386                 rxdp->Control_2 = SET_BUFFER0_SIZE_1( size - NET_IP_ALIGN);
6387         } else if (sp->rxd_mode == RXD_MODE_3B) {
6388                 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6389                 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
6390                 rxdp->Control_2 |= SET_BUFFER2_SIZE_3( dev->mtu + 4);
6391         } else {
6392                 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6393                 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(l3l4hdr_size + 4);
6394                 rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu);
6395         }
6396 }
6397
6398 static  int rxd_owner_bit_reset(struct s2io_nic *sp)
6399 {
6400         int i, j, k, blk_cnt = 0, size;
6401         struct mac_info * mac_control = &sp->mac_control;
6402         struct config_param *config = &sp->config;
6403         struct net_device *dev = sp->dev;
6404         struct RxD_t *rxdp = NULL;
6405         struct sk_buff *skb = NULL;
6406         struct buffAdd *ba = NULL;
6407         u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6408
6409         /* Calculate the size based on ring mode */
6410         size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6411                 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6412         if (sp->rxd_mode == RXD_MODE_1)
6413                 size += NET_IP_ALIGN;
6414         else if (sp->rxd_mode == RXD_MODE_3B)
6415                 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
6416         else
6417                 size = l3l4hdr_size + ALIGN_SIZE + BUF0_LEN + 4;
6418
6419         for (i = 0; i < config->rx_ring_num; i++) {
6420                 blk_cnt = config->rx_cfg[i].num_rxd /
6421                         (rxd_count[sp->rxd_mode] +1);
6422
6423                 for (j = 0; j < blk_cnt; j++) {
6424                         for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
6425                                 rxdp = mac_control->rings[i].
6426                                         rx_blocks[j].rxds[k].virt_addr;
6427                                 if(sp->rxd_mode >= RXD_MODE_3A)
6428                                         ba = &mac_control->rings[i].ba[j][k];
6429                                 if (set_rxd_buffer_pointer(sp, rxdp, ba,
6430                                                        &skb,(u64 *)&temp0_64,
6431                                                        (u64 *)&temp1_64,
6432                                                        (u64 *)&temp2_64,
6433                                                         size) == ENOMEM) {
6434                                         return 0;
6435                                 }
6436
6437                                 set_rxd_buffer_size(sp, rxdp, size);
6438                                 wmb();
6439                                 /* flip the Ownership bit to Hardware */
6440                                 rxdp->Control_1 |= RXD_OWN_XENA;
6441                         }
6442                 }
6443         }
6444         return 0;
6445
6446 }
6447
6448 static int s2io_add_isr(struct s2io_nic * sp)
6449 {
6450         int ret = 0;
6451         struct net_device *dev = sp->dev;
6452         int err = 0;
6453
6454         if (sp->intr_type == MSI)
6455                 ret = s2io_enable_msi(sp);
6456         else if (sp->intr_type == MSI_X)
6457                 ret = s2io_enable_msi_x(sp);
6458         if (ret) {
6459                 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
6460                 sp->intr_type = INTA;
6461         }
6462
6463         /* Store the values of the MSIX table in the struct s2io_nic structure */
6464         store_xmsi_data(sp);
6465
6466         /* After proper initialization of H/W, register ISR */
6467         if (sp->intr_type == MSI) {
6468                 err = request_irq((int) sp->pdev->irq, s2io_msi_handle,
6469                         IRQF_SHARED, sp->name, dev);
6470                 if (err) {
6471                         pci_disable_msi(sp->pdev);
6472                         DBG_PRINT(ERR_DBG, "%s: MSI registration failed\n",
6473                                   dev->name);
6474                         return -1;
6475                 }
6476         }
6477         if (sp->intr_type == MSI_X) {
6478                 int i, msix_tx_cnt=0,msix_rx_cnt=0;
6479
6480                 for (i=1; (sp->s2io_entries[i].in_use == MSIX_FLG); i++) {
6481                         if (sp->s2io_entries[i].type == MSIX_FIFO_TYPE) {
6482                                 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
6483                                         dev->name, i);
6484                                 err = request_irq(sp->entries[i].vector,
6485                                           s2io_msix_fifo_handle, 0, sp->desc[i],
6486                                                   sp->s2io_entries[i].arg);
6487                                 /* If either data or addr is zero print it */
6488                                 if(!(sp->msix_info[i].addr &&
6489                                         sp->msix_info[i].data)) {
6490                                         DBG_PRINT(ERR_DBG, "%s @ Addr:0x%llx"
6491                                                 "Data:0x%lx\n",sp->desc[i],
6492                                                 (unsigned long long)
6493                                                 sp->msix_info[i].addr,
6494                                                 (unsigned long)
6495                                                 ntohl(sp->msix_info[i].data));
6496                                 } else {
6497                                         msix_tx_cnt++;
6498                                 }
6499                         } else {
6500                                 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
6501                                         dev->name, i);
6502                                 err = request_irq(sp->entries[i].vector,
6503                                           s2io_msix_ring_handle, 0, sp->desc[i],
6504                                                   sp->s2io_entries[i].arg);
6505                                 /* If either data or addr is zero print it */
6506                                 if(!(sp->msix_info[i].addr &&
6507                                         sp->msix_info[i].data)) {
6508                                         DBG_PRINT(ERR_DBG, "%s @ Addr:0x%llx"
6509                                                 "Data:0x%lx\n",sp->desc[i],
6510                                                 (unsigned long long)
6511                                                 sp->msix_info[i].addr,
6512                                                 (unsigned long)
6513                                                 ntohl(sp->msix_info[i].data));
6514                                 } else {
6515                                         msix_rx_cnt++;
6516                                 }
6517                         }
6518                         if (err) {
6519                                 DBG_PRINT(ERR_DBG,"%s:MSI-X-%d registration "
6520                                           "failed\n", dev->name, i);
6521                                 DBG_PRINT(ERR_DBG, "Returned: %d\n", err);
6522                                 return -1;
6523                         }
6524                         sp->s2io_entries[i].in_use = MSIX_REGISTERED_SUCCESS;
6525                 }
6526                 printk("MSI-X-TX %d entries enabled\n",msix_tx_cnt);
6527                 printk("MSI-X-RX %d entries enabled\n",msix_rx_cnt);
6528         }
6529         if (sp->intr_type == INTA) {
6530                 err = request_irq((int) sp->pdev->irq, s2io_isr, IRQF_SHARED,
6531                                 sp->name, dev);
6532                 if (err) {
6533                         DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
6534                                   dev->name);
6535                         return -1;
6536                 }
6537         }
6538         return 0;
6539 }
6540 static void s2io_rem_isr(struct s2io_nic * sp)
6541 {
6542         int cnt = 0;
6543         struct net_device *dev = sp->dev;
6544
6545         if (sp->intr_type == MSI_X) {
6546                 int i;
6547                 u16 msi_control;
6548
6549                 for (i=1; (sp->s2io_entries[i].in_use ==
6550                         MSIX_REGISTERED_SUCCESS); i++) {
6551                         int vector = sp->entries[i].vector;
6552                         void *arg = sp->s2io_entries[i].arg;
6553
6554                         free_irq(vector, arg);
6555                 }
6556                 pci_read_config_word(sp->pdev, 0x42, &msi_control);
6557                 msi_control &= 0xFFFE; /* Disable MSI */
6558                 pci_write_config_word(sp->pdev, 0x42, msi_control);
6559
6560                 pci_disable_msix(sp->pdev);
6561         } else {
6562                 free_irq(sp->pdev->irq, dev);
6563                 if (sp->intr_type == MSI) {
6564                         u16 val;
6565
6566                         pci_disable_msi(sp->pdev);
6567                         pci_read_config_word(sp->pdev, 0x4c, &val);
6568                         val ^= 0x1;
6569                         pci_write_config_word(sp->pdev, 0x4c, val);
6570                 }
6571         }
6572         /* Waiting till all Interrupt handlers are complete */
6573         cnt = 0;
6574         do {
6575                 msleep(10);
6576                 if (!atomic_read(&sp->isr_cnt))
6577                         break;
6578                 cnt++;
6579         } while(cnt < 5);
6580 }
6581
6582 static void s2io_card_down(struct s2io_nic * sp)
6583 {
6584         int cnt = 0;
6585         struct XENA_dev_config __iomem *bar0 = sp->bar0;
6586         unsigned long flags;
6587         register u64 val64 = 0;
6588
6589         del_timer_sync(&sp->alarm_timer);
6590         /* If s2io_set_link task is executing, wait till it completes. */
6591         while (test_and_set_bit(0, &(sp->link_state))) {
6592                 msleep(50);
6593         }
6594         atomic_set(&sp->card_state, CARD_DOWN);
6595
6596         /* disable Tx and Rx traffic on the NIC */
6597         stop_nic(sp);
6598
6599         s2io_rem_isr(sp);
6600
6601         /* Kill tasklet. */
6602         tasklet_kill(&sp->task);
6603
6604         /* Check if the device is Quiescent and then Reset the NIC */
6605         do {
6606                 /* As per the HW requirement we need to replenish the
6607                  * receive buffer to avoid the ring bump. Since there is
6608                  * no intention of processing the Rx frame at this pointwe are
6609                  * just settting the ownership bit of rxd in Each Rx
6610                  * ring to HW and set the appropriate buffer size
6611                  * based on the ring mode
6612                  */
6613                 rxd_owner_bit_reset(sp);
6614
6615                 val64 = readq(&bar0->adapter_status);
6616                 if (verify_xena_quiescence(sp)) {
6617                         if(verify_pcc_quiescent(sp, sp->device_enabled_once))
6618                         break;
6619                 }
6620
6621                 msleep(50);
6622                 cnt++;
6623                 if (cnt == 10) {
6624                         DBG_PRINT(ERR_DBG,
6625                                   "s2io_close:Device not Quiescent ");
6626                         DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
6627                                   (unsigned long long) val64);
6628                         break;
6629                 }
6630         } while (1);
6631         s2io_reset(sp);
6632
6633         spin_lock_irqsave(&sp->tx_lock, flags);
6634         /* Free all Tx buffers */
6635         free_tx_buffers(sp);
6636         spin_unlock_irqrestore(&sp->tx_lock, flags);
6637
6638         /* Free all Rx buffers */
6639         spin_lock_irqsave(&sp->rx_lock, flags);
6640         free_rx_buffers(sp);
6641         spin_unlock_irqrestore(&sp->rx_lock, flags);
6642
6643         clear_bit(0, &(sp->link_state));
6644 }
6645
6646 static int s2io_card_up(struct s2io_nic * sp)
6647 {
6648         int i, ret = 0;
6649         struct mac_info *mac_control;
6650         struct config_param *config;
6651         struct net_device *dev = (struct net_device *) sp->dev;
6652         u16 interruptible;
6653
6654         /* Initialize the H/W I/O registers */
6655         if (init_nic(sp) != 0) {
6656                 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
6657                           dev->name);
6658                 s2io_reset(sp);
6659                 return -ENODEV;
6660         }
6661
6662         /*
6663          * Initializing the Rx buffers. For now we are considering only 1
6664          * Rx ring and initializing buffers into 30 Rx blocks
6665          */
6666         mac_control = &sp->mac_control;
6667         config = &sp->config;
6668
6669         for (i = 0; i < config->rx_ring_num; i++) {
6670                 if ((ret = fill_rx_buffers(sp, i))) {
6671                         DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
6672                                   dev->name);
6673                         s2io_reset(sp);
6674                         free_rx_buffers(sp);
6675                         return -ENOMEM;
6676                 }
6677                 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
6678                           atomic_read(&sp->rx_bufs_left[i]));
6679         }
6680         /* Maintain the state prior to the open */
6681         if (sp->promisc_flg)
6682                 sp->promisc_flg = 0;
6683         if (sp->m_cast_flg) {
6684                 sp->m_cast_flg = 0;
6685                 sp->all_multi_pos= 0;
6686         }
6687
6688         /* Setting its receive mode */
6689         s2io_set_multicast(dev);
6690
6691         if (sp->lro) {
6692                 /* Initialize max aggregatable pkts per session based on MTU */
6693                 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
6694                 /* Check if we can use(if specified) user provided value */
6695                 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
6696                         sp->lro_max_aggr_per_sess = lro_max_pkts;
6697         }
6698
6699         /* Enable Rx Traffic and interrupts on the NIC */
6700         if (start_nic(sp)) {
6701                 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
6702                 s2io_reset(sp);
6703                 free_rx_buffers(sp);
6704                 return -ENODEV;
6705         }
6706
6707         /* Add interrupt service routine */
6708         if (s2io_add_isr(sp) != 0) {
6709                 if (sp->intr_type == MSI_X)
6710                         s2io_rem_isr(sp);
6711                 s2io_reset(sp);
6712                 free_rx_buffers(sp);
6713                 return -ENODEV;
6714         }
6715
6716         S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
6717
6718         /* Enable tasklet for the device */
6719         tasklet_init(&sp->task, s2io_tasklet, (unsigned long) dev);
6720
6721         /*  Enable select interrupts */
6722         if (sp->intr_type != INTA)
6723                 en_dis_able_nic_intrs(sp, ENA_ALL_INTRS, DISABLE_INTRS);
6724         else {
6725                 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
6726                 interruptible |= TX_PIC_INTR | RX_PIC_INTR;
6727                 interruptible |= TX_MAC_INTR | RX_MAC_INTR;
6728                 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
6729         }
6730
6731
6732         atomic_set(&sp->card_state, CARD_UP);
6733         return 0;
6734 }
6735
6736 /**
6737  * s2io_restart_nic - Resets the NIC.
6738  * @data : long pointer to the device private structure
6739  * Description:
6740  * This function is scheduled to be run by the s2io_tx_watchdog
6741  * function after 0.5 secs to reset the NIC. The idea is to reduce
6742  * the run time of the watch dog routine which is run holding a
6743  * spin lock.
6744  */
6745
6746 static void s2io_restart_nic(struct work_struct *work)
6747 {
6748         struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
6749         struct net_device *dev = sp->dev;
6750
6751         rtnl_lock();
6752
6753         if (!netif_running(dev))
6754                 goto out_unlock;
6755
6756         s2io_card_down(sp);
6757         if (s2io_card_up(sp)) {
6758                 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6759                           dev->name);
6760         }
6761         netif_wake_queue(dev);
6762         DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
6763                   dev->name);
6764 out_unlock:
6765         rtnl_unlock();
6766 }
6767
6768 /**
6769  *  s2io_tx_watchdog - Watchdog for transmit side.
6770  *  @dev : Pointer to net device structure
6771  *  Description:
6772  *  This function is triggered if the Tx Queue is stopped
6773  *  for a pre-defined amount of time when the Interface is still up.
6774  *  If the Interface is jammed in such a situation, the hardware is
6775  *  reset (by s2io_close) and restarted again (by s2io_open) to
6776  *  overcome any problem that might have been caused in the hardware.
6777  *  Return value:
6778  *  void
6779  */
6780
6781 static void s2io_tx_watchdog(struct net_device *dev)
6782 {
6783         struct s2io_nic *sp = dev->priv;
6784
6785         if (netif_carrier_ok(dev)) {
6786                 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt++;
6787                 schedule_work(&sp->rst_timer_task);
6788                 sp->mac_control.stats_info->sw_stat.soft_reset_cnt++;
6789         }
6790 }
6791
6792 /**
6793  *   rx_osm_handler - To perform some OS related operations on SKB.
6794  *   @sp: private member of the device structure,pointer to s2io_nic structure.
6795  *   @skb : the socket buffer pointer.
6796  *   @len : length of the packet
6797  *   @cksum : FCS checksum of the frame.
6798  *   @ring_no : the ring from which this RxD was extracted.
6799  *   Description:
6800  *   This function is called by the Rx interrupt serivce routine to perform
6801  *   some OS related operations on the SKB before passing it to the upper
6802  *   layers. It mainly checks if the checksum is OK, if so adds it to the
6803  *   SKBs cksum variable, increments the Rx packet count and passes the SKB
6804  *   to the upper layer. If the checksum is wrong, it increments the Rx
6805  *   packet error count, frees the SKB and returns error.
6806  *   Return value:
6807  *   SUCCESS on success and -1 on failure.
6808  */
6809 static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
6810 {
6811         struct s2io_nic *sp = ring_data->nic;
6812         struct net_device *dev = (struct net_device *) sp->dev;
6813         struct sk_buff *skb = (struct sk_buff *)
6814                 ((unsigned long) rxdp->Host_Control);
6815         int ring_no = ring_data->ring_no;
6816         u16 l3_csum, l4_csum;
6817         unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
6818         struct lro *lro;
6819
6820         skb->dev = dev;
6821
6822         if (err) {
6823                 /* Check for parity error */
6824                 if (err & 0x1) {
6825                         sp->mac_control.stats_info->sw_stat.parity_err_cnt++;
6826                 }
6827                 err >>= 48;
6828                 switch(err) {
6829                         case 1:
6830                                 sp->mac_control.stats_info->sw_stat.
6831                                 rx_parity_err_cnt++;
6832                         break;
6833
6834                         case 2:
6835                                 sp->mac_control.stats_info->sw_stat.
6836                                 rx_abort_cnt++;
6837                         break;
6838
6839                         case 3:
6840                                 sp->mac_control.stats_info->sw_stat.
6841                                 rx_parity_abort_cnt++;
6842                         break;
6843
6844                         case 4:
6845                                 sp->mac_control.stats_info->sw_stat.
6846                                 rx_rda_fail_cnt++;
6847                         break;
6848
6849                         case 5:
6850                                 sp->mac_control.stats_info->sw_stat.
6851                                 rx_unkn_prot_cnt++;
6852                         break;
6853
6854                         case 6:
6855                                 sp->mac_control.stats_info->sw_stat.
6856                                 rx_fcs_err_cnt++;
6857                         break;
6858
6859                         case 7:
6860                                 sp->mac_control.stats_info->sw_stat.
6861                                 rx_buf_size_err_cnt++;
6862                         break;
6863
6864                         case 8:
6865                                 sp->mac_control.stats_info->sw_stat.
6866                                 rx_rxd_corrupt_cnt++;
6867                         break;
6868
6869                         case 15:
6870                                 sp->mac_control.stats_info->sw_stat.
6871                                 rx_unkn_err_cnt++;
6872                         break;
6873                 }
6874                 /*
6875                 * Drop the packet if bad transfer code. Exception being
6876                 * 0x5, which could be due to unsupported IPv6 extension header.
6877                 * In this case, we let stack handle the packet.
6878                 * Note that in this case, since checksum will be incorrect,
6879                 * stack will validate the same.
6880                 */
6881                 if (err != 0x5) {
6882                         DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%llx\n",
6883                                 dev->name, err);
6884                         sp->stats.rx_crc_errors++;
6885                         sp->mac_control.stats_info->sw_stat.mem_freed
6886                                 += skb->truesize;
6887                         dev_kfree_skb(skb);
6888                         atomic_dec(&sp->rx_bufs_left[ring_no]);
6889                         rxdp->Host_Control = 0;
6890                         return 0;
6891                 }
6892         }
6893
6894         /* Updating statistics */
6895         rxdp->Host_Control = 0;
6896         if (sp->rxd_mode == RXD_MODE_1) {
6897                 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
6898
6899                 sp->stats.rx_bytes += len;
6900                 skb_put(skb, len);
6901
6902         } else if (sp->rxd_mode >= RXD_MODE_3A) {
6903                 int get_block = ring_data->rx_curr_get_info.block_index;
6904                 int get_off = ring_data->rx_curr_get_info.offset;
6905                 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
6906                 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
6907                 unsigned char *buff = skb_push(skb, buf0_len);
6908
6909                 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
6910                 sp->stats.rx_bytes += buf0_len + buf2_len;
6911                 memcpy(buff, ba->ba_0, buf0_len);
6912
6913                 if (sp->rxd_mode == RXD_MODE_3A) {
6914                         int buf1_len = RXD_GET_BUFFER1_SIZE_3(rxdp->Control_2);
6915
6916                         skb_put(skb, buf1_len);
6917                         skb->len += buf2_len;
6918                         skb->data_len += buf2_len;
6919                         skb_put(skb_shinfo(skb)->frag_list, buf2_len);
6920                         sp->stats.rx_bytes += buf1_len;
6921
6922                 } else
6923                         skb_put(skb, buf2_len);
6924         }
6925
6926         if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && ((!sp->lro) ||
6927             (sp->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
6928             (sp->rx_csum)) {
6929                 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
6930                 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
6931                 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
6932                         /*
6933                          * NIC verifies if the Checksum of the received
6934                          * frame is Ok or not and accordingly returns
6935                          * a flag in the RxD.
6936                          */
6937                         skb->ip_summed = CHECKSUM_UNNECESSARY;
6938                         if (sp->lro) {
6939                                 u32 tcp_len;
6940                                 u8 *tcp;
6941                                 int ret = 0;
6942
6943                                 ret = s2io_club_tcp_session(skb->data, &tcp,
6944                                                 &tcp_len, &lro, rxdp, sp);
6945                                 switch (ret) {
6946                                         case 3: /* Begin anew */
6947                                                 lro->parent = skb;
6948                                                 goto aggregate;
6949                                         case 1: /* Aggregate */
6950                                         {
6951                                                 lro_append_pkt(sp, lro,
6952                                                         skb, tcp_len);
6953                                                 goto aggregate;
6954                                         }
6955                                         case 4: /* Flush session */
6956                                         {
6957                                                 lro_append_pkt(sp, lro,
6958                                                         skb, tcp_len);
6959                                                 queue_rx_frame(lro->parent);
6960                                                 clear_lro_session(lro);
6961                                                 sp->mac_control.stats_info->
6962                                                     sw_stat.flush_max_pkts++;
6963                                                 goto aggregate;
6964                                         }
6965                                         case 2: /* Flush both */
6966                                                 lro->parent->data_len =
6967                                                         lro->frags_len;
6968                                                 sp->mac_control.stats_info->
6969                                                      sw_stat.sending_both++;
6970                                                 queue_rx_frame(lro->parent);
6971                                                 clear_lro_session(lro);
6972                                                 goto send_up;
6973                                         case 0: /* sessions exceeded */
6974                                         case -1: /* non-TCP or not
6975                                                   * L2 aggregatable
6976                                                   */
6977                                         case 5: /*
6978                                                  * First pkt in session not
6979                                                  * L3/L4 aggregatable
6980                                                  */
6981                                                 break;
6982                                         default:
6983                                                 DBG_PRINT(ERR_DBG,
6984                                                         "%s: Samadhana!!\n",
6985                                                          __FUNCTION__);
6986                                                 BUG();
6987                                 }
6988                         }
6989                 } else {
6990                         /*
6991                          * Packet with erroneous checksum, let the
6992                          * upper layers deal with it.
6993                          */
6994                         skb->ip_summed = CHECKSUM_NONE;
6995                 }
6996         } else {
6997                 skb->ip_summed = CHECKSUM_NONE;
6998         }
6999         sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
7000         if (!sp->lro) {
7001                 skb->protocol = eth_type_trans(skb, dev);
7002                 if ((sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2) &&
7003                         vlan_strip_flag)) {
7004                         /* Queueing the vlan frame to the upper layer */
7005                         if (napi)
7006                                 vlan_hwaccel_receive_skb(skb, sp->vlgrp,
7007                                         RXD_GET_VLAN_TAG(rxdp->Control_2));
7008                         else
7009                                 vlan_hwaccel_rx(skb, sp->vlgrp,
7010                                         RXD_GET_VLAN_TAG(rxdp->Control_2));
7011                 } else {
7012                         if (napi)
7013                                 netif_receive_skb(skb);
7014                         else
7015                                 netif_rx(skb);
7016                 }
7017         } else {
7018 send_up:
7019                 queue_rx_frame(skb);
7020         }
7021         dev->last_rx = jiffies;
7022 aggregate:
7023         atomic_dec(&sp->rx_bufs_left[ring_no]);
7024         return SUCCESS;
7025 }
7026
7027 /**
7028  *  s2io_link - stops/starts the Tx queue.
7029  *  @sp : private member of the device structure, which is a pointer to the
7030  *  s2io_nic structure.
7031  *  @link : inidicates whether link is UP/DOWN.
7032  *  Description:
7033  *  This function stops/starts the Tx queue depending on whether the link
7034  *  status of the NIC is is down or up. This is called by the Alarm
7035  *  interrupt handler whenever a link change interrupt comes up.
7036  *  Return value:
7037  *  void.
7038  */
7039
7040 static void s2io_link(struct s2io_nic * sp, int link)
7041 {
7042         struct net_device *dev = (struct net_device *) sp->dev;
7043
7044         if (link != sp->last_link_state) {
7045                 if (link == LINK_DOWN) {
7046                         DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
7047                         netif_carrier_off(dev);
7048                         if(sp->mac_control.stats_info->sw_stat.link_up_cnt)
7049                         sp->mac_control.stats_info->sw_stat.link_up_time =
7050                                 jiffies - sp->start_time;
7051                         sp->mac_control.stats_info->sw_stat.link_down_cnt++;
7052                 } else {
7053                         DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
7054                         if (sp->mac_control.stats_info->sw_stat.link_down_cnt)
7055                         sp->mac_control.stats_info->sw_stat.link_down_time =
7056                                 jiffies - sp->start_time;
7057                         sp->mac_control.stats_info->sw_stat.link_up_cnt++;
7058                         netif_carrier_on(dev);
7059                 }
7060         }
7061         sp->last_link_state = link;
7062         sp->start_time = jiffies;
7063 }
7064
7065 /**
7066  *  get_xena_rev_id - to identify revision ID of xena.
7067  *  @pdev : PCI Dev structure
7068  *  Description:
7069  *  Function to identify the Revision ID of xena.
7070  *  Return value:
7071  *  returns the revision ID of the device.
7072  */
7073
7074 static int get_xena_rev_id(struct pci_dev *pdev)
7075 {
7076         u8 id = 0;
7077         int ret;
7078         ret = pci_read_config_byte(pdev, PCI_REVISION_ID, (u8 *) & id);
7079         return id;
7080 }
7081
7082 /**
7083  *  s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7084  *  @sp : private member of the device structure, which is a pointer to the
7085  *  s2io_nic structure.
7086  *  Description:
7087  *  This function initializes a few of the PCI and PCI-X configuration registers
7088  *  with recommended values.
7089  *  Return value:
7090  *  void
7091  */
7092
7093 static void s2io_init_pci(struct s2io_nic * sp)
7094 {
7095         u16 pci_cmd = 0, pcix_cmd = 0;
7096
7097         /* Enable Data Parity Error Recovery in PCI-X command register. */
7098         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7099                              &(pcix_cmd));
7100         pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7101                               (pcix_cmd | 1));
7102         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7103                              &(pcix_cmd));
7104
7105         /* Set the PErr Response bit in PCI command register. */
7106         pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7107         pci_write_config_word(sp->pdev, PCI_COMMAND,
7108                               (pci_cmd | PCI_COMMAND_PARITY));
7109         pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7110 }
7111
7112 static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type)
7113 {
7114         if ( tx_fifo_num > 8) {
7115                 DBG_PRINT(ERR_DBG, "s2io: Requested number of Tx fifos not "
7116                          "supported\n");
7117                 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Tx fifos\n");
7118                 tx_fifo_num = 8;
7119         }
7120         if ( rx_ring_num > 8) {
7121                 DBG_PRINT(ERR_DBG, "s2io: Requested number of Rx rings not "
7122                          "supported\n");
7123                 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Rx rings\n");
7124                 rx_ring_num = 8;
7125         }
7126         if (*dev_intr_type != INTA)
7127                 napi = 0;
7128
7129 #ifndef CONFIG_PCI_MSI
7130         if (*dev_intr_type != INTA) {
7131                 DBG_PRINT(ERR_DBG, "s2io: This kernel does not support"
7132                           "MSI/MSI-X. Defaulting to INTA\n");
7133                 *dev_intr_type = INTA;
7134         }
7135 #else
7136         if (*dev_intr_type > MSI_X) {
7137                 DBG_PRINT(ERR_DBG, "s2io: Wrong intr_type requested. "
7138                           "Defaulting to INTA\n");
7139                 *dev_intr_type = INTA;
7140         }
7141 #endif
7142         if ((*dev_intr_type == MSI_X) &&
7143                         ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7144                         (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
7145                 DBG_PRINT(ERR_DBG, "s2io: Xframe I does not support MSI_X. "
7146                                         "Defaulting to INTA\n");
7147                 *dev_intr_type = INTA;
7148         }
7149
7150         if (rx_ring_mode > 3) {
7151                 DBG_PRINT(ERR_DBG, "s2io: Requested ring mode not supported\n");
7152                 DBG_PRINT(ERR_DBG, "s2io: Defaulting to 3-buffer mode\n");
7153                 rx_ring_mode = 3;
7154         }
7155         return SUCCESS;
7156 }
7157
7158 /**
7159  * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7160  * or Traffic class respectively.
7161  * @nic: device peivate variable
7162  * Description: The function configures the receive steering to
7163  * desired receive ring.
7164  * Return Value:  SUCCESS on success and
7165  * '-1' on failure (endian settings incorrect).
7166  */
7167 static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7168 {
7169         struct XENA_dev_config __iomem *bar0 = nic->bar0;
7170         register u64 val64 = 0;
7171
7172         if (ds_codepoint > 63)
7173                 return FAILURE;
7174
7175         val64 = RTS_DS_MEM_DATA(ring);
7176         writeq(val64, &bar0->rts_ds_mem_data);
7177
7178         val64 = RTS_DS_MEM_CTRL_WE |
7179                 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7180                 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7181
7182         writeq(val64, &bar0->rts_ds_mem_ctrl);
7183
7184         return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
7185                                 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7186                                 S2IO_BIT_RESET);
7187 }
7188
7189 /**
7190  *  s2io_init_nic - Initialization of the adapter .
7191  *  @pdev : structure containing the PCI related information of the device.
7192  *  @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7193  *  Description:
7194  *  The function initializes an adapter identified by the pci_dec structure.
7195  *  All OS related initialization including memory and device structure and
7196  *  initlaization of the device private variable is done. Also the swapper
7197  *  control register is initialized to enable read and write into the I/O
7198  *  registers of the device.
7199  *  Return value:
7200  *  returns 0 on success and negative on failure.
7201  */
7202
7203 static int __devinit
7204 s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7205 {
7206         struct s2io_nic *sp;
7207         struct net_device *dev;
7208         int i, j, ret;
7209         int dma_flag = FALSE;
7210         u32 mac_up, mac_down;
7211         u64 val64 = 0, tmp64 = 0;
7212         struct XENA_dev_config __iomem *bar0 = NULL;
7213         u16 subid;
7214         struct mac_info *mac_control;
7215         struct config_param *config;
7216         int mode;
7217         u8 dev_intr_type = intr_type;
7218
7219         if ((ret = s2io_verify_parm(pdev, &dev_intr_type)))
7220                 return ret;
7221
7222         if ((ret = pci_enable_device(pdev))) {
7223                 DBG_PRINT(ERR_DBG,
7224                           "s2io_init_nic: pci_enable_device failed\n");
7225                 return ret;
7226         }
7227
7228         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
7229                 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
7230                 dma_flag = TRUE;
7231                 if (pci_set_consistent_dma_mask
7232                     (pdev, DMA_64BIT_MASK)) {
7233                         DBG_PRINT(ERR_DBG,
7234                                   "Unable to obtain 64bit DMA for \
7235                                         consistent allocations\n");
7236                         pci_disable_device(pdev);
7237                         return -ENOMEM;
7238                 }
7239         } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
7240                 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
7241         } else {
7242                 pci_disable_device(pdev);
7243                 return -ENOMEM;
7244         }
7245         if (dev_intr_type != MSI_X) {
7246                 if (pci_request_regions(pdev, s2io_driver_name)) {
7247                         DBG_PRINT(ERR_DBG, "Request Regions failed\n");
7248                         pci_disable_device(pdev);
7249                         return -ENODEV;
7250                 }
7251         }
7252         else {
7253                 if (!(request_mem_region(pci_resource_start(pdev, 0),
7254                          pci_resource_len(pdev, 0), s2io_driver_name))) {
7255                         DBG_PRINT(ERR_DBG, "bar0 Request Regions failed\n");
7256                         pci_disable_device(pdev);
7257                         return -ENODEV;
7258                 }
7259                 if (!(request_mem_region(pci_resource_start(pdev, 2),
7260                          pci_resource_len(pdev, 2), s2io_driver_name))) {
7261                         DBG_PRINT(ERR_DBG, "bar1 Request Regions failed\n");
7262                         release_mem_region(pci_resource_start(pdev, 0),
7263                                    pci_resource_len(pdev, 0));
7264                         pci_disable_device(pdev);
7265                         return -ENODEV;
7266                 }
7267         }
7268
7269         dev = alloc_etherdev(sizeof(struct s2io_nic));
7270         if (dev == NULL) {
7271                 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
7272                 pci_disable_device(pdev);
7273                 pci_release_regions(pdev);
7274                 return -ENODEV;
7275         }
7276
7277         pci_set_master(pdev);
7278         pci_set_drvdata(pdev, dev);
7279         SET_MODULE_OWNER(dev);
7280         SET_NETDEV_DEV(dev, &pdev->dev);
7281
7282         /*  Private member variable initialized to s2io NIC structure */
7283         sp = dev->priv;
7284         memset(sp, 0, sizeof(struct s2io_nic));
7285         sp->dev = dev;
7286         sp->pdev = pdev;
7287         sp->high_dma_flag = dma_flag;
7288         sp->device_enabled_once = FALSE;
7289         if (rx_ring_mode == 1)
7290                 sp->rxd_mode = RXD_MODE_1;
7291         if (rx_ring_mode == 2)
7292                 sp->rxd_mode = RXD_MODE_3B;
7293         if (rx_ring_mode == 3)
7294                 sp->rxd_mode = RXD_MODE_3A;
7295
7296         sp->intr_type = dev_intr_type;
7297
7298         if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
7299                 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
7300                 sp->device_type = XFRAME_II_DEVICE;
7301         else
7302                 sp->device_type = XFRAME_I_DEVICE;
7303
7304         sp->lro = lro;
7305
7306         /* Initialize some PCI/PCI-X fields of the NIC. */
7307         s2io_init_pci(sp);
7308
7309         /*
7310          * Setting the device configuration parameters.
7311          * Most of these parameters can be specified by the user during
7312          * module insertion as they are module loadable parameters. If
7313          * these parameters are not not specified during load time, they
7314          * are initialized with default values.
7315          */
7316         mac_control = &sp->mac_control;
7317         config = &sp->config;
7318
7319         /* Tx side parameters. */
7320         config->tx_fifo_num = tx_fifo_num;
7321         for (i = 0; i < MAX_TX_FIFOS; i++) {
7322                 config->tx_cfg[i].fifo_len = tx_fifo_len[i];
7323                 config->tx_cfg[i].fifo_priority = i;
7324         }
7325
7326         /* mapping the QoS priority to the configured fifos */
7327         for (i = 0; i < MAX_TX_FIFOS; i++)
7328                 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num][i];
7329
7330         config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7331         for (i = 0; i < config->tx_fifo_num; i++) {
7332                 config->tx_cfg[i].f_no_snoop =
7333                     (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7334                 if (config->tx_cfg[i].fifo_len < 65) {
7335                         config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7336                         break;
7337                 }
7338         }
7339         /* + 2 because one Txd for skb->data and one Txd for UFO */
7340         config->max_txds = MAX_SKB_FRAGS + 2;
7341
7342         /* Rx side parameters. */
7343         config->rx_ring_num = rx_ring_num;
7344         for (i = 0; i < MAX_RX_RINGS; i++) {
7345                 config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
7346                     (rxd_count[sp->rxd_mode] + 1);
7347                 config->rx_cfg[i].ring_priority = i;
7348         }
7349
7350         for (i = 0; i < rx_ring_num; i++) {
7351                 config->rx_cfg[i].ring_org = RING_ORG_BUFF1;
7352                 config->rx_cfg[i].f_no_snoop =
7353                     (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
7354         }
7355
7356         /*  Setting Mac Control parameters */
7357         mac_control->rmac_pause_time = rmac_pause_time;
7358         mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7359         mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7360
7361
7362         /* Initialize Ring buffer parameters. */
7363         for (i = 0; i < config->rx_ring_num; i++)
7364                 atomic_set(&sp->rx_bufs_left[i], 0);
7365
7366         /* Initialize the number of ISRs currently running */
7367         atomic_set(&sp->isr_cnt, 0);
7368
7369         /*  initialize the shared memory used by the NIC and the host */
7370         if (init_shared_mem(sp)) {
7371                 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
7372                           dev->name);
7373                 ret = -ENOMEM;
7374                 goto mem_alloc_failed;
7375         }
7376
7377         sp->bar0 = ioremap(pci_resource_start(pdev, 0),
7378                                      pci_resource_len(pdev, 0));
7379         if (!sp->bar0) {
7380                 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
7381                           dev->name);
7382                 ret = -ENOMEM;
7383                 goto bar0_remap_failed;
7384         }
7385
7386         sp->bar1 = ioremap(pci_resource_start(pdev, 2),
7387                                      pci_resource_len(pdev, 2));
7388         if (!sp->bar1) {
7389                 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
7390                           dev->name);
7391                 ret = -ENOMEM;
7392                 goto bar1_remap_failed;
7393         }
7394
7395         dev->irq = pdev->irq;
7396         dev->base_addr = (unsigned long) sp->bar0;
7397
7398         /* Initializing the BAR1 address as the start of the FIFO pointer. */
7399         for (j = 0; j < MAX_TX_FIFOS; j++) {
7400                 mac_control->tx_FIFO_start[j] = (struct TxFIFO_element __iomem *)
7401                     (sp->bar1 + (j * 0x00020000));
7402         }
7403
7404         /*  Driver entry points */
7405         dev->open = &s2io_open;
7406         dev->stop = &s2io_close;
7407         dev->hard_start_xmit = &s2io_xmit;
7408         dev->get_stats = &s2io_get_stats;
7409         dev->set_multicast_list = &s2io_set_multicast;
7410         dev->do_ioctl = &s2io_ioctl;
7411         dev->change_mtu = &s2io_change_mtu;
7412         SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
7413         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7414         dev->vlan_rx_register = s2io_vlan_rx_register;
7415         dev->vlan_rx_kill_vid = (void *)s2io_vlan_rx_kill_vid;
7416
7417         /*
7418          * will use eth_mac_addr() for  dev->set_mac_address
7419          * mac address will be set every time dev->open() is called
7420          */
7421         dev->poll = s2io_poll;
7422         dev->weight = 32;
7423
7424 #ifdef CONFIG_NET_POLL_CONTROLLER
7425         dev->poll_controller = s2io_netpoll;
7426 #endif
7427
7428         dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
7429         if (sp->high_dma_flag == TRUE)
7430                 dev->features |= NETIF_F_HIGHDMA;
7431         dev->features |= NETIF_F_TSO;
7432         dev->features |= NETIF_F_TSO6;
7433         if ((sp->device_type & XFRAME_II_DEVICE) && (ufo))  {
7434                 dev->features |= NETIF_F_UFO;
7435                 dev->features |= NETIF_F_HW_CSUM;
7436         }
7437
7438         dev->tx_timeout = &s2io_tx_watchdog;
7439         dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
7440         INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
7441         INIT_WORK(&sp->set_link_task, s2io_set_link);
7442
7443         pci_save_state(sp->pdev);
7444
7445         /* Setting swapper control on the NIC, for proper reset operation */
7446         if (s2io_set_swapper(sp)) {
7447                 DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
7448                           dev->name);
7449                 ret = -EAGAIN;
7450                 goto set_swap_failed;
7451         }
7452
7453         /* Verify if the Herc works on the slot its placed into */
7454         if (sp->device_type & XFRAME_II_DEVICE) {
7455                 mode = s2io_verify_pci_mode(sp);
7456                 if (mode < 0) {
7457                         DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__);
7458                         DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
7459                         ret = -EBADSLT;
7460                         goto set_swap_failed;
7461                 }
7462         }
7463
7464         /* Not needed for Herc */
7465         if (sp->device_type & XFRAME_I_DEVICE) {
7466                 /*
7467                  * Fix for all "FFs" MAC address problems observed on
7468                  * Alpha platforms
7469                  */
7470                 fix_mac_address(sp);
7471                 s2io_reset(sp);
7472         }
7473
7474         /*
7475          * MAC address initialization.
7476          * For now only one mac address will be read and used.
7477          */
7478         bar0 = sp->bar0;
7479         val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
7480             RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET);
7481         writeq(val64, &bar0->rmac_addr_cmd_mem);
7482         wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
7483                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, S2IO_BIT_RESET);
7484         tmp64 = readq(&bar0->rmac_addr_data0_mem);
7485         mac_down = (u32) tmp64;
7486         mac_up = (u32) (tmp64 >> 32);
7487
7488         sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
7489         sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
7490         sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
7491         sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
7492         sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
7493         sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
7494
7495         /*  Set the factory defined MAC address initially   */
7496         dev->addr_len = ETH_ALEN;
7497         memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
7498
7499         /* reset Nic and bring it to known state */
7500         s2io_reset(sp);
7501
7502         /*
7503          * Initialize the tasklet status and link state flags
7504          * and the card state parameter
7505          */
7506         atomic_set(&(sp->card_state), 0);
7507         sp->tasklet_status = 0;
7508         sp->link_state = 0;
7509
7510         /* Initialize spinlocks */
7511         spin_lock_init(&sp->tx_lock);
7512
7513         if (!napi)
7514                 spin_lock_init(&sp->put_lock);
7515         spin_lock_init(&sp->rx_lock);
7516
7517         /*
7518          * SXE-002: Configure link and activity LED to init state
7519          * on driver load.
7520          */
7521         subid = sp->pdev->subsystem_device;
7522         if ((subid & 0xFF) >= 0x07) {
7523                 val64 = readq(&bar0->gpio_control);
7524                 val64 |= 0x0000800000000000ULL;
7525                 writeq(val64, &bar0->gpio_control);
7526                 val64 = 0x0411040400000000ULL;
7527                 writeq(val64, (void __iomem *) bar0 + 0x2700);
7528                 val64 = readq(&bar0->gpio_control);
7529         }
7530
7531         sp->rx_csum = 1;        /* Rx chksum verify enabled by default */
7532
7533         if (register_netdev(dev)) {
7534                 DBG_PRINT(ERR_DBG, "Device registration failed\n");
7535                 ret = -ENODEV;
7536                 goto register_failed;
7537         }
7538         s2io_vpd_read(sp);
7539         DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2007 Neterion Inc.\n");
7540         DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n",dev->name,
7541                   sp->product_name, get_xena_rev_id(sp->pdev));
7542         DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
7543                   s2io_driver_version);
7544         DBG_PRINT(ERR_DBG, "%s: MAC ADDR: "
7545                           "%02x:%02x:%02x:%02x:%02x:%02x", dev->name,
7546                           sp->def_mac_addr[0].mac_addr[0],
7547                           sp->def_mac_addr[0].mac_addr[1],
7548                           sp->def_mac_addr[0].mac_addr[2],
7549                           sp->def_mac_addr[0].mac_addr[3],
7550                           sp->def_mac_addr[0].mac_addr[4],
7551                           sp->def_mac_addr[0].mac_addr[5]);
7552         DBG_PRINT(ERR_DBG, "SERIAL NUMBER: %s\n", sp->serial_num);
7553         if (sp->device_type & XFRAME_II_DEVICE) {
7554                 mode = s2io_print_pci_mode(sp);
7555                 if (mode < 0) {
7556                         DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
7557                         ret = -EBADSLT;
7558                         unregister_netdev(dev);
7559                         goto set_swap_failed;
7560                 }
7561         }
7562         switch(sp->rxd_mode) {
7563                 case RXD_MODE_1:
7564                     DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
7565                                                 dev->name);
7566                     break;
7567                 case RXD_MODE_3B:
7568                     DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
7569                                                 dev->name);
7570                     break;
7571                 case RXD_MODE_3A:
7572                     DBG_PRINT(ERR_DBG, "%s: 3-Buffer receive mode enabled\n",
7573                                                 dev->name);
7574                     break;
7575         }
7576
7577         if (napi)
7578                 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
7579         switch(sp->intr_type) {
7580                 case INTA:
7581                     DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
7582                     break;
7583                 case MSI:
7584                     DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI\n", dev->name);
7585                     break;
7586                 case MSI_X:
7587                     DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
7588                     break;
7589         }
7590         if (sp->lro)
7591                 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
7592                           dev->name);
7593         if (ufo)
7594                 DBG_PRINT(ERR_DBG, "%s: UDP Fragmentation Offload(UFO)"
7595                                         " enabled\n", dev->name);
7596         /* Initialize device name */
7597         sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
7598
7599         /* Initialize bimodal Interrupts */
7600         sp->config.bimodal = bimodal;
7601         if (!(sp->device_type & XFRAME_II_DEVICE) && bimodal) {
7602                 sp->config.bimodal = 0;
7603                 DBG_PRINT(ERR_DBG,"%s:Bimodal intr not supported by Xframe I\n",
7604                         dev->name);
7605         }
7606
7607         /*
7608          * Make Link state as off at this point, when the Link change
7609          * interrupt comes the state will be automatically changed to
7610          * the right state.
7611          */
7612         netif_carrier_off(dev);
7613
7614         return 0;
7615
7616       register_failed:
7617       set_swap_failed:
7618         iounmap(sp->bar1);
7619       bar1_remap_failed:
7620         iounmap(sp->bar0);
7621       bar0_remap_failed:
7622       mem_alloc_failed:
7623         free_shared_mem(sp);
7624         pci_disable_device(pdev);
7625         if (dev_intr_type != MSI_X)
7626                 pci_release_regions(pdev);
7627         else {
7628                 release_mem_region(pci_resource_start(pdev, 0),
7629                         pci_resource_len(pdev, 0));
7630                 release_mem_region(pci_resource_start(pdev, 2),
7631                         pci_resource_len(pdev, 2));
7632         }
7633         pci_set_drvdata(pdev, NULL);
7634         free_netdev(dev);
7635
7636         return ret;
7637 }
7638
7639 /**
7640  * s2io_rem_nic - Free the PCI device
7641  * @pdev: structure containing the PCI related information of the device.
7642  * Description: This function is called by the Pci subsystem to release a
7643  * PCI device and free up all resource held up by the device. This could
7644  * be in response to a Hot plug event or when the driver is to be removed
7645  * from memory.
7646  */
7647
7648 static void __devexit s2io_rem_nic(struct pci_dev *pdev)
7649 {
7650         struct net_device *dev =
7651             (struct net_device *) pci_get_drvdata(pdev);
7652         struct s2io_nic *sp;
7653
7654         if (dev == NULL) {
7655                 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
7656                 return;
7657         }
7658
7659         flush_scheduled_work();
7660
7661         sp = dev->priv;
7662         unregister_netdev(dev);
7663
7664         free_shared_mem(sp);
7665         iounmap(sp->bar0);
7666         iounmap(sp->bar1);
7667         if (sp->intr_type != MSI_X)
7668                 pci_release_regions(pdev);
7669         else {
7670                 release_mem_region(pci_resource_start(pdev, 0),
7671                         pci_resource_len(pdev, 0));
7672                 release_mem_region(pci_resource_start(pdev, 2),
7673                         pci_resource_len(pdev, 2));
7674         }
7675         pci_set_drvdata(pdev, NULL);
7676         free_netdev(dev);
7677         pci_disable_device(pdev);
7678 }
7679
7680 /**
7681  * s2io_starter - Entry point for the driver
7682  * Description: This function is the entry point for the driver. It verifies
7683  * the module loadable parameters and initializes PCI configuration space.
7684  */
7685
7686 int __init s2io_starter(void)
7687 {
7688         return pci_register_driver(&s2io_driver);
7689 }
7690
7691 /**
7692  * s2io_closer - Cleanup routine for the driver
7693  * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
7694  */
7695
7696 static __exit void s2io_closer(void)
7697 {
7698         pci_unregister_driver(&s2io_driver);
7699         DBG_PRINT(INIT_DBG, "cleanup done\n");
7700 }
7701
7702 module_init(s2io_starter);
7703 module_exit(s2io_closer);
7704
7705 static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
7706                 struct tcphdr **tcp, struct RxD_t *rxdp)
7707 {
7708         int ip_off;
7709         u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
7710
7711         if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
7712                 DBG_PRINT(INIT_DBG,"%s: Non-TCP frames not supported for LRO\n",
7713                           __FUNCTION__);
7714                 return -1;
7715         }
7716
7717         /* TODO:
7718          * By default the VLAN field in the MAC is stripped by the card, if this
7719          * feature is turned off in rx_pa_cfg register, then the ip_off field
7720          * has to be shifted by a further 2 bytes
7721          */
7722         switch (l2_type) {
7723                 case 0: /* DIX type */
7724                 case 4: /* DIX type with VLAN */
7725                         ip_off = HEADER_ETHERNET_II_802_3_SIZE;
7726                         break;
7727                 /* LLC, SNAP etc are considered non-mergeable */
7728                 default:
7729                         return -1;
7730         }
7731
7732         *ip = (struct iphdr *)((u8 *)buffer + ip_off);
7733         ip_len = (u8)((*ip)->ihl);
7734         ip_len <<= 2;
7735         *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
7736
7737         return 0;
7738 }
7739
7740 static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
7741                                   struct tcphdr *tcp)
7742 {
7743         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7744         if ((lro->iph->saddr != ip->saddr) || (lro->iph->daddr != ip->daddr) ||
7745            (lro->tcph->source != tcp->source) || (lro->tcph->dest != tcp->dest))
7746                 return -1;
7747         return 0;
7748 }
7749
7750 static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
7751 {
7752         return(ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2));
7753 }
7754
7755 static void initiate_new_session(struct lro *lro, u8 *l2h,
7756                      struct iphdr *ip, struct tcphdr *tcp, u32 tcp_pyld_len)
7757 {
7758         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7759         lro->l2h = l2h;
7760         lro->iph = ip;
7761         lro->tcph = tcp;
7762         lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
7763         lro->tcp_ack = ntohl(tcp->ack_seq);
7764         lro->sg_num = 1;
7765         lro->total_len = ntohs(ip->tot_len);
7766         lro->frags_len = 0;
7767         /*
7768          * check if we saw TCP timestamp. Other consistency checks have
7769          * already been done.
7770          */
7771         if (tcp->doff == 8) {
7772                 u32 *ptr;
7773                 ptr = (u32 *)(tcp+1);
7774                 lro->saw_ts = 1;
7775                 lro->cur_tsval = *(ptr+1);
7776                 lro->cur_tsecr = *(ptr+2);
7777         }
7778         lro->in_use = 1;
7779 }
7780
7781 static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
7782 {
7783         struct iphdr *ip = lro->iph;
7784         struct tcphdr *tcp = lro->tcph;
7785         __sum16 nchk;
7786         struct stat_block *statinfo = sp->mac_control.stats_info;
7787         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7788
7789         /* Update L3 header */
7790         ip->tot_len = htons(lro->total_len);
7791         ip->check = 0;
7792         nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
7793         ip->check = nchk;
7794
7795         /* Update L4 header */
7796         tcp->ack_seq = lro->tcp_ack;
7797         tcp->window = lro->window;
7798
7799         /* Update tsecr field if this session has timestamps enabled */
7800         if (lro->saw_ts) {
7801                 u32 *ptr = (u32 *)(tcp + 1);
7802                 *(ptr+2) = lro->cur_tsecr;
7803         }
7804
7805         /* Update counters required for calculation of
7806          * average no. of packets aggregated.
7807          */
7808         statinfo->sw_stat.sum_avg_pkts_aggregated += lro->sg_num;
7809         statinfo->sw_stat.num_aggregations++;
7810 }
7811
7812 static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
7813                 struct tcphdr *tcp, u32 l4_pyld)
7814 {
7815         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7816         lro->total_len += l4_pyld;
7817         lro->frags_len += l4_pyld;
7818         lro->tcp_next_seq += l4_pyld;
7819         lro->sg_num++;
7820
7821         /* Update ack seq no. and window ad(from this pkt) in LRO object */
7822         lro->tcp_ack = tcp->ack_seq;
7823         lro->window = tcp->window;
7824
7825         if (lro->saw_ts) {
7826                 u32 *ptr;
7827                 /* Update tsecr and tsval from this packet */
7828                 ptr = (u32 *) (tcp + 1);
7829                 lro->cur_tsval = *(ptr + 1);
7830                 lro->cur_tsecr = *(ptr + 2);
7831         }
7832 }
7833
7834 static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
7835                                     struct tcphdr *tcp, u32 tcp_pyld_len)
7836 {
7837         u8 *ptr;
7838
7839         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7840
7841         if (!tcp_pyld_len) {
7842                 /* Runt frame or a pure ack */
7843                 return -1;
7844         }
7845
7846         if (ip->ihl != 5) /* IP has options */
7847                 return -1;
7848
7849         /* If we see CE codepoint in IP header, packet is not mergeable */
7850         if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
7851                 return -1;
7852
7853         /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
7854         if (tcp->urg || tcp->psh || tcp->rst || tcp->syn || tcp->fin ||
7855                                     tcp->ece || tcp->cwr || !tcp->ack) {
7856                 /*
7857                  * Currently recognize only the ack control word and
7858                  * any other control field being set would result in
7859                  * flushing the LRO session
7860                  */
7861                 return -1;
7862         }
7863
7864         /*
7865          * Allow only one TCP timestamp option. Don't aggregate if
7866          * any other options are detected.
7867          */
7868         if (tcp->doff != 5 && tcp->doff != 8)
7869                 return -1;
7870
7871         if (tcp->doff == 8) {
7872                 ptr = (u8 *)(tcp + 1);
7873                 while (*ptr == TCPOPT_NOP)
7874                         ptr++;
7875                 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
7876                         return -1;
7877
7878                 /* Ensure timestamp value increases monotonically */
7879                 if (l_lro)
7880                         if (l_lro->cur_tsval > *((u32 *)(ptr+2)))
7881                                 return -1;
7882
7883                 /* timestamp echo reply should be non-zero */
7884                 if (*((u32 *)(ptr+6)) == 0)
7885                         return -1;
7886         }
7887
7888         return 0;
7889 }
7890
7891 static int
7892 s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, struct lro **lro,
7893                       struct RxD_t *rxdp, struct s2io_nic *sp)
7894 {
7895         struct iphdr *ip;
7896         struct tcphdr *tcph;
7897         int ret = 0, i;
7898
7899         if (!(ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
7900                                          rxdp))) {
7901                 DBG_PRINT(INFO_DBG,"IP Saddr: %x Daddr: %x\n",
7902                           ip->saddr, ip->daddr);
7903         } else {
7904                 return ret;
7905         }
7906
7907         tcph = (struct tcphdr *)*tcp;
7908         *tcp_len = get_l4_pyld_length(ip, tcph);
7909         for (i=0; i<MAX_LRO_SESSIONS; i++) {
7910                 struct lro *l_lro = &sp->lro0_n[i];
7911                 if (l_lro->in_use) {
7912                         if (check_for_socket_match(l_lro, ip, tcph))
7913                                 continue;
7914                         /* Sock pair matched */
7915                         *lro = l_lro;
7916
7917                         if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
7918                                 DBG_PRINT(INFO_DBG, "%s:Out of order. expected "
7919                                           "0x%x, actual 0x%x\n", __FUNCTION__,
7920                                           (*lro)->tcp_next_seq,
7921                                           ntohl(tcph->seq));
7922
7923                                 sp->mac_control.stats_info->
7924                                    sw_stat.outof_sequence_pkts++;
7925                                 ret = 2;
7926                                 break;
7927                         }
7928
7929                         if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,*tcp_len))
7930                                 ret = 1; /* Aggregate */
7931                         else
7932                                 ret = 2; /* Flush both */
7933                         break;
7934                 }
7935         }
7936
7937         if (ret == 0) {
7938                 /* Before searching for available LRO objects,
7939                  * check if the pkt is L3/L4 aggregatable. If not
7940                  * don't create new LRO session. Just send this
7941                  * packet up.
7942                  */
7943                 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len)) {
7944                         return 5;
7945                 }
7946
7947                 for (i=0; i<MAX_LRO_SESSIONS; i++) {
7948                         struct lro *l_lro = &sp->lro0_n[i];
7949                         if (!(l_lro->in_use)) {
7950                                 *lro = l_lro;
7951                                 ret = 3; /* Begin anew */
7952                                 break;
7953                         }
7954                 }
7955         }
7956
7957         if (ret == 0) { /* sessions exceeded */
7958                 DBG_PRINT(INFO_DBG,"%s:All LRO sessions already in use\n",
7959                           __FUNCTION__);
7960                 *lro = NULL;
7961                 return ret;
7962         }
7963
7964         switch (ret) {
7965                 case 3:
7966                         initiate_new_session(*lro, buffer, ip, tcph, *tcp_len);
7967                         break;
7968                 case 2:
7969                         update_L3L4_header(sp, *lro);
7970                         break;
7971                 case 1:
7972                         aggregate_new_rx(*lro, ip, tcph, *tcp_len);
7973                         if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
7974                                 update_L3L4_header(sp, *lro);
7975                                 ret = 4; /* Flush the LRO */
7976                         }
7977                         break;
7978                 default:
7979                         DBG_PRINT(ERR_DBG,"%s:Dont know, can't say!!\n",
7980                                 __FUNCTION__);
7981                         break;
7982         }
7983
7984         return ret;
7985 }
7986
7987 static void clear_lro_session(struct lro *lro)
7988 {
7989         static u16 lro_struct_size = sizeof(struct lro);
7990
7991         memset(lro, 0, lro_struct_size);
7992 }
7993
7994 static void queue_rx_frame(struct sk_buff *skb)
7995 {
7996         struct net_device *dev = skb->dev;
7997
7998         skb->protocol = eth_type_trans(skb, dev);
7999         if (napi)
8000                 netif_receive_skb(skb);
8001         else
8002                 netif_rx(skb);
8003 }
8004
8005 static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
8006                            struct sk_buff *skb,
8007                            u32 tcp_len)
8008 {
8009         struct sk_buff *first = lro->parent;
8010
8011         first->len += tcp_len;
8012         first->data_len = lro->frags_len;
8013         skb_pull(skb, (skb->len - tcp_len));
8014         if (skb_shinfo(first)->frag_list)
8015                 lro->last_frag->next = skb;
8016         else
8017                 skb_shinfo(first)->frag_list = skb;
8018         first->truesize += skb->truesize;
8019         lro->last_frag = skb;
8020         sp->mac_control.stats_info->sw_stat.clubbed_frms_cnt++;
8021         return;
8022 }