Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[sfrench/cifs-2.6.git] / drivers / net / s2io.c
1 /************************************************************************
2  * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3  * Copyright(c) 2002-2007 Neterion Inc.
4
5  * This software may be used and distributed according to the terms of
6  * the GNU General Public License (GPL), incorporated herein by reference.
7  * Drivers based on or derived from this code fall under the GPL and must
8  * retain the authorship, copyright and license notice.  This file is not
9  * a complete program and may only be used when the entire operating
10  * system is licensed under the GPL.
11  * See the file COPYING in this distribution for more information.
12  *
13  * Credits:
14  * Jeff Garzik          : For pointing out the improper error condition
15  *                        check in the s2io_xmit routine and also some
16  *                        issues in the Tx watch dog function. Also for
17  *                        patiently answering all those innumerable
18  *                        questions regaring the 2.6 porting issues.
19  * Stephen Hemminger    : Providing proper 2.6 porting mechanism for some
20  *                        macros available only in 2.6 Kernel.
21  * Francois Romieu      : For pointing out all code part that were
22  *                        deprecated and also styling related comments.
23  * Grant Grundler       : For helping me get rid of some Architecture
24  *                        dependent code.
25  * Christopher Hellwig  : Some more 2.6 specific issues in the driver.
26  *
27  * The module loadable parameters that are supported by the driver and a brief
28  * explaination of all the variables.
29  *
30  * rx_ring_num : This can be used to program the number of receive rings used
31  * in the driver.
32  * rx_ring_sz: This defines the number of receive blocks each ring can have.
33  *     This is also an array of size 8.
34  * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
35  *              values are 1, 2.
36  * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
37  * tx_fifo_len: This too is an array of 8. Each element defines the number of
38  * Tx descriptors that can be associated with each corresponding FIFO.
39  * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40  *     2(MSI_X). Default value is '2(MSI_X)'
41  * lro_enable: Specifies whether to enable Large Receive Offload (LRO) or not.
42  *     Possible values '1' for enable '0' for disable. Default is '0'
43  * lro_max_pkts: This parameter defines maximum number of packets can be
44  *     aggregated as a single large packet
45  * napi: This parameter used to enable/disable NAPI (polling Rx)
46  *     Possible values '1' for enable and '0' for disable. Default is '1'
47  * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
48  *      Possible values '1' for enable and '0' for disable. Default is '0'
49  * vlan_tag_strip: This can be used to enable or disable vlan stripping.
50  *                 Possible values '1' for enable , '0' for disable.
51  *                 Default is '2' - which means disable in promisc mode
52  *                 and enable in non-promiscuous mode.
53  ************************************************************************/
54
55 #include <linux/module.h>
56 #include <linux/types.h>
57 #include <linux/errno.h>
58 #include <linux/ioport.h>
59 #include <linux/pci.h>
60 #include <linux/dma-mapping.h>
61 #include <linux/kernel.h>
62 #include <linux/netdevice.h>
63 #include <linux/etherdevice.h>
64 #include <linux/skbuff.h>
65 #include <linux/init.h>
66 #include <linux/delay.h>
67 #include <linux/stddef.h>
68 #include <linux/ioctl.h>
69 #include <linux/timex.h>
70 #include <linux/ethtool.h>
71 #include <linux/workqueue.h>
72 #include <linux/if_vlan.h>
73 #include <linux/ip.h>
74 #include <linux/tcp.h>
75 #include <net/tcp.h>
76
77 #include <asm/system.h>
78 #include <asm/uaccess.h>
79 #include <asm/io.h>
80 #include <asm/div64.h>
81 #include <asm/irq.h>
82
83 /* local include */
84 #include "s2io.h"
85 #include "s2io-regs.h"
86
87 #define DRV_VERSION "2.0.26.6"
88
89 /* S2io Driver name & version. */
90 static char s2io_driver_name[] = "Neterion";
91 static char s2io_driver_version[] = DRV_VERSION;
92
93 static int rxd_size[2] = {32,48};
94 static int rxd_count[2] = {127,85};
95
96 static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
97 {
98         int ret;
99
100         ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
101                 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
102
103         return ret;
104 }
105
106 /*
107  * Cards with following subsystem_id have a link state indication
108  * problem, 600B, 600C, 600D, 640B, 640C and 640D.
109  * macro below identifies these cards given the subsystem_id.
110  */
111 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
112         (dev_type == XFRAME_I_DEVICE) ?                 \
113                 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
114                  ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
115
116 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
117                                       ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
118 #define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
119 #define PANIC   1
120 #define LOW     2
121 static inline int rx_buffer_level(struct s2io_nic * sp, int rxb_size, int ring)
122 {
123         struct mac_info *mac_control;
124
125         mac_control = &sp->mac_control;
126         if (rxb_size <= rxd_count[sp->rxd_mode])
127                 return PANIC;
128         else if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16)
129                 return  LOW;
130         return 0;
131 }
132
133 static inline int is_s2io_card_up(const struct s2io_nic * sp)
134 {
135         return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
136 }
137
138 /* Ethtool related variables and Macros. */
139 static char s2io_gstrings[][ETH_GSTRING_LEN] = {
140         "Register test\t(offline)",
141         "Eeprom test\t(offline)",
142         "Link test\t(online)",
143         "RLDRAM test\t(offline)",
144         "BIST Test\t(offline)"
145 };
146
147 static char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
148         {"tmac_frms"},
149         {"tmac_data_octets"},
150         {"tmac_drop_frms"},
151         {"tmac_mcst_frms"},
152         {"tmac_bcst_frms"},
153         {"tmac_pause_ctrl_frms"},
154         {"tmac_ttl_octets"},
155         {"tmac_ucst_frms"},
156         {"tmac_nucst_frms"},
157         {"tmac_any_err_frms"},
158         {"tmac_ttl_less_fb_octets"},
159         {"tmac_vld_ip_octets"},
160         {"tmac_vld_ip"},
161         {"tmac_drop_ip"},
162         {"tmac_icmp"},
163         {"tmac_rst_tcp"},
164         {"tmac_tcp"},
165         {"tmac_udp"},
166         {"rmac_vld_frms"},
167         {"rmac_data_octets"},
168         {"rmac_fcs_err_frms"},
169         {"rmac_drop_frms"},
170         {"rmac_vld_mcst_frms"},
171         {"rmac_vld_bcst_frms"},
172         {"rmac_in_rng_len_err_frms"},
173         {"rmac_out_rng_len_err_frms"},
174         {"rmac_long_frms"},
175         {"rmac_pause_ctrl_frms"},
176         {"rmac_unsup_ctrl_frms"},
177         {"rmac_ttl_octets"},
178         {"rmac_accepted_ucst_frms"},
179         {"rmac_accepted_nucst_frms"},
180         {"rmac_discarded_frms"},
181         {"rmac_drop_events"},
182         {"rmac_ttl_less_fb_octets"},
183         {"rmac_ttl_frms"},
184         {"rmac_usized_frms"},
185         {"rmac_osized_frms"},
186         {"rmac_frag_frms"},
187         {"rmac_jabber_frms"},
188         {"rmac_ttl_64_frms"},
189         {"rmac_ttl_65_127_frms"},
190         {"rmac_ttl_128_255_frms"},
191         {"rmac_ttl_256_511_frms"},
192         {"rmac_ttl_512_1023_frms"},
193         {"rmac_ttl_1024_1518_frms"},
194         {"rmac_ip"},
195         {"rmac_ip_octets"},
196         {"rmac_hdr_err_ip"},
197         {"rmac_drop_ip"},
198         {"rmac_icmp"},
199         {"rmac_tcp"},
200         {"rmac_udp"},
201         {"rmac_err_drp_udp"},
202         {"rmac_xgmii_err_sym"},
203         {"rmac_frms_q0"},
204         {"rmac_frms_q1"},
205         {"rmac_frms_q2"},
206         {"rmac_frms_q3"},
207         {"rmac_frms_q4"},
208         {"rmac_frms_q5"},
209         {"rmac_frms_q6"},
210         {"rmac_frms_q7"},
211         {"rmac_full_q0"},
212         {"rmac_full_q1"},
213         {"rmac_full_q2"},
214         {"rmac_full_q3"},
215         {"rmac_full_q4"},
216         {"rmac_full_q5"},
217         {"rmac_full_q6"},
218         {"rmac_full_q7"},
219         {"rmac_pause_cnt"},
220         {"rmac_xgmii_data_err_cnt"},
221         {"rmac_xgmii_ctrl_err_cnt"},
222         {"rmac_accepted_ip"},
223         {"rmac_err_tcp"},
224         {"rd_req_cnt"},
225         {"new_rd_req_cnt"},
226         {"new_rd_req_rtry_cnt"},
227         {"rd_rtry_cnt"},
228         {"wr_rtry_rd_ack_cnt"},
229         {"wr_req_cnt"},
230         {"new_wr_req_cnt"},
231         {"new_wr_req_rtry_cnt"},
232         {"wr_rtry_cnt"},
233         {"wr_disc_cnt"},
234         {"rd_rtry_wr_ack_cnt"},
235         {"txp_wr_cnt"},
236         {"txd_rd_cnt"},
237         {"txd_wr_cnt"},
238         {"rxd_rd_cnt"},
239         {"rxd_wr_cnt"},
240         {"txf_rd_cnt"},
241         {"rxf_wr_cnt"}
242 };
243
244 static char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
245         {"rmac_ttl_1519_4095_frms"},
246         {"rmac_ttl_4096_8191_frms"},
247         {"rmac_ttl_8192_max_frms"},
248         {"rmac_ttl_gt_max_frms"},
249         {"rmac_osized_alt_frms"},
250         {"rmac_jabber_alt_frms"},
251         {"rmac_gt_max_alt_frms"},
252         {"rmac_vlan_frms"},
253         {"rmac_len_discard"},
254         {"rmac_fcs_discard"},
255         {"rmac_pf_discard"},
256         {"rmac_da_discard"},
257         {"rmac_red_discard"},
258         {"rmac_rts_discard"},
259         {"rmac_ingm_full_discard"},
260         {"link_fault_cnt"}
261 };
262
263 static char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
264         {"\n DRIVER STATISTICS"},
265         {"single_bit_ecc_errs"},
266         {"double_bit_ecc_errs"},
267         {"parity_err_cnt"},
268         {"serious_err_cnt"},
269         {"soft_reset_cnt"},
270         {"fifo_full_cnt"},
271         {"ring_0_full_cnt"},
272         {"ring_1_full_cnt"},
273         {"ring_2_full_cnt"},
274         {"ring_3_full_cnt"},
275         {"ring_4_full_cnt"},
276         {"ring_5_full_cnt"},
277         {"ring_6_full_cnt"},
278         {"ring_7_full_cnt"},
279         {"alarm_transceiver_temp_high"},
280         {"alarm_transceiver_temp_low"},
281         {"alarm_laser_bias_current_high"},
282         {"alarm_laser_bias_current_low"},
283         {"alarm_laser_output_power_high"},
284         {"alarm_laser_output_power_low"},
285         {"warn_transceiver_temp_high"},
286         {"warn_transceiver_temp_low"},
287         {"warn_laser_bias_current_high"},
288         {"warn_laser_bias_current_low"},
289         {"warn_laser_output_power_high"},
290         {"warn_laser_output_power_low"},
291         {"lro_aggregated_pkts"},
292         {"lro_flush_both_count"},
293         {"lro_out_of_sequence_pkts"},
294         {"lro_flush_due_to_max_pkts"},
295         {"lro_avg_aggr_pkts"},
296         {"mem_alloc_fail_cnt"},
297         {"pci_map_fail_cnt"},
298         {"watchdog_timer_cnt"},
299         {"mem_allocated"},
300         {"mem_freed"},
301         {"link_up_cnt"},
302         {"link_down_cnt"},
303         {"link_up_time"},
304         {"link_down_time"},
305         {"tx_tcode_buf_abort_cnt"},
306         {"tx_tcode_desc_abort_cnt"},
307         {"tx_tcode_parity_err_cnt"},
308         {"tx_tcode_link_loss_cnt"},
309         {"tx_tcode_list_proc_err_cnt"},
310         {"rx_tcode_parity_err_cnt"},
311         {"rx_tcode_abort_cnt"},
312         {"rx_tcode_parity_abort_cnt"},
313         {"rx_tcode_rda_fail_cnt"},
314         {"rx_tcode_unkn_prot_cnt"},
315         {"rx_tcode_fcs_err_cnt"},
316         {"rx_tcode_buf_size_err_cnt"},
317         {"rx_tcode_rxd_corrupt_cnt"},
318         {"rx_tcode_unkn_err_cnt"},
319         {"tda_err_cnt"},
320         {"pfc_err_cnt"},
321         {"pcc_err_cnt"},
322         {"tti_err_cnt"},
323         {"tpa_err_cnt"},
324         {"sm_err_cnt"},
325         {"lso_err_cnt"},
326         {"mac_tmac_err_cnt"},
327         {"mac_rmac_err_cnt"},
328         {"xgxs_txgxs_err_cnt"},
329         {"xgxs_rxgxs_err_cnt"},
330         {"rc_err_cnt"},
331         {"prc_pcix_err_cnt"},
332         {"rpa_err_cnt"},
333         {"rda_err_cnt"},
334         {"rti_err_cnt"},
335         {"mc_err_cnt"}
336 };
337
338 #define S2IO_XENA_STAT_LEN sizeof(ethtool_xena_stats_keys)/ ETH_GSTRING_LEN
339 #define S2IO_ENHANCED_STAT_LEN sizeof(ethtool_enhanced_stats_keys)/ \
340                                         ETH_GSTRING_LEN
341 #define S2IO_DRIVER_STAT_LEN sizeof(ethtool_driver_stats_keys)/ ETH_GSTRING_LEN
342
343 #define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN )
344 #define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN )
345
346 #define XFRAME_I_STAT_STRINGS_LEN ( XFRAME_I_STAT_LEN * ETH_GSTRING_LEN )
347 #define XFRAME_II_STAT_STRINGS_LEN ( XFRAME_II_STAT_LEN * ETH_GSTRING_LEN )
348
349 #define S2IO_TEST_LEN   sizeof(s2io_gstrings) / ETH_GSTRING_LEN
350 #define S2IO_STRINGS_LEN        S2IO_TEST_LEN * ETH_GSTRING_LEN
351
352 #define S2IO_TIMER_CONF(timer, handle, arg, exp)                \
353                         init_timer(&timer);                     \
354                         timer.function = handle;                \
355                         timer.data = (unsigned long) arg;       \
356                         mod_timer(&timer, (jiffies + exp))      \
357
358 /* copy mac addr to def_mac_addr array */
359 static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
360 {
361         sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
362         sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
363         sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
364         sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
365         sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
366         sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
367 }
368 /* Add the vlan */
369 static void s2io_vlan_rx_register(struct net_device *dev,
370                                         struct vlan_group *grp)
371 {
372         struct s2io_nic *nic = dev->priv;
373         unsigned long flags;
374
375         spin_lock_irqsave(&nic->tx_lock, flags);
376         nic->vlgrp = grp;
377         spin_unlock_irqrestore(&nic->tx_lock, flags);
378 }
379
380 /* A flag indicating whether 'RX_PA_CFG_STRIP_VLAN_TAG' bit is set or not */
381 static int vlan_strip_flag;
382
383 /*
384  * Constants to be programmed into the Xena's registers, to configure
385  * the XAUI.
386  */
387
388 #define END_SIGN        0x0
389 static const u64 herc_act_dtx_cfg[] = {
390         /* Set address */
391         0x8000051536750000ULL, 0x80000515367500E0ULL,
392         /* Write data */
393         0x8000051536750004ULL, 0x80000515367500E4ULL,
394         /* Set address */
395         0x80010515003F0000ULL, 0x80010515003F00E0ULL,
396         /* Write data */
397         0x80010515003F0004ULL, 0x80010515003F00E4ULL,
398         /* Set address */
399         0x801205150D440000ULL, 0x801205150D4400E0ULL,
400         /* Write data */
401         0x801205150D440004ULL, 0x801205150D4400E4ULL,
402         /* Set address */
403         0x80020515F2100000ULL, 0x80020515F21000E0ULL,
404         /* Write data */
405         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
406         /* Done */
407         END_SIGN
408 };
409
410 static const u64 xena_dtx_cfg[] = {
411         /* Set address */
412         0x8000051500000000ULL, 0x80000515000000E0ULL,
413         /* Write data */
414         0x80000515D9350004ULL, 0x80000515D93500E4ULL,
415         /* Set address */
416         0x8001051500000000ULL, 0x80010515000000E0ULL,
417         /* Write data */
418         0x80010515001E0004ULL, 0x80010515001E00E4ULL,
419         /* Set address */
420         0x8002051500000000ULL, 0x80020515000000E0ULL,
421         /* Write data */
422         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
423         END_SIGN
424 };
425
426 /*
427  * Constants for Fixing the MacAddress problem seen mostly on
428  * Alpha machines.
429  */
430 static const u64 fix_mac[] = {
431         0x0060000000000000ULL, 0x0060600000000000ULL,
432         0x0040600000000000ULL, 0x0000600000000000ULL,
433         0x0020600000000000ULL, 0x0060600000000000ULL,
434         0x0020600000000000ULL, 0x0060600000000000ULL,
435         0x0020600000000000ULL, 0x0060600000000000ULL,
436         0x0020600000000000ULL, 0x0060600000000000ULL,
437         0x0020600000000000ULL, 0x0060600000000000ULL,
438         0x0020600000000000ULL, 0x0060600000000000ULL,
439         0x0020600000000000ULL, 0x0060600000000000ULL,
440         0x0020600000000000ULL, 0x0060600000000000ULL,
441         0x0020600000000000ULL, 0x0060600000000000ULL,
442         0x0020600000000000ULL, 0x0060600000000000ULL,
443         0x0020600000000000ULL, 0x0000600000000000ULL,
444         0x0040600000000000ULL, 0x0060600000000000ULL,
445         END_SIGN
446 };
447
448 MODULE_LICENSE("GPL");
449 MODULE_VERSION(DRV_VERSION);
450
451
452 /* Module Loadable parameters. */
453 S2IO_PARM_INT(tx_fifo_num, 1);
454 S2IO_PARM_INT(rx_ring_num, 1);
455
456
457 S2IO_PARM_INT(rx_ring_mode, 1);
458 S2IO_PARM_INT(use_continuous_tx_intrs, 1);
459 S2IO_PARM_INT(rmac_pause_time, 0x100);
460 S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
461 S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
462 S2IO_PARM_INT(shared_splits, 0);
463 S2IO_PARM_INT(tmac_util_period, 5);
464 S2IO_PARM_INT(rmac_util_period, 5);
465 S2IO_PARM_INT(l3l4hdr_size, 128);
466 /* Frequency of Rx desc syncs expressed as power of 2 */
467 S2IO_PARM_INT(rxsync_frequency, 3);
468 /* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
469 S2IO_PARM_INT(intr_type, 2);
470 /* Large receive offload feature */
471 static unsigned int lro_enable;
472 module_param_named(lro, lro_enable, uint, 0);
473
474 /* Max pkts to be aggregated by LRO at one time. If not specified,
475  * aggregation happens until we hit max IP pkt size(64K)
476  */
477 S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
478 S2IO_PARM_INT(indicate_max_pkts, 0);
479
480 S2IO_PARM_INT(napi, 1);
481 S2IO_PARM_INT(ufo, 0);
482 S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
483
484 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
485     {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
486 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
487     {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
488 static unsigned int rts_frm_len[MAX_RX_RINGS] =
489     {[0 ...(MAX_RX_RINGS - 1)] = 0 };
490
491 module_param_array(tx_fifo_len, uint, NULL, 0);
492 module_param_array(rx_ring_sz, uint, NULL, 0);
493 module_param_array(rts_frm_len, uint, NULL, 0);
494
495 /*
496  * S2IO device table.
497  * This table lists all the devices that this driver supports.
498  */
499 static struct pci_device_id s2io_tbl[] __devinitdata = {
500         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
501          PCI_ANY_ID, PCI_ANY_ID},
502         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
503          PCI_ANY_ID, PCI_ANY_ID},
504         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
505          PCI_ANY_ID, PCI_ANY_ID},
506         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
507          PCI_ANY_ID, PCI_ANY_ID},
508         {0,}
509 };
510
511 MODULE_DEVICE_TABLE(pci, s2io_tbl);
512
513 static struct pci_error_handlers s2io_err_handler = {
514         .error_detected = s2io_io_error_detected,
515         .slot_reset = s2io_io_slot_reset,
516         .resume = s2io_io_resume,
517 };
518
519 static struct pci_driver s2io_driver = {
520       .name = "S2IO",
521       .id_table = s2io_tbl,
522       .probe = s2io_init_nic,
523       .remove = __devexit_p(s2io_rem_nic),
524       .err_handler = &s2io_err_handler,
525 };
526
527 /* A simplifier macro used both by init and free shared_mem Fns(). */
528 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
529
530 /**
531  * init_shared_mem - Allocation and Initialization of Memory
532  * @nic: Device private variable.
533  * Description: The function allocates all the memory areas shared
534  * between the NIC and the driver. This includes Tx descriptors,
535  * Rx descriptors and the statistics block.
536  */
537
538 static int init_shared_mem(struct s2io_nic *nic)
539 {
540         u32 size;
541         void *tmp_v_addr, *tmp_v_addr_next;
542         dma_addr_t tmp_p_addr, tmp_p_addr_next;
543         struct RxD_block *pre_rxd_blk = NULL;
544         int i, j, blk_cnt;
545         int lst_size, lst_per_page;
546         struct net_device *dev = nic->dev;
547         unsigned long tmp;
548         struct buffAdd *ba;
549
550         struct mac_info *mac_control;
551         struct config_param *config;
552         unsigned long long mem_allocated = 0;
553
554         mac_control = &nic->mac_control;
555         config = &nic->config;
556
557
558         /* Allocation and initialization of TXDLs in FIOFs */
559         size = 0;
560         for (i = 0; i < config->tx_fifo_num; i++) {
561                 size += config->tx_cfg[i].fifo_len;
562         }
563         if (size > MAX_AVAILABLE_TXDS) {
564                 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
565                 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
566                 return -EINVAL;
567         }
568
569         lst_size = (sizeof(struct TxD) * config->max_txds);
570         lst_per_page = PAGE_SIZE / lst_size;
571
572         for (i = 0; i < config->tx_fifo_num; i++) {
573                 int fifo_len = config->tx_cfg[i].fifo_len;
574                 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
575                 mac_control->fifos[i].list_info = kzalloc(list_holder_size,
576                                                           GFP_KERNEL);
577                 if (!mac_control->fifos[i].list_info) {
578                         DBG_PRINT(INFO_DBG,
579                                   "Malloc failed for list_info\n");
580                         return -ENOMEM;
581                 }
582                 mem_allocated += list_holder_size;
583         }
584         for (i = 0; i < config->tx_fifo_num; i++) {
585                 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
586                                                 lst_per_page);
587                 mac_control->fifos[i].tx_curr_put_info.offset = 0;
588                 mac_control->fifos[i].tx_curr_put_info.fifo_len =
589                     config->tx_cfg[i].fifo_len - 1;
590                 mac_control->fifos[i].tx_curr_get_info.offset = 0;
591                 mac_control->fifos[i].tx_curr_get_info.fifo_len =
592                     config->tx_cfg[i].fifo_len - 1;
593                 mac_control->fifos[i].fifo_no = i;
594                 mac_control->fifos[i].nic = nic;
595                 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
596
597                 for (j = 0; j < page_num; j++) {
598                         int k = 0;
599                         dma_addr_t tmp_p;
600                         void *tmp_v;
601                         tmp_v = pci_alloc_consistent(nic->pdev,
602                                                      PAGE_SIZE, &tmp_p);
603                         if (!tmp_v) {
604                                 DBG_PRINT(INFO_DBG,
605                                           "pci_alloc_consistent ");
606                                 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
607                                 return -ENOMEM;
608                         }
609                         /* If we got a zero DMA address(can happen on
610                          * certain platforms like PPC), reallocate.
611                          * Store virtual address of page we don't want,
612                          * to be freed later.
613                          */
614                         if (!tmp_p) {
615                                 mac_control->zerodma_virt_addr = tmp_v;
616                                 DBG_PRINT(INIT_DBG,
617                                 "%s: Zero DMA address for TxDL. ", dev->name);
618                                 DBG_PRINT(INIT_DBG,
619                                 "Virtual address %p\n", tmp_v);
620                                 tmp_v = pci_alloc_consistent(nic->pdev,
621                                                      PAGE_SIZE, &tmp_p);
622                                 if (!tmp_v) {
623                                         DBG_PRINT(INFO_DBG,
624                                           "pci_alloc_consistent ");
625                                         DBG_PRINT(INFO_DBG, "failed for TxDL\n");
626                                         return -ENOMEM;
627                                 }
628                                 mem_allocated += PAGE_SIZE;
629                         }
630                         while (k < lst_per_page) {
631                                 int l = (j * lst_per_page) + k;
632                                 if (l == config->tx_cfg[i].fifo_len)
633                                         break;
634                                 mac_control->fifos[i].list_info[l].list_virt_addr =
635                                     tmp_v + (k * lst_size);
636                                 mac_control->fifos[i].list_info[l].list_phy_addr =
637                                     tmp_p + (k * lst_size);
638                                 k++;
639                         }
640                 }
641         }
642
643         nic->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
644         if (!nic->ufo_in_band_v)
645                 return -ENOMEM;
646          mem_allocated += (size * sizeof(u64));
647
648         /* Allocation and initialization of RXDs in Rings */
649         size = 0;
650         for (i = 0; i < config->rx_ring_num; i++) {
651                 if (config->rx_cfg[i].num_rxd %
652                     (rxd_count[nic->rxd_mode] + 1)) {
653                         DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
654                         DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
655                                   i);
656                         DBG_PRINT(ERR_DBG, "RxDs per Block");
657                         return FAILURE;
658                 }
659                 size += config->rx_cfg[i].num_rxd;
660                 mac_control->rings[i].block_count =
661                         config->rx_cfg[i].num_rxd /
662                         (rxd_count[nic->rxd_mode] + 1 );
663                 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
664                         mac_control->rings[i].block_count;
665         }
666         if (nic->rxd_mode == RXD_MODE_1)
667                 size = (size * (sizeof(struct RxD1)));
668         else
669                 size = (size * (sizeof(struct RxD3)));
670
671         for (i = 0; i < config->rx_ring_num; i++) {
672                 mac_control->rings[i].rx_curr_get_info.block_index = 0;
673                 mac_control->rings[i].rx_curr_get_info.offset = 0;
674                 mac_control->rings[i].rx_curr_get_info.ring_len =
675                     config->rx_cfg[i].num_rxd - 1;
676                 mac_control->rings[i].rx_curr_put_info.block_index = 0;
677                 mac_control->rings[i].rx_curr_put_info.offset = 0;
678                 mac_control->rings[i].rx_curr_put_info.ring_len =
679                     config->rx_cfg[i].num_rxd - 1;
680                 mac_control->rings[i].nic = nic;
681                 mac_control->rings[i].ring_no = i;
682
683                 blk_cnt = config->rx_cfg[i].num_rxd /
684                                 (rxd_count[nic->rxd_mode] + 1);
685                 /*  Allocating all the Rx blocks */
686                 for (j = 0; j < blk_cnt; j++) {
687                         struct rx_block_info *rx_blocks;
688                         int l;
689
690                         rx_blocks = &mac_control->rings[i].rx_blocks[j];
691                         size = SIZE_OF_BLOCK; //size is always page size
692                         tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
693                                                           &tmp_p_addr);
694                         if (tmp_v_addr == NULL) {
695                                 /*
696                                  * In case of failure, free_shared_mem()
697                                  * is called, which should free any
698                                  * memory that was alloced till the
699                                  * failure happened.
700                                  */
701                                 rx_blocks->block_virt_addr = tmp_v_addr;
702                                 return -ENOMEM;
703                         }
704                         mem_allocated += size;
705                         memset(tmp_v_addr, 0, size);
706                         rx_blocks->block_virt_addr = tmp_v_addr;
707                         rx_blocks->block_dma_addr = tmp_p_addr;
708                         rx_blocks->rxds = kmalloc(sizeof(struct rxd_info)*
709                                                   rxd_count[nic->rxd_mode],
710                                                   GFP_KERNEL);
711                         if (!rx_blocks->rxds)
712                                 return -ENOMEM;
713                         mem_allocated +=
714                         (sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
715                         for (l=0; l<rxd_count[nic->rxd_mode];l++) {
716                                 rx_blocks->rxds[l].virt_addr =
717                                         rx_blocks->block_virt_addr +
718                                         (rxd_size[nic->rxd_mode] * l);
719                                 rx_blocks->rxds[l].dma_addr =
720                                         rx_blocks->block_dma_addr +
721                                         (rxd_size[nic->rxd_mode] * l);
722                         }
723                 }
724                 /* Interlinking all Rx Blocks */
725                 for (j = 0; j < blk_cnt; j++) {
726                         tmp_v_addr =
727                                 mac_control->rings[i].rx_blocks[j].block_virt_addr;
728                         tmp_v_addr_next =
729                                 mac_control->rings[i].rx_blocks[(j + 1) %
730                                               blk_cnt].block_virt_addr;
731                         tmp_p_addr =
732                                 mac_control->rings[i].rx_blocks[j].block_dma_addr;
733                         tmp_p_addr_next =
734                                 mac_control->rings[i].rx_blocks[(j + 1) %
735                                               blk_cnt].block_dma_addr;
736
737                         pre_rxd_blk = (struct RxD_block *) tmp_v_addr;
738                         pre_rxd_blk->reserved_2_pNext_RxD_block =
739                             (unsigned long) tmp_v_addr_next;
740                         pre_rxd_blk->pNext_RxD_Blk_physical =
741                             (u64) tmp_p_addr_next;
742                 }
743         }
744         if (nic->rxd_mode == RXD_MODE_3B) {
745                 /*
746                  * Allocation of Storages for buffer addresses in 2BUFF mode
747                  * and the buffers as well.
748                  */
749                 for (i = 0; i < config->rx_ring_num; i++) {
750                         blk_cnt = config->rx_cfg[i].num_rxd /
751                            (rxd_count[nic->rxd_mode]+ 1);
752                         mac_control->rings[i].ba =
753                                 kmalloc((sizeof(struct buffAdd *) * blk_cnt),
754                                      GFP_KERNEL);
755                         if (!mac_control->rings[i].ba)
756                                 return -ENOMEM;
757                         mem_allocated +=(sizeof(struct buffAdd *) * blk_cnt);
758                         for (j = 0; j < blk_cnt; j++) {
759                                 int k = 0;
760                                 mac_control->rings[i].ba[j] =
761                                         kmalloc((sizeof(struct buffAdd) *
762                                                 (rxd_count[nic->rxd_mode] + 1)),
763                                                 GFP_KERNEL);
764                                 if (!mac_control->rings[i].ba[j])
765                                         return -ENOMEM;
766                                 mem_allocated += (sizeof(struct buffAdd) *  \
767                                         (rxd_count[nic->rxd_mode] + 1));
768                                 while (k != rxd_count[nic->rxd_mode]) {
769                                         ba = &mac_control->rings[i].ba[j][k];
770
771                                         ba->ba_0_org = (void *) kmalloc
772                                             (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
773                                         if (!ba->ba_0_org)
774                                                 return -ENOMEM;
775                                         mem_allocated +=
776                                                 (BUF0_LEN + ALIGN_SIZE);
777                                         tmp = (unsigned long)ba->ba_0_org;
778                                         tmp += ALIGN_SIZE;
779                                         tmp &= ~((unsigned long) ALIGN_SIZE);
780                                         ba->ba_0 = (void *) tmp;
781
782                                         ba->ba_1_org = (void *) kmalloc
783                                             (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
784                                         if (!ba->ba_1_org)
785                                                 return -ENOMEM;
786                                         mem_allocated
787                                                 += (BUF1_LEN + ALIGN_SIZE);
788                                         tmp = (unsigned long) ba->ba_1_org;
789                                         tmp += ALIGN_SIZE;
790                                         tmp &= ~((unsigned long) ALIGN_SIZE);
791                                         ba->ba_1 = (void *) tmp;
792                                         k++;
793                                 }
794                         }
795                 }
796         }
797
798         /* Allocation and initialization of Statistics block */
799         size = sizeof(struct stat_block);
800         mac_control->stats_mem = pci_alloc_consistent
801             (nic->pdev, size, &mac_control->stats_mem_phy);
802
803         if (!mac_control->stats_mem) {
804                 /*
805                  * In case of failure, free_shared_mem() is called, which
806                  * should free any memory that was alloced till the
807                  * failure happened.
808                  */
809                 return -ENOMEM;
810         }
811         mem_allocated += size;
812         mac_control->stats_mem_sz = size;
813
814         tmp_v_addr = mac_control->stats_mem;
815         mac_control->stats_info = (struct stat_block *) tmp_v_addr;
816         memset(tmp_v_addr, 0, size);
817         DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
818                   (unsigned long long) tmp_p_addr);
819         mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
820         return SUCCESS;
821 }
822
823 /**
824  * free_shared_mem - Free the allocated Memory
825  * @nic:  Device private variable.
826  * Description: This function is to free all memory locations allocated by
827  * the init_shared_mem() function and return it to the kernel.
828  */
829
830 static void free_shared_mem(struct s2io_nic *nic)
831 {
832         int i, j, blk_cnt, size;
833         u32 ufo_size = 0;
834         void *tmp_v_addr;
835         dma_addr_t tmp_p_addr;
836         struct mac_info *mac_control;
837         struct config_param *config;
838         int lst_size, lst_per_page;
839         struct net_device *dev;
840         int page_num = 0;
841
842         if (!nic)
843                 return;
844
845         dev = nic->dev;
846
847         mac_control = &nic->mac_control;
848         config = &nic->config;
849
850         lst_size = (sizeof(struct TxD) * config->max_txds);
851         lst_per_page = PAGE_SIZE / lst_size;
852
853         for (i = 0; i < config->tx_fifo_num; i++) {
854                 ufo_size += config->tx_cfg[i].fifo_len;
855                 page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
856                                                         lst_per_page);
857                 for (j = 0; j < page_num; j++) {
858                         int mem_blks = (j * lst_per_page);
859                         if (!mac_control->fifos[i].list_info)
860                                 return;
861                         if (!mac_control->fifos[i].list_info[mem_blks].
862                                  list_virt_addr)
863                                 break;
864                         pci_free_consistent(nic->pdev, PAGE_SIZE,
865                                             mac_control->fifos[i].
866                                             list_info[mem_blks].
867                                             list_virt_addr,
868                                             mac_control->fifos[i].
869                                             list_info[mem_blks].
870                                             list_phy_addr);
871                         nic->mac_control.stats_info->sw_stat.mem_freed
872                                                 += PAGE_SIZE;
873                 }
874                 /* If we got a zero DMA address during allocation,
875                  * free the page now
876                  */
877                 if (mac_control->zerodma_virt_addr) {
878                         pci_free_consistent(nic->pdev, PAGE_SIZE,
879                                             mac_control->zerodma_virt_addr,
880                                             (dma_addr_t)0);
881                         DBG_PRINT(INIT_DBG,
882                                 "%s: Freeing TxDL with zero DMA addr. ",
883                                 dev->name);
884                         DBG_PRINT(INIT_DBG, "Virtual address %p\n",
885                                 mac_control->zerodma_virt_addr);
886                         nic->mac_control.stats_info->sw_stat.mem_freed
887                                                 += PAGE_SIZE;
888                 }
889                 kfree(mac_control->fifos[i].list_info);
890                 nic->mac_control.stats_info->sw_stat.mem_freed +=
891                 (nic->config.tx_cfg[i].fifo_len *sizeof(struct list_info_hold));
892         }
893
894         size = SIZE_OF_BLOCK;
895         for (i = 0; i < config->rx_ring_num; i++) {
896                 blk_cnt = mac_control->rings[i].block_count;
897                 for (j = 0; j < blk_cnt; j++) {
898                         tmp_v_addr = mac_control->rings[i].rx_blocks[j].
899                                 block_virt_addr;
900                         tmp_p_addr = mac_control->rings[i].rx_blocks[j].
901                                 block_dma_addr;
902                         if (tmp_v_addr == NULL)
903                                 break;
904                         pci_free_consistent(nic->pdev, size,
905                                             tmp_v_addr, tmp_p_addr);
906                         nic->mac_control.stats_info->sw_stat.mem_freed += size;
907                         kfree(mac_control->rings[i].rx_blocks[j].rxds);
908                         nic->mac_control.stats_info->sw_stat.mem_freed +=
909                         ( sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
910                 }
911         }
912
913         if (nic->rxd_mode == RXD_MODE_3B) {
914                 /* Freeing buffer storage addresses in 2BUFF mode. */
915                 for (i = 0; i < config->rx_ring_num; i++) {
916                         blk_cnt = config->rx_cfg[i].num_rxd /
917                             (rxd_count[nic->rxd_mode] + 1);
918                         for (j = 0; j < blk_cnt; j++) {
919                                 int k = 0;
920                                 if (!mac_control->rings[i].ba[j])
921                                         continue;
922                                 while (k != rxd_count[nic->rxd_mode]) {
923                                         struct buffAdd *ba =
924                                                 &mac_control->rings[i].ba[j][k];
925                                         kfree(ba->ba_0_org);
926                                         nic->mac_control.stats_info->sw_stat.\
927                                         mem_freed += (BUF0_LEN + ALIGN_SIZE);
928                                         kfree(ba->ba_1_org);
929                                         nic->mac_control.stats_info->sw_stat.\
930                                         mem_freed += (BUF1_LEN + ALIGN_SIZE);
931                                         k++;
932                                 }
933                                 kfree(mac_control->rings[i].ba[j]);
934                                 nic->mac_control.stats_info->sw_stat.mem_freed +=
935                                         (sizeof(struct buffAdd) *
936                                         (rxd_count[nic->rxd_mode] + 1));
937                         }
938                         kfree(mac_control->rings[i].ba);
939                         nic->mac_control.stats_info->sw_stat.mem_freed +=
940                         (sizeof(struct buffAdd *) * blk_cnt);
941                 }
942         }
943
944         if (mac_control->stats_mem) {
945                 pci_free_consistent(nic->pdev,
946                                     mac_control->stats_mem_sz,
947                                     mac_control->stats_mem,
948                                     mac_control->stats_mem_phy);
949                 nic->mac_control.stats_info->sw_stat.mem_freed +=
950                         mac_control->stats_mem_sz;
951         }
952         if (nic->ufo_in_band_v) {
953                 kfree(nic->ufo_in_band_v);
954                 nic->mac_control.stats_info->sw_stat.mem_freed
955                         += (ufo_size * sizeof(u64));
956         }
957 }
958
959 /**
960  * s2io_verify_pci_mode -
961  */
962
963 static int s2io_verify_pci_mode(struct s2io_nic *nic)
964 {
965         struct XENA_dev_config __iomem *bar0 = nic->bar0;
966         register u64 val64 = 0;
967         int     mode;
968
969         val64 = readq(&bar0->pci_mode);
970         mode = (u8)GET_PCI_MODE(val64);
971
972         if ( val64 & PCI_MODE_UNKNOWN_MODE)
973                 return -1;      /* Unknown PCI mode */
974         return mode;
975 }
976
977 #define NEC_VENID   0x1033
978 #define NEC_DEVID   0x0125
979 static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
980 {
981         struct pci_dev *tdev = NULL;
982         while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
983                 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
984                         if (tdev->bus == s2io_pdev->bus->parent)
985                                 pci_dev_put(tdev);
986                                 return 1;
987                 }
988         }
989         return 0;
990 }
991
992 static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
993 /**
994  * s2io_print_pci_mode -
995  */
996 static int s2io_print_pci_mode(struct s2io_nic *nic)
997 {
998         struct XENA_dev_config __iomem *bar0 = nic->bar0;
999         register u64 val64 = 0;
1000         int     mode;
1001         struct config_param *config = &nic->config;
1002
1003         val64 = readq(&bar0->pci_mode);
1004         mode = (u8)GET_PCI_MODE(val64);
1005
1006         if ( val64 & PCI_MODE_UNKNOWN_MODE)
1007                 return -1;      /* Unknown PCI mode */
1008
1009         config->bus_speed = bus_speed[mode];
1010
1011         if (s2io_on_nec_bridge(nic->pdev)) {
1012                 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
1013                                                         nic->dev->name);
1014                 return mode;
1015         }
1016
1017         if (val64 & PCI_MODE_32_BITS) {
1018                 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
1019         } else {
1020                 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
1021         }
1022
1023         switch(mode) {
1024                 case PCI_MODE_PCI_33:
1025                         DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
1026                         break;
1027                 case PCI_MODE_PCI_66:
1028                         DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
1029                         break;
1030                 case PCI_MODE_PCIX_M1_66:
1031                         DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
1032                         break;
1033                 case PCI_MODE_PCIX_M1_100:
1034                         DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
1035                         break;
1036                 case PCI_MODE_PCIX_M1_133:
1037                         DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
1038                         break;
1039                 case PCI_MODE_PCIX_M2_66:
1040                         DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
1041                         break;
1042                 case PCI_MODE_PCIX_M2_100:
1043                         DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
1044                         break;
1045                 case PCI_MODE_PCIX_M2_133:
1046                         DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
1047                         break;
1048                 default:
1049                         return -1;      /* Unsupported bus speed */
1050         }
1051
1052         return mode;
1053 }
1054
1055 /**
1056  *  init_nic - Initialization of hardware
1057  *  @nic: device peivate variable
1058  *  Description: The function sequentially configures every block
1059  *  of the H/W from their reset values.
1060  *  Return Value:  SUCCESS on success and
1061  *  '-1' on failure (endian settings incorrect).
1062  */
1063
1064 static int init_nic(struct s2io_nic *nic)
1065 {
1066         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1067         struct net_device *dev = nic->dev;
1068         register u64 val64 = 0;
1069         void __iomem *add;
1070         u32 time;
1071         int i, j;
1072         struct mac_info *mac_control;
1073         struct config_param *config;
1074         int dtx_cnt = 0;
1075         unsigned long long mem_share;
1076         int mem_size;
1077
1078         mac_control = &nic->mac_control;
1079         config = &nic->config;
1080
1081         /* to set the swapper controle on the card */
1082         if(s2io_set_swapper(nic)) {
1083                 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
1084                 return -1;
1085         }
1086
1087         /*
1088          * Herc requires EOI to be removed from reset before XGXS, so..
1089          */
1090         if (nic->device_type & XFRAME_II_DEVICE) {
1091                 val64 = 0xA500000000ULL;
1092                 writeq(val64, &bar0->sw_reset);
1093                 msleep(500);
1094                 val64 = readq(&bar0->sw_reset);
1095         }
1096
1097         /* Remove XGXS from reset state */
1098         val64 = 0;
1099         writeq(val64, &bar0->sw_reset);
1100         msleep(500);
1101         val64 = readq(&bar0->sw_reset);
1102
1103         /*  Enable Receiving broadcasts */
1104         add = &bar0->mac_cfg;
1105         val64 = readq(&bar0->mac_cfg);
1106         val64 |= MAC_RMAC_BCAST_ENABLE;
1107         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1108         writel((u32) val64, add);
1109         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1110         writel((u32) (val64 >> 32), (add + 4));
1111
1112         /* Read registers in all blocks */
1113         val64 = readq(&bar0->mac_int_mask);
1114         val64 = readq(&bar0->mc_int_mask);
1115         val64 = readq(&bar0->xgxs_int_mask);
1116
1117         /*  Set MTU */
1118         val64 = dev->mtu;
1119         writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1120
1121         if (nic->device_type & XFRAME_II_DEVICE) {
1122                 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
1123                         SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1124                                           &bar0->dtx_control, UF);
1125                         if (dtx_cnt & 0x1)
1126                                 msleep(1); /* Necessary!! */
1127                         dtx_cnt++;
1128                 }
1129         } else {
1130                 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1131                         SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1132                                           &bar0->dtx_control, UF);
1133                         val64 = readq(&bar0->dtx_control);
1134                         dtx_cnt++;
1135                 }
1136         }
1137
1138         /*  Tx DMA Initialization */
1139         val64 = 0;
1140         writeq(val64, &bar0->tx_fifo_partition_0);
1141         writeq(val64, &bar0->tx_fifo_partition_1);
1142         writeq(val64, &bar0->tx_fifo_partition_2);
1143         writeq(val64, &bar0->tx_fifo_partition_3);
1144
1145
1146         for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1147                 val64 |=
1148                     vBIT(config->tx_cfg[i].fifo_len - 1, ((i * 32) + 19),
1149                          13) | vBIT(config->tx_cfg[i].fifo_priority,
1150                                     ((i * 32) + 5), 3);
1151
1152                 if (i == (config->tx_fifo_num - 1)) {
1153                         if (i % 2 == 0)
1154                                 i++;
1155                 }
1156
1157                 switch (i) {
1158                 case 1:
1159                         writeq(val64, &bar0->tx_fifo_partition_0);
1160                         val64 = 0;
1161                         break;
1162                 case 3:
1163                         writeq(val64, &bar0->tx_fifo_partition_1);
1164                         val64 = 0;
1165                         break;
1166                 case 5:
1167                         writeq(val64, &bar0->tx_fifo_partition_2);
1168                         val64 = 0;
1169                         break;
1170                 case 7:
1171                         writeq(val64, &bar0->tx_fifo_partition_3);
1172                         break;
1173                 }
1174         }
1175
1176         /*
1177          * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1178          * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1179          */
1180         if ((nic->device_type == XFRAME_I_DEVICE) &&
1181                 (nic->pdev->revision < 4))
1182                 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1183
1184         val64 = readq(&bar0->tx_fifo_partition_0);
1185         DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1186                   &bar0->tx_fifo_partition_0, (unsigned long long) val64);
1187
1188         /*
1189          * Initialization of Tx_PA_CONFIG register to ignore packet
1190          * integrity checking.
1191          */
1192         val64 = readq(&bar0->tx_pa_cfg);
1193         val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1194             TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1195         writeq(val64, &bar0->tx_pa_cfg);
1196
1197         /* Rx DMA intialization. */
1198         val64 = 0;
1199         for (i = 0; i < config->rx_ring_num; i++) {
1200                 val64 |=
1201                     vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
1202                          3);
1203         }
1204         writeq(val64, &bar0->rx_queue_priority);
1205
1206         /*
1207          * Allocating equal share of memory to all the
1208          * configured Rings.
1209          */
1210         val64 = 0;
1211         if (nic->device_type & XFRAME_II_DEVICE)
1212                 mem_size = 32;
1213         else
1214                 mem_size = 64;
1215
1216         for (i = 0; i < config->rx_ring_num; i++) {
1217                 switch (i) {
1218                 case 0:
1219                         mem_share = (mem_size / config->rx_ring_num +
1220                                      mem_size % config->rx_ring_num);
1221                         val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1222                         continue;
1223                 case 1:
1224                         mem_share = (mem_size / config->rx_ring_num);
1225                         val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1226                         continue;
1227                 case 2:
1228                         mem_share = (mem_size / config->rx_ring_num);
1229                         val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1230                         continue;
1231                 case 3:
1232                         mem_share = (mem_size / config->rx_ring_num);
1233                         val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1234                         continue;
1235                 case 4:
1236                         mem_share = (mem_size / config->rx_ring_num);
1237                         val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1238                         continue;
1239                 case 5:
1240                         mem_share = (mem_size / config->rx_ring_num);
1241                         val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1242                         continue;
1243                 case 6:
1244                         mem_share = (mem_size / config->rx_ring_num);
1245                         val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1246                         continue;
1247                 case 7:
1248                         mem_share = (mem_size / config->rx_ring_num);
1249                         val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1250                         continue;
1251                 }
1252         }
1253         writeq(val64, &bar0->rx_queue_cfg);
1254
1255         /*
1256          * Filling Tx round robin registers
1257          * as per the number of FIFOs
1258          */
1259         switch (config->tx_fifo_num) {
1260         case 1:
1261                 val64 = 0x0000000000000000ULL;
1262                 writeq(val64, &bar0->tx_w_round_robin_0);
1263                 writeq(val64, &bar0->tx_w_round_robin_1);
1264                 writeq(val64, &bar0->tx_w_round_robin_2);
1265                 writeq(val64, &bar0->tx_w_round_robin_3);
1266                 writeq(val64, &bar0->tx_w_round_robin_4);
1267                 break;
1268         case 2:
1269                 val64 = 0x0000010000010000ULL;
1270                 writeq(val64, &bar0->tx_w_round_robin_0);
1271                 val64 = 0x0100000100000100ULL;
1272                 writeq(val64, &bar0->tx_w_round_robin_1);
1273                 val64 = 0x0001000001000001ULL;
1274                 writeq(val64, &bar0->tx_w_round_robin_2);
1275                 val64 = 0x0000010000010000ULL;
1276                 writeq(val64, &bar0->tx_w_round_robin_3);
1277                 val64 = 0x0100000000000000ULL;
1278                 writeq(val64, &bar0->tx_w_round_robin_4);
1279                 break;
1280         case 3:
1281                 val64 = 0x0001000102000001ULL;
1282                 writeq(val64, &bar0->tx_w_round_robin_0);
1283                 val64 = 0x0001020000010001ULL;
1284                 writeq(val64, &bar0->tx_w_round_robin_1);
1285                 val64 = 0x0200000100010200ULL;
1286                 writeq(val64, &bar0->tx_w_round_robin_2);
1287                 val64 = 0x0001000102000001ULL;
1288                 writeq(val64, &bar0->tx_w_round_robin_3);
1289                 val64 = 0x0001020000000000ULL;
1290                 writeq(val64, &bar0->tx_w_round_robin_4);
1291                 break;
1292         case 4:
1293                 val64 = 0x0001020300010200ULL;
1294                 writeq(val64, &bar0->tx_w_round_robin_0);
1295                 val64 = 0x0100000102030001ULL;
1296                 writeq(val64, &bar0->tx_w_round_robin_1);
1297                 val64 = 0x0200010000010203ULL;
1298                 writeq(val64, &bar0->tx_w_round_robin_2);
1299                 val64 = 0x0001020001000001ULL;
1300                 writeq(val64, &bar0->tx_w_round_robin_3);
1301                 val64 = 0x0203000100000000ULL;
1302                 writeq(val64, &bar0->tx_w_round_robin_4);
1303                 break;
1304         case 5:
1305                 val64 = 0x0001000203000102ULL;
1306                 writeq(val64, &bar0->tx_w_round_robin_0);
1307                 val64 = 0x0001020001030004ULL;
1308                 writeq(val64, &bar0->tx_w_round_robin_1);
1309                 val64 = 0x0001000203000102ULL;
1310                 writeq(val64, &bar0->tx_w_round_robin_2);
1311                 val64 = 0x0001020001030004ULL;
1312                 writeq(val64, &bar0->tx_w_round_robin_3);
1313                 val64 = 0x0001000000000000ULL;
1314                 writeq(val64, &bar0->tx_w_round_robin_4);
1315                 break;
1316         case 6:
1317                 val64 = 0x0001020304000102ULL;
1318                 writeq(val64, &bar0->tx_w_round_robin_0);
1319                 val64 = 0x0304050001020001ULL;
1320                 writeq(val64, &bar0->tx_w_round_robin_1);
1321                 val64 = 0x0203000100000102ULL;
1322                 writeq(val64, &bar0->tx_w_round_robin_2);
1323                 val64 = 0x0304000102030405ULL;
1324                 writeq(val64, &bar0->tx_w_round_robin_3);
1325                 val64 = 0x0001000200000000ULL;
1326                 writeq(val64, &bar0->tx_w_round_robin_4);
1327                 break;
1328         case 7:
1329                 val64 = 0x0001020001020300ULL;
1330                 writeq(val64, &bar0->tx_w_round_robin_0);
1331                 val64 = 0x0102030400010203ULL;
1332                 writeq(val64, &bar0->tx_w_round_robin_1);
1333                 val64 = 0x0405060001020001ULL;
1334                 writeq(val64, &bar0->tx_w_round_robin_2);
1335                 val64 = 0x0304050000010200ULL;
1336                 writeq(val64, &bar0->tx_w_round_robin_3);
1337                 val64 = 0x0102030000000000ULL;
1338                 writeq(val64, &bar0->tx_w_round_robin_4);
1339                 break;
1340         case 8:
1341                 val64 = 0x0001020300040105ULL;
1342                 writeq(val64, &bar0->tx_w_round_robin_0);
1343                 val64 = 0x0200030106000204ULL;
1344                 writeq(val64, &bar0->tx_w_round_robin_1);
1345                 val64 = 0x0103000502010007ULL;
1346                 writeq(val64, &bar0->tx_w_round_robin_2);
1347                 val64 = 0x0304010002060500ULL;
1348                 writeq(val64, &bar0->tx_w_round_robin_3);
1349                 val64 = 0x0103020400000000ULL;
1350                 writeq(val64, &bar0->tx_w_round_robin_4);
1351                 break;
1352         }
1353
1354         /* Enable all configured Tx FIFO partitions */
1355         val64 = readq(&bar0->tx_fifo_partition_0);
1356         val64 |= (TX_FIFO_PARTITION_EN);
1357         writeq(val64, &bar0->tx_fifo_partition_0);
1358
1359         /* Filling the Rx round robin registers as per the
1360          * number of Rings and steering based on QoS.
1361          */
1362         switch (config->rx_ring_num) {
1363         case 1:
1364                 val64 = 0x8080808080808080ULL;
1365                 writeq(val64, &bar0->rts_qos_steering);
1366                 break;
1367         case 2:
1368                 val64 = 0x0000010000010000ULL;
1369                 writeq(val64, &bar0->rx_w_round_robin_0);
1370                 val64 = 0x0100000100000100ULL;
1371                 writeq(val64, &bar0->rx_w_round_robin_1);
1372                 val64 = 0x0001000001000001ULL;
1373                 writeq(val64, &bar0->rx_w_round_robin_2);
1374                 val64 = 0x0000010000010000ULL;
1375                 writeq(val64, &bar0->rx_w_round_robin_3);
1376                 val64 = 0x0100000000000000ULL;
1377                 writeq(val64, &bar0->rx_w_round_robin_4);
1378
1379                 val64 = 0x8080808040404040ULL;
1380                 writeq(val64, &bar0->rts_qos_steering);
1381                 break;
1382         case 3:
1383                 val64 = 0x0001000102000001ULL;
1384                 writeq(val64, &bar0->rx_w_round_robin_0);
1385                 val64 = 0x0001020000010001ULL;
1386                 writeq(val64, &bar0->rx_w_round_robin_1);
1387                 val64 = 0x0200000100010200ULL;
1388                 writeq(val64, &bar0->rx_w_round_robin_2);
1389                 val64 = 0x0001000102000001ULL;
1390                 writeq(val64, &bar0->rx_w_round_robin_3);
1391                 val64 = 0x0001020000000000ULL;
1392                 writeq(val64, &bar0->rx_w_round_robin_4);
1393
1394                 val64 = 0x8080804040402020ULL;
1395                 writeq(val64, &bar0->rts_qos_steering);
1396                 break;
1397         case 4:
1398                 val64 = 0x0001020300010200ULL;
1399                 writeq(val64, &bar0->rx_w_round_robin_0);
1400                 val64 = 0x0100000102030001ULL;
1401                 writeq(val64, &bar0->rx_w_round_robin_1);
1402                 val64 = 0x0200010000010203ULL;
1403                 writeq(val64, &bar0->rx_w_round_robin_2);
1404                 val64 = 0x0001020001000001ULL;
1405                 writeq(val64, &bar0->rx_w_round_robin_3);
1406                 val64 = 0x0203000100000000ULL;
1407                 writeq(val64, &bar0->rx_w_round_robin_4);
1408
1409                 val64 = 0x8080404020201010ULL;
1410                 writeq(val64, &bar0->rts_qos_steering);
1411                 break;
1412         case 5:
1413                 val64 = 0x0001000203000102ULL;
1414                 writeq(val64, &bar0->rx_w_round_robin_0);
1415                 val64 = 0x0001020001030004ULL;
1416                 writeq(val64, &bar0->rx_w_round_robin_1);
1417                 val64 = 0x0001000203000102ULL;
1418                 writeq(val64, &bar0->rx_w_round_robin_2);
1419                 val64 = 0x0001020001030004ULL;
1420                 writeq(val64, &bar0->rx_w_round_robin_3);
1421                 val64 = 0x0001000000000000ULL;
1422                 writeq(val64, &bar0->rx_w_round_robin_4);
1423
1424                 val64 = 0x8080404020201008ULL;
1425                 writeq(val64, &bar0->rts_qos_steering);
1426                 break;
1427         case 6:
1428                 val64 = 0x0001020304000102ULL;
1429                 writeq(val64, &bar0->rx_w_round_robin_0);
1430                 val64 = 0x0304050001020001ULL;
1431                 writeq(val64, &bar0->rx_w_round_robin_1);
1432                 val64 = 0x0203000100000102ULL;
1433                 writeq(val64, &bar0->rx_w_round_robin_2);
1434                 val64 = 0x0304000102030405ULL;
1435                 writeq(val64, &bar0->rx_w_round_robin_3);
1436                 val64 = 0x0001000200000000ULL;
1437                 writeq(val64, &bar0->rx_w_round_robin_4);
1438
1439                 val64 = 0x8080404020100804ULL;
1440                 writeq(val64, &bar0->rts_qos_steering);
1441                 break;
1442         case 7:
1443                 val64 = 0x0001020001020300ULL;
1444                 writeq(val64, &bar0->rx_w_round_robin_0);
1445                 val64 = 0x0102030400010203ULL;
1446                 writeq(val64, &bar0->rx_w_round_robin_1);
1447                 val64 = 0x0405060001020001ULL;
1448                 writeq(val64, &bar0->rx_w_round_robin_2);
1449                 val64 = 0x0304050000010200ULL;
1450                 writeq(val64, &bar0->rx_w_round_robin_3);
1451                 val64 = 0x0102030000000000ULL;
1452                 writeq(val64, &bar0->rx_w_round_robin_4);
1453
1454                 val64 = 0x8080402010080402ULL;
1455                 writeq(val64, &bar0->rts_qos_steering);
1456                 break;
1457         case 8:
1458                 val64 = 0x0001020300040105ULL;
1459                 writeq(val64, &bar0->rx_w_round_robin_0);
1460                 val64 = 0x0200030106000204ULL;
1461                 writeq(val64, &bar0->rx_w_round_robin_1);
1462                 val64 = 0x0103000502010007ULL;
1463                 writeq(val64, &bar0->rx_w_round_robin_2);
1464                 val64 = 0x0304010002060500ULL;
1465                 writeq(val64, &bar0->rx_w_round_robin_3);
1466                 val64 = 0x0103020400000000ULL;
1467                 writeq(val64, &bar0->rx_w_round_robin_4);
1468
1469                 val64 = 0x8040201008040201ULL;
1470                 writeq(val64, &bar0->rts_qos_steering);
1471                 break;
1472         }
1473
1474         /* UDP Fix */
1475         val64 = 0;
1476         for (i = 0; i < 8; i++)
1477                 writeq(val64, &bar0->rts_frm_len_n[i]);
1478
1479         /* Set the default rts frame length for the rings configured */
1480         val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1481         for (i = 0 ; i < config->rx_ring_num ; i++)
1482                 writeq(val64, &bar0->rts_frm_len_n[i]);
1483
1484         /* Set the frame length for the configured rings
1485          * desired by the user
1486          */
1487         for (i = 0; i < config->rx_ring_num; i++) {
1488                 /* If rts_frm_len[i] == 0 then it is assumed that user not
1489                  * specified frame length steering.
1490                  * If the user provides the frame length then program
1491                  * the rts_frm_len register for those values or else
1492                  * leave it as it is.
1493                  */
1494                 if (rts_frm_len[i] != 0) {
1495                         writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1496                                 &bar0->rts_frm_len_n[i]);
1497                 }
1498         }
1499
1500         /* Disable differentiated services steering logic */
1501         for (i = 0; i < 64; i++) {
1502                 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1503                         DBG_PRINT(ERR_DBG, "%s: failed rts ds steering",
1504                                 dev->name);
1505                         DBG_PRINT(ERR_DBG, "set on codepoint %d\n", i);
1506                         return FAILURE;
1507                 }
1508         }
1509
1510         /* Program statistics memory */
1511         writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1512
1513         if (nic->device_type == XFRAME_II_DEVICE) {
1514                 val64 = STAT_BC(0x320);
1515                 writeq(val64, &bar0->stat_byte_cnt);
1516         }
1517
1518         /*
1519          * Initializing the sampling rate for the device to calculate the
1520          * bandwidth utilization.
1521          */
1522         val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1523             MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1524         writeq(val64, &bar0->mac_link_util);
1525
1526
1527         /*
1528          * Initializing the Transmit and Receive Traffic Interrupt
1529          * Scheme.
1530          */
1531         /*
1532          * TTI Initialization. Default Tx timer gets us about
1533          * 250 interrupts per sec. Continuous interrupts are enabled
1534          * by default.
1535          */
1536         if (nic->device_type == XFRAME_II_DEVICE) {
1537                 int count = (nic->config.bus_speed * 125)/2;
1538                 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1539         } else {
1540
1541                 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1542         }
1543         val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1544             TTI_DATA1_MEM_TX_URNG_B(0x10) |
1545             TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN;
1546                 if (use_continuous_tx_intrs)
1547                         val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1548         writeq(val64, &bar0->tti_data1_mem);
1549
1550         val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1551             TTI_DATA2_MEM_TX_UFC_B(0x20) |
1552             TTI_DATA2_MEM_TX_UFC_C(0x40) | TTI_DATA2_MEM_TX_UFC_D(0x80);
1553         writeq(val64, &bar0->tti_data2_mem);
1554
1555         val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1556         writeq(val64, &bar0->tti_command_mem);
1557
1558         /*
1559          * Once the operation completes, the Strobe bit of the command
1560          * register will be reset. We poll for this particular condition
1561          * We wait for a maximum of 500ms for the operation to complete,
1562          * if it's not complete by then we return error.
1563          */
1564         time = 0;
1565         while (TRUE) {
1566                 val64 = readq(&bar0->tti_command_mem);
1567                 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1568                         break;
1569                 }
1570                 if (time > 10) {
1571                         DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n",
1572                                   dev->name);
1573                         return -1;
1574                 }
1575                 msleep(50);
1576                 time++;
1577         }
1578
1579         /* RTI Initialization */
1580         if (nic->device_type == XFRAME_II_DEVICE) {
1581                 /*
1582                  * Programmed to generate Apprx 500 Intrs per
1583                  * second
1584                  */
1585                 int count = (nic->config.bus_speed * 125)/4;
1586                 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1587         } else
1588                 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1589         val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1590                  RTI_DATA1_MEM_RX_URNG_B(0x10) |
1591                  RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1592
1593         writeq(val64, &bar0->rti_data1_mem);
1594
1595         val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1596                 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1597         if (nic->config.intr_type == MSI_X)
1598             val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1599                         RTI_DATA2_MEM_RX_UFC_D(0x40));
1600         else
1601             val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1602                         RTI_DATA2_MEM_RX_UFC_D(0x80));
1603         writeq(val64, &bar0->rti_data2_mem);
1604
1605         for (i = 0; i < config->rx_ring_num; i++) {
1606                 val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1607                                 | RTI_CMD_MEM_OFFSET(i);
1608                 writeq(val64, &bar0->rti_command_mem);
1609
1610                 /*
1611                  * Once the operation completes, the Strobe bit of the
1612                  * command register will be reset. We poll for this
1613                  * particular condition. We wait for a maximum of 500ms
1614                  * for the operation to complete, if it's not complete
1615                  * by then we return error.
1616                  */
1617                 time = 0;
1618                 while (TRUE) {
1619                         val64 = readq(&bar0->rti_command_mem);
1620                         if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1621                                 break;
1622
1623                         if (time > 10) {
1624                                 DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1625                                           dev->name);
1626                                 return -1;
1627                         }
1628                         time++;
1629                         msleep(50);
1630                 }
1631         }
1632
1633         /*
1634          * Initializing proper values as Pause threshold into all
1635          * the 8 Queues on Rx side.
1636          */
1637         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1638         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1639
1640         /* Disable RMAC PAD STRIPPING */
1641         add = &bar0->mac_cfg;
1642         val64 = readq(&bar0->mac_cfg);
1643         val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1644         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1645         writel((u32) (val64), add);
1646         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1647         writel((u32) (val64 >> 32), (add + 4));
1648         val64 = readq(&bar0->mac_cfg);
1649
1650         /* Enable FCS stripping by adapter */
1651         add = &bar0->mac_cfg;
1652         val64 = readq(&bar0->mac_cfg);
1653         val64 |= MAC_CFG_RMAC_STRIP_FCS;
1654         if (nic->device_type == XFRAME_II_DEVICE)
1655                 writeq(val64, &bar0->mac_cfg);
1656         else {
1657                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1658                 writel((u32) (val64), add);
1659                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1660                 writel((u32) (val64 >> 32), (add + 4));
1661         }
1662
1663         /*
1664          * Set the time value to be inserted in the pause frame
1665          * generated by xena.
1666          */
1667         val64 = readq(&bar0->rmac_pause_cfg);
1668         val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1669         val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1670         writeq(val64, &bar0->rmac_pause_cfg);
1671
1672         /*
1673          * Set the Threshold Limit for Generating the pause frame
1674          * If the amount of data in any Queue exceeds ratio of
1675          * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1676          * pause frame is generated
1677          */
1678         val64 = 0;
1679         for (i = 0; i < 4; i++) {
1680                 val64 |=
1681                     (((u64) 0xFF00 | nic->mac_control.
1682                       mc_pause_threshold_q0q3)
1683                      << (i * 2 * 8));
1684         }
1685         writeq(val64, &bar0->mc_pause_thresh_q0q3);
1686
1687         val64 = 0;
1688         for (i = 0; i < 4; i++) {
1689                 val64 |=
1690                     (((u64) 0xFF00 | nic->mac_control.
1691                       mc_pause_threshold_q4q7)
1692                      << (i * 2 * 8));
1693         }
1694         writeq(val64, &bar0->mc_pause_thresh_q4q7);
1695
1696         /*
1697          * TxDMA will stop Read request if the number of read split has
1698          * exceeded the limit pointed by shared_splits
1699          */
1700         val64 = readq(&bar0->pic_control);
1701         val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1702         writeq(val64, &bar0->pic_control);
1703
1704         if (nic->config.bus_speed == 266) {
1705                 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1706                 writeq(0x0, &bar0->read_retry_delay);
1707                 writeq(0x0, &bar0->write_retry_delay);
1708         }
1709
1710         /*
1711          * Programming the Herc to split every write transaction
1712          * that does not start on an ADB to reduce disconnects.
1713          */
1714         if (nic->device_type == XFRAME_II_DEVICE) {
1715                 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1716                         MISC_LINK_STABILITY_PRD(3);
1717                 writeq(val64, &bar0->misc_control);
1718                 val64 = readq(&bar0->pic_control2);
1719                 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
1720                 writeq(val64, &bar0->pic_control2);
1721         }
1722         if (strstr(nic->product_name, "CX4")) {
1723                 val64 = TMAC_AVG_IPG(0x17);
1724                 writeq(val64, &bar0->tmac_avg_ipg);
1725         }
1726
1727         return SUCCESS;
1728 }
1729 #define LINK_UP_DOWN_INTERRUPT          1
1730 #define MAC_RMAC_ERR_TIMER              2
1731
1732 static int s2io_link_fault_indication(struct s2io_nic *nic)
1733 {
1734         if (nic->config.intr_type != INTA)
1735                 return MAC_RMAC_ERR_TIMER;
1736         if (nic->device_type == XFRAME_II_DEVICE)
1737                 return LINK_UP_DOWN_INTERRUPT;
1738         else
1739                 return MAC_RMAC_ERR_TIMER;
1740 }
1741
1742 /**
1743  *  do_s2io_write_bits -  update alarm bits in alarm register
1744  *  @value: alarm bits
1745  *  @flag: interrupt status
1746  *  @addr: address value
1747  *  Description: update alarm bits in alarm register
1748  *  Return Value:
1749  *  NONE.
1750  */
1751 static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1752 {
1753         u64 temp64;
1754
1755         temp64 = readq(addr);
1756
1757         if(flag == ENABLE_INTRS)
1758                 temp64 &= ~((u64) value);
1759         else
1760                 temp64 |= ((u64) value);
1761         writeq(temp64, addr);
1762 }
1763
1764 static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
1765 {
1766         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1767         register u64 gen_int_mask = 0;
1768
1769         if (mask & TX_DMA_INTR) {
1770
1771                 gen_int_mask |= TXDMA_INT_M;
1772
1773                 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
1774                                 TXDMA_PCC_INT | TXDMA_TTI_INT |
1775                                 TXDMA_LSO_INT | TXDMA_TPA_INT |
1776                                 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1777
1778                 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
1779                                 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1780                                 PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1781                                 &bar0->pfc_err_mask);
1782
1783                 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
1784                                 TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1785                                 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1786
1787                 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
1788                                 PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1789                                 PCC_N_SERR | PCC_6_COF_OV_ERR |
1790                                 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1791                                 PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1792                                 PCC_TXB_ECC_SG_ERR, flag, &bar0->pcc_err_mask);
1793
1794                 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
1795                                 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1796
1797                 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
1798                                 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1799                                 LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1800                                 flag, &bar0->lso_err_mask);
1801
1802                 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
1803                                 flag, &bar0->tpa_err_mask);
1804
1805                 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1806
1807         }
1808
1809         if (mask & TX_MAC_INTR) {
1810                 gen_int_mask |= TXMAC_INT_M;
1811                 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
1812                                 &bar0->mac_int_mask);
1813                 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
1814                                 TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1815                                 TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1816                                 flag, &bar0->mac_tmac_err_mask);
1817         }
1818
1819         if (mask & TX_XGXS_INTR) {
1820                 gen_int_mask |= TXXGXS_INT_M;
1821                 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
1822                                 &bar0->xgxs_int_mask);
1823                 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
1824                                 TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1825                                 flag, &bar0->xgxs_txgxs_err_mask);
1826         }
1827
1828         if (mask & RX_DMA_INTR) {
1829                 gen_int_mask |= RXDMA_INT_M;
1830                 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
1831                                 RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1832                                 flag, &bar0->rxdma_int_mask);
1833                 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
1834                                 RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
1835                                 RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
1836                                 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
1837                 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
1838                                 PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
1839                                 PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
1840                                 &bar0->prc_pcix_err_mask);
1841                 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
1842                                 RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
1843                                 &bar0->rpa_err_mask);
1844                 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
1845                                 RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
1846                                 RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
1847                                 RDA_FRM_ECC_SG_ERR | RDA_MISC_ERR|RDA_PCIX_ERR,
1848                                 flag, &bar0->rda_err_mask);
1849                 do_s2io_write_bits(RTI_SM_ERR_ALARM |
1850                                 RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
1851                                 flag, &bar0->rti_err_mask);
1852         }
1853
1854         if (mask & RX_MAC_INTR) {
1855                 gen_int_mask |= RXMAC_INT_M;
1856                 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
1857                                 &bar0->mac_int_mask);
1858                 do_s2io_write_bits(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
1859                                 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
1860                                 RMAC_DOUBLE_ECC_ERR |
1861                                 RMAC_LINK_STATE_CHANGE_INT,
1862                                 flag, &bar0->mac_rmac_err_mask);
1863         }
1864
1865         if (mask & RX_XGXS_INTR)
1866         {
1867                 gen_int_mask |= RXXGXS_INT_M;
1868                 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
1869                                 &bar0->xgxs_int_mask);
1870                 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
1871                                 &bar0->xgxs_rxgxs_err_mask);
1872         }
1873
1874         if (mask & MC_INTR) {
1875                 gen_int_mask |= MC_INT_M;
1876                 do_s2io_write_bits(MC_INT_MASK_MC_INT, flag, &bar0->mc_int_mask);
1877                 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
1878                                 MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
1879                                 &bar0->mc_err_mask);
1880         }
1881         nic->general_int_mask = gen_int_mask;
1882
1883         /* Remove this line when alarm interrupts are enabled */
1884         nic->general_int_mask = 0;
1885 }
1886 /**
1887  *  en_dis_able_nic_intrs - Enable or Disable the interrupts
1888  *  @nic: device private variable,
1889  *  @mask: A mask indicating which Intr block must be modified and,
1890  *  @flag: A flag indicating whether to enable or disable the Intrs.
1891  *  Description: This function will either disable or enable the interrupts
1892  *  depending on the flag argument. The mask argument can be used to
1893  *  enable/disable any Intr block.
1894  *  Return Value: NONE.
1895  */
1896
1897 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1898 {
1899         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1900         register u64 temp64 = 0, intr_mask = 0;
1901
1902         intr_mask = nic->general_int_mask;
1903
1904         /*  Top level interrupt classification */
1905         /*  PIC Interrupts */
1906         if (mask & TX_PIC_INTR) {
1907                 /*  Enable PIC Intrs in the general intr mask register */
1908                 intr_mask |= TXPIC_INT_M;
1909                 if (flag == ENABLE_INTRS) {
1910                         /*
1911                          * If Hercules adapter enable GPIO otherwise
1912                          * disable all PCIX, Flash, MDIO, IIC and GPIO
1913                          * interrupts for now.
1914                          * TODO
1915                          */
1916                         if (s2io_link_fault_indication(nic) ==
1917                                         LINK_UP_DOWN_INTERRUPT ) {
1918                                 do_s2io_write_bits(PIC_INT_GPIO, flag,
1919                                                 &bar0->pic_int_mask);
1920                                 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
1921                                                 &bar0->gpio_int_mask);
1922                         } else
1923                                 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1924                 } else if (flag == DISABLE_INTRS) {
1925                         /*
1926                          * Disable PIC Intrs in the general
1927                          * intr mask register
1928                          */
1929                         writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1930                 }
1931         }
1932
1933         /*  Tx traffic interrupts */
1934         if (mask & TX_TRAFFIC_INTR) {
1935                 intr_mask |= TXTRAFFIC_INT_M;
1936                 if (flag == ENABLE_INTRS) {
1937                         /*
1938                          * Enable all the Tx side interrupts
1939                          * writing 0 Enables all 64 TX interrupt levels
1940                          */
1941                         writeq(0x0, &bar0->tx_traffic_mask);
1942                 } else if (flag == DISABLE_INTRS) {
1943                         /*
1944                          * Disable Tx Traffic Intrs in the general intr mask
1945                          * register.
1946                          */
1947                         writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1948                 }
1949         }
1950
1951         /*  Rx traffic interrupts */
1952         if (mask & RX_TRAFFIC_INTR) {
1953                 intr_mask |= RXTRAFFIC_INT_M;
1954                 if (flag == ENABLE_INTRS) {
1955                         /* writing 0 Enables all 8 RX interrupt levels */
1956                         writeq(0x0, &bar0->rx_traffic_mask);
1957                 } else if (flag == DISABLE_INTRS) {
1958                         /*
1959                          * Disable Rx Traffic Intrs in the general intr mask
1960                          * register.
1961                          */
1962                         writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1963                 }
1964         }
1965
1966         temp64 = readq(&bar0->general_int_mask);
1967         if (flag == ENABLE_INTRS)
1968                 temp64 &= ~((u64) intr_mask);
1969         else
1970                 temp64 = DISABLE_ALL_INTRS;
1971         writeq(temp64, &bar0->general_int_mask);
1972
1973         nic->general_int_mask = readq(&bar0->general_int_mask);
1974 }
1975
1976 /**
1977  *  verify_pcc_quiescent- Checks for PCC quiescent state
1978  *  Return: 1 If PCC is quiescence
1979  *          0 If PCC is not quiescence
1980  */
1981 static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
1982 {
1983         int ret = 0, herc;
1984         struct XENA_dev_config __iomem *bar0 = sp->bar0;
1985         u64 val64 = readq(&bar0->adapter_status);
1986
1987         herc = (sp->device_type == XFRAME_II_DEVICE);
1988
1989         if (flag == FALSE) {
1990                 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
1991                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
1992                                 ret = 1;
1993                 } else {
1994                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
1995                                 ret = 1;
1996                 }
1997         } else {
1998                 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
1999                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
2000                              ADAPTER_STATUS_RMAC_PCC_IDLE))
2001                                 ret = 1;
2002                 } else {
2003                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
2004                              ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2005                                 ret = 1;
2006                 }
2007         }
2008
2009         return ret;
2010 }
2011 /**
2012  *  verify_xena_quiescence - Checks whether the H/W is ready
2013  *  Description: Returns whether the H/W is ready to go or not. Depending
2014  *  on whether adapter enable bit was written or not the comparison
2015  *  differs and the calling function passes the input argument flag to
2016  *  indicate this.
2017  *  Return: 1 If xena is quiescence
2018  *          0 If Xena is not quiescence
2019  */
2020
2021 static int verify_xena_quiescence(struct s2io_nic *sp)
2022 {
2023         int  mode;
2024         struct XENA_dev_config __iomem *bar0 = sp->bar0;
2025         u64 val64 = readq(&bar0->adapter_status);
2026         mode = s2io_verify_pci_mode(sp);
2027
2028         if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
2029                 DBG_PRINT(ERR_DBG, "%s", "TDMA is not ready!");
2030                 return 0;
2031         }
2032         if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
2033         DBG_PRINT(ERR_DBG, "%s", "RDMA is not ready!");
2034                 return 0;
2035         }
2036         if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
2037                 DBG_PRINT(ERR_DBG, "%s", "PFC is not ready!");
2038                 return 0;
2039         }
2040         if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
2041                 DBG_PRINT(ERR_DBG, "%s", "TMAC BUF is not empty!");
2042                 return 0;
2043         }
2044         if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
2045                 DBG_PRINT(ERR_DBG, "%s", "PIC is not QUIESCENT!");
2046                 return 0;
2047         }
2048         if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
2049                 DBG_PRINT(ERR_DBG, "%s", "MC_DRAM is not ready!");
2050                 return 0;
2051         }
2052         if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
2053                 DBG_PRINT(ERR_DBG, "%s", "MC_QUEUES is not ready!");
2054                 return 0;
2055         }
2056         if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
2057                 DBG_PRINT(ERR_DBG, "%s", "M_PLL is not locked!");
2058                 return 0;
2059         }
2060
2061         /*
2062          * In PCI 33 mode, the P_PLL is not used, and therefore,
2063          * the the P_PLL_LOCK bit in the adapter_status register will
2064          * not be asserted.
2065          */
2066         if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
2067                 sp->device_type == XFRAME_II_DEVICE && mode !=
2068                 PCI_MODE_PCI_33) {
2069                 DBG_PRINT(ERR_DBG, "%s", "P_PLL is not locked!");
2070                 return 0;
2071         }
2072         if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
2073                         ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
2074                 DBG_PRINT(ERR_DBG, "%s", "RC_PRC is not QUIESCENT!");
2075                 return 0;
2076         }
2077         return 1;
2078 }
2079
2080 /**
2081  * fix_mac_address -  Fix for Mac addr problem on Alpha platforms
2082  * @sp: Pointer to device specifc structure
2083  * Description :
2084  * New procedure to clear mac address reading  problems on Alpha platforms
2085  *
2086  */
2087
2088 static void fix_mac_address(struct s2io_nic * sp)
2089 {
2090         struct XENA_dev_config __iomem *bar0 = sp->bar0;
2091         u64 val64;
2092         int i = 0;
2093
2094         while (fix_mac[i] != END_SIGN) {
2095                 writeq(fix_mac[i++], &bar0->gpio_control);
2096                 udelay(10);
2097                 val64 = readq(&bar0->gpio_control);
2098         }
2099 }
2100
2101 /**
2102  *  start_nic - Turns the device on
2103  *  @nic : device private variable.
2104  *  Description:
2105  *  This function actually turns the device on. Before this  function is
2106  *  called,all Registers are configured from their reset states
2107  *  and shared memory is allocated but the NIC is still quiescent. On
2108  *  calling this function, the device interrupts are cleared and the NIC is
2109  *  literally switched on by writing into the adapter control register.
2110  *  Return Value:
2111  *  SUCCESS on success and -1 on failure.
2112  */
2113
2114 static int start_nic(struct s2io_nic *nic)
2115 {
2116         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2117         struct net_device *dev = nic->dev;
2118         register u64 val64 = 0;
2119         u16 subid, i;
2120         struct mac_info *mac_control;
2121         struct config_param *config;
2122
2123         mac_control = &nic->mac_control;
2124         config = &nic->config;
2125
2126         /*  PRC Initialization and configuration */
2127         for (i = 0; i < config->rx_ring_num; i++) {
2128                 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
2129                        &bar0->prc_rxd0_n[i]);
2130
2131                 val64 = readq(&bar0->prc_ctrl_n[i]);
2132                 if (nic->rxd_mode == RXD_MODE_1)
2133                         val64 |= PRC_CTRL_RC_ENABLED;
2134                 else
2135                         val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
2136                 if (nic->device_type == XFRAME_II_DEVICE)
2137                         val64 |= PRC_CTRL_GROUP_READS;
2138                 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2139                 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2140                 writeq(val64, &bar0->prc_ctrl_n[i]);
2141         }
2142
2143         if (nic->rxd_mode == RXD_MODE_3B) {
2144                 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2145                 val64 = readq(&bar0->rx_pa_cfg);
2146                 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2147                 writeq(val64, &bar0->rx_pa_cfg);
2148         }
2149
2150         if (vlan_tag_strip == 0) {
2151                 val64 = readq(&bar0->rx_pa_cfg);
2152                 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2153                 writeq(val64, &bar0->rx_pa_cfg);
2154                 vlan_strip_flag = 0;
2155         }
2156
2157         /*
2158          * Enabling MC-RLDRAM. After enabling the device, we timeout
2159          * for around 100ms, which is approximately the time required
2160          * for the device to be ready for operation.
2161          */
2162         val64 = readq(&bar0->mc_rldram_mrs);
2163         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2164         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2165         val64 = readq(&bar0->mc_rldram_mrs);
2166
2167         msleep(100);    /* Delay by around 100 ms. */
2168
2169         /* Enabling ECC Protection. */
2170         val64 = readq(&bar0->adapter_control);
2171         val64 &= ~ADAPTER_ECC_EN;
2172         writeq(val64, &bar0->adapter_control);
2173
2174         /*
2175          * Verify if the device is ready to be enabled, if so enable
2176          * it.
2177          */
2178         val64 = readq(&bar0->adapter_status);
2179         if (!verify_xena_quiescence(nic)) {
2180                 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2181                 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
2182                           (unsigned long long) val64);
2183                 return FAILURE;
2184         }
2185
2186         /*
2187          * With some switches, link might be already up at this point.
2188          * Because of this weird behavior, when we enable laser,
2189          * we may not get link. We need to handle this. We cannot
2190          * figure out which switch is misbehaving. So we are forced to
2191          * make a global change.
2192          */
2193
2194         /* Enabling Laser. */
2195         val64 = readq(&bar0->adapter_control);
2196         val64 |= ADAPTER_EOI_TX_ON;
2197         writeq(val64, &bar0->adapter_control);
2198
2199         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2200                 /*
2201                  * Dont see link state interrupts initally on some switches,
2202                  * so directly scheduling the link state task here.
2203                  */
2204                 schedule_work(&nic->set_link_task);
2205         }
2206         /* SXE-002: Initialize link and activity LED */
2207         subid = nic->pdev->subsystem_device;
2208         if (((subid & 0xFF) >= 0x07) &&
2209             (nic->device_type == XFRAME_I_DEVICE)) {
2210                 val64 = readq(&bar0->gpio_control);
2211                 val64 |= 0x0000800000000000ULL;
2212                 writeq(val64, &bar0->gpio_control);
2213                 val64 = 0x0411040400000000ULL;
2214                 writeq(val64, (void __iomem *)bar0 + 0x2700);
2215         }
2216
2217         return SUCCESS;
2218 }
2219 /**
2220  * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2221  */
2222 static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data, struct \
2223                                         TxD *txdlp, int get_off)
2224 {
2225         struct s2io_nic *nic = fifo_data->nic;
2226         struct sk_buff *skb;
2227         struct TxD *txds;
2228         u16 j, frg_cnt;
2229
2230         txds = txdlp;
2231         if (txds->Host_Control == (u64)(long)nic->ufo_in_band_v) {
2232                 pci_unmap_single(nic->pdev, (dma_addr_t)
2233                         txds->Buffer_Pointer, sizeof(u64),
2234                         PCI_DMA_TODEVICE);
2235                 txds++;
2236         }
2237
2238         skb = (struct sk_buff *) ((unsigned long)
2239                         txds->Host_Control);
2240         if (!skb) {
2241                 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2242                 return NULL;
2243         }
2244         pci_unmap_single(nic->pdev, (dma_addr_t)
2245                          txds->Buffer_Pointer,
2246                          skb->len - skb->data_len,
2247                          PCI_DMA_TODEVICE);
2248         frg_cnt = skb_shinfo(skb)->nr_frags;
2249         if (frg_cnt) {
2250                 txds++;
2251                 for (j = 0; j < frg_cnt; j++, txds++) {
2252                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2253                         if (!txds->Buffer_Pointer)
2254                                 break;
2255                         pci_unmap_page(nic->pdev, (dma_addr_t)
2256                                         txds->Buffer_Pointer,
2257                                        frag->size, PCI_DMA_TODEVICE);
2258                 }
2259         }
2260         memset(txdlp,0, (sizeof(struct TxD) * fifo_data->max_txds));
2261         return(skb);
2262 }
2263
2264 /**
2265  *  free_tx_buffers - Free all queued Tx buffers
2266  *  @nic : device private variable.
2267  *  Description:
2268  *  Free all queued Tx buffers.
2269  *  Return Value: void
2270 */
2271
2272 static void free_tx_buffers(struct s2io_nic *nic)
2273 {
2274         struct net_device *dev = nic->dev;
2275         struct sk_buff *skb;
2276         struct TxD *txdp;
2277         int i, j;
2278         struct mac_info *mac_control;
2279         struct config_param *config;
2280         int cnt = 0;
2281
2282         mac_control = &nic->mac_control;
2283         config = &nic->config;
2284
2285         for (i = 0; i < config->tx_fifo_num; i++) {
2286                 for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) {
2287                         txdp = (struct TxD *) \
2288                         mac_control->fifos[i].list_info[j].list_virt_addr;
2289                         skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2290                         if (skb) {
2291                                 nic->mac_control.stats_info->sw_stat.mem_freed
2292                                         += skb->truesize;
2293                                 dev_kfree_skb(skb);
2294                                 cnt++;
2295                         }
2296                 }
2297                 DBG_PRINT(INTR_DBG,
2298                           "%s:forcibly freeing %d skbs on FIFO%d\n",
2299                           dev->name, cnt, i);
2300                 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2301                 mac_control->fifos[i].tx_curr_put_info.offset = 0;
2302         }
2303 }
2304
2305 /**
2306  *   stop_nic -  To stop the nic
2307  *   @nic ; device private variable.
2308  *   Description:
2309  *   This function does exactly the opposite of what the start_nic()
2310  *   function does. This function is called to stop the device.
2311  *   Return Value:
2312  *   void.
2313  */
2314
2315 static void stop_nic(struct s2io_nic *nic)
2316 {
2317         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2318         register u64 val64 = 0;
2319         u16 interruptible;
2320         struct mac_info *mac_control;
2321         struct config_param *config;
2322
2323         mac_control = &nic->mac_control;
2324         config = &nic->config;
2325
2326         /*  Disable all interrupts */
2327         en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
2328         interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2329         interruptible |= TX_PIC_INTR;
2330         en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2331
2332         /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2333         val64 = readq(&bar0->adapter_control);
2334         val64 &= ~(ADAPTER_CNTL_EN);
2335         writeq(val64, &bar0->adapter_control);
2336 }
2337
2338 /**
2339  *  fill_rx_buffers - Allocates the Rx side skbs
2340  *  @nic:  device private variable
2341  *  @ring_no: ring number
2342  *  Description:
2343  *  The function allocates Rx side skbs and puts the physical
2344  *  address of these buffers into the RxD buffer pointers, so that the NIC
2345  *  can DMA the received frame into these locations.
2346  *  The NIC supports 3 receive modes, viz
2347  *  1. single buffer,
2348  *  2. three buffer and
2349  *  3. Five buffer modes.
2350  *  Each mode defines how many fragments the received frame will be split
2351  *  up into by the NIC. The frame is split into L3 header, L4 Header,
2352  *  L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2353  *  is split into 3 fragments. As of now only single buffer mode is
2354  *  supported.
2355  *   Return Value:
2356  *  SUCCESS on success or an appropriate -ve value on failure.
2357  */
2358
2359 static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
2360 {
2361         struct net_device *dev = nic->dev;
2362         struct sk_buff *skb;
2363         struct RxD_t *rxdp;
2364         int off, off1, size, block_no, block_no1;
2365         u32 alloc_tab = 0;
2366         u32 alloc_cnt;
2367         struct mac_info *mac_control;
2368         struct config_param *config;
2369         u64 tmp;
2370         struct buffAdd *ba;
2371         unsigned long flags;
2372         struct RxD_t *first_rxdp = NULL;
2373         u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
2374         struct RxD1 *rxdp1;
2375         struct RxD3 *rxdp3;
2376         struct swStat *stats = &nic->mac_control.stats_info->sw_stat;
2377
2378         mac_control = &nic->mac_control;
2379         config = &nic->config;
2380         alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
2381             atomic_read(&nic->rx_bufs_left[ring_no]);
2382
2383         block_no1 = mac_control->rings[ring_no].rx_curr_get_info.block_index;
2384         off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
2385         while (alloc_tab < alloc_cnt) {
2386                 block_no = mac_control->rings[ring_no].rx_curr_put_info.
2387                     block_index;
2388                 off = mac_control->rings[ring_no].rx_curr_put_info.offset;
2389
2390                 rxdp = mac_control->rings[ring_no].
2391                                 rx_blocks[block_no].rxds[off].virt_addr;
2392
2393                 if ((block_no == block_no1) && (off == off1) &&
2394                                         (rxdp->Host_Control)) {
2395                         DBG_PRINT(INTR_DBG, "%s: Get and Put",
2396                                   dev->name);
2397                         DBG_PRINT(INTR_DBG, " info equated\n");
2398                         goto end;
2399                 }
2400                 if (off && (off == rxd_count[nic->rxd_mode])) {
2401                         mac_control->rings[ring_no].rx_curr_put_info.
2402                             block_index++;
2403                         if (mac_control->rings[ring_no].rx_curr_put_info.
2404                             block_index == mac_control->rings[ring_no].
2405                                         block_count)
2406                                 mac_control->rings[ring_no].rx_curr_put_info.
2407                                         block_index = 0;
2408                         block_no = mac_control->rings[ring_no].
2409                                         rx_curr_put_info.block_index;
2410                         if (off == rxd_count[nic->rxd_mode])
2411                                 off = 0;
2412                         mac_control->rings[ring_no].rx_curr_put_info.
2413                                 offset = off;
2414                         rxdp = mac_control->rings[ring_no].
2415                                 rx_blocks[block_no].block_virt_addr;
2416                         DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2417                                   dev->name, rxdp);
2418                 }
2419                 if(!napi) {
2420                         spin_lock_irqsave(&nic->put_lock, flags);
2421                         mac_control->rings[ring_no].put_pos =
2422                         (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2423                         spin_unlock_irqrestore(&nic->put_lock, flags);
2424                 } else {
2425                         mac_control->rings[ring_no].put_pos =
2426                         (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2427                 }
2428                 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2429                         ((nic->rxd_mode == RXD_MODE_3B) &&
2430                                 (rxdp->Control_2 & s2BIT(0)))) {
2431                         mac_control->rings[ring_no].rx_curr_put_info.
2432                                         offset = off;
2433                         goto end;
2434                 }
2435                 /* calculate size of skb based on ring mode */
2436                 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
2437                                 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2438                 if (nic->rxd_mode == RXD_MODE_1)
2439                         size += NET_IP_ALIGN;
2440                 else
2441                         size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2442
2443                 /* allocate skb */
2444                 skb = dev_alloc_skb(size);
2445                 if(!skb) {
2446                         DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
2447                         DBG_PRINT(INFO_DBG, "memory to allocate SKBs\n");
2448                         if (first_rxdp) {
2449                                 wmb();
2450                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2451                         }
2452                         nic->mac_control.stats_info->sw_stat. \
2453                                 mem_alloc_fail_cnt++;
2454                         return -ENOMEM ;
2455                 }
2456                 nic->mac_control.stats_info->sw_stat.mem_allocated
2457                         += skb->truesize;
2458                 if (nic->rxd_mode == RXD_MODE_1) {
2459                         /* 1 buffer mode - normal operation mode */
2460                         rxdp1 = (struct RxD1*)rxdp;
2461                         memset(rxdp, 0, sizeof(struct RxD1));
2462                         skb_reserve(skb, NET_IP_ALIGN);
2463                         rxdp1->Buffer0_ptr = pci_map_single
2464                             (nic->pdev, skb->data, size - NET_IP_ALIGN,
2465                                 PCI_DMA_FROMDEVICE);
2466                         if( (rxdp1->Buffer0_ptr == 0) ||
2467                                 (rxdp1->Buffer0_ptr ==
2468                                 DMA_ERROR_CODE))
2469                                 goto pci_map_failed;
2470
2471                         rxdp->Control_2 =
2472                                 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2473
2474                 } else if (nic->rxd_mode == RXD_MODE_3B) {
2475                         /*
2476                          * 2 buffer mode -
2477                          * 2 buffer mode provides 128
2478                          * byte aligned receive buffers.
2479                          */
2480
2481                         rxdp3 = (struct RxD3*)rxdp;
2482                         /* save buffer pointers to avoid frequent dma mapping */
2483                         Buffer0_ptr = rxdp3->Buffer0_ptr;
2484                         Buffer1_ptr = rxdp3->Buffer1_ptr;
2485                         memset(rxdp, 0, sizeof(struct RxD3));
2486                         /* restore the buffer pointers for dma sync*/
2487                         rxdp3->Buffer0_ptr = Buffer0_ptr;
2488                         rxdp3->Buffer1_ptr = Buffer1_ptr;
2489
2490                         ba = &mac_control->rings[ring_no].ba[block_no][off];
2491                         skb_reserve(skb, BUF0_LEN);
2492                         tmp = (u64)(unsigned long) skb->data;
2493                         tmp += ALIGN_SIZE;
2494                         tmp &= ~ALIGN_SIZE;
2495                         skb->data = (void *) (unsigned long)tmp;
2496                         skb_reset_tail_pointer(skb);
2497
2498                         if (!(rxdp3->Buffer0_ptr))
2499                                 rxdp3->Buffer0_ptr =
2500                                    pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
2501                                            PCI_DMA_FROMDEVICE);
2502                         else
2503                                 pci_dma_sync_single_for_device(nic->pdev,
2504                                 (dma_addr_t) rxdp3->Buffer0_ptr,
2505                                     BUF0_LEN, PCI_DMA_FROMDEVICE);
2506                         if( (rxdp3->Buffer0_ptr == 0) ||
2507                                 (rxdp3->Buffer0_ptr == DMA_ERROR_CODE))
2508                                 goto pci_map_failed;
2509
2510                         rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2511                         if (nic->rxd_mode == RXD_MODE_3B) {
2512                                 /* Two buffer mode */
2513
2514                                 /*
2515                                  * Buffer2 will have L3/L4 header plus
2516                                  * L4 payload
2517                                  */
2518                                 rxdp3->Buffer2_ptr = pci_map_single
2519                                 (nic->pdev, skb->data, dev->mtu + 4,
2520                                                 PCI_DMA_FROMDEVICE);
2521
2522                                 if( (rxdp3->Buffer2_ptr == 0) ||
2523                                         (rxdp3->Buffer2_ptr == DMA_ERROR_CODE))
2524                                         goto pci_map_failed;
2525
2526                                 rxdp3->Buffer1_ptr =
2527                                                 pci_map_single(nic->pdev,
2528                                                 ba->ba_1, BUF1_LEN,
2529                                                 PCI_DMA_FROMDEVICE);
2530                                 if( (rxdp3->Buffer1_ptr == 0) ||
2531                                         (rxdp3->Buffer1_ptr == DMA_ERROR_CODE)) {
2532                                         pci_unmap_single
2533                                                 (nic->pdev,
2534                                                 (dma_addr_t)rxdp3->Buffer2_ptr,
2535                                                 dev->mtu + 4,
2536                                                 PCI_DMA_FROMDEVICE);
2537                                         goto pci_map_failed;
2538                                 }
2539                                 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2540                                 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2541                                                                 (dev->mtu + 4);
2542                         }
2543                         rxdp->Control_2 |= s2BIT(0);
2544                 }
2545                 rxdp->Host_Control = (unsigned long) (skb);
2546                 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2547                         rxdp->Control_1 |= RXD_OWN_XENA;
2548                 off++;
2549                 if (off == (rxd_count[nic->rxd_mode] + 1))
2550                         off = 0;
2551                 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
2552
2553                 rxdp->Control_2 |= SET_RXD_MARKER;
2554                 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2555                         if (first_rxdp) {
2556                                 wmb();
2557                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2558                         }
2559                         first_rxdp = rxdp;
2560                 }
2561                 atomic_inc(&nic->rx_bufs_left[ring_no]);
2562                 alloc_tab++;
2563         }
2564
2565       end:
2566         /* Transfer ownership of first descriptor to adapter just before
2567          * exiting. Before that, use memory barrier so that ownership
2568          * and other fields are seen by adapter correctly.
2569          */
2570         if (first_rxdp) {
2571                 wmb();
2572                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2573         }
2574
2575         return SUCCESS;
2576 pci_map_failed:
2577         stats->pci_map_fail_cnt++;
2578         stats->mem_freed += skb->truesize;
2579         dev_kfree_skb_irq(skb);
2580         return -ENOMEM;
2581 }
2582
2583 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2584 {
2585         struct net_device *dev = sp->dev;
2586         int j;
2587         struct sk_buff *skb;
2588         struct RxD_t *rxdp;
2589         struct mac_info *mac_control;
2590         struct buffAdd *ba;
2591         struct RxD1 *rxdp1;
2592         struct RxD3 *rxdp3;
2593
2594         mac_control = &sp->mac_control;
2595         for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2596                 rxdp = mac_control->rings[ring_no].
2597                                 rx_blocks[blk].rxds[j].virt_addr;
2598                 skb = (struct sk_buff *)
2599                         ((unsigned long) rxdp->Host_Control);
2600                 if (!skb) {
2601                         continue;
2602                 }
2603                 if (sp->rxd_mode == RXD_MODE_1) {
2604                         rxdp1 = (struct RxD1*)rxdp;
2605                         pci_unmap_single(sp->pdev, (dma_addr_t)
2606                                 rxdp1->Buffer0_ptr,
2607                                 dev->mtu +
2608                                 HEADER_ETHERNET_II_802_3_SIZE
2609                                 + HEADER_802_2_SIZE +
2610                                 HEADER_SNAP_SIZE,
2611                                 PCI_DMA_FROMDEVICE);
2612                         memset(rxdp, 0, sizeof(struct RxD1));
2613                 } else if(sp->rxd_mode == RXD_MODE_3B) {
2614                         rxdp3 = (struct RxD3*)rxdp;
2615                         ba = &mac_control->rings[ring_no].
2616                                 ba[blk][j];
2617                         pci_unmap_single(sp->pdev, (dma_addr_t)
2618                                 rxdp3->Buffer0_ptr,
2619                                 BUF0_LEN,
2620                                 PCI_DMA_FROMDEVICE);
2621                         pci_unmap_single(sp->pdev, (dma_addr_t)
2622                                 rxdp3->Buffer1_ptr,
2623                                 BUF1_LEN,
2624                                 PCI_DMA_FROMDEVICE);
2625                         pci_unmap_single(sp->pdev, (dma_addr_t)
2626                                 rxdp3->Buffer2_ptr,
2627                                 dev->mtu + 4,
2628                                 PCI_DMA_FROMDEVICE);
2629                         memset(rxdp, 0, sizeof(struct RxD3));
2630                 }
2631                 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
2632                 dev_kfree_skb(skb);
2633                 atomic_dec(&sp->rx_bufs_left[ring_no]);
2634         }
2635 }
2636
2637 /**
2638  *  free_rx_buffers - Frees all Rx buffers
2639  *  @sp: device private variable.
2640  *  Description:
2641  *  This function will free all Rx buffers allocated by host.
2642  *  Return Value:
2643  *  NONE.
2644  */
2645
2646 static void free_rx_buffers(struct s2io_nic *sp)
2647 {
2648         struct net_device *dev = sp->dev;
2649         int i, blk = 0, buf_cnt = 0;
2650         struct mac_info *mac_control;
2651         struct config_param *config;
2652
2653         mac_control = &sp->mac_control;
2654         config = &sp->config;
2655
2656         for (i = 0; i < config->rx_ring_num; i++) {
2657                 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2658                         free_rxd_blk(sp,i,blk);
2659
2660                 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2661                 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2662                 mac_control->rings[i].rx_curr_put_info.offset = 0;
2663                 mac_control->rings[i].rx_curr_get_info.offset = 0;
2664                 atomic_set(&sp->rx_bufs_left[i], 0);
2665                 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2666                           dev->name, buf_cnt, i);
2667         }
2668 }
2669
2670 /**
2671  * s2io_poll - Rx interrupt handler for NAPI support
2672  * @napi : pointer to the napi structure.
2673  * @budget : The number of packets that were budgeted to be processed
2674  * during  one pass through the 'Poll" function.
2675  * Description:
2676  * Comes into picture only if NAPI support has been incorporated. It does
2677  * the same thing that rx_intr_handler does, but not in a interrupt context
2678  * also It will process only a given number of packets.
2679  * Return value:
2680  * 0 on success and 1 if there are No Rx packets to be processed.
2681  */
2682
2683 static int s2io_poll(struct napi_struct *napi, int budget)
2684 {
2685         struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
2686         struct net_device *dev = nic->dev;
2687         int pkt_cnt = 0, org_pkts_to_process;
2688         struct mac_info *mac_control;
2689         struct config_param *config;
2690         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2691         int i;
2692
2693         if (!is_s2io_card_up(nic))
2694                 return 0;
2695
2696         mac_control = &nic->mac_control;
2697         config = &nic->config;
2698
2699         nic->pkts_to_process = budget;
2700         org_pkts_to_process = nic->pkts_to_process;
2701
2702         writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
2703         readl(&bar0->rx_traffic_int);
2704
2705         for (i = 0; i < config->rx_ring_num; i++) {
2706                 rx_intr_handler(&mac_control->rings[i]);
2707                 pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
2708                 if (!nic->pkts_to_process) {
2709                         /* Quota for the current iteration has been met */
2710                         goto no_rx;
2711                 }
2712         }
2713
2714         netif_rx_complete(dev, napi);
2715
2716         for (i = 0; i < config->rx_ring_num; i++) {
2717                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2718                         DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2719                         DBG_PRINT(INFO_DBG, " in Rx Poll!!\n");
2720                         break;
2721                 }
2722         }
2723         /* Re enable the Rx interrupts. */
2724         writeq(0x0, &bar0->rx_traffic_mask);
2725         readl(&bar0->rx_traffic_mask);
2726         return pkt_cnt;
2727
2728 no_rx:
2729         for (i = 0; i < config->rx_ring_num; i++) {
2730                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2731                         DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2732                         DBG_PRINT(INFO_DBG, " in Rx Poll!!\n");
2733                         break;
2734                 }
2735         }
2736         return pkt_cnt;
2737 }
2738
2739 #ifdef CONFIG_NET_POLL_CONTROLLER
2740 /**
2741  * s2io_netpoll - netpoll event handler entry point
2742  * @dev : pointer to the device structure.
2743  * Description:
2744  *      This function will be called by upper layer to check for events on the
2745  * interface in situations where interrupts are disabled. It is used for
2746  * specific in-kernel networking tasks, such as remote consoles and kernel
2747  * debugging over the network (example netdump in RedHat).
2748  */
2749 static void s2io_netpoll(struct net_device *dev)
2750 {
2751         struct s2io_nic *nic = dev->priv;
2752         struct mac_info *mac_control;
2753         struct config_param *config;
2754         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2755         u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2756         int i;
2757
2758         if (pci_channel_offline(nic->pdev))
2759                 return;
2760
2761         disable_irq(dev->irq);
2762
2763         mac_control = &nic->mac_control;
2764         config = &nic->config;
2765
2766         writeq(val64, &bar0->rx_traffic_int);
2767         writeq(val64, &bar0->tx_traffic_int);
2768
2769         /* we need to free up the transmitted skbufs or else netpoll will
2770          * run out of skbs and will fail and eventually netpoll application such
2771          * as netdump will fail.
2772          */
2773         for (i = 0; i < config->tx_fifo_num; i++)
2774                 tx_intr_handler(&mac_control->fifos[i]);
2775
2776         /* check for received packet and indicate up to network */
2777         for (i = 0; i < config->rx_ring_num; i++)
2778                 rx_intr_handler(&mac_control->rings[i]);
2779
2780         for (i = 0; i < config->rx_ring_num; i++) {
2781                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2782                         DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2783                         DBG_PRINT(INFO_DBG, " in Rx Netpoll!!\n");
2784                         break;
2785                 }
2786         }
2787         enable_irq(dev->irq);
2788         return;
2789 }
2790 #endif
2791
2792 /**
2793  *  rx_intr_handler - Rx interrupt handler
2794  *  @nic: device private variable.
2795  *  Description:
2796  *  If the interrupt is because of a received frame or if the
2797  *  receive ring contains fresh as yet un-processed frames,this function is
2798  *  called. It picks out the RxD at which place the last Rx processing had
2799  *  stopped and sends the skb to the OSM's Rx handler and then increments
2800  *  the offset.
2801  *  Return Value:
2802  *  NONE.
2803  */
2804 static void rx_intr_handler(struct ring_info *ring_data)
2805 {
2806         struct s2io_nic *nic = ring_data->nic;
2807         struct net_device *dev = (struct net_device *) nic->dev;
2808         int get_block, put_block, put_offset;
2809         struct rx_curr_get_info get_info, put_info;
2810         struct RxD_t *rxdp;
2811         struct sk_buff *skb;
2812         int pkt_cnt = 0;
2813         int i;
2814         struct RxD1* rxdp1;
2815         struct RxD3* rxdp3;
2816
2817         spin_lock(&nic->rx_lock);
2818
2819         get_info = ring_data->rx_curr_get_info;
2820         get_block = get_info.block_index;
2821         memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
2822         put_block = put_info.block_index;
2823         rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2824         if (!napi) {
2825                 spin_lock(&nic->put_lock);
2826                 put_offset = ring_data->put_pos;
2827                 spin_unlock(&nic->put_lock);
2828         } else
2829                 put_offset = ring_data->put_pos;
2830
2831         while (RXD_IS_UP2DT(rxdp)) {
2832                 /*
2833                  * If your are next to put index then it's
2834                  * FIFO full condition
2835                  */
2836                 if ((get_block == put_block) &&
2837                     (get_info.offset + 1) == put_info.offset) {
2838                         DBG_PRINT(INTR_DBG, "%s: Ring Full\n",dev->name);
2839                         break;
2840                 }
2841                 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2842                 if (skb == NULL) {
2843                         DBG_PRINT(ERR_DBG, "%s: The skb is ",
2844                                   dev->name);
2845                         DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
2846                         spin_unlock(&nic->rx_lock);
2847                         return;
2848                 }
2849                 if (nic->rxd_mode == RXD_MODE_1) {
2850                         rxdp1 = (struct RxD1*)rxdp;
2851                         pci_unmap_single(nic->pdev, (dma_addr_t)
2852                                 rxdp1->Buffer0_ptr,
2853                                 dev->mtu +
2854                                 HEADER_ETHERNET_II_802_3_SIZE +
2855                                 HEADER_802_2_SIZE +
2856                                 HEADER_SNAP_SIZE,
2857                                 PCI_DMA_FROMDEVICE);
2858                 } else if (nic->rxd_mode == RXD_MODE_3B) {
2859                         rxdp3 = (struct RxD3*)rxdp;
2860                         pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
2861                                 rxdp3->Buffer0_ptr,
2862                                 BUF0_LEN, PCI_DMA_FROMDEVICE);
2863                         pci_unmap_single(nic->pdev, (dma_addr_t)
2864                                 rxdp3->Buffer2_ptr,
2865                                 dev->mtu + 4,
2866                                 PCI_DMA_FROMDEVICE);
2867                 }
2868                 prefetch(skb->data);
2869                 rx_osm_handler(ring_data, rxdp);
2870                 get_info.offset++;
2871                 ring_data->rx_curr_get_info.offset = get_info.offset;
2872                 rxdp = ring_data->rx_blocks[get_block].
2873                                 rxds[get_info.offset].virt_addr;
2874                 if (get_info.offset == rxd_count[nic->rxd_mode]) {
2875                         get_info.offset = 0;
2876                         ring_data->rx_curr_get_info.offset = get_info.offset;
2877                         get_block++;
2878                         if (get_block == ring_data->block_count)
2879                                 get_block = 0;
2880                         ring_data->rx_curr_get_info.block_index = get_block;
2881                         rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2882                 }
2883
2884                 nic->pkts_to_process -= 1;
2885                 if ((napi) && (!nic->pkts_to_process))
2886                         break;
2887                 pkt_cnt++;
2888                 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2889                         break;
2890         }
2891         if (nic->lro) {
2892                 /* Clear all LRO sessions before exiting */
2893                 for (i=0; i<MAX_LRO_SESSIONS; i++) {
2894                         struct lro *lro = &nic->lro0_n[i];
2895                         if (lro->in_use) {
2896                                 update_L3L4_header(nic, lro);
2897                                 queue_rx_frame(lro->parent);
2898                                 clear_lro_session(lro);
2899                         }
2900                 }
2901         }
2902
2903         spin_unlock(&nic->rx_lock);
2904 }
2905
2906 /**
2907  *  tx_intr_handler - Transmit interrupt handler
2908  *  @nic : device private variable
2909  *  Description:
2910  *  If an interrupt was raised to indicate DMA complete of the
2911  *  Tx packet, this function is called. It identifies the last TxD
2912  *  whose buffer was freed and frees all skbs whose data have already
2913  *  DMA'ed into the NICs internal memory.
2914  *  Return Value:
2915  *  NONE
2916  */
2917
2918 static void tx_intr_handler(struct fifo_info *fifo_data)
2919 {
2920         struct s2io_nic *nic = fifo_data->nic;
2921         struct net_device *dev = (struct net_device *) nic->dev;
2922         struct tx_curr_get_info get_info, put_info;
2923         struct sk_buff *skb;
2924         struct TxD *txdlp;
2925         u8 err_mask;
2926
2927         get_info = fifo_data->tx_curr_get_info;
2928         memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
2929         txdlp = (struct TxD *) fifo_data->list_info[get_info.offset].
2930             list_virt_addr;
2931         while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
2932                (get_info.offset != put_info.offset) &&
2933                (txdlp->Host_Control)) {
2934                 /* Check for TxD errors */
2935                 if (txdlp->Control_1 & TXD_T_CODE) {
2936                         unsigned long long err;
2937                         err = txdlp->Control_1 & TXD_T_CODE;
2938                         if (err & 0x1) {
2939                                 nic->mac_control.stats_info->sw_stat.
2940                                                 parity_err_cnt++;
2941                         }
2942
2943                         /* update t_code statistics */
2944                         err_mask = err >> 48;
2945                         switch(err_mask) {
2946                                 case 2:
2947                                         nic->mac_control.stats_info->sw_stat.
2948                                                         tx_buf_abort_cnt++;
2949                                 break;
2950
2951                                 case 3:
2952                                         nic->mac_control.stats_info->sw_stat.
2953                                                         tx_desc_abort_cnt++;
2954                                 break;
2955
2956                                 case 7:
2957                                         nic->mac_control.stats_info->sw_stat.
2958                                                         tx_parity_err_cnt++;
2959                                 break;
2960
2961                                 case 10:
2962                                         nic->mac_control.stats_info->sw_stat.
2963                                                         tx_link_loss_cnt++;
2964                                 break;
2965
2966                                 case 15:
2967                                         nic->mac_control.stats_info->sw_stat.
2968                                                         tx_list_proc_err_cnt++;
2969                                 break;
2970                         }
2971                 }
2972
2973                 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
2974                 if (skb == NULL) {
2975                         DBG_PRINT(ERR_DBG, "%s: Null skb ",
2976                         __FUNCTION__);
2977                         DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
2978                         return;
2979                 }
2980
2981                 /* Updating the statistics block */
2982                 nic->stats.tx_bytes += skb->len;
2983                 nic->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
2984                 dev_kfree_skb_irq(skb);
2985
2986                 get_info.offset++;
2987                 if (get_info.offset == get_info.fifo_len + 1)
2988                         get_info.offset = 0;
2989                 txdlp = (struct TxD *) fifo_data->list_info
2990                     [get_info.offset].list_virt_addr;
2991                 fifo_data->tx_curr_get_info.offset =
2992                     get_info.offset;
2993         }
2994
2995         spin_lock(&nic->tx_lock);
2996         if (netif_queue_stopped(dev))
2997                 netif_wake_queue(dev);
2998         spin_unlock(&nic->tx_lock);
2999 }
3000
3001 /**
3002  *  s2io_mdio_write - Function to write in to MDIO registers
3003  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3004  *  @addr     : address value
3005  *  @value    : data value
3006  *  @dev      : pointer to net_device structure
3007  *  Description:
3008  *  This function is used to write values to the MDIO registers
3009  *  NONE
3010  */
3011 static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
3012 {
3013         u64 val64 = 0x0;
3014         struct s2io_nic *sp = dev->priv;
3015         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3016
3017         //address transaction
3018         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3019                         | MDIO_MMD_DEV_ADDR(mmd_type)
3020                         | MDIO_MMS_PRT_ADDR(0x0);
3021         writeq(val64, &bar0->mdio_control);
3022         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3023         writeq(val64, &bar0->mdio_control);
3024         udelay(100);
3025
3026         //Data transaction
3027         val64 = 0x0;
3028         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3029                         | MDIO_MMD_DEV_ADDR(mmd_type)
3030                         | MDIO_MMS_PRT_ADDR(0x0)
3031                         | MDIO_MDIO_DATA(value)
3032                         | MDIO_OP(MDIO_OP_WRITE_TRANS);
3033         writeq(val64, &bar0->mdio_control);
3034         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3035         writeq(val64, &bar0->mdio_control);
3036         udelay(100);
3037
3038         val64 = 0x0;
3039         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3040         | MDIO_MMD_DEV_ADDR(mmd_type)
3041         | MDIO_MMS_PRT_ADDR(0x0)
3042         | MDIO_OP(MDIO_OP_READ_TRANS);
3043         writeq(val64, &bar0->mdio_control);
3044         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3045         writeq(val64, &bar0->mdio_control);
3046         udelay(100);
3047
3048 }
3049
3050 /**
3051  *  s2io_mdio_read - Function to write in to MDIO registers
3052  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3053  *  @addr     : address value