[PATCH] s2io bogus memset
[sfrench/cifs-2.6.git] / drivers / net / s2io.c
1 /************************************************************************
2  * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3  * Copyright(c) 2002-2005 Neterion Inc.
4
5  * This software may be used and distributed according to the terms of
6  * the GNU General Public License (GPL), incorporated herein by reference.
7  * Drivers based on or derived from this code fall under the GPL and must
8  * retain the authorship, copyright and license notice.  This file is not
9  * a complete program and may only be used when the entire operating
10  * system is licensed under the GPL.
11  * See the file COPYING in this distribution for more information.
12  *
13  * Credits:
14  * Jeff Garzik          : For pointing out the improper error condition
15  *                        check in the s2io_xmit routine and also some
16  *                        issues in the Tx watch dog function. Also for
17  *                        patiently answering all those innumerable
18  *                        questions regaring the 2.6 porting issues.
19  * Stephen Hemminger    : Providing proper 2.6 porting mechanism for some
20  *                        macros available only in 2.6 Kernel.
21  * Francois Romieu      : For pointing out all code part that were
22  *                        deprecated and also styling related comments.
23  * Grant Grundler       : For helping me get rid of some Architecture
24  *                        dependent code.
25  * Christopher Hellwig  : Some more 2.6 specific issues in the driver.
26  *
27  * The module loadable parameters that are supported by the driver and a brief
28  * explaination of all the variables.
29  *
30  * rx_ring_num : This can be used to program the number of receive rings used
31  * in the driver.
32  * rx_ring_sz: This defines the number of receive blocks each ring can have.
33  *     This is also an array of size 8.
34  * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
35  *              values are 1, 2 and 3.
36  * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
37  * tx_fifo_len: This too is an array of 8. Each element defines the number of
38  * Tx descriptors that can be associated with each corresponding FIFO.
39  * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40  *     1(MSI), 2(MSI_X). Default value is '0(INTA)'
41  * lro: Specifies whether to enable Large Receive Offload (LRO) or not.
42  *     Possible values '1' for enable '0' for disable. Default is '0'
43  * lro_max_pkts: This parameter defines maximum number of packets can be
44  *     aggregated as a single large packet
45  ************************************************************************/
46
47 #include <linux/module.h>
48 #include <linux/types.h>
49 #include <linux/errno.h>
50 #include <linux/ioport.h>
51 #include <linux/pci.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/kernel.h>
54 #include <linux/netdevice.h>
55 #include <linux/etherdevice.h>
56 #include <linux/skbuff.h>
57 #include <linux/init.h>
58 #include <linux/delay.h>
59 #include <linux/stddef.h>
60 #include <linux/ioctl.h>
61 #include <linux/timex.h>
62 #include <linux/sched.h>
63 #include <linux/ethtool.h>
64 #include <linux/workqueue.h>
65 #include <linux/if_vlan.h>
66 #include <linux/ip.h>
67 #include <linux/tcp.h>
68 #include <net/tcp.h>
69
70 #include <asm/system.h>
71 #include <asm/uaccess.h>
72 #include <asm/io.h>
73 #include <asm/div64.h>
74 #include <asm/irq.h>
75
76 /* local include */
77 #include "s2io.h"
78 #include "s2io-regs.h"
79
80 #define DRV_VERSION "2.0.15.2"
81
82 /* S2io Driver name & version. */
83 static char s2io_driver_name[] = "Neterion";
84 static char s2io_driver_version[] = DRV_VERSION;
85
86 static int rxd_size[4] = {32,48,48,64};
87 static int rxd_count[4] = {127,85,85,63};
88
89 static inline int RXD_IS_UP2DT(RxD_t *rxdp)
90 {
91         int ret;
92
93         ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
94                 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
95
96         return ret;
97 }
98
99 /*
100  * Cards with following subsystem_id have a link state indication
101  * problem, 600B, 600C, 600D, 640B, 640C and 640D.
102  * macro below identifies these cards given the subsystem_id.
103  */
104 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
105         (dev_type == XFRAME_I_DEVICE) ?                 \
106                 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
107                  ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
108
109 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
110                                       ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
111 #define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
112 #define PANIC   1
113 #define LOW     2
114 static inline int rx_buffer_level(nic_t * sp, int rxb_size, int ring)
115 {
116         mac_info_t *mac_control;
117
118         mac_control = &sp->mac_control;
119         if (rxb_size <= rxd_count[sp->rxd_mode])
120                 return PANIC;
121         else if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16)
122                 return  LOW;
123         return 0;
124 }
125
126 /* Ethtool related variables and Macros. */
127 static char s2io_gstrings[][ETH_GSTRING_LEN] = {
128         "Register test\t(offline)",
129         "Eeprom test\t(offline)",
130         "Link test\t(online)",
131         "RLDRAM test\t(offline)",
132         "BIST Test\t(offline)"
133 };
134
135 static char ethtool_stats_keys[][ETH_GSTRING_LEN] = {
136         {"tmac_frms"},
137         {"tmac_data_octets"},
138         {"tmac_drop_frms"},
139         {"tmac_mcst_frms"},
140         {"tmac_bcst_frms"},
141         {"tmac_pause_ctrl_frms"},
142         {"tmac_ttl_octets"},
143         {"tmac_ucst_frms"},
144         {"tmac_nucst_frms"},
145         {"tmac_any_err_frms"},
146         {"tmac_ttl_less_fb_octets"},
147         {"tmac_vld_ip_octets"},
148         {"tmac_vld_ip"},
149         {"tmac_drop_ip"},
150         {"tmac_icmp"},
151         {"tmac_rst_tcp"},
152         {"tmac_tcp"},
153         {"tmac_udp"},
154         {"rmac_vld_frms"},
155         {"rmac_data_octets"},
156         {"rmac_fcs_err_frms"},
157         {"rmac_drop_frms"},
158         {"rmac_vld_mcst_frms"},
159         {"rmac_vld_bcst_frms"},
160         {"rmac_in_rng_len_err_frms"},
161         {"rmac_out_rng_len_err_frms"},
162         {"rmac_long_frms"},
163         {"rmac_pause_ctrl_frms"},
164         {"rmac_unsup_ctrl_frms"},
165         {"rmac_ttl_octets"},
166         {"rmac_accepted_ucst_frms"},
167         {"rmac_accepted_nucst_frms"},
168         {"rmac_discarded_frms"},
169         {"rmac_drop_events"},
170         {"rmac_ttl_less_fb_octets"},
171         {"rmac_ttl_frms"},
172         {"rmac_usized_frms"},
173         {"rmac_osized_frms"},
174         {"rmac_frag_frms"},
175         {"rmac_jabber_frms"},
176         {"rmac_ttl_64_frms"},
177         {"rmac_ttl_65_127_frms"},
178         {"rmac_ttl_128_255_frms"},
179         {"rmac_ttl_256_511_frms"},
180         {"rmac_ttl_512_1023_frms"},
181         {"rmac_ttl_1024_1518_frms"},
182         {"rmac_ip"},
183         {"rmac_ip_octets"},
184         {"rmac_hdr_err_ip"},
185         {"rmac_drop_ip"},
186         {"rmac_icmp"},
187         {"rmac_tcp"},
188         {"rmac_udp"},
189         {"rmac_err_drp_udp"},
190         {"rmac_xgmii_err_sym"},
191         {"rmac_frms_q0"},
192         {"rmac_frms_q1"},
193         {"rmac_frms_q2"},
194         {"rmac_frms_q3"},
195         {"rmac_frms_q4"},
196         {"rmac_frms_q5"},
197         {"rmac_frms_q6"},
198         {"rmac_frms_q7"},
199         {"rmac_full_q0"},
200         {"rmac_full_q1"},
201         {"rmac_full_q2"},
202         {"rmac_full_q3"},
203         {"rmac_full_q4"},
204         {"rmac_full_q5"},
205         {"rmac_full_q6"},
206         {"rmac_full_q7"},
207         {"rmac_pause_cnt"},
208         {"rmac_xgmii_data_err_cnt"},
209         {"rmac_xgmii_ctrl_err_cnt"},
210         {"rmac_accepted_ip"},
211         {"rmac_err_tcp"},
212         {"rd_req_cnt"},
213         {"new_rd_req_cnt"},
214         {"new_rd_req_rtry_cnt"},
215         {"rd_rtry_cnt"},
216         {"wr_rtry_rd_ack_cnt"},
217         {"wr_req_cnt"},
218         {"new_wr_req_cnt"},
219         {"new_wr_req_rtry_cnt"},
220         {"wr_rtry_cnt"},
221         {"wr_disc_cnt"},
222         {"rd_rtry_wr_ack_cnt"},
223         {"txp_wr_cnt"},
224         {"txd_rd_cnt"},
225         {"txd_wr_cnt"},
226         {"rxd_rd_cnt"},
227         {"rxd_wr_cnt"},
228         {"txf_rd_cnt"},
229         {"rxf_wr_cnt"},
230         {"rmac_ttl_1519_4095_frms"},
231         {"rmac_ttl_4096_8191_frms"},
232         {"rmac_ttl_8192_max_frms"},
233         {"rmac_ttl_gt_max_frms"},
234         {"rmac_osized_alt_frms"},
235         {"rmac_jabber_alt_frms"},
236         {"rmac_gt_max_alt_frms"},
237         {"rmac_vlan_frms"},
238         {"rmac_len_discard"},
239         {"rmac_fcs_discard"},
240         {"rmac_pf_discard"},
241         {"rmac_da_discard"},
242         {"rmac_red_discard"},
243         {"rmac_rts_discard"},
244         {"rmac_ingm_full_discard"},
245         {"link_fault_cnt"},
246         {"\n DRIVER STATISTICS"},
247         {"single_bit_ecc_errs"},
248         {"double_bit_ecc_errs"},
249         {"parity_err_cnt"},
250         {"serious_err_cnt"},
251         {"soft_reset_cnt"},
252         {"fifo_full_cnt"},
253         {"ring_full_cnt"},
254         ("alarm_transceiver_temp_high"),
255         ("alarm_transceiver_temp_low"),
256         ("alarm_laser_bias_current_high"),
257         ("alarm_laser_bias_current_low"),
258         ("alarm_laser_output_power_high"),
259         ("alarm_laser_output_power_low"),
260         ("warn_transceiver_temp_high"),
261         ("warn_transceiver_temp_low"),
262         ("warn_laser_bias_current_high"),
263         ("warn_laser_bias_current_low"),
264         ("warn_laser_output_power_high"),
265         ("warn_laser_output_power_low"),
266         ("lro_aggregated_pkts"),
267         ("lro_flush_both_count"),
268         ("lro_out_of_sequence_pkts"),
269         ("lro_flush_due_to_max_pkts"),
270         ("lro_avg_aggr_pkts"),
271 };
272
273 #define S2IO_STAT_LEN sizeof(ethtool_stats_keys)/ ETH_GSTRING_LEN
274 #define S2IO_STAT_STRINGS_LEN S2IO_STAT_LEN * ETH_GSTRING_LEN
275
276 #define S2IO_TEST_LEN   sizeof(s2io_gstrings) / ETH_GSTRING_LEN
277 #define S2IO_STRINGS_LEN        S2IO_TEST_LEN * ETH_GSTRING_LEN
278
279 #define S2IO_TIMER_CONF(timer, handle, arg, exp)                \
280                         init_timer(&timer);                     \
281                         timer.function = handle;                \
282                         timer.data = (unsigned long) arg;       \
283                         mod_timer(&timer, (jiffies + exp))      \
284
285 /* Add the vlan */
286 static void s2io_vlan_rx_register(struct net_device *dev,
287                                         struct vlan_group *grp)
288 {
289         nic_t *nic = dev->priv;
290         unsigned long flags;
291
292         spin_lock_irqsave(&nic->tx_lock, flags);
293         nic->vlgrp = grp;
294         spin_unlock_irqrestore(&nic->tx_lock, flags);
295 }
296
297 /* Unregister the vlan */
298 static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid)
299 {
300         nic_t *nic = dev->priv;
301         unsigned long flags;
302
303         spin_lock_irqsave(&nic->tx_lock, flags);
304         if (nic->vlgrp)
305                 nic->vlgrp->vlan_devices[vid] = NULL;
306         spin_unlock_irqrestore(&nic->tx_lock, flags);
307 }
308
309 /*
310  * Constants to be programmed into the Xena's registers, to configure
311  * the XAUI.
312  */
313
314 #define END_SIGN        0x0
315 static const u64 herc_act_dtx_cfg[] = {
316         /* Set address */
317         0x8000051536750000ULL, 0x80000515367500E0ULL,
318         /* Write data */
319         0x8000051536750004ULL, 0x80000515367500E4ULL,
320         /* Set address */
321         0x80010515003F0000ULL, 0x80010515003F00E0ULL,
322         /* Write data */
323         0x80010515003F0004ULL, 0x80010515003F00E4ULL,
324         /* Set address */
325         0x801205150D440000ULL, 0x801205150D4400E0ULL,
326         /* Write data */
327         0x801205150D440004ULL, 0x801205150D4400E4ULL,
328         /* Set address */
329         0x80020515F2100000ULL, 0x80020515F21000E0ULL,
330         /* Write data */
331         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
332         /* Done */
333         END_SIGN
334 };
335
336 static const u64 xena_dtx_cfg[] = {
337         /* Set address */
338         0x8000051500000000ULL, 0x80000515000000E0ULL,
339         /* Write data */
340         0x80000515D9350004ULL, 0x80000515D93500E4ULL,
341         /* Set address */
342         0x8001051500000000ULL, 0x80010515000000E0ULL,
343         /* Write data */
344         0x80010515001E0004ULL, 0x80010515001E00E4ULL,
345         /* Set address */
346         0x8002051500000000ULL, 0x80020515000000E0ULL,
347         /* Write data */
348         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
349         END_SIGN
350 };
351
352 /*
353  * Constants for Fixing the MacAddress problem seen mostly on
354  * Alpha machines.
355  */
356 static const u64 fix_mac[] = {
357         0x0060000000000000ULL, 0x0060600000000000ULL,
358         0x0040600000000000ULL, 0x0000600000000000ULL,
359         0x0020600000000000ULL, 0x0060600000000000ULL,
360         0x0020600000000000ULL, 0x0060600000000000ULL,
361         0x0020600000000000ULL, 0x0060600000000000ULL,
362         0x0020600000000000ULL, 0x0060600000000000ULL,
363         0x0020600000000000ULL, 0x0060600000000000ULL,
364         0x0020600000000000ULL, 0x0060600000000000ULL,
365         0x0020600000000000ULL, 0x0060600000000000ULL,
366         0x0020600000000000ULL, 0x0060600000000000ULL,
367         0x0020600000000000ULL, 0x0060600000000000ULL,
368         0x0020600000000000ULL, 0x0060600000000000ULL,
369         0x0020600000000000ULL, 0x0000600000000000ULL,
370         0x0040600000000000ULL, 0x0060600000000000ULL,
371         END_SIGN
372 };
373
374 MODULE_AUTHOR("Raghavendra Koushik <raghavendra.koushik@neterion.com>");
375 MODULE_LICENSE("GPL");
376 MODULE_VERSION(DRV_VERSION);
377
378
379 /* Module Loadable parameters. */
380 S2IO_PARM_INT(tx_fifo_num, 1);
381 S2IO_PARM_INT(rx_ring_num, 1);
382
383
384 S2IO_PARM_INT(rx_ring_mode, 1);
385 S2IO_PARM_INT(use_continuous_tx_intrs, 1);
386 S2IO_PARM_INT(rmac_pause_time, 0x100);
387 S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
388 S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
389 S2IO_PARM_INT(shared_splits, 0);
390 S2IO_PARM_INT(tmac_util_period, 5);
391 S2IO_PARM_INT(rmac_util_period, 5);
392 S2IO_PARM_INT(bimodal, 0);
393 S2IO_PARM_INT(l3l4hdr_size, 128);
394 /* Frequency of Rx desc syncs expressed as power of 2 */
395 S2IO_PARM_INT(rxsync_frequency, 3);
396 /* Interrupt type. Values can be 0(INTA), 1(MSI), 2(MSI_X) */
397 S2IO_PARM_INT(intr_type, 0);
398 /* Large receive offload feature */
399 S2IO_PARM_INT(lro, 0);
400 /* Max pkts to be aggregated by LRO at one time. If not specified,
401  * aggregation happens until we hit max IP pkt size(64K)
402  */
403 S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
404 #ifndef CONFIG_S2IO_NAPI
405 S2IO_PARM_INT(indicate_max_pkts, 0);
406 #endif
407
408 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
409     {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
410 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
411     {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
412 static unsigned int rts_frm_len[MAX_RX_RINGS] =
413     {[0 ...(MAX_RX_RINGS - 1)] = 0 };
414
415 module_param_array(tx_fifo_len, uint, NULL, 0);
416 module_param_array(rx_ring_sz, uint, NULL, 0);
417 module_param_array(rts_frm_len, uint, NULL, 0);
418
419 /*
420  * S2IO device table.
421  * This table lists all the devices that this driver supports.
422  */
423 static struct pci_device_id s2io_tbl[] __devinitdata = {
424         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
425          PCI_ANY_ID, PCI_ANY_ID},
426         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
427          PCI_ANY_ID, PCI_ANY_ID},
428         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
429          PCI_ANY_ID, PCI_ANY_ID},
430         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
431          PCI_ANY_ID, PCI_ANY_ID},
432         {0,}
433 };
434
435 MODULE_DEVICE_TABLE(pci, s2io_tbl);
436
437 static struct pci_driver s2io_driver = {
438       .name = "S2IO",
439       .id_table = s2io_tbl,
440       .probe = s2io_init_nic,
441       .remove = __devexit_p(s2io_rem_nic),
442 };
443
444 /* A simplifier macro used both by init and free shared_mem Fns(). */
445 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
446
447 /**
448  * init_shared_mem - Allocation and Initialization of Memory
449  * @nic: Device private variable.
450  * Description: The function allocates all the memory areas shared
451  * between the NIC and the driver. This includes Tx descriptors,
452  * Rx descriptors and the statistics block.
453  */
454
455 static int init_shared_mem(struct s2io_nic *nic)
456 {
457         u32 size;
458         void *tmp_v_addr, *tmp_v_addr_next;
459         dma_addr_t tmp_p_addr, tmp_p_addr_next;
460         RxD_block_t *pre_rxd_blk = NULL;
461         int i, j, blk_cnt, rx_sz, tx_sz;
462         int lst_size, lst_per_page;
463         struct net_device *dev = nic->dev;
464         unsigned long tmp;
465         buffAdd_t *ba;
466
467         mac_info_t *mac_control;
468         struct config_param *config;
469
470         mac_control = &nic->mac_control;
471         config = &nic->config;
472
473
474         /* Allocation and initialization of TXDLs in FIOFs */
475         size = 0;
476         for (i = 0; i < config->tx_fifo_num; i++) {
477                 size += config->tx_cfg[i].fifo_len;
478         }
479         if (size > MAX_AVAILABLE_TXDS) {
480                 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
481                 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
482                 return -EINVAL;
483         }
484
485         lst_size = (sizeof(TxD_t) * config->max_txds);
486         tx_sz = lst_size * size;
487         lst_per_page = PAGE_SIZE / lst_size;
488
489         for (i = 0; i < config->tx_fifo_num; i++) {
490                 int fifo_len = config->tx_cfg[i].fifo_len;
491                 int list_holder_size = fifo_len * sizeof(list_info_hold_t);
492                 mac_control->fifos[i].list_info = kmalloc(list_holder_size,
493                                                           GFP_KERNEL);
494                 if (!mac_control->fifos[i].list_info) {
495                         DBG_PRINT(ERR_DBG,
496                                   "Malloc failed for list_info\n");
497                         return -ENOMEM;
498                 }
499                 memset(mac_control->fifos[i].list_info, 0, list_holder_size);
500         }
501         for (i = 0; i < config->tx_fifo_num; i++) {
502                 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
503                                                 lst_per_page);
504                 mac_control->fifos[i].tx_curr_put_info.offset = 0;
505                 mac_control->fifos[i].tx_curr_put_info.fifo_len =
506                     config->tx_cfg[i].fifo_len - 1;
507                 mac_control->fifos[i].tx_curr_get_info.offset = 0;
508                 mac_control->fifos[i].tx_curr_get_info.fifo_len =
509                     config->tx_cfg[i].fifo_len - 1;
510                 mac_control->fifos[i].fifo_no = i;
511                 mac_control->fifos[i].nic = nic;
512                 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
513
514                 for (j = 0; j < page_num; j++) {
515                         int k = 0;
516                         dma_addr_t tmp_p;
517                         void *tmp_v;
518                         tmp_v = pci_alloc_consistent(nic->pdev,
519                                                      PAGE_SIZE, &tmp_p);
520                         if (!tmp_v) {
521                                 DBG_PRINT(ERR_DBG,
522                                           "pci_alloc_consistent ");
523                                 DBG_PRINT(ERR_DBG, "failed for TxDL\n");
524                                 return -ENOMEM;
525                         }
526                         /* If we got a zero DMA address(can happen on
527                          * certain platforms like PPC), reallocate.
528                          * Store virtual address of page we don't want,
529                          * to be freed later.
530                          */
531                         if (!tmp_p) {
532                                 mac_control->zerodma_virt_addr = tmp_v;
533                                 DBG_PRINT(INIT_DBG,
534                                 "%s: Zero DMA address for TxDL. ", dev->name);
535                                 DBG_PRINT(INIT_DBG,
536                                 "Virtual address %p\n", tmp_v);
537                                 tmp_v = pci_alloc_consistent(nic->pdev,
538                                                      PAGE_SIZE, &tmp_p);
539                                 if (!tmp_v) {
540                                         DBG_PRINT(ERR_DBG,
541                                           "pci_alloc_consistent ");
542                                         DBG_PRINT(ERR_DBG, "failed for TxDL\n");
543                                         return -ENOMEM;
544                                 }
545                         }
546                         while (k < lst_per_page) {
547                                 int l = (j * lst_per_page) + k;
548                                 if (l == config->tx_cfg[i].fifo_len)
549                                         break;
550                                 mac_control->fifos[i].list_info[l].list_virt_addr =
551                                     tmp_v + (k * lst_size);
552                                 mac_control->fifos[i].list_info[l].list_phy_addr =
553                                     tmp_p + (k * lst_size);
554                                 k++;
555                         }
556                 }
557         }
558
559         nic->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
560         if (!nic->ufo_in_band_v)
561                 return -ENOMEM;
562
563         /* Allocation and initialization of RXDs in Rings */
564         size = 0;
565         for (i = 0; i < config->rx_ring_num; i++) {
566                 if (config->rx_cfg[i].num_rxd %
567                     (rxd_count[nic->rxd_mode] + 1)) {
568                         DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
569                         DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
570                                   i);
571                         DBG_PRINT(ERR_DBG, "RxDs per Block");
572                         return FAILURE;
573                 }
574                 size += config->rx_cfg[i].num_rxd;
575                 mac_control->rings[i].block_count =
576                         config->rx_cfg[i].num_rxd /
577                         (rxd_count[nic->rxd_mode] + 1 );
578                 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
579                         mac_control->rings[i].block_count;
580         }
581         if (nic->rxd_mode == RXD_MODE_1)
582                 size = (size * (sizeof(RxD1_t)));
583         else
584                 size = (size * (sizeof(RxD3_t)));
585         rx_sz = size;
586
587         for (i = 0; i < config->rx_ring_num; i++) {
588                 mac_control->rings[i].rx_curr_get_info.block_index = 0;
589                 mac_control->rings[i].rx_curr_get_info.offset = 0;
590                 mac_control->rings[i].rx_curr_get_info.ring_len =
591                     config->rx_cfg[i].num_rxd - 1;
592                 mac_control->rings[i].rx_curr_put_info.block_index = 0;
593                 mac_control->rings[i].rx_curr_put_info.offset = 0;
594                 mac_control->rings[i].rx_curr_put_info.ring_len =
595                     config->rx_cfg[i].num_rxd - 1;
596                 mac_control->rings[i].nic = nic;
597                 mac_control->rings[i].ring_no = i;
598
599                 blk_cnt = config->rx_cfg[i].num_rxd /
600                                 (rxd_count[nic->rxd_mode] + 1);
601                 /*  Allocating all the Rx blocks */
602                 for (j = 0; j < blk_cnt; j++) {
603                         rx_block_info_t *rx_blocks;
604                         int l;
605
606                         rx_blocks = &mac_control->rings[i].rx_blocks[j];
607                         size = SIZE_OF_BLOCK; //size is always page size
608                         tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
609                                                           &tmp_p_addr);
610                         if (tmp_v_addr == NULL) {
611                                 /*
612                                  * In case of failure, free_shared_mem()
613                                  * is called, which should free any
614                                  * memory that was alloced till the
615                                  * failure happened.
616                                  */
617                                 rx_blocks->block_virt_addr = tmp_v_addr;
618                                 return -ENOMEM;
619                         }
620                         memset(tmp_v_addr, 0, size);
621                         rx_blocks->block_virt_addr = tmp_v_addr;
622                         rx_blocks->block_dma_addr = tmp_p_addr;
623                         rx_blocks->rxds = kmalloc(sizeof(rxd_info_t)*
624                                                   rxd_count[nic->rxd_mode],
625                                                   GFP_KERNEL);
626                         for (l=0; l<rxd_count[nic->rxd_mode];l++) {
627                                 rx_blocks->rxds[l].virt_addr =
628                                         rx_blocks->block_virt_addr +
629                                         (rxd_size[nic->rxd_mode] * l);
630                                 rx_blocks->rxds[l].dma_addr =
631                                         rx_blocks->block_dma_addr +
632                                         (rxd_size[nic->rxd_mode] * l);
633                         }
634                 }
635                 /* Interlinking all Rx Blocks */
636                 for (j = 0; j < blk_cnt; j++) {
637                         tmp_v_addr =
638                                 mac_control->rings[i].rx_blocks[j].block_virt_addr;
639                         tmp_v_addr_next =
640                                 mac_control->rings[i].rx_blocks[(j + 1) %
641                                               blk_cnt].block_virt_addr;
642                         tmp_p_addr =
643                                 mac_control->rings[i].rx_blocks[j].block_dma_addr;
644                         tmp_p_addr_next =
645                                 mac_control->rings[i].rx_blocks[(j + 1) %
646                                               blk_cnt].block_dma_addr;
647
648                         pre_rxd_blk = (RxD_block_t *) tmp_v_addr;
649                         pre_rxd_blk->reserved_2_pNext_RxD_block =
650                             (unsigned long) tmp_v_addr_next;
651                         pre_rxd_blk->pNext_RxD_Blk_physical =
652                             (u64) tmp_p_addr_next;
653                 }
654         }
655         if (nic->rxd_mode >= RXD_MODE_3A) {
656                 /*
657                  * Allocation of Storages for buffer addresses in 2BUFF mode
658                  * and the buffers as well.
659                  */
660                 for (i = 0; i < config->rx_ring_num; i++) {
661                         blk_cnt = config->rx_cfg[i].num_rxd /
662                            (rxd_count[nic->rxd_mode]+ 1);
663                         mac_control->rings[i].ba =
664                                 kmalloc((sizeof(buffAdd_t *) * blk_cnt),
665                                      GFP_KERNEL);
666                         if (!mac_control->rings[i].ba)
667                                 return -ENOMEM;
668                         for (j = 0; j < blk_cnt; j++) {
669                                 int k = 0;
670                                 mac_control->rings[i].ba[j] =
671                                         kmalloc((sizeof(buffAdd_t) *
672                                                 (rxd_count[nic->rxd_mode] + 1)),
673                                                 GFP_KERNEL);
674                                 if (!mac_control->rings[i].ba[j])
675                                         return -ENOMEM;
676                                 while (k != rxd_count[nic->rxd_mode]) {
677                                         ba = &mac_control->rings[i].ba[j][k];
678
679                                         ba->ba_0_org = (void *) kmalloc
680                                             (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
681                                         if (!ba->ba_0_org)
682                                                 return -ENOMEM;
683                                         tmp = (unsigned long)ba->ba_0_org;
684                                         tmp += ALIGN_SIZE;
685                                         tmp &= ~((unsigned long) ALIGN_SIZE);
686                                         ba->ba_0 = (void *) tmp;
687
688                                         ba->ba_1_org = (void *) kmalloc
689                                             (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
690                                         if (!ba->ba_1_org)
691                                                 return -ENOMEM;
692                                         tmp = (unsigned long) ba->ba_1_org;
693                                         tmp += ALIGN_SIZE;
694                                         tmp &= ~((unsigned long) ALIGN_SIZE);
695                                         ba->ba_1 = (void *) tmp;
696                                         k++;
697                                 }
698                         }
699                 }
700         }
701
702         /* Allocation and initialization of Statistics block */
703         size = sizeof(StatInfo_t);
704         mac_control->stats_mem = pci_alloc_consistent
705             (nic->pdev, size, &mac_control->stats_mem_phy);
706
707         if (!mac_control->stats_mem) {
708                 /*
709                  * In case of failure, free_shared_mem() is called, which
710                  * should free any memory that was alloced till the
711                  * failure happened.
712                  */
713                 return -ENOMEM;
714         }
715         mac_control->stats_mem_sz = size;
716
717         tmp_v_addr = mac_control->stats_mem;
718         mac_control->stats_info = (StatInfo_t *) tmp_v_addr;
719         memset(tmp_v_addr, 0, size);
720         DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
721                   (unsigned long long) tmp_p_addr);
722
723         return SUCCESS;
724 }
725
726 /**
727  * free_shared_mem - Free the allocated Memory
728  * @nic:  Device private variable.
729  * Description: This function is to free all memory locations allocated by
730  * the init_shared_mem() function and return it to the kernel.
731  */
732
733 static void free_shared_mem(struct s2io_nic *nic)
734 {
735         int i, j, blk_cnt, size;
736         void *tmp_v_addr;
737         dma_addr_t tmp_p_addr;
738         mac_info_t *mac_control;
739         struct config_param *config;
740         int lst_size, lst_per_page;
741         struct net_device *dev = nic->dev;
742
743         if (!nic)
744                 return;
745
746         mac_control = &nic->mac_control;
747         config = &nic->config;
748
749         lst_size = (sizeof(TxD_t) * config->max_txds);
750         lst_per_page = PAGE_SIZE / lst_size;
751
752         for (i = 0; i < config->tx_fifo_num; i++) {
753                 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
754                                                 lst_per_page);
755                 for (j = 0; j < page_num; j++) {
756                         int mem_blks = (j * lst_per_page);
757                         if (!mac_control->fifos[i].list_info)
758                                 return;
759                         if (!mac_control->fifos[i].list_info[mem_blks].
760                                  list_virt_addr)
761                                 break;
762                         pci_free_consistent(nic->pdev, PAGE_SIZE,
763                                             mac_control->fifos[i].
764                                             list_info[mem_blks].
765                                             list_virt_addr,
766                                             mac_control->fifos[i].
767                                             list_info[mem_blks].
768                                             list_phy_addr);
769                 }
770                 /* If we got a zero DMA address during allocation,
771                  * free the page now
772                  */
773                 if (mac_control->zerodma_virt_addr) {
774                         pci_free_consistent(nic->pdev, PAGE_SIZE,
775                                             mac_control->zerodma_virt_addr,
776                                             (dma_addr_t)0);
777                         DBG_PRINT(INIT_DBG,
778                                 "%s: Freeing TxDL with zero DMA addr. ",
779                                 dev->name);
780                         DBG_PRINT(INIT_DBG, "Virtual address %p\n",
781                                 mac_control->zerodma_virt_addr);
782                 }
783                 kfree(mac_control->fifos[i].list_info);
784         }
785
786         size = SIZE_OF_BLOCK;
787         for (i = 0; i < config->rx_ring_num; i++) {
788                 blk_cnt = mac_control->rings[i].block_count;
789                 for (j = 0; j < blk_cnt; j++) {
790                         tmp_v_addr = mac_control->rings[i].rx_blocks[j].
791                                 block_virt_addr;
792                         tmp_p_addr = mac_control->rings[i].rx_blocks[j].
793                                 block_dma_addr;
794                         if (tmp_v_addr == NULL)
795                                 break;
796                         pci_free_consistent(nic->pdev, size,
797                                             tmp_v_addr, tmp_p_addr);
798                         kfree(mac_control->rings[i].rx_blocks[j].rxds);
799                 }
800         }
801
802         if (nic->rxd_mode >= RXD_MODE_3A) {
803                 /* Freeing buffer storage addresses in 2BUFF mode. */
804                 for (i = 0; i < config->rx_ring_num; i++) {
805                         blk_cnt = config->rx_cfg[i].num_rxd /
806                             (rxd_count[nic->rxd_mode] + 1);
807                         for (j = 0; j < blk_cnt; j++) {
808                                 int k = 0;
809                                 if (!mac_control->rings[i].ba[j])
810                                         continue;
811                                 while (k != rxd_count[nic->rxd_mode]) {
812                                         buffAdd_t *ba =
813                                                 &mac_control->rings[i].ba[j][k];
814                                         kfree(ba->ba_0_org);
815                                         kfree(ba->ba_1_org);
816                                         k++;
817                                 }
818                                 kfree(mac_control->rings[i].ba[j]);
819                         }
820                         kfree(mac_control->rings[i].ba);
821                 }
822         }
823
824         if (mac_control->stats_mem) {
825                 pci_free_consistent(nic->pdev,
826                                     mac_control->stats_mem_sz,
827                                     mac_control->stats_mem,
828                                     mac_control->stats_mem_phy);
829         }
830         if (nic->ufo_in_band_v)
831                 kfree(nic->ufo_in_band_v);
832 }
833
834 /**
835  * s2io_verify_pci_mode -
836  */
837
838 static int s2io_verify_pci_mode(nic_t *nic)
839 {
840         XENA_dev_config_t __iomem *bar0 = nic->bar0;
841         register u64 val64 = 0;
842         int     mode;
843
844         val64 = readq(&bar0->pci_mode);
845         mode = (u8)GET_PCI_MODE(val64);
846
847         if ( val64 & PCI_MODE_UNKNOWN_MODE)
848                 return -1;      /* Unknown PCI mode */
849         return mode;
850 }
851
852 #define NEC_VENID   0x1033
853 #define NEC_DEVID   0x0125
854 static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
855 {
856         struct pci_dev *tdev = NULL;
857         while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
858                 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
859                         if (tdev->bus == s2io_pdev->bus->parent)
860                                 pci_dev_put(tdev);
861                                 return 1;
862                 }
863         }
864         return 0;
865 }
866
867 static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
868 /**
869  * s2io_print_pci_mode -
870  */
871 static int s2io_print_pci_mode(nic_t *nic)
872 {
873         XENA_dev_config_t __iomem *bar0 = nic->bar0;
874         register u64 val64 = 0;
875         int     mode;
876         struct config_param *config = &nic->config;
877
878         val64 = readq(&bar0->pci_mode);
879         mode = (u8)GET_PCI_MODE(val64);
880
881         if ( val64 & PCI_MODE_UNKNOWN_MODE)
882                 return -1;      /* Unknown PCI mode */
883
884         config->bus_speed = bus_speed[mode];
885
886         if (s2io_on_nec_bridge(nic->pdev)) {
887                 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
888                                                         nic->dev->name);
889                 return mode;
890         }
891
892         if (val64 & PCI_MODE_32_BITS) {
893                 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
894         } else {
895                 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
896         }
897
898         switch(mode) {
899                 case PCI_MODE_PCI_33:
900                         DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
901                         break;
902                 case PCI_MODE_PCI_66:
903                         DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
904                         break;
905                 case PCI_MODE_PCIX_M1_66:
906                         DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
907                         break;
908                 case PCI_MODE_PCIX_M1_100:
909                         DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
910                         break;
911                 case PCI_MODE_PCIX_M1_133:
912                         DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
913                         break;
914                 case PCI_MODE_PCIX_M2_66:
915                         DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
916                         break;
917                 case PCI_MODE_PCIX_M2_100:
918                         DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
919                         break;
920                 case PCI_MODE_PCIX_M2_133:
921                         DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
922                         break;
923                 default:
924                         return -1;      /* Unsupported bus speed */
925         }
926
927         return mode;
928 }
929
930 /**
931  *  init_nic - Initialization of hardware
932  *  @nic: device peivate variable
933  *  Description: The function sequentially configures every block
934  *  of the H/W from their reset values.
935  *  Return Value:  SUCCESS on success and
936  *  '-1' on failure (endian settings incorrect).
937  */
938
939 static int init_nic(struct s2io_nic *nic)
940 {
941         XENA_dev_config_t __iomem *bar0 = nic->bar0;
942         struct net_device *dev = nic->dev;
943         register u64 val64 = 0;
944         void __iomem *add;
945         u32 time;
946         int i, j;
947         mac_info_t *mac_control;
948         struct config_param *config;
949         int dtx_cnt = 0;
950         unsigned long long mem_share;
951         int mem_size;
952
953         mac_control = &nic->mac_control;
954         config = &nic->config;
955
956         /* to set the swapper controle on the card */
957         if(s2io_set_swapper(nic)) {
958                 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
959                 return -1;
960         }
961
962         /*
963          * Herc requires EOI to be removed from reset before XGXS, so..
964          */
965         if (nic->device_type & XFRAME_II_DEVICE) {
966                 val64 = 0xA500000000ULL;
967                 writeq(val64, &bar0->sw_reset);
968                 msleep(500);
969                 val64 = readq(&bar0->sw_reset);
970         }
971
972         /* Remove XGXS from reset state */
973         val64 = 0;
974         writeq(val64, &bar0->sw_reset);
975         msleep(500);
976         val64 = readq(&bar0->sw_reset);
977
978         /*  Enable Receiving broadcasts */
979         add = &bar0->mac_cfg;
980         val64 = readq(&bar0->mac_cfg);
981         val64 |= MAC_RMAC_BCAST_ENABLE;
982         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
983         writel((u32) val64, add);
984         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
985         writel((u32) (val64 >> 32), (add + 4));
986
987         /* Read registers in all blocks */
988         val64 = readq(&bar0->mac_int_mask);
989         val64 = readq(&bar0->mc_int_mask);
990         val64 = readq(&bar0->xgxs_int_mask);
991
992         /*  Set MTU */
993         val64 = dev->mtu;
994         writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
995
996         if (nic->device_type & XFRAME_II_DEVICE) {
997                 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
998                         SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
999                                           &bar0->dtx_control, UF);
1000                         if (dtx_cnt & 0x1)
1001                                 msleep(1); /* Necessary!! */
1002                         dtx_cnt++;
1003                 }
1004         } else {
1005                 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1006                         SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1007                                           &bar0->dtx_control, UF);
1008                         val64 = readq(&bar0->dtx_control);
1009                         dtx_cnt++;
1010                 }
1011         }
1012
1013         /*  Tx DMA Initialization */
1014         val64 = 0;
1015         writeq(val64, &bar0->tx_fifo_partition_0);
1016         writeq(val64, &bar0->tx_fifo_partition_1);
1017         writeq(val64, &bar0->tx_fifo_partition_2);
1018         writeq(val64, &bar0->tx_fifo_partition_3);
1019
1020
1021         for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1022                 val64 |=
1023                     vBIT(config->tx_cfg[i].fifo_len - 1, ((i * 32) + 19),
1024                          13) | vBIT(config->tx_cfg[i].fifo_priority,
1025                                     ((i * 32) + 5), 3);
1026
1027                 if (i == (config->tx_fifo_num - 1)) {
1028                         if (i % 2 == 0)
1029                                 i++;
1030                 }
1031
1032                 switch (i) {
1033                 case 1:
1034                         writeq(val64, &bar0->tx_fifo_partition_0);
1035                         val64 = 0;
1036                         break;
1037                 case 3:
1038                         writeq(val64, &bar0->tx_fifo_partition_1);
1039                         val64 = 0;
1040                         break;
1041                 case 5:
1042                         writeq(val64, &bar0->tx_fifo_partition_2);
1043                         val64 = 0;
1044                         break;
1045                 case 7:
1046                         writeq(val64, &bar0->tx_fifo_partition_3);
1047                         break;
1048                 }
1049         }
1050
1051         /*
1052          * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1053          * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1054          */
1055         if ((nic->device_type == XFRAME_I_DEVICE) &&
1056                 (get_xena_rev_id(nic->pdev) < 4))
1057                 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1058
1059         val64 = readq(&bar0->tx_fifo_partition_0);
1060         DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1061                   &bar0->tx_fifo_partition_0, (unsigned long long) val64);
1062
1063         /*
1064          * Initialization of Tx_PA_CONFIG register to ignore packet
1065          * integrity checking.
1066          */
1067         val64 = readq(&bar0->tx_pa_cfg);
1068         val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1069             TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1070         writeq(val64, &bar0->tx_pa_cfg);
1071
1072         /* Rx DMA intialization. */
1073         val64 = 0;
1074         for (i = 0; i < config->rx_ring_num; i++) {
1075                 val64 |=
1076                     vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
1077                          3);
1078         }
1079         writeq(val64, &bar0->rx_queue_priority);
1080
1081         /*
1082          * Allocating equal share of memory to all the
1083          * configured Rings.
1084          */
1085         val64 = 0;
1086         if (nic->device_type & XFRAME_II_DEVICE)
1087                 mem_size = 32;
1088         else
1089                 mem_size = 64;
1090
1091         for (i = 0; i < config->rx_ring_num; i++) {
1092                 switch (i) {
1093                 case 0:
1094                         mem_share = (mem_size / config->rx_ring_num +
1095                                      mem_size % config->rx_ring_num);
1096                         val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1097                         continue;
1098                 case 1:
1099                         mem_share = (mem_size / config->rx_ring_num);
1100                         val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1101                         continue;
1102                 case 2:
1103                         mem_share = (mem_size / config->rx_ring_num);
1104                         val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1105                         continue;
1106                 case 3:
1107                         mem_share = (mem_size / config->rx_ring_num);
1108                         val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1109                         continue;
1110                 case 4:
1111                         mem_share = (mem_size / config->rx_ring_num);
1112                         val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1113                         continue;
1114                 case 5:
1115                         mem_share = (mem_size / config->rx_ring_num);
1116                         val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1117                         continue;
1118                 case 6:
1119                         mem_share = (mem_size / config->rx_ring_num);
1120                         val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1121                         continue;
1122                 case 7:
1123                         mem_share = (mem_size / config->rx_ring_num);
1124                         val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1125                         continue;
1126                 }
1127         }
1128         writeq(val64, &bar0->rx_queue_cfg);
1129
1130         /*
1131          * Filling Tx round robin registers
1132          * as per the number of FIFOs
1133          */
1134         switch (config->tx_fifo_num) {
1135         case 1:
1136                 val64 = 0x0000000000000000ULL;
1137                 writeq(val64, &bar0->tx_w_round_robin_0);
1138                 writeq(val64, &bar0->tx_w_round_robin_1);
1139                 writeq(val64, &bar0->tx_w_round_robin_2);
1140                 writeq(val64, &bar0->tx_w_round_robin_3);
1141                 writeq(val64, &bar0->tx_w_round_robin_4);
1142                 break;
1143         case 2:
1144                 val64 = 0x0000010000010000ULL;
1145                 writeq(val64, &bar0->tx_w_round_robin_0);
1146                 val64 = 0x0100000100000100ULL;
1147                 writeq(val64, &bar0->tx_w_round_robin_1);
1148                 val64 = 0x0001000001000001ULL;
1149                 writeq(val64, &bar0->tx_w_round_robin_2);
1150                 val64 = 0x0000010000010000ULL;
1151                 writeq(val64, &bar0->tx_w_round_robin_3);
1152                 val64 = 0x0100000000000000ULL;
1153                 writeq(val64, &bar0->tx_w_round_robin_4);
1154                 break;
1155         case 3:
1156                 val64 = 0x0001000102000001ULL;
1157                 writeq(val64, &bar0->tx_w_round_robin_0);
1158                 val64 = 0x0001020000010001ULL;
1159                 writeq(val64, &bar0->tx_w_round_robin_1);
1160                 val64 = 0x0200000100010200ULL;
1161                 writeq(val64, &bar0->tx_w_round_robin_2);
1162                 val64 = 0x0001000102000001ULL;
1163                 writeq(val64, &bar0->tx_w_round_robin_3);
1164                 val64 = 0x0001020000000000ULL;
1165                 writeq(val64, &bar0->tx_w_round_robin_4);
1166                 break;
1167         case 4:
1168                 val64 = 0x0001020300010200ULL;
1169                 writeq(val64, &bar0->tx_w_round_robin_0);
1170                 val64 = 0x0100000102030001ULL;
1171                 writeq(val64, &bar0->tx_w_round_robin_1);
1172                 val64 = 0x0200010000010203ULL;
1173                 writeq(val64, &bar0->tx_w_round_robin_2);
1174                 val64 = 0x0001020001000001ULL;
1175                 writeq(val64, &bar0->tx_w_round_robin_3);
1176                 val64 = 0x0203000100000000ULL;
1177                 writeq(val64, &bar0->tx_w_round_robin_4);
1178                 break;
1179         case 5:
1180                 val64 = 0x0001000203000102ULL;
1181                 writeq(val64, &bar0->tx_w_round_robin_0);
1182                 val64 = 0x0001020001030004ULL;
1183                 writeq(val64, &bar0->tx_w_round_robin_1);
1184                 val64 = 0x0001000203000102ULL;
1185                 writeq(val64, &bar0->tx_w_round_robin_2);
1186                 val64 = 0x0001020001030004ULL;
1187                 writeq(val64, &bar0->tx_w_round_robin_3);
1188                 val64 = 0x0001000000000000ULL;
1189                 writeq(val64, &bar0->tx_w_round_robin_4);
1190                 break;
1191         case 6:
1192                 val64 = 0x0001020304000102ULL;
1193                 writeq(val64, &bar0->tx_w_round_robin_0);
1194                 val64 = 0x0304050001020001ULL;
1195                 writeq(val64, &bar0->tx_w_round_robin_1);
1196                 val64 = 0x0203000100000102ULL;
1197                 writeq(val64, &bar0->tx_w_round_robin_2);
1198                 val64 = 0x0304000102030405ULL;
1199                 writeq(val64, &bar0->tx_w_round_robin_3);
1200                 val64 = 0x0001000200000000ULL;
1201                 writeq(val64, &bar0->tx_w_round_robin_4);
1202                 break;
1203         case 7:
1204                 val64 = 0x0001020001020300ULL;
1205                 writeq(val64, &bar0->tx_w_round_robin_0);
1206                 val64 = 0x0102030400010203ULL;
1207                 writeq(val64, &bar0->tx_w_round_robin_1);
1208                 val64 = 0x0405060001020001ULL;
1209                 writeq(val64, &bar0->tx_w_round_robin_2);
1210                 val64 = 0x0304050000010200ULL;
1211                 writeq(val64, &bar0->tx_w_round_robin_3);
1212                 val64 = 0x0102030000000000ULL;
1213                 writeq(val64, &bar0->tx_w_round_robin_4);
1214                 break;
1215         case 8:
1216                 val64 = 0x0001020300040105ULL;
1217                 writeq(val64, &bar0->tx_w_round_robin_0);
1218                 val64 = 0x0200030106000204ULL;
1219                 writeq(val64, &bar0->tx_w_round_robin_1);
1220                 val64 = 0x0103000502010007ULL;
1221                 writeq(val64, &bar0->tx_w_round_robin_2);
1222                 val64 = 0x0304010002060500ULL;
1223                 writeq(val64, &bar0->tx_w_round_robin_3);
1224                 val64 = 0x0103020400000000ULL;
1225                 writeq(val64, &bar0->tx_w_round_robin_4);
1226                 break;
1227         }
1228
1229         /* Enable all configured Tx FIFO partitions */
1230         val64 = readq(&bar0->tx_fifo_partition_0);
1231         val64 |= (TX_FIFO_PARTITION_EN);
1232         writeq(val64, &bar0->tx_fifo_partition_0);
1233
1234         /* Filling the Rx round robin registers as per the
1235          * number of Rings and steering based on QoS.
1236          */
1237         switch (config->rx_ring_num) {
1238         case 1:
1239                 val64 = 0x8080808080808080ULL;
1240                 writeq(val64, &bar0->rts_qos_steering);
1241                 break;
1242         case 2:
1243                 val64 = 0x0000010000010000ULL;
1244                 writeq(val64, &bar0->rx_w_round_robin_0);
1245                 val64 = 0x0100000100000100ULL;
1246                 writeq(val64, &bar0->rx_w_round_robin_1);
1247                 val64 = 0x0001000001000001ULL;
1248                 writeq(val64, &bar0->rx_w_round_robin_2);
1249                 val64 = 0x0000010000010000ULL;
1250                 writeq(val64, &bar0->rx_w_round_robin_3);
1251                 val64 = 0x0100000000000000ULL;
1252                 writeq(val64, &bar0->rx_w_round_robin_4);
1253
1254                 val64 = 0x8080808040404040ULL;
1255                 writeq(val64, &bar0->rts_qos_steering);
1256                 break;
1257         case 3:
1258                 val64 = 0x0001000102000001ULL;
1259                 writeq(val64, &bar0->rx_w_round_robin_0);
1260                 val64 = 0x0001020000010001ULL;
1261                 writeq(val64, &bar0->rx_w_round_robin_1);
1262                 val64 = 0x0200000100010200ULL;
1263                 writeq(val64, &bar0->rx_w_round_robin_2);
1264                 val64 = 0x0001000102000001ULL;
1265                 writeq(val64, &bar0->rx_w_round_robin_3);
1266                 val64 = 0x0001020000000000ULL;
1267                 writeq(val64, &bar0->rx_w_round_robin_4);
1268
1269                 val64 = 0x8080804040402020ULL;
1270                 writeq(val64, &bar0->rts_qos_steering);
1271                 break;
1272         case 4:
1273                 val64 = 0x0001020300010200ULL;
1274                 writeq(val64, &bar0->rx_w_round_robin_0);
1275                 val64 = 0x0100000102030001ULL;
1276                 writeq(val64, &bar0->rx_w_round_robin_1);
1277                 val64 = 0x0200010000010203ULL;
1278                 writeq(val64, &bar0->rx_w_round_robin_2);
1279                 val64 = 0x0001020001000001ULL;
1280                 writeq(val64, &bar0->rx_w_round_robin_3);
1281                 val64 = 0x0203000100000000ULL;
1282                 writeq(val64, &bar0->rx_w_round_robin_4);
1283
1284                 val64 = 0x8080404020201010ULL;
1285                 writeq(val64, &bar0->rts_qos_steering);
1286                 break;
1287         case 5:
1288                 val64 = 0x0001000203000102ULL;
1289                 writeq(val64, &bar0->rx_w_round_robin_0);
1290                 val64 = 0x0001020001030004ULL;
1291                 writeq(val64, &bar0->rx_w_round_robin_1);
1292                 val64 = 0x0001000203000102ULL;
1293                 writeq(val64, &bar0->rx_w_round_robin_2);
1294                 val64 = 0x0001020001030004ULL;
1295                 writeq(val64, &bar0->rx_w_round_robin_3);
1296                 val64 = 0x0001000000000000ULL;
1297                 writeq(val64, &bar0->rx_w_round_robin_4);
1298
1299                 val64 = 0x8080404020201008ULL;
1300                 writeq(val64, &bar0->rts_qos_steering);
1301                 break;
1302         case 6:
1303                 val64 = 0x0001020304000102ULL;
1304                 writeq(val64, &bar0->rx_w_round_robin_0);
1305                 val64 = 0x0304050001020001ULL;
1306                 writeq(val64, &bar0->rx_w_round_robin_1);
1307                 val64 = 0x0203000100000102ULL;
1308                 writeq(val64, &bar0->rx_w_round_robin_2);
1309                 val64 = 0x0304000102030405ULL;
1310                 writeq(val64, &bar0->rx_w_round_robin_3);
1311                 val64 = 0x0001000200000000ULL;
1312                 writeq(val64, &bar0->rx_w_round_robin_4);
1313
1314                 val64 = 0x8080404020100804ULL;
1315                 writeq(val64, &bar0->rts_qos_steering);
1316                 break;
1317         case 7:
1318                 val64 = 0x0001020001020300ULL;
1319                 writeq(val64, &bar0->rx_w_round_robin_0);
1320                 val64 = 0x0102030400010203ULL;
1321                 writeq(val64, &bar0->rx_w_round_robin_1);
1322                 val64 = 0x0405060001020001ULL;
1323                 writeq(val64, &bar0->rx_w_round_robin_2);
1324                 val64 = 0x0304050000010200ULL;
1325                 writeq(val64, &bar0->rx_w_round_robin_3);
1326                 val64 = 0x0102030000000000ULL;
1327                 writeq(val64, &bar0->rx_w_round_robin_4);
1328
1329                 val64 = 0x8080402010080402ULL;
1330                 writeq(val64, &bar0->rts_qos_steering);
1331                 break;
1332         case 8:
1333                 val64 = 0x0001020300040105ULL;
1334                 writeq(val64, &bar0->rx_w_round_robin_0);
1335                 val64 = 0x0200030106000204ULL;
1336                 writeq(val64, &bar0->rx_w_round_robin_1);
1337                 val64 = 0x0103000502010007ULL;
1338                 writeq(val64, &bar0->rx_w_round_robin_2);
1339                 val64 = 0x0304010002060500ULL;
1340                 writeq(val64, &bar0->rx_w_round_robin_3);
1341                 val64 = 0x0103020400000000ULL;
1342                 writeq(val64, &bar0->rx_w_round_robin_4);
1343
1344                 val64 = 0x8040201008040201ULL;
1345                 writeq(val64, &bar0->rts_qos_steering);
1346                 break;
1347         }
1348
1349         /* UDP Fix */
1350         val64 = 0;
1351         for (i = 0; i < 8; i++)
1352                 writeq(val64, &bar0->rts_frm_len_n[i]);
1353
1354         /* Set the default rts frame length for the rings configured */
1355         val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1356         for (i = 0 ; i < config->rx_ring_num ; i++)
1357                 writeq(val64, &bar0->rts_frm_len_n[i]);
1358
1359         /* Set the frame length for the configured rings
1360          * desired by the user
1361          */
1362         for (i = 0; i < config->rx_ring_num; i++) {
1363                 /* If rts_frm_len[i] == 0 then it is assumed that user not
1364                  * specified frame length steering.
1365                  * If the user provides the frame length then program
1366                  * the rts_frm_len register for those values or else
1367                  * leave it as it is.
1368                  */
1369                 if (rts_frm_len[i] != 0) {
1370                         writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1371                                 &bar0->rts_frm_len_n[i]);
1372                 }
1373         }
1374
1375         /* Program statistics memory */
1376         writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1377
1378         if (nic->device_type == XFRAME_II_DEVICE) {
1379                 val64 = STAT_BC(0x320);
1380                 writeq(val64, &bar0->stat_byte_cnt);
1381         }
1382
1383         /*
1384          * Initializing the sampling rate for the device to calculate the
1385          * bandwidth utilization.
1386          */
1387         val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1388             MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1389         writeq(val64, &bar0->mac_link_util);
1390
1391
1392         /*
1393          * Initializing the Transmit and Receive Traffic Interrupt
1394          * Scheme.
1395          */
1396         /*
1397          * TTI Initialization. Default Tx timer gets us about
1398          * 250 interrupts per sec. Continuous interrupts are enabled
1399          * by default.
1400          */
1401         if (nic->device_type == XFRAME_II_DEVICE) {
1402                 int count = (nic->config.bus_speed * 125)/2;
1403                 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1404         } else {
1405
1406                 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1407         }
1408         val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1409             TTI_DATA1_MEM_TX_URNG_B(0x10) |
1410             TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN;
1411                 if (use_continuous_tx_intrs)
1412                         val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1413         writeq(val64, &bar0->tti_data1_mem);
1414
1415         val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1416             TTI_DATA2_MEM_TX_UFC_B(0x20) |
1417             TTI_DATA2_MEM_TX_UFC_C(0x70) | TTI_DATA2_MEM_TX_UFC_D(0x80);
1418         writeq(val64, &bar0->tti_data2_mem);
1419
1420         val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1421         writeq(val64, &bar0->tti_command_mem);
1422
1423         /*
1424          * Once the operation completes, the Strobe bit of the command
1425          * register will be reset. We poll for this particular condition
1426          * We wait for a maximum of 500ms for the operation to complete,
1427          * if it's not complete by then we return error.
1428          */
1429         time = 0;
1430         while (TRUE) {
1431                 val64 = readq(&bar0->tti_command_mem);
1432                 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1433                         break;
1434                 }
1435                 if (time > 10) {
1436                         DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n",
1437                                   dev->name);
1438                         return -1;
1439                 }
1440                 msleep(50);
1441                 time++;
1442         }
1443
1444         if (nic->config.bimodal) {
1445                 int k = 0;
1446                 for (k = 0; k < config->rx_ring_num; k++) {
1447                         val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1448                         val64 |= TTI_CMD_MEM_OFFSET(0x38+k);
1449                         writeq(val64, &bar0->tti_command_mem);
1450
1451                 /*
1452                  * Once the operation completes, the Strobe bit of the command
1453                  * register will be reset. We poll for this particular condition
1454                  * We wait for a maximum of 500ms for the operation to complete,
1455                  * if it's not complete by then we return error.
1456                 */
1457                         time = 0;
1458                         while (TRUE) {
1459                                 val64 = readq(&bar0->tti_command_mem);
1460                                 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1461                                         break;
1462                                 }
1463                                 if (time > 10) {
1464                                         DBG_PRINT(ERR_DBG,
1465                                                 "%s: TTI init Failed\n",
1466                                         dev->name);
1467                                         return -1;
1468                                 }
1469                                 time++;
1470                                 msleep(50);
1471                         }
1472                 }
1473         } else {
1474
1475                 /* RTI Initialization */
1476                 if (nic->device_type == XFRAME_II_DEVICE) {
1477                         /*
1478                          * Programmed to generate Apprx 500 Intrs per
1479                          * second
1480                          */
1481                         int count = (nic->config.bus_speed * 125)/4;
1482                         val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1483                 } else {
1484                         val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1485                 }
1486                 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1487                     RTI_DATA1_MEM_RX_URNG_B(0x10) |
1488                     RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1489
1490                 writeq(val64, &bar0->rti_data1_mem);
1491
1492                 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1493                     RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1494                 if (nic->intr_type == MSI_X)
1495                     val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1496                                 RTI_DATA2_MEM_RX_UFC_D(0x40));
1497                 else
1498                     val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1499                                 RTI_DATA2_MEM_RX_UFC_D(0x80));
1500                 writeq(val64, &bar0->rti_data2_mem);
1501
1502                 for (i = 0; i < config->rx_ring_num; i++) {
1503                         val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1504                                         | RTI_CMD_MEM_OFFSET(i);
1505                         writeq(val64, &bar0->rti_command_mem);
1506
1507                         /*
1508                          * Once the operation completes, the Strobe bit of the
1509                          * command register will be reset. We poll for this
1510                          * particular condition. We wait for a maximum of 500ms
1511                          * for the operation to complete, if it's not complete
1512                          * by then we return error.
1513                          */
1514                         time = 0;
1515                         while (TRUE) {
1516                                 val64 = readq(&bar0->rti_command_mem);
1517                                 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) {
1518                                         break;
1519                                 }
1520                                 if (time > 10) {
1521                                         DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1522                                                   dev->name);
1523                                         return -1;
1524                                 }
1525                                 time++;
1526                                 msleep(50);
1527                         }
1528                 }
1529         }
1530
1531         /*
1532          * Initializing proper values as Pause threshold into all
1533          * the 8 Queues on Rx side.
1534          */
1535         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1536         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1537
1538         /* Disable RMAC PAD STRIPPING */
1539         add = &bar0->mac_cfg;
1540         val64 = readq(&bar0->mac_cfg);
1541         val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1542         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1543         writel((u32) (val64), add);
1544         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1545         writel((u32) (val64 >> 32), (add + 4));
1546         val64 = readq(&bar0->mac_cfg);
1547
1548         /* Enable FCS stripping by adapter */
1549         add = &bar0->mac_cfg;
1550         val64 = readq(&bar0->mac_cfg);
1551         val64 |= MAC_CFG_RMAC_STRIP_FCS;
1552         if (nic->device_type == XFRAME_II_DEVICE)
1553                 writeq(val64, &bar0->mac_cfg);
1554         else {
1555                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1556                 writel((u32) (val64), add);
1557                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1558                 writel((u32) (val64 >> 32), (add + 4));
1559         }
1560
1561         /*
1562          * Set the time value to be inserted in the pause frame
1563          * generated by xena.
1564          */
1565         val64 = readq(&bar0->rmac_pause_cfg);
1566         val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1567         val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1568         writeq(val64, &bar0->rmac_pause_cfg);
1569
1570         /*
1571          * Set the Threshold Limit for Generating the pause frame
1572          * If the amount of data in any Queue exceeds ratio of
1573          * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1574          * pause frame is generated
1575          */
1576         val64 = 0;
1577         for (i = 0; i < 4; i++) {
1578                 val64 |=
1579                     (((u64) 0xFF00 | nic->mac_control.
1580                       mc_pause_threshold_q0q3)
1581                      << (i * 2 * 8));
1582         }
1583         writeq(val64, &bar0->mc_pause_thresh_q0q3);
1584
1585         val64 = 0;
1586         for (i = 0; i < 4; i++) {
1587                 val64 |=
1588                     (((u64) 0xFF00 | nic->mac_control.
1589                       mc_pause_threshold_q4q7)
1590                      << (i * 2 * 8));
1591         }
1592         writeq(val64, &bar0->mc_pause_thresh_q4q7);
1593
1594         /*
1595          * TxDMA will stop Read request if the number of read split has
1596          * exceeded the limit pointed by shared_splits
1597          */
1598         val64 = readq(&bar0->pic_control);
1599         val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1600         writeq(val64, &bar0->pic_control);
1601
1602         if (nic->config.bus_speed == 266) {
1603                 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1604                 writeq(0x0, &bar0->read_retry_delay);
1605                 writeq(0x0, &bar0->write_retry_delay);
1606         }
1607
1608         /*
1609          * Programming the Herc to split every write transaction
1610          * that does not start on an ADB to reduce disconnects.
1611          */
1612         if (nic->device_type == XFRAME_II_DEVICE) {
1613                 val64 = EXT_REQ_EN | MISC_LINK_STABILITY_PRD(3);
1614                 writeq(val64, &bar0->misc_control);
1615                 val64 = readq(&bar0->pic_control2);
1616                 val64 &= ~(BIT(13)|BIT(14)|BIT(15));
1617                 writeq(val64, &bar0->pic_control2);
1618         }
1619         if (strstr(nic->product_name, "CX4")) {
1620                 val64 = TMAC_AVG_IPG(0x17);
1621                 writeq(val64, &bar0->tmac_avg_ipg);
1622         }
1623
1624         return SUCCESS;
1625 }
1626 #define LINK_UP_DOWN_INTERRUPT          1
1627 #define MAC_RMAC_ERR_TIMER              2
1628
1629 static int s2io_link_fault_indication(nic_t *nic)
1630 {
1631         if (nic->intr_type != INTA)
1632                 return MAC_RMAC_ERR_TIMER;
1633         if (nic->device_type == XFRAME_II_DEVICE)
1634                 return LINK_UP_DOWN_INTERRUPT;
1635         else
1636                 return MAC_RMAC_ERR_TIMER;
1637 }
1638
1639 /**
1640  *  en_dis_able_nic_intrs - Enable or Disable the interrupts
1641  *  @nic: device private variable,
1642  *  @mask: A mask indicating which Intr block must be modified and,
1643  *  @flag: A flag indicating whether to enable or disable the Intrs.
1644  *  Description: This function will either disable or enable the interrupts
1645  *  depending on the flag argument. The mask argument can be used to
1646  *  enable/disable any Intr block.
1647  *  Return Value: NONE.
1648  */
1649
1650 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1651 {
1652         XENA_dev_config_t __iomem *bar0 = nic->bar0;
1653         register u64 val64 = 0, temp64 = 0;
1654
1655         /*  Top level interrupt classification */
1656         /*  PIC Interrupts */
1657         if ((mask & (TX_PIC_INTR | RX_PIC_INTR))) {
1658                 /*  Enable PIC Intrs in the general intr mask register */
1659                 val64 = TXPIC_INT_M | PIC_RX_INT_M;
1660                 if (flag == ENABLE_INTRS) {
1661                         temp64 = readq(&bar0->general_int_mask);
1662                         temp64 &= ~((u64) val64);
1663                         writeq(temp64, &bar0->general_int_mask);
1664                         /*
1665                          * If Hercules adapter enable GPIO otherwise
1666                          * disable all PCIX, Flash, MDIO, IIC and GPIO
1667                          * interrupts for now.
1668                          * TODO
1669                          */
1670                         if (s2io_link_fault_indication(nic) ==
1671                                         LINK_UP_DOWN_INTERRUPT ) {
1672                                 temp64 = readq(&bar0->pic_int_mask);
1673                                 temp64 &= ~((u64) PIC_INT_GPIO);
1674                                 writeq(temp64, &bar0->pic_int_mask);
1675                                 temp64 = readq(&bar0->gpio_int_mask);
1676                                 temp64 &= ~((u64) GPIO_INT_MASK_LINK_UP);
1677                                 writeq(temp64, &bar0->gpio_int_mask);
1678                         } else {
1679                                 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1680                         }
1681                         /*
1682                          * No MSI Support is available presently, so TTI and
1683                          * RTI interrupts are also disabled.
1684                          */
1685                 } else if (flag == DISABLE_INTRS) {
1686                         /*
1687                          * Disable PIC Intrs in the general
1688                          * intr mask register
1689                          */
1690                         writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1691                         temp64 = readq(&bar0->general_int_mask);
1692                         val64 |= temp64;
1693                         writeq(val64, &bar0->general_int_mask);
1694                 }
1695         }
1696
1697         /*  DMA Interrupts */
1698         /*  Enabling/Disabling Tx DMA interrupts */
1699         if (mask & TX_DMA_INTR) {
1700                 /* Enable TxDMA Intrs in the general intr mask register */
1701                 val64 = TXDMA_INT_M;
1702                 if (flag == ENABLE_INTRS) {
1703                         temp64 = readq(&bar0->general_int_mask);
1704                         temp64 &= ~((u64) val64);
1705                         writeq(temp64, &bar0->general_int_mask);
1706                         /*
1707                          * Keep all interrupts other than PFC interrupt
1708                          * and PCC interrupt disabled in DMA level.
1709                          */
1710                         val64 = DISABLE_ALL_INTRS & ~(TXDMA_PFC_INT_M |
1711                                                       TXDMA_PCC_INT_M);
1712                         writeq(val64, &bar0->txdma_int_mask);
1713                         /*
1714                          * Enable only the MISC error 1 interrupt in PFC block
1715                          */
1716                         val64 = DISABLE_ALL_INTRS & (~PFC_MISC_ERR_1);
1717                         writeq(val64, &bar0->pfc_err_mask);
1718                         /*
1719                          * Enable only the FB_ECC error interrupt in PCC block
1720                          */
1721                         val64 = DISABLE_ALL_INTRS & (~PCC_FB_ECC_ERR);
1722                         writeq(val64, &bar0->pcc_err_mask);
1723                 } else if (flag == DISABLE_INTRS) {
1724                         /*
1725                          * Disable TxDMA Intrs in the general intr mask
1726                          * register
1727                          */
1728                         writeq(DISABLE_ALL_INTRS, &bar0->txdma_int_mask);
1729                         writeq(DISABLE_ALL_INTRS, &bar0->pfc_err_mask);
1730                         temp64 = readq(&bar0->general_int_mask);
1731                         val64 |= temp64;
1732                         writeq(val64, &bar0->general_int_mask);
1733                 }
1734         }
1735
1736         /*  Enabling/Disabling Rx DMA interrupts */
1737         if (mask & RX_DMA_INTR) {
1738                 /*  Enable RxDMA Intrs in the general intr mask register */
1739                 val64 = RXDMA_INT_M;
1740                 if (flag == ENABLE_INTRS) {
1741                         temp64 = readq(&bar0->general_int_mask);
1742                         temp64 &= ~((u64) val64);
1743                         writeq(temp64, &bar0->general_int_mask);
1744                         /*
1745                          * All RxDMA block interrupts are disabled for now
1746                          * TODO
1747                          */
1748                         writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
1749                 } else if (flag == DISABLE_INTRS) {
1750                         /*
1751                          * Disable RxDMA Intrs in the general intr mask
1752                          * register
1753                          */
1754                         writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
1755                         temp64 = readq(&bar0->general_int_mask);
1756                         val64 |= temp64;
1757                         writeq(val64, &bar0->general_int_mask);
1758                 }
1759         }
1760
1761         /*  MAC Interrupts */
1762         /*  Enabling/Disabling MAC interrupts */
1763         if (mask & (TX_MAC_INTR | RX_MAC_INTR)) {
1764                 val64 = TXMAC_INT_M | RXMAC_INT_M;
1765                 if (flag == ENABLE_INTRS) {
1766                         temp64 = readq(&bar0->general_int_mask);
1767                         temp64 &= ~((u64) val64);
1768                         writeq(temp64, &bar0->general_int_mask);
1769                         /*
1770                          * All MAC block error interrupts are disabled for now
1771                          * TODO
1772                          */
1773                 } else if (flag == DISABLE_INTRS) {
1774                         /*
1775                          * Disable MAC Intrs in the general intr mask register
1776                          */
1777                         writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask);
1778                         writeq(DISABLE_ALL_INTRS,
1779                                &bar0->mac_rmac_err_mask);
1780
1781                         temp64 = readq(&bar0->general_int_mask);
1782                         val64 |= temp64;
1783                         writeq(val64, &bar0->general_int_mask);
1784                 }
1785         }
1786
1787         /*  XGXS Interrupts */
1788         if (mask & (TX_XGXS_INTR | RX_XGXS_INTR)) {
1789                 val64 = TXXGXS_INT_M | RXXGXS_INT_M;
1790                 if (flag == ENABLE_INTRS) {
1791                         temp64 = readq(&bar0->general_int_mask);
1792                         temp64 &= ~((u64) val64);
1793                         writeq(temp64, &bar0->general_int_mask);
1794                         /*
1795                          * All XGXS block error interrupts are disabled for now
1796                          * TODO
1797                          */
1798                         writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
1799                 } else if (flag == DISABLE_INTRS) {
1800                         /*
1801                          * Disable MC Intrs in the general intr mask register
1802                          */
1803                         writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
1804                         temp64 = readq(&bar0->general_int_mask);
1805                         val64 |= temp64;
1806                         writeq(val64, &bar0->general_int_mask);
1807                 }
1808         }
1809
1810         /*  Memory Controller(MC) interrupts */
1811         if (mask & MC_INTR) {
1812                 val64 = MC_INT_M;
1813                 if (flag == ENABLE_INTRS) {
1814                         temp64 = readq(&bar0->general_int_mask);
1815                         temp64 &= ~((u64) val64);
1816                         writeq(temp64, &bar0->general_int_mask);
1817                         /*
1818                          * Enable all MC Intrs.
1819                          */
1820                         writeq(0x0, &bar0->mc_int_mask);
1821                         writeq(0x0, &bar0->mc_err_mask);
1822                 } else if (flag == DISABLE_INTRS) {
1823                         /*
1824                          * Disable MC Intrs in the general intr mask register
1825                          */
1826                         writeq(DISABLE_ALL_INTRS, &bar0->mc_int_mask);
1827                         temp64 = readq(&bar0->general_int_mask);
1828                         val64 |= temp64;
1829                         writeq(val64, &bar0->general_int_mask);
1830                 }
1831         }
1832
1833
1834         /*  Tx traffic interrupts */
1835         if (mask & TX_TRAFFIC_INTR) {
1836                 val64 = TXTRAFFIC_INT_M;
1837                 if (flag == ENABLE_INTRS) {
1838                         temp64 = readq(&bar0->general_int_mask);
1839                         temp64 &= ~((u64) val64);
1840                         writeq(temp64, &bar0->general_int_mask);
1841                         /*
1842                          * Enable all the Tx side interrupts
1843                          * writing 0 Enables all 64 TX interrupt levels
1844                          */
1845                         writeq(0x0, &bar0->tx_traffic_mask);
1846                 } else if (flag == DISABLE_INTRS) {
1847                         /*
1848                          * Disable Tx Traffic Intrs in the general intr mask
1849                          * register.
1850                          */
1851                         writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1852                         temp64 = readq(&bar0->general_int_mask);
1853                         val64 |= temp64;
1854                         writeq(val64, &bar0->general_int_mask);
1855                 }
1856         }
1857
1858         /*  Rx traffic interrupts */
1859         if (mask & RX_TRAFFIC_INTR) {
1860                 val64 = RXTRAFFIC_INT_M;
1861                 if (flag == ENABLE_INTRS) {
1862                         temp64 = readq(&bar0->general_int_mask);
1863                         temp64 &= ~((u64) val64);
1864                         writeq(temp64, &bar0->general_int_mask);
1865                         /* writing 0 Enables all 8 RX interrupt levels */
1866                         writeq(0x0, &bar0->rx_traffic_mask);
1867                 } else if (flag == DISABLE_INTRS) {
1868                         /*
1869                          * Disable Rx Traffic Intrs in the general intr mask
1870                          * register.
1871                          */
1872                         writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1873                         temp64 = readq(&bar0->general_int_mask);
1874                         val64 |= temp64;
1875                         writeq(val64, &bar0->general_int_mask);
1876                 }
1877         }
1878 }
1879
1880 static int check_prc_pcc_state(u64 val64, int flag, int rev_id, int herc)
1881 {
1882         int ret = 0;
1883
1884         if (flag == FALSE) {
1885                 if ((!herc && (rev_id >= 4)) || herc) {
1886                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) &&
1887                             ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1888                              ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1889                                 ret = 1;
1890                         }
1891                 }else {
1892                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) &&
1893                             ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1894                              ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1895                                 ret = 1;
1896                         }
1897                 }
1898         } else {
1899                 if ((!herc && (rev_id >= 4)) || herc) {
1900                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
1901                              ADAPTER_STATUS_RMAC_PCC_IDLE) &&
1902                             (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
1903                              ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1904                               ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
1905                                 ret = 1;
1906                         }
1907                 } else {
1908                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
1909                              ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) &&
1910                             (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
1911                              ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1912                               ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
1913                                 ret = 1;
1914                         }
1915                 }
1916         }
1917
1918         return ret;
1919 }
1920 /**
1921  *  verify_xena_quiescence - Checks whether the H/W is ready
1922  *  @val64 :  Value read from adapter status register.
1923  *  @flag : indicates if the adapter enable bit was ever written once
1924  *  before.
1925  *  Description: Returns whether the H/W is ready to go or not. Depending
1926  *  on whether adapter enable bit was written or not the comparison
1927  *  differs and the calling function passes the input argument flag to
1928  *  indicate this.
1929  *  Return: 1 If xena is quiescence
1930  *          0 If Xena is not quiescence
1931  */
1932
1933 static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag)
1934 {
1935         int ret = 0, herc;
1936         u64 tmp64 = ~((u64) val64);
1937         int rev_id = get_xena_rev_id(sp->pdev);
1938
1939         herc = (sp->device_type == XFRAME_II_DEVICE);
1940         if (!
1941             (tmp64 &
1942              (ADAPTER_STATUS_TDMA_READY | ADAPTER_STATUS_RDMA_READY |
1943               ADAPTER_STATUS_PFC_READY | ADAPTER_STATUS_TMAC_BUF_EMPTY |
1944               ADAPTER_STATUS_PIC_QUIESCENT | ADAPTER_STATUS_MC_DRAM_READY |
1945               ADAPTER_STATUS_MC_QUEUES_READY | ADAPTER_STATUS_M_PLL_LOCK |
1946               ADAPTER_STATUS_P_PLL_LOCK))) {
1947                 ret = check_prc_pcc_state(val64, flag, rev_id, herc);
1948         }
1949
1950         return ret;
1951 }
1952
1953 /**
1954  * fix_mac_address -  Fix for Mac addr problem on Alpha platforms
1955  * @sp: Pointer to device specifc structure
1956  * Description :
1957  * New procedure to clear mac address reading  problems on Alpha platforms
1958  *
1959  */
1960
1961 static void fix_mac_address(nic_t * sp)
1962 {
1963         XENA_dev_config_t __iomem *bar0 = sp->bar0;
1964         u64 val64;
1965         int i = 0;
1966
1967         while (fix_mac[i] != END_SIGN) {
1968                 writeq(fix_mac[i++], &bar0->gpio_control);
1969                 udelay(10);
1970                 val64 = readq(&bar0->gpio_control);
1971         }
1972 }
1973
1974 /**
1975  *  start_nic - Turns the device on
1976  *  @nic : device private variable.
1977  *  Description:
1978  *  This function actually turns the device on. Before this  function is
1979  *  called,all Registers are configured from their reset states
1980  *  and shared memory is allocated but the NIC is still quiescent. On
1981  *  calling this function, the device interrupts are cleared and the NIC is
1982  *  literally switched on by writing into the adapter control register.
1983  *  Return Value:
1984  *  SUCCESS on success and -1 on failure.
1985  */
1986
1987 static int start_nic(struct s2io_nic *nic)
1988 {
1989         XENA_dev_config_t __iomem *bar0 = nic->bar0;
1990         struct net_device *dev = nic->dev;
1991         register u64 val64 = 0;
1992         u16 subid, i;
1993         mac_info_t *mac_control;
1994         struct config_param *config;
1995
1996         mac_control = &nic->mac_control;
1997         config = &nic->config;
1998
1999         /*  PRC Initialization and configuration */
2000         for (i = 0; i < config->rx_ring_num; i++) {
2001                 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
2002                        &bar0->prc_rxd0_n[i]);
2003
2004                 val64 = readq(&bar0->prc_ctrl_n[i]);
2005                 if (nic->config.bimodal)
2006                         val64 |= PRC_CTRL_BIMODAL_INTERRUPT;
2007                 if (nic->rxd_mode == RXD_MODE_1)
2008                         val64 |= PRC_CTRL_RC_ENABLED;
2009                 else
2010                         val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
2011                 if (nic->device_type == XFRAME_II_DEVICE)
2012                         val64 |= PRC_CTRL_GROUP_READS;
2013                 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2014                 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2015                 writeq(val64, &bar0->prc_ctrl_n[i]);
2016         }
2017
2018         if (nic->rxd_mode == RXD_MODE_3B) {
2019                 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2020                 val64 = readq(&bar0->rx_pa_cfg);
2021                 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2022                 writeq(val64, &bar0->rx_pa_cfg);
2023         }
2024
2025         /*
2026          * Enabling MC-RLDRAM. After enabling the device, we timeout
2027          * for around 100ms, which is approximately the time required
2028          * for the device to be ready for operation.
2029          */
2030         val64 = readq(&bar0->mc_rldram_mrs);
2031         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2032         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2033         val64 = readq(&bar0->mc_rldram_mrs);
2034
2035         msleep(100);    /* Delay by around 100 ms. */
2036
2037         /* Enabling ECC Protection. */
2038         val64 = readq(&bar0->adapter_control);
2039         val64 &= ~ADAPTER_ECC_EN;
2040         writeq(val64, &bar0->adapter_control);
2041
2042         /*
2043          * Clearing any possible Link state change interrupts that
2044          * could have popped up just before Enabling the card.
2045          */
2046         val64 = readq(&bar0->mac_rmac_err_reg);
2047         if (val64)
2048                 writeq(val64, &bar0->mac_rmac_err_reg);
2049
2050         /*
2051          * Verify if the device is ready to be enabled, if so enable
2052          * it.
2053          */
2054         val64 = readq(&bar0->adapter_status);
2055         if (!verify_xena_quiescence(nic, val64, nic->device_enabled_once)) {
2056                 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2057                 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
2058                           (unsigned long long) val64);
2059                 return FAILURE;
2060         }
2061
2062         /*
2063          * With some switches, link might be already up at this point.
2064          * Because of this weird behavior, when we enable laser,
2065          * we may not get link. We need to handle this. We cannot
2066          * figure out which switch is misbehaving. So we are forced to
2067          * make a global change.
2068          */
2069
2070         /* Enabling Laser. */
2071         val64 = readq(&bar0->adapter_control);
2072         val64 |= ADAPTER_EOI_TX_ON;
2073         writeq(val64, &bar0->adapter_control);
2074
2075         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2076                 /*
2077                  * Dont see link state interrupts initally on some switches,
2078                  * so directly scheduling the link state task here.
2079                  */
2080                 schedule_work(&nic->set_link_task);
2081         }
2082         /* SXE-002: Initialize link and activity LED */
2083         subid = nic->pdev->subsystem_device;
2084         if (((subid & 0xFF) >= 0x07) &&
2085             (nic->device_type == XFRAME_I_DEVICE)) {
2086                 val64 = readq(&bar0->gpio_control);
2087                 val64 |= 0x0000800000000000ULL;
2088                 writeq(val64, &bar0->gpio_control);
2089                 val64 = 0x0411040400000000ULL;
2090                 writeq(val64, (void __iomem *)bar0 + 0x2700);
2091         }
2092
2093         return SUCCESS;
2094 }
2095 /**
2096  * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2097  */
2098 static struct sk_buff *s2io_txdl_getskb(fifo_info_t *fifo_data, TxD_t *txdlp, int get_off)
2099 {
2100         nic_t *nic = fifo_data->nic;
2101         struct sk_buff *skb;
2102         TxD_t *txds;
2103         u16 j, frg_cnt;
2104
2105         txds = txdlp;
2106         if (txds->Host_Control == (u64)(long)nic->ufo_in_band_v) {
2107                 pci_unmap_single(nic->pdev, (dma_addr_t)
2108                         txds->Buffer_Pointer, sizeof(u64),
2109                         PCI_DMA_TODEVICE);
2110                 txds++;
2111         }
2112
2113         skb = (struct sk_buff *) ((unsigned long)
2114                         txds->Host_Control);
2115         if (!skb) {
2116                 memset(txdlp, 0, (sizeof(TxD_t) * fifo_data->max_txds));
2117                 return NULL;
2118         }
2119         pci_unmap_single(nic->pdev, (dma_addr_t)
2120                          txds->Buffer_Pointer,
2121                          skb->len - skb->data_len,
2122                          PCI_DMA_TODEVICE);
2123         frg_cnt = skb_shinfo(skb)->nr_frags;
2124         if (frg_cnt) {
2125                 txds++;
2126                 for (j = 0; j < frg_cnt; j++, txds++) {
2127                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2128                         if (!txds->Buffer_Pointer)
2129                                 break;
2130                         pci_unmap_page(nic->pdev, (dma_addr_t)
2131                                         txds->Buffer_Pointer,
2132                                        frag->size, PCI_DMA_TODEVICE);
2133                 }
2134         }
2135         memset(txdlp,0, (sizeof(TxD_t) * fifo_data->max_txds));
2136         return(skb);
2137 }
2138
2139 /**
2140  *  free_tx_buffers - Free all queued Tx buffers
2141  *  @nic : device private variable.
2142  *  Description:
2143  *  Free all queued Tx buffers.
2144  *  Return Value: void
2145 */
2146
2147 static void free_tx_buffers(struct s2io_nic *nic)
2148 {
2149         struct net_device *dev = nic->dev;
2150         struct sk_buff *skb;
2151         TxD_t *txdp;
2152         int i, j;
2153         mac_info_t *mac_control;
2154         struct config_param *config;
2155         int cnt = 0;
2156
2157         mac_control = &nic->mac_control;
2158         config = &nic->config;
2159
2160         for (i = 0; i < config->tx_fifo_num; i++) {
2161                 for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) {
2162                         txdp = (TxD_t *) mac_control->fifos[i].list_info[j].
2163                             list_virt_addr;
2164                         skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2165                         if (skb) {
2166                                 dev_kfree_skb(skb);
2167                                 cnt++;
2168                         }
2169                 }
2170                 DBG_PRINT(INTR_DBG,
2171                           "%s:forcibly freeing %d skbs on FIFO%d\n",
2172                           dev->name, cnt, i);
2173                 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2174                 mac_control->fifos[i].tx_curr_put_info.offset = 0;
2175         }
2176 }
2177
2178 /**
2179  *   stop_nic -  To stop the nic
2180  *   @nic ; device private variable.
2181  *   Description:
2182  *   This function does exactly the opposite of what the start_nic()
2183  *   function does. This function is called to stop the device.
2184  *   Return Value:
2185  *   void.
2186  */
2187
2188 static void stop_nic(struct s2io_nic *nic)
2189 {
2190         XENA_dev_config_t __iomem *bar0 = nic->bar0;
2191         register u64 val64 = 0;
2192         u16 interruptible;
2193         mac_info_t *mac_control;
2194         struct config_param *config;
2195
2196         mac_control = &nic->mac_control;
2197         config = &nic->config;
2198
2199         /*  Disable all interrupts */
2200         interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2201         interruptible |= TX_PIC_INTR | RX_PIC_INTR;
2202         interruptible |= TX_MAC_INTR | RX_MAC_INTR;
2203         en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2204
2205         /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2206         val64 = readq(&bar0->adapter_control);
2207         val64 &= ~(ADAPTER_CNTL_EN);
2208         writeq(val64, &bar0->adapter_control);
2209 }
2210
2211 static int fill_rxd_3buf(nic_t *nic, RxD_t *rxdp, struct sk_buff *skb)
2212 {
2213         struct net_device *dev = nic->dev;
2214         struct sk_buff *frag_list;
2215         void *tmp;
2216
2217         /* Buffer-1 receives L3/L4 headers */
2218         ((RxD3_t*)rxdp)->Buffer1_ptr = pci_map_single
2219                         (nic->pdev, skb->data, l3l4hdr_size + 4,
2220                         PCI_DMA_FROMDEVICE);
2221
2222         /* skb_shinfo(skb)->frag_list will have L4 data payload */
2223         skb_shinfo(skb)->frag_list = dev_alloc_skb(dev->mtu + ALIGN_SIZE);
2224         if (skb_shinfo(skb)->frag_list == NULL) {
2225                 DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb failed\n ", dev->name);
2226                 return -ENOMEM ;
2227         }
2228         frag_list = skb_shinfo(skb)->frag_list;
2229         frag_list->next = NULL;
2230         tmp = (void *)ALIGN((long)frag_list->data, ALIGN_SIZE + 1);
2231         frag_list->data = tmp;
2232         frag_list->tail = tmp;
2233
2234         /* Buffer-2 receives L4 data payload */
2235         ((RxD3_t*)rxdp)->Buffer2_ptr = pci_map_single(nic->pdev,
2236                                 frag_list->data, dev->mtu,
2237                                 PCI_DMA_FROMDEVICE);
2238         rxdp->Control_2 |= SET_BUFFER1_SIZE_3(l3l4hdr_size + 4);
2239         rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu);
2240
2241         return SUCCESS;
2242 }
2243
2244 /**
2245  *  fill_rx_buffers - Allocates the Rx side skbs
2246  *  @nic:  device private variable
2247  *  @ring_no: ring number
2248  *  Description:
2249  *  The function allocates Rx side skbs and puts the physical
2250  *  address of these buffers into the RxD buffer pointers, so that the NIC
2251  *  can DMA the received frame into these locations.
2252  *  The NIC supports 3 receive modes, viz
2253  *  1. single buffer,
2254  *  2. three buffer and
2255  *  3. Five buffer modes.
2256  *  Each mode defines how many fragments the received frame will be split
2257  *  up into by the NIC. The frame is split into L3 header, L4 Header,
2258  *  L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2259  *  is split into 3 fragments. As of now only single buffer mode is
2260  *  supported.
2261  *   Return Value:
2262  *  SUCCESS on success or an appropriate -ve value on failure.
2263  */
2264
2265 static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
2266 {
2267         struct net_device *dev = nic->dev;
2268         struct sk_buff *skb;
2269         RxD_t *rxdp;
2270         int off, off1, size, block_no, block_no1;
2271         u32 alloc_tab = 0;
2272         u32 alloc_cnt;
2273         mac_info_t *mac_control;
2274         struct config_param *config;
2275         u64 tmp;
2276         buffAdd_t *ba;
2277 #ifndef CONFIG_S2IO_NAPI
2278         unsigned long flags;
2279 #endif
2280         RxD_t *first_rxdp = NULL;
2281
2282         mac_control = &nic->mac_control;
2283         config = &nic->config;
2284         alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
2285             atomic_read(&nic->rx_bufs_left[ring_no]);
2286
2287         block_no1 = mac_control->rings[ring_no].rx_curr_get_info.block_index;
2288         off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
2289         while (alloc_tab < alloc_cnt) {
2290                 block_no = mac_control->rings[ring_no].rx_curr_put_info.
2291                     block_index;
2292                 off = mac_control->rings[ring_no].rx_curr_put_info.offset;
2293
2294                 rxdp = mac_control->rings[ring_no].
2295                                 rx_blocks[block_no].rxds[off].virt_addr;
2296
2297                 if ((block_no == block_no1) && (off == off1) &&
2298                                         (rxdp->Host_Control)) {
2299                         DBG_PRINT(INTR_DBG, "%s: Get and Put",
2300                                   dev->name);
2301                         DBG_PRINT(INTR_DBG, " info equated\n");
2302                         goto end;
2303                 }
2304                 if (off && (off == rxd_count[nic->rxd_mode])) {
2305                         mac_control->rings[ring_no].rx_curr_put_info.
2306                             block_index++;
2307                         if (mac_control->rings[ring_no].rx_curr_put_info.
2308                             block_index == mac_control->rings[ring_no].
2309                                         block_count)
2310                                 mac_control->rings[ring_no].rx_curr_put_info.
2311                                         block_index = 0;
2312                         block_no = mac_control->rings[ring_no].
2313                                         rx_curr_put_info.block_index;
2314                         if (off == rxd_count[nic->rxd_mode])
2315                                 off = 0;
2316                         mac_control->rings[ring_no].rx_curr_put_info.
2317                                 offset = off;
2318                         rxdp = mac_control->rings[ring_no].
2319                                 rx_blocks[block_no].block_virt_addr;
2320                         DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2321                                   dev->name, rxdp);
2322                 }
2323 #ifndef CONFIG_S2IO_NAPI
2324                 spin_lock_irqsave(&nic->put_lock, flags);
2325                 mac_control->rings[ring_no].put_pos =
2326                     (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2327                 spin_unlock_irqrestore(&nic->put_lock, flags);
2328 #endif
2329                 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2330                         ((nic->rxd_mode >= RXD_MODE_3A) &&
2331                                 (rxdp->Control_2 & BIT(0)))) {
2332                         mac_control->rings[ring_no].rx_curr_put_info.
2333                                         offset = off;
2334                         goto end;
2335                 }
2336                 /* calculate size of skb based on ring mode */
2337                 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
2338                                 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2339                 if (nic->rxd_mode == RXD_MODE_1)
2340                         size += NET_IP_ALIGN;
2341                 else if (nic->rxd_mode == RXD_MODE_3B)
2342                         size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2343                 else
2344                         size = l3l4hdr_size + ALIGN_SIZE + BUF0_LEN + 4;
2345
2346                 /* allocate skb */
2347                 skb = dev_alloc_skb(size);
2348                 if(!skb) {
2349                         DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);
2350                         DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");
2351                         if (first_rxdp) {
2352                                 wmb();
2353                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2354                         }
2355                         return -ENOMEM ;
2356                 }
2357                 if (nic->rxd_mode == RXD_MODE_1) {
2358                         /* 1 buffer mode - normal operation mode */
2359                         memset(rxdp, 0, sizeof(RxD1_t));
2360                         skb_reserve(skb, NET_IP_ALIGN);
2361                         ((RxD1_t*)rxdp)->Buffer0_ptr = pci_map_single
2362                             (nic->pdev, skb->data, size - NET_IP_ALIGN,
2363                                 PCI_DMA_FROMDEVICE);
2364                         rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2365
2366                 } else if (nic->rxd_mode >= RXD_MODE_3A) {
2367                         /*
2368                          * 2 or 3 buffer mode -
2369                          * Both 2 buffer mode and 3 buffer mode provides 128
2370                          * byte aligned receive buffers.
2371                          *
2372                          * 3 buffer mode provides header separation where in
2373                          * skb->data will have L3/L4 headers where as
2374                          * skb_shinfo(skb)->frag_list will have the L4 data
2375                          * payload
2376                          */
2377
2378                         memset(rxdp, 0, sizeof(RxD3_t));
2379                         ba = &mac_control->rings[ring_no].ba[block_no][off];
2380                         skb_reserve(skb, BUF0_LEN);
2381                         tmp = (u64)(unsigned long) skb->data;
2382                         tmp += ALIGN_SIZE;
2383                         tmp &= ~ALIGN_SIZE;
2384                         skb->data = (void *) (unsigned long)tmp;
2385                         skb->tail = (void *) (unsigned long)tmp;
2386
2387                         if (!(((RxD3_t*)rxdp)->Buffer0_ptr))
2388                                 ((RxD3_t*)rxdp)->Buffer0_ptr =
2389                                    pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
2390                                            PCI_DMA_FROMDEVICE);
2391                         else
2392                                 pci_dma_sync_single_for_device(nic->pdev,
2393                                     (dma_addr_t) ((RxD3_t*)rxdp)->Buffer0_ptr,
2394                                     BUF0_LEN, PCI_DMA_FROMDEVICE);
2395                         rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2396                         if (nic->rxd_mode == RXD_MODE_3B) {
2397                                 /* Two buffer mode */
2398
2399                                 /*
2400                                  * Buffer2 will have L3/L4 header plus
2401                                  * L4 payload
2402                                  */
2403                                 ((RxD3_t*)rxdp)->Buffer2_ptr = pci_map_single
2404                                 (nic->pdev, skb->data, dev->mtu + 4,
2405                                                 PCI_DMA_FROMDEVICE);
2406
2407                                 /* Buffer-1 will be dummy buffer. Not used */
2408                                 if (!(((RxD3_t*)rxdp)->Buffer1_ptr)) {
2409                                         ((RxD3_t*)rxdp)->Buffer1_ptr =
2410                                                 pci_map_single(nic->pdev,
2411                                                 ba->ba_1, BUF1_LEN,
2412                                                 PCI_DMA_FROMDEVICE);
2413                                 }
2414                                 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2415                                 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2416                                                                 (dev->mtu + 4);
2417                         } else {
2418                                 /* 3 buffer mode */
2419                                 if (fill_rxd_3buf(nic, rxdp, skb) == -ENOMEM) {
2420                                         dev_kfree_skb_irq(skb);
2421                                         if (first_rxdp) {
2422                                                 wmb();
2423                                                 first_rxdp->Control_1 |=
2424                                                         RXD_OWN_XENA;
2425                                         }
2426                                         return -ENOMEM ;
2427                                 }
2428                         }
2429                         rxdp->Control_2 |= BIT(0);
2430                 }
2431                 rxdp->Host_Control = (unsigned long) (skb);
2432                 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2433                         rxdp->Control_1 |= RXD_OWN_XENA;
2434                 off++;
2435                 if (off == (rxd_count[nic->rxd_mode] + 1))
2436                         off = 0;
2437                 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
2438
2439                 rxdp->Control_2 |= SET_RXD_MARKER;
2440                 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2441                         if (first_rxdp) {
2442                                 wmb();
2443                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2444                         }
2445                         first_rxdp = rxdp;
2446                 }
2447                 atomic_inc(&nic->rx_bufs_left[ring_no]);
2448                 alloc_tab++;
2449         }
2450
2451       end:
2452         /* Transfer ownership of first descriptor to adapter just before
2453          * exiting. Before that, use memory barrier so that ownership
2454          * and other fields are seen by adapter correctly.
2455          */
2456         if (first_rxdp) {
2457                 wmb();
2458                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2459         }
2460
2461         return SUCCESS;
2462 }
2463
2464 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2465 {
2466         struct net_device *dev = sp->dev;
2467         int j;
2468         struct sk_buff *skb;
2469         RxD_t *rxdp;
2470         mac_info_t *mac_control;
2471         buffAdd_t *ba;
2472
2473         mac_control = &sp->mac_control;
2474         for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2475                 rxdp = mac_control->rings[ring_no].
2476                                 rx_blocks[blk].rxds[j].virt_addr;
2477                 skb = (struct sk_buff *)
2478                         ((unsigned long) rxdp->Host_Control);
2479                 if (!skb) {
2480                         continue;
2481                 }
2482                 if (sp->rxd_mode == RXD_MODE_1) {
2483                         pci_unmap_single(sp->pdev, (dma_addr_t)
2484                                  ((RxD1_t*)rxdp)->Buffer0_ptr,
2485                                  dev->mtu +
2486                                  HEADER_ETHERNET_II_802_3_SIZE
2487                                  + HEADER_802_2_SIZE +
2488                                  HEADER_SNAP_SIZE,
2489                                  PCI_DMA_FROMDEVICE);
2490                         memset(rxdp, 0, sizeof(RxD1_t));
2491                 } else if(sp->rxd_mode == RXD_MODE_3B) {
2492                         ba = &mac_control->rings[ring_no].
2493                                 ba[blk][j];
2494                         pci_unmap_single(sp->pdev, (dma_addr_t)
2495                                  ((RxD3_t*)rxdp)->Buffer0_ptr,
2496                                  BUF0_LEN,
2497                                  PCI_DMA_FROMDEVICE);
2498                         pci_unmap_single(sp->pdev, (dma_addr_t)
2499                                  ((RxD3_t*)rxdp)->Buffer1_ptr,
2500                                  BUF1_LEN,
2501                                  PCI_DMA_FROMDEVICE);
2502                         pci_unmap_single(sp->pdev, (dma_addr_t)
2503                                  ((RxD3_t*)rxdp)->Buffer2_ptr,
2504                                  dev->mtu + 4,
2505                                  PCI_DMA_FROMDEVICE);
2506                         memset(rxdp, 0, sizeof(RxD3_t));
2507                 } else {
2508                         pci_unmap_single(sp->pdev, (dma_addr_t)
2509                                 ((RxD3_t*)rxdp)->Buffer0_ptr, BUF0_LEN,
2510                                 PCI_DMA_FROMDEVICE);
2511                         pci_unmap_single(sp->pdev, (dma_addr_t)
2512                                 ((RxD3_t*)rxdp)->Buffer1_ptr,
2513                                 l3l4hdr_size + 4,
2514                                 PCI_DMA_FROMDEVICE);
2515                         pci_unmap_single(sp->pdev, (dma_addr_t)
2516                                 ((RxD3_t*)rxdp)->Buffer2_ptr, dev->mtu,
2517                                 PCI_DMA_FROMDEVICE);
2518                         memset(rxdp, 0, sizeof(RxD3_t));
2519                 }
2520                 dev_kfree_skb(skb);
2521                 atomic_dec(&sp->rx_bufs_left[ring_no]);
2522         }
2523 }
2524
2525 /**
2526  *  free_rx_buffers - Frees all Rx buffers
2527  *  @sp: device private variable.
2528  *  Description:
2529  *  This function will free all Rx buffers allocated by host.
2530  *  Return Value:
2531  *  NONE.
2532  */
2533
2534 static void free_rx_buffers(struct s2io_nic *sp)
2535 {
2536         struct net_device *dev = sp->dev;
2537         int i, blk = 0, buf_cnt = 0;
2538         mac_info_t *mac_control;
2539         struct config_param *config;
2540
2541         mac_control = &sp->mac_control;
2542         config = &sp->config;
2543
2544         for (i = 0; i < config->rx_ring_num; i++) {
2545                 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2546                         free_rxd_blk(sp,i,blk);
2547
2548                 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2549                 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2550                 mac_control->rings[i].rx_curr_put_info.offset = 0;
2551                 mac_control->rings[i].rx_curr_get_info.offset = 0;
2552                 atomic_set(&sp->rx_bufs_left[i], 0);
2553                 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2554                           dev->name, buf_cnt, i);
2555         }
2556 }
2557
2558 /**
2559  * s2io_poll - Rx interrupt handler for NAPI support
2560  * @dev : pointer to the device structure.
2561  * @budget : The number of packets that were budgeted to be processed
2562  * during  one pass through the 'Poll" function.
2563  * Description:
2564  * Comes into picture only if NAPI support has been incorporated. It does
2565  * the same thing that rx_intr_handler does, but not in a interrupt context
2566  * also It will process only a given number of packets.
2567  * Return value:
2568  * 0 on success and 1 if there are No Rx packets to be processed.
2569  */
2570
2571 #if defined(CONFIG_S2IO_NAPI)
2572 static int s2io_poll(struct net_device *dev, int *budget)
2573 {
2574         nic_t *nic = dev->priv;
2575         int pkt_cnt = 0, org_pkts_to_process;
2576         mac_info_t *mac_control;
2577         struct config_param *config;
2578         XENA_dev_config_t __iomem *bar0 = nic->bar0;
2579         u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2580         int i;
2581
2582         atomic_inc(&nic->isr_cnt);
2583         mac_control = &nic->mac_control;
2584         config = &nic->config;
2585
2586         nic->pkts_to_process = *budget;
2587         if (nic->pkts_to_process > dev->quota)
2588                 nic->pkts_to_process = dev->quota;
2589         org_pkts_to_process = nic->pkts_to_process;
2590
2591         writeq(val64, &bar0->rx_traffic_int);
2592         val64 = readl(&bar0->rx_traffic_int);
2593
2594         for (i = 0; i < config->rx_ring_num; i++) {
2595                 rx_intr_handler(&mac_control->rings[i]);
2596                 pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
2597                 if (!nic->pkts_to_process) {
2598                         /* Quota for the current iteration has been met */
2599                         goto no_rx;
2600                 }
2601         }
2602         if (!pkt_cnt)
2603                 pkt_cnt = 1;
2604
2605         dev->quota -= pkt_cnt;
2606         *budget -= pkt_cnt;
2607         netif_rx_complete(dev);
2608
2609         for (i = 0; i < config->rx_ring_num; i++) {
2610                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2611                         DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2612                         DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
2613                         break;
2614                 }
2615         }
2616         /* Re enable the Rx interrupts. */
2617         writeq(0x0, &bar0->rx_traffic_mask);
2618         val64 = readl(&bar0->rx_traffic_mask);
2619         atomic_dec(&nic->isr_cnt);
2620         return 0;
2621
2622 no_rx:
2623         dev->quota -= pkt_cnt;
2624         *budget -= pkt_cnt;
2625
2626         for (i = 0; i < config->rx_ring_num; i++) {
2627                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2628                         DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2629                         DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
2630                         break;
2631                 }
2632         }
2633         atomic_dec(&nic->isr_cnt);
2634         return 1;
2635 }
2636 #endif
2637
2638 #ifdef CONFIG_NET_POLL_CONTROLLER
2639 /**
2640  * s2io_netpoll - netpoll event handler entry point
2641  * @dev : pointer to the device structure.
2642  * Description:
2643  *      This function will be called by upper layer to check for events on the
2644  * interface in situations where interrupts are disabled. It is used for
2645  * specific in-kernel networking tasks, such as remote consoles and kernel
2646  * debugging over the network (example netdump in RedHat).
2647  */
2648 static void s2io_netpoll(struct net_device *dev)
2649 {
2650         nic_t *nic = dev->priv;
2651         mac_info_t *mac_control;
2652         struct config_param *config;
2653         XENA_dev_config_t __iomem *bar0 = nic->bar0;
2654         u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2655         int i;
2656
2657         disable_irq(dev->irq);
2658
2659         atomic_inc(&nic->isr_cnt);
2660         mac_control = &nic->mac_control;
2661         config = &nic->config;
2662
2663         writeq(val64, &bar0->rx_traffic_int);
2664         writeq(val64, &bar0->tx_traffic_int);
2665
2666         /* we need to free up the transmitted skbufs or else netpoll will
2667          * run out of skbs and will fail and eventually netpoll application such
2668          * as netdump will fail.
2669          */
2670         for (i = 0; i < config->tx_fifo_num; i++)
2671                 tx_intr_handler(&mac_control->fifos[i]);
2672
2673         /* check for received packet and indicate up to network */
2674         for (i = 0; i < config->rx_ring_num; i++)
2675                 rx_intr_handler(&mac_control->rings[i]);
2676
2677         for (i = 0; i < config->rx_ring_num; i++) {
2678                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2679                         DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2680                         DBG_PRINT(ERR_DBG, " in Rx Netpoll!!\n");
2681                         break;
2682                 }
2683         }
2684         atomic_dec(&nic->isr_cnt);
2685         enable_irq(dev->irq);
2686         return;
2687 }
2688 #endif
2689
2690 /**
2691  *  rx_intr_handler - Rx interrupt handler
2692  *  @nic: device private variable.
2693  *  Description:
2694  *  If the interrupt is because of a received frame or if the
2695  *  receive ring contains fresh as yet un-processed frames,this function is
2696  *  called. It picks out the RxD at which place the last Rx processing had
2697  *  stopped and sends the skb to the OSM's Rx handler and then increments
2698  *  the offset.
2699  *  Return Value:
2700  *  NONE.
2701  */
2702 static void rx_intr_handler(ring_info_t *ring_data)
2703 {
2704         nic_t *nic = ring_data->nic;
2705         struct net_device *dev = (struct net_device *) nic->dev;
2706         int get_block, put_block, put_offset;
2707         rx_curr_get_info_t get_info, put_info;
2708         RxD_t *rxdp;
2709         struct sk_buff *skb;
2710 #ifndef CONFIG_S2IO_NAPI
2711         int pkt_cnt = 0;
2712 #endif
2713         int i;
2714
2715         spin_lock(&nic->rx_lock);
2716         if (atomic_read(&nic->card_state) == CARD_DOWN) {
2717                 DBG_PRINT(INTR_DBG, "%s: %s going down for reset\n",
2718                           __FUNCTION__, dev->name);
2719                 spin_unlock(&nic->rx_lock);
2720                 return;
2721         }
2722
2723         get_info = ring_data->rx_curr_get_info;
2724         get_block = get_info.block_index;
2725         put_info = ring_data->rx_curr_put_info;
2726         put_block = put_info.block_index;
2727         rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2728 #ifndef CONFIG_S2IO_NAPI
2729         spin_lock(&nic->put_lock);
2730         put_offset = ring_data->put_pos;
2731         spin_unlock(&nic->put_lock);
2732 #else
2733         put_offset = (put_block * (rxd_count[nic->rxd_mode] + 1)) +
2734                 put_info.offset;
2735 #endif
2736         while (RXD_IS_UP2DT(rxdp)) {
2737                 /* If your are next to put index then it's FIFO full condition */
2738                 if ((get_block == put_block) &&
2739                     (get_info.offset + 1) == put_info.offset) {
2740                         DBG_PRINT(INTR_DBG, "%s: Ring Full\n",dev->name);
2741                         break;
2742                 }
2743                 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2744                 if (skb == NULL) {
2745                         DBG_PRINT(ERR_DBG, "%s: The skb is ",
2746                                   dev->name);
2747                         DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
2748                         spin_unlock(&nic->rx_lock);
2749                         return;
2750                 }
2751                 if (nic->rxd_mode == RXD_MODE_1) {
2752                         pci_unmap_single(nic->pdev, (dma_addr_t)
2753                                  ((RxD1_t*)rxdp)->Buffer0_ptr,
2754                                  dev->mtu +
2755                                  HEADER_ETHERNET_II_802_3_SIZE +
2756                                  HEADER_802_2_SIZE +
2757                                  HEADER_SNAP_SIZE,
2758                                  PCI_DMA_FROMDEVICE);
2759                 } else if (nic->rxd_mode == RXD_MODE_3B) {
2760                         pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
2761                                  ((RxD3_t*)rxdp)->Buffer0_ptr,
2762                                  BUF0_LEN, PCI_DMA_FROMDEVICE);
2763                         pci_unmap_single(nic->pdev, (dma_addr_t)
2764                                  ((RxD3_t*)rxdp)->Buffer2_ptr,
2765                                  dev->mtu + 4,
2766                                  PCI_DMA_FROMDEVICE);
2767                 } else {
2768                         pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
2769                                          ((RxD3_t*)rxdp)->Buffer0_ptr, BUF0_LEN,
2770                                          PCI_DMA_FROMDEVICE);
2771                         pci_unmap_single(nic->pdev, (dma_addr_t)
2772                                          ((RxD3_t*)rxdp)->Buffer1_ptr,
2773                                          l3l4hdr_size + 4,
2774                                          PCI_DMA_FROMDEVICE);
2775                         pci_unmap_single(nic->pdev, (dma_addr_t)
2776                                          ((RxD3_t*)rxdp)->Buffer2_ptr,
2777                                          dev->mtu, PCI_DMA_FROMDEVICE);
2778                 }
2779                 prefetch(skb->data);
2780                 rx_osm_handler(ring_data, rxdp);
2781                 get_info.offset++;
2782                 ring_data->rx_curr_get_info.offset = get_info.offset;
2783                 rxdp = ring_data->rx_blocks[get_block].
2784                                 rxds[get_info.offset].virt_addr;
2785                 if (get_info.offset == rxd_count[nic->rxd_mode]) {
2786                         get_info.offset = 0;
2787                         ring_data->rx_curr_get_info.offset = get_info.offset;
2788                         get_block++;
2789                         if (get_block == ring_data->block_count)
2790                                 get_block = 0;
2791                         ring_data->rx_curr_get_info.block_index = get_block;
2792                         rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2793                 }
2794
2795 #ifdef CONFIG_S2IO_NAPI
2796                 nic->pkts_to_process -= 1;
2797                 if (!nic->pkts_to_process)
2798                         break;
2799 #else
2800                 pkt_cnt++;
2801                 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2802                         break;
2803 #endif
2804         }
2805         if (nic->lro) {
2806                 /* Clear all LRO sessions before exiting */
2807                 for (i=0; i<MAX_LRO_SESSIONS; i++) {
2808                         lro_t *lro = &nic->lro0_n[i];
2809                         if (lro->in_use) {
2810                                 update_L3L4_header(nic, lro);
2811                                 queue_rx_frame(lro->parent);
2812                                 clear_lro_session(lro);
2813                         }
2814                 }
2815         }
2816
2817         spin_unlock(&nic->rx_lock);
2818 }
2819
2820 /**
2821  *  tx_intr_handler - Transmit interrupt handler
2822  *  @nic : device private variable
2823  *  Description:
2824  *  If an interrupt was raised to indicate DMA complete of the
2825  *  Tx packet, this function is called. It identifies the last TxD
2826  *  whose buffer was freed and frees all skbs whose data have already
2827  *  DMA'ed into the NICs internal memory.
2828  *  Return Value:
2829  *  NONE
2830  */
2831
2832 static void tx_intr_handler(fifo_info_t *fifo_data)
2833 {
2834         nic_t *nic = fifo_data->nic;
2835         struct net_device *dev = (struct net_device *) nic->dev;
2836         tx_curr_get_info_t get_info, put_info;
2837         struct sk_buff *skb;
2838         TxD_t *txdlp;
2839
2840         get_info = fifo_data->tx_curr_get_info;
2841         put_info = fifo_data->tx_curr_put_info;
2842         txdlp = (TxD_t *) fifo_data->list_info[get_info.offset].
2843             list_virt_addr;
2844         while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
2845                (get_info.offset != put_info.offset) &&
2846                (txdlp->Host_Control)) {
2847                 /* Check for TxD errors */
2848                 if (txdlp->Control_1 & TXD_T_CODE) {
2849                         unsigned long long err;
2850                         err = txdlp->Control_1 & TXD_T_CODE;
2851                         if (err & 0x1) {
2852                                 nic->mac_control.stats_info->sw_stat.
2853                                                 parity_err_cnt++;
2854                         }
2855                         if ((err >> 48) == 0xA) {
2856                                 DBG_PRINT(TX_DBG, "TxD returned due \
2857 to loss of link\n");
2858                         }
2859                         else {
2860                                 DBG_PRINT(ERR_DBG, "***TxD error \
2861 %llx\n", err);
2862                         }
2863                 }
2864
2865                 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
2866                 if (skb == NULL) {
2867                         DBG_PRINT(ERR_DBG, "%s: Null skb ",
2868                         __FUNCTION__);
2869                         DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
2870                         return;
2871                 }
2872
2873                 /* Updating the statistics block */
2874                 nic->stats.tx_bytes += skb->len;
2875                 dev_kfree_skb_irq(skb);
2876
2877                 get_info.offset++;
2878                 if (get_info.offset == get_info.fifo_len + 1)
2879                         get_info.offset = 0;
2880                 txdlp = (TxD_t *) fifo_data->list_info
2881                     [get_info.offset].list_virt_addr;
2882                 fifo_data->tx_curr_get_info.offset =
2883                     get_info.offset;
2884         }
2885
2886         spin_lock(&nic->tx_lock);
2887         if (netif_queue_stopped(dev))
2888                 netif_wake_queue(dev);
2889         spin_unlock(&nic->tx_lock);
2890 }
2891
2892 /**
2893  *  s2io_mdio_write - Function to write in to MDIO registers
2894  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2895  *  @addr     : address value
2896  *  @value    : data value
2897  *  @dev      : pointer to net_device structure
2898  *  Description:
2899  *  This function is used to write values to the MDIO registers
2900  *  NONE
2901  */
2902 static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
2903 {
2904         u64 val64 = 0x0;
2905         nic_t *sp = dev->priv;
2906         XENA_dev_config_t __iomem *bar0 = sp->bar0;
2907
2908         //address transaction
2909         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2910                         | MDIO_MMD_DEV_ADDR(mmd_type)
2911                         | MDIO_MMS_PRT_ADDR(0x0);
2912         writeq(val64, &bar0->mdio_control);
2913         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2914         writeq(val64, &bar0->mdio_control);
2915         udelay(100);
2916
2917         //Data transaction
2918         val64 = 0x0;
2919         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2920                         | MDIO_MMD_DEV_ADDR(mmd_type)
2921                         | MDIO_MMS_PRT_ADDR(0x0)
2922                         | MDIO_MDIO_DATA(value)
2923                         | MDIO_OP(MDIO_OP_WRITE_TRANS);
2924         writeq(val64, &bar0->mdio_control);
2925         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2926         writeq(val64, &bar0->mdio_control);
2927         udelay(100);
2928
2929         val64 = 0x0;
2930         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2931         | MDIO_MMD_DEV_ADDR(mmd_type)
2932         | MDIO_MMS_PRT_ADDR(0x0)
2933         | MDIO_OP(MDIO_OP_READ_TRANS);
2934         writeq(val64, &bar0->mdio_control);
2935         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2936         writeq(val64, &bar0->mdio_control);
2937         udelay(100);
2938
2939 }
2940
2941 /**
2942  *  s2io_mdio_read - Function to write in to MDIO registers
2943  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2944  *  @addr     : address value
2945  *  @dev      : pointer to net_device structure
2946  *  Description:
2947  *  This function is used to read values to the MDIO registers
2948  *  NONE
2949  */
2950 static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
2951 {
2952         u64 val64 = 0x0;
2953         u64 rval64 = 0x0;
2954         nic_t *sp = dev->priv;
2955         XENA_dev_config_t __iomem *bar0 = sp->bar0;
2956
2957         /* address transaction */
2958         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2959                         | MDIO_MMD_DEV_ADDR(mmd_type)
2960                         | MDIO_MMS_PRT_ADDR(0x0);
2961         writeq(val64, &bar0->mdio_control);
2962         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2963         writeq(val64, &bar0->mdio_control);
2964         udelay(100);
2965
2966         /* Data transaction */
2967         val64 = 0x0;
2968         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2969                         | MDIO_MMD_DEV_ADDR(mmd_type)
2970                         | MDIO_MMS_PRT_ADDR(0x0)
2971                         | MDIO_OP(MDIO_OP_READ_TRANS);
2972         writeq(val64, &bar0->mdio_control);
2973         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2974         writeq(val64, &bar0->mdio_control);
2975         udelay(100);
2976
2977         /* Read the value from regs */
2978         rval64 = readq(&bar0->mdio_control);
2979         rval64 = rval64 & 0xFFFF0000;
2980         rval64 = rval64 >> 16;
2981         return rval64;
2982 }
2983 /**
2984  *  s2io_chk_xpak_counter - Function to check the status of the xpak counters
2985  *  @counter      : couter value to be updated
2986  *  @flag         : flag to indicate the status
2987  *  @type         : counter type
2988  *  Description:
2989  *  This function is to check the status of the xpak counters value
2990  *  NONE
2991  */
2992
2993 static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type)
2994 {
2995         u64 mask = 0x3;
2996         u64 val64;
2997         int i;
2998         for(i = 0; i <index; i++)
2999                 mask = mask << 0x2;
3000
3001         if(flag > 0)
3002         {
3003                 *counter = *counter + 1;
3004                 val64 = *regs_stat & mask;
3005                 val64 = val64 >> (index * 0x2);
3006                 val64 = val64 + 1;
3007                 if(val64 == 3)
3008                 {
3009                         switch(type)
3010                         {
3011                         case 1:
3012                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3013                                           "service. Excessive temperatures may "
3014                                           "result in premature transceiver "
3015                                           "failure \n");
3016                         break;
3017                         case 2:
3018                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3019                                           "service Excessive bias currents may "
3020                                           "indicate imminent laser diode "
3021                                           "failure \n");
3022                         break;
3023                         case 3:
3024                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3025                                           "service Excessive laser output "
3026                                           "power may saturate far-end "
3027                                           "receiver\n");
3028                         break;
3029                         default:
3030                                 DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm "
3031                                           "type \n");
3032                         }
3033  &nbs