drivers/net/phy/mscc.c

   1 /*
   2  * Driver for Microsemi VSC85xx PHYs
   3  *
   4  * Author: Nagaraju Lakkaraju
   5  * License: Dual MIT/GPL
   6  * Copyright (c) 2016 Microsemi Corporation
   7  */
   8
   9 #include <linux/firmware.h>
  10 #include <linux/jiffies.h>
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/mdio.h>
  14 #include <linux/mii.h>
  15 #include <linux/phy.h>
  16 #include <linux/of.h>
  17 #include <linux/netdevice.h>
  18 #include <dt-bindings/net/mscc-phy-vsc8531.h>
  19
  20 enum rgmii_rx_clock_delay {
  21         RGMII_RX_CLK_DELAY_0_2_NS = 0,
  22         RGMII_RX_CLK_DELAY_0_8_NS = 1,
  23         RGMII_RX_CLK_DELAY_1_1_NS = 2,
  24         RGMII_RX_CLK_DELAY_1_7_NS = 3,
  25         RGMII_RX_CLK_DELAY_2_0_NS = 4,
  26         RGMII_RX_CLK_DELAY_2_3_NS = 5,
  27         RGMII_RX_CLK_DELAY_2_6_NS = 6,
  28         RGMII_RX_CLK_DELAY_3_4_NS = 7
  29 };
  30
  31 /* Microsemi VSC85xx PHY registers */
  32 /* IEEE 802. Std Registers */
  33 #define MSCC_PHY_BYPASS_CONTROL           18
  34 #define DISABLE_HP_AUTO_MDIX_MASK         0x0080
  35 #define DISABLE_PAIR_SWAP_CORR_MASK       0x0020
  36 #define DISABLE_POLARITY_CORR_MASK        0x0010
  37 #define PARALLEL_DET_IGNORE_ADVERTISED    0x0008
  38
  39 #define MSCC_PHY_EXT_CNTL_STATUS          22
  40 #define SMI_BROADCAST_WR_EN               0x0001
  41
  42 #define MSCC_PHY_ERR_RX_CNT               19
  43 #define MSCC_PHY_ERR_FALSE_CARRIER_CNT    20
  44 #define MSCC_PHY_ERR_LINK_DISCONNECT_CNT  21
  45 #define ERR_CNT_MASK                      GENMASK(7, 0)
  46
  47 #define MSCC_PHY_EXT_PHY_CNTL_1           23
  48 #define MAC_IF_SELECTION_MASK             0x1800
  49 #define MAC_IF_SELECTION_GMII             0
  50 #define MAC_IF_SELECTION_RMII             1
  51 #define MAC_IF_SELECTION_RGMII            2
  52 #define MAC_IF_SELECTION_POS              11
  53 #define VSC8584_MAC_IF_SELECTION_MASK     0x1000
  54 #define VSC8584_MAC_IF_SELECTION_SGMII    0
  55 #define VSC8584_MAC_IF_SELECTION_1000BASEX 1
  56 #define VSC8584_MAC_IF_SELECTION_POS      12
  57 #define FAR_END_LOOPBACK_MODE_MASK        0x0008
  58 #define MEDIA_OP_MODE_MASK                0x0700
  59 #define MEDIA_OP_MODE_COPPER              0
  60 #define MEDIA_OP_MODE_SERDES              1
  61 #define MEDIA_OP_MODE_1000BASEX           2
  62 #define MEDIA_OP_MODE_100BASEFX           3
  63 #define MEDIA_OP_MODE_AMS_COPPER_SERDES   5
  64 #define MEDIA_OP_MODE_AMS_COPPER_1000BASEX      6
  65 #define MEDIA_OP_MODE_AMS_COPPER_100BASEFX      7
  66 #define MEDIA_OP_MODE_POS                 8
  67
  68 #define MSCC_PHY_EXT_PHY_CNTL_2           24
  69
  70 #define MII_VSC85XX_INT_MASK              25
  71 #define MII_VSC85XX_INT_MASK_MASK         0xa000
  72 #define MII_VSC85XX_INT_MASK_WOL          0x0040
  73 #define MII_VSC85XX_INT_STATUS            26
  74
  75 #define MSCC_PHY_WOL_MAC_CONTROL          27
  76 #define EDGE_RATE_CNTL_POS                5
  77 #define EDGE_RATE_CNTL_MASK               0x00E0
  78
  79 #define MSCC_PHY_DEV_AUX_CNTL             28
  80 #define HP_AUTO_MDIX_X_OVER_IND_MASK      0x2000
  81
  82 #define MSCC_PHY_LED_MODE_SEL             29
  83 #define LED_MODE_SEL_POS(x)               ((x) * 4)
  84 #define LED_MODE_SEL_MASK(x)              (GENMASK(3, 0) << LED_MODE_SEL_POS(x))
  85 #define LED_MODE_SEL(x, mode)             (((mode) << LED_MODE_SEL_POS(x)) & LED_MODE_SEL_MASK(x))
  86
  87 #define MSCC_EXT_PAGE_ACCESS              31
  88 #define MSCC_PHY_PAGE_STANDARD            0x0000 /* Standard registers */
  89 #define MSCC_PHY_PAGE_EXTENDED            0x0001 /* Extended registers */
  90 #define MSCC_PHY_PAGE_EXTENDED_2          0x0002 /* Extended reg - page 2 */
  91 #define MSCC_PHY_PAGE_EXTENDED_3          0x0003 /* Extended reg - page 3 */
  92 #define MSCC_PHY_PAGE_EXTENDED_4          0x0004 /* Extended reg - page 4 */
  93 /* Extended reg - GPIO; this is a bank of registers that are shared for all PHYs
  94  * in the same package.
  95  */
  96 #define MSCC_PHY_PAGE_EXTENDED_GPIO       0x0010 /* Extended reg - GPIO */
  97 #define MSCC_PHY_PAGE_TEST                0x2a30 /* Test reg */
  98 #define MSCC_PHY_PAGE_TR                  0x52b5 /* Token ring registers */
  99
 100 /* Extended Page 1 Registers */
 101 #define MSCC_PHY_CU_MEDIA_CRC_VALID_CNT   18
 102 #define VALID_CRC_CNT_CRC_MASK            GENMASK(13, 0)
 103
 104 #define MSCC_PHY_EXT_MODE_CNTL            19
 105 #define FORCE_MDI_CROSSOVER_MASK          0x000C
 106 #define FORCE_MDI_CROSSOVER_MDIX          0x000C
 107 #define FORCE_MDI_CROSSOVER_MDI           0x0008
 108
 109 #define MSCC_PHY_ACTIPHY_CNTL             20
 110 #define PHY_ADDR_REVERSED                 0x0200
 111 #define DOWNSHIFT_CNTL_MASK               0x001C
 112 #define DOWNSHIFT_EN                      0x0010
 113 #define DOWNSHIFT_CNTL_POS                2
 114
 115 #define MSCC_PHY_EXT_PHY_CNTL_4           23
 116 #define PHY_CNTL_4_ADDR_POS               11
 117
 118 #define MSCC_PHY_VERIPHY_CNTL_2           25
 119
 120 #define MSCC_PHY_VERIPHY_CNTL_3           26
 121
 122 /* Extended Page 2 Registers */
 123 #define MSCC_PHY_CU_PMD_TX_CNTL           16
 124
 125 #define MSCC_PHY_RGMII_CNTL               20
 126 #define RGMII_RX_CLK_DELAY_MASK           0x0070
 127 #define RGMII_RX_CLK_DELAY_POS            4
 128
 129 #define MSCC_PHY_WOL_LOWER_MAC_ADDR       21
 130 #define MSCC_PHY_WOL_MID_MAC_ADDR         22
 131 #define MSCC_PHY_WOL_UPPER_MAC_ADDR       23
 132 #define MSCC_PHY_WOL_LOWER_PASSWD         24
 133 #define MSCC_PHY_WOL_MID_PASSWD           25
 134 #define MSCC_PHY_WOL_UPPER_PASSWD         26
 135
 136 #define MSCC_PHY_WOL_MAC_CONTROL          27
 137 #define SECURE_ON_ENABLE                  0x8000
 138 #define SECURE_ON_PASSWD_LEN_4            0x4000
 139
 140 /* Extended Page 3 Registers */
 141 #define MSCC_PHY_SERDES_TX_VALID_CNT      21
 142 #define MSCC_PHY_SERDES_TX_CRC_ERR_CNT    22
 143 #define MSCC_PHY_SERDES_RX_VALID_CNT      28
 144 #define MSCC_PHY_SERDES_RX_CRC_ERR_CNT    29
 145
 146 /* Extended page GPIO Registers */
 147 #define MSCC_DW8051_CNTL_STATUS           0
 148 #define MICRO_NSOFT_RESET                 0x8000
 149 #define RUN_FROM_INT_ROM                  0x4000
 150 #define AUTOINC_ADDR                      0x2000
 151 #define PATCH_RAM_CLK                     0x1000
 152 #define MICRO_PATCH_EN                    0x0080
 153 #define DW8051_CLK_EN                     0x0010
 154 #define MICRO_CLK_EN                      0x0008
 155 #define MICRO_CLK_DIVIDE(x)               ((x) >> 1)
 156 #define MSCC_DW8051_VLD_MASK              0xf1ff
 157
 158 /* x Address in range 1-4 */
 159 #define MSCC_TRAP_ROM_ADDR(x)             ((x) * 2 + 1)
 160 #define MSCC_PATCH_RAM_ADDR(x)            (((x) + 1) * 2)
 161 #define MSCC_INT_MEM_ADDR                 11
 162
 163 #define MSCC_INT_MEM_CNTL                 12
 164 #define READ_SFR                          0x6000
 165 #define READ_PRAM                         0x4000
 166 #define READ_ROM                          0x2000
 167 #define READ_RAM                          0x0000
 168 #define INT_MEM_WRITE_EN                  0x1000
 169 #define EN_PATCH_RAM_TRAP_ADDR(x)         (0x0100 << ((x) - 1))
 170 #define INT_MEM_DATA_M                    0x00ff
 171 #define INT_MEM_DATA(x)                   (INT_MEM_DATA_M & (x))
 172
 173 #define MSCC_PHY_PROC_CMD                 18
 174 #define PROC_CMD_NCOMPLETED               0x8000
 175 #define PROC_CMD_FAILED                   0x4000
 176 #define PROC_CMD_SGMII_PORT(x)            ((x) << 8)
 177 #define PROC_CMD_FIBER_PORT(x)            (0x0100 << (x) % 4)
 178 #define PROC_CMD_QSGMII_PORT              0x0c00
 179 #define PROC_CMD_RST_CONF_PORT            0x0080
 180 #define PROC_CMD_RECONF_PORT              0x0000
 181 #define PROC_CMD_READ_MOD_WRITE_PORT      0x0040
 182 #define PROC_CMD_WRITE                    0x0040
 183 #define PROC_CMD_READ                     0x0000
 184 #define PROC_CMD_FIBER_DISABLE            0x0020
 185 #define PROC_CMD_FIBER_100BASE_FX         0x0010
 186 #define PROC_CMD_FIBER_1000BASE_X         0x0000
 187 #define PROC_CMD_SGMII_MAC                0x0030
 188 #define PROC_CMD_QSGMII_MAC               0x0020
 189 #define PROC_CMD_NO_MAC_CONF              0x0000
 190 #define PROC_CMD_1588_DEFAULT_INIT        0x0010
 191 #define PROC_CMD_NOP                      0x000f
 192 #define PROC_CMD_PHY_INIT                 0x000a
 193 #define PROC_CMD_CRC16                    0x0008
 194 #define PROC_CMD_FIBER_MEDIA_CONF         0x0001
 195 #define PROC_CMD_MCB_ACCESS_MAC_CONF      0x0000
 196 #define PROC_CMD_NCOMPLETED_TIMEOUT_MS    500
 197
 198 #define MSCC_PHY_MAC_CFG_FASTLINK         19
 199 #define MAC_CFG_MASK                      0xc000
 200 #define MAC_CFG_SGMII                     0x0000
 201 #define MAC_CFG_QSGMII                    0x4000
 202
 203 /* Test page Registers */
 204 #define MSCC_PHY_TEST_PAGE_5              5
 205 #define MSCC_PHY_TEST_PAGE_8              8
 206 #define MSCC_PHY_TEST_PAGE_9              9
 207 #define MSCC_PHY_TEST_PAGE_20             20
 208 #define MSCC_PHY_TEST_PAGE_24             24
 209
 210 /* Token ring page Registers */
 211 #define MSCC_PHY_TR_CNTL                  16
 212 #define TR_WRITE                          0x8000
 213 #define TR_ADDR(x)                        (0x7fff & (x))
 214 #define MSCC_PHY_TR_LSB                   17
 215 #define MSCC_PHY_TR_MSB                   18
 216
 217 /* Microsemi PHY ID's */
 218 #define PHY_ID_VSC8530                    0x00070560
 219 #define PHY_ID_VSC8531                    0x00070570
 220 #define PHY_ID_VSC8540                    0x00070760
 221 #define PHY_ID_VSC8541                    0x00070770
 222 #define PHY_ID_VSC8574                    0x000704a0
 223 #define PHY_ID_VSC8584                    0x000707c0
 224
 225 #define MSCC_VDDMAC_1500                  1500
 226 #define MSCC_VDDMAC_1800                  1800
 227 #define MSCC_VDDMAC_2500                  2500
 228 #define MSCC_VDDMAC_3300                  3300
 229
 230 #define DOWNSHIFT_COUNT_MAX               5
 231
 232 #define MAX_LEDS                          4
 233
 234 #define VSC8584_SUPP_LED_MODES (BIT(VSC8531_LINK_ACTIVITY) | \
 235                                 BIT(VSC8531_LINK_1000_ACTIVITY) | \
 236                                 BIT(VSC8531_LINK_100_ACTIVITY) | \
 237                                 BIT(VSC8531_LINK_10_ACTIVITY) | \
 238                                 BIT(VSC8531_LINK_100_1000_ACTIVITY) | \
 239                                 BIT(VSC8531_LINK_10_1000_ACTIVITY) | \
 240                                 BIT(VSC8531_LINK_10_100_ACTIVITY) | \
 241                                 BIT(VSC8584_LINK_100FX_1000X_ACTIVITY) | \
 242                                 BIT(VSC8531_DUPLEX_COLLISION) | \
 243                                 BIT(VSC8531_COLLISION) | \
 244                                 BIT(VSC8531_ACTIVITY) | \
 245                                 BIT(VSC8584_100FX_1000X_ACTIVITY) | \
 246                                 BIT(VSC8531_AUTONEG_FAULT) | \
 247                                 BIT(VSC8531_SERIAL_MODE) | \
 248                                 BIT(VSC8531_FORCE_LED_OFF) | \
 249                                 BIT(VSC8531_FORCE_LED_ON))
 250
 251 #define VSC85XX_SUPP_LED_MODES (BIT(VSC8531_LINK_ACTIVITY) | \
 252                                 BIT(VSC8531_LINK_1000_ACTIVITY) | \
 253                                 BIT(VSC8531_LINK_100_ACTIVITY) | \
 254                                 BIT(VSC8531_LINK_10_ACTIVITY) | \
 255                                 BIT(VSC8531_LINK_100_1000_ACTIVITY) | \
 256                                 BIT(VSC8531_LINK_10_1000_ACTIVITY) | \
 257                                 BIT(VSC8531_LINK_10_100_ACTIVITY) | \
 258                                 BIT(VSC8531_DUPLEX_COLLISION) | \
 259                                 BIT(VSC8531_COLLISION) | \
 260                                 BIT(VSC8531_ACTIVITY) | \
 261                                 BIT(VSC8531_AUTONEG_FAULT) | \
 262                                 BIT(VSC8531_SERIAL_MODE) | \
 263                                 BIT(VSC8531_FORCE_LED_OFF) | \
 264                                 BIT(VSC8531_FORCE_LED_ON))
 265
 266 #define MSCC_VSC8584_REVB_INT8051_FW            "mscc_vsc8584_revb_int8051_fb48.bin"
 267 #define MSCC_VSC8584_REVB_INT8051_FW_START_ADDR 0xe800
 268 #define MSCC_VSC8584_REVB_INT8051_FW_CRC        0xfb48
 269
 270 #define MSCC_VSC8574_REVB_INT8051_FW            "mscc_vsc8574_revb_int8051_29e8.bin"
 271 #define MSCC_VSC8574_REVB_INT8051_FW_START_ADDR 0x4000
 272 #define MSCC_VSC8574_REVB_INT8051_FW_CRC        0x29e8
 273
 274 #define VSC8584_REVB                            0x0001
 275 #define MSCC_DEV_REV_MASK                       GENMASK(3, 0)
 276
 277 struct reg_val {
 278         u16     reg;
 279         u32     val;
 280 };
 281
 282 struct vsc85xx_hw_stat {
 283         const char *string;
 284         u8 reg;
 285         u16 page;
 286         u16 mask;
 287 };
 288
 289 static const struct vsc85xx_hw_stat vsc85xx_hw_stats[] = {
 290         {
 291                 .string = "phy_receive_errors",
 292                 .reg    = MSCC_PHY_ERR_RX_CNT,
 293                 .page   = MSCC_PHY_PAGE_STANDARD,
 294                 .mask   = ERR_CNT_MASK,
 295         }, {
 296                 .string = "phy_false_carrier",
 297                 .reg    = MSCC_PHY_ERR_FALSE_CARRIER_CNT,
 298                 .page   = MSCC_PHY_PAGE_STANDARD,
 299                 .mask   = ERR_CNT_MASK,
 300         }, {
 301                 .string = "phy_cu_media_link_disconnect",
 302                 .reg    = MSCC_PHY_ERR_LINK_DISCONNECT_CNT,
 303                 .page   = MSCC_PHY_PAGE_STANDARD,
 304                 .mask   = ERR_CNT_MASK,
 305         }, {
 306                 .string = "phy_cu_media_crc_good_count",
 307                 .reg    = MSCC_PHY_CU_MEDIA_CRC_VALID_CNT,
 308                 .page   = MSCC_PHY_PAGE_EXTENDED,
 309                 .mask   = VALID_CRC_CNT_CRC_MASK,
 310         }, {
 311                 .string = "phy_cu_media_crc_error_count",
 312                 .reg    = MSCC_PHY_EXT_PHY_CNTL_4,
 313                 .page   = MSCC_PHY_PAGE_EXTENDED,
 314                 .mask   = ERR_CNT_MASK,
 315         },
 316 };
 317
 318 static const struct vsc85xx_hw_stat vsc8584_hw_stats[] = {
 319         {
 320                 .string = "phy_receive_errors",
 321                 .reg    = MSCC_PHY_ERR_RX_CNT,
 322                 .page   = MSCC_PHY_PAGE_STANDARD,
 323                 .mask   = ERR_CNT_MASK,
 324         }, {
 325                 .string = "phy_false_carrier",
 326                 .reg    = MSCC_PHY_ERR_FALSE_CARRIER_CNT,
 327                 .page   = MSCC_PHY_PAGE_STANDARD,
 328                 .mask   = ERR_CNT_MASK,
 329         }, {
 330                 .string = "phy_cu_media_link_disconnect",
 331                 .reg    = MSCC_PHY_ERR_LINK_DISCONNECT_CNT,
 332                 .page   = MSCC_PHY_PAGE_STANDARD,
 333                 .mask   = ERR_CNT_MASK,
 334         }, {
 335                 .string = "phy_cu_media_crc_good_count",
 336                 .reg    = MSCC_PHY_CU_MEDIA_CRC_VALID_CNT,
 337                 .page   = MSCC_PHY_PAGE_EXTENDED,
 338                 .mask   = VALID_CRC_CNT_CRC_MASK,
 339         }, {
 340                 .string = "phy_cu_media_crc_error_count",
 341                 .reg    = MSCC_PHY_EXT_PHY_CNTL_4,
 342                 .page   = MSCC_PHY_PAGE_EXTENDED,
 343                 .mask   = ERR_CNT_MASK,
 344         }, {
 345                 .string = "phy_serdes_tx_good_pkt_count",
 346                 .reg    = MSCC_PHY_SERDES_TX_VALID_CNT,
 347                 .page   = MSCC_PHY_PAGE_EXTENDED_3,
 348                 .mask   = VALID_CRC_CNT_CRC_MASK,
 349         }, {
 350                 .string = "phy_serdes_tx_bad_crc_count",
 351                 .reg    = MSCC_PHY_SERDES_TX_CRC_ERR_CNT,
 352                 .page   = MSCC_PHY_PAGE_EXTENDED_3,
 353                 .mask   = ERR_CNT_MASK,
 354         }, {
 355                 .string = "phy_serdes_rx_good_pkt_count",
 356                 .reg    = MSCC_PHY_SERDES_RX_VALID_CNT,
 357                 .page   = MSCC_PHY_PAGE_EXTENDED_3,
 358                 .mask   = VALID_CRC_CNT_CRC_MASK,
 359         }, {
 360                 .string = "phy_serdes_rx_bad_crc_count",
 361                 .reg    = MSCC_PHY_SERDES_RX_CRC_ERR_CNT,
 362                 .page   = MSCC_PHY_PAGE_EXTENDED_3,
 363                 .mask   = ERR_CNT_MASK,
 364         },
 365 };
 366
 367 struct vsc8531_private {
 368         int rate_magic;
 369         u16 supp_led_modes;
 370         u32 leds_mode[MAX_LEDS];
 371         u8 nleds;
 372         const struct vsc85xx_hw_stat *hw_stats;
 373         u64 *stats;
 374         int nstats;
 375         bool pkg_init;
 376         /* For multiple port PHYs; the MDIO address of the base PHY in the
 377          * package.
 378          */
 379         unsigned int base_addr;
 380 };
 381
 382 #ifdef CONFIG_OF_MDIO
 383 struct vsc8531_edge_rate_table {
 384         u32 vddmac;
 385         u32 slowdown[8];
 386 };
 387
 388 static const struct vsc8531_edge_rate_table edge_table[] = {
 389         {MSCC_VDDMAC_3300, { 0, 2,  4,  7, 10, 17, 29, 53} },
 390         {MSCC_VDDMAC_2500, { 0, 3,  6, 10, 14, 23, 37, 63} },
 391         {MSCC_VDDMAC_1800, { 0, 5,  9, 16, 23, 35, 52, 76} },
 392         {MSCC_VDDMAC_1500, { 0, 6, 14, 21, 29, 42, 58, 77} },
 393 };
 394 #endif /* CONFIG_OF_MDIO */
 395
 396 static int vsc85xx_phy_read_page(struct phy_device *phydev)
 397 {
 398         return __phy_read(phydev, MSCC_EXT_PAGE_ACCESS);
 399 }
 400
 401 static int vsc85xx_phy_write_page(struct phy_device *phydev, int page)
 402 {
 403         return __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, page);
 404 }
 405
 406 static int vsc85xx_get_sset_count(struct phy_device *phydev)
 407 {
 408         struct vsc8531_private *priv = phydev->priv;
 409
 410         if (!priv)
 411                 return 0;
 412
 413         return priv->nstats;
 414 }
 415
 416 static void vsc85xx_get_strings(struct phy_device *phydev, u8 *data)
 417 {
 418         struct vsc8531_private *priv = phydev->priv;
 419         int i;
 420
 421         if (!priv)
 422                 return;
 423
 424         for (i = 0; i < priv->nstats; i++)
 425                 strlcpy(data + i * ETH_GSTRING_LEN, priv->hw_stats[i].string,
 426                         ETH_GSTRING_LEN);
 427 }
 428
 429 static u64 vsc85xx_get_stat(struct phy_device *phydev, int i)
 430 {
 431         struct vsc8531_private *priv = phydev->priv;
 432         int val;
 433
 434         val = phy_read_paged(phydev, priv->hw_stats[i].page,
 435                              priv->hw_stats[i].reg);
 436         if (val < 0)
 437                 return U64_MAX;
 438
 439         val = val & priv->hw_stats[i].mask;
 440         priv->stats[i] += val;
 441
 442         return priv->stats[i];
 443 }
 444
 445 static void vsc85xx_get_stats(struct phy_device *phydev,
 446                               struct ethtool_stats *stats, u64 *data)
 447 {
 448         struct vsc8531_private *priv = phydev->priv;
 449         int i;
 450
 451         if (!priv)
 452                 return;
 453
 454         for (i = 0; i < priv->nstats; i++)
 455                 data[i] = vsc85xx_get_stat(phydev, i);
 456 }
 457
 458 static int vsc85xx_led_cntl_set(struct phy_device *phydev,
 459                                 u8 led_num,
 460                                 u8 mode)
 461 {
 462         int rc;
 463         u16 reg_val;
 464
 465         mutex_lock(&phydev->lock);
 466         reg_val = phy_read(phydev, MSCC_PHY_LED_MODE_SEL);
 467         reg_val &= ~LED_MODE_SEL_MASK(led_num);
 468         reg_val |= LED_MODE_SEL(led_num, (u16)mode);
 469         rc = phy_write(phydev, MSCC_PHY_LED_MODE_SEL, reg_val);
 470         mutex_unlock(&phydev->lock);
 471
 472         return rc;
 473 }
 474
 475 static int vsc85xx_mdix_get(struct phy_device *phydev, u8 *mdix)
 476 {
 477         u16 reg_val;
 478
 479         reg_val = phy_read(phydev, MSCC_PHY_DEV_AUX_CNTL);
 480         if (reg_val & HP_AUTO_MDIX_X_OVER_IND_MASK)
 481                 *mdix = ETH_TP_MDI_X;
 482         else
 483                 *mdix = ETH_TP_MDI;
 484
 485         return 0;
 486 }
 487
 488 static int vsc85xx_mdix_set(struct phy_device *phydev, u8 mdix)
 489 {
 490         int rc;
 491         u16 reg_val;
 492
 493         reg_val = phy_read(phydev, MSCC_PHY_BYPASS_CONTROL);
 494         if (mdix == ETH_TP_MDI || mdix == ETH_TP_MDI_X) {
 495                 reg_val |= (DISABLE_PAIR_SWAP_CORR_MASK |
 496                             DISABLE_POLARITY_CORR_MASK  |
 497                             DISABLE_HP_AUTO_MDIX_MASK);
 498         } else {
 499                 reg_val &= ~(DISABLE_PAIR_SWAP_CORR_MASK |
 500                              DISABLE_POLARITY_CORR_MASK  |
 501                              DISABLE_HP_AUTO_MDIX_MASK);
 502         }
 503         rc = phy_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg_val);
 504         if (rc)
 505                 return rc;
 506
 507         reg_val = 0;
 508
 509         if (mdix == ETH_TP_MDI)
 510                 reg_val = FORCE_MDI_CROSSOVER_MDI;
 511         else if (mdix == ETH_TP_MDI_X)
 512                 reg_val = FORCE_MDI_CROSSOVER_MDIX;
 513
 514         rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED,
 515                               MSCC_PHY_EXT_MODE_CNTL, FORCE_MDI_CROSSOVER_MASK,
 516                               reg_val);
 517         if (rc < 0)
 518                 return rc;
 519
 520         return genphy_restart_aneg(phydev);
 521 }
 522
 523 static int vsc85xx_downshift_get(struct phy_device *phydev, u8 *count)
 524 {
 525         int reg_val;
 526
 527         reg_val = phy_read_paged(phydev, MSCC_PHY_PAGE_EXTENDED,
 528                                  MSCC_PHY_ACTIPHY_CNTL);
 529         if (reg_val < 0)
 530                 return reg_val;
 531
 532         reg_val &= DOWNSHIFT_CNTL_MASK;
 533         if (!(reg_val & DOWNSHIFT_EN))
 534                 *count = DOWNSHIFT_DEV_DISABLE;
 535         else
 536                 *count = ((reg_val & ~DOWNSHIFT_EN) >> DOWNSHIFT_CNTL_POS) + 2;
 537
 538         return 0;
 539 }
 540
 541 static int vsc85xx_downshift_set(struct phy_device *phydev, u8 count)
 542 {
 543         if (count == DOWNSHIFT_DEV_DEFAULT_COUNT) {
 544                 /* Default downshift count 3 (i.e. Bit3:2 = 0b01) */
 545                 count = ((1 << DOWNSHIFT_CNTL_POS) | DOWNSHIFT_EN);
 546         } else if (count > DOWNSHIFT_COUNT_MAX || count == 1) {
 547                 phydev_err(phydev, "Downshift count should be 2,3,4 or 5\n");
 548                 return -ERANGE;
 549         } else if (count) {
 550                 /* Downshift count is either 2,3,4 or 5 */
 551                 count = (((count - 2) << DOWNSHIFT_CNTL_POS) | DOWNSHIFT_EN);
 552         }
 553
 554         return phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED,
 555                                 MSCC_PHY_ACTIPHY_CNTL, DOWNSHIFT_CNTL_MASK,
 556                                 count);
 557 }
 558
 559 static int vsc85xx_wol_set(struct phy_device *phydev,
 560                            struct ethtool_wolinfo *wol)
 561 {
 562         int rc;
 563         u16 reg_val;
 564         u8  i;
 565         u16 pwd[3] = {0, 0, 0};
 566         struct ethtool_wolinfo *wol_conf = wol;
 567         u8 *mac_addr = phydev->attached_dev->dev_addr;
 568
 569         mutex_lock(&phydev->lock);
 570         rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2);
 571         if (rc < 0) {
 572                 rc = phy_restore_page(phydev, rc, rc);
 573                 goto out_unlock;
 574         }
 575
 576         if (wol->wolopts & WAKE_MAGIC) {
 577                 /* Store the device address for the magic packet */
 578                 for (i = 0; i < ARRAY_SIZE(pwd); i++)
 579                         pwd[i] = mac_addr[5 - (i * 2 + 1)] << 8 |
 580                                  mac_addr[5 - i * 2];
 581                 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, pwd[0]);
 582                 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, pwd[1]);
 583                 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, pwd[2]);
 584         } else {
 585                 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, 0);
 586                 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, 0);
 587                 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, 0);
 588         }
 589
 590         if (wol_conf->wolopts & WAKE_MAGICSECURE) {
 591                 for (i = 0; i < ARRAY_SIZE(pwd); i++)
 592                         pwd[i] = wol_conf->sopass[5 - (i * 2 + 1)] << 8 |
 593                                  wol_conf->sopass[5 - i * 2];
 594                 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, pwd[0]);
 595                 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, pwd[1]);
 596                 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, pwd[2]);
 597         } else {
 598                 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, 0);
 599                 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, 0);
 600                 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, 0);
 601         }
 602
 603         reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
 604         if (wol_conf->wolopts & WAKE_MAGICSECURE)
 605                 reg_val |= SECURE_ON_ENABLE;
 606         else
 607                 reg_val &= ~SECURE_ON_ENABLE;
 608         __phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val);
 609
 610         rc = phy_restore_page(phydev, rc, rc > 0 ? 0 : rc);
 611         if (rc < 0)
 612                 goto out_unlock;
 613
 614         if (wol->wolopts & WAKE_MAGIC) {
 615                 /* Enable the WOL interrupt */
 616                 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK);
 617                 reg_val |= MII_VSC85XX_INT_MASK_WOL;
 618                 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val);
 619                 if (rc)
 620                         goto out_unlock;
 621         } else {
 622                 /* Disable the WOL interrupt */
 623                 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK);
 624                 reg_val &= (~MII_VSC85XX_INT_MASK_WOL);
 625                 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val);
 626                 if (rc)
 627                         goto out_unlock;
 628         }
 629         /* Clear WOL iterrupt status */
 630         reg_val = phy_read(phydev, MII_VSC85XX_INT_STATUS);
 631
 632 out_unlock:
 633         mutex_unlock(&phydev->lock);
 634
 635         return rc;
 636 }
 637
 638 static void vsc85xx_wol_get(struct phy_device *phydev,
 639                             struct ethtool_wolinfo *wol)
 640 {
 641         int rc;
 642         u16 reg_val;
 643         u8  i;
 644         u16 pwd[3] = {0, 0, 0};
 645         struct ethtool_wolinfo *wol_conf = wol;
 646
 647         mutex_lock(&phydev->lock);
 648         rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2);
 649         if (rc < 0)
 650                 goto out_unlock;
 651
 652         reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
 653         if (reg_val & SECURE_ON_ENABLE)
 654                 wol_conf->wolopts |= WAKE_MAGICSECURE;
 655         if (wol_conf->wolopts & WAKE_MAGICSECURE) {
 656                 pwd[0] = __phy_read(phydev, MSCC_PHY_WOL_LOWER_PASSWD);
 657                 pwd[1] = __phy_read(phydev, MSCC_PHY_WOL_MID_PASSWD);
 658                 pwd[2] = __phy_read(phydev, MSCC_PHY_WOL_UPPER_PASSWD);
 659                 for (i = 0; i < ARRAY_SIZE(pwd); i++) {
 660                         wol_conf->sopass[5 - i * 2] = pwd[i] & 0x00ff;
 661                         wol_conf->sopass[5 - (i * 2 + 1)] = (pwd[i] & 0xff00)
 662                                                             >> 8;
 663                 }
 664         }
 665
 666 out_unlock:
 667         phy_restore_page(phydev, rc, rc > 0 ? 0 : rc);
 668         mutex_unlock(&phydev->lock);
 669 }
 670
 671 #ifdef CONFIG_OF_MDIO
 672 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev)
 673 {
 674         u32 vdd, sd;
 675         int i, j;
 676         struct device *dev = &phydev->mdio.dev;
 677         struct device_node *of_node = dev->of_node;
 678         u8 sd_array_size = ARRAY_SIZE(edge_table[0].slowdown);
 679
 680         if (!of_node)
 681                 return -ENODEV;
 682
 683         if (of_property_read_u32(of_node, "vsc8531,vddmac", &vdd))
 684                 vdd = MSCC_VDDMAC_3300;
 685
 686         if (of_property_read_u32(of_node, "vsc8531,edge-slowdown", &sd))
 687                 sd = 0;
 688
 689         for (i = 0; i < ARRAY_SIZE(edge_table); i++)
 690                 if (edge_table[i].vddmac == vdd)
 691                         for (j = 0; j < sd_array_size; j++)
 692                                 if (edge_table[i].slowdown[j] == sd)
 693                                         return (sd_array_size - j - 1);
 694
 695         return -EINVAL;
 696 }
 697
 698 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev,
 699                                    char *led,
 700                                    u32 default_mode)
 701 {
 702         struct vsc8531_private *priv = phydev->priv;
 703         struct device *dev = &phydev->mdio.dev;
 704         struct device_node *of_node = dev->of_node;
 705         u32 led_mode;
 706         int err;
 707
 708         if (!of_node)
 709                 return -ENODEV;
 710
 711         led_mode = default_mode;
 712         err = of_property_read_u32(of_node, led, &led_mode);
 713         if (!err && !(BIT(led_mode) & priv->supp_led_modes)) {
 714                 phydev_err(phydev, "DT %s invalid\n", led);
 715                 return -EINVAL;
 716         }
 717
 718         return led_mode;
 719 }
 720
 721 #else
 722 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev)
 723 {
 724         return 0;
 725 }
 726
 727 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev,
 728                                    char *led,
 729                                    u8 default_mode)
 730 {
 731         return default_mode;
 732 }
 733 #endif /* CONFIG_OF_MDIO */
 734
 735 static int vsc85xx_dt_led_modes_get(struct phy_device *phydev,
 736                                     u32 *default_mode)
 737 {
 738         struct vsc8531_private *priv = phydev->priv;
 739         char led_dt_prop[28];
 740         int i, ret;
 741
 742         for (i = 0; i < priv->nleds; i++) {
 743                 ret = sprintf(led_dt_prop, "vsc8531,led-%d-mode", i);
 744                 if (ret < 0)
 745                         return ret;
 746
 747                 ret = vsc85xx_dt_led_mode_get(phydev, led_dt_prop,
 748                                               default_mode[i]);
 749                 if (ret < 0)
 750                         return ret;
 751                 priv->leds_mode[i] = ret;
 752         }
 753
 754         return 0;
 755 }
 756
 757 static int vsc85xx_edge_rate_cntl_set(struct phy_device *phydev, u8 edge_rate)
 758 {
 759         int rc;
 760
 761         mutex_lock(&phydev->lock);
 762         rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2,
 763                               MSCC_PHY_WOL_MAC_CONTROL, EDGE_RATE_CNTL_MASK,
 764                               edge_rate << EDGE_RATE_CNTL_POS);
 765         mutex_unlock(&phydev->lock);
 766
 767         return rc;
 768 }
 769
 770 static int vsc85xx_mac_if_set(struct phy_device *phydev,
 771                               phy_interface_t interface)
 772 {
 773         int rc;
 774         u16 reg_val;
 775
 776         mutex_lock(&phydev->lock);
 777         reg_val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1);
 778         reg_val &= ~(MAC_IF_SELECTION_MASK);
 779         switch (interface) {
 780         case PHY_INTERFACE_MODE_RGMII:
 781                 reg_val |= (MAC_IF_SELECTION_RGMII << MAC_IF_SELECTION_POS);
 782                 break;
 783         case PHY_INTERFACE_MODE_RMII:
 784                 reg_val |= (MAC_IF_SELECTION_RMII << MAC_IF_SELECTION_POS);
 785                 break;
 786         case PHY_INTERFACE_MODE_MII:
 787         case PHY_INTERFACE_MODE_GMII:
 788                 reg_val |= (MAC_IF_SELECTION_GMII << MAC_IF_SELECTION_POS);
 789                 break;
 790         default:
 791                 rc = -EINVAL;
 792                 goto out_unlock;
 793         }
 794         rc = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, reg_val);
 795         if (rc)
 796                 goto out_unlock;
 797
 798         rc = genphy_soft_reset(phydev);
 799
 800 out_unlock:
 801         mutex_unlock(&phydev->lock);
 802
 803         return rc;
 804 }
 805
 806 static int vsc85xx_default_config(struct phy_device *phydev)
 807 {
 808         int rc;
 809         u16 reg_val;
 810
 811         phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
 812         mutex_lock(&phydev->lock);
 813         rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2);
 814         if (rc < 0)
 815                 goto out_unlock;
 816
 817         reg_val = phy_read(phydev, MSCC_PHY_RGMII_CNTL);
 818         reg_val &= ~(RGMII_RX_CLK_DELAY_MASK);
 819         reg_val |= (RGMII_RX_CLK_DELAY_1_1_NS << RGMII_RX_CLK_DELAY_POS);
 820         phy_write(phydev, MSCC_PHY_RGMII_CNTL, reg_val);
 821
 822 out_unlock:
 823         rc = phy_restore_page(phydev, rc, rc > 0 ? 0 : rc);
 824         mutex_unlock(&phydev->lock);
 825
 826         return rc;
 827 }
 828
 829 static int vsc85xx_get_tunable(struct phy_device *phydev,
 830                                struct ethtool_tunable *tuna, void *data)
 831 {
 832         switch (tuna->id) {
 833         case ETHTOOL_PHY_DOWNSHIFT:
 834                 return vsc85xx_downshift_get(phydev, (u8 *)data);
 835         default:
 836                 return -EINVAL;
 837         }
 838 }
 839
 840 static int vsc85xx_set_tunable(struct phy_device *phydev,
 841                                struct ethtool_tunable *tuna,
 842                                const void *data)
 843 {
 844         switch (tuna->id) {
 845         case ETHTOOL_PHY_DOWNSHIFT:
 846                 return vsc85xx_downshift_set(phydev, *(u8 *)data);
 847         default:
 848                 return -EINVAL;
 849         }
 850 }
 851
 852 /* mdiobus lock should be locked when using this function */
 853 static void vsc85xx_tr_write(struct phy_device *phydev, u16 addr, u32 val)
 854 {
 855         __phy_write(phydev, MSCC_PHY_TR_MSB, val >> 16);
 856         __phy_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0));
 857         __phy_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr));
 858 }
 859
 860 static int vsc85xx_eee_init_seq_set(struct phy_device *phydev)
 861 {
 862         const struct reg_val init_eee[] = {
 863                 {0x0f82, 0x0012b00a},
 864                 {0x1686, 0x00000004},
 865                 {0x168c, 0x00d2c46f},
 866                 {0x17a2, 0x00000620},
 867                 {0x16a0, 0x00eeffdd},
 868                 {0x16a6, 0x00071448},
 869                 {0x16a4, 0x0013132f},
 870                 {0x16a8, 0x00000000},
 871                 {0x0ffc, 0x00c0a028},
 872                 {0x0fe8, 0x0091b06c},
 873                 {0x0fea, 0x00041600},
 874                 {0x0f80, 0x00000af4},
 875                 {0x0fec, 0x00901809},
 876                 {0x0fee, 0x0000a6a1},
 877                 {0x0ffe, 0x00b01007},
 878                 {0x16b0, 0x00eeff00},
 879                 {0x16b2, 0x00007000},
 880                 {0x16b4, 0x00000814},
 881         };
 882         unsigned int i;
 883         int oldpage;
 884
 885         mutex_lock(&phydev->lock);
 886         oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR);
 887         if (oldpage < 0)
 888                 goto out_unlock;
 889
 890         for (i = 0; i < ARRAY_SIZE(init_eee); i++)
 891                 vsc85xx_tr_write(phydev, init_eee[i].reg, init_eee[i].val);
 892
 893 out_unlock:
 894         oldpage = phy_restore_page(phydev, oldpage, oldpage);
 895         mutex_unlock(&phydev->lock);
 896
 897         return oldpage;
 898 }
 899
 900 /* phydev->bus->mdio_lock should be locked when using this function */
 901 static int phy_base_write(struct phy_device *phydev, u32 regnum, u16 val)
 902 {
 903         struct vsc8531_private *priv = phydev->priv;
 904
 905         if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) {
 906                 dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n");
 907                 dump_stack();
 908         }
 909
 910         return __mdiobus_write(phydev->mdio.bus, priv->base_addr, regnum, val);
 911 }
 912
 913 /* phydev->bus->mdio_lock should be locked when using this function */
 914 static int phy_base_read(struct phy_device *phydev, u32 regnum)
 915 {
 916         struct vsc8531_private *priv = phydev->priv;
 917
 918         if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) {
 919                 dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n");
 920                 dump_stack();
 921         }
 922
 923         return __mdiobus_read(phydev->mdio.bus, priv->base_addr, regnum);
 924 }
 925
 926 /* bus->mdio_lock should be locked when using this function */
 927 static void vsc8584_csr_write(struct phy_device *phydev, u16 addr, u32 val)
 928 {
 929         phy_base_write(phydev, MSCC_PHY_TR_MSB, val >> 16);
 930         phy_base_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0));
 931         phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr));
 932 }
 933
 934 /* bus->mdio_lock should be locked when using this function */
 935 static int vsc8584_cmd(struct phy_device *phydev, u16 val)
 936 {
 937         unsigned long deadline;
 938         u16 reg_val;
 939
 940         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
 941                        MSCC_PHY_PAGE_EXTENDED_GPIO);
 942
 943         phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NCOMPLETED | val);
 944
 945         deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
 946         do {
 947                 reg_val = phy_base_read(phydev, MSCC_PHY_PROC_CMD);
 948         } while (time_before(jiffies, deadline) &&
 949                  (reg_val & PROC_CMD_NCOMPLETED) &&
 950                  !(reg_val & PROC_CMD_FAILED));
 951
 952         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
 953
 954         if (reg_val & PROC_CMD_FAILED)
 955                 return -EIO;
 956
 957         if (reg_val & PROC_CMD_NCOMPLETED)
 958                 return -ETIMEDOUT;
 959
 960         return 0;
 961 }
 962
 963 /* bus->mdio_lock should be locked when using this function */
 964 static int vsc8584_micro_deassert_reset(struct phy_device *phydev,
 965                                         bool patch_en)
 966 {
 967         u32 enable, release;
 968
 969         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
 970                        MSCC_PHY_PAGE_EXTENDED_GPIO);
 971
 972         enable = RUN_FROM_INT_ROM | MICRO_CLK_EN | DW8051_CLK_EN;
 973         release = MICRO_NSOFT_RESET | RUN_FROM_INT_ROM | DW8051_CLK_EN |
 974                 MICRO_CLK_EN;
 975
 976         if (patch_en) {
 977                 enable |= MICRO_PATCH_EN;
 978                 release |= MICRO_PATCH_EN;
 979
 980                 /* Clear all patches */
 981                 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM);
 982         }
 983
 984         /* Enable 8051 Micro clock; CLEAR/SET patch present; disable PRAM clock
 985          * override and addr. auto-incr; operate at 125 MHz
 986          */
 987         phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, enable);
 988         /* Release 8051 Micro SW reset */
 989         phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, release);
 990
 991         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
 992
 993         return 0;
 994 }
 995
 996 /* bus->mdio_lock should be locked when using this function */
 997 static int vsc8584_micro_assert_reset(struct phy_device *phydev)
 998 {
 999         int ret;
1000         u16 reg;
1001
1002         ret = vsc8584_cmd(phydev, PROC_CMD_NOP);
1003         if (ret)
1004                 return ret;
1005
1006         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1007                        MSCC_PHY_PAGE_EXTENDED_GPIO);
1008
1009         reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
1010         reg &= ~EN_PATCH_RAM_TRAP_ADDR(4);
1011         phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
1012
1013         phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(4), 0x005b);
1014         phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(4), 0x005b);
1015
1016         reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
1017         reg |= EN_PATCH_RAM_TRAP_ADDR(4);
1018         phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
1019
1020         phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NOP);
1021
1022         reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS);
1023         reg &= ~MICRO_NSOFT_RESET;
1024         phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, reg);
1025
1026         phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_MCB_ACCESS_MAC_CONF |
1027                        PROC_CMD_SGMII_PORT(0) | PROC_CMD_NO_MAC_CONF |
1028                        PROC_CMD_READ);
1029
1030         reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
1031         reg &= ~EN_PATCH_RAM_TRAP_ADDR(4);
1032         phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
1033
1034         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1035
1036         return 0;
1037 }
1038
1039 /* bus->mdio_lock should be locked when using this function */
1040 static int vsc8584_get_fw_crc(struct phy_device *phydev, u16 start, u16 size,
1041                               u16 *crc)
1042 {
1043         int ret;
1044
1045         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);
1046
1047         phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_2, start);
1048         phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_3, size);
1049
1050         /* Start Micro command */
1051         ret = vsc8584_cmd(phydev, PROC_CMD_CRC16);
1052         if (ret)
1053                 goto out;
1054
1055         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);
1056
1057         *crc = phy_base_read(phydev, MSCC_PHY_VERIPHY_CNTL_2);
1058
1059 out:
1060         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1061
1062         return ret;
1063 }
1064
1065 /* bus->mdio_lock should be locked when using this function */
1066 static int vsc8584_patch_fw(struct phy_device *phydev,
1067                             const struct firmware *fw)
1068 {
1069         int i, ret;
1070
1071         ret = vsc8584_micro_assert_reset(phydev);
1072         if (ret) {
1073                 dev_err(&phydev->mdio.dev,
1074                         "%s: failed to assert reset of micro\n", __func__);
1075                 return ret;
1076         }
1077
1078         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1079                        MSCC_PHY_PAGE_EXTENDED_GPIO);
1080
1081         /* Hold 8051 Micro in SW Reset, Enable auto incr address and patch clock
1082          * Disable the 8051 Micro clock
1083          */
1084         phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, RUN_FROM_INT_ROM |
1085                        AUTOINC_ADDR | PATCH_RAM_CLK | MICRO_CLK_EN |
1086                        MICRO_CLK_DIVIDE(2));
1087         phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM | INT_MEM_WRITE_EN |
1088                        INT_MEM_DATA(2));
1089         phy_base_write(phydev, MSCC_INT_MEM_ADDR, 0x0000);
1090
1091         for (i = 0; i < fw->size; i++)
1092                 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM |
1093                                INT_MEM_WRITE_EN | fw->data[i]);
1094
1095         /* Clear internal memory access */
1096         phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM);
1097
1098         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1099
1100         return 0;
1101 }
1102
1103 /* bus->mdio_lock should be locked when using this function */
1104 static bool vsc8574_is_serdes_init(struct phy_device *phydev)
1105 {
1106         u16 reg;
1107         bool ret;
1108
1109         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1110                        MSCC_PHY_PAGE_EXTENDED_GPIO);
1111
1112         reg = phy_base_read(phydev, MSCC_TRAP_ROM_ADDR(1));
1113         if (reg != 0x3eb7) {
1114                 ret = false;
1115                 goto out;
1116         }
1117
1118         reg = phy_base_read(phydev, MSCC_PATCH_RAM_ADDR(1));
1119         if (reg != 0x4012) {
1120                 ret = false;
1121                 goto out;
1122         }
1123
1124         reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
1125         if (reg != EN_PATCH_RAM_TRAP_ADDR(1)) {
1126                 ret = false;
1127                 goto out;
1128         }
1129
1130         reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS);
1131         if ((MICRO_NSOFT_RESET | RUN_FROM_INT_ROM |  DW8051_CLK_EN |
1132              MICRO_CLK_EN) != (reg & MSCC_DW8051_VLD_MASK)) {
1133                 ret = false;
1134                 goto out;
1135         }
1136
1137         ret = true;
1138 out:
1139         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1140
1141         return ret;
1142 }
1143
1144 /* bus->mdio_lock should be locked when using this function */
1145 static int vsc8574_config_pre_init(struct phy_device *phydev)
1146 {
1147         const struct reg_val pre_init1[] = {
1148                 {0x0fae, 0x000401bd},
1149                 {0x0fac, 0x000f000f},
1150                 {0x17a0, 0x00a0f147},
1151                 {0x0fe4, 0x00052f54},
1152                 {0x1792, 0x0027303d},
1153                 {0x07fe, 0x00000704},
1154                 {0x0fe0, 0x00060150},
1155                 {0x0f82, 0x0012b00a},
1156                 {0x0f80, 0x00000d74},
1157                 {0x02e0, 0x00000012},
1158                 {0x03a2, 0x00050208},
1159                 {0x03b2, 0x00009186},
1160                 {0x0fb0, 0x000e3700},
1161                 {0x1688, 0x00049f81},
1162                 {0x0fd2, 0x0000ffff},
1163                 {0x168a, 0x00039fa2},
1164                 {0x1690, 0x0020640b},
1165                 {0x0258, 0x00002220},
1166                 {0x025a, 0x00002a20},
1167                 {0x025c, 0x00003060},
1168                 {0x025e, 0x00003fa0},
1169                 {0x03a6, 0x0000e0f0},
1170                 {0x0f92, 0x00001489},
1171                 {0x16a2, 0x00007000},
1172                 {0x16a6, 0x00071448},
1173                 {0x16a0, 0x00eeffdd},
1174                 {0x0fe8, 0x0091b06c},
1175                 {0x0fea, 0x00041600},
1176                 {0x16b0, 0x00eeff00},
1177                 {0x16b2, 0x00007000},
1178                 {0x16b4, 0x00000814},
1179                 {0x0f90, 0x00688980},
1180                 {0x03a4, 0x0000d8f0},
1181                 {0x0fc0, 0x00000400},
1182                 {0x07fa, 0x0050100f},
1183                 {0x0796, 0x00000003},
1184                 {0x07f8, 0x00c3ff98},
1185                 {0x0fa4, 0x0018292a},
1186                 {0x168c, 0x00d2c46f},
1187                 {0x17a2, 0x00000620},
1188                 {0x16a4, 0x0013132f},
1189                 {0x16a8, 0x00000000},
1190                 {0x0ffc, 0x00c0a028},
1191                 {0x0fec, 0x00901c09},
1192                 {0x0fee, 0x0004a6a1},
1193                 {0x0ffe, 0x00b01807},
1194         };
1195         const struct reg_val pre_init2[] = {
1196                 {0x0486, 0x0008a518},
1197                 {0x0488, 0x006dc696},
1198                 {0x048a, 0x00000912},
1199                 {0x048e, 0x00000db6},
1200                 {0x049c, 0x00596596},
1201                 {0x049e, 0x00000514},
1202                 {0x04a2, 0x00410280},
1203                 {0x04a4, 0x00000000},
1204                 {0x04a6, 0x00000000},
1205                 {0x04a8, 0x00000000},
1206                 {0x04aa, 0x00000000},
1207                 {0x04ae, 0x007df7dd},
1208                 {0x04b0, 0x006d95d4},
1209                 {0x04b2, 0x00492410},
1210         };
1211         struct device *dev = &phydev->mdio.dev;
1212         const struct firmware *fw;
1213         unsigned int i;
1214         u16 crc, reg;
1215         bool serdes_init;
1216         int ret;
1217
1218         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1219
1220         /* all writes below are broadcasted to all PHYs in the same package */
1221         reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1222         reg |= SMI_BROADCAST_WR_EN;
1223         phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1224
1225         phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0);
1226
1227         /* The below register writes are tweaking analog and electrical
1228          * configuration that were determined through characterization by PHY
1229          * engineers. These don't mean anything more than "these are the best
1230          * values".
1231          */
1232         phy_base_write(phydev, MSCC_PHY_EXT_PHY_CNTL_2, 0x0040);
1233
1234         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1235
1236         phy_base_write(phydev, MSCC_PHY_TEST_PAGE_20, 0x4320);
1237         phy_base_write(phydev, MSCC_PHY_TEST_PAGE_24, 0x0c00);
1238         phy_base_write(phydev, MSCC_PHY_TEST_PAGE_9, 0x18ca);
1239         phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1b20);
1240
1241         reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1242         reg |= 0x8000;
1243         phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1244
1245         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1246
1247         for (i = 0; i < ARRAY_SIZE(pre_init1); i++)
1248                 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
1249
1250         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2);
1251
1252         phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e);
1253
1254         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1255
1256         for (i = 0; i < ARRAY_SIZE(pre_init2); i++)
1257                 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val);
1258
1259         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1260
1261         reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1262         reg &= ~0x8000;
1263         phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1264
1265         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1266
1267         /* end of write broadcasting */
1268         reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1269         reg &= ~SMI_BROADCAST_WR_EN;
1270         phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1271
1272         ret = request_firmware(&fw, MSCC_VSC8574_REVB_INT8051_FW, dev);
1273         if (ret) {
1274                 dev_err(dev, "failed to load firmware %s, ret: %d\n",
1275                         MSCC_VSC8574_REVB_INT8051_FW, ret);
1276                 return ret;
1277         }
1278
1279         /* Add one byte to size for the one added by the patch_fw function */
1280         ret = vsc8584_get_fw_crc(phydev,
1281                                  MSCC_VSC8574_REVB_INT8051_FW_START_ADDR,
1282                                  fw->size + 1, &crc);
1283         if (ret)
1284                 goto out;
1285
1286         if (crc == MSCC_VSC8574_REVB_INT8051_FW_CRC) {
1287                 serdes_init = vsc8574_is_serdes_init(phydev);
1288
1289                 if (!serdes_init) {
1290                         ret = vsc8584_micro_assert_reset(phydev);
1291                         if (ret) {
1292                                 dev_err(dev,
1293                                         "%s: failed to assert reset of micro\n",
1294                                         __func__);
1295                                 goto out;
1296                         }
1297                 }
1298         } else {
1299                 dev_dbg(dev, "FW CRC is not the expected one, patching FW\n");
1300
1301                 serdes_init = false;
1302
1303                 if (vsc8584_patch_fw(phydev, fw))
1304                         dev_warn(dev,
1305                                  "failed to patch FW, expect non-optimal device\n");
1306         }
1307
1308         if (!serdes_init) {
1309                 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1310                                MSCC_PHY_PAGE_EXTENDED_GPIO);
1311
1312                 phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), 0x3eb7);
1313                 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), 0x4012);
1314                 phy_base_write(phydev, MSCC_INT_MEM_CNTL,
1315                                EN_PATCH_RAM_TRAP_ADDR(1));
1316
1317                 vsc8584_micro_deassert_reset(phydev, false);
1318
1319                 /* Add one byte to size for the one added by the patch_fw
1320                  * function
1321                  */
1322                 ret = vsc8584_get_fw_crc(phydev,
1323                                          MSCC_VSC8574_REVB_INT8051_FW_START_ADDR,
1324                                          fw->size + 1, &crc);
1325                 if (ret)
1326                         goto out;
1327
1328                 if (crc != MSCC_VSC8574_REVB_INT8051_FW_CRC)
1329                         dev_warn(dev,
1330                                  "FW CRC after patching is not the expected one, expect non-optimal device\n");
1331         }
1332
1333         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1334                        MSCC_PHY_PAGE_EXTENDED_GPIO);
1335
1336         ret = vsc8584_cmd(phydev, PROC_CMD_1588_DEFAULT_INIT |
1337                           PROC_CMD_PHY_INIT);
1338
1339 out:
1340         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1341
1342         release_firmware(fw);
1343
1344         return ret;
1345 }
1346
1347 /* bus->mdio_lock should be locked when using this function */
1348 static int vsc8584_config_pre_init(struct phy_device *phydev)
1349 {
1350         const struct reg_val pre_init1[] = {
1351                 {0x07fa, 0x0050100f},
1352                 {0x1688, 0x00049f81},
1353                 {0x0f90, 0x00688980},
1354                 {0x03a4, 0x0000d8f0},
1355                 {0x0fc0, 0x00000400},
1356                 {0x0f82, 0x0012b002},
1357                 {0x1686, 0x00000004},
1358                 {0x168c, 0x00d2c46f},
1359                 {0x17a2, 0x00000620},
1360                 {0x16a0, 0x00eeffdd},
1361                 {0x16a6, 0x00071448},
1362                 {0x16a4, 0x0013132f},
1363                 {0x16a8, 0x00000000},
1364                 {0x0ffc, 0x00c0a028},
1365                 {0x0fe8, 0x0091b06c},
1366                 {0x0fea, 0x00041600},
1367                 {0x0f80, 0x00fffaff},
1368                 {0x0fec, 0x00901809},
1369                 {0x0ffe, 0x00b01007},
1370                 {0x16b0, 0x00eeff00},
1371                 {0x16b2, 0x00007000},
1372                 {0x16b4, 0x00000814},
1373         };
1374         const struct reg_val pre_init2[] = {
1375                 {0x0486, 0x0008a518},
1376                 {0x0488, 0x006dc696},
1377                 {0x048a, 0x00000912},
1378         };
1379         const struct firmware *fw;
1380         struct device *dev = &phydev->mdio.dev;
1381         unsigned int i;
1382         u16 crc, reg;
1383         int ret;
1384
1385         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1386
1387         /* all writes below are broadcasted to all PHYs in the same package */
1388         reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1389         reg |= SMI_BROADCAST_WR_EN;
1390         phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1391
1392         phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0);
1393
1394         reg = phy_base_read(phydev,  MSCC_PHY_BYPASS_CONTROL);
1395         reg |= PARALLEL_DET_IGNORE_ADVERTISED;
1396         phy_base_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg);
1397
1398         /* The below register writes are tweaking analog and electrical
1399          * configuration that were determined through characterization by PHY
1400          * engineers. These don't mean anything more than "these are the best
1401          * values".
1402          */
1403         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_3);
1404
1405         phy_base_write(phydev, MSCC_PHY_SERDES_TX_CRC_ERR_CNT, 0x2000);
1406
1407         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1408
1409         phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1f20);
1410
1411         reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1412         reg |= 0x8000;
1413         phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1414
1415         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1416
1417         phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x2fa4));
1418
1419         reg = phy_base_read(phydev, MSCC_PHY_TR_MSB);
1420         reg &= ~0x007f;
1421         reg |= 0x0019;
1422         phy_base_write(phydev, MSCC_PHY_TR_MSB, reg);
1423
1424         phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x0fa4));
1425
1426         for (i = 0; i < ARRAY_SIZE(pre_init1); i++)
1427                 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
1428
1429         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2);
1430
1431         phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e);
1432
1433         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1434
1435         for (i = 0; i < ARRAY_SIZE(pre_init2); i++)
1436                 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val);
1437
1438         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1439
1440         reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1441         reg &= ~0x8000;
1442         phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1443
1444         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1445
1446         /* end of write broadcasting */
1447         reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1448         reg &= ~SMI_BROADCAST_WR_EN;
1449         phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1450
1451         ret = request_firmware(&fw, MSCC_VSC8584_REVB_INT8051_FW, dev);
1452         if (ret) {
1453                 dev_err(dev, "failed to load firmware %s, ret: %d\n",
1454                         MSCC_VSC8584_REVB_INT8051_FW, ret);
1455                 return ret;
1456         }
1457
1458         /* Add one byte to size for the one added by the patch_fw function */
1459         ret = vsc8584_get_fw_crc(phydev,
1460                                  MSCC_VSC8584_REVB_INT8051_FW_START_ADDR,
1461                                  fw->size + 1, &crc);
1462         if (ret)
1463                 goto out;
1464
1465         if (crc != MSCC_VSC8584_REVB_INT8051_FW_CRC) {
1466                 dev_dbg(dev, "FW CRC is not the expected one, patching FW\n");
1467                 if (vsc8584_patch_fw(phydev, fw))
1468                         dev_warn(dev,
1469                                  "failed to patch FW, expect non-optimal device\n");
1470         }
1471
1472         vsc8584_micro_deassert_reset(phydev, false);
1473
1474         /* Add one byte to size for the one added by the patch_fw function */
1475         ret = vsc8584_get_fw_crc(phydev,
1476                                  MSCC_VSC8584_REVB_INT8051_FW_START_ADDR,
1477                                  fw->size + 1, &crc);
1478         if (ret)
1479                 goto out;
1480
1481         if (crc != MSCC_VSC8584_REVB_INT8051_FW_CRC)
1482                 dev_warn(dev,
1483                          "FW CRC after patching is not the expected one, expect non-optimal device\n");
1484
1485         ret = vsc8584_micro_assert_reset(phydev);
1486         if (ret)
1487                 goto out;
1488
1489         vsc8584_micro_deassert_reset(phydev, true);
1490
1491 out:
1492         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1493
1494         release_firmware(fw);
1495
1496         return ret;
1497 }
1498
1499 /* Check if one PHY has already done the init of the parts common to all PHYs
1500  * in the Quad PHY package.
1501  */
1502 static bool vsc8584_is_pkg_init(struct phy_device *phydev, bool reversed)
1503 {
1504         struct mdio_device **map = phydev->mdio.bus->mdio_map;
1505         struct vsc8531_private *vsc8531;
1506         struct phy_device *phy;
1507         int i, addr;
1508
1509         /* VSC8584 is a Quad PHY */
1510         for (i = 0; i < 4; i++) {
1511                 vsc8531 = phydev->priv;
1512
1513                 if (reversed)
1514                         addr = vsc8531->base_addr - i;
1515                 else
1516                         addr = vsc8531->base_addr + i;
1517
1518                 phy = container_of(map[addr], struct phy_device, mdio);
1519
1520                 if ((phy->phy_id & phydev->drv->phy_id_mask) !=
1521                     (phydev->drv->phy_id & phydev->drv->phy_id_mask))
1522                         continue;
1523
1524                 vsc8531 = phy->priv;
1525
1526                 if (vsc8531 && vsc8531->pkg_init)
1527                         return true;
1528         }
1529
1530         return false;
1531 }
1532
1533 static int vsc8584_config_init(struct phy_device *phydev)
1534 {
1535         struct vsc8531_private *vsc8531 = phydev->priv;
1536         u16 addr, val;
1537         int ret, i;
1538
1539         phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1540
1541         mutex_lock(&phydev->mdio.bus->mdio_lock);
1542
1543         __mdiobus_write(phydev->mdio.bus, phydev->mdio.addr,
1544                         MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);
1545         addr = __mdiobus_read(phydev->mdio.bus, phydev->mdio.addr,
1546                               MSCC_PHY_EXT_PHY_CNTL_4);
1547         addr >>= PHY_CNTL_4_ADDR_POS;
1548
1549         val = __mdiobus_read(phydev->mdio.bus, phydev->mdio.addr,
1550                              MSCC_PHY_ACTIPHY_CNTL);
1551         if (val & PHY_ADDR_REVERSED)
1552                 vsc8531->base_addr = phydev->mdio.addr + addr;
1553         else
1554                 vsc8531->base_addr = phydev->mdio.addr - addr;
1555
1556         /* Some parts of the init sequence are identical for every PHY in the
1557          * package. Some parts are modifying the GPIO register bank which is a
1558          * set of registers that are affecting all PHYs, a few resetting the
1559          * microprocessor common to all PHYs. The CRC check responsible of the
1560          * checking the firmware within the 8051 microprocessor can only be
1561          * accessed via the PHY whose internal address in the package is 0.
1562          * All PHYs' interrupts mask register has to be zeroed before enabling
1563          * any PHY's interrupt in this register.
1564          * For all these reasons, we need to do the init sequence once and only
1565          * once whatever is the first PHY in the package that is initialized and
1566          * do the correct init sequence for all PHYs that are package-critical
1567          * in this pre-init function.
1568          */
1569         if (!vsc8584_is_pkg_init(phydev, val & PHY_ADDR_REVERSED ? 1 : 0)) {
1570                 if ((phydev->phy_id & phydev->drv->phy_id_mask) ==
1571                     (PHY_ID_VSC8574 & phydev->drv->phy_id_mask))
1572                         ret = vsc8574_config_pre_init(phydev);
1573                 else if ((phydev->phy_id & phydev->drv->phy_id_mask) ==
1574                          (PHY_ID_VSC8584 & phydev->drv->phy_id_mask))
1575                         ret = vsc8584_config_pre_init(phydev);
1576                 else
1577                         ret = -EINVAL;
1578
1579                 if (ret)
1580                         goto err;
1581         }
1582
1583         vsc8531->pkg_init = true;
1584
1585         phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1586                        MSCC_PHY_PAGE_EXTENDED_GPIO);
1587
1588         val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);
1589         val &= ~MAC_CFG_MASK;
1590         if (phydev->interface == PHY_INTERFACE_MODE_QSGMII)
1591                 val |= MAC_CFG_QSGMII;
1592         else
1593                 val |= MAC_CFG_SGMII;
1594
1595         ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val);
1596         if (ret)
1597                 goto err;
1598
1599         val = PROC_CMD_MCB_ACCESS_MAC_CONF | PROC_CMD_RST_CONF_PORT |
1600                 PROC_CMD_READ_MOD_WRITE_PORT;
1601         if (phydev->interface == PHY_INTERFACE_MODE_QSGMII)
1602                 val |= PROC_CMD_QSGMII_MAC;
1603         else
1604                 val |= PROC_CMD_SGMII_MAC;
1605
1606         ret = vsc8584_cmd(phydev, val);
1607         if (ret)
1608                 goto err;
1609
1610         usleep_range(10000, 20000);
1611
1612         /* Disable SerDes for 100Base-FX */
1613         ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF |
1614                           PROC_CMD_FIBER_PORT(addr) | PROC_CMD_FIBER_DISABLE |
1615                           PROC_CMD_READ_MOD_WRITE_PORT |
1616                           PROC_CMD_RST_CONF_PORT | PROC_CMD_FIBER_100BASE_FX);
1617         if (ret)
1618                 goto err;
1619
1620         /* Disable SerDes for 1000Base-X */
1621         ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF |
1622                           PROC_CMD_FIBER_PORT(addr) | PROC_CMD_FIBER_DISABLE |
1623                           PROC_CMD_READ_MOD_WRITE_PORT |
1624                           PROC_CMD_RST_CONF_PORT | PROC_CMD_FIBER_1000BASE_X);
1625         if (ret)
1626                 goto err;
1627
1628         mutex_unlock(&phydev->mdio.bus->mdio_lock);
1629
1630         phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1631
1632         val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1);
1633         val &= ~(MEDIA_OP_MODE_MASK | VSC8584_MAC_IF_SELECTION_MASK);
1634         val |= MEDIA_OP_MODE_COPPER | (VSC8584_MAC_IF_SELECTION_SGMII <<
1635                                        VSC8584_MAC_IF_SELECTION_POS);
1636         ret = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, val);
1637
1638         ret = genphy_soft_reset(phydev);
1639         if (ret)
1640                 return ret;
1641
1642         for (i = 0; i < vsc8531->nleds; i++) {
1643                 ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]);
1644                 if (ret)
1645                         return ret;
1646         }
1647
1648         return genphy_config_init(phydev);
1649
1650 err:
1651         mutex_unlock(&phydev->mdio.bus->mdio_lock);
1652         return ret;
1653 }
1654
1655 static int vsc85xx_config_init(struct phy_device *phydev)
1656 {
1657         int rc, i;
1658         struct vsc8531_private *vsc8531 = phydev->priv;
1659
1660         rc = vsc85xx_default_config(phydev);
1661         if (rc)
1662                 return rc;
1663
1664         rc = vsc85xx_mac_if_set(phydev, phydev->interface);
1665         if (rc)
1666                 return rc;
1667
1668         rc = vsc85xx_edge_rate_cntl_set(phydev, vsc8531->rate_magic);
1669         if (rc)
1670                 return rc;
1671
1672         rc = vsc85xx_eee_init_seq_set(phydev);
1673         if (rc)
1674                 return rc;
1675
1676         for (i = 0; i < vsc8531->nleds; i++) {
1677                 rc = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]);
1678                 if (rc)
1679                         return rc;
1680         }
1681
1682         return genphy_config_init(phydev);
1683 }
1684
1685 static int vsc8584_did_interrupt(struct phy_device *phydev)
1686 {
1687         int rc = 0;
1688
1689         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
1690                 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
1691
1692         return (rc < 0) ? 0 : rc & MII_VSC85XX_INT_MASK_MASK;
1693 }
1694
1695 static int vsc85xx_ack_interrupt(struct phy_device *phydev)
1696 {
1697         int rc = 0;
1698
1699         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
1700                 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
1701
1702         return (rc < 0) ? rc : 0;
1703 }
1704
1705 static int vsc85xx_config_intr(struct phy_device *phydev)
1706 {
1707         int rc;
1708
1709         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1710                 rc = phy_write(phydev, MII_VSC85XX_INT_MASK,
1711                                MII_VSC85XX_INT_MASK_MASK);
1712         } else {
1713                 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, 0);
1714                 if (rc < 0)
1715                         return rc;
1716                 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
1717         }
1718
1719         return rc;
1720 }
1721
1722 static int vsc85xx_config_aneg(struct phy_device *phydev)
1723 {
1724         int rc;
1725
1726         rc = vsc85xx_mdix_set(phydev, phydev->mdix_ctrl);
1727         if (rc < 0)
1728                 return rc;
1729
1730         return genphy_config_aneg(phydev);
1731 }
1732
1733 static int vsc85xx_read_status(struct phy_device *phydev)
1734 {
1735         int rc;
1736
1737         rc = vsc85xx_mdix_get(phydev, &phydev->mdix);
1738         if (rc < 0)
1739                 return rc;
1740
1741         return genphy_read_status(phydev);
1742 }
1743
1744 static int vsc8574_probe(struct phy_device *phydev)
1745 {
1746         struct vsc8531_private *vsc8531;
1747         u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY,
1748            VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY,
1749            VSC8531_DUPLEX_COLLISION};
1750
1751         vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
1752         if (!vsc8531)
1753                 return -ENOMEM;
1754
1755         phydev->priv = vsc8531;
1756
1757         vsc8531->nleds = 4;
1758         vsc8531->supp_led_modes = VSC8584_SUPP_LED_MODES;
1759         vsc8531->hw_stats = vsc8584_hw_stats;
1760         vsc8531->nstats = ARRAY_SIZE(vsc8584_hw_stats);
1761         vsc8531->stats = devm_kmalloc_array(&phydev->mdio.dev, vsc8531->nstats,
1762                                             sizeof(u64), GFP_KERNEL);
1763         if (!vsc8531->stats)
1764                 return -ENOMEM;
1765
1766         return vsc85xx_dt_led_modes_get(phydev, default_mode);
1767 }
1768
1769 static int vsc8584_probe(struct phy_device *phydev)
1770 {
1771         struct vsc8531_private *vsc8531;
1772         u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY,
1773            VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY,
1774            VSC8531_DUPLEX_COLLISION};
1775
1776         if ((phydev->phy_id & MSCC_DEV_REV_MASK) != VSC8584_REVB) {
1777                 dev_err(&phydev->mdio.dev, "Only VSC8584 revB is supported.\n");
1778                 return -ENOTSUPP;
1779         }
1780
1781         vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
1782         if (!vsc8531)
1783                 return -ENOMEM;
1784
1785         phydev->priv = vsc8531;
1786
1787         vsc8531->nleds = 4;
1788         vsc8531->supp_led_modes = VSC8584_SUPP_LED_MODES;
1789         vsc8531->hw_stats = vsc8584_hw_stats;
1790         vsc8531->nstats = ARRAY_SIZE(vsc8584_hw_stats);
1791         vsc8531->stats = devm_kmalloc_array(&phydev->mdio.dev, vsc8531->nstats,
1792                                             sizeof(u64), GFP_KERNEL);
1793         if (!vsc8531->stats)
1794                 return -ENOMEM;
1795
1796         return vsc85xx_dt_led_modes_get(phydev, default_mode);
1797 }
1798
1799 static int vsc85xx_probe(struct phy_device *phydev)
1800 {
1801         struct vsc8531_private *vsc8531;
1802         int rate_magic;
1803         u32 default_mode[2] = {VSC8531_LINK_1000_ACTIVITY,
1804            VSC8531_LINK_100_ACTIVITY};
1805
1806         rate_magic = vsc85xx_edge_rate_magic_get(phydev);
1807         if (rate_magic < 0)
1808                 return rate_magic;
1809
1810         vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
1811         if (!vsc8531)
1812                 return -ENOMEM;
1813
1814         phydev->priv = vsc8531;
1815
1816         vsc8531->rate_magic = rate_magic;
1817         vsc8531->nleds = 2;
1818         vsc8531->supp_led_modes = VSC85XX_SUPP_LED_MODES;
1819         vsc8531->hw_stats = vsc85xx_hw_stats;
1820         vsc8531->nstats = ARRAY_SIZE(vsc85xx_hw_stats);
1821         vsc8531->stats = devm_kmalloc_array(&phydev->mdio.dev, vsc8531->nstats,
1822                                             sizeof(u64), GFP_KERNEL);
1823         if (!vsc8531->stats)
1824                 return -ENOMEM;
1825
1826         return vsc85xx_dt_led_modes_get(phydev, default_mode);
1827 }
1828
1829 /* Microsemi VSC85xx PHYs */
1830 static struct phy_driver vsc85xx_driver[] = {
1831 {
1832         .phy_id         = PHY_ID_VSC8530,
1833         .name           = "Microsemi FE VSC8530",
1834         .phy_id_mask    = 0xfffffff0,
1835         .features       = PHY_BASIC_FEATURES,
1836         .flags          = PHY_HAS_INTERRUPT,
1837         .soft_reset     = &genphy_soft_reset,
1838         .config_init    = &vsc85xx_config_init,
1839         .config_aneg    = &vsc85xx_config_aneg,
1840         .aneg_done      = &genphy_aneg_done,
1841         .read_status    = &vsc85xx_read_status,
1842         .ack_interrupt  = &vsc85xx_ack_interrupt,
1843         .config_intr    = &vsc85xx_config_intr,
1844         .suspend        = &genphy_suspend,
1845         .resume         = &genphy_resume,
1846         .probe          = &vsc85xx_probe,
1847         .set_wol        = &vsc85xx_wol_set,
1848         .get_wol        = &vsc85xx_wol_get,
1849         .get_tunable    = &vsc85xx_get_tunable,
1850         .set_tunable    = &vsc85xx_set_tunable,
1851         .read_page      = &vsc85xx_phy_read_page,
1852         .write_page     = &vsc85xx_phy_write_page,
1853         .get_sset_count = &vsc85xx_get_sset_count,
1854         .get_strings    = &vsc85xx_get_strings,
1855         .get_stats      = &vsc85xx_get_stats,
1856 },
1857 {
1858         .phy_id         = PHY_ID_VSC8531,
1859         .name           = "Microsemi VSC8531",
1860         .phy_id_mask    = 0xfffffff0,
1861         .features       = PHY_GBIT_FEATURES,
1862         .flags          = PHY_HAS_INTERRUPT,
1863         .soft_reset     = &genphy_soft_reset,
1864         .config_init    = &vsc85xx_config_init,
1865         .config_aneg    = &vsc85xx_config_aneg,
1866         .aneg_done      = &genphy_aneg_done,
1867         .read_status    = &vsc85xx_read_status,
1868         .ack_interrupt  = &vsc85xx_ack_interrupt,
1869         .config_intr    = &vsc85xx_config_intr,
1870         .suspend        = &genphy_suspend,
1871         .resume         = &genphy_resume,
1872         .probe          = &vsc85xx_probe,
1873         .set_wol        = &vsc85xx_wol_set,
1874         .get_wol        = &vsc85xx_wol_get,
1875         .get_tunable    = &vsc85xx_get_tunable,
1876         .set_tunable    = &vsc85xx_set_tunable,
1877         .read_page      = &vsc85xx_phy_read_page,
1878         .write_page     = &vsc85xx_phy_write_page,
1879         .get_sset_count = &vsc85xx_get_sset_count,
1880         .get_strings    = &vsc85xx_get_strings,
1881         .get_stats      = &vsc85xx_get_stats,
1882 },
1883 {
1884         .phy_id         = PHY_ID_VSC8540,
1885         .name           = "Microsemi FE VSC8540 SyncE",
1886         .phy_id_mask    = 0xfffffff0,
1887         .features       = PHY_BASIC_FEATURES,
1888         .flags          = PHY_HAS_INTERRUPT,
1889         .soft_reset     = &genphy_soft_reset,
1890         .config_init    = &vsc85xx_config_init,
1891         .config_aneg    = &vsc85xx_config_aneg,
1892         .aneg_done      = &genphy_aneg_done,
1893         .read_status    = &vsc85xx_read_status,
1894         .ack_interrupt  = &vsc85xx_ack_interrupt,
1895         .config_intr    = &vsc85xx_config_intr,
1896         .suspend        = &genphy_suspend,
1897         .resume         = &genphy_resume,
1898         .probe          = &vsc85xx_probe,
1899         .set_wol        = &vsc85xx_wol_set,
1900         .get_wol        = &vsc85xx_wol_get,
1901         .get_tunable    = &vsc85xx_get_tunable,
1902         .set_tunable    = &vsc85xx_set_tunable,
1903         .read_page      = &vsc85xx_phy_read_page,
1904         .write_page     = &vsc85xx_phy_write_page,
1905         .get_sset_count = &vsc85xx_get_sset_count,
1906         .get_strings    = &vsc85xx_get_strings,
1907         .get_stats      = &vsc85xx_get_stats,
1908 },
1909 {
1910         .phy_id         = PHY_ID_VSC8541,
1911         .name           = "Microsemi VSC8541 SyncE",
1912         .phy_id_mask    = 0xfffffff0,
1913         .features       = PHY_GBIT_FEATURES,
1914         .flags          = PHY_HAS_INTERRUPT,
1915         .soft_reset     = &genphy_soft_reset,
1916         .config_init    = &vsc85xx_config_init,
1917         .config_aneg    = &vsc85xx_config_aneg,
1918         .aneg_done      = &genphy_aneg_done,
1919         .read_status    = &vsc85xx_read_status,
1920         .ack_interrupt  = &vsc85xx_ack_interrupt,
1921         .config_intr    = &vsc85xx_config_intr,
1922         .suspend        = &genphy_suspend,
1923         .resume         = &genphy_resume,
1924         .probe          = &vsc85xx_probe,
1925         .set_wol        = &vsc85xx_wol_set,
1926         .get_wol        = &vsc85xx_wol_get,
1927         .get_tunable    = &vsc85xx_get_tunable,
1928         .set_tunable    = &vsc85xx_set_tunable,
1929         .read_page      = &vsc85xx_phy_read_page,
1930         .write_page     = &vsc85xx_phy_write_page,
1931         .get_sset_count = &vsc85xx_get_sset_count,
1932         .get_strings    = &vsc85xx_get_strings,
1933         .get_stats      = &vsc85xx_get_stats,
1934 },
1935 {
1936         .phy_id         = PHY_ID_VSC8574,
1937         .name           = "Microsemi GE VSC8574 SyncE",
1938         .phy_id_mask    = 0xfffffff0,
1939         .features       = PHY_GBIT_FEATURES,
1940         .flags          = PHY_HAS_INTERRUPT,
1941         .soft_reset     = &genphy_soft_reset,
1942         .config_init    = &vsc8584_config_init,
1943         .config_aneg    = &vsc85xx_config_aneg,
1944         .aneg_done      = &genphy_aneg_done,
1945         .read_status    = &vsc85xx_read_status,
1946         .ack_interrupt  = &vsc85xx_ack_interrupt,
1947         .config_intr    = &vsc85xx_config_intr,
1948         .did_interrupt  = &vsc8584_did_interrupt,
1949         .suspend        = &genphy_suspend,
1950         .resume         = &genphy_resume,
1951         .probe          = &vsc8574_probe,
1952         .set_wol        = &vsc85xx_wol_set,
1953         .get_wol        = &vsc85xx_wol_get,
1954         .get_tunable    = &vsc85xx_get_tunable,
1955         .set_tunable    = &vsc85xx_set_tunable,
1956         .read_page      = &vsc85xx_phy_read_page,
1957         .write_page     = &vsc85xx_phy_write_page,
1958         .get_sset_count = &vsc85xx_get_sset_count,
1959         .get_strings    = &vsc85xx_get_strings,
1960         .get_stats      = &vsc85xx_get_stats,
1961 },
1962 {
1963         .phy_id         = PHY_ID_VSC8584,
1964         .name           = "Microsemi GE VSC8584 SyncE",
1965         .phy_id_mask    = 0xfffffff0,
1966         .features       = PHY_GBIT_FEATURES,
1967         .flags          = PHY_HAS_INTERRUPT,
1968         .soft_reset     = &genphy_soft_reset,
1969         .config_init    = &vsc8584_config_init,
1970         .config_aneg    = &vsc85xx_config_aneg,
1971         .aneg_done      = &genphy_aneg_done,
1972         .read_status    = &vsc85xx_read_status,
1973         .ack_interrupt  = &vsc85xx_ack_interrupt,
1974         .config_intr    = &vsc85xx_config_intr,
1975         .did_interrupt  = &vsc8584_did_interrupt,
1976         .suspend        = &genphy_suspend,
1977         .resume         = &genphy_resume,
1978         .probe          = &vsc8584_probe,
1979         .get_tunable    = &vsc85xx_get_tunable,
1980         .set_tunable    = &vsc85xx_set_tunable,
1981         .read_page      = &vsc85xx_phy_read_page,
1982         .write_page     = &vsc85xx_phy_write_page,
1983         .get_sset_count = &vsc85xx_get_sset_count,
1984         .get_strings    = &vsc85xx_get_strings,
1985         .get_stats      = &vsc85xx_get_stats,
1986 }
1987
1988 };
1989
1990 module_phy_driver(vsc85xx_driver);
1991
1992 static struct mdio_device_id __maybe_unused vsc85xx_tbl[] = {
1993         { PHY_ID_VSC8530, 0xfffffff0, },
1994         { PHY_ID_VSC8531, 0xfffffff0, },
1995         { PHY_ID_VSC8540, 0xfffffff0, },
1996         { PHY_ID_VSC8541, 0xfffffff0, },
1997         { PHY_ID_VSC8574, 0xfffffff0, },
1998         { PHY_ID_VSC8584, 0xfffffff0, },
1999         { }
2000 };
2001
2002 MODULE_DEVICE_TABLE(mdio, vsc85xx_tbl);
2003
2004 MODULE_DESCRIPTION("Microsemi VSC85xx PHY driver");
2005 MODULE_AUTHOR("Nagaraju Lakkaraju");
2006 MODULE_LICENSE("Dual MIT/GPL");