drivers/net/phy/micrel.c

   1 /*
   2  * drivers/net/phy/micrel.c
   3  *
   4  * Driver for Micrel PHYs
   5  *
   6  * Author: David J. Choi
   7  *
   8  * Copyright (c) 2010-2013 Micrel, Inc.
   9  * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
  10  *
  11  * This program is free software; you can redistribute  it and/or modify it
  12  * under  the terms of  the GNU General  Public License as published by the
  13  * Free Software Foundation;  either version 2 of the  License, or (at your
  14  * option) any later version.
  15  *
  16  * Support : Micrel Phys:
  17  *              Giga phys: ksz9021, ksz9031, ksz9131
  18  *              100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
  19  *                         ksz8021, ksz8031, ksz8051,
  20  *                         ksz8081, ksz8091,
  21  *                         ksz8061,
  22  *              Switch : ksz8873, ksz886x
  23  *                       ksz9477
  24  */
  25
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/phy.h>
  29 #include <linux/micrel_phy.h>
  30 #include <linux/of.h>
  31 #include <linux/clk.h>
  32
  33 /* Operation Mode Strap Override */
  34 #define MII_KSZPHY_OMSO                         0x16
  35 #define KSZPHY_OMSO_B_CAST_OFF                  BIT(9)
  36 #define KSZPHY_OMSO_NAND_TREE_ON                BIT(5)
  37 #define KSZPHY_OMSO_RMII_OVERRIDE               BIT(1)
  38 #define KSZPHY_OMSO_MII_OVERRIDE                BIT(0)
  39
  40 /* general Interrupt control/status reg in vendor specific block. */
  41 #define MII_KSZPHY_INTCS                        0x1B
  42 #define KSZPHY_INTCS_JABBER                     BIT(15)
  43 #define KSZPHY_INTCS_RECEIVE_ERR                BIT(14)
  44 #define KSZPHY_INTCS_PAGE_RECEIVE               BIT(13)
  45 #define KSZPHY_INTCS_PARELLEL                   BIT(12)
  46 #define KSZPHY_INTCS_LINK_PARTNER_ACK           BIT(11)
  47 #define KSZPHY_INTCS_LINK_DOWN                  BIT(10)
  48 #define KSZPHY_INTCS_REMOTE_FAULT               BIT(9)
  49 #define KSZPHY_INTCS_LINK_UP                    BIT(8)
  50 #define KSZPHY_INTCS_ALL                        (KSZPHY_INTCS_LINK_UP |\
  51                                                 KSZPHY_INTCS_LINK_DOWN)
  52
  53 /* PHY Control 1 */
  54 #define MII_KSZPHY_CTRL_1                       0x1e
  55
  56 /* PHY Control 2 / PHY Control (if no PHY Control 1) */
  57 #define MII_KSZPHY_CTRL_2                       0x1f
  58 #define MII_KSZPHY_CTRL                         MII_KSZPHY_CTRL_2
  59 /* bitmap of PHY register to set interrupt mode */
  60 #define KSZPHY_CTRL_INT_ACTIVE_HIGH             BIT(9)
  61 #define KSZPHY_RMII_REF_CLK_SEL                 BIT(7)
  62
  63 /* Write/read to/from extended registers */
  64 #define MII_KSZPHY_EXTREG                       0x0b
  65 #define KSZPHY_EXTREG_WRITE                     0x8000
  66
  67 #define MII_KSZPHY_EXTREG_WRITE                 0x0c
  68 #define MII_KSZPHY_EXTREG_READ                  0x0d
  69
  70 /* Extended registers */
  71 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW         0x104
  72 #define MII_KSZPHY_RX_DATA_PAD_SKEW             0x105
  73 #define MII_KSZPHY_TX_DATA_PAD_SKEW             0x106
  74
  75 #define PS_TO_REG                               200
  76
  77 struct kszphy_hw_stat {
  78         const char *string;
  79         u8 reg;
  80         u8 bits;
  81 };
  82
  83 static struct kszphy_hw_stat kszphy_hw_stats[] = {
  84         { "phy_receive_errors", 21, 16},
  85         { "phy_idle_errors", 10, 8 },
  86 };
  87
  88 struct kszphy_type {
  89         u32 led_mode_reg;
  90         u16 interrupt_level_mask;
  91         bool has_broadcast_disable;
  92         bool has_nand_tree_disable;
  93         bool has_rmii_ref_clk_sel;
  94 };
  95
  96 struct kszphy_priv {
  97         const struct kszphy_type *type;
  98         int led_mode;
  99         bool rmii_ref_clk_sel;
 100         bool rmii_ref_clk_sel_val;
 101         u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
 102 };
 103
 104 static const struct kszphy_type ksz8021_type = {
 105         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 106         .has_broadcast_disable  = true,
 107         .has_nand_tree_disable  = true,
 108         .has_rmii_ref_clk_sel   = true,
 109 };
 110
 111 static const struct kszphy_type ksz8041_type = {
 112         .led_mode_reg           = MII_KSZPHY_CTRL_1,
 113 };
 114
 115 static const struct kszphy_type ksz8051_type = {
 116         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 117         .has_nand_tree_disable  = true,
 118 };
 119
 120 static const struct kszphy_type ksz8081_type = {
 121         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 122         .has_broadcast_disable  = true,
 123         .has_nand_tree_disable  = true,
 124         .has_rmii_ref_clk_sel   = true,
 125 };
 126
 127 static const struct kszphy_type ks8737_type = {
 128         .interrupt_level_mask   = BIT(14),
 129 };
 130
 131 static const struct kszphy_type ksz9021_type = {
 132         .interrupt_level_mask   = BIT(14),
 133 };
 134
 135 static int kszphy_extended_write(struct phy_device *phydev,
 136                                 u32 regnum, u16 val)
 137 {
 138         phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
 139         return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
 140 }
 141
 142 static int kszphy_extended_read(struct phy_device *phydev,
 143                                 u32 regnum)
 144 {
 145         phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
 146         return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
 147 }
 148
 149 static int kszphy_ack_interrupt(struct phy_device *phydev)
 150 {
 151         /* bit[7..0] int status, which is a read and clear register. */
 152         int rc;
 153
 154         rc = phy_read(phydev, MII_KSZPHY_INTCS);
 155
 156         return (rc < 0) ? rc : 0;
 157 }
 158
 159 static int kszphy_config_intr(struct phy_device *phydev)
 160 {
 161         const struct kszphy_type *type = phydev->drv->driver_data;
 162         int temp;
 163         u16 mask;
 164
 165         if (type && type->interrupt_level_mask)
 166                 mask = type->interrupt_level_mask;
 167         else
 168                 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
 169
 170         /* set the interrupt pin active low */
 171         temp = phy_read(phydev, MII_KSZPHY_CTRL);
 172         if (temp < 0)
 173                 return temp;
 174         temp &= ~mask;
 175         phy_write(phydev, MII_KSZPHY_CTRL, temp);
 176
 177         /* enable / disable interrupts */
 178         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 179                 temp = KSZPHY_INTCS_ALL;
 180         else
 181                 temp = 0;
 182
 183         return phy_write(phydev, MII_KSZPHY_INTCS, temp);
 184 }
 185
 186 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
 187 {
 188         int ctrl;
 189
 190         ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
 191         if (ctrl < 0)
 192                 return ctrl;
 193
 194         if (val)
 195                 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
 196         else
 197                 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
 198
 199         return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
 200 }
 201
 202 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
 203 {
 204         int rc, temp, shift;
 205
 206         switch (reg) {
 207         case MII_KSZPHY_CTRL_1:
 208                 shift = 14;
 209                 break;
 210         case MII_KSZPHY_CTRL_2:
 211                 shift = 4;
 212                 break;
 213         default:
 214                 return -EINVAL;
 215         }
 216
 217         temp = phy_read(phydev, reg);
 218         if (temp < 0) {
 219                 rc = temp;
 220                 goto out;
 221         }
 222
 223         temp &= ~(3 << shift);
 224         temp |= val << shift;
 225         rc = phy_write(phydev, reg, temp);
 226 out:
 227         if (rc < 0)
 228                 phydev_err(phydev, "failed to set led mode\n");
 229
 230         return rc;
 231 }
 232
 233 /* Disable PHY address 0 as the broadcast address, so that it can be used as a
 234  * unique (non-broadcast) address on a shared bus.
 235  */
 236 static int kszphy_broadcast_disable(struct phy_device *phydev)
 237 {
 238         int ret;
 239
 240         ret = phy_read(phydev, MII_KSZPHY_OMSO);
 241         if (ret < 0)
 242                 goto out;
 243
 244         ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
 245 out:
 246         if (ret)
 247                 phydev_err(phydev, "failed to disable broadcast address\n");
 248
 249         return ret;
 250 }
 251
 252 static int kszphy_nand_tree_disable(struct phy_device *phydev)
 253 {
 254         int ret;
 255
 256         ret = phy_read(phydev, MII_KSZPHY_OMSO);
 257         if (ret < 0)
 258                 goto out;
 259
 260         if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
 261                 return 0;
 262
 263         ret = phy_write(phydev, MII_KSZPHY_OMSO,
 264                         ret & ~KSZPHY_OMSO_NAND_TREE_ON);
 265 out:
 266         if (ret)
 267                 phydev_err(phydev, "failed to disable NAND tree mode\n");
 268
 269         return ret;
 270 }
 271
 272 /* Some config bits need to be set again on resume, handle them here. */
 273 static int kszphy_config_reset(struct phy_device *phydev)
 274 {
 275         struct kszphy_priv *priv = phydev->priv;
 276         int ret;
 277
 278         if (priv->rmii_ref_clk_sel) {
 279                 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
 280                 if (ret) {
 281                         phydev_err(phydev,
 282                                    "failed to set rmii reference clock\n");
 283                         return ret;
 284                 }
 285         }
 286
 287         if (priv->led_mode >= 0)
 288                 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode);
 289
 290         return 0;
 291 }
 292
 293 static int kszphy_config_init(struct phy_device *phydev)
 294 {
 295         struct kszphy_priv *priv = phydev->priv;
 296         const struct kszphy_type *type;
 297
 298         if (!priv)
 299                 return 0;
 300
 301         type = priv->type;
 302
 303         if (type->has_broadcast_disable)
 304                 kszphy_broadcast_disable(phydev);
 305
 306         if (type->has_nand_tree_disable)
 307                 kszphy_nand_tree_disable(phydev);
 308
 309         return kszphy_config_reset(phydev);
 310 }
 311
 312 static int ksz8041_config_init(struct phy_device *phydev)
 313 {
 314         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
 315
 316         struct device_node *of_node = phydev->mdio.dev.of_node;
 317
 318         /* Limit supported and advertised modes in fiber mode */
 319         if (of_property_read_bool(of_node, "micrel,fiber-mode")) {
 320                 phydev->dev_flags |= MICREL_PHY_FXEN;
 321                 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask);
 322                 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask);
 323
 324                 linkmode_and(phydev->supported, phydev->supported, mask);
 325                 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
 326                                  phydev->supported);
 327                 linkmode_and(phydev->advertising, phydev->advertising, mask);
 328                 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
 329                                  phydev->advertising);
 330                 phydev->autoneg = AUTONEG_DISABLE;
 331         }
 332
 333         return kszphy_config_init(phydev);
 334 }
 335
 336 static int ksz8041_config_aneg(struct phy_device *phydev)
 337 {
 338         /* Skip auto-negotiation in fiber mode */
 339         if (phydev->dev_flags & MICREL_PHY_FXEN) {
 340                 phydev->speed = SPEED_100;
 341                 return 0;
 342         }
 343
 344         return genphy_config_aneg(phydev);
 345 }
 346
 347 static int ksz9021_load_values_from_of(struct phy_device *phydev,
 348                                        const struct device_node *of_node,
 349                                        u16 reg,
 350                                        const char *field1, const char *field2,
 351                                        const char *field3, const char *field4)
 352 {
 353         int val1 = -1;
 354         int val2 = -2;
 355         int val3 = -3;
 356         int val4 = -4;
 357         int newval;
 358         int matches = 0;
 359
 360         if (!of_property_read_u32(of_node, field1, &val1))
 361                 matches++;
 362
 363         if (!of_property_read_u32(of_node, field2, &val2))
 364                 matches++;
 365
 366         if (!of_property_read_u32(of_node, field3, &val3))
 367                 matches++;
 368
 369         if (!of_property_read_u32(of_node, field4, &val4))
 370                 matches++;
 371
 372         if (!matches)
 373                 return 0;
 374
 375         if (matches < 4)
 376                 newval = kszphy_extended_read(phydev, reg);
 377         else
 378                 newval = 0;
 379
 380         if (val1 != -1)
 381                 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
 382
 383         if (val2 != -2)
 384                 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
 385
 386         if (val3 != -3)
 387                 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
 388
 389         if (val4 != -4)
 390                 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
 391
 392         return kszphy_extended_write(phydev, reg, newval);
 393 }
 394
 395 static int ksz9021_config_init(struct phy_device *phydev)
 396 {
 397         const struct device *dev = &phydev->mdio.dev;
 398         const struct device_node *of_node = dev->of_node;
 399         const struct device *dev_walker;
 400
 401         /* The Micrel driver has a deprecated option to place phy OF
 402          * properties in the MAC node. Walk up the tree of devices to
 403          * find a device with an OF node.
 404          */
 405         dev_walker = &phydev->mdio.dev;
 406         do {
 407                 of_node = dev_walker->of_node;
 408                 dev_walker = dev_walker->parent;
 409
 410         } while (!of_node && dev_walker);
 411
 412         if (of_node) {
 413                 ksz9021_load_values_from_of(phydev, of_node,
 414                                     MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
 415                                     "txen-skew-ps", "txc-skew-ps",
 416                                     "rxdv-skew-ps", "rxc-skew-ps");
 417                 ksz9021_load_values_from_of(phydev, of_node,
 418                                     MII_KSZPHY_RX_DATA_PAD_SKEW,
 419                                     "rxd0-skew-ps", "rxd1-skew-ps",
 420                                     "rxd2-skew-ps", "rxd3-skew-ps");
 421                 ksz9021_load_values_from_of(phydev, of_node,
 422                                     MII_KSZPHY_TX_DATA_PAD_SKEW,
 423                                     "txd0-skew-ps", "txd1-skew-ps",
 424                                     "txd2-skew-ps", "txd3-skew-ps");
 425         }
 426         return 0;
 427 }
 428
 429 #define MII_KSZ9031RN_MMD_CTRL_REG      0x0d
 430 #define MII_KSZ9031RN_MMD_REGDATA_REG   0x0e
 431 #define OP_DATA                         1
 432 #define KSZ9031_PS_TO_REG               60
 433
 434 /* Extended registers */
 435 /* MMD Address 0x0 */
 436 #define MII_KSZ9031RN_FLP_BURST_TX_LO   3
 437 #define MII_KSZ9031RN_FLP_BURST_TX_HI   4
 438
 439 /* MMD Address 0x2 */
 440 #define MII_KSZ9031RN_CONTROL_PAD_SKEW  4
 441 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW  5
 442 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW  6
 443 #define MII_KSZ9031RN_CLK_PAD_SKEW      8
 444
 445 /* MMD Address 0x1C */
 446 #define MII_KSZ9031RN_EDPD              0x23
 447 #define MII_KSZ9031RN_EDPD_ENABLE       BIT(0)
 448
 449 static int ksz9031_extended_write(struct phy_device *phydev,
 450                                   u8 mode, u32 dev_addr, u32 regnum, u16 val)
 451 {
 452         phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
 453         phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
 454         phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
 455         return phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, val);
 456 }
 457
 458 static int ksz9031_extended_read(struct phy_device *phydev,
 459                                  u8 mode, u32 dev_addr, u32 regnum)
 460 {
 461         phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
 462         phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
 463         phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
 464         return phy_read(phydev, MII_KSZ9031RN_MMD_REGDATA_REG);
 465 }
 466
 467 static int ksz9031_of_load_skew_values(struct phy_device *phydev,
 468                                        const struct device_node *of_node,
 469                                        u16 reg, size_t field_sz,
 470                                        const char *field[], u8 numfields)
 471 {
 472         int val[4] = {-1, -2, -3, -4};
 473         int matches = 0;
 474         u16 mask;
 475         u16 maxval;
 476         u16 newval;
 477         int i;
 478
 479         for (i = 0; i < numfields; i++)
 480                 if (!of_property_read_u32(of_node, field[i], val + i))
 481                         matches++;
 482
 483         if (!matches)
 484                 return 0;
 485
 486         if (matches < numfields)
 487                 newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg);
 488         else
 489                 newval = 0;
 490
 491         maxval = (field_sz == 4) ? 0xf : 0x1f;
 492         for (i = 0; i < numfields; i++)
 493                 if (val[i] != -(i + 1)) {
 494                         mask = 0xffff;
 495                         mask ^= maxval << (field_sz * i);
 496                         newval = (newval & mask) |
 497                                 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
 498                                         << (field_sz * i));
 499                 }
 500
 501         return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
 502 }
 503
 504 /* Center KSZ9031RNX FLP timing at 16ms. */
 505 static int ksz9031_center_flp_timing(struct phy_device *phydev)
 506 {
 507         int result;
 508
 509         result = ksz9031_extended_write(phydev, OP_DATA, 0,
 510                                         MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006);
 511         if (result)
 512                 return result;
 513
 514         result = ksz9031_extended_write(phydev, OP_DATA, 0,
 515                                         MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80);
 516         if (result)
 517                 return result;
 518
 519         return genphy_restart_aneg(phydev);
 520 }
 521
 522 /* Enable energy-detect power-down mode */
 523 static int ksz9031_enable_edpd(struct phy_device *phydev)
 524 {
 525         int reg;
 526
 527         reg = ksz9031_extended_read(phydev, OP_DATA, 0x1C, MII_KSZ9031RN_EDPD);
 528         if (reg < 0)
 529                 return reg;
 530         return ksz9031_extended_write(phydev, OP_DATA, 0x1C, MII_KSZ9031RN_EDPD,
 531                                       reg | MII_KSZ9031RN_EDPD_ENABLE);
 532 }
 533
 534 static int ksz9031_config_init(struct phy_device *phydev)
 535 {
 536         const struct device *dev = &phydev->mdio.dev;
 537         const struct device_node *of_node = dev->of_node;
 538         static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
 539         static const char *rx_data_skews[4] = {
 540                 "rxd0-skew-ps", "rxd1-skew-ps",
 541                 "rxd2-skew-ps", "rxd3-skew-ps"
 542         };
 543         static const char *tx_data_skews[4] = {
 544                 "txd0-skew-ps", "txd1-skew-ps",
 545                 "txd2-skew-ps", "txd3-skew-ps"
 546         };
 547         static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
 548         const struct device *dev_walker;
 549         int result;
 550
 551         result = ksz9031_enable_edpd(phydev);
 552         if (result < 0)
 553                 return result;
 554
 555         /* The Micrel driver has a deprecated option to place phy OF
 556          * properties in the MAC node. Walk up the tree of devices to
 557          * find a device with an OF node.
 558          */
 559         dev_walker = &phydev->mdio.dev;
 560         do {
 561                 of_node = dev_walker->of_node;
 562                 dev_walker = dev_walker->parent;
 563         } while (!of_node && dev_walker);
 564
 565         if (of_node) {
 566                 ksz9031_of_load_skew_values(phydev, of_node,
 567                                 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
 568                                 clk_skews, 2);
 569
 570                 ksz9031_of_load_skew_values(phydev, of_node,
 571                                 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
 572                                 control_skews, 2);
 573
 574                 ksz9031_of_load_skew_values(phydev, of_node,
 575                                 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
 576                                 rx_data_skews, 4);
 577
 578                 ksz9031_of_load_skew_values(phydev, of_node,
 579                                 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
 580                                 tx_data_skews, 4);
 581
 582                 /* Silicon Errata Sheet (DS80000691D or DS80000692D):
 583                  * When the device links in the 1000BASE-T slave mode only,
 584                  * the optional 125MHz reference output clock (CLK125_NDO)
 585                  * has wide duty cycle variation.
 586                  *
 587                  * The optional CLK125_NDO clock does not meet the RGMII
 588                  * 45/55 percent (min/max) duty cycle requirement and therefore
 589                  * cannot be used directly by the MAC side for clocking
 590                  * applications that have setup/hold time requirements on
 591                  * rising and falling clock edges.
 592                  *
 593                  * Workaround:
 594                  * Force the phy to be the master to receive a stable clock
 595                  * which meets the duty cycle requirement.
 596                  */
 597                 if (of_property_read_bool(of_node, "micrel,force-master")) {
 598                         result = phy_read(phydev, MII_CTRL1000);
 599                         if (result < 0)
 600                                 goto err_force_master;
 601
 602                         /* enable master mode, config & prefer master */
 603                         result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER;
 604                         result = phy_write(phydev, MII_CTRL1000, result);
 605                         if (result < 0)
 606                                 goto err_force_master;
 607                 }
 608         }
 609
 610         return ksz9031_center_flp_timing(phydev);
 611
 612 err_force_master:
 613         phydev_err(phydev, "failed to force the phy to master mode\n");
 614         return result;
 615 }
 616
 617 #define KSZ9131_SKEW_5BIT_MAX   2400
 618 #define KSZ9131_SKEW_4BIT_MAX   800
 619 #define KSZ9131_OFFSET          700
 620 #define KSZ9131_STEP            100
 621
 622 static int ksz9131_of_load_skew_values(struct phy_device *phydev,
 623                                        struct device_node *of_node,
 624                                        u16 reg, size_t field_sz,
 625                                        char *field[], u8 numfields)
 626 {
 627         int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET),
 628                       -(3 + KSZ9131_OFFSET), -(4 + KSZ9131_OFFSET)};
 629         int skewval, skewmax = 0;
 630         int matches = 0;
 631         u16 maxval;
 632         u16 newval;
 633         u16 mask;
 634         int i;
 635
 636         /* psec properties in dts should mean x pico seconds */
 637         if (field_sz == 5)
 638                 skewmax = KSZ9131_SKEW_5BIT_MAX;
 639         else
 640                 skewmax = KSZ9131_SKEW_4BIT_MAX;
 641
 642         for (i = 0; i < numfields; i++)
 643                 if (!of_property_read_s32(of_node, field[i], &skewval)) {
 644                         if (skewval < -KSZ9131_OFFSET)
 645                                 skewval = -KSZ9131_OFFSET;
 646                         else if (skewval > skewmax)
 647                                 skewval = skewmax;
 648
 649                         val[i] = skewval + KSZ9131_OFFSET;
 650                         matches++;
 651                 }
 652
 653         if (!matches)
 654                 return 0;
 655
 656         if (matches < numfields)
 657                 newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg);
 658         else
 659                 newval = 0;
 660
 661         maxval = (field_sz == 4) ? 0xf : 0x1f;
 662         for (i = 0; i < numfields; i++)
 663                 if (val[i] != -(i + 1 + KSZ9131_OFFSET)) {
 664                         mask = 0xffff;
 665                         mask ^= maxval << (field_sz * i);
 666                         newval = (newval & mask) |
 667                                 (((val[i] / KSZ9131_STEP) & maxval)
 668                                         << (field_sz * i));
 669                 }
 670
 671         return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
 672 }
 673
 674 static int ksz9131_config_init(struct phy_device *phydev)
 675 {
 676         const struct device *dev = &phydev->mdio.dev;
 677         struct device_node *of_node = dev->of_node;
 678         char *clk_skews[2] = {"rxc-skew-psec", "txc-skew-psec"};
 679         char *rx_data_skews[4] = {
 680                 "rxd0-skew-psec", "rxd1-skew-psec",
 681                 "rxd2-skew-psec", "rxd3-skew-psec"
 682         };
 683         char *tx_data_skews[4] = {
 684                 "txd0-skew-psec", "txd1-skew-psec",
 685                 "txd2-skew-psec", "txd3-skew-psec"
 686         };
 687         char *control_skews[2] = {"txen-skew-psec", "rxdv-skew-psec"};
 688         const struct device *dev_walker;
 689         int ret;
 690
 691         dev_walker = &phydev->mdio.dev;
 692         do {
 693                 of_node = dev_walker->of_node;
 694                 dev_walker = dev_walker->parent;
 695         } while (!of_node && dev_walker);
 696
 697         if (!of_node)
 698                 return 0;
 699
 700         ret = ksz9131_of_load_skew_values(phydev, of_node,
 701                                           MII_KSZ9031RN_CLK_PAD_SKEW, 5,
 702                                           clk_skews, 2);
 703         if (ret < 0)
 704                 return ret;
 705
 706         ret = ksz9131_of_load_skew_values(phydev, of_node,
 707                                           MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
 708                                           control_skews, 2);
 709         if (ret < 0)
 710                 return ret;
 711
 712         ret = ksz9131_of_load_skew_values(phydev, of_node,
 713                                           MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
 714                                           rx_data_skews, 4);
 715         if (ret < 0)
 716                 return ret;
 717
 718         ret = ksz9131_of_load_skew_values(phydev, of_node,
 719                                           MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
 720                                           tx_data_skews, 4);
 721         if (ret < 0)
 722                 return ret;
 723
 724         return 0;
 725 }
 726
 727 #define KSZ8873MLL_GLOBAL_CONTROL_4     0x06
 728 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX      BIT(6)
 729 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED       BIT(4)
 730 static int ksz8873mll_read_status(struct phy_device *phydev)
 731 {
 732         int regval;
 733
 734         /* dummy read */
 735         regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
 736
 737         regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
 738
 739         if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
 740                 phydev->duplex = DUPLEX_HALF;
 741         else
 742                 phydev->duplex = DUPLEX_FULL;
 743
 744         if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
 745                 phydev->speed = SPEED_10;
 746         else
 747                 phydev->speed = SPEED_100;
 748
 749         phydev->link = 1;
 750         phydev->pause = phydev->asym_pause = 0;
 751
 752         return 0;
 753 }
 754
 755 static int ksz9031_read_status(struct phy_device *phydev)
 756 {
 757         int err;
 758         int regval;
 759
 760         err = genphy_read_status(phydev);
 761         if (err)
 762                 return err;
 763
 764         /* Make sure the PHY is not broken. Read idle error count,
 765          * and reset the PHY if it is maxed out.
 766          */
 767         regval = phy_read(phydev, MII_STAT1000);
 768         if ((regval & 0xFF) == 0xFF) {
 769                 phy_init_hw(phydev);
 770                 phydev->link = 0;
 771                 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev))
 772                         phydev->drv->config_intr(phydev);
 773                 return genphy_config_aneg(phydev);
 774         }
 775
 776         return 0;
 777 }
 778
 779 static int ksz8873mll_config_aneg(struct phy_device *phydev)
 780 {
 781         return 0;
 782 }
 783
 784 static int kszphy_get_sset_count(struct phy_device *phydev)
 785 {
 786         return ARRAY_SIZE(kszphy_hw_stats);
 787 }
 788
 789 static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
 790 {
 791         int i;
 792
 793         for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) {
 794                 strlcpy(data + i * ETH_GSTRING_LEN,
 795                         kszphy_hw_stats[i].string, ETH_GSTRING_LEN);
 796         }
 797 }
 798
 799 static u64 kszphy_get_stat(struct phy_device *phydev, int i)
 800 {
 801         struct kszphy_hw_stat stat = kszphy_hw_stats[i];
 802         struct kszphy_priv *priv = phydev->priv;
 803         int val;
 804         u64 ret;
 805
 806         val = phy_read(phydev, stat.reg);
 807         if (val < 0) {
 808                 ret = U64_MAX;
 809         } else {
 810                 val = val & ((1 << stat.bits) - 1);
 811                 priv->stats[i] += val;
 812                 ret = priv->stats[i];
 813         }
 814
 815         return ret;
 816 }
 817
 818 static void kszphy_get_stats(struct phy_device *phydev,
 819                              struct ethtool_stats *stats, u64 *data)
 820 {
 821         int i;
 822
 823         for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
 824                 data[i] = kszphy_get_stat(phydev, i);
 825 }
 826
 827 static int kszphy_suspend(struct phy_device *phydev)
 828 {
 829         /* Disable PHY Interrupts */
 830         if (phy_interrupt_is_valid(phydev)) {
 831                 phydev->interrupts = PHY_INTERRUPT_DISABLED;
 832                 if (phydev->drv->config_intr)
 833                         phydev->drv->config_intr(phydev);
 834         }
 835
 836         return genphy_suspend(phydev);
 837 }
 838
 839 static int kszphy_resume(struct phy_device *phydev)
 840 {
 841         int ret;
 842
 843         genphy_resume(phydev);
 844
 845         ret = kszphy_config_reset(phydev);
 846         if (ret)
 847                 return ret;
 848
 849         /* Enable PHY Interrupts */
 850         if (phy_interrupt_is_valid(phydev)) {
 851                 phydev->interrupts = PHY_INTERRUPT_ENABLED;
 852                 if (phydev->drv->config_intr)
 853                         phydev->drv->config_intr(phydev);
 854         }
 855
 856         return 0;
 857 }
 858
 859 static int kszphy_probe(struct phy_device *phydev)
 860 {
 861         const struct kszphy_type *type = phydev->drv->driver_data;
 862         const struct device_node *np = phydev->mdio.dev.of_node;
 863         struct kszphy_priv *priv;
 864         struct clk *clk;
 865         int ret;
 866
 867         priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
 868         if (!priv)
 869                 return -ENOMEM;
 870
 871         phydev->priv = priv;
 872
 873         priv->type = type;
 874
 875         if (type->led_mode_reg) {
 876                 ret = of_property_read_u32(np, "micrel,led-mode",
 877                                 &priv->led_mode);
 878                 if (ret)
 879                         priv->led_mode = -1;
 880
 881                 if (priv->led_mode > 3) {
 882                         phydev_err(phydev, "invalid led mode: 0x%02x\n",
 883                                    priv->led_mode);
 884                         priv->led_mode = -1;
 885                 }
 886         } else {
 887                 priv->led_mode = -1;
 888         }
 889
 890         clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref");
 891         /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
 892         if (!IS_ERR_OR_NULL(clk)) {
 893                 unsigned long rate = clk_get_rate(clk);
 894                 bool rmii_ref_clk_sel_25_mhz;
 895
 896                 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
 897                 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
 898                                 "micrel,rmii-reference-clock-select-25-mhz");
 899
 900                 if (rate > 24500000 && rate < 25500000) {
 901                         priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
 902                 } else if (rate > 49500000 && rate < 50500000) {
 903                         priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
 904                 } else {
 905                         phydev_err(phydev, "Clock rate out of range: %ld\n",
 906                                    rate);
 907                         return -EINVAL;
 908                 }
 909         }
 910
 911         /* Support legacy board-file configuration */
 912         if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
 913                 priv->rmii_ref_clk_sel = true;
 914                 priv->rmii_ref_clk_sel_val = true;
 915         }
 916
 917         return 0;
 918 }
 919
 920 static struct phy_driver ksphy_driver[] = {
 921 {
 922         .phy_id         = PHY_ID_KS8737,
 923         .phy_id_mask    = MICREL_PHY_ID_MASK,
 924         .name           = "Micrel KS8737",
 925         .features       = PHY_BASIC_FEATURES,
 926         .driver_data    = &ks8737_type,
 927         .config_init    = kszphy_config_init,
 928         .ack_interrupt  = kszphy_ack_interrupt,
 929         .config_intr    = kszphy_config_intr,
 930         .suspend        = genphy_suspend,
 931         .resume         = genphy_resume,
 932 }, {
 933         .phy_id         = PHY_ID_KSZ8021,
 934         .phy_id_mask    = 0x00ffffff,
 935         .name           = "Micrel KSZ8021 or KSZ8031",
 936         .features       = PHY_BASIC_FEATURES,
 937         .driver_data    = &ksz8021_type,
 938         .probe          = kszphy_probe,
 939         .config_init    = kszphy_config_init,
 940         .ack_interrupt  = kszphy_ack_interrupt,
 941         .config_intr    = kszphy_config_intr,
 942         .get_sset_count = kszphy_get_sset_count,
 943         .get_strings    = kszphy_get_strings,
 944         .get_stats      = kszphy_get_stats,
 945         .suspend        = genphy_suspend,
 946         .resume         = genphy_resume,
 947 }, {
 948         .phy_id         = PHY_ID_KSZ8031,
 949         .phy_id_mask    = 0x00ffffff,
 950         .name           = "Micrel KSZ8031",
 951         .features       = PHY_BASIC_FEATURES,
 952         .driver_data    = &ksz8021_type,
 953         .probe          = kszphy_probe,
 954         .config_init    = kszphy_config_init,
 955         .ack_interrupt  = kszphy_ack_interrupt,
 956         .config_intr    = kszphy_config_intr,
 957         .get_sset_count = kszphy_get_sset_count,
 958         .get_strings    = kszphy_get_strings,
 959         .get_stats      = kszphy_get_stats,
 960         .suspend        = genphy_suspend,
 961         .resume         = genphy_resume,
 962 }, {
 963         .phy_id         = PHY_ID_KSZ8041,
 964         .phy_id_mask    = MICREL_PHY_ID_MASK,
 965         .name           = "Micrel KSZ8041",
 966         .features       = PHY_BASIC_FEATURES,
 967         .driver_data    = &ksz8041_type,
 968         .probe          = kszphy_probe,
 969         .config_init    = ksz8041_config_init,
 970         .config_aneg    = ksz8041_config_aneg,
 971         .ack_interrupt  = kszphy_ack_interrupt,
 972         .config_intr    = kszphy_config_intr,
 973         .get_sset_count = kszphy_get_sset_count,
 974         .get_strings    = kszphy_get_strings,
 975         .get_stats      = kszphy_get_stats,
 976         .suspend        = genphy_suspend,
 977         .resume         = genphy_resume,
 978 }, {
 979         .phy_id         = PHY_ID_KSZ8041RNLI,
 980         .phy_id_mask    = MICREL_PHY_ID_MASK,
 981         .name           = "Micrel KSZ8041RNLI",
 982         .features       = PHY_BASIC_FEATURES,
 983         .driver_data    = &ksz8041_type,
 984         .probe          = kszphy_probe,
 985         .config_init    = kszphy_config_init,
 986         .ack_interrupt  = kszphy_ack_interrupt,
 987         .config_intr    = kszphy_config_intr,
 988         .get_sset_count = kszphy_get_sset_count,
 989         .get_strings    = kszphy_get_strings,
 990         .get_stats      = kszphy_get_stats,
 991         .suspend        = genphy_suspend,
 992         .resume         = genphy_resume,
 993 }, {
 994         .phy_id         = PHY_ID_KSZ8051,
 995         .phy_id_mask    = MICREL_PHY_ID_MASK,
 996         .name           = "Micrel KSZ8051",
 997         .features       = PHY_BASIC_FEATURES,
 998         .driver_data    = &ksz8051_type,
 999         .probe          = kszphy_probe,
1000         .config_init    = kszphy_config_init,
1001         .ack_interrupt  = kszphy_ack_interrupt,
1002         .config_intr    = kszphy_config_intr,
1003         .get_sset_count = kszphy_get_sset_count,
1004         .get_strings    = kszphy_get_strings,
1005         .get_stats      = kszphy_get_stats,
1006         .suspend        = genphy_suspend,
1007         .resume         = genphy_resume,
1008 }, {
1009         .phy_id         = PHY_ID_KSZ8001,
1010         .name           = "Micrel KSZ8001 or KS8721",
1011         .phy_id_mask    = 0x00fffffc,
1012         .features       = PHY_BASIC_FEATURES,
1013         .driver_data    = &ksz8041_type,
1014         .probe          = kszphy_probe,
1015         .config_init    = kszphy_config_init,
1016         .ack_interrupt  = kszphy_ack_interrupt,
1017         .config_intr    = kszphy_config_intr,
1018         .get_sset_count = kszphy_get_sset_count,
1019         .get_strings    = kszphy_get_strings,
1020         .get_stats      = kszphy_get_stats,
1021         .suspend        = genphy_suspend,
1022         .resume         = genphy_resume,
1023 }, {
1024         .phy_id         = PHY_ID_KSZ8081,
1025         .name           = "Micrel KSZ8081 or KSZ8091",
1026         .phy_id_mask    = MICREL_PHY_ID_MASK,
1027         .features       = PHY_BASIC_FEATURES,
1028         .driver_data    = &ksz8081_type,
1029         .probe          = kszphy_probe,
1030         .config_init    = kszphy_config_init,
1031         .ack_interrupt  = kszphy_ack_interrupt,
1032         .config_intr    = kszphy_config_intr,
1033         .get_sset_count = kszphy_get_sset_count,
1034         .get_strings    = kszphy_get_strings,
1035         .get_stats      = kszphy_get_stats,
1036         .suspend        = kszphy_suspend,
1037         .resume         = kszphy_resume,
1038 }, {
1039         .phy_id         = PHY_ID_KSZ8061,
1040         .name           = "Micrel KSZ8061",
1041         .phy_id_mask    = MICREL_PHY_ID_MASK,
1042         .features       = PHY_BASIC_FEATURES,
1043         .config_init    = kszphy_config_init,
1044         .ack_interrupt  = kszphy_ack_interrupt,
1045         .config_intr    = kszphy_config_intr,
1046         .suspend        = genphy_suspend,
1047         .resume         = genphy_resume,
1048 }, {
1049         .phy_id         = PHY_ID_KSZ9021,
1050         .phy_id_mask    = 0x000ffffe,
1051         .name           = "Micrel KSZ9021 Gigabit PHY",
1052         .features       = PHY_GBIT_FEATURES,
1053         .driver_data    = &ksz9021_type,
1054         .probe          = kszphy_probe,
1055         .config_init    = ksz9021_config_init,
1056         .ack_interrupt  = kszphy_ack_interrupt,
1057         .config_intr    = kszphy_config_intr,
1058         .get_sset_count = kszphy_get_sset_count,
1059         .get_strings    = kszphy_get_strings,
1060         .get_stats      = kszphy_get_stats,
1061         .suspend        = genphy_suspend,
1062         .resume         = genphy_resume,
1063         .read_mmd       = genphy_read_mmd_unsupported,
1064         .write_mmd      = genphy_write_mmd_unsupported,
1065 }, {
1066         .phy_id         = PHY_ID_KSZ9031,
1067         .phy_id_mask    = MICREL_PHY_ID_MASK,
1068         .name           = "Micrel KSZ9031 Gigabit PHY",
1069         .features       = PHY_GBIT_FEATURES,
1070         .driver_data    = &ksz9021_type,
1071         .probe          = kszphy_probe,
1072         .config_init    = ksz9031_config_init,
1073         .soft_reset     = genphy_soft_reset,
1074         .read_status    = ksz9031_read_status,
1075         .ack_interrupt  = kszphy_ack_interrupt,
1076         .config_intr    = kszphy_config_intr,
1077         .get_sset_count = kszphy_get_sset_count,
1078         .get_strings    = kszphy_get_strings,
1079         .get_stats      = kszphy_get_stats,
1080         .suspend        = genphy_suspend,
1081         .resume         = kszphy_resume,
1082 }, {
1083         .phy_id         = PHY_ID_KSZ9131,
1084         .phy_id_mask    = MICREL_PHY_ID_MASK,
1085         .name           = "Microchip KSZ9131 Gigabit PHY",
1086         .features       = PHY_GBIT_FEATURES,
1087         .driver_data    = &ksz9021_type,
1088         .probe          = kszphy_probe,
1089         .config_init    = ksz9131_config_init,
1090         .read_status    = ksz9031_read_status,
1091         .ack_interrupt  = kszphy_ack_interrupt,
1092         .config_intr    = kszphy_config_intr,
1093         .get_sset_count = kszphy_get_sset_count,
1094         .get_strings    = kszphy_get_strings,
1095         .get_stats      = kszphy_get_stats,
1096         .suspend        = genphy_suspend,
1097         .resume         = kszphy_resume,
1098 }, {
1099         .phy_id         = PHY_ID_KSZ8873MLL,
1100         .phy_id_mask    = MICREL_PHY_ID_MASK,
1101         .name           = "Micrel KSZ8873MLL Switch",
1102         .features       = PHY_BASIC_FEATURES,
1103         .config_init    = kszphy_config_init,
1104         .config_aneg    = ksz8873mll_config_aneg,
1105         .read_status    = ksz8873mll_read_status,
1106         .suspend        = genphy_suspend,
1107         .resume         = genphy_resume,
1108 }, {
1109         .phy_id         = PHY_ID_KSZ886X,
1110         .phy_id_mask    = MICREL_PHY_ID_MASK,
1111         .name           = "Micrel KSZ886X Switch",
1112         .features       = PHY_BASIC_FEATURES,
1113         .config_init    = kszphy_config_init,
1114         .suspend        = genphy_suspend,
1115         .resume         = genphy_resume,
1116 }, {
1117         .phy_id         = PHY_ID_KSZ8795,
1118         .phy_id_mask    = MICREL_PHY_ID_MASK,
1119         .name           = "Micrel KSZ8795",
1120         .features       = PHY_BASIC_FEATURES,
1121         .config_init    = kszphy_config_init,
1122         .config_aneg    = ksz8873mll_config_aneg,
1123         .read_status    = ksz8873mll_read_status,
1124         .suspend        = genphy_suspend,
1125         .resume         = genphy_resume,
1126 }, {
1127         .phy_id         = PHY_ID_KSZ9477,
1128         .phy_id_mask    = MICREL_PHY_ID_MASK,
1129         .name           = "Microchip KSZ9477",
1130         .features       = PHY_GBIT_FEATURES,
1131         .config_init    = kszphy_config_init,
1132         .suspend        = genphy_suspend,
1133         .resume         = genphy_resume,
1134 } };
1135
1136 module_phy_driver(ksphy_driver);
1137
1138 MODULE_DESCRIPTION("Micrel PHY driver");
1139 MODULE_AUTHOR("David J. Choi");
1140 MODULE_LICENSE("GPL");
1141
1142 static struct mdio_device_id __maybe_unused micrel_tbl[] = {
1143         { PHY_ID_KSZ9021, 0x000ffffe },
1144         { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK },
1145         { PHY_ID_KSZ9131, MICREL_PHY_ID_MASK },
1146         { PHY_ID_KSZ8001, 0x00fffffc },
1147         { PHY_ID_KS8737, MICREL_PHY_ID_MASK },
1148         { PHY_ID_KSZ8021, 0x00ffffff },
1149         { PHY_ID_KSZ8031, 0x00ffffff },
1150         { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK },
1151         { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK },
1152         { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK },
1153         { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },
1154         { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },
1155         { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
1156         { }
1157 };
1158
1159 MODULE_DEVICE_TABLE(mdio, micrel_tbl);