drivers/net/phy/marvell.c

   1 /*
   2  * drivers/net/phy/marvell.c
   3  *
   4  * Driver for Marvell PHYs
   5  *
   6  * Author: Andy Fleming
   7  *
   8  * Copyright (c) 2004 Freescale Semiconductor, Inc.
   9  *
  10  * Copyright (c) 2013 Michael Stapelberg <michael@stapelberg.de>
  11  *
  12  * This program is free software; you can redistribute  it and/or modify it
  13  * under  the terms of  the GNU General  Public License as published by the
  14  * Free Software Foundation;  either version 2 of the  License, or (at your
  15  * option) any later version.
  16  *
  17  */
  18 #include <linux/kernel.h>
  19 #include <linux/string.h>
  20 #include <linux/errno.h>
  21 #include <linux/unistd.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/init.h>
  24 #include <linux/delay.h>
  25 #include <linux/netdevice.h>
  26 #include <linux/etherdevice.h>
  27 #include <linux/skbuff.h>
  28 #include <linux/spinlock.h>
  29 #include <linux/mm.h>
  30 #include <linux/module.h>
  31 #include <linux/mii.h>
  32 #include <linux/ethtool.h>
  33 #include <linux/phy.h>
  34 #include <linux/marvell_phy.h>
  35 #include <linux/of.h>
  36
  37 #include <linux/io.h>
  38 #include <asm/irq.h>
  39 #include <linux/uaccess.h>
  40
  41 #define MII_MARVELL_PHY_PAGE            22
  42
  43 #define MII_M1011_IEVENT                0x13
  44 #define MII_M1011_IEVENT_CLEAR          0x0000
  45
  46 #define MII_M1011_IMASK                 0x12
  47 #define MII_M1011_IMASK_INIT            0x6400
  48 #define MII_M1011_IMASK_CLEAR           0x0000
  49
  50 #define MII_M1011_PHY_SCR               0x10
  51 #define MII_M1011_PHY_SCR_AUTO_CROSS    0x0060
  52
  53 #define MII_M1145_PHY_EXT_SR            0x1b
  54 #define MII_M1145_PHY_EXT_CR            0x14
  55 #define MII_M1145_RGMII_RX_DELAY        0x0080
  56 #define MII_M1145_RGMII_TX_DELAY        0x0002
  57
  58 #define MII_M1145_HWCFG_MODE_SGMII_NO_CLK       0x4
  59 #define MII_M1145_HWCFG_MODE_MASK               0xf
  60 #define MII_M1145_HWCFG_FIBER_COPPER_AUTO       0x8000
  61
  62 #define MII_M1111_PHY_LED_CONTROL       0x18
  63 #define MII_M1111_PHY_LED_DIRECT        0x4100
  64 #define MII_M1111_PHY_LED_COMBINE       0x411c
  65 #define MII_M1111_PHY_EXT_CR            0x14
  66 #define MII_M1111_RX_DELAY              0x80
  67 #define MII_M1111_TX_DELAY              0x2
  68 #define MII_M1111_PHY_EXT_SR            0x1b
  69
  70 #define MII_M1111_HWCFG_MODE_MASK               0xf
  71 #define MII_M1111_HWCFG_MODE_COPPER_RGMII       0xb
  72 #define MII_M1111_HWCFG_MODE_FIBER_RGMII        0x3
  73 #define MII_M1111_HWCFG_MODE_SGMII_NO_CLK       0x4
  74 #define MII_M1111_HWCFG_MODE_COPPER_RTBI        0x9
  75 #define MII_M1111_HWCFG_FIBER_COPPER_AUTO       0x8000
  76 #define MII_M1111_HWCFG_FIBER_COPPER_RES        0x2000
  77
  78 #define MII_M1111_COPPER                0
  79 #define MII_M1111_FIBER                 1
  80
  81 #define MII_88E1121_PHY_MSCR_PAGE       2
  82 #define MII_88E1121_PHY_MSCR_REG        21
  83 #define MII_88E1121_PHY_MSCR_RX_DELAY   BIT(5)
  84 #define MII_88E1121_PHY_MSCR_TX_DELAY   BIT(4)
  85 #define MII_88E1121_PHY_MSCR_DELAY_MASK (~(0x3 << 4))
  86
  87 #define MII_88E1318S_PHY_MSCR1_REG      16
  88 #define MII_88E1318S_PHY_MSCR1_PAD_ODD  BIT(6)
  89
  90 /* Copper Specific Interrupt Enable Register */
  91 #define MII_88E1318S_PHY_CSIER                              0x12
  92 /* WOL Event Interrupt Enable */
  93 #define MII_88E1318S_PHY_CSIER_WOL_EIE                      BIT(7)
  94
  95 /* LED Timer Control Register */
  96 #define MII_88E1318S_PHY_LED_PAGE                           0x03
  97 #define MII_88E1318S_PHY_LED_TCR                            0x12
  98 #define MII_88E1318S_PHY_LED_TCR_FORCE_INT                  BIT(15)
  99 #define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE                BIT(7)
 100 #define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW             BIT(11)
 101
 102 /* Magic Packet MAC address registers */
 103 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD2                 0x17
 104 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD1                 0x18
 105 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD0                 0x19
 106
 107 #define MII_88E1318S_PHY_WOL_PAGE                           0x11
 108 #define MII_88E1318S_PHY_WOL_CTRL                           0x10
 109 #define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS          BIT(12)
 110 #define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14)
 111
 112 #define MII_88E1121_PHY_LED_CTRL        16
 113 #define MII_88E1121_PHY_LED_PAGE        3
 114 #define MII_88E1121_PHY_LED_DEF         0x0030
 115
 116 #define MII_M1011_PHY_STATUS            0x11
 117 #define MII_M1011_PHY_STATUS_1000       0x8000
 118 #define MII_M1011_PHY_STATUS_100        0x4000
 119 #define MII_M1011_PHY_STATUS_SPD_MASK   0xc000
 120 #define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
 121 #define MII_M1011_PHY_STATUS_RESOLVED   0x0800
 122 #define MII_M1011_PHY_STATUS_LINK       0x0400
 123
 124 #define MII_M1116R_CONTROL_REG_MAC      21
 125
 126
 127 MODULE_DESCRIPTION("Marvell PHY driver");
 128 MODULE_AUTHOR("Andy Fleming");
 129 MODULE_LICENSE("GPL");
 130
 131 static int marvell_ack_interrupt(struct phy_device *phydev)
 132 {
 133         int err;
 134
 135         /* Clear the interrupts by reading the reg */
 136         err = phy_read(phydev, MII_M1011_IEVENT);
 137
 138         if (err < 0)
 139                 return err;
 140
 141         return 0;
 142 }
 143
 144 static int marvell_config_intr(struct phy_device *phydev)
 145 {
 146         int err;
 147
 148         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 149                 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
 150         else
 151                 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
 152
 153         return err;
 154 }
 155
 156 static int marvell_config_aneg(struct phy_device *phydev)
 157 {
 158         int err;
 159
 160         /* The Marvell PHY has an errata which requires
 161          * that certain registers get written in order
 162          * to restart autonegotiation */
 163         err = phy_write(phydev, MII_BMCR, BMCR_RESET);
 164
 165         if (err < 0)
 166                 return err;
 167
 168         err = phy_write(phydev, 0x1d, 0x1f);
 169         if (err < 0)
 170                 return err;
 171
 172         err = phy_write(phydev, 0x1e, 0x200c);
 173         if (err < 0)
 174                 return err;
 175
 176         err = phy_write(phydev, 0x1d, 0x5);
 177         if (err < 0)
 178                 return err;
 179
 180         err = phy_write(phydev, 0x1e, 0);
 181         if (err < 0)
 182                 return err;
 183
 184         err = phy_write(phydev, 0x1e, 0x100);
 185         if (err < 0)
 186                 return err;
 187
 188         err = phy_write(phydev, MII_M1011_PHY_SCR,
 189                         MII_M1011_PHY_SCR_AUTO_CROSS);
 190         if (err < 0)
 191                 return err;
 192
 193         err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
 194                         MII_M1111_PHY_LED_DIRECT);
 195         if (err < 0)
 196                 return err;
 197
 198         err = genphy_config_aneg(phydev);
 199         if (err < 0)
 200                 return err;
 201
 202         if (phydev->autoneg != AUTONEG_ENABLE) {
 203                 int bmcr;
 204
 205                 /*
 206                  * A write to speed/duplex bits (that is performed by
 207                  * genphy_config_aneg() call above) must be followed by
 208                  * a software reset. Otherwise, the write has no effect.
 209                  */
 210                 bmcr = phy_read(phydev, MII_BMCR);
 211                 if (bmcr < 0)
 212                         return bmcr;
 213
 214                 err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
 215                 if (err < 0)
 216                         return err;
 217         }
 218
 219         return 0;
 220 }
 221
 222 #ifdef CONFIG_OF_MDIO
 223 /*
 224  * Set and/or override some configuration registers based on the
 225  * marvell,reg-init property stored in the of_node for the phydev.
 226  *
 227  * marvell,reg-init = <reg-page reg mask value>,...;
 228  *
 229  * There may be one or more sets of <reg-page reg mask value>:
 230  *
 231  * reg-page: which register bank to use.
 232  * reg: the register.
 233  * mask: if non-zero, ANDed with existing register value.
 234  * value: ORed with the masked value and written to the regiser.
 235  *
 236  */
 237 static int marvell_of_reg_init(struct phy_device *phydev)
 238 {
 239         const __be32 *paddr;
 240         int len, i, saved_page, current_page, page_changed, ret;
 241
 242         if (!phydev->dev.of_node)
 243                 return 0;
 244
 245         paddr = of_get_property(phydev->dev.of_node, "marvell,reg-init", &len);
 246         if (!paddr || len < (4 * sizeof(*paddr)))
 247                 return 0;
 248
 249         saved_page = phy_read(phydev, MII_MARVELL_PHY_PAGE);
 250         if (saved_page < 0)
 251                 return saved_page;
 252         page_changed = 0;
 253         current_page = saved_page;
 254
 255         ret = 0;
 256         len /= sizeof(*paddr);
 257         for (i = 0; i < len - 3; i += 4) {
 258                 u16 reg_page = be32_to_cpup(paddr + i);
 259                 u16 reg = be32_to_cpup(paddr + i + 1);
 260                 u16 mask = be32_to_cpup(paddr + i + 2);
 261                 u16 val_bits = be32_to_cpup(paddr + i + 3);
 262                 int val;
 263
 264                 if (reg_page != current_page) {
 265                         current_page = reg_page;
 266                         page_changed = 1;
 267                         ret = phy_write(phydev, MII_MARVELL_PHY_PAGE, reg_page);
 268                         if (ret < 0)
 269                                 goto err;
 270                 }
 271
 272                 val = 0;
 273                 if (mask) {
 274                         val = phy_read(phydev, reg);
 275                         if (val < 0) {
 276                                 ret = val;
 277                                 goto err;
 278                         }
 279                         val &= mask;
 280                 }
 281                 val |= val_bits;
 282
 283                 ret = phy_write(phydev, reg, val);
 284                 if (ret < 0)
 285                         goto err;
 286
 287         }
 288 err:
 289         if (page_changed) {
 290                 i = phy_write(phydev, MII_MARVELL_PHY_PAGE, saved_page);
 291                 if (ret == 0)
 292                         ret = i;
 293         }
 294         return ret;
 295 }
 296 #else
 297 static int marvell_of_reg_init(struct phy_device *phydev)
 298 {
 299         return 0;
 300 }
 301 #endif /* CONFIG_OF_MDIO */
 302
 303 static int m88e1121_config_aneg(struct phy_device *phydev)
 304 {
 305         int err, oldpage, mscr;
 306
 307         oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
 308
 309         err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
 310                         MII_88E1121_PHY_MSCR_PAGE);
 311         if (err < 0)
 312                 return err;
 313
 314         if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
 315             (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
 316             (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
 317             (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
 318
 319                 mscr = phy_read(phydev, MII_88E1121_PHY_MSCR_REG) &
 320                         MII_88E1121_PHY_MSCR_DELAY_MASK;
 321
 322                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 323                         mscr |= (MII_88E1121_PHY_MSCR_RX_DELAY |
 324                                  MII_88E1121_PHY_MSCR_TX_DELAY);
 325                 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 326                         mscr |= MII_88E1121_PHY_MSCR_RX_DELAY;
 327                 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 328                         mscr |= MII_88E1121_PHY_MSCR_TX_DELAY;
 329
 330                 err = phy_write(phydev, MII_88E1121_PHY_MSCR_REG, mscr);
 331                 if (err < 0)
 332                         return err;
 333         }
 334
 335         phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
 336
 337         err = phy_write(phydev, MII_BMCR, BMCR_RESET);
 338         if (err < 0)
 339                 return err;
 340
 341         err = phy_write(phydev, MII_M1011_PHY_SCR,
 342                         MII_M1011_PHY_SCR_AUTO_CROSS);
 343         if (err < 0)
 344                 return err;
 345
 346         oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
 347
 348         phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_88E1121_PHY_LED_PAGE);
 349         phy_write(phydev, MII_88E1121_PHY_LED_CTRL, MII_88E1121_PHY_LED_DEF);
 350         phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
 351
 352         err = genphy_config_aneg(phydev);
 353
 354         return err;
 355 }
 356
 357 static int m88e1318_config_aneg(struct phy_device *phydev)
 358 {
 359         int err, oldpage, mscr;
 360
 361         oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
 362
 363         err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
 364                         MII_88E1121_PHY_MSCR_PAGE);
 365         if (err < 0)
 366                 return err;
 367
 368         mscr = phy_read(phydev, MII_88E1318S_PHY_MSCR1_REG);
 369         mscr |= MII_88E1318S_PHY_MSCR1_PAD_ODD;
 370
 371         err = phy_write(phydev, MII_88E1318S_PHY_MSCR1_REG, mscr);
 372         if (err < 0)
 373                 return err;
 374
 375         err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
 376         if (err < 0)
 377                 return err;
 378
 379         return m88e1121_config_aneg(phydev);
 380 }
 381
 382 static int m88e1510_config_aneg(struct phy_device *phydev)
 383 {
 384         int err;
 385
 386         err = m88e1318_config_aneg(phydev);
 387         if (err < 0)
 388                 return err;
 389
 390         return marvell_of_reg_init(phydev);
 391 }
 392
 393 static int m88e1116r_config_init(struct phy_device *phydev)
 394 {
 395         int temp;
 396         int err;
 397
 398         temp = phy_read(phydev, MII_BMCR);
 399         temp |= BMCR_RESET;
 400         err = phy_write(phydev, MII_BMCR, temp);
 401         if (err < 0)
 402                 return err;
 403
 404         mdelay(500);
 405
 406         err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
 407         if (err < 0)
 408                 return err;
 409
 410         temp = phy_read(phydev, MII_M1011_PHY_SCR);
 411         temp |= (7 << 12);      /* max number of gigabit attempts */
 412         temp |= (1 << 11);      /* enable downshift */
 413         temp |= MII_M1011_PHY_SCR_AUTO_CROSS;
 414         err = phy_write(phydev, MII_M1011_PHY_SCR, temp);
 415         if (err < 0)
 416                 return err;
 417
 418         err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 2);
 419         if (err < 0)
 420                 return err;
 421         temp = phy_read(phydev, MII_M1116R_CONTROL_REG_MAC);
 422         temp |= (1 << 5);
 423         temp |= (1 << 4);
 424         err = phy_write(phydev, MII_M1116R_CONTROL_REG_MAC, temp);
 425         if (err < 0)
 426                 return err;
 427         err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
 428         if (err < 0)
 429                 return err;
 430
 431         temp = phy_read(phydev, MII_BMCR);
 432         temp |= BMCR_RESET;
 433         err = phy_write(phydev, MII_BMCR, temp);
 434         if (err < 0)
 435                 return err;
 436
 437         mdelay(500);
 438
 439         return 0;
 440 }
 441
 442 static int m88e1111_config_init(struct phy_device *phydev)
 443 {
 444         int err;
 445         int temp;
 446
 447         if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
 448             (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
 449             (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
 450             (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
 451
 452                 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
 453                 if (temp < 0)
 454                         return temp;
 455
 456                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
 457                         temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
 458                 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
 459                         temp &= ~MII_M1111_TX_DELAY;
 460                         temp |= MII_M1111_RX_DELAY;
 461                 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
 462                         temp &= ~MII_M1111_RX_DELAY;
 463                         temp |= MII_M1111_TX_DELAY;
 464                 }
 465
 466                 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
 467                 if (err < 0)
 468                         return err;
 469
 470                 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
 471                 if (temp < 0)
 472                         return temp;
 473
 474                 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
 475
 476                 if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
 477                         temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
 478                 else
 479                         temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
 480
 481                 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
 482                 if (err < 0)
 483                         return err;
 484         }
 485
 486         if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
 487                 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
 488                 if (temp < 0)
 489                         return temp;
 490
 491                 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
 492                 temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK;
 493                 temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
 494
 495                 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
 496                 if (err < 0)
 497                         return err;
 498         }
 499
 500         if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
 501                 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
 502                 if (temp < 0)
 503                         return temp;
 504                 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
 505                 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
 506                 if (err < 0)
 507                         return err;
 508
 509                 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
 510                 if (temp < 0)
 511                         return temp;
 512                 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
 513                 temp |= 0x7 | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
 514                 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
 515                 if (err < 0)
 516                         return err;
 517
 518                 /* soft reset */
 519                 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
 520                 if (err < 0)
 521                         return err;
 522                 do
 523                         temp = phy_read(phydev, MII_BMCR);
 524                 while (temp & BMCR_RESET);
 525
 526                 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
 527                 if (temp < 0)
 528                         return temp;
 529                 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
 530                 temp |= MII_M1111_HWCFG_MODE_COPPER_RTBI | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
 531                 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
 532                 if (err < 0)
 533                         return err;
 534         }
 535
 536         err = marvell_of_reg_init(phydev);
 537         if (err < 0)
 538                 return err;
 539
 540         return phy_write(phydev, MII_BMCR, BMCR_RESET);
 541 }
 542
 543 static int m88e1118_config_aneg(struct phy_device *phydev)
 544 {
 545         int err;
 546
 547         err = phy_write(phydev, MII_BMCR, BMCR_RESET);
 548         if (err < 0)
 549                 return err;
 550
 551         err = phy_write(phydev, MII_M1011_PHY_SCR,
 552                         MII_M1011_PHY_SCR_AUTO_CROSS);
 553         if (err < 0)
 554                 return err;
 555
 556         err = genphy_config_aneg(phydev);
 557         return 0;
 558 }
 559
 560 static int m88e1118_config_init(struct phy_device *phydev)
 561 {
 562         int err;
 563
 564         /* Change address */
 565         err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
 566         if (err < 0)
 567                 return err;
 568
 569         /* Enable 1000 Mbit */
 570         err = phy_write(phydev, 0x15, 0x1070);
 571         if (err < 0)
 572                 return err;
 573
 574         /* Change address */
 575         err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0003);
 576         if (err < 0)
 577                 return err;
 578
 579         /* Adjust LED Control */
 580         if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
 581                 err = phy_write(phydev, 0x10, 0x1100);
 582         else
 583                 err = phy_write(phydev, 0x10, 0x021e);
 584         if (err < 0)
 585                 return err;
 586
 587         err = marvell_of_reg_init(phydev);
 588         if (err < 0)
 589                 return err;
 590
 591         /* Reset address */
 592         err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
 593         if (err < 0)
 594                 return err;
 595
 596         return phy_write(phydev, MII_BMCR, BMCR_RESET);
 597 }
 598
 599 static int m88e1149_config_init(struct phy_device *phydev)
 600 {
 601         int err;
 602
 603         /* Change address */
 604         err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
 605         if (err < 0)
 606                 return err;
 607
 608         /* Enable 1000 Mbit */
 609         err = phy_write(phydev, 0x15, 0x1048);
 610         if (err < 0)
 611                 return err;
 612
 613         err = marvell_of_reg_init(phydev);
 614         if (err < 0)
 615                 return err;
 616
 617         /* Reset address */
 618         err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
 619         if (err < 0)
 620                 return err;
 621
 622         return phy_write(phydev, MII_BMCR, BMCR_RESET);
 623 }
 624
 625 static int m88e1145_config_init(struct phy_device *phydev)
 626 {
 627         int err;
 628
 629         /* Take care of errata E0 & E1 */
 630         err = phy_write(phydev, 0x1d, 0x001b);
 631         if (err < 0)
 632                 return err;
 633
 634         err = phy_write(phydev, 0x1e, 0x418f);
 635         if (err < 0)
 636                 return err;
 637
 638         err = phy_write(phydev, 0x1d, 0x0016);
 639         if (err < 0)
 640                 return err;
 641
 642         err = phy_write(phydev, 0x1e, 0xa2da);
 643         if (err < 0)
 644                 return err;
 645
 646         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
 647                 int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR);
 648                 if (temp < 0)
 649                         return temp;
 650
 651                 temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY);
 652
 653                 err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp);
 654                 if (err < 0)
 655                         return err;
 656
 657                 if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) {
 658                         err = phy_write(phydev, 0x1d, 0x0012);
 659                         if (err < 0)
 660                                 return err;
 661
 662                         temp = phy_read(phydev, 0x1e);
 663                         if (temp < 0)
 664                                 return temp;
 665
 666                         temp &= 0xf03f;
 667                         temp |= 2 << 9; /* 36 ohm */
 668                         temp |= 2 << 6; /* 39 ohm */
 669
 670                         err = phy_write(phydev, 0x1e, temp);
 671                         if (err < 0)
 672                                 return err;
 673
 674                         err = phy_write(phydev, 0x1d, 0x3);
 675                         if (err < 0)
 676                                 return err;
 677
 678                         err = phy_write(phydev, 0x1e, 0x8000);
 679                         if (err < 0)
 680                                 return err;
 681                 }
 682         }
 683
 684         if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
 685                 int temp = phy_read(phydev, MII_M1145_PHY_EXT_SR);
 686                 if (temp < 0)
 687                         return temp;
 688
 689                 temp &= ~MII_M1145_HWCFG_MODE_MASK;
 690                 temp |= MII_M1145_HWCFG_MODE_SGMII_NO_CLK;
 691                 temp |= MII_M1145_HWCFG_FIBER_COPPER_AUTO;
 692
 693                 err = phy_write(phydev, MII_M1145_PHY_EXT_SR, temp);
 694                 if (err < 0)
 695                         return err;
 696         }
 697
 698         err = marvell_of_reg_init(phydev);
 699         if (err < 0)
 700                 return err;
 701
 702         return 0;
 703 }
 704
 705 /* marvell_read_status
 706  *
 707  * Generic status code does not detect Fiber correctly!
 708  * Description:
 709  *   Check the link, then figure out the current state
 710  *   by comparing what we advertise with what the link partner
 711  *   advertises.  Start by checking the gigabit possibilities,
 712  *   then move on to 10/100.
 713  */
 714 static int marvell_read_status(struct phy_device *phydev)
 715 {
 716         int adv;
 717         int err;
 718         int lpa;
 719         int status = 0;
 720
 721         /* Update the link, but return if there
 722          * was an error */
 723         err = genphy_update_link(phydev);
 724         if (err)
 725                 return err;
 726
 727         if (AUTONEG_ENABLE == phydev->autoneg) {
 728                 status = phy_read(phydev, MII_M1011_PHY_STATUS);
 729                 if (status < 0)
 730                         return status;
 731
 732                 lpa = phy_read(phydev, MII_LPA);
 733                 if (lpa < 0)
 734                         return lpa;
 735
 736                 adv = phy_read(phydev, MII_ADVERTISE);
 737                 if (adv < 0)
 738                         return adv;
 739
 740                 lpa &= adv;
 741
 742                 if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
 743                         phydev->duplex = DUPLEX_FULL;
 744                 else
 745                         phydev->duplex = DUPLEX_HALF;
 746
 747                 status = status & MII_M1011_PHY_STATUS_SPD_MASK;
 748                 phydev->pause = phydev->asym_pause = 0;
 749
 750                 switch (status) {
 751                 case MII_M1011_PHY_STATUS_1000:
 752                         phydev->speed = SPEED_1000;
 753                         break;
 754
 755                 case MII_M1011_PHY_STATUS_100:
 756                         phydev->speed = SPEED_100;
 757                         break;
 758
 759                 default:
 760                         phydev->speed = SPEED_10;
 761                         break;
 762                 }
 763
 764                 if (phydev->duplex == DUPLEX_FULL) {
 765                         phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
 766                         phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
 767                 }
 768         } else {
 769                 int bmcr = phy_read(phydev, MII_BMCR);
 770
 771                 if (bmcr < 0)
 772                         return bmcr;
 773
 774                 if (bmcr & BMCR_FULLDPLX)
 775                         phydev->duplex = DUPLEX_FULL;
 776                 else
 777                         phydev->duplex = DUPLEX_HALF;
 778
 779                 if (bmcr & BMCR_SPEED1000)
 780                         phydev->speed = SPEED_1000;
 781                 else if (bmcr & BMCR_SPEED100)
 782                         phydev->speed = SPEED_100;
 783                 else
 784                         phydev->speed = SPEED_10;
 785
 786                 phydev->pause = phydev->asym_pause = 0;
 787         }
 788
 789         return 0;
 790 }
 791
 792 static int m88e1121_did_interrupt(struct phy_device *phydev)
 793 {
 794         int imask;
 795
 796         imask = phy_read(phydev, MII_M1011_IEVENT);
 797
 798         if (imask & MII_M1011_IMASK_INIT)
 799                 return 1;
 800
 801         return 0;
 802 }
 803
 804 static void m88e1318_get_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
 805 {
 806         wol->supported = WAKE_MAGIC;
 807         wol->wolopts = 0;
 808
 809         if (phy_write(phydev, MII_MARVELL_PHY_PAGE,
 810                       MII_88E1318S_PHY_WOL_PAGE) < 0)
 811                 return;
 812
 813         if (phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL) &
 814             MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE)
 815                 wol->wolopts |= WAKE_MAGIC;
 816
 817         if (phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00) < 0)
 818                 return;
 819 }
 820
 821 static int m88e1318_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
 822 {
 823         int err, oldpage, temp;
 824
 825         oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
 826
 827         if (wol->wolopts & WAKE_MAGIC) {
 828                 /* Explicitly switch to page 0x00, just to be sure */
 829                 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00);
 830                 if (err < 0)
 831                         return err;
 832
 833                 /* Enable the WOL interrupt */
 834                 temp = phy_read(phydev, MII_88E1318S_PHY_CSIER);
 835                 temp |= MII_88E1318S_PHY_CSIER_WOL_EIE;
 836                 err = phy_write(phydev, MII_88E1318S_PHY_CSIER, temp);
 837                 if (err < 0)
 838                         return err;
 839
 840                 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
 841                                 MII_88E1318S_PHY_LED_PAGE);
 842                 if (err < 0)
 843                         return err;
 844
 845                 /* Setup LED[2] as interrupt pin (active low) */
 846                 temp = phy_read(phydev, MII_88E1318S_PHY_LED_TCR);
 847                 temp &= ~MII_88E1318S_PHY_LED_TCR_FORCE_INT;
 848                 temp |= MII_88E1318S_PHY_LED_TCR_INTn_ENABLE;
 849                 temp |= MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW;
 850                 err = phy_write(phydev, MII_88E1318S_PHY_LED_TCR, temp);
 851                 if (err < 0)
 852                         return err;
 853
 854                 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
 855                                 MII_88E1318S_PHY_WOL_PAGE);
 856                 if (err < 0)
 857                         return err;
 858
 859                 /* Store the device address for the magic packet */
 860                 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD2,
 861                                 ((phydev->attached_dev->dev_addr[5] << 8) |
 862                                  phydev->attached_dev->dev_addr[4]));
 863                 if (err < 0)
 864                         return err;
 865                 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD1,
 866                                 ((phydev->attached_dev->dev_addr[3] << 8) |
 867                                  phydev->attached_dev->dev_addr[2]));
 868                 if (err < 0)
 869                         return err;
 870                 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD0,
 871                                 ((phydev->attached_dev->dev_addr[1] << 8) |
 872                                  phydev->attached_dev->dev_addr[0]));
 873                 if (err < 0)
 874                         return err;
 875
 876                 /* Clear WOL status and enable magic packet matching */
 877                 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
 878                 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
 879                 temp |= MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
 880                 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
 881                 if (err < 0)
 882                         return err;
 883         } else {
 884                 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
 885                                 MII_88E1318S_PHY_WOL_PAGE);
 886                 if (err < 0)
 887                         return err;
 888
 889                 /* Clear WOL status and disable magic packet matching */
 890                 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
 891                 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
 892                 temp &= ~MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
 893                 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
 894                 if (err < 0)
 895                         return err;
 896         }
 897
 898         err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
 899         if (err < 0)
 900                 return err;
 901
 902         return 0;
 903 }
 904
 905 static struct phy_driver marvell_drivers[] = {
 906         {
 907                 .phy_id = MARVELL_PHY_ID_88E1101,
 908                 .phy_id_mask = MARVELL_PHY_ID_MASK,
 909                 .name = "Marvell 88E1101",
 910                 .features = PHY_GBIT_FEATURES,
 911                 .flags = PHY_HAS_INTERRUPT,
 912                 .config_aneg = &marvell_config_aneg,
 913                 .read_status = &genphy_read_status,
 914                 .ack_interrupt = &marvell_ack_interrupt,
 915                 .config_intr = &marvell_config_intr,
 916                 .resume = &genphy_resume,
 917                 .suspend = &genphy_suspend,
 918                 .driver = { .owner = THIS_MODULE },
 919         },
 920         {
 921                 .phy_id = MARVELL_PHY_ID_88E1112,
 922                 .phy_id_mask = MARVELL_PHY_ID_MASK,
 923                 .name = "Marvell 88E1112",
 924                 .features = PHY_GBIT_FEATURES,
 925                 .flags = PHY_HAS_INTERRUPT,
 926                 .config_init = &m88e1111_config_init,
 927                 .config_aneg = &marvell_config_aneg,
 928                 .read_status = &genphy_read_status,
 929                 .ack_interrupt = &marvell_ack_interrupt,
 930                 .config_intr = &marvell_config_intr,
 931                 .resume = &genphy_resume,
 932                 .suspend = &genphy_suspend,
 933                 .driver = { .owner = THIS_MODULE },
 934         },
 935         {
 936                 .phy_id = MARVELL_PHY_ID_88E1111,
 937                 .phy_id_mask = MARVELL_PHY_ID_MASK,
 938                 .name = "Marvell 88E1111",
 939                 .features = PHY_GBIT_FEATURES,
 940                 .flags = PHY_HAS_INTERRUPT,
 941                 .config_init = &m88e1111_config_init,
 942                 .config_aneg = &marvell_config_aneg,
 943                 .read_status = &marvell_read_status,
 944                 .ack_interrupt = &marvell_ack_interrupt,
 945                 .config_intr = &marvell_config_intr,
 946                 .resume = &genphy_resume,
 947                 .suspend = &genphy_suspend,
 948                 .driver = { .owner = THIS_MODULE },
 949         },
 950         {
 951                 .phy_id = MARVELL_PHY_ID_88E1118,
 952                 .phy_id_mask = MARVELL_PHY_ID_MASK,
 953                 .name = "Marvell 88E1118",
 954                 .features = PHY_GBIT_FEATURES,
 955                 .flags = PHY_HAS_INTERRUPT,
 956                 .config_init = &m88e1118_config_init,
 957                 .config_aneg = &m88e1118_config_aneg,
 958                 .read_status = &genphy_read_status,
 959                 .ack_interrupt = &marvell_ack_interrupt,
 960                 .config_intr = &marvell_config_intr,
 961                 .resume = &genphy_resume,
 962                 .suspend = &genphy_suspend,
 963                 .driver = {.owner = THIS_MODULE,},
 964         },
 965         {
 966                 .phy_id = MARVELL_PHY_ID_88E1121R,
 967                 .phy_id_mask = MARVELL_PHY_ID_MASK,
 968                 .name = "Marvell 88E1121R",
 969                 .features = PHY_GBIT_FEATURES,
 970                 .flags = PHY_HAS_INTERRUPT,
 971                 .config_aneg = &m88e1121_config_aneg,
 972                 .read_status = &marvell_read_status,
 973                 .ack_interrupt = &marvell_ack_interrupt,
 974                 .config_intr = &marvell_config_intr,
 975                 .did_interrupt = &m88e1121_did_interrupt,
 976                 .resume = &genphy_resume,
 977                 .suspend = &genphy_suspend,
 978                 .driver = { .owner = THIS_MODULE },
 979         },
 980         {
 981                 .phy_id = MARVELL_PHY_ID_88E1318S,
 982                 .phy_id_mask = MARVELL_PHY_ID_MASK,
 983                 .name = "Marvell 88E1318S",
 984                 .features = PHY_GBIT_FEATURES,
 985                 .flags = PHY_HAS_INTERRUPT,
 986                 .config_aneg = &m88e1318_config_aneg,
 987                 .read_status = &marvell_read_status,
 988                 .ack_interrupt = &marvell_ack_interrupt,
 989                 .config_intr = &marvell_config_intr,
 990                 .did_interrupt = &m88e1121_did_interrupt,
 991                 .get_wol = &m88e1318_get_wol,
 992                 .set_wol = &m88e1318_set_wol,
 993                 .resume = &genphy_resume,
 994                 .suspend = &genphy_suspend,
 995                 .driver = { .owner = THIS_MODULE },
 996         },
 997         {
 998                 .phy_id = MARVELL_PHY_ID_88E1145,
 999                 .phy_id_mask = MARVELL_PHY_ID_MASK,
1000                 .name = "Marvell 88E1145",
1001                 .features = PHY_GBIT_FEATURES,
1002                 .flags = PHY_HAS_INTERRUPT,
1003                 .config_init = &m88e1145_config_init,
1004                 .config_aneg = &marvell_config_aneg,
1005                 .read_status = &genphy_read_status,
1006                 .ack_interrupt = &marvell_ack_interrupt,
1007                 .config_intr = &marvell_config_intr,
1008                 .resume = &genphy_resume,
1009                 .suspend = &genphy_suspend,
1010                 .driver = { .owner = THIS_MODULE },
1011         },
1012         {
1013                 .phy_id = MARVELL_PHY_ID_88E1149R,
1014                 .phy_id_mask = MARVELL_PHY_ID_MASK,
1015                 .name = "Marvell 88E1149R",
1016                 .features = PHY_GBIT_FEATURES,
1017                 .flags = PHY_HAS_INTERRUPT,
1018                 .config_init = &m88e1149_config_init,
1019                 .config_aneg = &m88e1118_config_aneg,
1020                 .read_status = &genphy_read_status,
1021                 .ack_interrupt = &marvell_ack_interrupt,
1022                 .config_intr = &marvell_config_intr,
1023                 .resume = &genphy_resume,
1024                 .suspend = &genphy_suspend,
1025                 .driver = { .owner = THIS_MODULE },
1026         },
1027         {
1028                 .phy_id = MARVELL_PHY_ID_88E1240,
1029                 .phy_id_mask = MARVELL_PHY_ID_MASK,
1030                 .name = "Marvell 88E1240",
1031                 .features = PHY_GBIT_FEATURES,
1032                 .flags = PHY_HAS_INTERRUPT,
1033                 .config_init = &m88e1111_config_init,
1034                 .config_aneg = &marvell_config_aneg,
1035                 .read_status = &genphy_read_status,
1036                 .ack_interrupt = &marvell_ack_interrupt,
1037                 .config_intr = &marvell_config_intr,
1038                 .resume = &genphy_resume,
1039                 .suspend = &genphy_suspend,
1040                 .driver = { .owner = THIS_MODULE },
1041         },
1042         {
1043                 .phy_id = MARVELL_PHY_ID_88E1116R,
1044                 .phy_id_mask = MARVELL_PHY_ID_MASK,
1045                 .name = "Marvell 88E1116R",
1046                 .features = PHY_GBIT_FEATURES,
1047                 .flags = PHY_HAS_INTERRUPT,
1048                 .config_init = &m88e1116r_config_init,
1049                 .config_aneg = &genphy_config_aneg,
1050                 .read_status = &genphy_read_status,
1051                 .ack_interrupt = &marvell_ack_interrupt,
1052                 .config_intr = &marvell_config_intr,
1053                 .resume = &genphy_resume,
1054                 .suspend = &genphy_suspend,
1055                 .driver = { .owner = THIS_MODULE },
1056         },
1057         {
1058                 .phy_id = MARVELL_PHY_ID_88E1510,
1059                 .phy_id_mask = MARVELL_PHY_ID_MASK,
1060                 .name = "Marvell 88E1510",
1061                 .features = PHY_GBIT_FEATURES,
1062                 .flags = PHY_HAS_INTERRUPT,
1063                 .config_aneg = &m88e1510_config_aneg,
1064                 .read_status = &marvell_read_status,
1065                 .ack_interrupt = &marvell_ack_interrupt,
1066                 .config_intr = &marvell_config_intr,
1067                 .did_interrupt = &m88e1121_did_interrupt,
1068                 .resume = &genphy_resume,
1069                 .suspend = &genphy_suspend,
1070                 .driver = { .owner = THIS_MODULE },
1071         },
1072 };
1073
1074 static int __init marvell_init(void)
1075 {
1076         return phy_drivers_register(marvell_drivers,
1077                  ARRAY_SIZE(marvell_drivers));
1078 }
1079
1080 static void __exit marvell_exit(void)
1081 {
1082         phy_drivers_unregister(marvell_drivers,
1083                  ARRAY_SIZE(marvell_drivers));
1084 }
1085
1086 module_init(marvell_init);
1087 module_exit(marvell_exit);
1088
1089 static struct mdio_device_id __maybe_unused marvell_tbl[] = {
1090         { MARVELL_PHY_ID_88E1101, MARVELL_PHY_ID_MASK },
1091         { MARVELL_PHY_ID_88E1112, MARVELL_PHY_ID_MASK },
1092         { MARVELL_PHY_ID_88E1111, MARVELL_PHY_ID_MASK },
1093         { MARVELL_PHY_ID_88E1118, MARVELL_PHY_ID_MASK },
1094         { MARVELL_PHY_ID_88E1121R, MARVELL_PHY_ID_MASK },
1095         { MARVELL_PHY_ID_88E1145, MARVELL_PHY_ID_MASK },
1096         { MARVELL_PHY_ID_88E1149R, MARVELL_PHY_ID_MASK },
1097         { MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK },
1098         { MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK },
1099         { MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK },
1100         { MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK },
1101         { }
1102 };
1103
1104 MODULE_DEVICE_TABLE(mdio, marvell_tbl);