drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <net/checksum.h>
  40 #include <net/ip6_checksum.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/if_vlan.h>
  43 #include <scsi/fc/fc_fcoe.h>
  44
  45 #include "ixgbe.h"
  46 #include "ixgbe_common.h"
  47 #include "ixgbe_dcb_82599.h"
  48
  49 char ixgbe_driver_name[] = "ixgbe";
  50 static const char ixgbe_driver_string[] =
  51                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  52
  53 #define DRV_VERSION "2.0.44-k2"
  54 const char ixgbe_driver_version[] = DRV_VERSION;
  55 static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
  56
  57 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  58         [board_82598] = &ixgbe_82598_info,
  59         [board_82599] = &ixgbe_82599_info,
  60 };
  61
  62 /* ixgbe_pci_tbl - PCI Device ID Table
  63  *
  64  * Wildcard entries (PCI_ANY_ID) should come last
  65  * Last entry must be all 0s
  66  *
  67  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  68  *   Class, Class Mask, private data (not used) }
  69  */
  70 static struct pci_device_id ixgbe_pci_tbl[] = {
  71         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  72          board_82598 },
  73         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  74          board_82598 },
  75         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  76          board_82598 },
  77         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  78          board_82598 },
  79         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  80          board_82598 },
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  84          board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  86          board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  88          board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  90          board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  92          board_82598 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  94          board_82598 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  96          board_82599 },
  97         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
  98          board_82599 },
  99         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
 100          board_82599 },
 101         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 102          board_82599 },
 103         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 104          board_82599 },
 105         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 106          board_82599 },
 107
 108         /* required last entry */
 109         {0, }
 110 };
 111 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 112
 113 #ifdef CONFIG_IXGBE_DCA
 114 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 115                             void *p);
 116 static struct notifier_block dca_notifier = {
 117         .notifier_call = ixgbe_notify_dca,
 118         .next          = NULL,
 119         .priority      = 0
 120 };
 121 #endif
 122
 123 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 124 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 125 MODULE_LICENSE("GPL");
 126 MODULE_VERSION(DRV_VERSION);
 127
 128 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 129
 130 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 131 {
 132         u32 ctrl_ext;
 133
 134         /* Let firmware take over control of h/w */
 135         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 136         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 137                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 138 }
 139
 140 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 141 {
 142         u32 ctrl_ext;
 143
 144         /* Let firmware know the driver has taken over */
 145         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 146         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 147                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 148 }
 149
 150 /*
 151  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 152  * @adapter: pointer to adapter struct
 153  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 154  * @queue: queue to map the corresponding interrupt to
 155  * @msix_vector: the vector to map to the corresponding queue
 156  *
 157  */
 158 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 159                            u8 queue, u8 msix_vector)
 160 {
 161         u32 ivar, index;
 162         struct ixgbe_hw *hw = &adapter->hw;
 163         switch (hw->mac.type) {
 164         case ixgbe_mac_82598EB:
 165                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 166                 if (direction == -1)
 167                         direction = 0;
 168                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 169                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 170                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 171                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 172                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 173                 break;
 174         case ixgbe_mac_82599EB:
 175                 if (direction == -1) {
 176                         /* other causes */
 177                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 178                         index = ((queue & 1) * 8);
 179                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 180                         ivar &= ~(0xFF << index);
 181                         ivar |= (msix_vector << index);
 182                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 183                         break;
 184                 } else {
 185                         /* tx or rx causes */
 186                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 187                         index = ((16 * (queue & 1)) + (8 * direction));
 188                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 189                         ivar &= ~(0xFF << index);
 190                         ivar |= (msix_vector << index);
 191                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 192                         break;
 193                 }
 194         default:
 195                 break;
 196         }
 197 }
 198
 199 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 200                                           u64 qmask)
 201 {
 202         u32 mask;
 203
 204         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 205                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 206                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 207         } else {
 208                 mask = (qmask & 0xFFFFFFFF);
 209                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 210                 mask = (qmask >> 32);
 211                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 212         }
 213 }
 214
 215 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
 216                                              struct ixgbe_tx_buffer
 217                                              *tx_buffer_info)
 218 {
 219         tx_buffer_info->dma = 0;
 220         if (tx_buffer_info->skb) {
 221                 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
 222                               DMA_TO_DEVICE);
 223                 dev_kfree_skb_any(tx_buffer_info->skb);
 224                 tx_buffer_info->skb = NULL;
 225         }
 226         tx_buffer_info->time_stamp = 0;
 227         /* tx_buffer_info must be completely set up in the transmit path */
 228 }
 229
 230 /**
 231  * ixgbe_tx_is_paused - check if the tx ring is paused
 232  * @adapter: the ixgbe adapter
 233  * @tx_ring: the corresponding tx_ring
 234  *
 235  * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
 236  * corresponding TC of this tx_ring when checking TFCS.
 237  *
 238  * Returns : true if paused
 239  */
 240 static inline bool ixgbe_tx_is_paused(struct ixgbe_adapter *adapter,
 241                                       struct ixgbe_ring *tx_ring)
 242 {
 243         int tc;
 244         u32 txoff = IXGBE_TFCS_TXOFF;
 245
 246 #ifdef CONFIG_IXGBE_DCB
 247         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
 248                 int reg_idx = tx_ring->reg_idx;
 249                 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
 250
 251                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 252                         tc = reg_idx >> 2;
 253                         txoff = IXGBE_TFCS_TXOFF0;
 254                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 255                         tc = 0;
 256                         txoff = IXGBE_TFCS_TXOFF;
 257                         if (dcb_i == 8) {
 258                                 /* TC0, TC1 */
 259                                 tc = reg_idx >> 5;
 260                                 if (tc == 2) /* TC2, TC3 */
 261                                         tc += (reg_idx - 64) >> 4;
 262                                 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
 263                                         tc += 1 + ((reg_idx - 96) >> 3);
 264                         } else if (dcb_i == 4) {
 265                                 /* TC0, TC1 */
 266                                 tc = reg_idx >> 6;
 267                                 if (tc == 1) {
 268                                         tc += (reg_idx - 64) >> 5;
 269                                         if (tc == 2) /* TC2, TC3 */
 270                                                 tc += (reg_idx - 96) >> 4;
 271                                 }
 272                         }
 273                 }
 274                 txoff <<= tc;
 275         }
 276 #endif
 277         return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
 278 }
 279
 280 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 281                                        struct ixgbe_ring *tx_ring,
 282                                        unsigned int eop)
 283 {
 284         struct ixgbe_hw *hw = &adapter->hw;
 285
 286         /* Detect a transmit hang in hardware, this serializes the
 287          * check with the clearing of time_stamp and movement of eop */
 288         adapter->detect_tx_hung = false;
 289         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 290             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 291             !ixgbe_tx_is_paused(adapter, tx_ring)) {
 292                 /* detected Tx unit hang */
 293                 union ixgbe_adv_tx_desc *tx_desc;
 294                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 295                 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
 296                         "  Tx Queue             <%d>\n"
 297                         "  TDH, TDT             <%x>, <%x>\n"
 298                         "  next_to_use          <%x>\n"
 299                         "  next_to_clean        <%x>\n"
 300                         "tx_buffer_info[next_to_clean]\n"
 301                         "  time_stamp           <%lx>\n"
 302                         "  jiffies              <%lx>\n",
 303                         tx_ring->queue_index,
 304                         IXGBE_READ_REG(hw, tx_ring->head),
 305                         IXGBE_READ_REG(hw, tx_ring->tail),
 306                         tx_ring->next_to_use, eop,
 307                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 308                 return true;
 309         }
 310
 311         return false;
 312 }
 313
 314 #define IXGBE_MAX_TXD_PWR       14
 315 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 316
 317 /* Tx Descriptors needed, worst case */
 318 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 319                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 320 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 321         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 322
 323 static void ixgbe_tx_timeout(struct net_device *netdev);
 324
 325 /**
 326  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 327  * @q_vector: structure containing interrupt and ring information
 328  * @tx_ring: tx ring to clean
 329  **/
 330 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 331                                struct ixgbe_ring *tx_ring)
 332 {
 333         struct ixgbe_adapter *adapter = q_vector->adapter;
 334         struct net_device *netdev = adapter->netdev;
 335         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 336         struct ixgbe_tx_buffer *tx_buffer_info;
 337         unsigned int i, eop, count = 0;
 338         unsigned int total_bytes = 0, total_packets = 0;
 339
 340         i = tx_ring->next_to_clean;
 341         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 342         eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 343
 344         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 345                (count < tx_ring->work_limit)) {
 346                 bool cleaned = false;
 347                 for ( ; !cleaned; count++) {
 348                         struct sk_buff *skb;
 349                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 350                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 351                         cleaned = (i == eop);
 352                         skb = tx_buffer_info->skb;
 353
 354                         if (cleaned && skb) {
 355                                 unsigned int segs, bytecount;
 356                                 unsigned int hlen = skb_headlen(skb);
 357
 358                                 /* gso_segs is currently only valid for tcp */
 359                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
 360 #ifdef IXGBE_FCOE
 361                                 /* adjust for FCoE Sequence Offload */
 362                                 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
 363                                     && (skb->protocol == htons(ETH_P_FCOE)) &&
 364                                     skb_is_gso(skb)) {
 365                                         hlen = skb_transport_offset(skb) +
 366                                                 sizeof(struct fc_frame_header) +
 367                                                 sizeof(struct fcoe_crc_eof);
 368                                         segs = DIV_ROUND_UP(skb->len - hlen,
 369                                                 skb_shinfo(skb)->gso_size);
 370                                 }
 371 #endif /* IXGBE_FCOE */
 372                                 /* multiply data chunks by size of headers */
 373                                 bytecount = ((segs - 1) * hlen) + skb->len;
 374                                 total_packets += segs;
 375                                 total_bytes += bytecount;
 376                         }
 377
 378                         ixgbe_unmap_and_free_tx_resource(adapter,
 379                                                          tx_buffer_info);
 380
 381                         tx_desc->wb.status = 0;
 382
 383                         i++;
 384                         if (i == tx_ring->count)
 385                                 i = 0;
 386                 }
 387
 388                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 389                 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 390         }
 391
 392         tx_ring->next_to_clean = i;
 393
 394 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 395         if (unlikely(count && netif_carrier_ok(netdev) &&
 396                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 397                 /* Make sure that anybody stopping the queue after this
 398                  * sees the new next_to_clean.
 399                  */
 400                 smp_mb();
 401                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
 402                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 403                         netif_wake_subqueue(netdev, tx_ring->queue_index);
 404                         ++adapter->restart_queue;
 405                 }
 406         }
 407
 408         if (adapter->detect_tx_hung) {
 409                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 410                         /* schedule immediate reset if we believe we hung */
 411                         DPRINTK(PROBE, INFO,
 412                                 "tx hang %d detected, resetting adapter\n",
 413                                 adapter->tx_timeout_count + 1);
 414                         ixgbe_tx_timeout(adapter->netdev);
 415                 }
 416         }
 417
 418         /* re-arm the interrupt */
 419         if (count >= tx_ring->work_limit)
 420                 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
 421
 422         tx_ring->total_bytes += total_bytes;
 423         tx_ring->total_packets += total_packets;
 424         tx_ring->stats.packets += total_packets;
 425         tx_ring->stats.bytes += total_bytes;
 426         adapter->net_stats.tx_bytes += total_bytes;
 427         adapter->net_stats.tx_packets += total_packets;
 428         return (count < tx_ring->work_limit);
 429 }
 430
 431 #ifdef CONFIG_IXGBE_DCA
 432 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 433                                 struct ixgbe_ring *rx_ring)
 434 {
 435         u32 rxctrl;
 436         int cpu = get_cpu();
 437         int q = rx_ring - adapter->rx_ring;
 438
 439         if (rx_ring->cpu != cpu) {
 440                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
 441                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 442                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 443                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 444                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 445                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 446                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 447                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 448                 }
 449                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 450                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 451                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 452                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 453                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 454                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
 455                 rx_ring->cpu = cpu;
 456         }
 457         put_cpu();
 458 }
 459
 460 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 461                                 struct ixgbe_ring *tx_ring)
 462 {
 463         u32 txctrl;
 464         int cpu = get_cpu();
 465         int q = tx_ring - adapter->tx_ring;
 466         struct ixgbe_hw *hw = &adapter->hw;
 467
 468         if (tx_ring->cpu != cpu) {
 469                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 470                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
 471                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 472                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 473                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 474                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
 475                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 476                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
 477                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 478                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 479                                   IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 480                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 481                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
 482                 }
 483                 tx_ring->cpu = cpu;
 484         }
 485         put_cpu();
 486 }
 487
 488 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 489 {
 490         int i;
 491
 492         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 493                 return;
 494
 495         /* always use CB2 mode, difference is masked in the CB driver */
 496         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 497
 498         for (i = 0; i < adapter->num_tx_queues; i++) {
 499                 adapter->tx_ring[i].cpu = -1;
 500                 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
 501         }
 502         for (i = 0; i < adapter->num_rx_queues; i++) {
 503                 adapter->rx_ring[i].cpu = -1;
 504                 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
 505         }
 506 }
 507
 508 static int __ixgbe_notify_dca(struct device *dev, void *data)
 509 {
 510         struct net_device *netdev = dev_get_drvdata(dev);
 511         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 512         unsigned long event = *(unsigned long *)data;
 513
 514         switch (event) {
 515         case DCA_PROVIDER_ADD:
 516                 /* if we're already enabled, don't do it again */
 517                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 518                         break;
 519                 if (dca_add_requester(dev) == 0) {
 520                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 521                         ixgbe_setup_dca(adapter);
 522                         break;
 523                 }
 524                 /* Fall Through since DCA is disabled. */
 525         case DCA_PROVIDER_REMOVE:
 526                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 527                         dca_remove_requester(dev);
 528                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 529                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 530                 }
 531                 break;
 532         }
 533
 534         return 0;
 535 }
 536
 537 #endif /* CONFIG_IXGBE_DCA */
 538 /**
 539  * ixgbe_receive_skb - Send a completed packet up the stack
 540  * @adapter: board private structure
 541  * @skb: packet to send up
 542  * @status: hardware indication of status of receive
 543  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 544  * @rx_desc: rx descriptor
 545  **/
 546 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 547                               struct sk_buff *skb, u8 status,
 548                               struct ixgbe_ring *ring,
 549                               union ixgbe_adv_rx_desc *rx_desc)
 550 {
 551         struct ixgbe_adapter *adapter = q_vector->adapter;
 552         struct napi_struct *napi = &q_vector->napi;
 553         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 554         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 555
 556         skb_record_rx_queue(skb, ring->queue_index);
 557         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
 558                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 559                         vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
 560                 else
 561                         napi_gro_receive(napi, skb);
 562         } else {
 563                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 564                         vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
 565                 else
 566                         netif_rx(skb);
 567         }
 568 }
 569
 570 /**
 571  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 572  * @adapter: address of board private structure
 573  * @status_err: hardware indication of status of receive
 574  * @skb: skb currently being received and modified
 575  **/
 576 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 577                                      union ixgbe_adv_rx_desc *rx_desc,
 578                                      struct sk_buff *skb)
 579 {
 580         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
 581
 582         skb->ip_summed = CHECKSUM_NONE;
 583
 584         /* Rx csum disabled */
 585         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 586                 return;
 587
 588         /* if IP and error */
 589         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
 590             (status_err & IXGBE_RXDADV_ERR_IPE)) {
 591                 adapter->hw_csum_rx_error++;
 592                 return;
 593         }
 594
 595         if (!(status_err & IXGBE_RXD_STAT_L4CS))
 596                 return;
 597
 598         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
 599                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 600
 601                 /*
 602                  * 82599 errata, UDP frames with a 0 checksum can be marked as
 603                  * checksum errors.
 604                  */
 605                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
 606                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
 607                         return;
 608
 609                 adapter->hw_csum_rx_error++;
 610                 return;
 611         }
 612
 613         /* It must be a TCP or UDP packet with a valid checksum */
 614         skb->ip_summed = CHECKSUM_UNNECESSARY;
 615         adapter->hw_csum_rx_good++;
 616 }
 617
 618 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
 619                                          struct ixgbe_ring *rx_ring, u32 val)
 620 {
 621         /*
 622          * Force memory writes to complete before letting h/w
 623          * know there are new descriptors to fetch.  (Only
 624          * applicable for weak-ordered memory model archs,
 625          * such as IA-64).
 626          */
 627         wmb();
 628         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
 629 }
 630
 631 /**
 632  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
 633  * @adapter: address of board private structure
 634  **/
 635 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
 636                                    struct ixgbe_ring *rx_ring,
 637                                    int cleaned_count)
 638 {
 639         struct pci_dev *pdev = adapter->pdev;
 640         union ixgbe_adv_rx_desc *rx_desc;
 641         struct ixgbe_rx_buffer *bi;
 642         unsigned int i;
 643
 644         i = rx_ring->next_to_use;
 645         bi = &rx_ring->rx_buffer_info[i];
 646
 647         while (cleaned_count--) {
 648                 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 649
 650                 if (!bi->page_dma &&
 651                     (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
 652                         if (!bi->page) {
 653                                 bi->page = alloc_page(GFP_ATOMIC);
 654                                 if (!bi->page) {
 655                                         adapter->alloc_rx_page_failed++;
 656                                         goto no_buffers;
 657                                 }
 658                                 bi->page_offset = 0;
 659                         } else {
 660                                 /* use a half page if we're re-using */
 661                                 bi->page_offset ^= (PAGE_SIZE / 2);
 662                         }
 663
 664                         bi->page_dma = pci_map_page(pdev, bi->page,
 665                                                     bi->page_offset,
 666                                                     (PAGE_SIZE / 2),
 667                                                     PCI_DMA_FROMDEVICE);
 668                 }
 669
 670                 if (!bi->skb) {
 671                         struct sk_buff *skb;
 672                         skb = netdev_alloc_skb(adapter->netdev,
 673                                                (rx_ring->rx_buf_len +
 674                                                 NET_IP_ALIGN));
 675
 676                         if (!skb) {
 677                                 adapter->alloc_rx_buff_failed++;
 678                                 goto no_buffers;
 679                         }
 680
 681                         /*
 682                          * Make buffer alignment 2 beyond a 16 byte boundary
 683                          * this will result in a 16 byte aligned IP header after
 684                          * the 14 byte MAC header is removed
 685                          */
 686                         skb_reserve(skb, NET_IP_ALIGN);
 687
 688                         bi->skb = skb;
 689                         bi->dma = pci_map_single(pdev, skb->data,
 690                                                  rx_ring->rx_buf_len,
 691                                                  PCI_DMA_FROMDEVICE);
 692                 }
 693                 /* Refresh the desc even if buffer_addrs didn't change because
 694                  * each write-back erases this info. */
 695                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 696                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
 697                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 698                 } else {
 699                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 700                 }
 701
 702                 i++;
 703                 if (i == rx_ring->count)
 704                         i = 0;
 705                 bi = &rx_ring->rx_buffer_info[i];
 706         }
 707
 708 no_buffers:
 709         if (rx_ring->next_to_use != i) {
 710                 rx_ring->next_to_use = i;
 711                 if (i-- == 0)
 712                         i = (rx_ring->count - 1);
 713
 714                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
 715         }
 716 }
 717
 718 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
 719 {
 720         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
 721 }
 722
 723 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
 724 {
 725         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 726 }
 727
 728 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
 729 {
 730         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
 731                 IXGBE_RXDADV_RSCCNT_MASK) >>
 732                 IXGBE_RXDADV_RSCCNT_SHIFT;
 733 }
 734
 735 /**
 736  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
 737  * @skb: pointer to the last skb in the rsc queue
 738  *
 739  * This function changes a queue full of hw rsc buffers into a completed
 740  * packet.  It uses the ->prev pointers to find the first packet and then
 741  * turns it into the frag list owner.
 742  **/
 743 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
 744 {
 745         unsigned int frag_list_size = 0;
 746
 747         while (skb->prev) {
 748                 struct sk_buff *prev = skb->prev;
 749                 frag_list_size += skb->len;
 750                 skb->prev = NULL;
 751                 skb = prev;
 752         }
 753
 754         skb_shinfo(skb)->frag_list = skb->next;
 755         skb->next = NULL;
 756         skb->len += frag_list_size;
 757         skb->data_len += frag_list_size;
 758         skb->truesize += frag_list_size;
 759         return skb;
 760 }
 761
 762 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
 763                                struct ixgbe_ring *rx_ring,
 764                                int *work_done, int work_to_do)
 765 {
 766         struct ixgbe_adapter *adapter = q_vector->adapter;
 767         struct pci_dev *pdev = adapter->pdev;
 768         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
 769         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
 770         struct sk_buff *skb;
 771         unsigned int i, rsc_count = 0;
 772         u32 len, staterr;
 773         u16 hdr_info;
 774         bool cleaned = false;
 775         int cleaned_count = 0;
 776         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 777 #ifdef IXGBE_FCOE
 778         int ddp_bytes = 0;
 779 #endif /* IXGBE_FCOE */
 780
 781         i = rx_ring->next_to_clean;
 782         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 783         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 784         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 785
 786         while (staterr & IXGBE_RXD_STAT_DD) {
 787                 u32 upper_len = 0;
 788                 if (*work_done >= work_to_do)
 789                         break;
 790                 (*work_done)++;
 791
 792                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 793                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
 794                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
 795                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
 796                         if (hdr_info & IXGBE_RXDADV_SPH)
 797                                 adapter->rx_hdr_split++;
 798                         if (len > IXGBE_RX_HDR_SIZE)
 799                                 len = IXGBE_RX_HDR_SIZE;
 800                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
 801                 } else {
 802                         len = le16_to_cpu(rx_desc->wb.upper.length);
 803                 }
 804
 805                 cleaned = true;
 806                 skb = rx_buffer_info->skb;
 807                 prefetch(skb->data - NET_IP_ALIGN);
 808                 rx_buffer_info->skb = NULL;
 809
 810                 if (rx_buffer_info->dma) {
 811                         pci_unmap_single(pdev, rx_buffer_info->dma,
 812                                          rx_ring->rx_buf_len,
 813                                          PCI_DMA_FROMDEVICE);
 814                         rx_buffer_info->dma = 0;
 815                         skb_put(skb, len);
 816                 }
 817
 818                 if (upper_len) {
 819                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
 820                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
 821                         rx_buffer_info->page_dma = 0;
 822                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
 823                                            rx_buffer_info->page,
 824                                            rx_buffer_info->page_offset,
 825                                            upper_len);
 826
 827                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
 828                             (page_count(rx_buffer_info->page) != 1))
 829                                 rx_buffer_info->page = NULL;
 830                         else
 831                                 get_page(rx_buffer_info->page);
 832
 833                         skb->len += upper_len;
 834                         skb->data_len += upper_len;
 835                         skb->truesize += upper_len;
 836                 }
 837
 838                 i++;
 839                 if (i == rx_ring->count)
 840                         i = 0;
 841
 842                 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
 843                 prefetch(next_rxd);
 844                 cleaned_count++;
 845
 846                 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
 847                         rsc_count = ixgbe_get_rsc_count(rx_desc);
 848
 849                 if (rsc_count) {
 850                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
 851                                      IXGBE_RXDADV_NEXTP_SHIFT;
 852                         next_buffer = &rx_ring->rx_buffer_info[nextp];
 853                         rx_ring->rsc_count += (rsc_count - 1);
 854                 } else {
 855                         next_buffer = &rx_ring->rx_buffer_info[i];
 856                 }
 857
 858                 if (staterr & IXGBE_RXD_STAT_EOP) {
 859                         if (skb->prev)
 860                                 skb = ixgbe_transform_rsc_queue(skb);
 861                         rx_ring->stats.packets++;
 862                         rx_ring->stats.bytes += skb->len;
 863                 } else {
 864                         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 865                                 rx_buffer_info->skb = next_buffer->skb;
 866                                 rx_buffer_info->dma = next_buffer->dma;
 867                                 next_buffer->skb = skb;
 868                                 next_buffer->dma = 0;
 869                         } else {
 870                                 skb->next = next_buffer->skb;
 871                                 skb->next->prev = skb;
 872                         }
 873                         adapter->non_eop_descs++;
 874                         goto next_desc;
 875                 }
 876
 877                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
 878                         dev_kfree_skb_irq(skb);
 879                         goto next_desc;
 880                 }
 881
 882                 ixgbe_rx_checksum(adapter, rx_desc, skb);
 883
 884                 /* probably a little skewed due to removing CRC */
 885                 total_rx_bytes += skb->len;
 886                 total_rx_packets++;
 887
 888                 skb->protocol = eth_type_trans(skb, adapter->netdev);
 889 #ifdef IXGBE_FCOE
 890                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
 891                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
 892                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
 893                         if (!ddp_bytes)
 894                                 goto next_desc;
 895                 }
 896 #endif /* IXGBE_FCOE */
 897                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
 898
 899 next_desc:
 900                 rx_desc->wb.upper.status_error = 0;
 901
 902                 /* return some buffers to hardware, one at a time is too slow */
 903                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
 904                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 905                         cleaned_count = 0;
 906                 }
 907
 908                 /* use prefetched values */
 909                 rx_desc = next_rxd;
 910                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
 911
 912                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 913         }
 914
 915         rx_ring->next_to_clean = i;
 916         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
 917
 918         if (cleaned_count)
 919                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 920
 921 #ifdef IXGBE_FCOE
 922         /* include DDPed FCoE data */
 923         if (ddp_bytes > 0) {
 924                 unsigned int mss;
 925
 926                 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
 927                         sizeof(struct fc_frame_header) -
 928                         sizeof(struct fcoe_crc_eof);
 929                 if (mss > 512)
 930                         mss &= ~511;
 931                 total_rx_bytes += ddp_bytes;
 932                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
 933         }
 934 #endif /* IXGBE_FCOE */
 935
 936         rx_ring->total_packets += total_rx_packets;
 937         rx_ring->total_bytes += total_rx_bytes;
 938         adapter->net_stats.rx_bytes += total_rx_bytes;
 939         adapter->net_stats.rx_packets += total_rx_packets;
 940
 941         return cleaned;
 942 }
 943
 944 static int ixgbe_clean_rxonly(struct napi_struct *, int);
 945 /**
 946  * ixgbe_configure_msix - Configure MSI-X hardware
 947  * @adapter: board private structure
 948  *
 949  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
 950  * interrupts.
 951  **/
 952 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
 953 {
 954         struct ixgbe_q_vector *q_vector;
 955         int i, j, q_vectors, v_idx, r_idx;
 956         u32 mask;
 957
 958         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 959
 960         /*
 961          * Populate the IVAR table and set the ITR values to the
 962          * corresponding register.
 963          */
 964         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
 965                 q_vector = adapter->q_vector[v_idx];
 966                 /* XXX for_each_bit(...) */
 967                 r_idx = find_first_bit(q_vector->rxr_idx,
 968                                        adapter->num_rx_queues);
 969
 970                 for (i = 0; i < q_vector->rxr_count; i++) {
 971                         j = adapter->rx_ring[r_idx].reg_idx;
 972                         ixgbe_set_ivar(adapter, 0, j, v_idx);
 973                         r_idx = find_next_bit(q_vector->rxr_idx,
 974                                               adapter->num_rx_queues,
 975                                               r_idx + 1);
 976                 }
 977                 r_idx = find_first_bit(q_vector->txr_idx,
 978                                        adapter->num_tx_queues);
 979
 980                 for (i = 0; i < q_vector->txr_count; i++) {
 981                         j = adapter->tx_ring[r_idx].reg_idx;
 982                         ixgbe_set_ivar(adapter, 1, j, v_idx);
 983                         r_idx = find_next_bit(q_vector->txr_idx,
 984                                               adapter->num_tx_queues,
 985                                               r_idx + 1);
 986                 }
 987
 988                 if (q_vector->txr_count && !q_vector->rxr_count)
 989                         /* tx only */
 990                         q_vector->eitr = adapter->tx_eitr_param;
 991                 else if (q_vector->rxr_count)
 992                         /* rx or mixed */
 993                         q_vector->eitr = adapter->rx_eitr_param;
 994
 995                 ixgbe_write_eitr(q_vector);
 996         }
 997
 998         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
 999                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1000                                v_idx);
1001         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1002                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1003         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1004
1005         /* set up to autoclear timer, and the vectors */
1006         mask = IXGBE_EIMS_ENABLE_MASK;
1007         mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1008         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1009 }
1010
1011 enum latency_range {
1012         lowest_latency = 0,
1013         low_latency = 1,
1014         bulk_latency = 2,
1015         latency_invalid = 255
1016 };
1017
1018 /**
1019  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1020  * @adapter: pointer to adapter
1021  * @eitr: eitr setting (ints per sec) to give last timeslice
1022  * @itr_setting: current throttle rate in ints/second
1023  * @packets: the number of packets during this measurement interval
1024  * @bytes: the number of bytes during this measurement interval
1025  *
1026  *      Stores a new ITR value based on packets and byte
1027  *      counts during the last interrupt.  The advantage of per interrupt
1028  *      computation is faster updates and more accurate ITR for the current
1029  *      traffic pattern.  Constants in this function were computed
1030  *      based on theoretical maximum wire speed and thresholds were set based
1031  *      on testing data as well as attempting to minimize response time
1032  *      while increasing bulk throughput.
1033  *      this functionality is controlled by the InterruptThrottleRate module
1034  *      parameter (see ixgbe_param.c)
1035  **/
1036 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1037                            u32 eitr, u8 itr_setting,
1038                            int packets, int bytes)
1039 {
1040         unsigned int retval = itr_setting;
1041         u32 timepassed_us;
1042         u64 bytes_perint;
1043
1044         if (packets == 0)
1045                 goto update_itr_done;
1046
1047
1048         /* simple throttlerate management
1049          *    0-20MB/s lowest (100000 ints/s)
1050          *   20-100MB/s low   (20000 ints/s)
1051          *  100-1249MB/s bulk (8000 ints/s)
1052          */
1053         /* what was last interrupt timeslice? */
1054         timepassed_us = 1000000/eitr;
1055         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1056
1057         switch (itr_setting) {
1058         case lowest_latency:
1059                 if (bytes_perint > adapter->eitr_low)
1060                         retval = low_latency;
1061                 break;
1062         case low_latency:
1063                 if (bytes_perint > adapter->eitr_high)
1064                         retval = bulk_latency;
1065                 else if (bytes_perint <= adapter->eitr_low)
1066                         retval = lowest_latency;
1067                 break;
1068         case bulk_latency:
1069                 if (bytes_perint <= adapter->eitr_high)
1070                         retval = low_latency;
1071                 break;
1072         }
1073
1074 update_itr_done:
1075         return retval;
1076 }
1077
1078 /**
1079  * ixgbe_write_eitr - write EITR register in hardware specific way
1080  * @q_vector: structure containing interrupt and ring information
1081  *
1082  * This function is made to be called by ethtool and by the driver
1083  * when it needs to update EITR registers at runtime.  Hardware
1084  * specific quirks/differences are taken care of here.
1085  */
1086 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1087 {
1088         struct ixgbe_adapter *adapter = q_vector->adapter;
1089         struct ixgbe_hw *hw = &adapter->hw;
1090         int v_idx = q_vector->v_idx;
1091         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1092
1093         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1094                 /* must write high and low 16 bits to reset counter */
1095                 itr_reg |= (itr_reg << 16);
1096         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1097                 /*
1098                  * set the WDIS bit to not clear the timer bits and cause an
1099                  * immediate assertion of the interrupt
1100                  */
1101                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1102         }
1103         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1104 }
1105
1106 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1107 {
1108         struct ixgbe_adapter *adapter = q_vector->adapter;
1109         u32 new_itr;
1110         u8 current_itr, ret_itr;
1111         int i, r_idx;
1112         struct ixgbe_ring *rx_ring, *tx_ring;
1113
1114         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1115         for (i = 0; i < q_vector->txr_count; i++) {
1116                 tx_ring = &(adapter->tx_ring[r_idx]);
1117                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1118                                            q_vector->tx_itr,
1119                                            tx_ring->total_packets,
1120                                            tx_ring->total_bytes);
1121                 /* if the result for this queue would decrease interrupt
1122                  * rate for this vector then use that result */
1123                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1124                                     q_vector->tx_itr - 1 : ret_itr);
1125                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1126                                       r_idx + 1);
1127         }
1128
1129         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1130         for (i = 0; i < q_vector->rxr_count; i++) {
1131                 rx_ring = &(adapter->rx_ring[r_idx]);
1132                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1133                                            q_vector->rx_itr,
1134                                            rx_ring->total_packets,
1135                                            rx_ring->total_bytes);
1136                 /* if the result for this queue would decrease interrupt
1137                  * rate for this vector then use that result */
1138                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1139                                     q_vector->rx_itr - 1 : ret_itr);
1140                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1141                                       r_idx + 1);
1142         }
1143
1144         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1145
1146         switch (current_itr) {
1147         /* counts and packets in update_itr are dependent on these numbers */
1148         case lowest_latency:
1149                 new_itr = 100000;
1150                 break;
1151         case low_latency:
1152                 new_itr = 20000; /* aka hwitr = ~200 */
1153                 break;
1154         case bulk_latency:
1155         default:
1156                 new_itr = 8000;
1157                 break;
1158         }
1159
1160         if (new_itr != q_vector->eitr) {
1161                 /* do an exponential smoothing */
1162                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1163
1164                 /* save the algorithm value here, not the smoothed one */
1165                 q_vector->eitr = new_itr;
1166
1167                 ixgbe_write_eitr(q_vector);
1168         }
1169
1170         return;
1171 }
1172
1173 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1174 {
1175         struct ixgbe_hw *hw = &adapter->hw;
1176
1177         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1178             (eicr & IXGBE_EICR_GPI_SDP1)) {
1179                 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1180                 /* write to clear the interrupt */
1181                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1182         }
1183 }
1184
1185 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1186 {
1187         struct ixgbe_hw *hw = &adapter->hw;
1188
1189         if (eicr & IXGBE_EICR_GPI_SDP1) {
1190                 /* Clear the interrupt */
1191                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1192                 schedule_work(&adapter->multispeed_fiber_task);
1193         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1194                 /* Clear the interrupt */
1195                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1196                 schedule_work(&adapter->sfp_config_module_task);
1197         } else {
1198                 /* Interrupt isn't for us... */
1199                 return;
1200         }
1201 }
1202
1203 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1204 {
1205         struct ixgbe_hw *hw = &adapter->hw;
1206
1207         adapter->lsc_int++;
1208         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1209         adapter->link_check_timeout = jiffies;
1210         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1211                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1212                 schedule_work(&adapter->watchdog_task);
1213         }
1214 }
1215
1216 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1217 {
1218         struct net_device *netdev = data;
1219         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1220         struct ixgbe_hw *hw = &adapter->hw;
1221         u32 eicr;
1222
1223         /*
1224          * Workaround for Silicon errata.  Use clear-by-write instead
1225          * of clear-by-read.  Reading with EICS will return the
1226          * interrupt causes without clearing, which later be done
1227          * with the write to EICR.
1228          */
1229         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1230         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1231
1232         if (eicr & IXGBE_EICR_LSC)
1233                 ixgbe_check_lsc(adapter);
1234
1235         if (hw->mac.type == ixgbe_mac_82598EB)
1236                 ixgbe_check_fan_failure(adapter, eicr);
1237
1238         if (hw->mac.type == ixgbe_mac_82599EB) {
1239                 ixgbe_check_sfp_event(adapter, eicr);
1240
1241                 /* Handle Flow Director Full threshold interrupt */
1242                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1243                         int i;
1244                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1245                         /* Disable transmits before FDIR Re-initialization */
1246                         netif_tx_stop_all_queues(netdev);
1247                         for (i = 0; i < adapter->num_tx_queues; i++) {
1248                                 struct ixgbe_ring *tx_ring =
1249                                                            &adapter->tx_ring[i];
1250                                 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1251                                                        &tx_ring->reinit_state))
1252                                         schedule_work(&adapter->fdir_reinit_task);
1253                         }
1254                 }
1255         }
1256         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1257                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1258
1259         return IRQ_HANDLED;
1260 }
1261
1262 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1263                                            u64 qmask)
1264 {
1265         u32 mask;
1266
1267         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1268                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1269                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1270         } else {
1271                 mask = (qmask & 0xFFFFFFFF);
1272                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1273                 mask = (qmask >> 32);
1274                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1275         }
1276         /* skip the flush */
1277 }
1278
1279 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1280                                             u64 qmask)
1281 {
1282         u32 mask;
1283
1284         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1285                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1286                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1287         } else {
1288                 mask = (qmask & 0xFFFFFFFF);
1289                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1290                 mask = (qmask >> 32);
1291                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1292         }
1293         /* skip the flush */
1294 }
1295
1296 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1297 {
1298         struct ixgbe_q_vector *q_vector = data;
1299         struct ixgbe_adapter  *adapter = q_vector->adapter;
1300         struct ixgbe_ring     *tx_ring;
1301         int i, r_idx;
1302
1303         if (!q_vector->txr_count)
1304                 return IRQ_HANDLED;
1305
1306         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1307         for (i = 0; i < q_vector->txr_count; i++) {
1308                 tx_ring = &(adapter->tx_ring[r_idx]);
1309                 tx_ring->total_bytes = 0;
1310                 tx_ring->total_packets = 0;
1311                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1312                                       r_idx + 1);
1313         }
1314
1315         /* disable interrupts on this vector only */
1316         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1317         napi_schedule(&q_vector->napi);
1318
1319         return IRQ_HANDLED;
1320 }
1321
1322 /**
1323  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1324  * @irq: unused
1325  * @data: pointer to our q_vector struct for this interrupt vector
1326  **/
1327 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1328 {
1329         struct ixgbe_q_vector *q_vector = data;
1330         struct ixgbe_adapter  *adapter = q_vector->adapter;
1331         struct ixgbe_ring  *rx_ring;
1332         int r_idx;
1333         int i;
1334
1335         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1336         for (i = 0;  i < q_vector->rxr_count; i++) {
1337                 rx_ring = &(adapter->rx_ring[r_idx]);
1338                 rx_ring->total_bytes = 0;
1339                 rx_ring->total_packets = 0;
1340                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1341                                       r_idx + 1);
1342         }
1343
1344         if (!q_vector->rxr_count)
1345                 return IRQ_HANDLED;
1346
1347         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1348         rx_ring = &(adapter->rx_ring[r_idx]);
1349         /* disable interrupts on this vector only */
1350         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1351         napi_schedule(&q_vector->napi);
1352
1353         return IRQ_HANDLED;
1354 }
1355
1356 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1357 {
1358         struct ixgbe_q_vector *q_vector = data;
1359         struct ixgbe_adapter  *adapter = q_vector->adapter;
1360         struct ixgbe_ring  *ring;
1361         int r_idx;
1362         int i;
1363
1364         if (!q_vector->txr_count && !q_vector->rxr_count)
1365                 return IRQ_HANDLED;
1366
1367         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1368         for (i = 0; i < q_vector->txr_count; i++) {
1369                 ring = &(adapter->tx_ring[r_idx]);
1370                 ring->total_bytes = 0;
1371                 ring->total_packets = 0;
1372                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1373                                       r_idx + 1);
1374         }
1375
1376         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1377         for (i = 0; i < q_vector->rxr_count; i++) {
1378                 ring = &(adapter->rx_ring[r_idx]);
1379                 ring->total_bytes = 0;
1380                 ring->total_packets = 0;
1381                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1382                                       r_idx + 1);
1383         }
1384
1385         /* disable interrupts on this vector only */
1386         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1387         napi_schedule(&q_vector->napi);
1388
1389         return IRQ_HANDLED;
1390 }
1391
1392 /**
1393  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1394  * @napi: napi struct with our devices info in it
1395  * @budget: amount of work driver is allowed to do this pass, in packets
1396  *
1397  * This function is optimized for cleaning one queue only on a single
1398  * q_vector!!!
1399  **/
1400 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1401 {
1402         struct ixgbe_q_vector *q_vector =
1403                                container_of(napi, struct ixgbe_q_vector, napi);
1404         struct ixgbe_adapter *adapter = q_vector->adapter;
1405         struct ixgbe_ring *rx_ring = NULL;
1406         int work_done = 0;
1407         long r_idx;
1408
1409         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1410         rx_ring = &(adapter->rx_ring[r_idx]);
1411 #ifdef CONFIG_IXGBE_DCA
1412         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1413                 ixgbe_update_rx_dca(adapter, rx_ring);
1414 #endif
1415
1416         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1417
1418         /* If all Rx work done, exit the polling mode */
1419         if (work_done < budget) {
1420                 napi_complete(napi);
1421                 if (adapter->rx_itr_setting & 1)
1422                         ixgbe_set_itr_msix(q_vector);
1423                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1424                         ixgbe_irq_enable_queues(adapter,
1425                                                 ((u64)1 << q_vector->v_idx));
1426         }
1427
1428         return work_done;
1429 }
1430
1431 /**
1432  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1433  * @napi: napi struct with our devices info in it
1434  * @budget: amount of work driver is allowed to do this pass, in packets
1435  *
1436  * This function will clean more than one rx queue associated with a
1437  * q_vector.
1438  **/
1439 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1440 {
1441         struct ixgbe_q_vector *q_vector =
1442                                container_of(napi, struct ixgbe_q_vector, napi);
1443         struct ixgbe_adapter *adapter = q_vector->adapter;
1444         struct ixgbe_ring *ring = NULL;
1445         int work_done = 0, i;
1446         long r_idx;
1447         bool tx_clean_complete = true;
1448
1449         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1450         for (i = 0; i < q_vector->txr_count; i++) {
1451                 ring = &(adapter->tx_ring[r_idx]);
1452 #ifdef CONFIG_IXGBE_DCA
1453                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1454                         ixgbe_update_tx_dca(adapter, ring);
1455 #endif
1456                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1457                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1458                                       r_idx + 1);
1459         }
1460
1461         /* attempt to distribute budget to each queue fairly, but don't allow
1462          * the budget to go below 1 because we'll exit polling */
1463         budget /= (q_vector->rxr_count ?: 1);
1464         budget = max(budget, 1);
1465         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1466         for (i = 0; i < q_vector->rxr_count; i++) {
1467                 ring = &(adapter->rx_ring[r_idx]);
1468 #ifdef CONFIG_IXGBE_DCA
1469                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1470                         ixgbe_update_rx_dca(adapter, ring);
1471 #endif
1472                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1473                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1474                                       r_idx + 1);
1475         }
1476
1477         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1478         ring = &(adapter->rx_ring[r_idx]);
1479         /* If all Rx work done, exit the polling mode */
1480         if (work_done < budget) {
1481                 napi_complete(napi);
1482                 if (adapter->rx_itr_setting & 1)
1483                         ixgbe_set_itr_msix(q_vector);
1484                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1485                         ixgbe_irq_enable_queues(adapter,
1486                                                 ((u64)1 << q_vector->v_idx));
1487                 return 0;
1488         }
1489
1490         return work_done;
1491 }
1492
1493 /**
1494  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1495  * @napi: napi struct with our devices info in it
1496  * @budget: amount of work driver is allowed to do this pass, in packets
1497  *
1498  * This function is optimized for cleaning one queue only on a single
1499  * q_vector!!!
1500  **/
1501 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1502 {
1503         struct ixgbe_q_vector *q_vector =
1504                                container_of(napi, struct ixgbe_q_vector, napi);
1505         struct ixgbe_adapter *adapter = q_vector->adapter;
1506         struct ixgbe_ring *tx_ring = NULL;
1507         int work_done = 0;
1508         long r_idx;
1509
1510         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1511         tx_ring = &(adapter->tx_ring[r_idx]);
1512 #ifdef CONFIG_IXGBE_DCA
1513         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1514                 ixgbe_update_tx_dca(adapter, tx_ring);
1515 #endif
1516
1517         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1518                 work_done = budget;
1519
1520         /* If all Tx work done, exit the polling mode */
1521         if (work_done < budget) {
1522                 napi_complete(napi);
1523                 if (adapter->tx_itr_setting & 1)
1524                         ixgbe_set_itr_msix(q_vector);
1525                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1526                         ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1527         }
1528
1529         return work_done;
1530 }
1531
1532 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1533                                      int r_idx)
1534 {
1535         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1536
1537         set_bit(r_idx, q_vector->rxr_idx);
1538         q_vector->rxr_count++;
1539 }
1540
1541 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1542                                      int t_idx)
1543 {
1544         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1545
1546         set_bit(t_idx, q_vector->txr_idx);
1547         q_vector->txr_count++;
1548 }
1549
1550 /**
1551  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1552  * @adapter: board private structure to initialize
1553  * @vectors: allotted vector count for descriptor rings
1554  *
1555  * This function maps descriptor rings to the queue-specific vectors
1556  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
1557  * one vector per ring/queue, but on a constrained vector budget, we
1558  * group the rings as "efficiently" as possible.  You would add new
1559  * mapping configurations in here.
1560  **/
1561 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1562                                       int vectors)
1563 {
1564         int v_start = 0;
1565         int rxr_idx = 0, txr_idx = 0;
1566         int rxr_remaining = adapter->num_rx_queues;
1567         int txr_remaining = adapter->num_tx_queues;
1568         int i, j;
1569         int rqpv, tqpv;
1570         int err = 0;
1571
1572         /* No mapping required if MSI-X is disabled. */
1573         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1574                 goto out;
1575
1576         /*
1577          * The ideal configuration...
1578          * We have enough vectors to map one per queue.
1579          */
1580         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1581                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1582                         map_vector_to_rxq(adapter, v_start, rxr_idx);
1583
1584                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1585                         map_vector_to_txq(adapter, v_start, txr_idx);
1586
1587                 goto out;
1588         }
1589
1590         /*
1591          * If we don't have enough vectors for a 1-to-1
1592          * mapping, we'll have to group them so there are
1593          * multiple queues per vector.
1594          */
1595         /* Re-adjusting *qpv takes care of the remainder. */
1596         for (i = v_start; i < vectors; i++) {
1597                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1598                 for (j = 0; j < rqpv; j++) {
1599                         map_vector_to_rxq(adapter, i, rxr_idx);
1600                         rxr_idx++;
1601                         rxr_remaining--;
1602                 }
1603         }
1604         for (i = v_start; i < vectors; i++) {
1605                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1606                 for (j = 0; j < tqpv; j++) {
1607                         map_vector_to_txq(adapter, i, txr_idx);
1608                         txr_idx++;
1609                         txr_remaining--;
1610                 }
1611         }
1612
1613 out:
1614         return err;
1615 }
1616
1617 /**
1618  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1619  * @adapter: board private structure
1620  *
1621  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1622  * interrupts from the kernel.
1623  **/
1624 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1625 {
1626         struct net_device *netdev = adapter->netdev;
1627         irqreturn_t (*handler)(int, void *);
1628         int i, vector, q_vectors, err;
1629         int ri=0, ti=0;
1630
1631         /* Decrement for Other and TCP Timer vectors */
1632         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1633
1634         /* Map the Tx/Rx rings to the vectors we were allotted. */
1635         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1636         if (err)
1637                 goto out;
1638
1639 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1640                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1641                          &ixgbe_msix_clean_many)
1642         for (vector = 0; vector < q_vectors; vector++) {
1643                 handler = SET_HANDLER(adapter->q_vector[vector]);
1644
1645                 if(handler == &ixgbe_msix_clean_rx) {
1646                         sprintf(adapter->name[vector], "%s-%s-%d",
1647                                 netdev->name, "rx", ri++);
1648                 }
1649                 else if(handler == &ixgbe_msix_clean_tx) {
1650                         sprintf(adapter->name[vector], "%s-%s-%d",
1651                                 netdev->name, "tx", ti++);
1652                 }
1653                 else
1654                         sprintf(adapter->name[vector], "%s-%s-%d",
1655                                 netdev->name, "TxRx", vector);
1656
1657                 err = request_irq(adapter->msix_entries[vector].vector,
1658                                   handler, 0, adapter->name[vector],
1659                                   adapter->q_vector[vector]);
1660                 if (err) {
1661                         DPRINTK(PROBE, ERR,
1662                                 "request_irq failed for MSIX interrupt "
1663                                 "Error: %d\n", err);
1664                         goto free_queue_irqs;
1665                 }
1666         }
1667
1668         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1669         err = request_irq(adapter->msix_entries[vector].vector,
1670                           &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1671         if (err) {
1672                 DPRINTK(PROBE, ERR,
1673                         "request_irq for msix_lsc failed: %d\n", err);
1674                 goto free_queue_irqs;
1675         }
1676
1677         return 0;
1678
1679 free_queue_irqs:
1680         for (i = vector - 1; i >= 0; i--)
1681                 free_irq(adapter->msix_entries[--vector].vector,
1682                          adapter->q_vector[i]);
1683         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1684         pci_disable_msix(adapter->pdev);
1685         kfree(adapter->msix_entries);
1686         adapter->msix_entries = NULL;
1687 out:
1688         return err;
1689 }
1690
1691 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1692 {
1693         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1694         u8 current_itr;
1695         u32 new_itr = q_vector->eitr;
1696         struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1697         struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1698
1699         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1700                                             q_vector->tx_itr,
1701                                             tx_ring->total_packets,
1702                                             tx_ring->total_bytes);
1703         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1704                                             q_vector->rx_itr,
1705                                             rx_ring->total_packets,
1706                                             rx_ring->total_bytes);
1707
1708         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1709
1710         switch (current_itr) {
1711         /* counts and packets in update_itr are dependent on these numbers */
1712         case lowest_latency:
1713                 new_itr = 100000;
1714                 break;
1715         case low_latency:
1716                 new_itr = 20000; /* aka hwitr = ~200 */
1717                 break;
1718         case bulk_latency:
1719                 new_itr = 8000;
1720                 break;
1721         default:
1722                 break;
1723         }
1724
1725         if (new_itr != q_vector->eitr) {
1726                 /* do an exponential smoothing */
1727                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1728
1729                 /* save the algorithm value here, not the smoothed one */
1730                 q_vector->eitr = new_itr;
1731
1732                 ixgbe_write_eitr(q_vector);
1733         }
1734
1735         return;
1736 }
1737
1738 /**
1739  * ixgbe_irq_enable - Enable default interrupt generation settings
1740  * @adapter: board private structure
1741  **/
1742 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1743 {
1744         u32 mask;
1745
1746         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1747         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1748                 mask |= IXGBE_EIMS_GPI_SDP1;
1749         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1750                 mask |= IXGBE_EIMS_ECC;
1751                 mask |= IXGBE_EIMS_GPI_SDP1;
1752                 mask |= IXGBE_EIMS_GPI_SDP2;
1753         }
1754         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1755             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1756                 mask |= IXGBE_EIMS_FLOW_DIR;
1757
1758         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1759         ixgbe_irq_enable_queues(adapter, ~0);
1760         IXGBE_WRITE_FLUSH(&adapter->hw);
1761 }
1762
1763 /**
1764  * ixgbe_intr - legacy mode Interrupt Handler
1765  * @irq: interrupt number
1766  * @data: pointer to a network interface device structure
1767  **/
1768 static irqreturn_t ixgbe_intr(int irq, void *data)
1769 {
1770         struct net_device *netdev = data;
1771         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1772         struct ixgbe_hw *hw = &adapter->hw;
1773         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1774         u32 eicr;
1775
1776         /*
1777          * Workaround for silicon errata.  Mask the interrupts
1778          * before the read of EICR.
1779          */
1780         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1781
1782         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1783          * therefore no explict interrupt disable is necessary */
1784         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1785         if (!eicr) {
1786                 /* shared interrupt alert!
1787                  * make sure interrupts are enabled because the read will
1788                  * have disabled interrupts due to EIAM */
1789                 ixgbe_irq_enable(adapter);
1790                 return IRQ_NONE;        /* Not our interrupt */
1791         }
1792
1793         if (eicr & IXGBE_EICR_LSC)
1794                 ixgbe_check_lsc(adapter);
1795
1796         if (hw->mac.type == ixgbe_mac_82599EB)
1797                 ixgbe_check_sfp_event(adapter, eicr);
1798
1799         ixgbe_check_fan_failure(adapter, eicr);
1800
1801         if (napi_schedule_prep(&(q_vector->napi))) {
1802                 adapter->tx_ring[0].total_packets = 0;
1803                 adapter->tx_ring[0].total_bytes = 0;
1804                 adapter->rx_ring[0].total_packets = 0;
1805                 adapter->rx_ring[0].total_bytes = 0;
1806                 /* would disable interrupts here but EIAM disabled it */
1807                 __napi_schedule(&(q_vector->napi));
1808         }
1809
1810         return IRQ_HANDLED;
1811 }
1812
1813 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1814 {
1815         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1816
1817         for (i = 0; i < q_vectors; i++) {
1818                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
1819                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1820                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1821                 q_vector->rxr_count = 0;
1822                 q_vector->txr_count = 0;
1823         }
1824 }
1825
1826 /**
1827  * ixgbe_request_irq - initialize interrupts
1828  * @adapter: board private structure
1829  *
1830  * Attempts to configure interrupts using the best available
1831  * capabilities of the hardware and kernel.
1832  **/
1833 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1834 {
1835         struct net_device *netdev = adapter->netdev;
1836         int err;
1837
1838         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1839                 err = ixgbe_request_msix_irqs(adapter);
1840         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1841                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1842                                   netdev->name, netdev);
1843         } else {
1844                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1845                                   netdev->name, netdev);
1846         }
1847
1848         if (err)
1849                 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1850
1851         return err;
1852 }
1853
1854 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1855 {
1856         struct net_device *netdev = adapter->netdev;
1857
1858         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1859                 int i, q_vectors;
1860
1861                 q_vectors = adapter->num_msix_vectors;
1862
1863                 i = q_vectors - 1;
1864                 free_irq(adapter->msix_entries[i].vector, netdev);
1865
1866                 i--;
1867                 for (; i >= 0; i--) {
1868                         free_irq(adapter->msix_entries[i].vector,
1869                                  adapter->q_vector[i]);
1870                 }
1871
1872                 ixgbe_reset_q_vectors(adapter);
1873         } else {
1874                 free_irq(adapter->pdev->irq, netdev);
1875         }
1876 }
1877
1878 /**
1879  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1880  * @adapter: board private structure
1881  **/
1882 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1883 {
1884         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1885                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1886         } else {
1887                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1888                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
1889                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1890         }
1891         IXGBE_WRITE_FLUSH(&adapter->hw);
1892         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1893                 int i;
1894                 for (i = 0; i < adapter->num_msix_vectors; i++)
1895                         synchronize_irq(adapter->msix_entries[i].vector);
1896         } else {
1897                 synchronize_irq(adapter->pdev->irq);
1898         }
1899 }
1900
1901 /**
1902  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1903  *
1904  **/
1905 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1906 {
1907         struct ixgbe_hw *hw = &adapter->hw;
1908
1909         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1910                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
1911
1912         ixgbe_set_ivar(adapter, 0, 0, 0);
1913         ixgbe_set_ivar(adapter, 1, 0, 0);
1914
1915         map_vector_to_rxq(adapter, 0, 0);
1916         map_vector_to_txq(adapter, 0, 0);
1917
1918         DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1919 }
1920
1921 /**
1922  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1923  * @adapter: board private structure
1924  *
1925  * Configure the Tx unit of the MAC after a reset.
1926  **/
1927 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1928 {
1929         u64 tdba;
1930         struct ixgbe_hw *hw = &adapter->hw;
1931         u32 i, j, tdlen, txctrl;
1932
1933         /* Setup the HW Tx Head and Tail descriptor pointers */
1934         for (i = 0; i < adapter->num_tx_queues; i++) {
1935                 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1936                 j = ring->reg_idx;
1937                 tdba = ring->dma;
1938                 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1939                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1940                                 (tdba & DMA_BIT_MASK(32)));
1941                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1942                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1943                 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1944                 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1945                 adapter->tx_ring[i].head = IXGBE_TDH(j);
1946                 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1947                 /*
1948                  * Disable Tx Head Writeback RO bit, since this hoses
1949                  * bookkeeping if things aren't delivered in order.
1950                  */
1951                 switch (hw->mac.type) {
1952                 case ixgbe_mac_82598EB:
1953                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1954                         break;
1955                 case ixgbe_mac_82599EB:
1956                 default:
1957                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
1958                         break;
1959                 }
1960                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1961                 switch (hw->mac.type) {
1962                 case ixgbe_mac_82598EB:
1963                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1964                         break;
1965                 case ixgbe_mac_82599EB:
1966                 default:
1967                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
1968                         break;
1969                 }
1970         }
1971
1972         if (hw->mac.type == ixgbe_mac_82599EB) {
1973                 u32 rttdcs;
1974
1975                 /* disable the arbiter while setting MTQC */
1976                 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
1977                 rttdcs |= IXGBE_RTTDCS_ARBDIS;
1978                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
1979
1980                 /* We enable 8 traffic classes, DCB only */
1981                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1982                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1983                                         IXGBE_MTQC_8TC_8TQ));
1984                 else
1985                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
1986
1987                 /* re-eable the arbiter */
1988                 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
1989                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
1990         }
1991 }
1992
1993 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1994
1995 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
1996                                    struct ixgbe_ring *rx_ring)
1997 {
1998         u32 srrctl;
1999         int index;
2000         struct ixgbe_ring_feature *feature = adapter->ring_feature;
2001
2002         index = rx_ring->reg_idx;
2003         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2004                 unsigned long mask;
2005                 mask = (unsigned long) feature[RING_F_RSS].mask;
2006                 index = index & mask;
2007         }
2008         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2009
2010         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2011         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2012
2013         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2014                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2015
2016         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2017 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2018                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2019 #else
2020                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2021 #endif
2022                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2023         } else {
2024                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2025                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2026                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2027         }
2028
2029         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2030 }
2031
2032 static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2033 {
2034         u32 mrqc = 0;
2035         int mask;
2036
2037         if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
2038                 return mrqc;
2039
2040         mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2041 #ifdef CONFIG_IXGBE_DCB
2042                                  | IXGBE_FLAG_DCB_ENABLED
2043 #endif
2044                                 );
2045
2046         switch (mask) {
2047         case (IXGBE_FLAG_RSS_ENABLED):
2048                 mrqc = IXGBE_MRQC_RSSEN;
2049                 break;
2050 #ifdef CONFIG_IXGBE_DCB
2051         case (IXGBE_FLAG_DCB_ENABLED):
2052                 mrqc = IXGBE_MRQC_RT8TCEN;
2053                 break;
2054 #endif /* CONFIG_IXGBE_DCB */
2055         default:
2056                 break;
2057         }
2058
2059         return mrqc;
2060 }
2061
2062 /**
2063  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2064  * @adapter:    address of board private structure
2065  * @index:      index of ring to set
2066  * @rx_buf_len: rx buffer length
2067  **/
2068 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index,
2069                                    int rx_buf_len)
2070 {
2071         struct ixgbe_ring *rx_ring;
2072         struct ixgbe_hw *hw = &adapter->hw;
2073         int j;
2074         u32 rscctrl;
2075
2076         rx_ring = &adapter->rx_ring[index];
2077         j = rx_ring->reg_idx;
2078         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2079         rscctrl |= IXGBE_RSCCTL_RSCEN;
2080         /*
2081          * we must limit the number of descriptors so that the
2082          * total size of max desc * buf_len is not greater
2083          * than 65535
2084          */
2085         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2086 #if (MAX_SKB_FRAGS > 16)
2087                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2088 #elif (MAX_SKB_FRAGS > 8)
2089                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2090 #elif (MAX_SKB_FRAGS > 4)
2091                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2092 #else
2093                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2094 #endif
2095         } else {
2096                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2097                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2098                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2099                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2100                 else
2101                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2102         }
2103         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2104 }
2105
2106 /**
2107  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2108  * @adapter: board private structure
2109  *
2110  * Configure the Rx unit of the MAC after a reset.
2111  **/
2112 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2113 {
2114         u64 rdba;
2115         struct ixgbe_hw *hw = &adapter->hw;
2116         struct ixgbe_ring *rx_ring;
2117         struct net_device *netdev = adapter->netdev;
2118         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2119         int i, j;
2120         u32 rdlen, rxctrl, rxcsum;
2121         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2122                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2123                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2124         u32 fctrl, hlreg0;
2125         u32 reta = 0, mrqc = 0;
2126         u32 rdrxctl;
2127         int rx_buf_len;
2128
2129         /* Decide whether to use packet split mode or not */
2130         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2131
2132         /* Set the RX buffer length according to the mode */
2133         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2134                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2135                 if (hw->mac.type == ixgbe_mac_82599EB) {
2136                         /* PSRTYPE must be initialized in 82599 */
2137                         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2138                                       IXGBE_PSRTYPE_UDPHDR |
2139                                       IXGBE_PSRTYPE_IPV4HDR |
2140                                       IXGBE_PSRTYPE_IPV6HDR |
2141                                       IXGBE_PSRTYPE_L2HDR;
2142                         IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
2143                 }
2144         } else {
2145                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2146                     (netdev->mtu <= ETH_DATA_LEN))
2147                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2148                 else
2149                         rx_buf_len = ALIGN(max_frame, 1024);
2150         }
2151
2152         fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2153         fctrl |= IXGBE_FCTRL_BAM;
2154         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
2155         fctrl |= IXGBE_FCTRL_PMCF;
2156         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2157
2158         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2159         if (adapter->netdev->mtu <= ETH_DATA_LEN)
2160                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2161         else
2162                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2163 #ifdef IXGBE_FCOE
2164         if (netdev->features & NETIF_F_FCOE_MTU)
2165                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2166 #endif
2167         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2168
2169         rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
2170         /* disable receives while setting up the descriptors */
2171         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2172         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2173
2174         /*
2175          * Setup the HW Rx Head and Tail Descriptor Pointers and
2176          * the Base and Length of the Rx Descriptor Ring
2177          */
2178         for (i = 0; i < adapter->num_rx_queues; i++) {
2179                 rx_ring = &adapter->rx_ring[i];
2180                 rdba = rx_ring->dma;
2181                 j = rx_ring->reg_idx;
2182                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
2183                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2184                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2185                 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2186                 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
2187                 rx_ring->head = IXGBE_RDH(j);
2188                 rx_ring->tail = IXGBE_RDT(j);
2189                 rx_ring->rx_buf_len = rx_buf_len;
2190
2191                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2192                         rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2193                 else
2194                         rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2195
2196 #ifdef IXGBE_FCOE
2197                 if (netdev->features & NETIF_F_FCOE_MTU) {
2198                         struct ixgbe_ring_feature *f;
2199                         f = &adapter->ring_feature[RING_F_FCOE];
2200                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
2201                                 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2202                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2203                                         rx_ring->rx_buf_len =
2204                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2205                         }
2206                 }
2207
2208 #endif /* IXGBE_FCOE */
2209                 ixgbe_configure_srrctl(adapter, rx_ring);
2210         }
2211
2212         if (hw->mac.type == ixgbe_mac_82598EB) {
2213                 /*
2214                  * For VMDq support of different descriptor types or
2215                  * buffer sizes through the use of multiple SRRCTL
2216                  * registers, RDRXCTL.MVMEN must be set to 1
2217                  *
2218                  * also, the manual doesn't mention it clearly but DCA hints
2219                  * will only use queue 0's tags unless this bit is set.  Side
2220                  * effects of setting this bit are only that SRRCTL must be
2221                  * fully programmed [0..15]
2222                  */
2223                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2224                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2225                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2226         }
2227
2228         /* Program MRQC for the distribution of queues */
2229         mrqc = ixgbe_setup_mrqc(adapter);
2230
2231         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2232                 /* Fill out redirection table */
2233                 for (i = 0, j = 0; i < 128; i++, j++) {
2234                         if (j == adapter->ring_feature[RING_F_RSS].indices)
2235                                 j = 0;
2236                         /* reta = 4-byte sliding window of
2237                          * 0x00..(indices-1)(indices-1)00..etc. */
2238                         reta = (reta << 8) | (j * 0x11);
2239                         if ((i & 3) == 3)
2240                                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2241                 }
2242
2243                 /* Fill out hash function seeds */
2244                 for (i = 0; i < 10; i++)
2245                         IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2246
2247                 if (hw->mac.type == ixgbe_mac_82598EB)
2248                         mrqc |= IXGBE_MRQC_RSSEN;
2249                     /* Perform hash on these packet types */
2250                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2251                       | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2252                       | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2253                       | IXGBE_MRQC_RSS_FIELD_IPV6
2254                       | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2255                       | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2256         }
2257         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2258
2259         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2260
2261         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2262             adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2263                 /* Disable indicating checksum in descriptor, enables
2264                  * RSS hash */
2265                 rxcsum |= IXGBE_RXCSUM_PCSD;
2266         }
2267         if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2268                 /* Enable IPv4 payload checksum for UDP fragments
2269                  * if PCSD is not set */
2270                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2271         }
2272
2273         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2274
2275         if (hw->mac.type == ixgbe_mac_82599EB) {
2276                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2277                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2278                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2279                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2280         }
2281
2282         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2283                 /* Enable 82599 HW-RSC */
2284                 for (i = 0; i < adapter->num_rx_queues; i++)
2285                         ixgbe_configure_rscctl(adapter, i, rx_buf_len);
2286
2287                 /* Disable RSC for ACK packets */
2288                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2289                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2290         }
2291 }
2292
2293 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2294 {
2295         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2296         struct ixgbe_hw *hw = &adapter->hw;
2297
2298         /* add VID to filter table */
2299         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
2300 }
2301
2302 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2303 {
2304         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2305         struct ixgbe_hw *hw = &adapter->hw;
2306
2307         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2308                 ixgbe_irq_disable(adapter);
2309
2310         vlan_group_set_device(adapter->vlgrp, vid, NULL);
2311
2312         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2313                 ixgbe_irq_enable(adapter);
2314
2315         /* remove VID from filter table */
2316         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2317 }
2318
2319 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2320                                    struct vlan_group *grp)
2321 {
2322         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2323         u32 ctrl;
2324         int i, j;
2325
2326         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2327                 ixgbe_irq_disable(adapter);
2328         adapter->vlgrp = grp;
2329
2330         /*
2331          * For a DCB driver, always enable VLAN tag stripping so we can
2332          * still receive traffic from a DCB-enabled host even if we're
2333          * not in DCB mode.
2334          */
2335         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2336         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2337                 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2338                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2339                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2340         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2341                 ctrl |= IXGBE_VLNCTRL_VFE;
2342                 /* enable VLAN tag insert/strip */
2343                 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2344                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2345                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2346                 for (i = 0; i < adapter->num_rx_queues; i++) {
2347                         j = adapter->rx_ring[i].reg_idx;
2348                         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2349                         ctrl |= IXGBE_RXDCTL_VME;
2350                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2351                 }
2352         }
2353         ixgbe_vlan_rx_add_vid(netdev, 0);
2354
2355         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2356                 ixgbe_irq_enable(adapter);
2357 }
2358
2359 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2360 {
2361         ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2362
2363         if (adapter->vlgrp) {
2364                 u16 vid;
2365                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2366                         if (!vlan_group_get_device(adapter->vlgrp, vid))
2367                                 continue;
2368                         ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2369                 }
2370         }
2371 }
2372
2373 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2374 {
2375         struct dev_mc_list *mc_ptr;
2376         u8 *addr = *mc_addr_ptr;
2377         *vmdq = 0;
2378
2379         mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2380         if (mc_ptr->next)
2381                 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2382         else
2383                 *mc_addr_ptr = NULL;
2384
2385         return addr;
2386 }
2387
2388 /**
2389  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2390  * @netdev: network interface device structure
2391  *
2392  * The set_rx_method entry point is called whenever the unicast/multicast
2393  * address list or the network interface flags are updated.  This routine is
2394  * responsible for configuring the hardware for proper unicast, multicast and
2395  * promiscuous mode.
2396  **/
2397 static void ixgbe_set_rx_mode(struct net_device *netdev)
2398 {
2399         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2400         struct ixgbe_hw *hw = &adapter->hw;
2401         u32 fctrl, vlnctrl;
2402         u8 *addr_list = NULL;
2403         int addr_count = 0;
2404
2405         /* Check for Promiscuous and All Multicast modes */
2406
2407         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2408         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2409
2410         if (netdev->flags & IFF_PROMISC) {
2411                 hw->addr_ctrl.user_set_promisc = 1;
2412                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2413                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2414         } else {
2415                 if (netdev->flags & IFF_ALLMULTI) {
2416                         fctrl |= IXGBE_FCTRL_MPE;
2417                         fctrl &= ~IXGBE_FCTRL_UPE;
2418                 } else {
2419                         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2420                 }
2421                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2422                 hw->addr_ctrl.user_set_promisc = 0;
2423         }
2424
2425         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2426         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2427
2428         /* reprogram secondary unicast list */
2429         hw->mac.ops.update_uc_addr_list(hw, &netdev->uc.list);
2430
2431         /* reprogram multicast list */
2432         addr_count = netdev->mc_count;
2433         if (addr_count)
2434                 addr_list = netdev->mc_list->dmi_addr;
2435         hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2436                                         ixgbe_addr_list_itr);
2437 }
2438
2439 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2440 {
2441         int q_idx;
2442         struct ixgbe_q_vector *q_vector;
2443         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2444
2445         /* legacy and MSI only use one vector */
2446         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2447                 q_vectors = 1;
2448
2449         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2450                 struct napi_struct *napi;
2451                 q_vector = adapter->q_vector[q_idx];
2452                 napi = &q_vector->napi;
2453                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2454                         if (!q_vector->rxr_count || !q_vector->txr_count) {
2455                                 if (q_vector->txr_count == 1)
2456                                         napi->poll = &ixgbe_clean_txonly;
2457                                 else if (q_vector->rxr_count == 1)
2458                                         napi->poll = &ixgbe_clean_rxonly;
2459                         }
2460                 }
2461
2462                 napi_enable(napi);
2463         }
2464 }
2465
2466 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2467 {
2468         int q_idx;
2469         struct ixgbe_q_vector *q_vector;
2470         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2471
2472         /* legacy and MSI only use one vector */
2473         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2474                 q_vectors = 1;
2475
2476         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2477                 q_vector = adapter->q_vector[q_idx];
2478                 napi_disable(&q_vector->napi);
2479         }
2480 }
2481
2482 #ifdef CONFIG_IXGBE_DCB
2483 /*
2484  * ixgbe_configure_dcb - Configure DCB hardware
2485  * @adapter: ixgbe adapter struct
2486  *
2487  * This is called by the driver on open to configure the DCB hardware.
2488  * This is also called by the gennetlink interface when reconfiguring
2489  * the DCB state.
2490  */
2491 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2492 {
2493         struct ixgbe_hw *hw = &adapter->hw;
2494         u32 txdctl, vlnctrl;
2495         int i, j;
2496
2497         ixgbe_dcb_check_config(&adapter->dcb_cfg);
2498         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2499         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2500
2501         /* reconfigure the hardware */
2502         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2503
2504         for (i = 0; i < adapter->num_tx_queues; i++) {
2505                 j = adapter->tx_ring[i].reg_idx;
2506                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2507                 /* PThresh workaround for Tx hang with DFP enabled. */
2508                 txdctl |= 32;
2509                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2510         }
2511         /* Enable VLAN tag insert/strip */
2512         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2513         if (hw->mac.type == ixgbe_mac_82598EB) {
2514                 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2515                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2516                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2517         } else if (hw->mac.type == ixgbe_mac_82599EB) {
2518                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2519                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2520                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2521                 for (i = 0; i < adapter->num_rx_queues; i++) {
2522                         j = adapter->rx_ring[i].reg_idx;
2523                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2524                         vlnctrl |= IXGBE_RXDCTL_VME;
2525                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2526                 }
2527         }
2528         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2529 }
2530
2531 #endif
2532 static void ixgbe_configure(struct ixgbe_adapter *adapter)
2533 {
2534         struct net_device *netdev = adapter->netdev;
2535         struct ixgbe_hw *hw = &adapter->hw;
2536         int i;
2537
2538         ixgbe_set_rx_mode(netdev);
2539
2540         ixgbe_restore_vlan(adapter);
2541 #ifdef CONFIG_IXGBE_DCB
2542         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2543                 if (hw->mac.type == ixgbe_mac_82598EB)
2544                         netif_set_gso_max_size(netdev, 32768);
2545                 else
2546                         netif_set_gso_max_size(netdev, 65536);
2547                 ixgbe_configure_dcb(adapter);
2548         } else {
2549                 netif_set_gso_max_size(netdev, 65536);
2550         }
2551 #else
2552         netif_set_gso_max_size(netdev, 65536);
2553 #endif
2554
2555 #ifdef IXGBE_FCOE
2556         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2557                 ixgbe_configure_fcoe(adapter);
2558
2559 #endif /* IXGBE_FCOE */
2560         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2561                 for (i = 0; i < adapter->num_tx_queues; i++)
2562                         adapter->tx_ring[i].atr_sample_rate =
2563                                                        adapter->atr_sample_rate;
2564                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2565         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2566                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2567         }
2568
2569         ixgbe_configure_tx(adapter);
2570         ixgbe_configure_rx(adapter);
2571         for (i = 0; i < adapter->num_rx_queues; i++)
2572                 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
2573                                        (adapter->rx_ring[i].count - 1));
2574 }
2575
2576 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2577 {
2578         switch (hw->phy.type) {
2579         case ixgbe_phy_sfp_avago:
2580         case ixgbe_phy_sfp_ftl:
2581         case ixgbe_phy_sfp_intel:
2582         case ixgbe_phy_sfp_unknown:
2583         case ixgbe_phy_tw_tyco:
2584         case ixgbe_phy_tw_unknown:
2585                 return true;
2586         default:
2587                 return false;
2588         }
2589 }
2590
2591 /**
2592  * ixgbe_sfp_link_config - set up SFP+ link
2593  * @adapter: pointer to private adapter struct
2594  **/
2595 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2596 {
2597         struct ixgbe_hw *hw = &adapter->hw;
2598
2599                 if (hw->phy.multispeed_fiber) {
2600                         /*
2601                          * In multispeed fiber setups, the device may not have
2602                          * had a physical connection when the driver loaded.
2603                          * If that's the case, the initial link configuration
2604                          * couldn't get the MAC into 10G or 1G mode, so we'll
2605                          * never have a link status change interrupt fire.
2606                          * We need to try and force an autonegotiation
2607                          * session, then bring up link.
2608                          */
2609                         hw->mac.ops.setup_sfp(hw);
2610                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2611                                 schedule_work(&adapter->multispeed_fiber_task);
2612                 } else {
2613                         /*
2614                          * Direct Attach Cu and non-multispeed fiber modules
2615                          * still need to be configured properly prior to
2616                          * attempting link.
2617                          */
2618                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2619                                 schedule_work(&adapter->sfp_config_module_task);
2620                 }
2621 }
2622
2623 /**
2624  * ixgbe_non_sfp_link_config - set up non-SFP+ link
2625  * @hw: pointer to private hardware struct
2626  *
2627  * Returns 0 on success, negative on failure
2628  **/
2629 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
2630 {
2631         u32 autoneg;
2632         bool negotiation, link_up = false;
2633         u32 ret = IXGBE_ERR_LINK_SETUP;
2634
2635         if (hw->mac.ops.check_link)
2636                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2637
2638         if (ret)
2639                 goto link_cfg_out;
2640
2641         if (hw->mac.ops.get_link_capabilities)
2642                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
2643         if (ret)
2644                 goto link_cfg_out;
2645
2646         if (hw->mac.ops.setup_link)
2647                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
2648 link_cfg_out:
2649         return ret;
2650 }
2651
2652 #define IXGBE_MAX_RX_DESC_POLL 10
2653 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2654                                               int rxr)
2655 {
2656         int j = adapter->rx_ring[rxr].reg_idx;
2657         int k;
2658
2659         for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2660                 if (IXGBE_READ_REG(&adapter->hw,
2661                                    IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2662                         break;
2663                 else
2664                         msleep(1);
2665         }
2666         if (k >= IXGBE_MAX_RX_DESC_POLL) {
2667                 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2668                         "not set within the polling period\n", rxr);
2669         }
2670         ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2671                               (adapter->rx_ring[rxr].count - 1));
2672 }
2673
2674 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2675 {
2676         struct net_device *netdev = adapter->netdev;
2677         struct ixgbe_hw *hw = &adapter->hw;
2678         int i, j = 0;
2679         int num_rx_rings = adapter->num_rx_queues;
2680         int err;
2681         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2682         u32 txdctl, rxdctl, mhadd;
2683         u32 dmatxctl;
2684         u32 gpie;
2685
2686         ixgbe_get_hw_control(adapter);
2687
2688         if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2689             (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
2690                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2691                         gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
2692                                 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
2693                 } else {
2694                         /* MSI only */
2695                         gpie = 0;
2696                 }
2697                 /* XXX: to interrupt immediately for EICS writes, enable this */
2698                 /* gpie |= IXGBE_GPIE_EIMEN; */
2699                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2700         }
2701
2702         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2703                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2704                  * specifically only auto mask tx and rx interrupts */
2705                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2706         }
2707
2708         /* Enable fan failure interrupt if media type is copper */
2709         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2710                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2711                 gpie |= IXGBE_SDP1_GPIEN;
2712                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2713         }
2714
2715         if (hw->mac.type == ixgbe_mac_82599EB) {
2716                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2717                 gpie |= IXGBE_SDP1_GPIEN;
2718                 gpie |= IXGBE_SDP2_GPIEN;
2719                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2720         }
2721
2722 #ifdef IXGBE_FCOE
2723         /* adjust max frame to be able to do baby jumbo for FCoE */
2724         if ((netdev->features & NETIF_F_FCOE_MTU) &&
2725             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2726                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2727
2728 #endif /* IXGBE_FCOE */
2729         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2730         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2731                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2732                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2733
2734                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2735         }
2736
2737         for (i = 0; i < adapter->num_tx_queues; i++) {
2738                 j = adapter->tx_ring[i].reg_idx;
2739                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2740                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2741                 txdctl |= (8 << 16);
2742                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2743         }
2744
2745         if (hw->mac.type == ixgbe_mac_82599EB) {
2746                 /* DMATXCTL.EN must be set after all Tx queue config is done */
2747                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2748                 dmatxctl |= IXGBE_DMATXCTL_TE;
2749                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2750         }
2751         for (i = 0; i < adapter->num_tx_queues; i++) {
2752                 j = adapter->tx_ring[i].reg_idx;
2753                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2754                 txdctl |= IXGBE_TXDCTL_ENABLE;
2755                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2756         }
2757
2758         for (i = 0; i < num_rx_rings; i++) {
2759                 j = adapter->rx_ring[i].reg_idx;
2760                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2761                 /* enable PTHRESH=32 descriptors (half the internal cache)
2762                  * and HTHRESH=0 descriptors (to minimize latency on fetch),
2763                  * this also removes a pesky rx_no_buffer_count increment */
2764                 rxdctl |= 0x0020;
2765                 rxdctl |= IXGBE_RXDCTL_ENABLE;
2766                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2767                 if (hw->mac.type == ixgbe_mac_82599EB)
2768                         ixgbe_rx_desc_queue_enable(adapter, i);
2769         }
2770         /* enable all receives */
2771         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2772         if (hw->mac.type == ixgbe_mac_82598EB)
2773                 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2774         else
2775                 rxdctl |= IXGBE_RXCTRL_RXEN;
2776         hw->mac.ops.enable_rx_dma(hw, rxdctl);
2777
2778         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2779                 ixgbe_configure_msix(adapter);
2780         else
2781                 ixgbe_configure_msi_and_legacy(adapter);
2782
2783         clear_bit(__IXGBE_DOWN, &adapter->state);
2784         ixgbe_napi_enable_all(adapter);
2785
2786         /* clear any pending interrupts, may auto mask */
2787         IXGBE_READ_REG(hw, IXGBE_EICR);
2788
2789         ixgbe_irq_enable(adapter);
2790
2791         /*
2792          * If this adapter has a fan, check to see if we had a failure
2793          * before we enabled the interrupt.
2794          */
2795         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2796                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2797                 if (esdp & IXGBE_ESDP_SDP1)
2798                         DPRINTK(DRV, CRIT,
2799                                 "Fan has stopped, replace the adapter\n");
2800         }
2801
2802         /*
2803          * For hot-pluggable SFP+ devices, a new SFP+ module may have
2804          * arrived before interrupts were enabled but after probe.  Such
2805          * devices wouldn't have their type identified yet. We need to
2806          * kick off the SFP+ module setup first, then try to bring up link.
2807          * If we're not hot-pluggable SFP+, we just need to configure link
2808          * and bring it up.
2809          */
2810         if (hw->phy.type == ixgbe_phy_unknown) {
2811                 err = hw->phy.ops.identify(hw);
2812                 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2813                         /*
2814                          * Take the device down and schedule the sfp tasklet
2815                          * which will unregister_netdev and log it.
2816                          */
2817                         ixgbe_down(adapter);
2818                         schedule_work(&adapter->sfp_config_module_task);
2819                         return err;
2820                 }
2821         }
2822
2823         if (ixgbe_is_sfp(hw)) {
2824                 ixgbe_sfp_link_config(adapter);
2825         } else {
2826                 err = ixgbe_non_sfp_link_config(hw);
2827                 if (err)
2828                         DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2829         }
2830
2831         for (i = 0; i < adapter->num_tx_queues; i++)
2832                 set_bit(__IXGBE_FDIR_INIT_DONE,
2833                         &(adapter->tx_ring[i].reinit_state));
2834
2835         /* enable transmits */
2836         netif_tx_start_all_queues(netdev);
2837
2838         /* bring the link up in the watchdog, this could race with our first
2839          * link up interrupt but shouldn't be a problem */
2840         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2841         adapter->link_check_timeout = jiffies;
2842         mod_timer(&adapter->watchdog_timer, jiffies);
2843         return 0;
2844 }
2845
2846 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2847 {
2848         WARN_ON(in_interrupt());
2849         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2850                 msleep(1);
2851         ixgbe_down(adapter);
2852         ixgbe_up(adapter);
2853         clear_bit(__IXGBE_RESETTING, &adapter->state);
2854 }
2855
2856 int ixgbe_up(struct ixgbe_adapter *adapter)
2857 {
2858         /* hardware has been reset, we need to reload some things */
2859         ixgbe_configure(adapter);
2860
2861         return ixgbe_up_complete(adapter);
2862 }
2863
2864 void ixgbe_reset(struct ixgbe_adapter *adapter)
2865 {
2866         struct ixgbe_hw *hw = &adapter->hw;
2867         int err;
2868
2869         err = hw->mac.ops.init_hw(hw);
2870         switch (err) {
2871         case 0:
2872         case IXGBE_ERR_SFP_NOT_PRESENT:
2873                 break;
2874         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
2875                 dev_err(&adapter->pdev->dev, "master disable timed out\n");
2876                 break;
2877         case IXGBE_ERR_EEPROM_VERSION:
2878                 /* We are running on a pre-production device, log a warning */
2879                 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
2880                          "adapter/LOM.  Please be aware there may be issues "
2881                          "associated with your hardware.  If you are "
2882                          "experiencing problems please contact your Intel or "
2883                          "hardware representative who provided you with this "
2884                          "hardware.\n");
2885                 break;
2886         default:
2887                 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
2888         }
2889
2890         /* reprogram the RAR[0] in case user changed it. */
2891         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2892 }
2893
2894 /**
2895  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2896  * @adapter: board private structure
2897  * @rx_ring: ring to free buffers from
2898  **/
2899 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
2900                                 struct ixgbe_ring *rx_ring)
2901 {
2902         struct pci_dev *pdev = adapter->pdev;
2903         unsigned long size;
2904         unsigned int i;
2905
2906         /* Free all the Rx ring sk_buffs */
2907
2908         for (i = 0; i < rx_ring->count; i++) {
2909                 struct ixgbe_rx_buffer *rx_buffer_info;
2910
2911                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2912                 if (rx_buffer_info->dma) {
2913                         pci_unmap_single(pdev, rx_buffer_info->dma,
2914                                          rx_ring->rx_buf_len,
2915                                          PCI_DMA_FROMDEVICE);
2916                         rx_buffer_info->dma = 0;
2917                 }
2918                 if (rx_buffer_info->skb) {
2919                         struct sk_buff *skb = rx_buffer_info->skb;
2920                         rx_buffer_info->skb = NULL;
2921                         do {
2922                                 struct sk_buff *this = skb;
2923                                 skb = skb->prev;
2924                                 dev_kfree_skb(this);
2925                         } while (skb);
2926                 }
2927                 if (!rx_buffer_info->page)
2928                         continue;
2929                 if (rx_buffer_info->page_dma) {
2930                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
2931                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
2932                         rx_buffer_info->page_dma = 0;
2933                 }
2934                 put_page(rx_buffer_info->page);
2935                 rx_buffer_info->page = NULL;
2936                 rx_buffer_info->page_offset = 0;
2937         }
2938
2939         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2940         memset(rx_ring->rx_buffer_info, 0, size);
2941
2942         /* Zero out the descriptor ring */
2943         memset(rx_ring->desc, 0, rx_ring->size);
2944
2945         rx_ring->next_to_clean = 0;
2946         rx_ring->next_to_use = 0;
2947
2948         if (rx_ring->head)
2949                 writel(0, adapter->hw.hw_addr + rx_ring->head);
2950         if (rx_ring->tail)
2951                 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2952 }
2953
2954 /**
2955  * ixgbe_clean_tx_ring - Free Tx Buffers
2956  * @adapter: board private structure
2957  * @tx_ring: ring to be cleaned
2958  **/
2959 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
2960                                 struct ixgbe_ring *tx_ring)
2961 {
2962         struct ixgbe_tx_buffer *tx_buffer_info;
2963         unsigned long size;
2964         unsigned int i;
2965
2966         /* Free all the Tx ring sk_buffs */
2967
2968         for (i = 0; i < tx_ring->count; i++) {
2969                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2970                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2971         }
2972
2973         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2974         memset(tx_ring->tx_buffer_info, 0, size);
2975
2976         /* Zero out the descriptor ring */
2977         memset(tx_ring->desc, 0, tx_ring->size);
2978
2979         tx_ring->next_to_use = 0;
2980         tx_ring->next_to_clean = 0;
2981
2982         if (tx_ring->head)
2983                 writel(0, adapter->hw.hw_addr + tx_ring->head);
2984         if (tx_ring->tail)
2985                 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2986 }
2987
2988 /**
2989  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
2990  * @adapter: board private structure
2991  **/
2992 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
2993 {
2994         int i;
2995
2996         for (i = 0; i < adapter->num_rx_queues; i++)
2997                 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
2998 }
2999
3000 /**
3001  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3002  * @adapter: board private structure
3003  **/
3004 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3005 {
3006         int i;
3007
3008         for (i = 0; i < adapter->num_tx_queues; i++)
3009                 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
3010 }
3011
3012 void ixgbe_down(struct ixgbe_adapter *adapter)
3013 {
3014         struct net_device *netdev = adapter->netdev;
3015         struct ixgbe_hw *hw = &adapter->hw;
3016         u32 rxctrl;
3017         u32 txdctl;
3018         int i, j;
3019
3020         /* signal that we are down to the interrupt handler */
3021         set_bit(__IXGBE_DOWN, &adapter->state);
3022
3023         /* disable receives */
3024         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3025         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3026
3027         netif_tx_disable(netdev);
3028
3029         IXGBE_WRITE_FLUSH(hw);
3030         msleep(10);
3031
3032         netif_tx_stop_all_queues(netdev);
3033
3034         ixgbe_irq_disable(adapter);
3035
3036         ixgbe_napi_disable_all(adapter);
3037
3038         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3039         del_timer_sync(&adapter->sfp_timer);
3040         del_timer_sync(&adapter->watchdog_timer);
3041         cancel_work_sync(&adapter->watchdog_task);
3042
3043         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3044             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3045                 cancel_work_sync(&adapter->fdir_reinit_task);
3046
3047         /* disable transmits in the hardware now that interrupts are off */
3048         for (i = 0; i < adapter->num_tx_queues; i++) {
3049                 j = adapter->tx_ring[i].reg_idx;
3050                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3051                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3052                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3053         }
3054         /* Disable the Tx DMA engine on 82599 */
3055         if (hw->mac.type == ixgbe_mac_82599EB)
3056                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3057                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3058                                  ~IXGBE_DMATXCTL_TE));
3059
3060         netif_carrier_off(netdev);
3061
3062         if (!pci_channel_offline(adapter->pdev))
3063                 ixgbe_reset(adapter);
3064         ixgbe_clean_all_tx_rings(adapter);
3065         ixgbe_clean_all_rx_rings(adapter);
3066
3067 #ifdef CONFIG_IXGBE_DCA
3068         /* since we reset the hardware DCA settings were cleared */
3069         ixgbe_setup_dca(adapter);
3070 #endif
3071 }
3072
3073 /**
3074  * ixgbe_poll - NAPI Rx polling callback
3075  * @napi: structure for representing this polling device
3076  * @budget: how many packets driver is allowed to clean
3077  *
3078  * This function is used for legacy and MSI, NAPI mode
3079  **/
3080 static int ixgbe_poll(struct napi_struct *napi, int budget)
3081 {
3082         struct ixgbe_q_vector *q_vector =
3083                                 container_of(napi, struct ixgbe_q_vector, napi);
3084         struct ixgbe_adapter *adapter = q_vector->adapter;
3085         int tx_clean_complete, work_done = 0;
3086
3087 #ifdef CONFIG_IXGBE_DCA
3088         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3089                 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
3090                 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
3091         }
3092 #endif
3093
3094         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring);
3095         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
3096
3097         if (!tx_clean_complete)
3098                 work_done = budget;
3099
3100         /* If budget not fully consumed, exit the polling mode */
3101         if (work_done < budget) {
3102                 napi_complete(napi);
3103                 if (adapter->rx_itr_setting & 1)
3104                         ixgbe_set_itr(adapter);
3105                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3106                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3107         }
3108         return work_done;
3109 }
3110
3111 /**
3112  * ixgbe_tx_timeout - Respond to a Tx Hang
3113  * @netdev: network interface device structure
3114  **/
3115 static void ixgbe_tx_timeout(struct net_device *netdev)
3116 {
3117         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3118
3119         /* Do the reset outside of interrupt context */
3120         schedule_work(&adapter->reset_task);
3121 }
3122
3123 static void ixgbe_reset_task(struct work_struct *work)
3124 {
3125         struct ixgbe_adapter *adapter;
3126         adapter = container_of(work, struct ixgbe_adapter, reset_task);
3127
3128         /* If we're already down or resetting, just bail */
3129         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3130             test_bit(__IXGBE_RESETTING, &adapter->state))
3131                 return;
3132
3133         adapter->tx_timeout_count++;
3134
3135         ixgbe_reinit_locked(adapter);
3136 }
3137
3138 #ifdef CONFIG_IXGBE_DCB
3139 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3140 {
3141         bool ret = false;
3142         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3143
3144         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3145                 return ret;
3146
3147         f->mask = 0x7 << 3;
3148         adapter->num_rx_queues = f->indices;
3149         adapter->num_tx_queues = f->indices;
3150         ret = true;
3151
3152         return ret;
3153 }
3154 #endif
3155
3156 /**
3157  * ixgbe_set_rss_queues: Allocate queues for RSS
3158  * @adapter: board private structure to initialize
3159  *
3160  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
3161  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3162  *
3163  **/
3164 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3165 {
3166         bool ret = false;
3167         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3168
3169         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3170                 f->mask = 0xF;
3171                 adapter->num_rx_queues = f->indices;
3172                 adapter->num_tx_queues = f->indices;
3173                 ret = true;
3174         } else {
3175                 ret = false;
3176         }
3177
3178         return ret;
3179 }
3180
3181 /**
3182  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3183  * @adapter: board private structure to initialize
3184  *
3185  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3186  * to the original CPU that initiated the Tx session.  This runs in addition
3187  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3188  * Rx load across CPUs using RSS.
3189  *
3190  **/
3191 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3192 {
3193         bool ret = false;
3194         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3195
3196         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3197         f_fdir->mask = 0;
3198
3199         /* Flow Director must have RSS enabled */
3200         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3201             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3202              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3203                 adapter->num_tx_queues = f_fdir->indices;
3204                 adapter->num_rx_queues = f_fdir->indices;
3205                 ret = true;
3206         } else {
3207                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3208                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3209         }
3210         return ret;
3211 }
3212
3213 #ifdef IXGBE_FCOE
3214 /**
3215  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3216  * @adapter: board private structure to initialize
3217  *
3218  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3219  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3220  * rx queues out of the max number of rx queues, instead, it is used as the
3221  * index of the first rx queue used by FCoE.
3222  *
3223  **/
3224 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3225 {
3226         bool ret = false;
3227         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3228
3229         f->indices = min((int)num_online_cpus(), f->indices);
3230         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3231                 adapter->num_rx_queues = 1;
3232                 adapter->num_tx_queues = 1;
3233 #ifdef CONFIG_IXGBE_DCB
3234                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3235                         DPRINTK(PROBE, INFO, "FCoE enabled with DCB \n");
3236                         ixgbe_set_dcb_queues(adapter);
3237                 }
3238 #endif
3239                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3240                         DPRINTK(PROBE, INFO, "FCoE enabled with RSS \n");
3241                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3242                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3243                                 ixgbe_set_fdir_queues(adapter);
3244                         else
3245                                 ixgbe_set_rss_queues(adapter);
3246                 }
3247                 /* adding FCoE rx rings to the end */
3248                 f->mask = adapter->num_rx_queues;
3249                 adapter->num_rx_queues += f->indices;
3250                 adapter->num_tx_queues += f->indices;
3251
3252                 ret = true;
3253         }
3254
3255         return ret;
3256 }
3257
3258 #endif /* IXGBE_FCOE */
3259 /*
3260  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3261  * @adapter: board private structure to initialize
3262  *
3263  * This is the top level queue allocation routine.  The order here is very
3264  * important, starting with the "most" number of features turned on at once,
3265  * and ending with the smallest set of features.  This way large combinations
3266  * can be allocated if they're turned on, and smaller combinations are the
3267  * fallthrough conditions.
3268  *
3269  **/
3270 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3271 {
3272 #ifdef IXGBE_FCOE
3273         if (ixgbe_set_fcoe_queues(adapter))
3274                 goto done;
3275
3276 #endif /* IXGBE_FCOE */
3277 #ifdef CONFIG_IXGBE_DCB
3278         if (ixgbe_set_dcb_queues(adapter))
3279                 goto done;
3280
3281 #endif
3282         if (ixgbe_set_fdir_queues(adapter))
3283                 goto done;
3284
3285         if (ixgbe_set_rss_queues(adapter))
3286                 goto done;
3287
3288         /* fallback to base case */
3289         adapter->num_rx_queues = 1;
3290         adapter->num_tx_queues = 1;
3291
3292 done:
3293         /* Notify the stack of the (possibly) reduced Tx Queue count. */
3294         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
3295 }
3296
3297 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
3298                                        int vectors)
3299 {
3300         int err, vector_threshold;
3301
3302         /* We'll want at least 3 (vector_threshold):
3303          * 1) TxQ[0] Cleanup
3304          * 2) RxQ[0] Cleanup
3305          * 3) Other (Link Status Change, etc.)
3306          * 4) TCP Timer (optional)
3307          */
3308         vector_threshold = MIN_MSIX_COUNT;
3309
3310         /* The more we get, the more we will assign to Tx/Rx Cleanup
3311          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3312          * Right now, we simply care about how many we'll get; we'll
3313          * set them up later while requesting irq's.
3314          */
3315         while (vectors >= vector_threshold) {
3316                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
3317                                       vectors);
3318                 if (!err) /* Success in acquiring all requested vectors. */
3319                         break;
3320                 else if (err < 0)
3321                         vectors = 0; /* Nasty failure, quit now */
3322                 else /* err == number of vectors we should try again with */
3323                         vectors = err;
3324         }
3325
3326         if (vectors < vector_threshold) {
3327                 /* Can't allocate enough MSI-X interrupts?  Oh well.
3328                  * This just means we'll go with either a single MSI
3329                  * vector or fall back to legacy interrupts.
3330                  */
3331                 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3332                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3333                 kfree(adapter->msix_entries);
3334                 adapter->msix_entries = NULL;
3335         } else {
3336                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
3337                 /*
3338                  * Adjust for only the vectors we'll use, which is minimum
3339                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3340                  * vectors we were allocated.
3341                  */
3342                 adapter->num_msix_vectors = min(vectors,
3343                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
3344         }
3345 }
3346
3347 /**
3348  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
3349  * @adapter: board private structure to initialize
3350  *
3351  * Cache the descriptor ring offsets for RSS to the assigned rings.
3352  *
3353  **/
3354 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
3355 {
3356         int i;
3357         bool ret = false;
3358
3359         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3360                 for (i = 0; i < adapter->num_rx_queues; i++)
3361                         adapter->rx_ring[i].reg_idx = i;
3362                 for (i = 0; i < adapter->num_tx_queues; i++)
3363                         adapter->tx_ring[i].reg_idx = i;
3364                 ret = true;
3365         } else {
3366                 ret = false;
3367         }
3368
3369         return ret;
3370 }
3371
3372 #ifdef CONFIG_IXGBE_DCB
3373 /**
3374  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3375  * @adapter: board private structure to initialize
3376  *
3377  * Cache the descriptor ring offsets for DCB to the assigned rings.
3378  *
3379  **/
3380 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3381 {
3382         int i;
3383         bool ret = false;
3384         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3385
3386         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3387                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3388                         /* the number of queues is assumed to be symmetric */
3389                         for (i = 0; i < dcb_i; i++) {
3390                                 adapter->rx_ring[i].reg_idx = i << 3;
3391                                 adapter->tx_ring[i].reg_idx = i << 2;
3392                         }
3393                         ret = true;
3394                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
3395                         if (dcb_i == 8) {
3396                                 /*
3397                                  * Tx TC0 starts at: descriptor queue 0
3398                                  * Tx TC1 starts at: descriptor queue 32
3399                                  * Tx TC2 starts at: descriptor queue 64
3400                                  * Tx TC3 starts at: descriptor queue 80
3401                                  * Tx TC4 starts at: descriptor queue 96
3402                                  * Tx TC5 starts at: descriptor queue 104
3403                                  * Tx TC6 starts at: descriptor queue 112
3404                                  * Tx TC7 starts at: descriptor queue 120
3405                                  *
3406                                  * Rx TC0-TC7 are offset by 16 queues each
3407                                  */
3408                                 for (i = 0; i < 3; i++) {
3409                                         adapter->tx_ring[i].reg_idx = i << 5;
3410                                         adapter->rx_ring[i].reg_idx = i << 4;
3411                                 }
3412                                 for ( ; i < 5; i++) {
3413                                         adapter->tx_ring[i].reg_idx =
3414                                                                  ((i + 2) << 4);
3415                                         adapter->rx_ring[i].reg_idx = i << 4;
3416                                 }
3417                                 for ( ; i < dcb_i; i++) {
3418                                         adapter->tx_ring[i].reg_idx =
3419                                                                  ((i + 8) << 3);
3420                                         adapter->rx_ring[i].reg_idx = i << 4;
3421                                 }
3422
3423                                 ret = true;
3424                         } else if (dcb_i == 4) {
3425                                 /*
3426                                  * Tx TC0 starts at: descriptor queue 0
3427                                  * Tx TC1 starts at: descriptor queue 64
3428                                  * Tx TC2 starts at: descriptor queue 96
3429                                  * Tx TC3 starts at: descriptor queue 112
3430                                  *
3431                                  * Rx TC0-TC3 are offset by 32 queues each
3432                                  */
3433                                 adapter->tx_ring[0].reg_idx = 0;
3434                                 adapter->tx_ring[1].reg_idx = 64;
3435                                 adapter->tx_ring[2].reg_idx = 96;
3436                                 adapter->tx_ring[3].reg_idx = 112;
3437                                 for (i = 0 ; i < dcb_i; i++)
3438                                         adapter->rx_ring[i].reg_idx = i << 5;
3439
3440                                 ret = true;
3441                         } else {
3442                                 ret = false;
3443                         }
3444                 } else {
3445                         ret = false;
3446                 }
3447         } else {
3448                 ret = false;
3449         }
3450
3451         return ret;
3452 }
3453 #endif
3454
3455 /**
3456  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3457  * @adapter: board private structure to initialize
3458  *
3459  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3460  *
3461  **/
3462 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3463 {
3464         int i;
3465         bool ret = false;
3466
3467         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3468             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3469              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3470                 for (i = 0; i < adapter->num_rx_queues; i++)
3471                         adapter->rx_ring[i].reg_idx = i;
3472                 for (i = 0; i < adapter->num_tx_queues; i++)
3473                         adapter->tx_ring[i].reg_idx = i;
3474                 ret = true;
3475         }
3476
3477         return ret;
3478 }
3479
3480 #ifdef IXGBE_FCOE
3481 /**
3482  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3483  * @adapter: board private structure to initialize
3484  *
3485  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3486  *
3487  */
3488 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3489 {
3490         int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
3491         bool ret = false;
3492         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3493
3494         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3495 #ifdef CONFIG_IXGBE_DCB
3496                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3497                         struct ixgbe_fcoe *fcoe = &adapter->fcoe;
3498
3499                         ixgbe_cache_ring_dcb(adapter);
3500                         /* find out queues in TC for FCoE */
3501                         fcoe_rx_i = adapter->rx_ring[fcoe->tc].reg_idx + 1;
3502                         fcoe_tx_i = adapter->tx_ring[fcoe->tc].reg_idx + 1;
3503                         /*
3504                          * In 82599, the number of Tx queues for each traffic
3505                          * class for both 8-TC and 4-TC modes are:
3506                          * TCs  : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
3507                          * 8 TCs:  32  32  16  16   8   8   8   8
3508                          * 4 TCs:  64  64  32  32
3509                          * We have max 8 queues for FCoE, where 8 the is
3510                          * FCoE redirection table size. If TC for FCoE is
3511                          * less than or equal to TC3, we have enough queues
3512                          * to add max of 8 queues for FCoE, so we start FCoE
3513                          * tx descriptor from the next one, i.e., reg_idx + 1.
3514                          * If TC for FCoE is above TC3, implying 8 TC mode,
3515                          * and we need 8 for FCoE, we have to take all queues
3516                          * in that traffic class for FCoE.
3517                          */
3518                         if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
3519                                 fcoe_tx_i--;
3520                 }
3521 #endif /* CONFIG_IXGBE_DCB */
3522                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3523                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3524                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3525                                 ixgbe_cache_ring_fdir(adapter);
3526                         else
3527                                 ixgbe_cache_ring_rss(adapter);
3528
3529                         fcoe_rx_i = f->mask;
3530                         fcoe_tx_i = f->mask;
3531                 }
3532                 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
3533                         adapter->rx_ring[f->mask + i].reg_idx = fcoe_rx_i;
3534                         adapter->tx_ring[f->mask + i].reg_idx = fcoe_tx_i;
3535                 }
3536                 ret = true;
3537         }
3538         return ret;
3539 }
3540
3541 #endif /* IXGBE_FCOE */
3542 /**
3543  * ixgbe_cache_ring_register - Descriptor ring to register mapping
3544  * @adapter: board private structure to initialize
3545  *
3546  * Once we know the feature-set enabled for the device, we'll cache
3547  * the register offset the descriptor ring is assigned to.
3548  *
3549  * Note, the order the various feature calls is important.  It must start with
3550  * the "most" features enabled at the same time, then trickle down to the
3551  * least amount of features turned on at once.
3552  **/
3553 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3554 {
3555         /* start with default case */
3556         adapter->rx_ring[0].reg_idx = 0;
3557         adapter->tx_ring[0].reg_idx = 0;
3558
3559 #ifdef IXGBE_FCOE
3560         if (ixgbe_cache_ring_fcoe(adapter))
3561                 return;
3562
3563 #endif /* IXGBE_FCOE */
3564 #ifdef CONFIG_IXGBE_DCB
3565         if (ixgbe_cache_ring_dcb(adapter))
3566                 return;
3567
3568 #endif
3569         if (ixgbe_cache_ring_fdir(adapter))
3570                 return;
3571
3572         if (ixgbe_cache_ring_rss(adapter))
3573                 return;
3574 }
3575
3576 /**
3577  * ixgbe_alloc_queues - Allocate memory for all rings
3578  * @adapter: board private structure to initialize
3579  *
3580  * We allocate one ring per queue at run-time since we don't know the
3581  * number of queues at compile-time.  The polling_netdev array is
3582  * intended for Multiqueue, but should work fine with a single queue.
3583  **/
3584 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
3585 {
3586         int i;
3587
3588         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
3589                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3590         if (!adapter->tx_ring)
3591                 goto err_tx_ring_allocation;
3592
3593         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
3594                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3595         if (!adapter->rx_ring)
3596                 goto err_rx_ring_allocation;
3597
3598         for (i = 0; i < adapter->num_tx_queues; i++) {
3599                 adapter->tx_ring[i].count = adapter->tx_ring_count;
3600                 adapter->tx_ring[i].queue_index = i;
3601         }
3602
3603         for (i = 0; i < adapter->num_rx_queues; i++) {
3604                 adapter->rx_ring[i].count = adapter->rx_ring_count;
3605                 adapter->rx_ring[i].queue_index = i;
3606         }
3607
3608         ixgbe_cache_ring_register(adapter);
3609
3610         return 0;
3611
3612 err_rx_ring_allocation:
3613         kfree(adapter->tx_ring);
3614 err_tx_ring_allocation:
3615         return -ENOMEM;
3616 }
3617
3618 /**
3619  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3620  * @adapter: board private structure to initialize
3621  *
3622  * Attempt to configure the interrupts using the best available
3623  * capabilities of the hardware and the kernel.
3624  **/
3625 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
3626 {
3627         struct ixgbe_hw *hw = &adapter->hw;
3628         int err = 0;
3629         int vector, v_budget;
3630
3631         /*
3632          * It's easy to be greedy for MSI-X vectors, but it really
3633          * doesn't do us much good if we have a lot more vectors
3634          * than CPU's.  So let's be conservative and only ask for
3635          * (roughly) twice the number of vectors as there are CPU's.
3636          */
3637         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
3638                        (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
3639
3640         /*
3641          * At the same time, hardware can only support a maximum of
3642          * hw.mac->max_msix_vectors vectors.  With features
3643          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3644          * descriptor queues supported by our device.  Thus, we cap it off in
3645          * those rare cases where the cpu count also exceeds our vector limit.
3646          */
3647         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
3648
3649         /* A failure in MSI-X entry allocation isn't fatal, but it does
3650          * mean we disable MSI-X capabilities of the adapter. */
3651         adapter->msix_entries = kcalloc(v_budget,
3652                                         sizeof(struct msix_entry), GFP_KERNEL);
3653         if (adapter->msix_entries) {
3654                 for (vector = 0; vector < v_budget; vector++)
3655                         adapter->msix_entries[vector].entry = vector;
3656
3657                 ixgbe_acquire_msix_vectors(adapter, v_budget);
3658
3659                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3660                         goto out;
3661         }
3662
3663         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3664         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3665         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3666         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3667         adapter->atr_sample_rate = 0;
3668         ixgbe_set_num_queues(adapter);
3669
3670         err = pci_enable_msi(adapter->pdev);
3671         if (!err) {
3672                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3673         } else {
3674                 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
3675                         "falling back to legacy.  Error: %d\n", err);
3676                 /* reset err */
3677                 err = 0;
3678         }
3679
3680 out:
3681         return err;
3682 }
3683
3684 /**
3685  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3686  * @adapter: board private structure to initialize
3687  *
3688  * We allocate one q_vector per queue interrupt.  If allocation fails we
3689  * return -ENOMEM.
3690  **/
3691 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3692 {
3693         int q_idx, num_q_vectors;
3694         struct ixgbe_q_vector *q_vector;
3695         int napi_vectors;
3696         int (*poll)(struct napi_struct *, int);
3697
3698         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3699                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3700                 napi_vectors = adapter->num_rx_queues;
3701                 poll = &ixgbe_clean_rxtx_many;
3702         } else {
3703                 num_q_vectors = 1;
3704                 napi_vectors = 1;
3705                 poll = &ixgbe_poll;
3706         }
3707
3708         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3709                 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3710                 if (!q_vector)
3711                         goto err_out;
3712                 q_vector->adapter = adapter;
3713                 if (q_vector->txr_count && !q_vector->rxr_count)
3714                         q_vector->eitr = adapter->tx_eitr_param;
3715                 else
3716                         q_vector->eitr = adapter->rx_eitr_param;
3717                 q_vector->v_idx = q_idx;
3718                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
3719                 adapter->q_vector[q_idx] = q_vector;
3720         }
3721
3722         return 0;
3723
3724 err_out:
3725         while (q_idx) {
3726                 q_idx--;
3727                 q_vector = adapter->q_vector[q_idx];
3728                 netif_napi_del(&q_vector->napi);
3729                 kfree(q_vector);
3730                 adapter->q_vector[q_idx] = NULL;
3731         }
3732         return -ENOMEM;
3733 }
3734
3735 /**
3736  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3737  * @adapter: board private structure to initialize
3738  *
3739  * This function frees the memory allocated to the q_vectors.  In addition if
3740  * NAPI is enabled it will delete any references to the NAPI struct prior
3741  * to freeing the q_vector.
3742  **/
3743 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3744 {
3745         int q_idx, num_q_vectors;
3746
3747         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3748                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3749         else
3750                 num_q_vectors = 1;
3751
3752         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3753                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
3754                 adapter->q_vector[q_idx] = NULL;
3755                 netif_napi_del(&q_vector->napi);
3756                 kfree(q_vector);
3757         }
3758 }
3759
3760 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
3761 {
3762         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3763                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3764                 pci_disable_msix(adapter->pdev);
3765                 kfree(adapter->msix_entries);
3766                 adapter->msix_entries = NULL;
3767         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3768                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3769                 pci_disable_msi(adapter->pdev);
3770         }
3771         return;
3772 }
3773
3774 /**
3775  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3776  * @adapter: board private structure to initialize
3777  *
3778  * We determine which interrupt scheme to use based on...
3779  * - Kernel support (MSI, MSI-X)
3780  *   - which can be user-defined (via MODULE_PARAM)
3781  * - Hardware queue count (num_*_queues)
3782  *   - defined by miscellaneous hardware support/features (RSS, etc.)
3783  **/
3784 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
3785 {
3786         int err;
3787
3788         /* Number of supported queues */
3789         ixgbe_set_num_queues(adapter);
3790
3791         err = ixgbe_set_interrupt_capability(adapter);
3792         if (err) {
3793                 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3794                 goto err_set_interrupt;
3795         }
3796
3797         err = ixgbe_alloc_q_vectors(adapter);
3798         if (err) {
3799                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3800                         "vectors\n");
3801                 goto err_alloc_q_vectors;
3802         }
3803
3804         err = ixgbe_alloc_queues(adapter);
3805         if (err) {
3806                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3807                 goto err_alloc_queues;
3808         }
3809
3810         DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
3811                 "Tx Queue count = %u\n",
3812                 (adapter->num_rx_queues > 1) ? "Enabled" :
3813                 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
3814
3815         set_bit(__IXGBE_DOWN, &adapter->state);
3816
3817         return 0;
3818
3819 err_alloc_queues:
3820         ixgbe_free_q_vectors(adapter);
3821 err_alloc_q_vectors:
3822         ixgbe_reset_interrupt_capability(adapter);
3823 err_set_interrupt:
3824         return err;
3825 }
3826
3827 /**
3828  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3829  * @adapter: board private structure to clear interrupt scheme on
3830  *
3831  * We go through and clear interrupt specific resources and reset the structure
3832  * to pre-load conditions
3833  **/
3834 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3835 {
3836         kfree(adapter->tx_ring);
3837         kfree(adapter->rx_ring);
3838         adapter->tx_ring = NULL;
3839         adapter->rx_ring = NULL;
3840
3841         ixgbe_free_q_vectors(adapter);
3842         ixgbe_reset_interrupt_capability(adapter);
3843 }
3844
3845 /**
3846  * ixgbe_sfp_timer - worker thread to find a missing module
3847  * @data: pointer to our adapter struct
3848  **/
3849 static void ixgbe_sfp_timer(unsigned long data)
3850 {
3851         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3852
3853         /*
3854          * Do the sfp_timer outside of interrupt context due to the
3855          * delays that sfp+ detection requires
3856          */
3857         schedule_work(&adapter->sfp_task);
3858 }
3859
3860 /**
3861  * ixgbe_sfp_task - worker thread to find a missing module
3862  * @work: pointer to work_struct containing our data
3863  **/
3864 static void ixgbe_sfp_task(struct work_struct *work)
3865 {
3866         struct ixgbe_adapter *adapter = container_of(work,
3867                                                      struct ixgbe_adapter,
3868                                                      sfp_task);
3869         struct ixgbe_hw *hw = &adapter->hw;
3870
3871         if ((hw->phy.type == ixgbe_phy_nl) &&
3872             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3873                 s32 ret = hw->phy.ops.identify_sfp(hw);
3874                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
3875                         goto reschedule;
3876                 ret = hw->phy.ops.reset(hw);
3877                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3878                         dev_err(&adapter->pdev->dev, "failed to initialize "
3879                                 "because an unsupported SFP+ module type "
3880                                 "was detected.\n"
3881                                 "Reload the driver after installing a "
3882                                 "supported module.\n");
3883                         unregister_netdev(adapter->netdev);
3884                 } else {
3885                         DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3886                                 hw->phy.sfp_type);
3887                 }
3888                 /* don't need this routine any more */
3889                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3890         }
3891         return;
3892 reschedule:
3893         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3894                 mod_timer(&adapter->sfp_timer,
3895                           round_jiffies(jiffies + (2 * HZ)));
3896 }
3897
3898 /**
3899  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3900  * @adapter: board private structure to initialize
3901  *
3902  * ixgbe_sw_init initializes the Adapter private data structure.
3903  * Fields are initialized based on PCI device information and
3904  * OS network device settings (MTU size).
3905  **/
3906 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3907 {
3908         struct ixgbe_hw *hw = &adapter->hw;
3909         struct pci_dev *pdev = adapter->pdev;
3910         unsigned int rss;
3911 #ifdef CONFIG_IXGBE_DCB
3912         int j;
3913         struct tc_configuration *tc;
3914 #endif
3915
3916         /* PCI config space info */
3917
3918         hw->vendor_id = pdev->vendor;
3919         hw->device_id = pdev->device;
3920         hw->revision_id = pdev->revision;
3921         hw->subsystem_vendor_id = pdev->subsystem_vendor;
3922         hw->subsystem_device_id = pdev->subsystem_device;
3923
3924         /* Set capability flags */
3925         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3926         adapter->ring_feature[RING_F_RSS].indices = rss;
3927         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
3928         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
3929         if (hw->mac.type == ixgbe_mac_82598EB) {
3930                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
3931                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
3932                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
3933         } else if (hw->mac.type == ixgbe_mac_82599EB) {
3934                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
3935                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
3936                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
3937                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
3938                 adapter->ring_feature[RING_F_FDIR].indices =
3939                                                          IXGBE_MAX_FDIR_INDICES;
3940                 adapter->atr_sample_rate = 20;
3941                 adapter->fdir_pballoc = 0;
3942 #ifdef IXGBE_FCOE
3943                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
3944                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
3945                 adapter->ring_feature[RING_F_FCOE].indices = 0;
3946                 /* Default traffic class to use for FCoE */
3947                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
3948 #endif /* IXGBE_FCOE */
3949         }
3950
3951 #ifdef CONFIG_IXGBE_DCB
3952         /* Configure DCB traffic classes */
3953         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3954                 tc = &adapter->dcb_cfg.tc_config[j];
3955                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3956                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3957                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3958                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3959                 tc->dcb_pfc = pfc_disabled;
3960         }
3961         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3962         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3963         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
3964         adapter->dcb_cfg.pfc_mode_enable = false;
3965         adapter->dcb_cfg.round_robin_enable = false;
3966         adapter->dcb_set_bitmap = 0x00;
3967         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3968                            adapter->ring_feature[RING_F_DCB].indices);
3969
3970 #endif
3971
3972         /* default flow control settings */
3973         hw->fc.requested_mode = ixgbe_fc_full;
3974         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
3975 #ifdef CONFIG_DCB
3976         adapter->last_lfc_mode = hw->fc.current_mode;
3977 #endif
3978         hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3979         hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3980         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3981         hw->fc.send_xon = true;
3982         hw->fc.disable_fc_autoneg = false;
3983
3984         /* enable itr by default in dynamic mode */
3985         adapter->rx_itr_setting = 1;
3986         adapter->rx_eitr_param = 20000;
3987         adapter->tx_itr_setting = 1;
3988         adapter->tx_eitr_param = 10000;
3989
3990         /* set defaults for eitr in MegaBytes */
3991         adapter->eitr_low = 10;
3992         adapter->eitr_high = 20;
3993
3994         /* set default ring sizes */
3995         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3996         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3997
3998         /* initialize eeprom parameters */
3999         if (ixgbe_init_eeprom_params_generic(hw)) {
4000                 dev_err(&pdev->dev, "EEPROM initialization failed\n");
4001                 return -EIO;
4002         }
4003
4004         /* enable rx csum by default */
4005         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4006
4007         set_bit(__IXGBE_DOWN, &adapter->state);
4008
4009         return 0;
4010 }
4011
4012 /**
4013  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4014  * @adapter: board private structure
4015  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
4016  *
4017  * Return 0 on success, negative on failure
4018  **/
4019 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
4020                              struct ixgbe_ring *tx_ring)
4021 {
4022         struct pci_dev *pdev = adapter->pdev;
4023         int size;
4024
4025         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4026         tx_ring->tx_buffer_info = vmalloc(size);
4027         if (!tx_ring->tx_buffer_info)
4028                 goto err;
4029         memset(tx_ring->tx_buffer_info, 0, size);
4030
4031         /* round up to nearest 4K */
4032         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4033         tx_ring->size = ALIGN(tx_ring->size, 4096);
4034
4035         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
4036                                              &tx_ring->dma);
4037         if (!tx_ring->desc)
4038                 goto err;
4039
4040         tx_ring->next_to_use = 0;
4041         tx_ring->next_to_clean = 0;
4042         tx_ring->work_limit = tx_ring->count;
4043         return 0;
4044
4045 err:
4046         vfree(tx_ring->tx_buffer_info);
4047         tx_ring->tx_buffer_info = NULL;
4048         DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
4049                             "descriptor ring\n");
4050         return -ENOMEM;
4051 }
4052
4053 /**
4054  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4055  * @adapter: board private structure
4056  *
4057  * If this function returns with an error, then it's possible one or
4058  * more of the rings is populated (while the rest are not).  It is the
4059  * callers duty to clean those orphaned rings.
4060  *
4061  * Return 0 on success, negative on failure
4062  **/
4063 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4064 {
4065         int i, err = 0;
4066
4067         for (i = 0; i < adapter->num_tx_queues; i++) {
4068                 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
4069                 if (!err)
4070                         continue;
4071                 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
4072                 break;
4073         }
4074
4075         return err;
4076 }
4077
4078 /**
4079  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4080  * @adapter: board private structure
4081  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
4082  *
4083  * Returns 0 on success, negative on failure
4084  **/
4085 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
4086                              struct ixgbe_ring *rx_ring)
4087 {
4088         struct pci_dev *pdev = adapter->pdev;
4089         int size;
4090
4091         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4092         rx_ring->rx_buffer_info = vmalloc(size);
4093         if (!rx_ring->rx_buffer_info) {
4094                 DPRINTK(PROBE, ERR,
4095                         "vmalloc allocation failed for the rx desc ring\n");
4096                 goto alloc_failed;
4097         }
4098         memset(rx_ring->rx_buffer_info, 0, size);
4099
4100         /* Round up to nearest 4K */
4101         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4102         rx_ring->size = ALIGN(rx_ring->size, 4096);
4103
4104         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
4105
4106         if (!rx_ring->desc) {
4107                 DPRINTK(PROBE, ERR,
4108                         "Memory allocation failed for the rx desc ring\n");
4109                 vfree(rx_ring->rx_buffer_info);
4110                 goto alloc_failed;
4111         }
4112
4113         rx_ring->next_to_clean = 0;
4114         rx_ring->next_to_use = 0;
4115
4116         return 0;
4117
4118 alloc_failed:
4119         return -ENOMEM;
4120 }
4121
4122 /**
4123  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4124  * @adapter: board private structure
4125  *
4126  * If this function returns with an error, then it's possible one or
4127  * more of the rings is populated (while the rest are not).  It is the
4128  * callers duty to clean those orphaned rings.
4129  *
4130  * Return 0 on success, negative on failure
4131  **/
4132
4133 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4134 {
4135         int i, err = 0;
4136
4137         for (i = 0; i < adapter->num_rx_queues; i++) {
4138                 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
4139                 if (!err)
4140                         continue;
4141                 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4142                 break;
4143         }
4144
4145         return err;
4146 }
4147
4148 /**
4149  * ixgbe_free_tx_resources - Free Tx Resources per Queue
4150  * @adapter: board private structure
4151  * @tx_ring: Tx descriptor ring for a specific queue
4152  *
4153  * Free all transmit software resources
4154  **/
4155 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4156                              struct ixgbe_ring *tx_ring)
4157 {
4158         struct pci_dev *pdev = adapter->pdev;
4159
4160         ixgbe_clean_tx_ring(adapter, tx_ring);
4161
4162         vfree(tx_ring->tx_buffer_info);
4163         tx_ring->tx_buffer_info = NULL;
4164
4165         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4166
4167         tx_ring->desc = NULL;
4168 }
4169
4170 /**
4171  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4172  * @adapter: board private structure
4173  *
4174  * Free all transmit software resources
4175  **/
4176 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4177 {
4178         int i;
4179
4180         for (i = 0; i < adapter->num_tx_queues; i++)
4181                 if (adapter->tx_ring[i].desc)
4182                         ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
4183 }
4184
4185 /**
4186  * ixgbe_free_rx_resources - Free Rx Resources
4187  * @adapter: board private structure
4188  * @rx_ring: ring to clean the resources from
4189  *
4190  * Free all receive software resources
4191  **/
4192 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4193                              struct ixgbe_ring *rx_ring)
4194 {
4195         struct pci_dev *pdev = adapter->pdev;
4196
4197         ixgbe_clean_rx_ring(adapter, rx_ring);
4198
4199         vfree(rx_ring->rx_buffer_info);
4200         rx_ring->rx_buffer_info = NULL;
4201
4202         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4203
4204         rx_ring->desc = NULL;
4205 }
4206
4207 /**
4208  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4209  * @adapter: board private structure
4210  *
4211  * Free all receive software resources
4212  **/
4213 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4214 {
4215         int i;
4216
4217         for (i = 0; i < adapter->num_rx_queues; i++)
4218                 if (adapter->rx_ring[i].desc)
4219                         ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
4220 }
4221
4222 /**
4223  * ixgbe_change_mtu - Change the Maximum Transfer Unit
4224  * @netdev: network interface device structure
4225  * @new_mtu: new value for maximum frame size
4226  *
4227  * Returns 0 on success, negative on failure
4228  **/
4229 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4230 {
4231         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4232         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4233
4234         /* MTU < 68 is an error and causes problems on some kernels */
4235         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4236                 return -EINVAL;
4237
4238         DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
4239                 netdev->mtu, new_mtu);
4240         /* must set new MTU before calling down or up */
4241         netdev->mtu = new_mtu;
4242
4243         if (netif_running(netdev))
4244                 ixgbe_reinit_locked(adapter);
4245
4246         return 0;
4247 }
4248
4249 /**
4250  * ixgbe_open - Called when a network interface is made active
4251  * @netdev: network interface device structure
4252  *
4253  * Returns 0 on success, negative value on failure
4254  *
4255  * The open entry point is called when a network interface is made
4256  * active by the system (IFF_UP).  At this point all resources needed
4257  * for transmit and receive operations are allocated, the interrupt
4258  * handler is registered with the OS, the watchdog timer is started,
4259  * and the stack is notified that the interface is ready.
4260  **/
4261 static int ixgbe_open(struct net_device *netdev)
4262 {
4263         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4264         int err;
4265
4266         /* disallow open during test */
4267         if (test_bit(__IXGBE_TESTING, &adapter->state))
4268                 return -EBUSY;
4269
4270         netif_carrier_off(netdev);
4271
4272         /* allocate transmit descriptors */
4273         err = ixgbe_setup_all_tx_resources(adapter);
4274         if (err)
4275                 goto err_setup_tx;
4276
4277         /* allocate receive descriptors */
4278         err = ixgbe_setup_all_rx_resources(adapter);
4279         if (err)
4280                 goto err_setup_rx;
4281
4282         ixgbe_configure(adapter);
4283
4284         err = ixgbe_request_irq(adapter);
4285         if (err)
4286                 goto err_req_irq;
4287
4288         err = ixgbe_up_complete(adapter);
4289         if (err)
4290                 goto err_up;
4291
4292         netif_tx_start_all_queues(netdev);
4293
4294         return 0;
4295
4296 err_up:
4297         ixgbe_release_hw_control(adapter);
4298         ixgbe_free_irq(adapter);
4299 err_req_irq:
4300 err_setup_rx:
4301         ixgbe_free_all_rx_resources(adapter);
4302 err_setup_tx:
4303         ixgbe_free_all_tx_resources(adapter);
4304         ixgbe_reset(adapter);
4305
4306         return err;
4307 }
4308
4309 /**
4310  * ixgbe_close - Disables a network interface
4311  * @netdev: network interface device structure
4312  *
4313  * Returns 0, this is not allowed to fail
4314  *
4315  * The close entry point is called when an interface is de-activated
4316  * by the OS.  The hardware is still under the drivers control, but
4317  * needs to be disabled.  A global MAC reset is issued to stop the
4318  * hardware, and all transmit and receive resources are freed.
4319  **/
4320 static int ixgbe_close(struct net_device *netdev)
4321 {
4322         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4323
4324         ixgbe_down(adapter);
4325         ixgbe_free_irq(adapter);
4326
4327         ixgbe_free_all_tx_resources(adapter);
4328         ixgbe_free_all_rx_resources(adapter);
4329
4330         ixgbe_release_hw_control(adapter);
4331
4332         return 0;
4333 }
4334
4335 #ifdef CONFIG_PM
4336 static int ixgbe_resume(struct pci_dev *pdev)
4337 {
4338         struct net_device *netdev = pci_get_drvdata(pdev);
4339         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4340         u32 err;
4341
4342         pci_set_power_state(pdev, PCI_D0);
4343         pci_restore_state(pdev);
4344
4345         err = pci_enable_device_mem(pdev);
4346         if (err) {
4347                 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
4348                                 "suspend\n");
4349                 return err;
4350         }
4351         pci_set_master(pdev);
4352
4353         pci_wake_from_d3(pdev, false);
4354
4355         err = ixgbe_init_interrupt_scheme(adapter);
4356         if (err) {
4357                 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4358                                 "device\n");
4359                 return err;
4360         }
4361
4362         ixgbe_reset(adapter);
4363
4364         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4365
4366         if (netif_running(netdev)) {
4367                 err = ixgbe_open(adapter->netdev);
4368                 if (err)
4369                         return err;
4370         }
4371
4372         netif_device_attach(netdev);
4373
4374         return 0;
4375 }
4376 #endif /* CONFIG_PM */
4377
4378 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
4379 {
4380         struct net_device *netdev = pci_get_drvdata(pdev);
4381         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4382         struct ixgbe_hw *hw = &adapter->hw;
4383         u32 ctrl, fctrl;
4384         u32 wufc = adapter->wol;
4385 #ifdef CONFIG_PM
4386         int retval = 0;
4387 #endif
4388
4389         netif_device_detach(netdev);
4390
4391         if (netif_running(netdev)) {
4392                 ixgbe_down(adapter);
4393                 ixgbe_free_irq(adapter);
4394                 ixgbe_free_all_tx_resources(adapter);
4395                 ixgbe_free_all_rx_resources(adapter);
4396         }
4397         ixgbe_clear_interrupt_scheme(adapter);
4398
4399 #ifdef CONFIG_PM
4400         retval = pci_save_state(pdev);
4401         if (retval)
4402                 return retval;
4403
4404 #endif
4405         if (wufc) {
4406                 ixgbe_set_rx_mode(netdev);
4407
4408                 /* turn on all-multi mode if wake on multicast is enabled */
4409                 if (wufc & IXGBE_WUFC_MC) {
4410                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4411                         fctrl |= IXGBE_FCTRL_MPE;
4412                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4413                 }
4414
4415                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4416                 ctrl |= IXGBE_CTRL_GIO_DIS;
4417                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4418
4419                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4420         } else {
4421                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4422                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4423         }
4424
4425         if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4426                 pci_wake_from_d3(pdev, true);
4427         else
4428                 pci_wake_from_d3(pdev, false);
4429
4430         *enable_wake = !!wufc;
4431
4432         ixgbe_release_hw_control(adapter);
4433
4434         pci_disable_device(pdev);
4435
4436         return 0;
4437 }
4438
4439 #ifdef CONFIG_PM
4440 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4441 {
4442         int retval;
4443         bool wake;
4444
4445         retval = __ixgbe_shutdown(pdev, &wake);
4446         if (retval)
4447                 return retval;
4448
4449         if (wake) {
4450                 pci_prepare_to_sleep(pdev);
4451         } else {
4452                 pci_wake_from_d3(pdev, false);
4453                 pci_set_power_state(pdev, PCI_D3hot);
4454         }
4455
4456         return 0;
4457 }
4458 #endif /* CONFIG_PM */
4459
4460 static void ixgbe_shutdown(struct pci_dev *pdev)
4461 {
4462         bool wake;
4463
4464         __ixgbe_shutdown(pdev, &wake);
4465
4466         if (system_state == SYSTEM_POWER_OFF) {
4467                 pci_wake_from_d3(pdev, wake);
4468                 pci_set_power_state(pdev, PCI_D3hot);
4469         }
4470 }
4471
4472 /**
4473  * ixgbe_update_stats - Update the board statistics counters.
4474  * @adapter: board private structure
4475  **/
4476 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4477 {
4478         struct ixgbe_hw *hw = &adapter->hw;
4479         u64 total_mpc = 0;
4480         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
4481
4482         if (hw->mac.type == ixgbe_mac_82599EB) {
4483                 u64 rsc_count = 0;
4484                 for (i = 0; i < 16; i++)
4485                         adapter->hw_rx_no_dma_resources +=
4486                                              IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4487                 for (i = 0; i < adapter->num_rx_queues; i++)
4488                         rsc_count += adapter->rx_ring[i].rsc_count;
4489                 adapter->rsc_count = rsc_count;
4490         }
4491
4492         adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
4493         for (i = 0; i < 8; i++) {
4494                 /* for packet buffers not used, the register should read 0 */
4495                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4496                 missed_rx += mpc;
4497                 adapter->stats.mpc[i] += mpc;
4498                 total_mpc += adapter->stats.mpc[i];
4499                 if (hw->mac.type == ixgbe_mac_82598EB)
4500                         adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
4501                 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4502                 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4503                 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4504                 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
4505                 if (hw->mac.type == ixgbe_mac_82599EB) {
4506                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4507                                                             IXGBE_PXONRXCNT(i));
4508                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4509                                                            IXGBE_PXOFFRXCNT(i));
4510                         adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4511                 } else {
4512                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4513                                                               IXGBE_PXONRXC(i));
4514                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4515                                                              IXGBE_PXOFFRXC(i));
4516                 }
4517                 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4518                                                             IXGBE_PXONTXC(i));
4519                 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
4520                                                              IXGBE_PXOFFTXC(i));
4521         }
4522         adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4523         /* work around hardware counting issue */
4524         adapter->stats.gprc -= missed_rx;
4525
4526         /* 82598 hardware only has a 32 bit counter in the high register */
4527         if (hw->mac.type == ixgbe_mac_82599EB) {
4528                 u64 tmp;
4529                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
4530                 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
4531                 adapter->stats.gorc += (tmp << 32);
4532                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
4533                 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
4534                 adapter->stats.gotc += (tmp << 32);
4535                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4536                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4537                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4538                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
4539                 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4540                 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
4541 #ifdef IXGBE_FCOE
4542                 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4543                 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4544                 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4545                 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4546                 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4547                 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4548 #endif /* IXGBE_FCOE */
4549         } else {
4550                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4551                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4552                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4553                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4554                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4555         }
4556         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4557         adapter->stats.bprc += bprc;
4558         adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
4559         if (hw->mac.type == ixgbe_mac_82598EB)
4560                 adapter->stats.mprc -= bprc;
4561         adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4562         adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4563         adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4564         adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4565         adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4566         adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4567         adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
4568         adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
4569         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4570         adapter->stats.lxontxc += lxon;
4571         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4572         adapter->stats.lxofftxc += lxoff;
4573         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4574         adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
4575         adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4576         /*
4577          * 82598 errata - tx of flow control packets is included in tx counters
4578          */
4579         xon_off_tot = lxon + lxoff;
4580         adapter->stats.gptc -= xon_off_tot;
4581         adapter->stats.mptc -= xon_off_tot;
4582         adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
4583         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4584         adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4585         adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
4586         adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4587         adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
4588         adapter->stats.ptc64 -= xon_off_tot;
4589         adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4590         adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4591         adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4592         adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4593         adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
4594         adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4595
4596         /* Fill out the OS statistics structure */
4597         adapter->net_stats.multicast = adapter->stats.mprc;
4598
4599         /* Rx Errors */
4600         adapter->net_stats.rx_errors = adapter->stats.crcerrs +
4601                                        adapter->stats.rlec;
4602         adapter->net_stats.rx_dropped = 0;
4603         adapter->net_stats.rx_length_errors = adapter->stats.rlec;
4604         adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
4605         adapter->net_stats.rx_missed_errors = total_mpc;
4606 }
4607
4608 /**
4609  * ixgbe_watchdog - Timer Call-back
4610  * @data: pointer to adapter cast into an unsigned long
4611  **/
4612 static void ixgbe_watchdog(unsigned long data)
4613 {
4614         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4615         struct ixgbe_hw *hw = &adapter->hw;
4616         u64 eics = 0;
4617         int i;
4618
4619         /*
4620          *  Do the watchdog outside of interrupt context due to the lovely
4621          * delays that some of the newer hardware requires
4622          */
4623
4624         if (test_bit(__IXGBE_DOWN, &adapter->state))
4625                 goto watchdog_short_circuit;
4626
4627         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4628                 /*
4629                  * for legacy and MSI interrupts don't set any bits
4630                  * that are enabled for EIAM, because this operation
4631                  * would set *both* EIMS and EICS for any bit in EIAM
4632                  */
4633                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4634                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4635                 goto watchdog_reschedule;
4636         }
4637
4638         /* get one bit for every active tx/rx interrupt vector */
4639         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
4640                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
4641                 if (qv->rxr_count || qv->txr_count)
4642                         eics |= ((u64)1 << i);
4643         }
4644
4645         /* Cause software interrupt to ensure rx rings are cleaned */
4646         ixgbe_irq_rearm_queues(adapter, eics);
4647
4648 watchdog_reschedule:
4649         /* Reset the timer */
4650         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
4651
4652 watchdog_short_circuit:
4653         schedule_work(&adapter->watchdog_task);
4654 }
4655
4656 /**
4657  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4658  * @work: pointer to work_struct containing our data
4659  **/
4660 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4661 {
4662         struct ixgbe_adapter *adapter = container_of(work,
4663                                                      struct ixgbe_adapter,
4664                                                      multispeed_fiber_task);
4665         struct ixgbe_hw *hw = &adapter->hw;
4666         u32 autoneg;
4667         bool negotiation;
4668
4669         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
4670         autoneg = hw->phy.autoneg_advertised;
4671         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
4672                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
4673         if (hw->mac.ops.setup_link)
4674                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
4675         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4676         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4677 }
4678
4679 /**
4680  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4681  * @work: pointer to work_struct containing our data
4682  **/
4683 static void ixgbe_sfp_config_module_task(struct work_struct *work)
4684 {
4685         struct ixgbe_adapter *adapter = container_of(work,
4686                                                      struct ixgbe_adapter,
4687                                                      sfp_config_module_task);
4688         struct ixgbe_hw *hw = &adapter->hw;
4689         u32 err;
4690
4691         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
4692
4693         /* Time for electrical oscillations to settle down */
4694         msleep(100);
4695         err = hw->phy.ops.identify_sfp(hw);
4696
4697         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4698                 dev_err(&adapter->pdev->dev, "failed to initialize because "
4699                         "an unsupported SFP+ module type was detected.\n"
4700                         "Reload the driver after installing a supported "
4701                         "module.\n");
4702                 unregister_netdev(adapter->netdev);
4703                 return;
4704         }
4705         hw->mac.ops.setup_sfp(hw);
4706
4707         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
4708                 /* This will also work for DA Twinax connections */
4709                 schedule_work(&adapter->multispeed_fiber_task);
4710         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4711 }
4712
4713 /**
4714  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
4715  * @work: pointer to work_struct containing our data
4716  **/
4717 static void ixgbe_fdir_reinit_task(struct work_struct *work)
4718 {
4719         struct ixgbe_adapter *adapter = container_of(work,
4720                                                      struct ixgbe_adapter,
4721                                                      fdir_reinit_task);
4722         struct ixgbe_hw *hw = &adapter->hw;
4723         int i;
4724
4725         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
4726                 for (i = 0; i < adapter->num_tx_queues; i++)
4727                         set_bit(__IXGBE_FDIR_INIT_DONE,
4728                                 &(adapter->tx_ring[i].reinit_state));
4729         } else {
4730                 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
4731                         "ignored adding FDIR ATR filters \n");
4732         }
4733         /* Done FDIR Re-initialization, enable transmits */
4734         netif_tx_start_all_queues(adapter->netdev);
4735 }
4736
4737 /**
4738  * ixgbe_watchdog_task - worker thread to bring link up
4739  * @work: pointer to work_struct containing our data
4740  **/
4741 static void ixgbe_watchdog_task(struct work_struct *work)
4742 {
4743         struct ixgbe_adapter *adapter = container_of(work,
4744                                                      struct ixgbe_adapter,
4745                                                      watchdog_task);
4746         struct net_device *netdev = adapter->netdev;
4747         struct ixgbe_hw *hw = &adapter->hw;
4748         u32 link_speed = adapter->link_speed;
4749         bool link_up = adapter->link_up;
4750         int i;
4751         struct ixgbe_ring *tx_ring;
4752         int some_tx_pending = 0;
4753
4754         adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4755
4756         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4757                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
4758                 if (link_up) {
4759 #ifdef CONFIG_DCB
4760                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4761                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
4762                                         hw->mac.ops.fc_enable(hw, i);
4763                         } else {
4764                                 hw->mac.ops.fc_enable(hw, 0);
4765                         }
4766 #else
4767                         hw->mac.ops.fc_enable(hw, 0);
4768 #endif
4769                 }
4770
4771                 if (link_up ||
4772                     time_after(jiffies, (adapter->link_check_timeout +
4773                                          IXGBE_TRY_LINK_TIMEOUT))) {
4774                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4775                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
4776                 }
4777                 adapter->link_up = link_up;
4778                 adapter->link_speed = link_speed;
4779         }
4780
4781         if (link_up) {
4782                 if (!netif_carrier_ok(netdev)) {
4783                         bool flow_rx, flow_tx;
4784
4785                         if (hw->mac.type == ixgbe_mac_82599EB) {
4786                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4787                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4788                                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
4789                                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
4790                         } else {
4791                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4792                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
4793                                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
4794                                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
4795                         }
4796
4797                         printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4798                                "Flow Control: %s\n",
4799                                netdev->name,
4800                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4801                                 "10 Gbps" :
4802                                 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4803                                  "1 Gbps" : "unknown speed")),
4804                                ((flow_rx && flow_tx) ? "RX/TX" :
4805                                 (flow_rx ? "RX" :
4806                                 (flow_tx ? "TX" : "None"))));
4807
4808                         netif_carrier_on(netdev);
4809                 } else {
4810                         /* Force detection of hung controller */
4811                         adapter->detect_tx_hung = true;
4812                 }
4813         } else {
4814                 adapter->link_up = false;
4815                 adapter->link_speed = 0;
4816                 if (netif_carrier_ok(netdev)) {
4817                         printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4818                                netdev->name);
4819                         netif_carrier_off(netdev);
4820                 }
4821         }
4822
4823         if (!netif_carrier_ok(netdev)) {
4824                 for (i = 0; i < adapter->num_tx_queues; i++) {
4825                         tx_ring = &adapter->tx_ring[i];
4826                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4827                                 some_tx_pending = 1;
4828                                 break;
4829                         }
4830                 }
4831
4832                 if (some_tx_pending) {
4833                         /* We've lost link, so the controller stops DMA,
4834                          * but we've got queued Tx work that's never going
4835                          * to get done, so reset controller to flush Tx.
4836                          * (Do the reset outside of interrupt context).
4837                          */
4838                          schedule_work(&adapter->reset_task);
4839                 }
4840         }
4841
4842         ixgbe_update_stats(adapter);
4843         adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
4844 }
4845
4846 static int ixgbe_tso(struct ixgbe_adapter *adapter,
4847                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4848                      u32 tx_flags, u8 *hdr_len)
4849 {
4850         struct ixgbe_adv_tx_context_desc *context_desc;
4851         unsigned int i;
4852         int err;
4853         struct ixgbe_tx_buffer *tx_buffer_info;
4854         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4855         u32 mss_l4len_idx, l4len;
4856
4857         if (skb_is_gso(skb)) {
4858                 if (skb_header_cloned(skb)) {
4859                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4860                         if (err)
4861                                 return err;
4862                 }
4863                 l4len = tcp_hdrlen(skb);
4864                 *hdr_len += l4len;
4865
4866                 if (skb->protocol == htons(ETH_P_IP)) {
4867                         struct iphdr *iph = ip_hdr(skb);
4868                         iph->tot_len = 0;
4869                         iph->check = 0;
4870                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4871                                                                  iph->daddr, 0,
4872                                                                  IPPROTO_TCP,
4873                                                                  0);
4874                         adapter->hw_tso_ctxt++;
4875                 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4876                         ipv6_hdr(skb)->payload_len = 0;
4877                         tcp_hdr(skb)->check =
4878                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4879                                              &ipv6_hdr(skb)->daddr,
4880                                              0, IPPROTO_TCP, 0);
4881                         adapter->hw_tso6_ctxt++;
4882                 }
4883
4884                 i = tx_ring->next_to_use;
4885
4886                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4887                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4888
4889                 /* VLAN MACLEN IPLEN */
4890                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4891                         vlan_macip_lens |=
4892                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4893                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
4894                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4895                 *hdr_len += skb_network_offset(skb);
4896                 vlan_macip_lens |=
4897                     (skb_transport_header(skb) - skb_network_header(skb));
4898                 *hdr_len +=
4899                     (skb_transport_header(skb) - skb_network_header(skb));
4900                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4901                 context_desc->seqnum_seed = 0;
4902
4903                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4904                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
4905                                    IXGBE_ADVTXD_DTYP_CTXT);
4906
4907                 if (skb->protocol == htons(ETH_P_IP))
4908                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4909                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4910                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4911
4912                 /* MSS L4LEN IDX */
4913                 mss_l4len_idx =
4914                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4915                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4916                 /* use index 1 for TSO */
4917                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4918                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4919
4920                 tx_buffer_info->time_stamp = jiffies;
4921                 tx_buffer_info->next_to_watch = i;
4922
4923                 i++;
4924                 if (i == tx_ring->count)
4925                         i = 0;
4926                 tx_ring->next_to_use = i;
4927
4928                 return true;
4929         }
4930         return false;
4931 }
4932
4933 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
4934                           struct ixgbe_ring *tx_ring,
4935                           struct sk_buff *skb, u32 tx_flags)
4936 {
4937         struct ixgbe_adv_tx_context_desc *context_desc;
4938         unsigned int i;
4939         struct ixgbe_tx_buffer *tx_buffer_info;
4940         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4941
4942         if (skb->ip_summed == CHECKSUM_PARTIAL ||
4943             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4944                 i = tx_ring->next_to_use;
4945                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4946                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4947
4948                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4949                         vlan_macip_lens |=
4950                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4951                 vlan_macip_lens |= (skb_network_offset(skb) <<
4952                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4953                 if (skb->ip_summed == CHECKSUM_PARTIAL)
4954                         vlan_macip_lens |= (skb_transport_header(skb) -
4955                                             skb_network_header(skb));
4956
4957                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4958                 context_desc->seqnum_seed = 0;
4959
4960                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
4961                                     IXGBE_ADVTXD_DTYP_CTXT);
4962
4963                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4964                         switch (skb->protocol) {
4965                         case cpu_to_be16(ETH_P_IP):
4966                                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4967                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4968                                         type_tucmd_mlhl |=
4969                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4970                                 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4971                                         type_tucmd_mlhl |=
4972                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4973                                 break;
4974                         case cpu_to_be16(ETH_P_IPV6):
4975                                 /* XXX what about other V6 headers?? */
4976                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4977                                         type_tucmd_mlhl |=
4978                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4979                                 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4980                                         type_tucmd_mlhl |=
4981                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4982                                 break;
4983                         default:
4984                                 if (unlikely(net_ratelimit())) {
4985                                         DPRINTK(PROBE, WARNING,
4986                                          "partial checksum but proto=%x!\n",
4987                                          skb->protocol);
4988                                 }
4989                                 break;
4990                         }
4991                 }
4992
4993                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4994                 /* use index zero for tx checksum offload */
4995                 context_desc->mss_l4len_idx = 0;
4996
4997                 tx_buffer_info->time_stamp = jiffies;
4998                 tx_buffer_info->next_to_watch = i;
4999
5000                 adapter->hw_csum_tx_good++;
5001                 i++;
5002                 if (i == tx_ring->count)
5003                         i = 0;
5004                 tx_ring->next_to_use = i;
5005
5006                 return true;
5007         }
5008
5009         return false;
5010 }
5011
5012 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
5013                         struct ixgbe_ring *tx_ring,
5014                         struct sk_buff *skb, u32 tx_flags,
5015                         unsigned int first)
5016 {
5017         struct ixgbe_tx_buffer *tx_buffer_info;
5018         unsigned int len;
5019         unsigned int total = skb->len;
5020         unsigned int offset = 0, size, count = 0, i;
5021         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5022         unsigned int f;
5023         dma_addr_t *map;
5024
5025         i = tx_ring->next_to_use;
5026
5027         if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
5028                 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
5029                 return 0;
5030         }
5031
5032         map = skb_shinfo(skb)->dma_maps;
5033
5034         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5035                 /* excluding fcoe_crc_eof for FCoE */
5036                 total -= sizeof(struct fcoe_crc_eof);
5037
5038         len = min(skb_headlen(skb), total);
5039         while (len) {
5040                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5041                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5042
5043                 tx_buffer_info->length = size;
5044                 tx_buffer_info->dma = skb_shinfo(skb)->dma_head + offset;
5045                 tx_buffer_info->time_stamp = jiffies;
5046                 tx_buffer_info->next_to_watch = i;
5047
5048                 len -= size;
5049                 total -= size;
5050                 offset += size;
5051                 count++;
5052
5053                 if (len) {
5054                         i++;
5055                         if (i == tx_ring->count)
5056                                 i = 0;
5057                 }
5058         }
5059
5060         for (f = 0; f < nr_frags; f++) {
5061                 struct skb_frag_struct *frag;
5062
5063                 frag = &skb_shinfo(skb)->frags[f];
5064                 len = min((unsigned int)frag->size, total);
5065                 offset = 0;
5066
5067                 while (len) {
5068                         i++;
5069                         if (i == tx_ring->count)
5070                                 i = 0;
5071
5072                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
5073                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5074
5075                         tx_buffer_info->length = size;
5076                         tx_buffer_info->dma = map[f] + offset;
5077                         tx_buffer_info->time_stamp = jiffies;
5078                         tx_buffer_info->next_to_watch = i;
5079
5080                         len -= size;
5081                         total -= size;
5082                         offset += size;
5083                         count++;
5084                 }
5085                 if (total == 0)
5086                         break;
5087         }
5088
5089         tx_ring->tx_buffer_info[i].skb = skb;
5090         tx_ring->tx_buffer_info[first].next_to_watch = i;
5091
5092         return count;
5093 }
5094
5095 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
5096                            struct ixgbe_ring *tx_ring,
5097                            int tx_flags, int count, u32 paylen, u8 hdr_len)
5098 {
5099         union ixgbe_adv_tx_desc *tx_desc = NULL;
5100         struct ixgbe_tx_buffer *tx_buffer_info;
5101         u32 olinfo_status = 0, cmd_type_len = 0;
5102         unsigned int i;
5103         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
5104
5105         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
5106
5107         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
5108
5109         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5110                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
5111
5112         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
5113                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5114
5115                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5116                                  IXGBE_ADVTXD_POPTS_SHIFT;
5117
5118                 /* use index 1 context for tso */
5119                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5120                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5121                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
5122                                          IXGBE_ADVTXD_POPTS_SHIFT;
5123
5124         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5125                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5126                                  IXGBE_ADVTXD_POPTS_SHIFT;
5127
5128         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5129                 olinfo_status |= IXGBE_ADVTXD_CC;
5130                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5131                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
5132                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5133         }
5134
5135         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
5136
5137         i = tx_ring->next_to_use;
5138         while (count--) {
5139                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5140                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5141                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5142                 tx_desc->read.cmd_type_len =
5143                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
5144                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
5145                 i++;
5146                 if (i == tx_ring->count)
5147                         i = 0;
5148         }
5149
5150         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5151
5152         /*
5153          * Force memory writes to complete before letting h/w
5154          * know there are new descriptors to fetch.  (Only
5155          * applicable for weak-ordered memory model archs,
5156          * such as IA-64).
5157          */
5158         wmb();
5159
5160         tx_ring->next_to_use = i;
5161         writel(i, adapter->hw.hw_addr + tx_ring->tail);
5162 }
5163
5164 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5165                       int queue, u32 tx_flags)
5166 {
5167         /* Right now, we support IPv4 only */
5168         struct ixgbe_atr_input atr_input;
5169         struct tcphdr *th;
5170         struct iphdr *iph = ip_hdr(skb);
5171         struct ethhdr *eth = (struct ethhdr *)skb->data;
5172         u16 vlan_id, src_port, dst_port, flex_bytes;
5173         u32 src_ipv4_addr, dst_ipv4_addr;
5174         u8 l4type = 0;
5175
5176         /* check if we're UDP or TCP */
5177         if (iph->protocol == IPPROTO_TCP) {
5178                 th = tcp_hdr(skb);
5179                 src_port = th->source;
5180                 dst_port = th->dest;
5181                 l4type |= IXGBE_ATR_L4TYPE_TCP;
5182                 /* l4type IPv4 type is 0, no need to assign */
5183         } else {
5184                 /* Unsupported L4 header, just bail here */
5185                 return;
5186         }
5187
5188         memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5189
5190         vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5191                    IXGBE_TX_FLAGS_VLAN_SHIFT;
5192         src_ipv4_addr = iph->saddr;
5193         dst_ipv4_addr = iph->daddr;
5194         flex_bytes = eth->h_proto;
5195
5196         ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5197         ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5198         ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5199         ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5200         ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5201         /* src and dst are inverted, think how the receiver sees them */
5202         ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5203         ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5204
5205         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5206         ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5207 }
5208
5209 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
5210                                  struct ixgbe_ring *tx_ring, int size)
5211 {
5212         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5213
5214         netif_stop_subqueue(netdev, tx_ring->queue_index);
5215         /* Herbert's original patch had:
5216          *  smp_mb__after_netif_stop_queue();
5217          * but since that doesn't exist yet, just open code it. */
5218         smp_mb();
5219
5220         /* We need to check again in a case another CPU has just
5221          * made room available. */
5222         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5223                 return -EBUSY;
5224
5225         /* A reprieve! - use start_queue because it doesn't call schedule */
5226         netif_start_subqueue(netdev, tx_ring->queue_index);
5227         ++adapter->restart_queue;
5228         return 0;
5229 }
5230
5231 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
5232                               struct ixgbe_ring *tx_ring, int size)
5233 {
5234         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5235                 return 0;
5236         return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5237 }
5238
5239 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5240 {
5241         struct ixgbe_adapter *adapter = netdev_priv(dev);
5242
5243         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
5244                 return smp_processor_id();
5245
5246         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5247                 return (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK) >> 13;
5248
5249         return skb_tx_hash(dev, skb);
5250 }
5251
5252 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
5253                                     struct net_device *netdev)
5254 {
5255         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5256         struct ixgbe_ring *tx_ring;
5257         unsigned int first;
5258         unsigned int tx_flags = 0;
5259         u8 hdr_len = 0;
5260         int r_idx = 0, tso;
5261         int count = 0;
5262         unsigned int f;
5263
5264         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5265                 tx_flags |= vlan_tx_tag_get(skb);
5266                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5267                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5268                         tx_flags |= (skb->queue_mapping << 13);
5269                 }
5270                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5271                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5272         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5273                 if (skb->priority != TC_PRIO_CONTROL) {
5274                         tx_flags |= (skb->queue_mapping << 13);
5275                         tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5276                         tx_flags |= IXGBE_TX_FLAGS_VLAN;
5277                 } else {
5278                         skb->queue_mapping =
5279                                 adapter->ring_feature[RING_F_DCB].indices-1;
5280                 }
5281         }
5282
5283         r_idx = skb->queue_mapping;
5284         tx_ring = &adapter->tx_ring[r_idx];
5285
5286         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
5287             (skb->protocol == htons(ETH_P_FCOE))) {
5288                 tx_flags |= IXGBE_TX_FLAGS_FCOE;
5289 #ifdef IXGBE_FCOE
5290                 r_idx = smp_processor_id();
5291                 r_idx &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
5292                 r_idx += adapter->ring_feature[RING_F_FCOE].mask;
5293                 tx_ring = &adapter->tx_ring[r_idx];
5294 #endif
5295         }
5296         /* four things can cause us to need a context descriptor */
5297         if (skb_is_gso(skb) ||
5298             (skb->ip_summed == CHECKSUM_PARTIAL) ||
5299             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5300             (tx_flags & IXGBE_TX_FLAGS_FCOE))
5301                 count++;
5302
5303         count += TXD_USE_COUNT(skb_headlen(skb));
5304         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5305                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5306
5307         if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
5308                 adapter->tx_busy++;
5309                 return NETDEV_TX_BUSY;
5310         }
5311
5312         first = tx_ring->next_to_use;
5313         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5314 #ifdef IXGBE_FCOE
5315                 /* setup tx offload for FCoE */
5316                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5317                 if (tso < 0) {
5318                         dev_kfree_skb_any(skb);
5319                         return NETDEV_TX_OK;
5320                 }
5321                 if (tso)
5322                         tx_flags |= IXGBE_TX_FLAGS_FSO;
5323 #endif /* IXGBE_FCOE */
5324         } else {
5325                 if (skb->protocol == htons(ETH_P_IP))
5326                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
5327                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5328                 if (tso < 0) {
5329                         dev_kfree_skb_any(skb);
5330                         return NETDEV_TX_OK;
5331                 }
5332
5333                 if (tso)
5334                         tx_flags |= IXGBE_TX_FLAGS_TSO;
5335                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5336                          (skb->ip_summed == CHECKSUM_PARTIAL))
5337                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
5338         }
5339
5340         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
5341         if (count) {
5342                 /* add the ATR filter if ATR is on */
5343                 if (tx_ring->atr_sample_rate) {
5344                         ++tx_ring->atr_count;
5345                         if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5346                              test_bit(__IXGBE_FDIR_INIT_DONE,
5347                                       &tx_ring->reinit_state)) {
5348                                 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5349                                           tx_flags);
5350                                 tx_ring->atr_count = 0;
5351                         }
5352                 }
5353                 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5354                                hdr_len);
5355                 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
5356
5357         } else {
5358                 dev_kfree_skb_any(skb);
5359                 tx_ring->tx_buffer_info[first].time_stamp = 0;
5360                 tx_ring->next_to_use = first;
5361         }
5362
5363         return NETDEV_TX_OK;
5364 }
5365
5366 /**
5367  * ixgbe_get_stats - Get System Network Statistics
5368  * @netdev: network interface device structure
5369  *
5370  * Returns the address of the device statistics structure.
5371  * The statistics are actually updated from the timer callback.
5372  **/
5373 static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
5374 {
5375         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5376
5377         /* only return the current stats */
5378         return &adapter->net_stats;
5379 }
5380
5381 /**
5382  * ixgbe_set_mac - Change the Ethernet Address of the NIC
5383  * @netdev: network interface device structure
5384  * @p: pointer to an address structure
5385  *
5386  * Returns 0 on success, negative on failure
5387  **/
5388 static int ixgbe_set_mac(struct net_device *netdev, void *p)
5389 {
5390         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5391         struct ixgbe_hw *hw = &adapter->hw;
5392         struct sockaddr *addr = p;
5393
5394         if (!is_valid_ether_addr(addr->sa_data))
5395                 return -EADDRNOTAVAIL;
5396
5397         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
5398         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
5399
5400         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
5401
5402         return 0;
5403 }
5404
5405 static int
5406 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5407 {
5408         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5409         struct ixgbe_hw *hw = &adapter->hw;
5410         u16 value;
5411         int rc;
5412
5413         if (prtad != hw->phy.mdio.prtad)
5414                 return -EINVAL;
5415         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5416         if (!rc)
5417                 rc = value;
5418         return rc;
5419 }
5420
5421 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5422                             u16 addr, u16 value)
5423 {
5424         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5425         struct ixgbe_hw *hw = &adapter->hw;
5426
5427         if (prtad != hw->phy.mdio.prtad)
5428                 return -EINVAL;
5429         return hw->phy.ops.write_reg(hw, addr, devad, value);
5430 }
5431
5432 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5433 {
5434         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5435
5436         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5437 }
5438
5439 /**
5440  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
5441  * netdev->dev_addrs
5442  * @netdev: network interface device structure
5443  *
5444  * Returns non-zero on failure
5445  **/
5446 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5447 {
5448         int err = 0;
5449         struct ixgbe_adapter *adapter = netdev_priv(dev);
5450         struct ixgbe_mac_info *mac = &adapter->hw.mac;
5451
5452         if (is_valid_ether_addr(mac->san_addr)) {
5453                 rtnl_lock();
5454                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5455                 rtnl_unlock();
5456         }
5457         return err;
5458 }
5459
5460 /**
5461  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
5462  * netdev->dev_addrs
5463  * @netdev: network interface device structure
5464  *
5465  * Returns non-zero on failure
5466  **/
5467 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5468 {
5469         int err = 0;
5470         struct ixgbe_adapter *adapter = netdev_priv(dev);
5471         struct ixgbe_mac_info *mac = &adapter->hw.mac;
5472
5473         if (is_valid_ether_addr(mac->san_addr)) {
5474                 rtnl_lock();
5475                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5476                 rtnl_unlock();
5477         }
5478         return err;
5479 }
5480
5481 #ifdef CONFIG_NET_POLL_CONTROLLER
5482 /*
5483  * Polling 'interrupt' - used by things like netconsole to send skbs
5484  * without having to re-enable interrupts. It's not called while
5485  * the interrupt routine is executing.
5486  */
5487 static void ixgbe_netpoll(struct net_device *netdev)
5488 {
5489         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5490         int i;
5491
5492         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
5493         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5494                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5495                 for (i = 0; i < num_q_vectors; i++) {
5496                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
5497                         ixgbe_msix_clean_many(0, q_vector);
5498                 }
5499         } else {
5500                 ixgbe_intr(adapter->pdev->irq, netdev);
5501         }
5502         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
5503 }
5504 #endif
5505
5506 static const struct net_device_ops ixgbe_netdev_ops = {
5507         .ndo_open               = ixgbe_open,
5508         .ndo_stop               = ixgbe_close,
5509         .ndo_start_xmit         = ixgbe_xmit_frame,
5510         .ndo_select_queue       = ixgbe_select_queue,
5511         .ndo_get_stats          = ixgbe_get_stats,
5512         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
5513         .ndo_set_multicast_list = ixgbe_set_rx_mode,
5514         .ndo_validate_addr      = eth_validate_addr,
5515         .ndo_set_mac_address    = ixgbe_set_mac,
5516         .ndo_change_mtu         = ixgbe_change_mtu,
5517         .ndo_tx_timeout         = ixgbe_tx_timeout,
5518         .ndo_vlan_rx_register   = ixgbe_vlan_rx_register,
5519         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
5520         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
5521         .ndo_do_ioctl           = ixgbe_ioctl,
5522 #ifdef CONFIG_NET_POLL_CONTROLLER
5523         .ndo_poll_controller    = ixgbe_netpoll,
5524 #endif
5525 #ifdef IXGBE_FCOE
5526         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5527         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
5528         .ndo_fcoe_enable = ixgbe_fcoe_enable,
5529         .ndo_fcoe_disable = ixgbe_fcoe_disable,
5530 #endif /* IXGBE_FCOE */
5531 };
5532
5533 /**
5534  * ixgbe_probe - Device Initialization Routine
5535  * @pdev: PCI device information struct
5536  * @ent: entry in ixgbe_pci_tbl
5537  *
5538  * Returns 0 on success, negative on failure
5539  *
5540  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5541  * The OS initialization, configuring of the adapter private structure,
5542  * and a hardware reset occur.
5543  **/
5544 static int __devinit ixgbe_probe(struct pci_dev *pdev,
5545                                  const struct pci_device_id *ent)
5546 {
5547         struct net_device *netdev;
5548         struct ixgbe_adapter *adapter = NULL;
5549         struct ixgbe_hw *hw;
5550         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
5551         static int cards_found;
5552         int i, err, pci_using_dac;
5553 #ifdef IXGBE_FCOE
5554         u16 device_caps;
5555 #endif
5556         u32 part_num, eec;
5557
5558         err = pci_enable_device_mem(pdev);
5559         if (err)
5560                 return err;
5561
5562         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
5563             !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
5564                 pci_using_dac = 1;
5565         } else {
5566                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5567                 if (err) {
5568                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5569                         if (err) {
5570                                 dev_err(&pdev->dev, "No usable DMA "
5571                                         "configuration, aborting\n");
5572                                 goto err_dma;
5573                         }
5574                 }
5575                 pci_using_dac = 0;
5576         }
5577
5578         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
5579                                            IORESOURCE_MEM), ixgbe_driver_name);
5580         if (err) {
5581                 dev_err(&pdev->dev,
5582                         "pci_request_selected_regions failed 0x%x\n", err);
5583                 goto err_pci_reg;
5584         }
5585
5586         pci_enable_pcie_error_reporting(pdev);
5587
5588         pci_set_master(pdev);
5589         pci_save_state(pdev);
5590
5591         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
5592         if (!netdev) {
5593                 err = -ENOMEM;
5594                 goto err_alloc_etherdev;
5595         }
5596
5597         SET_NETDEV_DEV(netdev, &pdev->dev);
5598
5599         pci_set_drvdata(pdev, netdev);
5600         adapter = netdev_priv(netdev);
5601
5602         adapter->netdev = netdev;
5603         adapter->pdev = pdev;
5604         hw = &adapter->hw;
5605         hw->back = adapter;
5606         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
5607
5608         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
5609                               pci_resource_len(pdev, 0));
5610         if (!hw->hw_addr) {
5611                 err = -EIO;
5612                 goto err_ioremap;
5613         }
5614
5615         for (i = 1; i <= 5; i++) {
5616                 if (pci_resource_len(pdev, i) == 0)
5617                         continue;
5618         }
5619
5620         netdev->netdev_ops = &ixgbe_netdev_ops;
5621         ixgbe_set_ethtool_ops(netdev);
5622         netdev->watchdog_timeo = 5 * HZ;
5623         strcpy(netdev->name, pci_name(pdev));
5624
5625         adapter->bd_number = cards_found;
5626
5627         /* Setup hw api */
5628         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
5629         hw->mac.type  = ii->mac;
5630
5631         /* EEPROM */
5632         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
5633         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5634         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5635         if (!(eec & (1 << 8)))
5636                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
5637
5638         /* PHY */
5639         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
5640         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
5641         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5642         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
5643         hw->phy.mdio.mmds = 0;
5644         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
5645         hw->phy.mdio.dev = netdev;
5646         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
5647         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
5648
5649         /* set up this timer and work struct before calling get_invariants
5650          * which might start the timer
5651          */
5652         init_timer(&adapter->sfp_timer);
5653         adapter->sfp_timer.function = &ixgbe_sfp_timer;
5654         adapter->sfp_timer.data = (unsigned long) adapter;
5655
5656         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
5657
5658         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5659         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
5660
5661         /* a new SFP+ module arrival, called from GPI SDP2 context */
5662         INIT_WORK(&adapter->sfp_config_module_task,
5663                   ixgbe_sfp_config_module_task);
5664
5665         ii->get_invariants(hw);
5666
5667         /* setup the private structure */
5668         err = ixgbe_sw_init(adapter);
5669         if (err)
5670                 goto err_sw_init;
5671
5672         /*
5673          * If there is a fan on this device and it has failed log the
5674          * failure.
5675          */
5676         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5677                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5678                 if (esdp & IXGBE_ESDP_SDP1)
5679                         DPRINTK(PROBE, CRIT,
5680                                 "Fan has stopped, replace the adapter\n");
5681         }
5682
5683         /* reset_hw fills in the perm_addr as well */
5684         err = hw->mac.ops.reset_hw(hw);
5685         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
5686             hw->mac.type == ixgbe_mac_82598EB) {
5687                 /*
5688                  * Start a kernel thread to watch for a module to arrive.
5689                  * Only do this for 82598, since 82599 will generate
5690                  * interrupts on module arrival.
5691                  */
5692                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5693                 mod_timer(&adapter->sfp_timer,
5694                           round_jiffies(jiffies + (2 * HZ)));
5695                 err = 0;
5696         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5697                 dev_err(&adapter->pdev->dev, "failed to initialize because "
5698                         "an unsupported SFP+ module type was detected.\n"
5699                         "Reload the driver after installing a supported "
5700                         "module.\n");
5701                 goto err_sw_init;
5702         } else if (err) {
5703                 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
5704                 goto err_sw_init;
5705         }
5706
5707         netdev->features = NETIF_F_SG |
5708                            NETIF_F_IP_CSUM |
5709                            NETIF_F_HW_VLAN_TX |
5710                            NETIF_F_HW_VLAN_RX |
5711                            NETIF_F_HW_VLAN_FILTER;
5712
5713         netdev->features |= NETIF_F_IPV6_CSUM;
5714         netdev->features |= NETIF_F_TSO;
5715         netdev->features |= NETIF_F_TSO6;
5716         netdev->features |= NETIF_F_GRO;
5717
5718         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
5719                 netdev->features |= NETIF_F_SCTP_CSUM;
5720
5721         netdev->vlan_features |= NETIF_F_TSO;
5722         netdev->vlan_features |= NETIF_F_TSO6;
5723         netdev->vlan_features |= NETIF_F_IP_CSUM;
5724         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
5725         netdev->vlan_features |= NETIF_F_SG;
5726
5727         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5728                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
5729
5730 #ifdef CONFIG_IXGBE_DCB
5731         netdev->dcbnl_ops = &dcbnl_ops;
5732 #endif
5733
5734 #ifdef IXGBE_FCOE
5735         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
5736                 if (hw->mac.ops.get_device_caps) {
5737                         hw->mac.ops.get_device_caps(hw, &device_caps);
5738                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
5739                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5740                 }
5741         }
5742 #endif /* IXGBE_FCOE */
5743         if (pci_using_dac)
5744                 netdev->features |= NETIF_F_HIGHDMA;
5745
5746         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
5747                 netdev->features |= NETIF_F_LRO;
5748
5749         /* make sure the EEPROM is good */
5750         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
5751                 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
5752                 err = -EIO;
5753                 goto err_eeprom;
5754         }
5755
5756         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
5757         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
5758
5759         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
5760                 dev_err(&pdev->dev, "invalid MAC address\n");
5761                 err = -EIO;
5762                 goto err_eeprom;
5763         }
5764
5765         init_timer(&adapter->watchdog_timer);
5766         adapter->watchdog_timer.function = &ixgbe_watchdog;
5767         adapter->watchdog_timer.data = (unsigned long)adapter;
5768
5769         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
5770         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
5771
5772         err = ixgbe_init_interrupt_scheme(adapter);
5773         if (err)
5774                 goto err_sw_init;
5775
5776         switch (pdev->device) {
5777         case IXGBE_DEV_ID_82599_KX4:
5778                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
5779                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
5780                 /* Enable ACPI wakeup in GRC */
5781                 IXGBE_WRITE_REG(hw, IXGBE_GRC,
5782                              (IXGBE_READ_REG(hw, IXGBE_GRC) & ~IXGBE_GRC_APME));
5783                 break;
5784         default:
5785                 adapter->wol = 0;
5786                 break;
5787         }
5788         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
5789
5790         /* pick up the PCI bus settings for reporting later */
5791         hw->mac.ops.get_bus_info(hw);
5792
5793         /* print bus type/speed/width info */
5794         dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
5795                 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
5796                  (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
5797                 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
5798                  (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
5799                  (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
5800                  "Unknown"),
5801                 netdev->dev_addr);
5802         ixgbe_read_pba_num_generic(hw, &part_num);
5803         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5804                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5805                          hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5806                          (part_num >> 8), (part_num & 0xff));
5807         else
5808                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5809                          hw->mac.type, hw->phy.type,
5810                          (part_num >> 8), (part_num & 0xff));
5811
5812         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
5813                 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
5814                          "this card is not sufficient for optimal "
5815                          "performance.\n");
5816                 dev_warn(&pdev->dev, "For optimal performance a x8 "
5817                          "PCI-Express slot is required.\n");
5818         }
5819
5820         /* save off EEPROM version number */
5821         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5822
5823         /* reset the hardware with the new settings */
5824         err = hw->mac.ops.start_hw(hw);
5825
5826         if (err == IXGBE_ERR_EEPROM_VERSION) {
5827                 /* We are running on a pre-production device, log a warning */
5828                 dev_warn(&pdev->dev, "This device is a pre-production "
5829                          "adapter/LOM.  Please be aware there may be issues "
5830                          "associated with your hardware.  If you are "
5831                          "experiencing problems please contact your Intel or "
5832                          "hardware representative who provided you with this "
5833                          "hardware.\n");
5834         }
5835         strcpy(netdev->name, "eth%d");
5836         err = register_netdev(netdev);
5837         if (err)
5838                 goto err_register;
5839
5840         /* carrier off reporting is important to ethtool even BEFORE open */
5841         netif_carrier_off(netdev);
5842
5843         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5844             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5845                 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
5846
5847 #ifdef CONFIG_IXGBE_DCA
5848         if (dca_add_requester(&pdev->dev) == 0) {
5849                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
5850                 ixgbe_setup_dca(adapter);
5851         }
5852 #endif
5853         /* add san mac addr to netdev */
5854         ixgbe_add_sanmac_netdev(netdev);
5855
5856         dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5857         cards_found++;
5858         return 0;
5859
5860 err_register:
5861         ixgbe_release_hw_control(adapter);
5862         ixgbe_clear_interrupt_scheme(adapter);
5863 err_sw_init:
5864 err_eeprom:
5865         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5866         del_timer_sync(&adapter->sfp_timer);
5867         cancel_work_sync(&adapter->sfp_task);
5868         cancel_work_sync(&adapter->multispeed_fiber_task);
5869         cancel_work_sync(&adapter->sfp_config_module_task);
5870         iounmap(hw->hw_addr);
5871 err_ioremap:
5872         free_netdev(netdev);
5873 err_alloc_etherdev:
5874         pci_release_selected_regions(pdev, pci_select_bars(pdev,
5875                                      IORESOURCE_MEM));
5876 err_pci_reg:
5877 err_dma:
5878         pci_disable_device(pdev);
5879         return err;
5880 }
5881
5882 /**
5883  * ixgbe_remove - Device Removal Routine
5884  * @pdev: PCI device information struct
5885  *
5886  * ixgbe_remove is called by the PCI subsystem to alert the driver
5887  * that it should release a PCI device.  The could be caused by a
5888  * Hot-Plug event, or because the driver is going to be removed from
5889  * memory.
5890  **/
5891 static void __devexit ixgbe_remove(struct pci_dev *pdev)
5892 {
5893         struct net_device *netdev = pci_get_drvdata(pdev);
5894         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5895
5896         set_bit(__IXGBE_DOWN, &adapter->state);
5897         /* clear the module not found bit to make sure the worker won't
5898          * reschedule
5899          */
5900         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5901         del_timer_sync(&adapter->watchdog_timer);
5902
5903         del_timer_sync(&adapter->sfp_timer);
5904         cancel_work_sync(&adapter->watchdog_task);
5905         cancel_work_sync(&adapter->sfp_task);
5906         cancel_work_sync(&adapter->multispeed_fiber_task);
5907         cancel_work_sync(&adapter->sfp_config_module_task);
5908         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5909             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5910                 cancel_work_sync(&adapter->fdir_reinit_task);
5911         flush_scheduled_work();
5912
5913 #ifdef CONFIG_IXGBE_DCA
5914         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5915                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5916                 dca_remove_requester(&pdev->dev);
5917                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5918         }
5919
5920 #endif
5921 #ifdef IXGBE_FCOE
5922         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
5923                 ixgbe_cleanup_fcoe(adapter);
5924
5925 #endif /* IXGBE_FCOE */
5926
5927         /* remove the added san mac */
5928         ixgbe_del_sanmac_netdev(netdev);
5929
5930         if (netdev->reg_state == NETREG_REGISTERED)
5931                 unregister_netdev(netdev);
5932
5933         ixgbe_clear_interrupt_scheme(adapter);
5934
5935         ixgbe_release_hw_control(adapter);
5936
5937         iounmap(adapter->hw.hw_addr);
5938         pci_release_selected_regions(pdev, pci_select_bars(pdev,
5939                                      IORESOURCE_MEM));
5940
5941         DPRINTK(PROBE, INFO, "complete\n");
5942
5943         free_netdev(netdev);
5944
5945         pci_disable_pcie_error_reporting(pdev);
5946
5947         pci_disable_device(pdev);
5948 }
5949
5950 /**
5951  * ixgbe_io_error_detected - called when PCI error is detected
5952  * @pdev: Pointer to PCI device
5953  * @state: The current pci connection state
5954  *
5955  * This function is called after a PCI bus error affecting
5956  * this device has been detected.
5957  */
5958 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
5959                                                 pci_channel_state_t state)
5960 {
5961         struct net_device *netdev = pci_get_drvdata(pdev);
5962         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5963
5964         netif_device_detach(netdev);
5965
5966         if (state == pci_channel_io_perm_failure)
5967                 return PCI_ERS_RESULT_DISCONNECT;
5968
5969         if (netif_running(netdev))
5970                 ixgbe_down(adapter);
5971         pci_disable_device(pdev);
5972
5973         /* Request a slot reset. */
5974         return PCI_ERS_RESULT_NEED_RESET;
5975 }
5976
5977 /**
5978  * ixgbe_io_slot_reset - called after the pci bus has been reset.
5979  * @pdev: Pointer to PCI device
5980  *
5981  * Restart the card from scratch, as if from a cold-boot.
5982  */
5983 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
5984 {
5985         struct net_device *netdev = pci_get_drvdata(pdev);
5986         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5987         pci_ers_result_t result;
5988         int err;
5989
5990         if (pci_enable_device_mem(pdev)) {
5991                 DPRINTK(PROBE, ERR,
5992                         "Cannot re-enable PCI device after reset.\n");
5993                 result = PCI_ERS_RESULT_DISCONNECT;
5994         } else {
5995                 pci_set_master(pdev);
5996                 pci_restore_state(pdev);
5997                 pci_save_state(pdev);
5998
5999                 pci_wake_from_d3(pdev, false);
6000
6001                 ixgbe_reset(adapter);
6002                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6003                 result = PCI_ERS_RESULT_RECOVERED;
6004         }
6005
6006         err = pci_cleanup_aer_uncorrect_error_status(pdev);
6007         if (err) {
6008                 dev_err(&pdev->dev,
6009                   "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
6010                 /* non-fatal, continue */
6011         }
6012
6013         return result;
6014 }
6015
6016 /**
6017  * ixgbe_io_resume - called when traffic can start flowing again.
6018  * @pdev: Pointer to PCI device
6019  *
6020  * This callback is called when the error recovery driver tells us that
6021  * its OK to resume normal operation.
6022  */
6023 static void ixgbe_io_resume(struct pci_dev *pdev)
6024 {
6025         struct net_device *netdev = pci_get_drvdata(pdev);
6026         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6027
6028         if (netif_running(netdev)) {
6029                 if (ixgbe_up(adapter)) {
6030                         DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
6031                         return;
6032                 }
6033         }
6034
6035         netif_device_attach(netdev);
6036 }
6037
6038 static struct pci_error_handlers ixgbe_err_handler = {
6039         .error_detected = ixgbe_io_error_detected,
6040         .slot_reset = ixgbe_io_slot_reset,
6041         .resume = ixgbe_io_resume,
6042 };
6043
6044 static struct pci_driver ixgbe_driver = {
6045         .name     = ixgbe_driver_name,
6046         .id_table = ixgbe_pci_tbl,
6047         .probe    = ixgbe_probe,
6048         .remove   = __devexit_p(ixgbe_remove),
6049 #ifdef CONFIG_PM
6050         .suspend  = ixgbe_suspend,
6051         .resume   = ixgbe_resume,
6052 #endif
6053         .shutdown = ixgbe_shutdown,
6054         .err_handler = &ixgbe_err_handler
6055 };
6056
6057 /**
6058  * ixgbe_init_module - Driver Registration Routine
6059  *
6060  * ixgbe_init_module is the first routine called when the driver is
6061  * loaded. All it does is register with the PCI subsystem.
6062  **/
6063 static int __init ixgbe_init_module(void)
6064 {
6065         int ret;
6066         printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
6067                ixgbe_driver_string, ixgbe_driver_version);
6068
6069         printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
6070
6071 #ifdef CONFIG_IXGBE_DCA
6072         dca_register_notify(&dca_notifier);
6073 #endif
6074
6075         ret = pci_register_driver(&ixgbe_driver);
6076         return ret;
6077 }
6078
6079 module_init(ixgbe_init_module);
6080
6081 /**
6082  * ixgbe_exit_module - Driver Exit Cleanup Routine
6083  *
6084  * ixgbe_exit_module is called just before the driver is removed
6085  * from memory.
6086  **/
6087 static void __exit ixgbe_exit_module(void)
6088 {
6089 #ifdef CONFIG_IXGBE_DCA
6090         dca_unregister_notify(&dca_notifier);
6091 #endif
6092         pci_unregister_driver(&ixgbe_driver);
6093 }
6094
6095 #ifdef CONFIG_IXGBE_DCA
6096 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
6097                             void *p)
6098 {
6099         int ret_val;
6100
6101         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
6102                                          __ixgbe_notify_dca);
6103
6104         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
6105 }
6106
6107 #endif /* CONFIG_IXGBE_DCA */
6108 #ifdef DEBUG
6109 /**
6110  * ixgbe_get_hw_dev_name - return device name string
6111  * used by hardware layer to print debugging information
6112  **/
6113 char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
6114 {
6115         struct ixgbe_adapter *adapter = hw->back;
6116         return adapter->netdev->name;
6117 }
6118
6119 #endif
6120 module_exit(ixgbe_exit_module);
6121
6122 /* ixgbe_main.c */