drivers/net/forcedeth.c

   1 /*
   2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
   3  *
   4  * Note: This driver is a cleanroom reimplementation based on reverse
   5  *      engineered documentation written by Carl-Daniel Hailfinger
   6  *      and Andrew de Quincey.
   7  *
   8  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
   9  * trademarks of NVIDIA Corporation in the United States and other
  10  * countries.
  11  *
  12  * Copyright (C) 2003,4,5 Manfred Spraul
  13  * Copyright (C) 2004 Andrew de Quincey (wol support)
  14  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  15  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
  16  * Copyright (c) 2004,5,6 NVIDIA Corporation
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License as published by
  20  * the Free Software Foundation; either version 2 of the License, or
  21  * (at your option) any later version.
  22  *
  23  * This program is distributed in the hope that it will be useful,
  24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  26  * GNU General Public License for more details.
  27  *
  28  * You should have received a copy of the GNU General Public License
  29  * along with this program; if not, write to the Free Software
  30  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  31  *
  32  * Changelog:
  33  *      0.01: 05 Oct 2003: First release that compiles without warnings.
  34  *      0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
  35  *                         Check all PCI BARs for the register window.
  36  *                         udelay added to mii_rw.
  37  *      0.03: 06 Oct 2003: Initialize dev->irq.
  38  *      0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
  39  *      0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
  40  *      0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
  41  *                         irq mask updated
  42  *      0.07: 14 Oct 2003: Further irq mask updates.
  43  *      0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
  44  *                         added into irq handler, NULL check for drain_ring.
  45  *      0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
  46  *                         requested interrupt sources.
  47  *      0.10: 20 Oct 2003: First cleanup for release.
  48  *      0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
  49  *                         MAC Address init fix, set_multicast cleanup.
  50  *      0.12: 23 Oct 2003: Cleanups for release.
  51  *      0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
  52  *                         Set link speed correctly. start rx before starting
  53  *                         tx (nv_start_rx sets the link speed).
  54  *      0.14: 25 Oct 2003: Nic dependant irq mask.
  55  *      0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
  56  *                         open.
  57  *      0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
  58  *                         increased to 1628 bytes.
  59  *      0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
  60  *                         the tx length.
  61  *      0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
  62  *      0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
  63  *                         addresses, really stop rx if already running
  64  *                         in nv_start_rx, clean up a bit.
  65  *      0.20: 07 Dec 2003: alloc fixes
  66  *      0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
  67  *      0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
  68  *                         on close.
  69  *      0.23: 26 Jan 2004: various small cleanups
  70  *      0.24: 27 Feb 2004: make driver even less anonymous in backtraces
  71  *      0.25: 09 Mar 2004: wol support
  72  *      0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
  73  *      0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
  74  *                         added CK804/MCP04 device IDs, code fixes
  75  *                         for registers, link status and other minor fixes.
  76  *      0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
  77  *      0.29: 31 Aug 2004: Add backup timer for link change notification.
  78  *      0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
  79  *                         into nv_close, otherwise reenabling for wol can
  80  *                         cause DMA to kfree'd memory.
  81  *      0.31: 14 Nov 2004: ethtool support for getting/setting link
  82  *                         capabilities.
  83  *      0.32: 16 Apr 2005: RX_ERROR4 handling added.
  84  *      0.33: 16 May 2005: Support for MCP51 added.
  85  *      0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
  86  *      0.35: 26 Jun 2005: Support for MCP55 added.
  87  *      0.36: 28 Jun 2005: Add jumbo frame support.
  88  *      0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
  89  *      0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
  90  *                         per-packet flags.
  91  *      0.39: 18 Jul 2005: Add 64bit descriptor support.
  92  *      0.40: 19 Jul 2005: Add support for mac address change.
  93  *      0.41: 30 Jul 2005: Write back original MAC in nv_close instead
  94  *                         of nv_remove
  95  *      0.42: 06 Aug 2005: Fix lack of link speed initialization
  96  *                         in the second (and later) nv_open call
  97  *      0.43: 10 Aug 2005: Add support for tx checksum.
  98  *      0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
  99  *      0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
 100  *      0.46: 20 Oct 2005: Add irq optimization modes.
 101  *      0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
 102  *      0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
 103  *      0.49: 10 Dec 2005: Fix tso for large buffers.
 104  *      0.50: 20 Jan 2006: Add 8021pq tagging support.
 105  *      0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
 106  *      0.52: 20 Jan 2006: Add MSI/MSIX support.
 107  *      0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.
 108  *      0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.
 109  *      0.55: 22 Mar 2006: Add flow control (pause frame).
 110  *      0.56: 22 Mar 2006: Additional ethtool config and moduleparam support.
 111  *      0.57: 14 May 2006: Mac address set in probe/remove and order corrections.
 112  *      0.58: 30 Oct 2006: Added support for sideband management unit.
 113  *      0.59: 30 Oct 2006: Added support for recoverable error.
 114  *      0.60: 20 Jan 2007: Code optimizations for rings, rx & tx data paths, and stats.
 115  *
 116  * Known bugs:
 117  * We suspect that on some hardware no TX done interrupts are generated.
 118  * This means recovery from netif_stop_queue only happens if the hw timer
 119  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
 120  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
 121  * If your hardware reliably generates tx done interrupts, then you can remove
 122  * DEV_NEED_TIMERIRQ from the driver_data flags.
 123  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
 124  * superfluous timer interrupts from the nic.
 125  */
 126 #ifdef CONFIG_FORCEDETH_NAPI
 127 #define DRIVERNAPI "-NAPI"
 128 #else
 129 #define DRIVERNAPI
 130 #endif
 131 #define FORCEDETH_VERSION               "0.60"
 132 #define DRV_NAME                        "forcedeth"
 133
 134 #include <linux/module.h>
 135 #include <linux/types.h>
 136 #include <linux/pci.h>
 137 #include <linux/interrupt.h>
 138 #include <linux/netdevice.h>
 139 #include <linux/etherdevice.h>
 140 #include <linux/delay.h>
 141 #include <linux/spinlock.h>
 142 #include <linux/ethtool.h>
 143 #include <linux/timer.h>
 144 #include <linux/skbuff.h>
 145 #include <linux/mii.h>
 146 #include <linux/random.h>
 147 #include <linux/init.h>
 148 #include <linux/if_vlan.h>
 149 #include <linux/dma-mapping.h>
 150
 151 #include <asm/irq.h>
 152 #include <asm/io.h>
 153 #include <asm/uaccess.h>
 154 #include <asm/system.h>
 155
 156 #if 0
 157 #define dprintk                 printk
 158 #else
 159 #define dprintk(x...)           do { } while (0)
 160 #endif
 161
 162
 163 /*
 164  * Hardware access:
 165  */
 166
 167 #define DEV_NEED_TIMERIRQ       0x0001  /* set the timer irq flag in the irq mask */
 168 #define DEV_NEED_LINKTIMER      0x0002  /* poll link settings. Relies on the timer irq */
 169 #define DEV_HAS_LARGEDESC       0x0004  /* device supports jumbo frames and needs packet format 2 */
 170 #define DEV_HAS_HIGH_DMA        0x0008  /* device supports 64bit dma */
 171 #define DEV_HAS_CHECKSUM        0x0010  /* device supports tx and rx checksum offloads */
 172 #define DEV_HAS_VLAN            0x0020  /* device supports vlan tagging and striping */
 173 #define DEV_HAS_MSI             0x0040  /* device supports MSI */
 174 #define DEV_HAS_MSI_X           0x0080  /* device supports MSI-X */
 175 #define DEV_HAS_POWER_CNTRL     0x0100  /* device supports power savings */
 176 #define DEV_HAS_PAUSEFRAME_TX   0x0200  /* device supports tx pause frames */
 177 #define DEV_HAS_STATISTICS_V1   0x0400  /* device supports hw statistics version 1 */
 178 #define DEV_HAS_STATISTICS_V2   0x0800  /* device supports hw statistics version 2 */
 179 #define DEV_HAS_TEST_EXTENDED   0x1000  /* device supports extended diagnostic test */
 180 #define DEV_HAS_MGMT_UNIT       0x2000  /* device supports management unit */
 181
 182 enum {
 183         NvRegIrqStatus = 0x000,
 184 #define NVREG_IRQSTAT_MIIEVENT  0x040
 185 #define NVREG_IRQSTAT_MASK              0x81ff
 186         NvRegIrqMask = 0x004,
 187 #define NVREG_IRQ_RX_ERROR              0x0001
 188 #define NVREG_IRQ_RX                    0x0002
 189 #define NVREG_IRQ_RX_NOBUF              0x0004
 190 #define NVREG_IRQ_TX_ERR                0x0008
 191 #define NVREG_IRQ_TX_OK                 0x0010
 192 #define NVREG_IRQ_TIMER                 0x0020
 193 #define NVREG_IRQ_LINK                  0x0040
 194 #define NVREG_IRQ_RX_FORCED             0x0080
 195 #define NVREG_IRQ_TX_FORCED             0x0100
 196 #define NVREG_IRQ_RECOVER_ERROR         0x8000
 197 #define NVREG_IRQMASK_THROUGHPUT        0x00df
 198 #define NVREG_IRQMASK_CPU               0x0060
 199 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
 200 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
 201 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
 202
 203 #define NVREG_IRQ_UNKNOWN       (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
 204                                         NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
 205                                         NVREG_IRQ_TX_FORCED|NVREG_IRQ_RECOVER_ERROR))
 206
 207         NvRegUnknownSetupReg6 = 0x008,
 208 #define NVREG_UNKSETUP6_VAL             3
 209
 210 /*
 211  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
 212  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
 213  */
 214         NvRegPollingInterval = 0x00c,
 215 #define NVREG_POLL_DEFAULT_THROUGHPUT   970 /* backup tx cleanup if loop max reached */
 216 #define NVREG_POLL_DEFAULT_CPU  13
 217         NvRegMSIMap0 = 0x020,
 218         NvRegMSIMap1 = 0x024,
 219         NvRegMSIIrqMask = 0x030,
 220 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
 221         NvRegMisc1 = 0x080,
 222 #define NVREG_MISC1_PAUSE_TX    0x01
 223 #define NVREG_MISC1_HD          0x02
 224 #define NVREG_MISC1_FORCE       0x3b0f3c
 225
 226         NvRegMacReset = 0x3c,
 227 #define NVREG_MAC_RESET_ASSERT  0x0F3
 228         NvRegTransmitterControl = 0x084,
 229 #define NVREG_XMITCTL_START     0x01
 230 #define NVREG_XMITCTL_MGMT_ST   0x40000000
 231 #define NVREG_XMITCTL_SYNC_MASK         0x000f0000
 232 #define NVREG_XMITCTL_SYNC_NOT_READY    0x0
 233 #define NVREG_XMITCTL_SYNC_PHY_INIT     0x00040000
 234 #define NVREG_XMITCTL_MGMT_SEMA_MASK    0x00000f00
 235 #define NVREG_XMITCTL_MGMT_SEMA_FREE    0x0
 236 #define NVREG_XMITCTL_HOST_SEMA_MASK    0x0000f000
 237 #define NVREG_XMITCTL_HOST_SEMA_ACQ     0x0000f000
 238 #define NVREG_XMITCTL_HOST_LOADED       0x00004000
 239 #define NVREG_XMITCTL_TX_PATH_EN        0x01000000
 240         NvRegTransmitterStatus = 0x088,
 241 #define NVREG_XMITSTAT_BUSY     0x01
 242
 243         NvRegPacketFilterFlags = 0x8c,
 244 #define NVREG_PFF_PAUSE_RX      0x08
 245 #define NVREG_PFF_ALWAYS        0x7F0000
 246 #define NVREG_PFF_PROMISC       0x80
 247 #define NVREG_PFF_MYADDR        0x20
 248 #define NVREG_PFF_LOOPBACK      0x10
 249
 250         NvRegOffloadConfig = 0x90,
 251 #define NVREG_OFFLOAD_HOMEPHY   0x601
 252 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
 253         NvRegReceiverControl = 0x094,
 254 #define NVREG_RCVCTL_START      0x01
 255 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
 256         NvRegReceiverStatus = 0x98,
 257 #define NVREG_RCVSTAT_BUSY      0x01
 258
 259         NvRegRandomSeed = 0x9c,
 260 #define NVREG_RNDSEED_MASK      0x00ff
 261 #define NVREG_RNDSEED_FORCE     0x7f00
 262 #define NVREG_RNDSEED_FORCE2    0x2d00
 263 #define NVREG_RNDSEED_FORCE3    0x7400
 264
 265         NvRegTxDeferral = 0xA0,
 266 #define NVREG_TX_DEFERRAL_DEFAULT       0x15050f
 267 #define NVREG_TX_DEFERRAL_RGMII_10_100  0x16070f
 268 #define NVREG_TX_DEFERRAL_RGMII_1000    0x14050f
 269         NvRegRxDeferral = 0xA4,
 270 #define NVREG_RX_DEFERRAL_DEFAULT       0x16
 271         NvRegMacAddrA = 0xA8,
 272         NvRegMacAddrB = 0xAC,
 273         NvRegMulticastAddrA = 0xB0,
 274 #define NVREG_MCASTADDRA_FORCE  0x01
 275         NvRegMulticastAddrB = 0xB4,
 276         NvRegMulticastMaskA = 0xB8,
 277         NvRegMulticastMaskB = 0xBC,
 278
 279         NvRegPhyInterface = 0xC0,
 280 #define PHY_RGMII               0x10000000
 281
 282         NvRegTxRingPhysAddr = 0x100,
 283         NvRegRxRingPhysAddr = 0x104,
 284         NvRegRingSizes = 0x108,
 285 #define NVREG_RINGSZ_TXSHIFT 0
 286 #define NVREG_RINGSZ_RXSHIFT 16
 287         NvRegTransmitPoll = 0x10c,
 288 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
 289         NvRegLinkSpeed = 0x110,
 290 #define NVREG_LINKSPEED_FORCE 0x10000
 291 #define NVREG_LINKSPEED_10      1000
 292 #define NVREG_LINKSPEED_100     100
 293 #define NVREG_LINKSPEED_1000    50
 294 #define NVREG_LINKSPEED_MASK    (0xFFF)
 295         NvRegUnknownSetupReg5 = 0x130,
 296 #define NVREG_UNKSETUP5_BIT31   (1<<31)
 297         NvRegTxWatermark = 0x13c,
 298 #define NVREG_TX_WM_DESC1_DEFAULT       0x0200010
 299 #define NVREG_TX_WM_DESC2_3_DEFAULT     0x1e08000
 300 #define NVREG_TX_WM_DESC2_3_1000        0xfe08000
 301         NvRegTxRxControl = 0x144,
 302 #define NVREG_TXRXCTL_KICK      0x0001
 303 #define NVREG_TXRXCTL_BIT1      0x0002
 304 #define NVREG_TXRXCTL_BIT2      0x0004
 305 #define NVREG_TXRXCTL_IDLE      0x0008
 306 #define NVREG_TXRXCTL_RESET     0x0010
 307 #define NVREG_TXRXCTL_RXCHECK   0x0400
 308 #define NVREG_TXRXCTL_DESC_1    0
 309 #define NVREG_TXRXCTL_DESC_2    0x002100
 310 #define NVREG_TXRXCTL_DESC_3    0xc02200
 311 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
 312 #define NVREG_TXRXCTL_VLANINS   0x00080
 313         NvRegTxRingPhysAddrHigh = 0x148,
 314         NvRegRxRingPhysAddrHigh = 0x14C,
 315         NvRegTxPauseFrame = 0x170,
 316 #define NVREG_TX_PAUSEFRAME_DISABLE     0x1ff0080
 317 #define NVREG_TX_PAUSEFRAME_ENABLE      0x0c00030
 318         NvRegMIIStatus = 0x180,
 319 #define NVREG_MIISTAT_ERROR             0x0001
 320 #define NVREG_MIISTAT_LINKCHANGE        0x0008
 321 #define NVREG_MIISTAT_MASK              0x000f
 322 #define NVREG_MIISTAT_MASK2             0x000f
 323         NvRegMIIMask = 0x184,
 324 #define NVREG_MII_LINKCHANGE            0x0008
 325
 326         NvRegAdapterControl = 0x188,
 327 #define NVREG_ADAPTCTL_START    0x02
 328 #define NVREG_ADAPTCTL_LINKUP   0x04
 329 #define NVREG_ADAPTCTL_PHYVALID 0x40000
 330 #define NVREG_ADAPTCTL_RUNNING  0x100000
 331 #define NVREG_ADAPTCTL_PHYSHIFT 24
 332         NvRegMIISpeed = 0x18c,
 333 #define NVREG_MIISPEED_BIT8     (1<<8)
 334 #define NVREG_MIIDELAY  5
 335         NvRegMIIControl = 0x190,
 336 #define NVREG_MIICTL_INUSE      0x08000
 337 #define NVREG_MIICTL_WRITE      0x00400
 338 #define NVREG_MIICTL_ADDRSHIFT  5
 339         NvRegMIIData = 0x194,
 340         NvRegWakeUpFlags = 0x200,
 341 #define NVREG_WAKEUPFLAGS_VAL           0x7770
 342 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
 343 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
 344 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
 345 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
 346 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
 347 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
 348 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
 349 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
 350 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
 351 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
 352
 353         NvRegPatternCRC = 0x204,
 354         NvRegPatternMask = 0x208,
 355         NvRegPowerCap = 0x268,
 356 #define NVREG_POWERCAP_D3SUPP   (1<<30)
 357 #define NVREG_POWERCAP_D2SUPP   (1<<26)
 358 #define NVREG_POWERCAP_D1SUPP   (1<<25)
 359         NvRegPowerState = 0x26c,
 360 #define NVREG_POWERSTATE_POWEREDUP      0x8000
 361 #define NVREG_POWERSTATE_VALID          0x0100
 362 #define NVREG_POWERSTATE_MASK           0x0003
 363 #define NVREG_POWERSTATE_D0             0x0000
 364 #define NVREG_POWERSTATE_D1             0x0001
 365 #define NVREG_POWERSTATE_D2             0x0002
 366 #define NVREG_POWERSTATE_D3             0x0003
 367         NvRegTxCnt = 0x280,
 368         NvRegTxZeroReXmt = 0x284,
 369         NvRegTxOneReXmt = 0x288,
 370         NvRegTxManyReXmt = 0x28c,
 371         NvRegTxLateCol = 0x290,
 372         NvRegTxUnderflow = 0x294,
 373         NvRegTxLossCarrier = 0x298,
 374         NvRegTxExcessDef = 0x29c,
 375         NvRegTxRetryErr = 0x2a0,
 376         NvRegRxFrameErr = 0x2a4,
 377         NvRegRxExtraByte = 0x2a8,
 378         NvRegRxLateCol = 0x2ac,
 379         NvRegRxRunt = 0x2b0,
 380         NvRegRxFrameTooLong = 0x2b4,
 381         NvRegRxOverflow = 0x2b8,
 382         NvRegRxFCSErr = 0x2bc,
 383         NvRegRxFrameAlignErr = 0x2c0,
 384         NvRegRxLenErr = 0x2c4,
 385         NvRegRxUnicast = 0x2c8,
 386         NvRegRxMulticast = 0x2cc,
 387         NvRegRxBroadcast = 0x2d0,
 388         NvRegTxDef = 0x2d4,
 389         NvRegTxFrame = 0x2d8,
 390         NvRegRxCnt = 0x2dc,
 391         NvRegTxPause = 0x2e0,
 392         NvRegRxPause = 0x2e4,
 393         NvRegRxDropFrame = 0x2e8,
 394         NvRegVlanControl = 0x300,
 395 #define NVREG_VLANCONTROL_ENABLE        0x2000
 396         NvRegMSIXMap0 = 0x3e0,
 397         NvRegMSIXMap1 = 0x3e4,
 398         NvRegMSIXIrqStatus = 0x3f0,
 399
 400         NvRegPowerState2 = 0x600,
 401 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F11
 402 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
 403 };
 404
 405 /* Big endian: should work, but is untested */
 406 struct ring_desc {
 407         __le32 buf;
 408         __le32 flaglen;
 409 };
 410
 411 struct ring_desc_ex {
 412         __le32 bufhigh;
 413         __le32 buflow;
 414         __le32 txvlan;
 415         __le32 flaglen;
 416 };
 417
 418 union ring_type {
 419         struct ring_desc* orig;
 420         struct ring_desc_ex* ex;
 421 };
 422
 423 #define FLAG_MASK_V1 0xffff0000
 424 #define FLAG_MASK_V2 0xffffc000
 425 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
 426 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
 427
 428 #define NV_TX_LASTPACKET        (1<<16)
 429 #define NV_TX_RETRYERROR        (1<<19)
 430 #define NV_TX_FORCED_INTERRUPT  (1<<24)
 431 #define NV_TX_DEFERRED          (1<<26)
 432 #define NV_TX_CARRIERLOST       (1<<27)
 433 #define NV_TX_LATECOLLISION     (1<<28)
 434 #define NV_TX_UNDERFLOW         (1<<29)
 435 #define NV_TX_ERROR             (1<<30)
 436 #define NV_TX_VALID             (1<<31)
 437
 438 #define NV_TX2_LASTPACKET       (1<<29)
 439 #define NV_TX2_RETRYERROR       (1<<18)
 440 #define NV_TX2_FORCED_INTERRUPT (1<<30)
 441 #define NV_TX2_DEFERRED         (1<<25)
 442 #define NV_TX2_CARRIERLOST      (1<<26)
 443 #define NV_TX2_LATECOLLISION    (1<<27)
 444 #define NV_TX2_UNDERFLOW        (1<<28)
 445 /* error and valid are the same for both */
 446 #define NV_TX2_ERROR            (1<<30)
 447 #define NV_TX2_VALID            (1<<31)
 448 #define NV_TX2_TSO              (1<<28)
 449 #define NV_TX2_TSO_SHIFT        14
 450 #define NV_TX2_TSO_MAX_SHIFT    14
 451 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
 452 #define NV_TX2_CHECKSUM_L3      (1<<27)
 453 #define NV_TX2_CHECKSUM_L4      (1<<26)
 454
 455 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
 456
 457 #define NV_RX_DESCRIPTORVALID   (1<<16)
 458 #define NV_RX_MISSEDFRAME       (1<<17)
 459 #define NV_RX_SUBSTRACT1        (1<<18)
 460 #define NV_RX_ERROR1            (1<<23)
 461 #define NV_RX_ERROR2            (1<<24)
 462 #define NV_RX_ERROR3            (1<<25)
 463 #define NV_RX_ERROR4            (1<<26)
 464 #define NV_RX_CRCERR            (1<<27)
 465 #define NV_RX_OVERFLOW          (1<<28)
 466 #define NV_RX_FRAMINGERR        (1<<29)
 467 #define NV_RX_ERROR             (1<<30)
 468 #define NV_RX_AVAIL             (1<<31)
 469
 470 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
 471 #define NV_RX2_CHECKSUMOK1      (0x10000000)
 472 #define NV_RX2_CHECKSUMOK2      (0x14000000)
 473 #define NV_RX2_CHECKSUMOK3      (0x18000000)
 474 #define NV_RX2_DESCRIPTORVALID  (1<<29)
 475 #define NV_RX2_SUBSTRACT1       (1<<25)
 476 #define NV_RX2_ERROR1           (1<<18)
 477 #define NV_RX2_ERROR2           (1<<19)
 478 #define NV_RX2_ERROR3           (1<<20)
 479 #define NV_RX2_ERROR4           (1<<21)
 480 #define NV_RX2_CRCERR           (1<<22)
 481 #define NV_RX2_OVERFLOW         (1<<23)
 482 #define NV_RX2_FRAMINGERR       (1<<24)
 483 /* error and avail are the same for both */
 484 #define NV_RX2_ERROR            (1<<30)
 485 #define NV_RX2_AVAIL            (1<<31)
 486
 487 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
 488 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
 489
 490 /* Miscelaneous hardware related defines: */
 491 #define NV_PCI_REGSZ_VER1       0x270
 492 #define NV_PCI_REGSZ_VER2       0x2d4
 493 #define NV_PCI_REGSZ_VER3       0x604
 494
 495 /* various timeout delays: all in usec */
 496 #define NV_TXRX_RESET_DELAY     4
 497 #define NV_TXSTOP_DELAY1        10
 498 #define NV_TXSTOP_DELAY1MAX     500000
 499 #define NV_TXSTOP_DELAY2        100
 500 #define NV_RXSTOP_DELAY1        10
 501 #define NV_RXSTOP_DELAY1MAX     500000
 502 #define NV_RXSTOP_DELAY2        100
 503 #define NV_SETUP5_DELAY         5
 504 #define NV_SETUP5_DELAYMAX      50000
 505 #define NV_POWERUP_DELAY        5
 506 #define NV_POWERUP_DELAYMAX     5000
 507 #define NV_MIIBUSY_DELAY        50
 508 #define NV_MIIPHY_DELAY 10
 509 #define NV_MIIPHY_DELAYMAX      10000
 510 #define NV_MAC_RESET_DELAY      64
 511
 512 #define NV_WAKEUPPATTERNS       5
 513 #define NV_WAKEUPMASKENTRIES    4
 514
 515 /* General driver defaults */
 516 #define NV_WATCHDOG_TIMEO       (5*HZ)
 517
 518 #define RX_RING_DEFAULT         128
 519 #define TX_RING_DEFAULT         256
 520 #define RX_RING_MIN             128
 521 #define TX_RING_MIN             64
 522 #define RING_MAX_DESC_VER_1     1024
 523 #define RING_MAX_DESC_VER_2_3   16384
 524
 525 /* rx/tx mac addr + type + vlan + align + slack*/
 526 #define NV_RX_HEADERS           (64)
 527 /* even more slack. */
 528 #define NV_RX_ALLOC_PAD         (64)
 529
 530 /* maximum mtu size */
 531 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
 532 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
 533
 534 #define OOM_REFILL      (1+HZ/20)
 535 #define POLL_WAIT       (1+HZ/100)
 536 #define LINK_TIMEOUT    (3*HZ)
 537 #define STATS_INTERVAL  (10*HZ)
 538
 539 /*
 540  * desc_ver values:
 541  * The nic supports three different descriptor types:
 542  * - DESC_VER_1: Original
 543  * - DESC_VER_2: support for jumbo frames.
 544  * - DESC_VER_3: 64-bit format.
 545  */
 546 #define DESC_VER_1      1
 547 #define DESC_VER_2      2
 548 #define DESC_VER_3      3
 549
 550 /* PHY defines */
 551 #define PHY_OUI_MARVELL 0x5043
 552 #define PHY_OUI_CICADA  0x03f1
 553 #define PHYID1_OUI_MASK 0x03ff
 554 #define PHYID1_OUI_SHFT 6
 555 #define PHYID2_OUI_MASK 0xfc00
 556 #define PHYID2_OUI_SHFT 10
 557 #define PHYID2_MODEL_MASK               0x03f0
 558 #define PHY_MODEL_MARVELL_E3016         0x220
 559 #define PHY_MARVELL_E3016_INITMASK      0x0300
 560 #define PHY_INIT1       0x0f000
 561 #define PHY_INIT2       0x0e00
 562 #define PHY_INIT3       0x01000
 563 #define PHY_INIT4       0x0200
 564 #define PHY_INIT5       0x0004
 565 #define PHY_INIT6       0x02000
 566 #define PHY_GIGABIT     0x0100
 567
 568 #define PHY_TIMEOUT     0x1
 569 #define PHY_ERROR       0x2
 570
 571 #define PHY_100 0x1
 572 #define PHY_1000        0x2
 573 #define PHY_HALF        0x100
 574
 575 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
 576 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
 577 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
 578 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
 579 #define NV_PAUSEFRAME_RX_REQ     0x0010
 580 #define NV_PAUSEFRAME_TX_REQ     0x0020
 581 #define NV_PAUSEFRAME_AUTONEG    0x0040
 582
 583 /* MSI/MSI-X defines */
 584 #define NV_MSI_X_MAX_VECTORS  8
 585 #define NV_MSI_X_VECTORS_MASK 0x000f
 586 #define NV_MSI_CAPABLE        0x0010
 587 #define NV_MSI_X_CAPABLE      0x0020
 588 #define NV_MSI_ENABLED        0x0040
 589 #define NV_MSI_X_ENABLED      0x0080
 590
 591 #define NV_MSI_X_VECTOR_ALL   0x0
 592 #define NV_MSI_X_VECTOR_RX    0x0
 593 #define NV_MSI_X_VECTOR_TX    0x1
 594 #define NV_MSI_X_VECTOR_OTHER 0x2
 595
 596 /* statistics */
 597 struct nv_ethtool_str {
 598         char name[ETH_GSTRING_LEN];
 599 };
 600
 601 static const struct nv_ethtool_str nv_estats_str[] = {
 602         { "tx_bytes" },
 603         { "tx_zero_rexmt" },
 604         { "tx_one_rexmt" },
 605         { "tx_many_rexmt" },
 606         { "tx_late_collision" },
 607         { "tx_fifo_errors" },
 608         { "tx_carrier_errors" },
 609         { "tx_excess_deferral" },
 610         { "tx_retry_error" },
 611         { "rx_frame_error" },
 612         { "rx_extra_byte" },
 613         { "rx_late_collision" },
 614         { "rx_runt" },
 615         { "rx_frame_too_long" },
 616         { "rx_over_errors" },
 617         { "rx_crc_errors" },
 618         { "rx_frame_align_error" },
 619         { "rx_length_error" },
 620         { "rx_unicast" },
 621         { "rx_multicast" },
 622         { "rx_broadcast" },
 623         { "rx_packets" },
 624         { "rx_errors_total" },
 625         { "tx_errors_total" },
 626
 627         /* version 2 stats */
 628         { "tx_deferral" },
 629         { "tx_packets" },
 630         { "rx_bytes" },
 631         { "tx_pause" },
 632         { "rx_pause" },
 633         { "rx_drop_frame" }
 634 };
 635
 636 struct nv_ethtool_stats {
 637         u64 tx_bytes;
 638         u64 tx_zero_rexmt;
 639         u64 tx_one_rexmt;
 640         u64 tx_many_rexmt;
 641         u64 tx_late_collision;
 642         u64 tx_fifo_errors;
 643         u64 tx_carrier_errors;
 644         u64 tx_excess_deferral;
 645         u64 tx_retry_error;
 646         u64 rx_frame_error;
 647         u64 rx_extra_byte;
 648         u64 rx_late_collision;
 649         u64 rx_runt;
 650         u64 rx_frame_too_long;
 651         u64 rx_over_errors;
 652         u64 rx_crc_errors;
 653         u64 rx_frame_align_error;
 654         u64 rx_length_error;
 655         u64 rx_unicast;
 656         u64 rx_multicast;
 657         u64 rx_broadcast;
 658         u64 rx_packets;
 659         u64 rx_errors_total;
 660         u64 tx_errors_total;
 661
 662         /* version 2 stats */
 663         u64 tx_deferral;
 664         u64 tx_packets;
 665         u64 rx_bytes;
 666         u64 tx_pause;
 667         u64 rx_pause;
 668         u64 rx_drop_frame;
 669 };
 670
 671 #define NV_DEV_STATISTICS_V2_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
 672 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
 673
 674 /* diagnostics */
 675 #define NV_TEST_COUNT_BASE 3
 676 #define NV_TEST_COUNT_EXTENDED 4
 677
 678 static const struct nv_ethtool_str nv_etests_str[] = {
 679         { "link      (online/offline)" },
 680         { "register  (offline)       " },
 681         { "interrupt (offline)       " },
 682         { "loopback  (offline)       " }
 683 };
 684
 685 struct register_test {
 686         __le32 reg;
 687         __le32 mask;
 688 };
 689
 690 static const struct register_test nv_registers_test[] = {
 691         { NvRegUnknownSetupReg6, 0x01 },
 692         { NvRegMisc1, 0x03c },
 693         { NvRegOffloadConfig, 0x03ff },
 694         { NvRegMulticastAddrA, 0xffffffff },
 695         { NvRegTxWatermark, 0x0ff },
 696         { NvRegWakeUpFlags, 0x07777 },
 697         { 0,0 }
 698 };
 699
 700 struct nv_skb_map {
 701         struct sk_buff *skb;
 702         dma_addr_t dma;
 703         unsigned int dma_len;
 704 };
 705
 706 /*
 707  * SMP locking:
 708  * All hardware access under dev->priv->lock, except the performance
 709  * critical parts:
 710  * - rx is (pseudo-) lockless: it relies on the single-threading provided
 711  *      by the arch code for interrupts.
 712  * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
 713  *      needs dev->priv->lock :-(
 714  * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
 715  */
 716
 717 /* in dev: base, irq */
 718 struct fe_priv {
 719         spinlock_t lock;
 720
 721         /* General data:
 722          * Locking: spin_lock(&np->lock); */
 723         struct net_device_stats stats;
 724         struct nv_ethtool_stats estats;
 725         int in_shutdown;
 726         u32 linkspeed;
 727         int duplex;
 728         int autoneg;
 729         int fixed_mode;
 730         int phyaddr;
 731         int wolenabled;
 732         unsigned int phy_oui;
 733         unsigned int phy_model;
 734         u16 gigabit;
 735         int intr_test;
 736         int recover_error;
 737
 738         /* General data: RO fields */
 739         dma_addr_t ring_addr;
 740         struct pci_dev *pci_dev;
 741         u32 orig_mac[2];
 742         u32 irqmask;
 743         u32 desc_ver;
 744         u32 txrxctl_bits;
 745         u32 vlanctl_bits;
 746         u32 driver_data;
 747         u32 register_size;
 748         int rx_csum;
 749         u32 mac_in_use;
 750
 751         void __iomem *base;
 752
 753         /* rx specific fields.
 754          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 755          */
 756         union ring_type get_rx, put_rx, first_rx, last_rx;
 757         struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
 758         struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
 759         struct nv_skb_map *rx_skb;
 760
 761         union ring_type rx_ring;
 762         unsigned int rx_buf_sz;
 763         unsigned int pkt_limit;
 764         struct timer_list oom_kick;
 765         struct timer_list nic_poll;
 766         struct timer_list stats_poll;
 767         u32 nic_poll_irq;
 768         int rx_ring_size;
 769
 770         /* media detection workaround.
 771          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 772          */
 773         int need_linktimer;
 774         unsigned long link_timeout;
 775         /*
 776          * tx specific fields.
 777          */
 778         union ring_type get_tx, put_tx, first_tx, last_tx;
 779         struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
 780         struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
 781         struct nv_skb_map *tx_skb;
 782
 783         union ring_type tx_ring;
 784         u32 tx_flags;
 785         int tx_ring_size;
 786         int tx_stop;
 787
 788         /* vlan fields */
 789         struct vlan_group *vlangrp;
 790
 791         /* msi/msi-x fields */
 792         u32 msi_flags;
 793         struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
 794
 795         /* flow control */
 796         u32 pause_flags;
 797 };
 798
 799 /*
 800  * Maximum number of loops until we assume that a bit in the irq mask
 801  * is stuck. Overridable with module param.
 802  */
 803 static int max_interrupt_work = 5;
 804
 805 /*
 806  * Optimization can be either throuput mode or cpu mode
 807  *
 808  * Throughput Mode: Every tx and rx packet will generate an interrupt.
 809  * CPU Mode: Interrupts are controlled by a timer.
 810  */
 811 enum {
 812         NV_OPTIMIZATION_MODE_THROUGHPUT,
 813         NV_OPTIMIZATION_MODE_CPU
 814 };
 815 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
 816
 817 /*
 818  * Poll interval for timer irq
 819  *
 820  * This interval determines how frequent an interrupt is generated.
 821  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
 822  * Min = 0, and Max = 65535
 823  */
 824 static int poll_interval = -1;
 825
 826 /*
 827  * MSI interrupts
 828  */
 829 enum {
 830         NV_MSI_INT_DISABLED,
 831         NV_MSI_INT_ENABLED
 832 };
 833 static int msi = NV_MSI_INT_ENABLED;
 834
 835 /*
 836  * MSIX interrupts
 837  */
 838 enum {
 839         NV_MSIX_INT_DISABLED,
 840         NV_MSIX_INT_ENABLED
 841 };
 842 static int msix = NV_MSIX_INT_DISABLED;
 843
 844 /*
 845  * DMA 64bit
 846  */
 847 enum {
 848         NV_DMA_64BIT_DISABLED,
 849         NV_DMA_64BIT_ENABLED
 850 };
 851 static int dma_64bit = NV_DMA_64BIT_ENABLED;
 852
 853 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
 854 {
 855         return netdev_priv(dev);
 856 }
 857
 858 static inline u8 __iomem *get_hwbase(struct net_device *dev)
 859 {
 860         return ((struct fe_priv *)netdev_priv(dev))->base;
 861 }
 862
 863 static inline void pci_push(u8 __iomem *base)
 864 {
 865         /* force out pending posted writes */
 866         readl(base);
 867 }
 868
 869 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
 870 {
 871         return le32_to_cpu(prd->flaglen)
 872                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
 873 }
 874
 875 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
 876 {
 877         return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
 878 }
 879
 880 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
 881                                 int delay, int delaymax, const char *msg)
 882 {
 883         u8 __iomem *base = get_hwbase(dev);
 884
 885         pci_push(base);
 886         do {
 887                 udelay(delay);
 888                 delaymax -= delay;
 889                 if (delaymax < 0) {
 890                         if (msg)
 891                                 printk(msg);
 892                         return 1;
 893                 }
 894         } while ((readl(base + offset) & mask) != target);
 895         return 0;
 896 }
 897
 898 #define NV_SETUP_RX_RING 0x01
 899 #define NV_SETUP_TX_RING 0x02
 900
 901 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
 902 {
 903         struct fe_priv *np = get_nvpriv(dev);
 904         u8 __iomem *base = get_hwbase(dev);
 905
 906         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
 907                 if (rxtx_flags & NV_SETUP_RX_RING) {
 908                         writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
 909                 }
 910                 if (rxtx_flags & NV_SETUP_TX_RING) {
 911                         writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
 912                 }
 913         } else {
 914                 if (rxtx_flags & NV_SETUP_RX_RING) {
 915                         writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
 916                         writel((u32) (cpu_to_le64(np->ring_addr) >> 32), base + NvRegRxRingPhysAddrHigh);
 917                 }
 918                 if (rxtx_flags & NV_SETUP_TX_RING) {
 919                         writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
 920                         writel((u32) (cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)) >> 32), base + NvRegTxRingPhysAddrHigh);
 921                 }
 922         }
 923 }
 924
 925 static void free_rings(struct net_device *dev)
 926 {
 927         struct fe_priv *np = get_nvpriv(dev);
 928
 929         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
 930                 if (np->rx_ring.orig)
 931                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
 932                                             np->rx_ring.orig, np->ring_addr);
 933         } else {
 934                 if (np->rx_ring.ex)
 935                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
 936                                             np->rx_ring.ex, np->ring_addr);
 937         }
 938         if (np->rx_skb)
 939                 kfree(np->rx_skb);
 940         if (np->tx_skb)
 941                 kfree(np->tx_skb);
 942 }
 943
 944 static int using_multi_irqs(struct net_device *dev)
 945 {
 946         struct fe_priv *np = get_nvpriv(dev);
 947
 948         if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
 949             ((np->msi_flags & NV_MSI_X_ENABLED) &&
 950              ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
 951                 return 0;
 952         else
 953                 return 1;
 954 }
 955
 956 static void nv_enable_irq(struct net_device *dev)
 957 {
 958         struct fe_priv *np = get_nvpriv(dev);
 959
 960         if (!using_multi_irqs(dev)) {
 961                 if (np->msi_flags & NV_MSI_X_ENABLED)
 962                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
 963                 else
 964                         enable_irq(dev->irq);
 965         } else {
 966                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
 967                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
 968                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
 969         }
 970 }
 971
 972 static void nv_disable_irq(struct net_device *dev)
 973 {
 974         struct fe_priv *np = get_nvpriv(dev);
 975
 976         if (!using_multi_irqs(dev)) {
 977                 if (np->msi_flags & NV_MSI_X_ENABLED)
 978                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
 979                 else
 980                         disable_irq(dev->irq);
 981         } else {
 982                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
 983                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
 984                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
 985         }
 986 }
 987
 988 /* In MSIX mode, a write to irqmask behaves as XOR */
 989 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
 990 {
 991         u8 __iomem *base = get_hwbase(dev);
 992
 993         writel(mask, base + NvRegIrqMask);
 994 }
 995
 996 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
 997 {
 998         struct fe_priv *np = get_nvpriv(dev);
 999         u8 __iomem *base = get_hwbase(dev);
1000
1001         if (np->msi_flags & NV_MSI_X_ENABLED) {
1002                 writel(mask, base + NvRegIrqMask);
1003         } else {
1004                 if (np->msi_flags & NV_MSI_ENABLED)
1005                         writel(0, base + NvRegMSIIrqMask);
1006                 writel(0, base + NvRegIrqMask);
1007         }
1008 }
1009
1010 #define MII_READ        (-1)
1011 /* mii_rw: read/write a register on the PHY.
1012  *
1013  * Caller must guarantee serialization
1014  */
1015 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1016 {
1017         u8 __iomem *base = get_hwbase(dev);
1018         u32 reg;
1019         int retval;
1020
1021         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1022
1023         reg = readl(base + NvRegMIIControl);
1024         if (reg & NVREG_MIICTL_INUSE) {
1025                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1026                 udelay(NV_MIIBUSY_DELAY);
1027         }
1028
1029         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1030         if (value != MII_READ) {
1031                 writel(value, base + NvRegMIIData);
1032                 reg |= NVREG_MIICTL_WRITE;
1033         }
1034         writel(reg, base + NvRegMIIControl);
1035
1036         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1037                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1038                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1039                                 dev->name, miireg, addr);
1040                 retval = -1;
1041         } else if (value != MII_READ) {
1042                 /* it was a write operation - fewer failures are detectable */
1043                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1044                                 dev->name, value, miireg, addr);
1045                 retval = 0;
1046         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1047                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1048                                 dev->name, miireg, addr);
1049                 retval = -1;
1050         } else {
1051                 retval = readl(base + NvRegMIIData);
1052                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1053                                 dev->name, miireg, addr, retval);
1054         }
1055
1056         return retval;
1057 }
1058
1059 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1060 {
1061         struct fe_priv *np = netdev_priv(dev);
1062         u32 miicontrol;
1063         unsigned int tries = 0;
1064
1065         miicontrol = BMCR_RESET | bmcr_setup;
1066         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1067                 return -1;
1068         }
1069
1070         /* wait for 500ms */
1071         msleep(500);
1072
1073         /* must wait till reset is deasserted */
1074         while (miicontrol & BMCR_RESET) {
1075                 msleep(10);
1076                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1077                 /* FIXME: 100 tries seem excessive */
1078                 if (tries++ > 100)
1079                         return -1;
1080         }
1081         return 0;
1082 }
1083
1084 static int phy_init(struct net_device *dev)
1085 {
1086         struct fe_priv *np = get_nvpriv(dev);
1087         u8 __iomem *base = get_hwbase(dev);
1088         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1089
1090         /* phy errata for E3016 phy */
1091         if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1092                 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1093                 reg &= ~PHY_MARVELL_E3016_INITMASK;
1094                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1095                         printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1096                         return PHY_ERROR;
1097                 }
1098         }
1099
1100         /* set advertise register */
1101         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1102         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1103         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1104                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1105                 return PHY_ERROR;
1106         }
1107
1108         /* get phy interface type */
1109         phyinterface = readl(base + NvRegPhyInterface);
1110
1111         /* see if gigabit phy */
1112         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1113         if (mii_status & PHY_GIGABIT) {
1114                 np->gigabit = PHY_GIGABIT;
1115                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1116                 mii_control_1000 &= ~ADVERTISE_1000HALF;
1117                 if (phyinterface & PHY_RGMII)
1118                         mii_control_1000 |= ADVERTISE_1000FULL;
1119                 else
1120                         mii_control_1000 &= ~ADVERTISE_1000FULL;
1121
1122                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1123                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1124                         return PHY_ERROR;
1125                 }
1126         }
1127         else
1128                 np->gigabit = 0;
1129
1130         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1131         mii_control |= BMCR_ANENABLE;
1132
1133         /* reset the phy
1134          * (certain phys need bmcr to be setup with reset)
1135          */
1136         if (phy_reset(dev, mii_control)) {
1137                 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1138                 return PHY_ERROR;
1139         }
1140
1141         /* phy vendor specific configuration */
1142         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1143                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1144                 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
1145                 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
1146                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1147                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1148                         return PHY_ERROR;
1149                 }
1150                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1151                 phy_reserved |= PHY_INIT5;
1152                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1153                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1154                         return PHY_ERROR;
1155                 }
1156         }
1157         if (np->phy_oui == PHY_OUI_CICADA) {
1158                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1159                 phy_reserved |= PHY_INIT6;
1160                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1161                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1162                         return PHY_ERROR;
1163                 }
1164         }
1165         /* some phys clear out pause advertisment on reset, set it back */
1166         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1167
1168         /* restart auto negotiation */
1169         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1170         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1171         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1172                 return PHY_ERROR;
1173         }
1174
1175         return 0;
1176 }
1177
1178 static void nv_start_rx(struct net_device *dev)
1179 {
1180         struct fe_priv *np = netdev_priv(dev);
1181         u8 __iomem *base = get_hwbase(dev);
1182         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1183
1184         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1185         /* Already running? Stop it. */
1186         if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1187                 rx_ctrl &= ~NVREG_RCVCTL_START;
1188                 writel(rx_ctrl, base + NvRegReceiverControl);
1189                 pci_push(base);
1190         }
1191         writel(np->linkspeed, base + NvRegLinkSpeed);
1192         pci_push(base);
1193         rx_ctrl |= NVREG_RCVCTL_START;
1194         if (np->mac_in_use)
1195                 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1196         writel(rx_ctrl, base + NvRegReceiverControl);
1197         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1198                                 dev->name, np->duplex, np->linkspeed);
1199         pci_push(base);
1200 }
1201
1202 static void nv_stop_rx(struct net_device *dev)
1203 {
1204         struct fe_priv *np = netdev_priv(dev);
1205         u8 __iomem *base = get_hwbase(dev);
1206         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1207
1208         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1209         if (!np->mac_in_use)
1210                 rx_ctrl &= ~NVREG_RCVCTL_START;
1211         else
1212                 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1213         writel(rx_ctrl, base + NvRegReceiverControl);
1214         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1215                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1216                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1217
1218         udelay(NV_RXSTOP_DELAY2);
1219         if (!np->mac_in_use)
1220                 writel(0, base + NvRegLinkSpeed);
1221 }
1222
1223 static void nv_start_tx(struct net_device *dev)
1224 {
1225         struct fe_priv *np = netdev_priv(dev);
1226         u8 __iomem *base = get_hwbase(dev);
1227         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1228
1229         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1230         tx_ctrl |= NVREG_XMITCTL_START;
1231         if (np->mac_in_use)
1232                 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1233         writel(tx_ctrl, base + NvRegTransmitterControl);
1234         pci_push(base);
1235 }
1236
1237 static void nv_stop_tx(struct net_device *dev)
1238 {
1239         struct fe_priv *np = netdev_priv(dev);
1240         u8 __iomem *base = get_hwbase(dev);
1241         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1242
1243         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1244         if (!np->mac_in_use)
1245                 tx_ctrl &= ~NVREG_XMITCTL_START;
1246         else
1247                 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1248         writel(tx_ctrl, base + NvRegTransmitterControl);
1249         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1250                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1251                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1252
1253         udelay(NV_TXSTOP_DELAY2);
1254         if (!np->mac_in_use)
1255                 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1256                        base + NvRegTransmitPoll);
1257 }
1258
1259 static void nv_txrx_reset(struct net_device *dev)
1260 {
1261         struct fe_priv *np = netdev_priv(dev);
1262         u8 __iomem *base = get_hwbase(dev);
1263
1264         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1265         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1266         pci_push(base);
1267         udelay(NV_TXRX_RESET_DELAY);
1268         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1269         pci_push(base);
1270 }
1271
1272 static void nv_mac_reset(struct net_device *dev)
1273 {
1274         struct fe_priv *np = netdev_priv(dev);
1275         u8 __iomem *base = get_hwbase(dev);
1276
1277         dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1278         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1279         pci_push(base);
1280         writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1281         pci_push(base);
1282         udelay(NV_MAC_RESET_DELAY);
1283         writel(0, base + NvRegMacReset);
1284         pci_push(base);
1285         udelay(NV_MAC_RESET_DELAY);
1286         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1287         pci_push(base);
1288 }
1289
1290 static void nv_get_hw_stats(struct net_device *dev)
1291 {
1292         struct fe_priv *np = netdev_priv(dev);
1293         u8 __iomem *base = get_hwbase(dev);
1294
1295         np->estats.tx_bytes += readl(base + NvRegTxCnt);
1296         np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1297         np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1298         np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1299         np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1300         np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1301         np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1302         np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1303         np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1304         np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1305         np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1306         np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1307         np->estats.rx_runt += readl(base + NvRegRxRunt);
1308         np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1309         np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1310         np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1311         np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1312         np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1313         np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1314         np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1315         np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1316         np->estats.rx_packets =
1317                 np->estats.rx_unicast +
1318                 np->estats.rx_multicast +
1319                 np->estats.rx_broadcast;
1320         np->estats.rx_errors_total =
1321                 np->estats.rx_crc_errors +
1322                 np->estats.rx_over_errors +
1323                 np->estats.rx_frame_error +
1324                 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1325                 np->estats.rx_late_collision +
1326                 np->estats.rx_runt +
1327                 np->estats.rx_frame_too_long;
1328         np->estats.tx_errors_total =
1329                 np->estats.tx_late_collision +
1330                 np->estats.tx_fifo_errors +
1331                 np->estats.tx_carrier_errors +
1332                 np->estats.tx_excess_deferral +
1333                 np->estats.tx_retry_error;
1334
1335         if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1336                 np->estats.tx_deferral += readl(base + NvRegTxDef);
1337                 np->estats.tx_packets += readl(base + NvRegTxFrame);
1338                 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1339                 np->estats.tx_pause += readl(base + NvRegTxPause);
1340                 np->estats.rx_pause += readl(base + NvRegRxPause);
1341                 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1342         }
1343 }
1344
1345 /*
1346  * nv_get_stats: dev->get_stats function
1347  * Get latest stats value from the nic.
1348  * Called with read_lock(&dev_base_lock) held for read -
1349  * only synchronized against unregister_netdevice.
1350  */
1351 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1352 {
1353         struct fe_priv *np = netdev_priv(dev);
1354
1355         /* If the nic supports hw counters then retrieve latest values */
1356         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2)) {
1357                 nv_get_hw_stats(dev);
1358
1359                 /* copy to net_device stats */
1360                 np->stats.tx_bytes = np->estats.tx_bytes;
1361                 np->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1362                 np->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1363                 np->stats.rx_crc_errors = np->estats.rx_crc_errors;
1364                 np->stats.rx_over_errors = np->estats.rx_over_errors;
1365                 np->stats.rx_errors = np->estats.rx_errors_total;
1366                 np->stats.tx_errors = np->estats.tx_errors_total;
1367         }
1368         return &np->stats;
1369 }
1370
1371 /*
1372  * nv_alloc_rx: fill rx ring entries.
1373  * Return 1 if the allocations for the skbs failed and the
1374  * rx engine is without Available descriptors
1375  */
1376 static int nv_alloc_rx(struct net_device *dev)
1377 {
1378         struct fe_priv *np = netdev_priv(dev);
1379         struct ring_desc* less_rx;
1380
1381         less_rx = np->get_rx.orig;
1382         if (less_rx-- == np->first_rx.orig)
1383                 less_rx = np->last_rx.orig;
1384
1385         while (np->put_rx.orig != less_rx) {
1386                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1387                 if (skb) {
1388                         np->put_rx_ctx->skb = skb;
1389                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1390                                                              skb->data,
1391                                                              skb_tailroom(skb),
1392                                                              PCI_DMA_FROMDEVICE);
1393                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1394                         np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1395                         wmb();
1396                         np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1397                         if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1398                                 np->put_rx.orig = np->first_rx.orig;
1399                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1400                                 np->put_rx_ctx = np->first_rx_ctx;
1401                 } else {
1402                         return 1;
1403                 }
1404         }
1405         return 0;
1406 }
1407
1408 static int nv_alloc_rx_optimized(struct net_device *dev)
1409 {
1410         struct fe_priv *np = netdev_priv(dev);
1411         struct ring_desc_ex* less_rx;
1412
1413         less_rx = np->get_rx.ex;
1414         if (less_rx-- == np->first_rx.ex)
1415                 less_rx = np->last_rx.ex;
1416
1417         while (np->put_rx.ex != less_rx) {
1418                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1419                 if (skb) {
1420                         np->put_rx_ctx->skb = skb;
1421                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1422                                                              skb->data,
1423                                                              skb_tailroom(skb),
1424                                                              PCI_DMA_FROMDEVICE);
1425                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1426                         np->put_rx.ex->bufhigh = cpu_to_le64(np->put_rx_ctx->dma) >> 32;
1427                         np->put_rx.ex->buflow = cpu_to_le64(np->put_rx_ctx->dma) & 0x0FFFFFFFF;
1428                         wmb();
1429                         np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1430                         if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1431                                 np->put_rx.ex = np->first_rx.ex;
1432                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1433                                 np->put_rx_ctx = np->first_rx_ctx;
1434                 } else {
1435                         return 1;
1436                 }
1437         }
1438         return 0;
1439 }
1440
1441 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1442 #ifdef CONFIG_FORCEDETH_NAPI
1443 static void nv_do_rx_refill(unsigned long data)
1444 {
1445         struct net_device *dev = (struct net_device *) data;
1446
1447         /* Just reschedule NAPI rx processing */
1448         netif_rx_schedule(dev);
1449 }
1450 #else
1451 static void nv_do_rx_refill(unsigned long data)
1452 {
1453         struct net_device *dev = (struct net_device *) data;
1454         struct fe_priv *np = netdev_priv(dev);
1455         int retcode;
1456
1457         if (!using_multi_irqs(dev)) {
1458                 if (np->msi_flags & NV_MSI_X_ENABLED)
1459                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1460                 else
1461                         disable_irq(dev->irq);
1462         } else {
1463                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1464         }
1465         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1466                 retcode = nv_alloc_rx(dev);
1467         else
1468                 retcode = nv_alloc_rx_optimized(dev);
1469         if (retcode) {
1470                 spin_lock_irq(&np->lock);
1471                 if (!np->in_shutdown)
1472                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1473                 spin_unlock_irq(&np->lock);
1474         }
1475         if (!using_multi_irqs(dev)) {
1476                 if (np->msi_flags & NV_MSI_X_ENABLED)
1477                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1478                 else
1479                         enable_irq(dev->irq);
1480         } else {
1481                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1482         }
1483 }
1484 #endif
1485
1486 static void nv_init_rx(struct net_device *dev)
1487 {
1488         struct fe_priv *np = netdev_priv(dev);
1489         int i;
1490         np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1491         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1492                 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1493         else
1494                 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1495         np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1496         np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1497
1498         for (i = 0; i < np->rx_ring_size; i++) {
1499                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1500                         np->rx_ring.orig[i].flaglen = 0;
1501                         np->rx_ring.orig[i].buf = 0;
1502                 } else {
1503                         np->rx_ring.ex[i].flaglen = 0;
1504                         np->rx_ring.ex[i].txvlan = 0;
1505                         np->rx_ring.ex[i].bufhigh = 0;
1506                         np->rx_ring.ex[i].buflow = 0;
1507                 }
1508                 np->rx_skb[i].skb = NULL;
1509                 np->rx_skb[i].dma = 0;
1510         }
1511 }
1512
1513 static void nv_init_tx(struct net_device *dev)
1514 {
1515         struct fe_priv *np = netdev_priv(dev);
1516         int i;
1517         np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1518         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1519                 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1520         else
1521                 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1522         np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1523         np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1524
1525         for (i = 0; i < np->tx_ring_size; i++) {
1526                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1527                         np->tx_ring.orig[i].flaglen = 0;
1528                         np->tx_ring.orig[i].buf = 0;
1529                 } else {
1530                         np->tx_ring.ex[i].flaglen = 0;
1531                         np->tx_ring.ex[i].txvlan = 0;
1532                         np->tx_ring.ex[i].bufhigh = 0;
1533                         np->tx_ring.ex[i].buflow = 0;
1534                 }
1535                 np->tx_skb[i].skb = NULL;
1536                 np->tx_skb[i].dma = 0;
1537         }
1538 }
1539
1540 static int nv_init_ring(struct net_device *dev)
1541 {
1542         struct fe_priv *np = netdev_priv(dev);
1543
1544         nv_init_tx(dev);
1545         nv_init_rx(dev);
1546         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1547                 return nv_alloc_rx(dev);
1548         else
1549                 return nv_alloc_rx_optimized(dev);
1550 }
1551
1552 static int nv_release_txskb(struct net_device *dev, struct nv_skb_map* tx_skb)
1553 {
1554         struct fe_priv *np = netdev_priv(dev);
1555
1556         if (tx_skb->dma) {
1557                 pci_unmap_page(np->pci_dev, tx_skb->dma,
1558                                tx_skb->dma_len,
1559                                PCI_DMA_TODEVICE);
1560                 tx_skb->dma = 0;
1561         }
1562         if (tx_skb->skb) {
1563                 dev_kfree_skb_any(tx_skb->skb);
1564                 tx_skb->skb = NULL;
1565                 return 1;
1566         } else {
1567                 return 0;
1568         }
1569 }
1570
1571 static void nv_drain_tx(struct net_device *dev)
1572 {
1573         struct fe_priv *np = netdev_priv(dev);
1574         unsigned int i;
1575
1576         for (i = 0; i < np->tx_ring_size; i++) {
1577                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1578                         np->tx_ring.orig[i].flaglen = 0;
1579                         np->tx_ring.orig[i].buf = 0;
1580                 } else {
1581                         np->tx_ring.ex[i].flaglen = 0;
1582                         np->tx_ring.ex[i].txvlan = 0;
1583                         np->tx_ring.ex[i].bufhigh = 0;
1584                         np->tx_ring.ex[i].buflow = 0;
1585                 }
1586                 if (nv_release_txskb(dev, &np->tx_skb[i]))
1587                         np->stats.tx_dropped++;
1588         }
1589 }
1590
1591 static void nv_drain_rx(struct net_device *dev)
1592 {
1593         struct fe_priv *np = netdev_priv(dev);
1594         int i;
1595
1596         for (i = 0; i < np->rx_ring_size; i++) {
1597                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1598                         np->rx_ring.orig[i].flaglen = 0;
1599                         np->rx_ring.orig[i].buf = 0;
1600                 } else {
1601                         np->rx_ring.ex[i].flaglen = 0;
1602                         np->rx_ring.ex[i].txvlan = 0;
1603                         np->rx_ring.ex[i].bufhigh = 0;
1604                         np->rx_ring.ex[i].buflow = 0;
1605                 }
1606                 wmb();
1607                 if (np->rx_skb[i].skb) {
1608                         pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
1609                                          (skb_end_pointer(np->rx_skb[i].skb) -
1610                                           np->rx_skb[i].skb->data),
1611                                          PCI_DMA_FROMDEVICE);
1612                         dev_kfree_skb(np->rx_skb[i].skb);
1613                         np->rx_skb[i].skb = NULL;
1614                 }
1615         }
1616 }
1617
1618 static void drain_ring(struct net_device *dev)
1619 {
1620         nv_drain_tx(dev);
1621         nv_drain_rx(dev);
1622 }
1623
1624 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1625 {
1626         return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1627 }
1628
1629 /*
1630  * nv_start_xmit: dev->hard_start_xmit function
1631  * Called with netif_tx_lock held.
1632  */
1633 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1634 {
1635         struct fe_priv *np = netdev_priv(dev);
1636         u32 tx_flags = 0;
1637         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
1638         unsigned int fragments = skb_shinfo(skb)->nr_frags;
1639         unsigned int i;
1640         u32 offset = 0;
1641         u32 bcnt;
1642         u32 size = skb->len-skb->data_len;
1643         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1644         u32 empty_slots;
1645         struct ring_desc* put_tx;
1646         struct ring_desc* start_tx;
1647         struct ring_desc* prev_tx;
1648         struct nv_skb_map* prev_tx_ctx;
1649
1650         /* add fragments to entries count */
1651         for (i = 0; i < fragments; i++) {
1652                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1653                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1654         }
1655
1656         empty_slots = nv_get_empty_tx_slots(np);
1657         if (unlikely(empty_slots <= entries)) {
1658                 spin_lock_irq(&np->lock);
1659                 netif_stop_queue(dev);
1660                 np->tx_stop = 1;
1661                 spin_unlock_irq(&np->lock);
1662                 return NETDEV_TX_BUSY;
1663         }
1664
1665         start_tx = put_tx = np->put_tx.orig;
1666
1667         /* setup the header buffer */
1668         do {
1669                 prev_tx = put_tx;
1670                 prev_tx_ctx = np->put_tx_ctx;
1671                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1672                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1673                                                 PCI_DMA_TODEVICE);
1674                 np->put_tx_ctx->dma_len = bcnt;
1675                 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
1676                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1677
1678                 tx_flags = np->tx_flags;
1679                 offset += bcnt;
1680                 size -= bcnt;
1681                 if (unlikely(put_tx++ == np->last_tx.orig))
1682                         put_tx = np->first_tx.orig;
1683                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1684                         np->put_tx_ctx = np->first_tx_ctx;
1685         } while (size);
1686
1687         /* setup the fragments */
1688         for (i = 0; i < fragments; i++) {
1689                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1690                 u32 size = frag->size;
1691                 offset = 0;
1692
1693                 do {
1694                         prev_tx = put_tx;
1695                         prev_tx_ctx = np->put_tx_ctx;
1696                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1697                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1698                                                            PCI_DMA_TODEVICE);
1699                         np->put_tx_ctx->dma_len = bcnt;
1700                         put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
1701                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1702
1703                         offset += bcnt;
1704                         size -= bcnt;
1705                         if (unlikely(put_tx++ == np->last_tx.orig))
1706                                 put_tx = np->first_tx.orig;
1707                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1708                                 np->put_tx_ctx = np->first_tx_ctx;
1709                 } while (size);
1710         }
1711
1712         /* set last fragment flag  */
1713         prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
1714
1715         /* save skb in this slot's context area */
1716         prev_tx_ctx->skb = skb;
1717
1718         if (skb_is_gso(skb))
1719                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
1720         else
1721                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
1722                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
1723
1724         spin_lock_irq(&np->lock);
1725
1726         /* set tx flags */
1727         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1728         np->put_tx.orig = put_tx;
1729
1730         spin_unlock_irq(&np->lock);
1731
1732         dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
1733                 dev->name, entries, tx_flags_extra);
1734         {
1735                 int j;
1736                 for (j=0; j<64; j++) {
1737                         if ((j%16) == 0)
1738                                 dprintk("\n%03x:", j);
1739                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1740                 }
1741                 dprintk("\n");
1742         }
1743
1744         dev->trans_start = jiffies;
1745         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1746         return NETDEV_TX_OK;
1747 }
1748
1749 static int nv_start_xmit_optimized(struct sk_buff *skb, struct net_device *dev)
1750 {
1751         struct fe_priv *np = netdev_priv(dev);
1752         u32 tx_flags = 0;
1753         u32 tx_flags_extra;
1754         unsigned int fragments = skb_shinfo(skb)->nr_frags;
1755         unsigned int i;
1756         u32 offset = 0;
1757         u32 bcnt;
1758         u32 size = skb->len-skb->data_len;
1759         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1760         u32 empty_slots;
1761         struct ring_desc_ex* put_tx;
1762         struct ring_desc_ex* start_tx;
1763         struct ring_desc_ex* prev_tx;
1764         struct nv_skb_map* prev_tx_ctx;
1765
1766         /* add fragments to entries count */
1767         for (i = 0; i < fragments; i++) {
1768                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1769                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1770         }
1771
1772         empty_slots = nv_get_empty_tx_slots(np);
1773         if (unlikely(empty_slots <= entries)) {
1774                 spin_lock_irq(&np->lock);
1775                 netif_stop_queue(dev);
1776                 np->tx_stop = 1;
1777                 spin_unlock_irq(&np->lock);
1778                 return NETDEV_TX_BUSY;
1779         }
1780
1781         start_tx = put_tx = np->put_tx.ex;
1782
1783         /* setup the header buffer */
1784         do {
1785                 prev_tx = put_tx;
1786                 prev_tx_ctx = np->put_tx_ctx;
1787                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1788                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1789                                                 PCI_DMA_TODEVICE);
1790                 np->put_tx_ctx->dma_len = bcnt;
1791                 put_tx->bufhigh = cpu_to_le64(np->put_tx_ctx->dma) >> 32;
1792                 put_tx->buflow = cpu_to_le64(np->put_tx_ctx->dma) & 0x0FFFFFFFF;
1793                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1794
1795                 tx_flags = NV_TX2_VALID;
1796                 offset += bcnt;
1797                 size -= bcnt;
1798                 if (unlikely(put_tx++ == np->last_tx.ex))
1799                         put_tx = np->first_tx.ex;
1800                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1801                         np->put_tx_ctx = np->first_tx_ctx;
1802         } while (size);
1803
1804         /* setup the fragments */
1805         for (i = 0; i < fragments; i++) {
1806                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1807                 u32 size = frag->size;
1808                 offset = 0;
1809
1810                 do {
1811                         prev_tx = put_tx;
1812                         prev_tx_ctx = np->put_tx_ctx;
1813                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1814                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1815                                                            PCI_DMA_TODEVICE);
1816                         np->put_tx_ctx->dma_len = bcnt;
1817                         put_tx->bufhigh = cpu_to_le64(np->put_tx_ctx->dma) >> 32;
1818                         put_tx->buflow = cpu_to_le64(np->put_tx_ctx->dma) & 0x0FFFFFFFF;
1819                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1820
1821                         offset += bcnt;
1822                         size -= bcnt;
1823                         if (unlikely(put_tx++ == np->last_tx.ex))
1824                                 put_tx = np->first_tx.ex;
1825                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1826                                 np->put_tx_ctx = np->first_tx_ctx;
1827                 } while (size);
1828         }
1829
1830         /* set last fragment flag  */
1831         prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
1832
1833         /* save skb in this slot's context area */
1834         prev_tx_ctx->skb = skb;
1835
1836         if (skb_is_gso(skb))
1837                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
1838         else
1839                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
1840                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
1841
1842         /* vlan tag */
1843         if (likely(!np->vlangrp)) {
1844                 start_tx->txvlan = 0;
1845         } else {
1846                 if (vlan_tx_tag_present(skb))
1847                         start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb));
1848                 else
1849                         start_tx->txvlan = 0;
1850         }
1851
1852         spin_lock_irq(&np->lock);
1853
1854         /* set tx flags */
1855         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1856         np->put_tx.ex = put_tx;
1857
1858         spin_unlock_irq(&np->lock);
1859
1860         dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
1861                 dev->name, entries, tx_flags_extra);
1862         {
1863                 int j;
1864                 for (j=0; j<64; j++) {
1865                         if ((j%16) == 0)
1866                                 dprintk("\n%03x:", j);
1867                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1868                 }
1869                 dprintk("\n");
1870         }
1871
1872         dev->trans_start = jiffies;
1873         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1874         return NETDEV_TX_OK;
1875 }
1876
1877 /*
1878  * nv_tx_done: check for completed packets, release the skbs.
1879  *
1880  * Caller must own np->lock.
1881  */
1882 static void nv_tx_done(struct net_device *dev)
1883 {
1884         struct fe_priv *np = netdev_priv(dev);
1885         u32 flags;
1886         struct ring_desc* orig_get_tx = np->get_tx.orig;
1887
1888         while ((np->get_tx.orig != np->put_tx.orig) &&
1889                !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID)) {
1890
1891                 dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
1892                                         dev->name, flags);
1893
1894                 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
1895                                np->get_tx_ctx->dma_len,
1896                                PCI_DMA_TODEVICE);
1897                 np->get_tx_ctx->dma = 0;
1898
1899                 if (np->desc_ver == DESC_VER_1) {
1900                         if (flags & NV_TX_LASTPACKET) {
1901                                 if (flags & NV_TX_ERROR) {
1902                                         if (flags & NV_TX_UNDERFLOW)
1903                                                 np->stats.tx_fifo_errors++;
1904                                         if (flags & NV_TX_CARRIERLOST)
1905                                                 np->stats.tx_carrier_errors++;
1906                                         np->stats.tx_errors++;
1907                                 } else {
1908                                         np->stats.tx_packets++;
1909                                         np->stats.tx_bytes += np->get_tx_ctx->skb->len;
1910                                 }
1911                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
1912                                 np->get_tx_ctx->skb = NULL;
1913                         }
1914                 } else {
1915                         if (flags & NV_TX2_LASTPACKET) {
1916                                 if (flags & NV_TX2_ERROR) {
1917                                         if (flags & NV_TX2_UNDERFLOW)
1918                                                 np->stats.tx_fifo_errors++;
1919                                         if (flags & NV_TX2_CARRIERLOST)
1920                                                 np->stats.tx_carrier_errors++;
1921                                         np->stats.tx_errors++;
1922                                 } else {
1923                                         np->stats.tx_packets++;
1924                                         np->stats.tx_bytes += np->get_tx_ctx->skb->len;
1925                                 }
1926                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
1927                                 np->get_tx_ctx->skb = NULL;
1928                         }
1929                 }
1930                 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
1931                         np->get_tx.orig = np->first_tx.orig;
1932                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
1933                         np->get_tx_ctx = np->first_tx_ctx;
1934         }
1935         if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
1936                 np->tx_stop = 0;
1937                 netif_wake_queue(dev);
1938         }
1939 }
1940
1941 static void nv_tx_done_optimized(struct net_device *dev, int limit)
1942 {
1943         struct fe_priv *np = netdev_priv(dev);
1944         u32 flags;
1945         struct ring_desc_ex* orig_get_tx = np->get_tx.ex;
1946
1947         while ((np->get_tx.ex != np->put_tx.ex) &&
1948                !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX_VALID) &&
1949                (limit-- > 0)) {
1950
1951                 dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n",
1952                                         dev->name, flags);
1953
1954                 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
1955                                np->get_tx_ctx->dma_len,
1956                                PCI_DMA_TODEVICE);
1957                 np->get_tx_ctx->dma = 0;
1958
1959                 if (flags & NV_TX2_LASTPACKET) {
1960                         if (!(flags & NV_TX2_ERROR))
1961                                 np->stats.tx_packets++;
1962                         dev_kfree_skb_any(np->get_tx_ctx->skb);
1963                         np->get_tx_ctx->skb = NULL;
1964                 }
1965                 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
1966                         np->get_tx.ex = np->first_tx.ex;
1967                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
1968                         np->get_tx_ctx = np->first_tx_ctx;
1969         }
1970         if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
1971                 np->tx_stop = 0;
1972                 netif_wake_queue(dev);
1973         }
1974 }
1975
1976 /*
1977  * nv_tx_timeout: dev->tx_timeout function
1978  * Called with netif_tx_lock held.
1979  */
1980 static void nv_tx_timeout(struct net_device *dev)
1981 {
1982         struct fe_priv *np = netdev_priv(dev);
1983         u8 __iomem *base = get_hwbase(dev);
1984         u32 status;
1985
1986         if (np->msi_flags & NV_MSI_X_ENABLED)
1987                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
1988         else
1989                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1990
1991         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
1992
1993         {
1994                 int i;
1995
1996                 printk(KERN_INFO "%s: Ring at %lx\n",
1997                        dev->name, (unsigned long)np->ring_addr);
1998                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
1999                 for (i=0;i<=np->register_size;i+= 32) {
2000                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2001                                         i,
2002                                         readl(base + i + 0), readl(base + i + 4),
2003                                         readl(base + i + 8), readl(base + i + 12),
2004                                         readl(base + i + 16), readl(base + i + 20),
2005                                         readl(base + i + 24), readl(base + i + 28));
2006                 }
2007                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
2008                 for (i=0;i<np->tx_ring_size;i+= 4) {
2009                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
2010                                 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2011                                        i,
2012                                        le32_to_cpu(np->tx_ring.orig[i].buf),
2013                                        le32_to_cpu(np->tx_ring.orig[i].flaglen),
2014                                        le32_to_cpu(np->tx_ring.orig[i+1].buf),
2015                                        le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2016                                        le32_to_cpu(np->tx_ring.orig[i+2].buf),
2017                                        le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2018                                        le32_to_cpu(np->tx_ring.orig[i+3].buf),
2019                                        le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2020                         } else {
2021                                 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2022                                        i,
2023                                        le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2024                                        le32_to_cpu(np->tx_ring.ex[i].buflow),
2025                                        le32_to_cpu(np->tx_ring.ex[i].flaglen),
2026                                        le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2027                                        le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2028                                        le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2029                                        le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2030                                        le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2031                                        le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2032                                        le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2033                                        le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2034                                        le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2035                         }
2036                 }
2037         }
2038
2039         spin_lock_irq(&np->lock);
2040
2041         /* 1) stop tx engine */
2042         nv_stop_tx(dev);
2043
2044         /* 2) check that the packets were not sent already: */
2045         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2046                 nv_tx_done(dev);
2047         else
2048                 nv_tx_done_optimized(dev, np->tx_ring_size);
2049
2050         /* 3) if there are dead entries: clear everything */
2051         if (np->get_tx_ctx != np->put_tx_ctx) {
2052                 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
2053                 nv_drain_tx(dev);
2054                 nv_init_tx(dev);
2055                 setup_hw_rings(dev, NV_SETUP_TX_RING);
2056         }
2057
2058         netif_wake_queue(dev);
2059
2060         /* 4) restart tx engine */
2061         nv_start_tx(dev);
2062         spin_unlock_irq(&np->lock);
2063 }
2064
2065 /*
2066  * Called when the nic notices a mismatch between the actual data len on the
2067  * wire and the len indicated in the 802 header
2068  */
2069 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2070 {
2071         int hdrlen;     /* length of the 802 header */
2072         int protolen;   /* length as stored in the proto field */
2073
2074         /* 1) calculate len according to header */
2075         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2076                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
2077                 hdrlen = VLAN_HLEN;
2078         } else {
2079                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
2080                 hdrlen = ETH_HLEN;
2081         }
2082         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
2083                                 dev->name, datalen, protolen, hdrlen);
2084         if (protolen > ETH_DATA_LEN)
2085                 return datalen; /* Value in proto field not a len, no checks possible */
2086
2087         protolen += hdrlen;
2088         /* consistency checks: */
2089         if (datalen > ETH_ZLEN) {
2090                 if (datalen >= protolen) {
2091                         /* more data on wire than in 802 header, trim of
2092                          * additional data.
2093                          */
2094                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2095                                         dev->name, protolen);
2096                         return protolen;
2097                 } else {
2098                         /* less data on wire than mentioned in header.
2099                          * Discard the packet.
2100                          */
2101                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
2102                                         dev->name);
2103                         return -1;
2104                 }
2105         } else {
2106                 /* short packet. Accept only if 802 values are also short */
2107                 if (protolen > ETH_ZLEN) {
2108                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
2109                                         dev->name);
2110                         return -1;
2111                 }
2112                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2113                                 dev->name, datalen);
2114                 return datalen;
2115         }
2116 }
2117
2118 static int nv_rx_process(struct net_device *dev, int limit)
2119 {
2120         struct fe_priv *np = netdev_priv(dev);
2121         u32 flags;
2122         u32 rx_processed_cnt = 0;
2123         struct sk_buff *skb;
2124         int len;
2125
2126         while((np->get_rx.orig != np->put_rx.orig) &&
2127               !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2128                 (rx_processed_cnt++ < limit)) {
2129
2130                 dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
2131                                         dev->name, flags);
2132
2133                 /*
2134                  * the packet is for us - immediately tear down the pci mapping.
2135                  * TODO: check if a prefetch of the first cacheline improves
2136                  * the performance.
2137                  */
2138                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2139                                 np->get_rx_ctx->dma_len,
2140                                 PCI_DMA_FROMDEVICE);
2141                 skb = np->get_rx_ctx->skb;
2142                 np->get_rx_ctx->skb = NULL;
2143
2144                 {
2145                         int j;
2146                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2147                         for (j=0; j<64; j++) {
2148                                 if ((j%16) == 0)
2149                                         dprintk("\n%03x:", j);
2150                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2151                         }
2152                         dprintk("\n");
2153                 }
2154                 /* look at what we actually got: */
2155                 if (np->desc_ver == DESC_VER_1) {
2156                         if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2157                                 len = flags & LEN_MASK_V1;
2158                                 if (unlikely(flags & NV_RX_ERROR)) {
2159                                         if (flags & NV_RX_ERROR4) {
2160                                                 len = nv_getlen(dev, skb->data, len);
2161                                                 if (len < 0) {
2162                                                         np->stats.rx_errors++;
2163                                                         dev_kfree_skb(skb);
2164                                                         goto next_pkt;
2165                                                 }
2166                                         }
2167                                         /* framing errors are soft errors */
2168                                         else if (flags & NV_RX_FRAMINGERR) {
2169                                                 if (flags & NV_RX_SUBSTRACT1) {
2170                                                         len--;
2171                                                 }
2172                                         }
2173                                         /* the rest are hard errors */
2174                                         else {
2175                                                 if (flags & NV_RX_MISSEDFRAME)
2176                                                         np->stats.rx_missed_errors++;
2177                                                 if (flags & NV_RX_CRCERR)
2178                                                         np->stats.rx_crc_errors++;
2179                                                 if (flags & NV_RX_OVERFLOW)
2180                                                         np->stats.rx_over_errors++;
2181                                                 np->stats.rx_errors++;
2182                                                 dev_kfree_skb(skb);
2183                                                 goto next_pkt;
2184                                         }
2185                                 }
2186                         } else {
2187                                 dev_kfree_skb(skb);
2188                                 goto next_pkt;
2189                         }
2190                 } else {
2191                         if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2192                                 len = flags & LEN_MASK_V2;
2193                                 if (unlikely(flags & NV_RX2_ERROR)) {
2194                                         if (flags & NV_RX2_ERROR4) {
2195                                                 len = nv_getlen(dev, skb->data, len);
2196                                                 if (len < 0) {
2197                                                         np->stats.rx_errors++;
2198                                                         dev_kfree_skb(skb);
2199                                                         goto next_pkt;
2200                                                 }
2201                                         }
2202                                         /* framing errors are soft errors */
2203                                         else if (flags & NV_RX2_FRAMINGERR) {
2204                                                 if (flags & NV_RX2_SUBSTRACT1) {
2205                                                         len--;
2206                                                 }
2207                                         }
2208                                         /* the rest are hard errors */
2209                                         else {
2210                                                 if (flags & NV_RX2_CRCERR)
2211                                                         np->stats.rx_crc_errors++;
2212                                                 if (flags & NV_RX2_OVERFLOW)
2213                                                         np->stats.rx_over_errors++;
2214                                                 np->stats.rx_errors++;
2215                                                 dev_kfree_skb(skb);
2216                                                 goto next_pkt;
2217                                         }
2218                                 }
2219                                 if ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK2)/*ip and tcp */ {
2220                                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2221                                 } else {
2222                                         if ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK1 ||
2223                                             (flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK3) {
2224                                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2225                                         }
2226                                 }
2227                         } else {
2228                                 dev_kfree_skb(skb);
2229                                 goto next_pkt;
2230                         }
2231                 }
2232                 /* got a valid packet - forward it to the network core */
2233                 skb_put(skb, len);
2234                 skb->protocol = eth_type_trans(skb, dev);
2235                 dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2236                                         dev->name, len, skb->protocol);
2237 #ifdef CONFIG_FORCEDETH_NAPI
2238                 netif_receive_skb(skb);
2239 #else
2240                 netif_rx(skb);
2241 #endif
2242                 dev->last_rx = jiffies;
2243                 np->stats.rx_packets++;
2244                 np->stats.rx_bytes += len;
2245 next_pkt:
2246                 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2247                         np->get_rx.orig = np->first_rx.orig;
2248                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2249                         np->get_rx_ctx = np->first_rx_ctx;
2250         }
2251
2252         return rx_processed_cnt;
2253 }
2254
2255 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2256 {
2257         struct fe_priv *np = netdev_priv(dev);
2258         u32 flags;
2259         u32 vlanflags = 0;
2260         u32 rx_processed_cnt = 0;
2261         struct sk_buff *skb;
2262         int len;
2263
2264         while((np->get_rx.ex != np->put_rx.ex) &&
2265               !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2266               (rx_processed_cnt++ < limit)) {
2267
2268                 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n",
2269                                         dev->name, flags);
2270
2271                 /*
2272                  * the packet is for us - immediately tear down the pci mapping.
2273                  * TODO: check if a prefetch of the first cacheline improves
2274                  * the performance.
2275                  */
2276                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2277                                 np->get_rx_ctx->dma_len,
2278                                 PCI_DMA_FROMDEVICE);
2279                 skb = np->get_rx_ctx->skb;
2280                 np->get_rx_ctx->skb = NULL;
2281
2282                 {
2283                         int j;
2284                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2285                         for (j=0; j<64; j++) {
2286                                 if ((j%16) == 0)
2287                                         dprintk("\n%03x:", j);
2288                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2289                         }
2290                         dprintk("\n");
2291                 }
2292                 /* look at what we actually got: */
2293                 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2294                         len = flags & LEN_MASK_V2;
2295                         if (unlikely(flags & NV_RX2_ERROR)) {
2296                                 if (flags & NV_RX2_ERROR4) {
2297                                         len = nv_getlen(dev, skb->data, len);
2298                                         if (len < 0) {
2299                                                 dev_kfree_skb(skb);
2300                                                 goto next_pkt;
2301                                         }
2302                                 }
2303                                 /* framing errors are soft errors */
2304                                 else if (flags & NV_RX2_FRAMINGERR) {
2305                                         if (flags & NV_RX2_SUBSTRACT1) {
2306                                                 len--;
2307                                         }
2308                                 }
2309                                 /* the rest are hard errors */
2310                                 else {
2311                                         dev_kfree_skb(skb);
2312                                         goto next_pkt;
2313                                 }
2314                         }
2315
2316                         if ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK2)/*ip and tcp */ {
2317                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2318                         } else {
2319                                 if ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK1 ||
2320                                     (flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK3) {
2321                                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2322                                 }
2323                         }
2324
2325                         /* got a valid packet - forward it to the network core */
2326                         skb_put(skb, len);
2327                         skb->protocol = eth_type_trans(skb, dev);
2328                         prefetch(skb->data);
2329
2330                         dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
2331                                 dev->name, len, skb->protocol);
2332
2333                         if (likely(!np->vlangrp)) {
2334 #ifdef CONFIG_FORCEDETH_NAPI
2335                                 netif_receive_skb(skb);
2336 #else
2337                                 netif_rx(skb);
2338 #endif
2339                         } else {
2340                                 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2341                                 if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2342 #ifdef CONFIG_FORCEDETH_NAPI
2343                                         vlan_hwaccel_receive_skb(skb, np->vlangrp,
2344                                                                  vlanflags & NV_RX3_VLAN_TAG_MASK);
2345 #else
2346                                         vlan_hwaccel_rx(skb, np->vlangrp,
2347                                                         vlanflags & NV_RX3_VLAN_TAG_MASK);
2348 #endif
2349                                 } else {
2350 #ifdef CONFIG_FORCEDETH_NAPI
2351                                         netif_receive_skb(skb);
2352 #else
2353                                         netif_rx(skb);
2354 #endif
2355                                 }
2356                         }
2357
2358                         dev->last_rx = jiffies;
2359                         np->stats.rx_packets++;
2360                         np->stats.rx_bytes += len;
2361                 } else {
2362                         dev_kfree_skb(skb);
2363                 }
2364 next_pkt:
2365                 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2366                         np->get_rx.ex = np->first_rx.ex;
2367                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2368                         np->get_rx_ctx = np->first_rx_ctx;
2369         }
2370
2371         return rx_processed_cnt;
2372 }
2373
2374 static void set_bufsize(struct net_device *dev)
2375 {
2376         struct fe_priv *np = netdev_priv(dev);
2377
2378         if (dev->mtu <= ETH_DATA_LEN)
2379                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2380         else
2381                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2382 }
2383
2384 /*
2385  * nv_change_mtu: dev->change_mtu function
2386  * Called with dev_base_lock held for read.
2387  */
2388 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2389 {
2390         struct fe_priv *np = netdev_priv(dev);
2391         int old_mtu;
2392
2393         if (new_mtu < 64 || new_mtu > np->pkt_limit)
2394                 return -EINVAL;
2395
2396         old_mtu = dev->mtu;
2397         dev->mtu = new_mtu;
2398
2399         /* return early if the buffer sizes will not change */
2400         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2401                 return 0;
2402         if (old_mtu == new_mtu)
2403                 return 0;
2404
2405         /* synchronized against open : rtnl_lock() held by caller */
2406         if (netif_running(dev)) {
2407                 u8 __iomem *base = get_hwbase(dev);
2408                 /*
2409                  * It seems that the nic preloads valid ring entries into an
2410                  * internal buffer. The procedure for flushing everything is
2411                  * guessed, there is probably a simpler approach.
2412                  * Changing the MTU is a rare event, it shouldn't matter.
2413                  */
2414                 nv_disable_irq(dev);
2415                 netif_tx_lock_bh(dev);
2416                 spin_lock(&np->lock);
2417                 /* stop engines */
2418                 nv_stop_rx(dev);
2419                 nv_stop_tx(dev);
2420                 nv_txrx_reset(dev);
2421                 /* drain rx queue */
2422                 nv_drain_rx(dev);
2423                 nv_drain_tx(dev);
2424                 /* reinit driver view of the rx queue */
2425                 set_bufsize(dev);
2426                 if (nv_init_ring(dev)) {
2427                         if (!np->in_shutdown)
2428                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2429                 }
2430                 /* reinit nic view of the rx queue */
2431                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2432                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2433                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2434                         base + NvRegRingSizes);
2435                 pci_push(base);
2436                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2437                 pci_push(base);
2438
2439                 /* restart rx engine */
2440                 nv_start_rx(dev);
2441                 nv_start_tx(dev);
2442                 spin_unlock(&np->lock);
2443                 netif_tx_unlock_bh(dev);
2444                 nv_enable_irq(dev);
2445         }
2446         return 0;
2447 }
2448
2449 static void nv_copy_mac_to_hw(struct net_device *dev)
2450 {
2451         u8 __iomem *base = get_hwbase(dev);
2452         u32 mac[2];
2453
2454         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2455                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2456         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2457
2458         writel(mac[0], base + NvRegMacAddrA);
2459         writel(mac[1], base + NvRegMacAddrB);
2460 }
2461
2462 /*
2463  * nv_set_mac_address: dev->set_mac_address function
2464  * Called with rtnl_lock() held.
2465  */
2466 static int nv_set_mac_address(struct net_device *dev, void *addr)
2467 {
2468         struct fe_priv *np = netdev_priv(dev);
2469         struct sockaddr *macaddr = (struct sockaddr*)addr;
2470
2471         if (!is_valid_ether_addr(macaddr->sa_data))
2472                 return -EADDRNOTAVAIL;
2473
2474         /* synchronized against open : rtnl_lock() held by caller */
2475         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2476
2477         if (netif_running(dev)) {
2478                 netif_tx_lock_bh(dev);
2479                 spin_lock_irq(&np->lock);
2480
2481                 /* stop rx engine */
2482                 nv_stop_rx(dev);
2483
2484                 /* set mac address */
2485                 nv_copy_mac_to_hw(dev);
2486
2487                 /* restart rx engine */
2488                 nv_start_rx(dev);
2489                 spin_unlock_irq(&np->lock);
2490                 netif_tx_unlock_bh(dev);
2491         } else {
2492                 nv_copy_mac_to_hw(dev);
2493         }
2494         return 0;
2495 }
2496
2497 /*
2498  * nv_set_multicast: dev->set_multicast function
2499  * Called with netif_tx_lock held.
2500  */
2501 static void nv_set_multicast(struct net_device *dev)
2502 {
2503         struct fe_priv *np = netdev_priv(dev);
2504         u8 __iomem *base = get_hwbase(dev);
2505         u32 addr[2];
2506         u32 mask[2];
2507         u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
2508
2509         memset(addr, 0, sizeof(addr));
2510         memset(mask, 0, sizeof(mask));
2511
2512         if (dev->flags & IFF_PROMISC) {
2513                 pff |= NVREG_PFF_PROMISC;
2514         } else {
2515                 pff |= NVREG_PFF_MYADDR;
2516
2517                 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
2518                         u32 alwaysOff[2];
2519                         u32 alwaysOn[2];
2520
2521                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
2522                         if (dev->flags & IFF_ALLMULTI) {
2523                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
2524                         } else {
2525                                 struct dev_mc_list *walk;
2526
2527                                 walk = dev->mc_list;
2528                                 while (walk != NULL) {
2529                                         u32 a, b;
2530                                         a = le32_to_cpu(*(u32 *) walk->dmi_addr);
2531                                         b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
2532                                         alwaysOn[0] &= a;
2533                                         alwaysOff[0] &= ~a;
2534                                         alwaysOn[1] &= b;
2535                                         alwaysOff[1] &= ~b;
2536                                         walk = walk->next;
2537                                 }
2538                         }
2539                         addr[0] = alwaysOn[0];
2540                         addr[1] = alwaysOn[1];
2541                         mask[0] = alwaysOn[0] | alwaysOff[0];
2542                         mask[1] = alwaysOn[1] | alwaysOff[1];
2543                 }
2544         }
2545         addr[0] |= NVREG_MCASTADDRA_FORCE;
2546         pff |= NVREG_PFF_ALWAYS;
2547         spin_lock_irq(&np->lock);
2548         nv_stop_rx(dev);
2549         writel(addr[0], base + NvRegMulticastAddrA);
2550         writel(addr[1], base + NvRegMulticastAddrB);
2551         writel(mask[0], base + NvRegMulticastMaskA);
2552         writel(mask[1], base + NvRegMulticastMaskB);
2553         writel(pff, base + NvRegPacketFilterFlags);
2554         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
2555                 dev->name);
2556         nv_start_rx(dev);
2557         spin_unlock_irq(&np->lock);
2558 }
2559
2560 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
2561 {
2562         struct fe_priv *np = netdev_priv(dev);
2563         u8 __iomem *base = get_hwbase(dev);
2564
2565         np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
2566
2567         if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
2568                 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
2569                 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
2570                         writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
2571                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2572                 } else {
2573                         writel(pff, base + NvRegPacketFilterFlags);
2574                 }
2575         }
2576         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
2577                 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
2578                 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
2579                         writel(NVREG_TX_PAUSEFRAME_ENABLE,  base + NvRegTxPauseFrame);
2580                         writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
2581                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2582                 } else {
2583                         writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
2584                         writel(regmisc, base + NvRegMisc1);
2585                 }
2586         }
2587 }
2588
2589 /**
2590  * nv_update_linkspeed: Setup the MAC according to the link partner
2591  * @dev: Network device to be configured
2592  *
2593  * The function queries the PHY and checks if there is a link partner.
2594  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
2595  * set to 10 MBit HD.
2596  *
2597  * The function returns 0 if there is no link partner and 1 if there is
2598  * a good link partner.
2599  */
2600 static int nv_update_linkspeed(struct net_device *dev)
2601 {
2602         struct fe_priv *np = netdev_priv(dev);
2603         u8 __iomem *base = get_hwbase(dev);
2604         int adv = 0;
2605         int lpa = 0;
2606         int adv_lpa, adv_pause, lpa_pause;
2607         int newls = np->linkspeed;
2608         int newdup = np->duplex;
2609         int mii_status;
2610         int retval = 0;
2611         u32 control_1000, status_1000, phyreg, pause_flags, txreg;
2612
2613         /* BMSR_LSTATUS is latched, read it twice:
2614          * we want the current value.
2615          */
2616         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2617         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2618
2619         if (!(mii_status & BMSR_LSTATUS)) {
2620                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
2621                                 dev->name);
2622                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2623                 newdup = 0;
2624                 retval = 0;
2625                 goto set_speed;
2626         }
2627
2628         if (np->autoneg == 0) {
2629                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
2630                                 dev->name, np->fixed_mode);
2631                 if (np->fixed_mode & LPA_100FULL) {
2632                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2633                         newdup = 1;
2634                 } else if (np->fixed_mode & LPA_100HALF) {
2635                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2636                         newdup = 0;
2637                 } else if (np->fixed_mode & LPA_10FULL) {
2638                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2639                         newdup = 1;
2640                 } else {
2641                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2642                         newdup = 0;
2643                 }
2644                 retval = 1;
2645                 goto set_speed;
2646         }
2647         /* check auto negotiation is complete */
2648         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
2649                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
2650                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2651                 newdup = 0;
2652                 retval = 0;
2653                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
2654                 goto set_speed;
2655         }
2656
2657         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2658         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
2659         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
2660                                 dev->name, adv, lpa);
2661
2662         retval = 1;
2663         if (np->gigabit == PHY_GIGABIT) {
2664                 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
2665                 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
2666
2667                 if ((control_1000 & ADVERTISE_1000FULL) &&
2668                         (status_1000 & LPA_1000FULL)) {
2669                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
2670                                 dev->name);
2671                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
2672                         newdup = 1;
2673                         goto set_speed;
2674                 }
2675         }
2676
2677         /* FIXME: handle parallel detection properly */
2678         adv_lpa = lpa & adv;
2679         if (adv_lpa & LPA_100FULL) {
2680                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2681                 newdup = 1;
2682         } else if (adv_lpa & LPA_100HALF) {
2683                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2684                 newdup = 0;
2685         } else if (adv_lpa & LPA_10FULL) {
2686                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2687                 newdup = 1;
2688         } else if (adv_lpa & LPA_10HALF) {
2689                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2690                 newdup = 0;
2691         } else {
2692                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
2693                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2694                 newdup = 0;
2695         }
2696
2697 set_speed:
2698         if (np->duplex == newdup && np->linkspeed == newls)
2699                 return retval;
2700
2701         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
2702                         dev->name, np->linkspeed, np->duplex, newls, newdup);
2703
2704         np->duplex = newdup;
2705         np->linkspeed = newls;
2706
2707         if (np->gigabit == PHY_GIGABIT) {
2708                 phyreg = readl(base + NvRegRandomSeed);
2709                 phyreg &= ~(0x3FF00);
2710                 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
2711                         phyreg |= NVREG_RNDSEED_FORCE3;
2712                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
2713                         phyreg |= NVREG_RNDSEED_FORCE2;
2714                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
2715                         phyreg |= NVREG_RNDSEED_FORCE;
2716                 writel(phyreg, base + NvRegRandomSeed);
2717         }
2718
2719         phyreg = readl(base + NvRegPhyInterface);
2720         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
2721         if (np->duplex == 0)
2722                 phyreg |= PHY_HALF;
2723         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
2724                 phyreg |= PHY_100;
2725         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2726                 phyreg |= PHY_1000;
2727         writel(phyreg, base + NvRegPhyInterface);
2728
2729         if (phyreg & PHY_RGMII) {
2730                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2731                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
2732                 else
2733                         txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
2734         } else {
2735                 txreg = NVREG_TX_DEFERRAL_DEFAULT;
2736         }
2737         writel(txreg, base + NvRegTxDeferral);
2738
2739         if (np->desc_ver == DESC_VER_1) {
2740                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
2741         } else {
2742                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2743                         txreg = NVREG_TX_WM_DESC2_3_1000;
2744                 else
2745                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
2746         }
2747         writel(txreg, base + NvRegTxWatermark);
2748
2749         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
2750                 base + NvRegMisc1);
2751         pci_push(base);
2752         writel(np->linkspeed, base + NvRegLinkSpeed);
2753         pci_push(base);
2754
2755         pause_flags = 0;
2756         /* setup pause frame */
2757         if (np->duplex != 0) {
2758                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
2759                         adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
2760                         lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
2761
2762                         switch (adv_pause) {
2763                         case ADVERTISE_PAUSE_CAP:
2764                                 if (lpa_pause & LPA_PAUSE_CAP) {
2765                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2766                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2767                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2768                                 }
2769                                 break;
2770                         case ADVERTISE_PAUSE_ASYM:
2771                                 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
2772                                 {
2773                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2774                                 }
2775                                 break;
2776                         case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
2777                                 if (lpa_pause & LPA_PAUSE_CAP)
2778                                 {
2779                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
2780                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2781                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2782                                 }
2783                                 if (lpa_pause == LPA_PAUSE_ASYM)
2784                                 {
2785                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2786                                 }
2787                                 break;
2788                         }
2789                 } else {
2790                         pause_flags = np->pause_flags;
2791                 }
2792         }
2793         nv_update_pause(dev, pause_flags);
2794
2795         return retval;
2796 }
2797
2798 static void nv_linkchange(struct net_device *dev)
2799 {
2800         if (nv_update_linkspeed(dev)) {
2801                 if (!netif_carrier_ok(dev)) {
2802                         netif_carrier_on(dev);
2803                         printk(KERN_INFO "%s: link up.\n", dev->name);
2804                         nv_start_rx(dev);
2805                 }
2806         } else {
2807                 if (netif_carrier_ok(dev)) {
2808                         netif_carrier_off(dev);
2809                         printk(KERN_INFO "%s: link down.\n", dev->name);
2810                         nv_stop_rx(dev);
2811                 }
2812         }
2813 }
2814
2815 static void nv_link_irq(struct net_device *dev)
2816 {
2817         u8 __iomem *base = get_hwbase(dev);
2818         u32 miistat;
2819
2820         miistat = readl(base + NvRegMIIStatus);
2821         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
2822         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
2823
2824         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
2825                 nv_linkchange(dev);
2826         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
2827 }
2828
2829 static irqreturn_t nv_nic_irq(int foo, void *data)
2830 {
2831         struct net_device *dev = (struct net_device *) data;
2832         struct fe_priv *np = netdev_priv(dev);
2833         u8 __iomem *base = get_hwbase(dev);
2834         u32 events;
2835         int i;
2836
2837         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
2838
2839         for (i=0; ; i++) {
2840                 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2841                         events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2842                         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2843                 } else {
2844                         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2845                         writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
2846                 }
2847                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2848                 if (!(events & np->irqmask))
2849                         break;
2850
2851                 spin_lock(&np->lock);
2852                 nv_tx_done(dev);
2853                 spin_unlock(&np->lock);
2854
2855 #ifdef CONFIG_FORCEDETH_NAPI
2856                 if (events & NVREG_IRQ_RX_ALL) {
2857                         netif_rx_schedule(dev);
2858
2859                         /* Disable furthur receive irq's */
2860                         spin_lock(&np->lock);
2861                         np->irqmask &= ~NVREG_IRQ_RX_ALL;
2862
2863                         if (np->msi_flags & NV_MSI_X_ENABLED)
2864                                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2865                         else
2866                                 writel(np->irqmask, base + NvRegIrqMask);
2867                         spin_unlock(&np->lock);
2868                 }
2869 #else
2870                 if (nv_rx_process(dev, dev->weight)) {
2871                         if (unlikely(nv_alloc_rx(dev))) {
2872                                 spin_lock(&np->lock);
2873                                 if (!np->in_shutdown)
2874                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2875                                 spin_unlock(&np->lock);
2876                         }
2877                 }
2878 #endif
2879                 if (unlikely(events & NVREG_IRQ_LINK)) {
2880                         spin_lock(&np->lock);
2881                         nv_link_irq(dev);
2882                         spin_unlock(&np->lock);
2883                 }
2884                 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
2885                         spin_lock(&np->lock);
2886                         nv_linkchange(dev);
2887                         spin_unlock(&np->lock);
2888                         np->link_timeout = jiffies + LINK_TIMEOUT;
2889                 }
2890                 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
2891                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2892                                                 dev->name, events);
2893                 }
2894                 if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
2895                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2896                                                 dev->name, events);
2897                 }
2898                 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
2899                         spin_lock(&np->lock);
2900                         /* disable interrupts on the nic */
2901                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
2902                                 writel(0, base + NvRegIrqMask);
2903                         else
2904                                 writel(np->irqmask, base + NvRegIrqMask);
2905                         pci_push(base);
2906
2907                         if (!np->in_shutdown) {
2908                                 np->nic_poll_irq = np->irqmask;
2909                                 np->recover_error = 1;
2910                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2911                         }
2912                         spin_unlock(&np->lock);
2913                         break;
2914                 }
2915                 if (unlikely(i > max_interrupt_work)) {
2916                         spin_lock(&np->lock);
2917                         /* disable interrupts on the nic */
2918                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
2919                                 writel(0, base + NvRegIrqMask);
2920                         else
2921                                 writel(np->irqmask, base + NvRegIrqMask);
2922                         pci_push(base);
2923
2924                         if (!np->in_shutdown) {
2925                                 np->nic_poll_irq = np->irqmask;
2926                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2927                         }
2928                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
2929                         spin_unlock(&np->lock);
2930                         break;
2931                 }
2932
2933         }
2934         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
2935
2936         return IRQ_RETVAL(i);
2937 }
2938
2939 #define TX_WORK_PER_LOOP  64
2940 #define RX_WORK_PER_LOOP  64
2941 /**
2942  * All _optimized functions are used to help increase performance
2943  * (reduce CPU and increase throughput). They use descripter version 3,
2944  * compiler directives, and reduce memory accesses.
2945  */
2946 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
2947 {
2948         struct net_device *dev = (struct net_device *) data;
2949         struct fe_priv *np = netdev_priv(dev);
2950         u8 __iomem *base = get_hwbase(dev);
2951         u32 events;
2952         int i;
2953
2954         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name);
2955
2956         for (i=0; ; i++) {
2957                 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2958                         events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2959                         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2960                 } else {
2961                         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2962                         writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
2963                 }
2964                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2965                 if (!(events & np->irqmask))
2966                         break;
2967
2968                 spin_lock(&np->lock);
2969                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
2970                 spin_unlock(&np->lock);
2971
2972 #ifdef CONFIG_FORCEDETH_NAPI
2973                 if (events & NVREG_IRQ_RX_ALL) {
2974                         netif_rx_schedule(dev);
2975
2976                         /* Disable furthur receive irq's */
2977                         spin_lock(&np->lock);
2978                         np->irqmask &= ~NVREG_IRQ_RX_ALL;
2979
2980                         if (np->msi_flags & NV_MSI_X_ENABLED)
2981                                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2982                         else
2983                                 writel(np->irqmask, base + NvRegIrqMask);
2984                         spin_unlock(&np->lock);
2985                 }
2986 #else
2987                 if (nv_rx_process_optimized(dev, dev->weight)) {
2988                         if (unlikely(nv_alloc_rx_optimized(dev))) {
2989                                 spin_lock(&np->lock);
2990                                 if (!np->in_shutdown)
2991                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2992                                 spin_unlock(&np->lock);
2993                         }
2994                 }
2995 #endif
2996                 if (unlikely(events & NVREG_IRQ_LINK)) {
2997                         spin_lock(&np->lock);
2998                         nv_link_irq(dev);
2999                         spin_unlock(&np->lock);
3000                 }
3001                 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3002                         spin_lock(&np->lock);
3003                         nv_linkchange(dev);
3004                         spin_unlock(&np->lock);
3005                         np->link_timeout = jiffies + LINK_TIMEOUT;
3006                 }
3007                 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3008                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3009                                                 dev->name, events);
3010                 }
3011                 if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
3012                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3013                                                 dev->name, events);
3014                 }
3015                 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
3016                         spin_lock(&np->lock);
3017                         /* disable interrupts on the nic */
3018                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3019                                 writel(0, base + NvRegIrqMask);
3020                         else
3021                                 writel(np->irqmask, base + NvRegIrqMask);
3022                         pci_push(base);
3023
3024                         if (!np->in_shutdown) {
3025                                 np->nic_poll_irq = np->irqmask;
3026                                 np->recover_error = 1;
3027                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3028                         }
3029                         spin_unlock(&np->lock);
3030                         break;
3031                 }
3032
3033                 if (unlikely(i > max_interrupt_work)) {
3034                         spin_lock(&np->lock);
3035                         /* disable interrupts on the nic */
3036                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3037                                 writel(0, base + NvRegIrqMask);
3038                         else
3039                                 writel(np->irqmask, base + NvRegIrqMask);
3040                         pci_push(base);
3041
3042                         if (!np->in_shutdown) {
3043                                 np->nic_poll_irq = np->irqmask;
3044                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3045                         }
3046                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
3047                         spin_unlock(&np->lock);
3048                         break;
3049                 }
3050
3051         }
3052         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name);
3053
3054         return IRQ_RETVAL(i);
3055 }
3056
3057 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3058 {
3059         struct net_device *dev = (struct net_device *) data;
3060         struct fe_priv *np = netdev_priv(dev);
3061         u8 __iomem *base = get_hwbase(dev);
3062         u32 events;
3063         int i;
3064         unsigned long flags;
3065
3066         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
3067
3068         for (i=0; ; i++) {
3069                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3070                 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
3071                 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
3072                 if (!(events & np->irqmask))
3073                         break;
3074
3075                 spin_lock_irqsave(&np->lock, flags);
3076                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3077                 spin_unlock_irqrestore(&np->lock, flags);
3078
3079                 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3080                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3081                                                 dev->name, events);
3082                 }
3083                 if (unlikely(i > max_interrupt_work)) {
3084                         spin_lock_irqsave(&np->lock, flags);
3085                         /* disable interrupts on the nic */
3086                         writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3087                         pci_push(base);
3088
3089                         if (!np->in_shutdown) {
3090                                 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3091                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3092                         }
3093                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
3094                         spin_unlock_irqrestore(&np->lock, flags);
3095                         break;
3096                 }
3097
3098         }
3099         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
3100
3101         return IRQ_RETVAL(i);
3102 }
3103
3104 #ifdef CONFIG_FORCEDETH_NAPI
3105 static int nv_napi_poll(struct net_device *dev, int *budget)
3106 {
3107         int pkts, limit = min(*budget, dev->quota);
3108         struct fe_priv *np = netdev_priv(dev);
3109         u8 __iomem *base = get_hwbase(dev);
3110         unsigned long flags;
3111         int retcode;
3112
3113         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3114                 pkts = nv_rx_process(dev, limit);
3115                 retcode = nv_alloc_rx(dev);
3116         } else {
3117                 pkts = nv_rx_process_optimized(dev, limit);
3118                 retcode = nv_alloc_rx_optimized(dev);
3119         }
3120
3121         if (retcode) {
3122                 spin_lock_irqsave(&np->lock, flags);
3123                 if (!np->in_shutdown)
3124                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3125                 spin_unlock_irqrestore(&np->lock, flags);
3126         }
3127
3128         if (pkts < limit) {
3129                 /* all done, no more packets present */
3130                 netif_rx_complete(dev);
3131
3132                 /* re-enable receive interrupts */
3133                 spin_lock_irqsave(&np->lock, flags);
3134
3135                 np->irqmask |= NVREG_IRQ_RX_ALL;
3136                 if (np->msi_flags & NV_MSI_X_ENABLED)
3137                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3138                 else
3139                         writel(np->irqmask, base + NvRegIrqMask);
3140
3141                 spin_unlock_irqrestore(&np->lock, flags);
3142                 return 0;
3143         } else {
3144                 /* used up our quantum, so reschedule */
3145                 dev->quota -= pkts;
3146                 *budget -= pkts;
3147                 return 1;
3148         }
3149 }
3150 #endif
3151
3152 #ifdef CONFIG_FORCEDETH_NAPI
3153 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3154 {
3155         struct net_device *dev = (struct net_device *) data;
3156         u8 __iomem *base = get_hwbase(dev);
3157         u32 events;
3158
3159         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3160         writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3161
3162         if (events) {
3163                 netif_rx_schedule(dev);
3164                 /* disable receive interrupts on the nic */
3165                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3166                 pci_push(base);
3167         }
3168         return IRQ_HANDLED;
3169 }
3170 #else
3171 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3172 {
3173         struct net_device *dev = (struct net_device *) data;
3174         struct fe_priv *np = netdev_priv(dev);
3175         u8 __iomem *base = get_hwbase(dev);
3176         u32 events;
3177         int i;
3178         unsigned long flags;
3179
3180         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
3181
3182         for (i=0; ; i++) {
3183                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3184                 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3185                 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
3186                 if (!(events & np->irqmask))
3187                         break;
3188
3189                 if (nv_rx_process_optimized(dev, dev->weight)) {
3190                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3191                                 spin_lock_irqsave(&np->lock, flags);
3192                                 if (!np->in_shutdown)
3193                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3194                                 spin_unlock_irqrestore(&np->lock, flags);
3195                         }
3196                 }
3197
3198                 if (unlikely(i > max_interrupt_work)) {
3199                         spin_lock_irqsave(&np->lock, flags);
3200                         /* disable interrupts on the nic */
3201                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3202                         pci_push(base);
3203
3204                         if (!np->in_shutdown) {
3205                                 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3206                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3207                         }
3208                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
3209                         spin_unlock_irqrestore(&np->lock, flags);
3210                         break;
3211                 }
3212         }
3213         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
3214
3215         return IRQ_RETVAL(i);
3216 }
3217 #endif
3218
3219 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3220 {
3221         struct net_device *dev = (struct net_device *) data;
3222         struct fe_priv *np = netdev_priv(dev);
3223         u8 __iomem *base = get_hwbase(dev);
3224         u32 events;
3225         int i;
3226         unsigned long flags;
3227
3228         dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
3229
3230         for (i=0; ; i++) {
3231                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3232                 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
3233                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3234                 if (!(events & np->irqmask))
3235                         break;
3236
3237                 /* check tx in case we reached max loop limit in tx isr */
3238                 spin_lock_irqsave(&np->lock, flags);
3239                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3240                 spin_unlock_irqrestore(&np->lock, flags);
3241
3242                 if (events & NVREG_IRQ_LINK) {
3243                         spin_lock_irqsave(&np->lock, flags);
3244                         nv_link_irq(dev);
3245                         spin_unlock_irqrestore(&np->lock, flags);
3246                 }
3247                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3248                         spin_lock_irqsave(&np->lock, flags);
3249                         nv_linkchange(dev);
3250                         spin_unlock_irqrestore(&np->lock, flags);
3251                         np->link_timeout = jiffies + LINK_TIMEOUT;
3252                 }
3253                 if (events & NVREG_IRQ_RECOVER_ERROR) {
3254                         spin_lock_irq(&np->lock);
3255                         /* disable interrupts on the nic */
3256                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3257                         pci_push(base);
3258
3259                         if (!np->in_shutdown) {
3260                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3261                                 np->recover_error = 1;
3262                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3263                         }
3264                         spin_unlock_irq(&np->lock);
3265                         break;
3266                 }
3267                 if (events & (NVREG_IRQ_UNKNOWN)) {
3268                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3269                                                 dev->name, events);
3270                 }
3271                 if (unlikely(i > max_interrupt_work)) {
3272                         spin_lock_irqsave(&np->lock, flags);
3273                         /* disable interrupts on the nic */
3274                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3275                         pci_push(base);
3276
3277                         if (!np->in_shutdown) {
3278                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3279                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3280                         }
3281                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
3282                         spin_unlock_irqrestore(&np->lock, flags);
3283                         break;
3284                 }
3285
3286         }
3287         dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
3288
3289         return IRQ_RETVAL(i);
3290 }
3291
3292 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3293 {
3294         struct net_device *dev = (struct net_device *) data;
3295         struct fe_priv *np = netdev_priv(dev);
3296         u8 __iomem *base = get_hwbase(dev);
3297         u32 events;
3298
3299         dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
3300
3301         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3302                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3303                 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3304         } else {
3305                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3306                 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3307         }
3308         pci_push(base);
3309         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3310         if (!(events & NVREG_IRQ_TIMER))
3311                 return IRQ_RETVAL(0);
3312
3313         spin_lock(&np->lock);
3314         np->intr_test = 1;
3315         spin_unlock(&np->lock);
3316
3317         dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
3318
3319         return IRQ_RETVAL(1);
3320 }
3321
3322 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3323 {
3324         u8 __iomem *base = get_hwbase(dev);
3325         int i;
3326         u32 msixmap = 0;
3327
3328         /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3329          * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3330          * the remaining 8 interrupts.
3331          */
3332         for (i = 0; i < 8; i++) {
3333                 if ((irqmask >> i) & 0x1) {
3334                         msixmap |= vector << (i << 2);
3335                 }
3336         }
3337         writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3338
3339         msixmap = 0;
3340         for (i = 0; i < 8; i++) {
3341                 if ((irqmask >> (i + 8)) & 0x1) {
3342                         msixmap |= vector << (i << 2);
3343                 }
3344         }
3345         writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3346 }
3347
3348 static int nv_request_irq(struct net_device *dev, int intr_test)
3349 {
3350         struct fe_priv *np = get_nvpriv(dev);
3351         u8 __iomem *base = get_hwbase(dev);
3352         int ret = 1;
3353         int i;
3354         irqreturn_t (*handler)(int foo, void *data);
3355
3356         if (intr_test) {
3357                 handler = nv_nic_irq_test;
3358         } else {
3359                 if (np->desc_ver == DESC_VER_3)
3360                         handler = nv_nic_irq_optimized;
3361                 else
3362                         handler = nv_nic_irq;
3363         }
3364
3365         if (np->msi_flags & NV_MSI_X_CAPABLE) {
3366                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3367                         np->msi_x_entry[i].entry = i;
3368                 }
3369                 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
3370                         np->msi_flags |= NV_MSI_X_ENABLED;
3371                         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3372                                 /* Request irq for rx handling */
3373                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, IRQF_SHARED, dev->name, dev) != 0) {
3374                                         printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
3375                                         pci_disable_msix(np->pci_dev);
3376                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3377                                         goto out_err;
3378                                 }
3379                                 /* Request irq for tx handling */
3380                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, IRQF_SHARED, dev->name, dev) != 0) {
3381                                         printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
3382                                         pci_disable_msix(np->pci_dev);
3383                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3384                                         goto out_free_rx;
3385                                 }
3386                                 /* Request irq for link and timer handling */
3387                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, IRQF_SHARED, dev->name, dev) != 0) {
3388                                         printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
3389                                         pci_disable_msix(np->pci_dev);
3390                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3391                                         goto out_free_tx;
3392                                 }
3393                                 /* map interrupts to their respective vector */
3394                                 writel(0, base + NvRegMSIXMap0);
3395                                 writel(0, base + NvRegMSIXMap1);
3396                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3397                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3398                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3399                         } else {
3400                                 /* Request irq for all interrupts */
3401                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
3402                                         printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3403                                         pci_disable_msix(np->pci_dev);
3404                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3405                                         goto out_err;
3406                                 }
3407
3408                                 /* map interrupts to vector 0 */
3409                                 writel(0, base + NvRegMSIXMap0);
3410                                 writel(0, base + NvRegMSIXMap1);
3411                         }
3412                 }
3413         }
3414         if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
3415                 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
3416                         np->msi_flags |= NV_MSI_ENABLED;
3417                         if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
3418                                 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3419                                 pci_disable_msi(np->pci_dev);
3420                                 np->msi_flags &= ~NV_MSI_ENABLED;
3421                                 goto out_err;
3422                         }
3423
3424                         /* map interrupts to vector 0 */
3425                         writel(0, base + NvRegMSIMap0);
3426                         writel(0, base + NvRegMSIMap1);
3427                         /* enable msi vector 0 */
3428                         writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3429                 }
3430         }
3431         if (ret != 0) {
3432                 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
3433                         goto out_err;
3434
3435         }
3436
3437         return 0;
3438 out_free_tx:
3439         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3440 out_free_rx:
3441         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3442 out_err:
3443         return 1;
3444 }
3445
3446 static void nv_free_irq(struct net_device *dev)
3447 {
3448         struct fe_priv *np = get_nvpriv(dev);
3449         int i;
3450
3451         if (np->msi_flags & NV_MSI_X_ENABLED) {
3452                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3453                         free_irq(np->msi_x_entry[i].vector, dev);
3454                 }
3455                 pci_disable_msix(np->pci_dev);
3456                 np->msi_flags &= ~NV_MSI_X_ENABLED;
3457         } else {
3458                 free_irq(np->pci_dev->irq, dev);
3459                 if (np->msi_flags & NV_MSI_ENABLED) {
3460                         pci_disable_msi(np->pci_dev);
3461                         np->msi_flags &= ~NV_MSI_ENABLED;
3462                 }
3463         }
3464 }
3465
3466 static void nv_do_nic_poll(unsigned long data)
3467 {
3468         struct net_device *dev = (struct net_device *) data;
3469         struct fe_priv *np = netdev_priv(dev);
3470         u8 __iomem *base = get_hwbase(dev);
3471         u32 mask = 0;
3472
3473         /*
3474          * First disable irq(s) and then
3475          * reenable interrupts on the nic, we have to do this before calling
3476          * nv_nic_irq because that may decide to do otherwise
3477          */
3478
3479         if (!using_multi_irqs(dev)) {
3480                 if (np->msi_flags & NV_MSI_X_ENABLED)
3481                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3482                 else
3483                         disable_irq_lockdep(dev->irq);
3484                 mask = np->irqmask;
3485         } else {
3486                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3487                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3488                         mask |= NVREG_IRQ_RX_ALL;
3489                 }
3490                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3491                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3492                         mask |= NVREG_IRQ_TX_ALL;
3493                 }
3494                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3495                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3496                         mask |= NVREG_IRQ_OTHER;
3497                 }
3498         }
3499         np->nic_poll_irq = 0;
3500
3501         if (np->recover_error) {
3502                 np->recover_error = 0;
3503                 printk(KERN_INFO "forcedeth: MAC in recoverable error state\n");
3504                 if (netif_running(dev)) {
3505                         netif_tx_lock_bh(dev);
3506                         spin_lock(&np->lock);
3507                         /* stop engines */
3508                         nv_stop_rx(dev);
3509                         nv_stop_tx(dev);
3510                         nv_txrx_reset(dev);
3511                         /* drain rx queue */
3512                         nv_drain_rx(dev);
3513                         nv_drain_tx(dev);
3514                         /* reinit driver view of the rx queue */
3515                         set_bufsize(dev);
3516                         if (nv_init_ring(dev)) {
3517                                 if (!np->in_shutdown)
3518                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3519                         }
3520                         /* reinit nic view of the rx queue */
3521                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3522                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3523                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3524                                 base + NvRegRingSizes);
3525                         pci_push(base);
3526                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3527                         pci_push(base);
3528
3529                         /* restart rx engine */
3530                         nv_start_rx(dev);
3531                         nv_start_tx(dev);
3532                         spin_unlock(&np->lock);
3533                         netif_tx_unlock_bh(dev);
3534                 }
3535         }
3536
3537         /* FIXME: Do we need synchronize_irq(dev->irq) here? */
3538
3539         writel(mask, base + NvRegIrqMask);
3540         pci_push(base);
3541
3542         if (!using_multi_irqs(dev)) {
3543                 if (np->desc_ver == DESC_VER_3)
3544                         nv_nic_irq_optimized(0, dev);
3545                 else
3546                         nv_nic_irq(0, dev);
3547                 if (np->msi_flags & NV_MSI_X_ENABLED)
3548                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3549                 else
3550                         enable_irq_lockdep(dev->irq);
3551         } else {
3552                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3553                         nv_nic_irq_rx(0, dev);
3554                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3555                 }
3556                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3557                         nv_nic_irq_tx(0, dev);
3558                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3559                 }
3560                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3561                         nv_nic_irq_other(0, dev);
3562                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3563                 }
3564         }
3565 }
3566
3567 #ifdef CONFIG_NET_POLL_CONTROLLER
3568 static void nv_poll_controller(struct net_device *dev)
3569 {
3570         nv_do_nic_poll((unsigned long) dev);
3571 }
3572 #endif
3573
3574 static void nv_do_stats_poll(unsigned long data)
3575 {
3576         struct net_device *dev = (struct net_device *) data;
3577         struct fe_priv *np = netdev_priv(dev);
3578
3579         nv_get_hw_stats(dev);
3580
3581         if (!np->in_shutdown)
3582                 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
3583 }
3584
3585 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
3586 {
3587         struct fe_priv *np = netdev_priv(dev);
3588         strcpy(info->driver, "forcedeth");
3589         strcpy(info->version, FORCEDETH_VERSION);
3590         strcpy(info->bus_info, pci_name(np->pci_dev));
3591 }
3592
3593 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3594 {
3595         struct fe_priv *np = netdev_priv(dev);
3596         wolinfo->supported = WAKE_MAGIC;
3597
3598         spin_lock_irq(&np->lock);
3599         if (np->wolenabled)
3600                 wolinfo->wolopts = WAKE_MAGIC;
3601         spin_unlock_irq(&np->lock);
3602 }
3603
3604 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3605 {
3606         struct fe_priv *np = netdev_priv(dev);
3607         u8 __iomem *base = get_hwbase(dev);
3608         u32 flags = 0;
3609
3610         if (wolinfo->wolopts == 0) {
3611                 np->wolenabled = 0;
3612         } else if (wolinfo->wolopts & WAKE_MAGIC) {
3613                 np->wolenabled = 1;
3614                 flags = NVREG_WAKEUPFLAGS_ENABLE;
3615         }
3616         if (netif_running(dev)) {
3617                 spin_lock_irq(&np->lock);
3618                 writel(flags, base + NvRegWakeUpFlags);
3619                 spin_unlock_irq(&np->lock);
3620         }
3621         return 0;
3622 }
3623
3624 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3625 {
3626         struct fe_priv *np = netdev_priv(dev);
3627         int adv;
3628
3629         spin_lock_irq(&np->lock);
3630         ecmd->port = PORT_MII;
3631         if (!netif_running(dev)) {
3632                 /* We do not track link speed / duplex setting if the
3633                  * interface is disabled. Force a link check */
3634                 if (nv_update_linkspeed(dev)) {
3635                         if (!netif_carrier_ok(dev))
3636                                 netif_carrier_on(dev);
3637                 } else {
3638                         if (netif_carrier_ok(dev))
3639                                 netif_carrier_off(dev);
3640                 }
3641         }
3642
3643         if (netif_carrier_ok(dev)) {
3644                 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
3645                 case NVREG_LINKSPEED_10:
3646                         ecmd->speed = SPEED_10;
3647                         break;
3648                 case NVREG_LINKSPEED_100:
3649                         ecmd->speed = SPEED_100;
3650                         break;
3651                 case NVREG_LINKSPEED_1000:
3652                         ecmd->speed = SPEED_1000;
3653                         break;
3654                 }
3655                 ecmd->duplex = DUPLEX_HALF;
3656                 if (np->duplex)
3657                         ecmd->duplex = DUPLEX_FULL;
3658         } else {
3659                 ecmd->speed = -1;
3660                 ecmd->duplex = -1;
3661         }
3662
3663         ecmd->autoneg = np->autoneg;
3664
3665         ecmd->advertising = ADVERTISED_MII;
3666         if (np->autoneg) {
3667                 ecmd->advertising |= ADVERTISED_Autoneg;
3668                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3669                 if (adv & ADVERTISE_10HALF)
3670                         ecmd->advertising |= ADVERTISED_10baseT_Half;
3671                 if (adv & ADVERTISE_10FULL)
3672                         ecmd->advertising |= ADVERTISED_10baseT_Full;
3673                 if (adv & ADVERTISE_100HALF)
3674                         ecmd->advertising |= ADVERTISED_100baseT_Half;
3675                 if (adv & ADVERTISE_100FULL)
3676                         ecmd->advertising |= ADVERTISED_100baseT_Full;
3677                 if (np->gigabit == PHY_GIGABIT) {
3678                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3679                         if (adv & ADVERTISE_1000FULL)
3680                                 ecmd->advertising |= ADVERTISED_1000baseT_Full;
3681                 }
3682         }
3683         ecmd->supported = (SUPPORTED_Autoneg |
3684                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
3685                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
3686                 SUPPORTED_MII);
3687         if (np->gigabit == PHY_GIGABIT)
3688                 ecmd->supported |= SUPPORTED_1000baseT_Full;
3689
3690         ecmd->phy_address = np->phyaddr;
3691         ecmd->transceiver = XCVR_EXTERNAL;
3692
3693         /* ignore maxtxpkt, maxrxpkt for now */
3694         spin_unlock_irq(&np->lock);
3695         return 0;
3696 }
3697
3698 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3699 {
3700         struct fe_priv *np = netdev_priv(dev);
3701
3702         if (ecmd->port != PORT_MII)
3703                 return -EINVAL;
3704         if (ecmd->transceiver != XCVR_EXTERNAL)
3705                 return -EINVAL;
3706         if (ecmd->phy_address != np->phyaddr) {
3707                 /* TODO: support switching between multiple phys. Should be
3708                  * trivial, but not enabled due to lack of test hardware. */
3709                 return -EINVAL;
3710         }
3711         if (ecmd->autoneg == AUTONEG_ENABLE) {
3712                 u32 mask;
3713
3714                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3715                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
3716                 if (np->gigabit == PHY_GIGABIT)
3717                         mask |= ADVERTISED_1000baseT_Full;
3718
3719                 if ((ecmd->advertising & mask) == 0)
3720                         return -EINVAL;
3721
3722         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
3723                 /* Note: autonegotiation disable, speed 1000 intentionally
3724                  * forbidden - noone should need that. */
3725
3726                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
3727                         return -EINVAL;
3728                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
3729                         return -EINVAL;
3730         } else {
3731                 return -EINVAL;
3732         }
3733
3734         netif_carrier_off(dev);
3735         if (netif_running(dev)) {
3736                 nv_disable_irq(dev);
3737                 netif_tx_lock_bh(dev);
3738                 spin_lock(&np->lock);
3739                 /* stop engines */
3740                 nv_stop_rx(dev);
3741                 nv_stop_tx(dev);
3742                 spin_unlock(&np->lock);
3743                 netif_tx_unlock_bh(dev);
3744         }
3745
3746         if (ecmd->autoneg == AUTONEG_ENABLE) {
3747                 int adv, bmcr;
3748
3749                 np->autoneg = 1;
3750
3751                 /* advertise only what has been requested */
3752                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3753                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3754                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
3755                         adv |= ADVERTISE_10HALF;
3756                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
3757                         adv |= ADVERTISE_10FULL;
3758                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
3759                         adv |= ADVERTISE_100HALF;
3760                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
3761                         adv |= ADVERTISE_100FULL;
3762                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)  /* for rx we set both advertisments but disable tx pause */
3763                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3764                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3765                         adv |=  ADVERTISE_PAUSE_ASYM;
3766                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3767
3768                 if (np->gigabit == PHY_GIGABIT) {
3769                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3770                         adv &= ~ADVERTISE_1000FULL;
3771                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
3772                                 adv |= ADVERTISE_1000FULL;
3773                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3774                 }
3775
3776                 if (netif_running(dev))
3777                         printk(KERN_INFO "%s: link down.\n", dev->name);
3778                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3779                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
3780                         bmcr |= BMCR_ANENABLE;
3781                         /* reset the phy in order for settings to stick,
3782                          * and cause autoneg to start */
3783                         if (phy_reset(dev, bmcr)) {
3784                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3785                                 return -EINVAL;
3786                         }
3787                 } else {
3788                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3789                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3790                 }
3791         } else {
3792                 int adv, bmcr;
3793
3794                 np->autoneg = 0;
3795
3796                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3797                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3798                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
3799                         adv |= ADVERTISE_10HALF;
3800                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
3801                         adv |= ADVERTISE_10FULL;
3802                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
3803                         adv |= ADVERTISE_100HALF;
3804                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
3805                         adv |= ADVERTISE_100FULL;
3806                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
3807                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
3808                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3809                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3810                 }
3811                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
3812                         adv |=  ADVERTISE_PAUSE_ASYM;
3813                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3814                 }
3815                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3816                 np->fixed_mode = adv;
3817
3818                 if (np->gigabit == PHY_GIGABIT) {
3819                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3820                         adv &= ~ADVERTISE_1000FULL;
3821                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3822                 }
3823
3824                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3825                 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
3826                 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
3827                         bmcr |= BMCR_FULLDPLX;
3828                 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
3829                         bmcr |= BMCR_SPEED100;
3830                 if (np->phy_oui == PHY_OUI_MARVELL) {
3831                         /* reset the phy in order for forced mode settings to stick */
3832                         if (phy_reset(dev, bmcr)) {
3833                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3834                                 return -EINVAL;
3835                         }
3836                 } else {
3837                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3838                         if (netif_running(dev)) {
3839                                 /* Wait a bit and then reconfigure the nic. */
3840                                 udelay(10);
3841                                 nv_linkchange(dev);
3842                         }
3843                 }
3844         }
3845
3846         if (netif_running(dev)) {
3847                 nv_start_rx(dev);
3848                 nv_start_tx(dev);
3849                 nv_enable_irq(dev);
3850         }
3851
3852         return 0;
3853 }
3854
3855 #define FORCEDETH_REGS_VER      1
3856
3857 static int nv_get_regs_len(struct net_device *dev)
3858 {
3859         struct fe_priv *np = netdev_priv(dev);
3860         return np->register_size;
3861 }
3862
3863 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
3864 {
3865         struct fe_priv *np = netdev_priv(dev);
3866         u8 __iomem *base = get_hwbase(dev);
3867         u32 *rbuf = buf;
3868         int i;
3869
3870         regs->version = FORCEDETH_REGS_VER;
3871         spin_lock_irq(&np->lock);
3872         for (i = 0;i <= np->register_size/sizeof(u32); i++)
3873                 rbuf[i] = readl(base + i*sizeof(u32));
3874         spin_unlock_irq(&np->lock);
3875 }
3876
3877 static int nv_nway_reset(struct net_device *dev)
3878 {
3879         struct fe_priv *np = netdev_priv(dev);
3880         int ret;
3881
3882         if (np->autoneg) {
3883                 int bmcr;
3884
3885                 netif_carrier_off(dev);
3886                 if (netif_running(dev)) {
3887                         nv_disable_irq(dev);
3888                         netif_tx_lock_bh(dev);
3889                         spin_lock(&np->lock);
3890                         /* stop engines */
3891                         nv_stop_rx(dev);
3892                         nv_stop_tx(dev);
3893                         spin_unlock(&np->lock);
3894                         netif_tx_unlock_bh(dev);
3895                         printk(KERN_INFO "%s: link down.\n", dev->name);
3896                 }
3897
3898                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3899                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
3900                         bmcr |= BMCR_ANENABLE;
3901                         /* reset the phy in order for settings to stick*/
3902                         if (phy_reset(dev, bmcr)) {
3903                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3904                                 return -EINVAL;
3905                         }
3906                 } else {
3907                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3908                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3909                 }
3910
3911                 if (netif_running(dev)) {
3912                         nv_start_rx(dev);
3913                         nv_start_tx(dev);
3914                         nv_enable_irq(dev);
3915                 }
3916                 ret = 0;
3917         } else {
3918                 ret = -EINVAL;
3919         }
3920
3921         return ret;
3922 }
3923
3924 static int nv_set_tso(struct net_device *dev, u32 value)
3925 {
3926         struct fe_priv *np = netdev_priv(dev);
3927
3928         if ((np->driver_data & DEV_HAS_CHECKSUM))
3929                 return ethtool_op_set_tso(dev, value);
3930         else
3931                 return -EOPNOTSUPP;
3932 }
3933
3934 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
3935 {
3936         struct fe_priv *np = netdev_priv(dev);
3937
3938         ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3939         ring->rx_mini_max_pending = 0;
3940         ring->rx_jumbo_max_pending = 0;
3941         ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3942
3943         ring->rx_pending = np->rx_ring_size;
3944         ring->rx_mini_pending = 0;
3945         ring->rx_jumbo_pending = 0;
3946         ring->tx_pending = np->tx_ring_size;
3947 }
3948
3949 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
3950 {
3951         struct fe_priv *np = netdev_priv(dev);
3952         u8 __iomem *base = get_hwbase(dev);
3953         u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
3954         dma_addr_t ring_addr;
3955
3956         if (ring->rx_pending < RX_RING_MIN ||
3957             ring->tx_pending < TX_RING_MIN ||
3958             ring->rx_mini_pending != 0 ||
3959             ring->rx_jumbo_pending != 0 ||
3960             (np->desc_ver == DESC_VER_1 &&
3961              (ring->rx_pending > RING_MAX_DESC_VER_1 ||
3962               ring->tx_pending > RING_MAX_DESC_VER_1)) ||
3963             (np->desc_ver != DESC_VER_1 &&
3964              (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
3965               ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
3966                 return -EINVAL;
3967         }
3968
3969         /* allocate new rings */
3970         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3971                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
3972                                             sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3973                                             &ring_addr);
3974         } else {
3975                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
3976                                             sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3977                                             &ring_addr);
3978         }
3979         rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
3980         tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
3981         if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
3982                 /* fall back to old rings */
3983                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3984                         if (rxtx_ring)
3985                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3986                                                     rxtx_ring, ring_addr);
3987                 } else {
3988                         if (rxtx_ring)
3989                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3990                                                     rxtx_ring, ring_addr);
3991                 }
3992                 if (rx_skbuff)
3993                         kfree(rx_skbuff);
3994                 if (tx_skbuff)
3995                         kfree(tx_skbuff);
3996                 goto exit;
3997         }
3998
3999         if (netif_running(dev)) {
4000                 nv_disable_irq(dev);
4001                 netif_tx_lock_bh(dev);
4002                 spin_lock(&np->lock);
4003                 /* stop engines */
4004                 nv_stop_rx(dev);
4005                 nv_stop_tx(dev);
4006                 nv_txrx_reset(dev);
4007                 /* drain queues */
4008                 nv_drain_rx(dev);
4009                 nv_drain_tx(dev);
4010                 /* delete queues */
4011                 free_rings(dev);
4012         }
4013
4014         /* set new values */
4015         np->rx_ring_size = ring->rx_pending;
4016         np->tx_ring_size = ring->tx_pending;
4017         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4018                 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
4019                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4020         } else {
4021                 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
4022                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4023         }
4024         np->rx_skb = (struct nv_skb_map*)rx_skbuff;
4025         np->tx_skb = (struct nv_skb_map*)tx_skbuff;
4026         np->ring_addr = ring_addr;
4027
4028         memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4029         memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4030
4031         if (netif_running(dev)) {
4032                 /* reinit driver view of the queues */
4033                 set_bufsize(dev);
4034                 if (nv_init_ring(dev)) {
4035                         if (!np->in_shutdown)
4036                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4037                 }
4038
4039                 /* reinit nic view of the queues */
4040                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4041                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4042                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4043                         base + NvRegRingSizes);
4044                 pci_push(base);
4045                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4046                 pci_push(base);
4047
4048                 /* restart engines */
4049                 nv_start_rx(dev);
4050                 nv_start_tx(dev);
4051                 spin_unlock(&np->lock);
4052                 netif_tx_unlock_bh(dev);
4053                 nv_enable_irq(dev);
4054         }
4055         return 0;
4056 exit:
4057         return -ENOMEM;
4058 }
4059
4060 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4061 {
4062         struct fe_priv *np = netdev_priv(dev);
4063
4064         pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4065         pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4066         pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4067 }
4068
4069 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4070 {
4071         struct fe_priv *np = netdev_priv(dev);
4072         int adv, bmcr;
4073
4074         if ((!np->autoneg && np->duplex == 0) ||
4075             (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4076                 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
4077                        dev->name);
4078                 return -EINVAL;
4079         }
4080         if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4081                 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
4082                 return -EINVAL;
4083         }
4084
4085         netif_carrier_off(dev);
4086         if (netif_running(dev)) {
4087                 nv_disable_irq(dev);
4088                 netif_tx_lock_bh(dev);
4089                 spin_lock(&np->lock);
4090                 /* stop engines */
4091                 nv_stop_rx(dev);
4092                 nv_stop_tx(dev);
4093                 spin_unlock(&np->lock);
4094                 netif_tx_unlock_bh(dev);
4095         }
4096
4097         np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4098         if (pause->rx_pause)
4099                 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4100         if (pause->tx_pause)
4101                 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4102
4103         if (np->autoneg && pause->autoneg) {
4104                 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4105
4106                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4107                 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4108                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4109                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4110                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4111                         adv |=  ADVERTISE_PAUSE_ASYM;
4112                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4113
4114                 if (netif_running(dev))
4115                         printk(KERN_INFO "%s: link down.\n", dev->name);
4116                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4117                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4118                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4119         } else {
4120                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4121                 if (pause->rx_pause)
4122                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4123                 if (pause->tx_pause)
4124                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4125
4126                 if (!netif_running(dev))
4127                         nv_update_linkspeed(dev);
4128                 else
4129                         nv_update_pause(dev, np->pause_flags);
4130         }
4131
4132         if (netif_running(dev)) {
4133                 nv_start_rx(dev);
4134                 nv_start_tx(dev);
4135                 nv_enable_irq(dev);
4136         }
4137         return 0;
4138 }
4139
4140 static u32 nv_get_rx_csum(struct net_device *dev)
4141 {
4142         struct fe_priv *np = netdev_priv(dev);
4143         return (np->rx_csum) != 0;
4144 }
4145
4146 static int nv_set_rx_csum(struct net_device *dev, u32 data)
4147 {
4148         struct fe_priv *np = netdev_priv(dev);
4149         u8 __iomem *base = get_hwbase(dev);
4150         int retcode = 0;
4151
4152         if (np->driver_data & DEV_HAS_CHECKSUM) {
4153                 if (data) {
4154                         np->rx_csum = 1;
4155                         np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4156                 } else {
4157                         np->rx_csum = 0;
4158                         /* vlan is dependent on rx checksum offload */
4159                         if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
4160                                 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4161                 }
4162                 if (netif_running(dev)) {
4163                         spin_lock_irq(&np->lock);
4164                         writel(np->txrxctl_bits, base + NvRegTxRxControl);
4165                         spin_unlock_irq(&np->lock);
4166                 }
4167         } else {
4168                 return -EINVAL;
4169         }
4170
4171         return retcode;
4172 }
4173
4174 static int nv_set_tx_csum(struct net_device *dev, u32 data)
4175 {
4176         struct fe_priv *np = netdev_priv(dev);
4177
4178         if (np->driver_data & DEV_HAS_CHECKSUM)
4179                 return ethtool_op_set_tx_hw_csum(dev, data);
4180         else
4181                 return -EOPNOTSUPP;
4182 }
4183
4184 static int nv_set_sg(struct net_device *dev, u32 data)
4185 {
4186         struct fe_priv *np = netdev_priv(dev);
4187
4188         if (np->driver_data & DEV_HAS_CHECKSUM)
4189                 return ethtool_op_set_sg(dev, data);
4190         else
4191                 return -EOPNOTSUPP;
4192 }
4193
4194 static int nv_get_stats_count(struct net_device *dev)
4195 {
4196         struct fe_priv *np = netdev_priv(dev);
4197
4198         if (np->driver_data & DEV_HAS_STATISTICS_V1)
4199                 return NV_DEV_STATISTICS_V1_COUNT;
4200         else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4201                 return NV_DEV_STATISTICS_V2_COUNT;
4202         else
4203                 return 0;
4204 }
4205
4206 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4207 {
4208         struct fe_priv *np = netdev_priv(dev);
4209
4210         /* update stats */
4211         nv_do_stats_poll((unsigned long)dev);
4212
4213         memcpy(buffer, &np->estats, nv_get_stats_count(dev)*sizeof(u64));
4214 }
4215
4216 static int nv_self_test_count(struct net_device *dev)
4217 {
4218         struct fe_priv *np = netdev_priv(dev);
4219
4220         if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4221                 return NV_TEST_COUNT_EXTENDED;
4222         else
4223                 return NV_TEST_COUNT_BASE;
4224 }
4225
4226 static int nv_link_test(struct net_device *dev)
4227 {
4228         struct fe_priv *np = netdev_priv(dev);
4229         int mii_status;
4230
4231         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4232         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4233
4234         /* check phy link status */
4235         if (!(mii_status & BMSR_LSTATUS))
4236                 return 0;
4237         else
4238                 return 1;
4239 }
4240
4241 static int nv_register_test(struct net_device *dev)
4242 {
4243         u8 __iomem *base = get_hwbase(dev);
4244         int i = 0;
4245         u32 orig_read, new_read;
4246
4247         do {
4248                 orig_read = readl(base + nv_registers_test[i].reg);
4249
4250                 /* xor with mask to toggle bits */
4251                 orig_read ^= nv_registers_test[i].mask;
4252
4253                 writel(orig_read, base + nv_registers_test[i].reg);
4254
4255                 new_read = readl(base + nv_registers_test[i].reg);
4256
4257                 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4258                         return 0;
4259
4260                 /* restore original value */
4261                 orig_read ^= nv_registers_test[i].mask;
4262                 writel(orig_read, base + nv_registers_test[i].reg);
4263
4264         } while (nv_registers_test[++i].reg != 0);
4265
4266         return 1;
4267 }
4268
4269 static int nv_interrupt_test(struct net_device *dev)
4270 {
4271         struct fe_priv *np = netdev_priv(dev);
4272         u8 __iomem *base = get_hwbase(dev);
4273         int ret = 1;
4274         int testcnt;
4275         u32 save_msi_flags, save_poll_interval = 0;
4276
4277         if (netif_running(dev)) {
4278                 /* free current irq */
4279                 nv_free_irq(dev);
4280                 save_poll_interval = readl(base+NvRegPollingInterval);
4281         }
4282
4283         /* flag to test interrupt handler */
4284         np->intr_test = 0;
4285
4286         /* setup test irq */
4287         save_msi_flags = np->msi_flags;
4288         np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4289         np->msi_flags |= 0x001; /* setup 1 vector */
4290         if (nv_request_irq(dev, 1))
4291                 return 0;
4292
4293         /* setup timer interrupt */
4294         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4295         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4296
4297         nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4298
4299         /* wait for at least one interrupt */
4300         msleep(100);
4301
4302         spin_lock_irq(&np->lock);
4303
4304         /* flag should be set within ISR */
4305         testcnt = np->intr_test;
4306         if (!testcnt)
4307                 ret = 2;
4308
4309         nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4310         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4311                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4312         else
4313                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4314
4315         spin_unlock_irq(&np->lock);
4316
4317         nv_free_irq(dev);
4318
4319         np->msi_flags = save_msi_flags;
4320
4321         if (netif_running(dev)) {
4322                 writel(save_poll_interval, base + NvRegPollingInterval);
4323                 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4324                 /* restore original irq */
4325                 if (nv_request_irq(dev, 0))
4326                         return 0;
4327         }
4328
4329         return ret;
4330 }
4331
4332 static int nv_loopback_test(struct net_device *dev)
4333 {
4334         struct fe_priv *np = netdev_priv(dev);
4335         u8 __iomem *base = get_hwbase(dev);
4336         struct sk_buff *tx_skb, *rx_skb;
4337         dma_addr_t test_dma_addr;
4338         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
4339         u32 flags;
4340         int len, i, pkt_len;
4341         u8 *pkt_data;
4342         u32 filter_flags = 0;
4343         u32 misc1_flags = 0;
4344         int ret = 1;
4345
4346         if (netif_running(dev)) {
4347                 nv_disable_irq(dev);
4348                 filter_flags = readl(base + NvRegPacketFilterFlags);
4349                 misc1_flags = readl(base + NvRegMisc1);
4350         } else {
4351                 nv_txrx_reset(dev);
4352         }
4353
4354         /* reinit driver view of the rx queue */
4355         set_bufsize(dev);
4356         nv_init_ring(dev);
4357
4358         /* setup hardware for loopback */
4359         writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
4360         writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
4361
4362         /* reinit nic view of the rx queue */
4363         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4364         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4365         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4366                 base + NvRegRingSizes);
4367         pci_push(base);
4368
4369         /* restart rx engine */
4370         nv_start_rx(dev);
4371         nv_start_tx(dev);
4372
4373         /* setup packet for tx */
4374         pkt_len = ETH_DATA_LEN;
4375         tx_skb = dev_alloc_skb(pkt_len);
4376         if (!tx_skb) {
4377                 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
4378                          " of %s\n", dev->name);
4379                 ret = 0;
4380                 goto out;
4381         }
4382         test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
4383                                        skb_tailroom(tx_skb),
4384                                        PCI_DMA_FROMDEVICE);
4385         pkt_data = skb_put(tx_skb, pkt_len);
4386         for (i = 0; i < pkt_len; i++)
4387                 pkt_data[i] = (u8)(i & 0xff);
4388
4389         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4390                 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
4391                 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4392         } else {
4393                 np->tx_ring.ex[0].bufhigh = cpu_to_le64(test_dma_addr) >> 32;
4394                 np->tx_ring.ex[0].buflow = cpu_to_le64(test_dma_addr) & 0x0FFFFFFFF;
4395                 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4396         }
4397         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4398         pci_push(get_hwbase(dev));
4399
4400         msleep(500);
4401
4402         /* check for rx of the packet */
4403         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4404                 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
4405                 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
4406
4407         } else {
4408                 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
4409                 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
4410         }
4411
4412         if (flags & NV_RX_AVAIL) {
4413                 ret = 0;
4414         } else if (np->desc_ver == DESC_VER_1) {
4415                 if (flags & NV_RX_ERROR)
4416                         ret = 0;
4417         } else {
4418                 if (flags & NV_RX2_ERROR) {
4419                         ret = 0;
4420                 }
4421         }
4422
4423         if (ret) {
4424                 if (len != pkt_len) {
4425                         ret = 0;
4426                         dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
4427                                 dev->name, len, pkt_len);
4428                 } else {
4429                         rx_skb = np->rx_skb[0].skb;
4430                         for (i = 0; i < pkt_len; i++) {
4431                                 if (rx_skb->data[i] != (u8)(i & 0xff)) {
4432                                         ret = 0;
4433                                         dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
4434                                                 dev->name, i);
4435                                         break;
4436                                 }
4437                         }
4438                 }
4439         } else {
4440                 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
4441         }
4442
4443         pci_unmap_page(np->pci_dev, test_dma_addr,
4444                        (skb_end_pointer(tx_skb) - tx_skb->data),
4445                        PCI_DMA_TODEVICE);
4446         dev_kfree_skb_any(tx_skb);
4447  out:
4448         /* stop engines */
4449         nv_stop_rx(dev);
4450         nv_stop_tx(dev);
4451         nv_txrx_reset(dev);
4452         /* drain rx queue */
4453         nv_drain_rx(dev);
4454         nv_drain_tx(dev);
4455
4456         if (netif_running(dev)) {
4457                 writel(misc1_flags, base + NvRegMisc1);
4458                 writel(filter_flags, base + NvRegPacketFilterFlags);
4459                 nv_enable_irq(dev);
4460         }
4461
4462         return ret;
4463 }
4464
4465 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
4466 {
4467         struct fe_priv *np = netdev_priv(dev);
4468         u8 __iomem *base = get_hwbase(dev);
4469         int result;
4470         memset(buffer, 0, nv_self_test_count(dev)*sizeof(u64));
4471
4472         if (!nv_link_test(dev)) {
4473                 test->flags |= ETH_TEST_FL_FAILED;
4474                 buffer[0] = 1;
4475         }
4476
4477         if (test->flags & ETH_TEST_FL_OFFLINE) {
4478                 if (netif_running(dev)) {
4479                         netif_stop_queue(dev);
4480                         netif_poll_disable(dev);
4481                         netif_tx_lock_bh(dev);
4482                         spin_lock_irq(&np->lock);
4483                         nv_disable_hw_interrupts(dev, np->irqmask);
4484                         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
4485                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4486                         } else {
4487                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4488                         }
4489                         /* stop engines */
4490                         nv_stop_rx(dev);
4491                         nv_stop_tx(dev);
4492                         nv_txrx_reset(dev);
4493                         /* drain rx queue */
4494                         nv_drain_rx(dev);
4495                         nv_drain_tx(dev);
4496                         spin_unlock_irq(&np->lock);
4497                         netif_tx_unlock_bh(dev);
4498                 }
4499
4500                 if (!nv_register_test(dev)) {
4501                         test->flags |= ETH_TEST_FL_FAILED;
4502                         buffer[1] = 1;
4503                 }
4504
4505                 result = nv_interrupt_test(dev);
4506                 if (result != 1) {
4507                         test->flags |= ETH_TEST_FL_FAILED;
4508                         buffer[2] = 1;
4509                 }
4510                 if (result == 0) {
4511                         /* bail out */
4512                         return;
4513                 }
4514
4515                 if (!nv_loopback_test(dev)) {
4516                         test->flags |= ETH_TEST_FL_FAILED;
4517                         buffer[3] = 1;
4518                 }
4519
4520                 if (netif_running(dev)) {
4521                         /* reinit driver view of the rx queue */
4522                         set_bufsize(dev);
4523                         if (nv_init_ring(dev)) {
4524                                 if (!np->in_shutdown)
4525                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4526                         }
4527                         /* reinit nic view of the rx queue */
4528                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4529                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4530                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4531                                 base + NvRegRingSizes);
4532                         pci_push(base);
4533                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4534                         pci_push(base);
4535                         /* restart rx engine */
4536                         nv_start_rx(dev);
4537                         nv_start_tx(dev);
4538                         netif_start_queue(dev);
4539                         netif_poll_enable(dev);
4540                         nv_enable_hw_interrupts(dev, np->irqmask);
4541                 }
4542         }
4543 }
4544
4545 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
4546 {
4547         switch (stringset) {
4548         case ETH_SS_STATS:
4549                 memcpy(buffer, &nv_estats_str, nv_get_stats_count(dev)*sizeof(struct nv_ethtool_str));
4550                 break;
4551         case ETH_SS_TEST:
4552                 memcpy(buffer, &nv_etests_str, nv_self_test_count(dev)*sizeof(struct nv_ethtool_str));
4553                 break;
4554         }
4555 }
4556
4557 static const struct ethtool_ops ops = {
4558         .get_drvinfo = nv_get_drvinfo,
4559         .get_link = ethtool_op_get_link,
4560         .get_wol = nv_get_wol,
4561         .set_wol = nv_set_wol,
4562         .get_settings = nv_get_settings,
4563         .set_settings = nv_set_settings,
4564         .get_regs_len = nv_get_regs_len,
4565         .get_regs = nv_get_regs,
4566         .nway_reset = nv_nway_reset,
4567         .get_perm_addr = ethtool_op_get_perm_addr,
4568         .get_tso = ethtool_op_get_tso,
4569         .set_tso = nv_set_tso,
4570         .get_ringparam = nv_get_ringparam,
4571         .set_ringparam = nv_set_ringparam,
4572         .get_pauseparam = nv_get_pauseparam,
4573         .set_pauseparam = nv_set_pauseparam,
4574         .get_rx_csum = nv_get_rx_csum,
4575         .set_rx_csum = nv_set_rx_csum,
4576         .get_tx_csum = ethtool_op_get_tx_csum,
4577         .set_tx_csum = nv_set_tx_csum,
4578         .get_sg = ethtool_op_get_sg,
4579         .set_sg = nv_set_sg,
4580         .get_strings = nv_get_strings,
4581         .get_stats_count = nv_get_stats_count,
4582         .get_ethtool_stats = nv_get_ethtool_stats,
4583         .self_test_count = nv_self_test_count,
4584         .self_test = nv_self_test,
4585 };
4586
4587 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
4588 {
4589         struct fe_priv *np = get_nvpriv(dev);
4590
4591         spin_lock_irq(&np->lock);
4592
4593         /* save vlan group */
4594         np->vlangrp = grp;
4595
4596         if (grp) {
4597                 /* enable vlan on MAC */
4598                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
4599         } else {
4600                 /* disable vlan on MAC */
4601                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
4602                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
4603         }
4604
4605         writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4606
4607         spin_unlock_irq(&np->lock);
4608 };
4609
4610 static void nv_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
4611 {
4612         /* nothing to do */
4613 };
4614
4615 /* The mgmt unit and driver use a semaphore to access the phy during init */
4616 static int nv_mgmt_acquire_sema(struct net_device *dev)
4617 {
4618         u8 __iomem *base = get_hwbase(dev);
4619         int i;
4620         u32 tx_ctrl, mgmt_sema;
4621
4622         for (i = 0; i < 10; i++) {
4623                 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
4624                 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
4625                         break;
4626                 msleep(500);
4627         }
4628
4629         if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
4630                 return 0;
4631
4632         for (i = 0; i < 2; i++) {
4633                 tx_ctrl = readl(base + NvRegTransmitterControl);
4634                 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
4635                 writel(tx_ctrl, base + NvRegTransmitterControl);
4636
4637                 /* verify that semaphore was acquired */
4638                 tx_ctrl = readl(base + NvRegTransmitterControl);
4639                 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
4640                     ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE))
4641                         return 1;
4642                 else
4643                         udelay(50);
4644         }
4645
4646         return 0;
4647 }
4648
4649 static int nv_open(struct net_device *dev)
4650 {
4651         struct fe_priv *np = netdev_priv(dev);
4652         u8 __iomem *base = get_hwbase(dev);
4653         int ret = 1;
4654         int oom, i;
4655
4656         dprintk(KERN_DEBUG "nv_open: begin\n");
4657
4658         /* erase previous misconfiguration */
4659         if (np->driver_data & DEV_HAS_POWER_CNTRL)
4660                 nv_mac_reset(dev);
4661         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4662         writel(0, base + NvRegMulticastAddrB);
4663         writel(0, base + NvRegMulticastMaskA);
4664         writel(0, base + NvRegMulticastMaskB);
4665         writel(0, base + NvRegPacketFilterFlags);
4666
4667         writel(0, base + NvRegTransmitterControl);
4668         writel(0, base + NvRegReceiverControl);
4669
4670         writel(0, base + NvRegAdapterControl);
4671
4672         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
4673                 writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
4674
4675         /* initialize descriptor rings */
4676         set_bufsize(dev);
4677         oom = nv_init_ring(dev);
4678
4679         writel(0, base + NvRegLinkSpeed);
4680         writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
4681         nv_txrx_reset(dev);
4682         writel(0, base + NvRegUnknownSetupReg6);
4683
4684         np->in_shutdown = 0;
4685
4686         /* give hw rings */
4687         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4688         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4689                 base + NvRegRingSizes);
4690
4691         writel(np->linkspeed, base + NvRegLinkSpeed);
4692         if (np->desc_ver == DESC_VER_1)
4693                 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
4694         else
4695                 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
4696         writel(np->txrxctl_bits, base + NvRegTxRxControl);
4697         writel(np->vlanctl_bits, base + NvRegVlanControl);
4698         pci_push(base);
4699         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
4700         reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
4701                         NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
4702                         KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
4703
4704         writel(0, base + NvRegMIIMask);
4705         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4706         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
4707
4708         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
4709         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
4710         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
4711         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4712
4713         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
4714         get_random_bytes(&i, sizeof(i));
4715         writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
4716         writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
4717         writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
4718         if (poll_interval == -1) {
4719                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
4720                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
4721                 else
4722                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4723         }
4724         else
4725                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
4726         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4727         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
4728                         base + NvRegAdapterControl);
4729         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
4730         writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
4731         if (np->wolenabled)
4732                 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
4733
4734         i = readl(base + NvRegPowerState);
4735         if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
4736                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
4737
4738         pci_push(base);
4739         udelay(10);
4740         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
4741
4742         nv_disable_hw_interrupts(dev, np->irqmask);
4743         pci_push(base);
4744         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
4745         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4746         pci_push(base);
4747
4748         if (nv_request_irq(dev, 0)) {
4749                 goto out_drain;
4750         }
4751
4752         /* ask for interrupts */
4753         nv_enable_hw_interrupts(dev, np->irqmask);
4754
4755         spin_lock_irq(&np->lock);
4756         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4757         writel(0, base + NvRegMulticastAddrB);
4758         writel(0, base + NvRegMulticastMaskA);
4759         writel(0, base + NvRegMulticastMaskB);
4760         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
4761         /* One manual link speed update: Interrupts are enabled, future link
4762          * speed changes cause interrupts and are handled by nv_link_irq().
4763          */
4764         {
4765                 u32 miistat;
4766                 miistat = readl(base + NvRegMIIStatus);
4767                 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
4768                 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
4769         }
4770         /* set linkspeed to invalid value, thus force nv_update_linkspeed
4771          * to init hw */
4772         np->linkspeed = 0;
4773         ret = nv_update_linkspeed(dev);
4774         nv_start_rx(dev);
4775         nv_start_tx(dev);
4776         netif_start_queue(dev);
4777         netif_poll_enable(dev);
4778
4779         if (ret) {
4780                 netif_carrier_on(dev);
4781         } else {
4782                 printk("%s: no link during initialization.\n", dev->name);
4783                 netif_carrier_off(dev);
4784         }
4785         if (oom)
4786                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4787
4788         /* start statistics timer */
4789         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2))
4790                 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
4791
4792         spin_unlock_irq(&np->lock);
4793
4794         return 0;
4795 out_drain:
4796         drain_ring(dev);
4797         return ret;
4798 }
4799
4800 static int nv_close(struct net_device *dev)
4801 {
4802         struct fe_priv *np = netdev_priv(dev);
4803         u8 __iomem *base;
4804
4805         spin_lock_irq(&np->lock);
4806         np->in_shutdown = 1;
4807         spin_unlock_irq(&np->lock);
4808         netif_poll_disable(dev);
4809         synchronize_irq(dev->irq);
4810
4811         del_timer_sync(&np->oom_kick);
4812         del_timer_sync(&np->nic_poll);
4813         del_timer_sync(&np->stats_poll);
4814
4815         netif_stop_queue(dev);
4816         spin_lock_irq(&np->lock);
4817         nv_stop_tx(dev);
4818         nv_stop_rx(dev);
4819         nv_txrx_reset(dev);
4820
4821         /* disable interrupts on the nic or we will lock up */
4822         base = get_hwbase(dev);
4823         nv_disable_hw_interrupts(dev, np->irqmask);
4824         pci_push(base);
4825         dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
4826
4827         spin_unlock_irq(&np->lock);
4828
4829         nv_free_irq(dev);
4830
4831         drain_ring(dev);
4832
4833         if (np->wolenabled)
4834                 nv_start_rx(dev);
4835
4836         /* FIXME: power down nic */
4837
4838         return 0;
4839 }
4840
4841 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
4842 {
4843         struct net_device *dev;
4844         struct fe_priv *np;
4845         unsigned long addr;
4846         u8 __iomem *base;
4847         int err, i;
4848         u32 powerstate, txreg;
4849         u32 phystate_orig = 0, phystate;
4850         int phyinitialized = 0;
4851
4852         dev = alloc_etherdev(sizeof(struct fe_priv));
4853         err = -ENOMEM;
4854         if (!dev)
4855                 goto out;
4856
4857         np = netdev_priv(dev);
4858         np->pci_dev = pci_dev;
4859         spin_lock_init(&np->lock);
4860         SET_MODULE_OWNER(dev);
4861         SET_NETDEV_DEV(dev, &pci_dev->dev);
4862
4863         init_timer(&np->oom_kick);
4864         np->oom_kick.data = (unsigned long) dev;
4865         np->oom_kick.function = &nv_do_rx_refill;       /* timer handler */
4866         init_timer(&np->nic_poll);
4867         np->nic_poll.data = (unsigned long) dev;
4868         np->nic_poll.function = &nv_do_nic_poll;        /* timer handler */
4869         init_timer(&np->stats_poll);
4870         np->stats_poll.data = (unsigned long) dev;
4871         np->stats_poll.function = &nv_do_stats_poll;    /* timer handler */
4872
4873         err = pci_enable_device(pci_dev);
4874         if (err) {
4875                 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
4876                                 err, pci_name(pci_dev));
4877                 goto out_free;
4878         }
4879
4880         pci_set_master(pci_dev);
4881
4882         err = pci_request_regions(pci_dev, DRV_NAME);
4883         if (err < 0)
4884                 goto out_disable;
4885
4886         if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2))
4887                 np->register_size = NV_PCI_REGSZ_VER3;
4888         else if (id->driver_data & DEV_HAS_STATISTICS_V1)
4889                 np->register_size = NV_PCI_REGSZ_VER2;
4890         else
4891                 np->register_size = NV_PCI_REGSZ_VER1;
4892
4893         err = -EINVAL;
4894         addr = 0;
4895         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
4896                 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
4897                                 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
4898                                 pci_resource_len(pci_dev, i),
4899                                 pci_resource_flags(pci_dev, i));
4900                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
4901                                 pci_resource_len(pci_dev, i) >= np->register_size) {
4902                         addr = pci_resource_start(pci_dev, i);
4903                         break;
4904                 }
4905         }
4906         if (i == DEVICE_COUNT_RESOURCE) {
4907                 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
4908                                         pci_name(pci_dev));
4909                 goto out_relreg;
4910         }
4911
4912         /* copy of driver data */
4913         np->driver_data = id->driver_data;
4914
4915         /* handle different descriptor versions */
4916         if (id->driver_data & DEV_HAS_HIGH_DMA) {
4917                 /* packet format 3: supports 40-bit addressing */
4918                 np->desc_ver = DESC_VER_3;
4919                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
4920                 if (dma_64bit) {
4921                         if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK)) {
4922                                 printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
4923                                        pci_name(pci_dev));
4924                         } else {
4925                                 dev->features |= NETIF_F_HIGHDMA;
4926                                 printk(KERN_INFO "forcedeth: using HIGHDMA\n");
4927                         }
4928                         if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) {
4929                                 printk(KERN_INFO "forcedeth: 64-bit DMA (consistent) failed, using 32-bit ring buffers for device %s.\n",
4930                                        pci_name(pci_dev));
4931                         }
4932                 }
4933         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
4934                 /* packet format 2: supports jumbo frames */
4935                 np->desc_ver = DESC_VER_2;
4936                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
4937         } else {
4938                 /* original packet format */
4939                 np->desc_ver = DESC_VER_1;
4940                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
4941         }
4942
4943         np->pkt_limit = NV_PKTLIMIT_1;
4944         if (id->driver_data & DEV_HAS_LARGEDESC)
4945                 np->pkt_limit = NV_PKTLIMIT_2;
4946
4947         if (id->driver_data & DEV_HAS_CHECKSUM) {
4948                 np->rx_csum = 1;
4949                 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4950                 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
4951                 dev->features |= NETIF_F_TSO;
4952         }
4953
4954         np->vlanctl_bits = 0;
4955         if (id->driver_data & DEV_HAS_VLAN) {
4956                 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
4957                 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
4958                 dev->vlan_rx_register = nv_vlan_rx_register;
4959                 dev->vlan_rx_kill_vid = nv_vlan_rx_kill_vid;
4960         }
4961
4962         np->msi_flags = 0;
4963         if ((id->driver_data & DEV_HAS_MSI) && msi) {
4964                 np->msi_flags |= NV_MSI_CAPABLE;
4965         }
4966         if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
4967                 np->msi_flags |= NV_MSI_X_CAPABLE;
4968         }
4969
4970         np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
4971         if (id->driver_data & DEV_HAS_PAUSEFRAME_TX) {
4972                 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
4973         }
4974
4975
4976         err = -ENOMEM;
4977         np->base = ioremap(addr, np->register_size);
4978         if (!np->base)
4979                 goto out_relreg;
4980         dev->base_addr = (unsigned long)np->base;
4981
4982         dev->irq = pci_dev->irq;
4983
4984         np->rx_ring_size = RX_RING_DEFAULT;
4985         np->tx_ring_size = TX_RING_DEFAULT;
4986
4987         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4988                 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
4989                                         sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
4990                                         &np->ring_addr);
4991                 if (!np->rx_ring.orig)
4992                         goto out_unmap;
4993                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4994         } else {
4995                 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
4996                                         sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
4997                                         &np->ring_addr);
4998                 if (!np->rx_ring.ex)
4999                         goto out_unmap;
5000                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
5001         }
5002         np->rx_skb = kmalloc(sizeof(struct nv_skb_map) * np->rx_ring_size, GFP_KERNEL);
5003         np->tx_skb = kmalloc(sizeof(struct nv_skb_map) * np->tx_ring_size, GFP_KERNEL);
5004         if (!np->rx_skb || !np->tx_skb)
5005                 goto out_freering;
5006         memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
5007         memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
5008
5009         dev->open = nv_open;
5010         dev->stop = nv_close;
5011         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
5012                 dev->hard_start_xmit = nv_start_xmit;
5013         else
5014                 dev->hard_start_xmit = nv_start_xmit_optimized;
5015         dev->get_stats = nv_get_stats;
5016         dev->change_mtu = nv_change_mtu;
5017         dev->set_mac_address = nv_set_mac_address;
5018         dev->set_multicast_list = nv_set_multicast;
5019 #ifdef CONFIG_NET_POLL_CONTROLLER
5020         dev->poll_controller = nv_poll_controller;
5021 #endif
5022         dev->weight = RX_WORK_PER_LOOP;
5023 #ifdef CONFIG_FORCEDETH_NAPI
5024         dev->poll = nv_napi_poll;
5025 #endif
5026         SET_ETHTOOL_OPS(dev, &ops);
5027         dev->tx_timeout = nv_tx_timeout;
5028         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5029
5030         pci_set_drvdata(pci_dev, dev);
5031
5032         /* read the mac address */
5033         base = get_hwbase(dev);
5034         np->orig_mac[0] = readl(base + NvRegMacAddrA);
5035         np->orig_mac[1] = readl(base + NvRegMacAddrB);
5036
5037         /* check the workaround bit for correct mac address order */
5038         txreg = readl(base + NvRegTransmitPoll);
5039         if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5040                 /* mac address is already in correct order */
5041                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5042                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5043                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5044                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5045                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5046                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5047         } else {
5048                 /* need to reverse mac address to correct order */
5049                 dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
5050                 dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
5051                 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5052                 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5053                 dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
5054                 dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
5055                 /* set permanent address to be correct aswell */
5056                 np->orig_mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
5057                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
5058                 np->orig_mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
5059                 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5060         }
5061         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
5062
5063         if (!is_valid_ether_addr(dev->perm_addr)) {
5064                 /*
5065                  * Bad mac address. At least one bios sets the mac address
5066                  * to 01:23:45:67:89:ab
5067                  */
5068                 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
5069                         pci_name(pci_dev),
5070                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
5071                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
5072                 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
5073                 dev->dev_addr[0] = 0x00;
5074                 dev->dev_addr[1] = 0x00;
5075                 dev->dev_addr[2] = 0x6c;
5076                 get_random_bytes(&dev->dev_addr[3], 3);
5077         }
5078
5079         dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
5080                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
5081                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
5082
5083         /* set mac address */
5084         nv_copy_mac_to_hw(dev);
5085
5086         /* disable WOL */
5087         writel(0, base + NvRegWakeUpFlags);
5088         np->wolenabled = 0;
5089
5090         if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5091                 u8 revision_id;
5092                 pci_read_config_byte(pci_dev, PCI_REVISION_ID, &revision_id);
5093
5094                 /* take phy and nic out of low power mode */
5095                 powerstate = readl(base + NvRegPowerState2);
5096                 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5097                 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
5098                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
5099                     revision_id >= 0xA3)
5100                         powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5101                 writel(powerstate, base + NvRegPowerState2);
5102         }
5103
5104         if (np->desc_ver == DESC_VER_1) {
5105                 np->tx_flags = NV_TX_VALID;
5106         } else {
5107                 np->tx_flags = NV_TX2_VALID;
5108         }
5109         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
5110                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5111                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5112                         np->msi_flags |= 0x0003;
5113         } else {
5114                 np->irqmask = NVREG_IRQMASK_CPU;
5115                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5116                         np->msi_flags |= 0x0001;
5117         }
5118
5119         if (id->driver_data & DEV_NEED_TIMERIRQ)
5120                 np->irqmask |= NVREG_IRQ_TIMER;
5121         if (id->driver_data & DEV_NEED_LINKTIMER) {
5122                 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
5123                 np->need_linktimer = 1;
5124                 np->link_timeout = jiffies + LINK_TIMEOUT;
5125         } else {
5126                 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
5127                 np->need_linktimer = 0;
5128         }
5129
5130         /* clear phy state and temporarily halt phy interrupts */
5131         writel(0, base + NvRegMIIMask);
5132         phystate = readl(base + NvRegAdapterControl);
5133         if (phystate & NVREG_ADAPTCTL_RUNNING) {
5134                 phystate_orig = 1;
5135                 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5136                 writel(phystate, base + NvRegAdapterControl);
5137         }
5138         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
5139
5140         if (id->driver_data & DEV_HAS_MGMT_UNIT) {
5141                 /* management unit running on the mac? */
5142                 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) {
5143                         np->mac_in_use = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST;
5144                         dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n", pci_name(pci_dev), np->mac_in_use);
5145                         for (i = 0; i < 5000; i++) {
5146                                 msleep(1);
5147                                 if (nv_mgmt_acquire_sema(dev)) {
5148                                         /* management unit setup the phy already? */
5149                                         if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5150                                             NVREG_XMITCTL_SYNC_PHY_INIT) {
5151                                                 /* phy is inited by mgmt unit */
5152                                                 phyinitialized = 1;
5153                                                 dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n", pci_name(pci_dev));
5154                                         } else {
5155                                                 /* we need to init the phy */
5156                                         }
5157                                         break;
5158                                 }
5159                         }
5160                 }
5161         }
5162
5163         /* find a suitable phy */
5164         for (i = 1; i <= 32; i++) {
5165                 int id1, id2;
5166                 int phyaddr = i & 0x1F;
5167
5168                 spin_lock_irq(&np->lock);
5169                 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5170                 spin_unlock_irq(&np->lock);
5171                 if (id1 < 0 || id1 == 0xffff)
5172                         continue;
5173                 spin_lock_irq(&np->lock);
5174                 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5175                 spin_unlock_irq(&np->lock);
5176                 if (id2 < 0 || id2 == 0xffff)
5177                         continue;
5178
5179                 np->phy_model = id2 & PHYID2_MODEL_MASK;
5180                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5181                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5182                 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
5183                         pci_name(pci_dev), id1, id2, phyaddr);
5184                 np->phyaddr = phyaddr;
5185                 np->phy_oui = id1 | id2;
5186                 break;
5187         }
5188         if (i == 33) {
5189                 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
5190                        pci_name(pci_dev));
5191                 goto out_error;
5192         }
5193
5194         if (!phyinitialized) {
5195                 /* reset it */
5196                 phy_init(dev);
5197         } else {
5198                 /* see if it is a gigabit phy */
5199                 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5200                 if (mii_status & PHY_GIGABIT) {
5201                         np->gigabit = PHY_GIGABIT;
5202                 }
5203         }
5204
5205         /* set default link speed settings */
5206         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5207         np->duplex = 0;
5208         np->autoneg = 1;
5209
5210         err = register_netdev(dev);
5211         if (err) {
5212                 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
5213                 goto out_error;
5214         }
5215         printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
5216                         dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
5217                         pci_name(pci_dev));
5218
5219         return 0;
5220
5221 out_error:
5222         if (phystate_orig)
5223                 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
5224         pci_set_drvdata(pci_dev, NULL);
5225 out_freering:
5226         free_rings(dev);
5227 out_unmap:
5228         iounmap(get_hwbase(dev));
5229 out_relreg:
5230         pci_release_regions(pci_dev);
5231 out_disable:
5232         pci_disable_device(pci_dev);
5233 out_free:
5234         free_netdev(dev);
5235 out:
5236         return err;
5237 }
5238
5239 static void __devexit nv_remove(struct pci_dev *pci_dev)
5240 {
5241         struct net_device *dev = pci_get_drvdata(pci_dev);
5242         struct fe_priv *np = netdev_priv(dev);
5243         u8 __iomem *base = get_hwbase(dev);
5244
5245         unregister_netdev(dev);
5246
5247         /* special op: write back the misordered MAC address - otherwise
5248          * the next nv_probe would see a wrong address.
5249          */
5250         writel(np->orig_mac[0], base + NvRegMacAddrA);
5251         writel(np->orig_mac[1], base + NvRegMacAddrB);
5252
5253         /* free all structures */
5254         free_rings(dev);
5255         iounmap(get_hwbase(dev));
5256         pci_release_regions(pci_dev);
5257         pci_disable_device(pci_dev);
5258         free_netdev(dev);
5259         pci_set_drvdata(pci_dev, NULL);
5260 }
5261
5262 #ifdef CONFIG_PM
5263 static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
5264 {
5265         struct net_device *dev = pci_get_drvdata(pdev);
5266         struct fe_priv *np = netdev_priv(dev);
5267
5268         if (!netif_running(dev))
5269                 goto out;
5270
5271         netif_device_detach(dev);
5272
5273         // Gross.
5274         nv_close(dev);
5275
5276         pci_save_state(pdev);
5277         pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
5278         pci_set_power_state(pdev, pci_choose_state(pdev, state));
5279 out:
5280         return 0;
5281 }
5282
5283 static int nv_resume(struct pci_dev *pdev)
5284 {
5285         struct net_device *dev = pci_get_drvdata(pdev);
5286         int rc = 0;
5287
5288         if (!netif_running(dev))
5289                 goto out;
5290
5291         netif_device_attach(dev);
5292
5293         pci_set_power_state(pdev, PCI_D0);
5294         pci_restore_state(pdev);
5295         pci_enable_wake(pdev, PCI_D0, 0);
5296
5297         rc = nv_open(dev);
5298 out:
5299         return rc;
5300 }
5301 #else
5302 #define nv_suspend NULL
5303 #define nv_resume NULL
5304 #endif /* CONFIG_PM */
5305
5306 static struct pci_device_id pci_tbl[] = {
5307         {       /* nForce Ethernet Controller */
5308                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
5309                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5310         },
5311         {       /* nForce2 Ethernet Controller */
5312                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
5313                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5314         },
5315         {       /* nForce3 Ethernet Controller */
5316                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
5317                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5318         },
5319         {       /* nForce3 Ethernet Controller */
5320                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
5321                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5322         },
5323         {       /* nForce3 Ethernet Controller */
5324                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
5325                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5326         },
5327         {       /* nForce3 Ethernet Controller */
5328                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
5329                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5330         },
5331         {       /* nForce3 Ethernet Controller */
5332                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
5333                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5334         },
5335         {       /* CK804 Ethernet Controller */
5336                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
5337                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1,
5338         },
5339         {       /* CK804 Ethernet Controller */
5340                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
5341                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1,
5342         },
5343         {       /* MCP04 Ethernet Controller */
5344                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
5345                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1,
5346         },
5347         {       /* MCP04 Ethernet Controller */
5348                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
5349                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1,
5350         },
5351         {       /* MCP51 Ethernet Controller */
5352                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
5353                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1,
5354         },
5355         {       /* MCP51 Ethernet Controller */
5356                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
5357                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1,
5358         },
5359         {       /* MCP55 Ethernet Controller */
5360                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
5361                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5362         },
5363         {       /* MCP55 Ethernet Controller */
5364                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
5365                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5366         },
5367         {       /* MCP61 Ethernet Controller */
5368                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),
5369                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5370         },
5371         {       /* MCP61 Ethernet Controller */
5372                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17),
5373                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5374         },
5375         {       /* MCP61 Ethernet Controller */
5376                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18),
5377                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5378         },
5379         {       /* MCP61 Ethernet Controller */
5380                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19),
5381                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5382         },
5383         {       /* MCP65 Ethernet Controller */
5384                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
5385                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5386         },
5387         {       /* MCP65 Ethernet Controller */
5388                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
5389                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5390         },
5391         {       /* MCP65 Ethernet Controller */
5392                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
5393                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5394         },
5395         {       /* MCP65 Ethernet Controller */
5396                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
5397                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5398         },
5399         {       /* MCP67 Ethernet Controller */
5400                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_24),
5401                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5402         },
5403         {       /* MCP67 Ethernet Controller */
5404                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_25),
5405                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5406         },
5407         {       /* MCP67 Ethernet Controller */
5408                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_26),
5409                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5410         },
5411         {       /* MCP67 Ethernet Controller */
5412                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_27),
5413                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5414         },
5415         {0,},
5416 };
5417
5418 static struct pci_driver driver = {
5419         .name = "forcedeth",
5420         .id_table = pci_tbl,
5421         .probe = nv_probe,
5422         .remove = __devexit_p(nv_remove),
5423         .suspend = nv_suspend,
5424         .resume = nv_resume,
5425 };
5426
5427 static int __init init_nic(void)
5428 {
5429         printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
5430         return pci_register_driver(&driver);
5431 }
5432
5433 static void __exit exit_nic(void)
5434 {
5435         pci_unregister_driver(&driver);
5436 }
5437
5438 module_param(max_interrupt_work, int, 0);
5439 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
5440 module_param(optimization_mode, int, 0);
5441 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
5442 module_param(poll_interval, int, 0);
5443 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
5444 module_param(msi, int, 0);
5445 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
5446 module_param(msix, int, 0);
5447 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
5448 module_param(dma_64bit, int, 0);
5449 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
5450
5451 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
5452 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
5453 MODULE_LICENSE("GPL");
5454
5455 MODULE_DEVICE_TABLE(pci, pci_tbl);
5456
5457 module_init(init_nic);
5458 module_exit(exit_nic);