drivers/net/ethernet/ti/cpsw.c

   1 /*
   2  * Texas Instruments Ethernet Switch Driver
   3  *
   4  * Copyright (C) 2012 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/io.h>
  18 #include <linux/clk.h>
  19 #include <linux/timer.h>
  20 #include <linux/module.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/irqreturn.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/if_ether.h>
  25 #include <linux/etherdevice.h>
  26 #include <linux/netdevice.h>
  27 #include <linux/net_tstamp.h>
  28 #include <linux/phy.h>
  29 #include <linux/workqueue.h>
  30 #include <linux/delay.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/of.h>
  33 #include <linux/of_net.h>
  34 #include <linux/of_device.h>
  35 #include <linux/if_vlan.h>
  36
  37 #include <linux/pinctrl/consumer.h>
  38
  39 #include "cpsw.h"
  40 #include "cpsw_ale.h"
  41 #include "cpts.h"
  42 #include "davinci_cpdma.h"
  43
  44 #define CPSW_DEBUG      (NETIF_MSG_HW           | NETIF_MSG_WOL         | \
  45                          NETIF_MSG_DRV          | NETIF_MSG_LINK        | \
  46                          NETIF_MSG_IFUP         | NETIF_MSG_INTR        | \
  47                          NETIF_MSG_PROBE        | NETIF_MSG_TIMER       | \
  48                          NETIF_MSG_IFDOWN       | NETIF_MSG_RX_ERR      | \
  49                          NETIF_MSG_TX_ERR       | NETIF_MSG_TX_DONE     | \
  50                          NETIF_MSG_PKTDATA      | NETIF_MSG_TX_QUEUED   | \
  51                          NETIF_MSG_RX_STATUS)
  52
  53 #define cpsw_info(priv, type, format, ...)              \
  54 do {                                                            \
  55         if (netif_msg_##type(priv) && net_ratelimit())          \
  56                 dev_info(priv->dev, format, ## __VA_ARGS__);    \
  57 } while (0)
  58
  59 #define cpsw_err(priv, type, format, ...)               \
  60 do {                                                            \
  61         if (netif_msg_##type(priv) && net_ratelimit())          \
  62                 dev_err(priv->dev, format, ## __VA_ARGS__);     \
  63 } while (0)
  64
  65 #define cpsw_dbg(priv, type, format, ...)               \
  66 do {                                                            \
  67         if (netif_msg_##type(priv) && net_ratelimit())          \
  68                 dev_dbg(priv->dev, format, ## __VA_ARGS__);     \
  69 } while (0)
  70
  71 #define cpsw_notice(priv, type, format, ...)            \
  72 do {                                                            \
  73         if (netif_msg_##type(priv) && net_ratelimit())          \
  74                 dev_notice(priv->dev, format, ## __VA_ARGS__);  \
  75 } while (0)
  76
  77 #define ALE_ALL_PORTS           0x7
  78
  79 #define CPSW_MAJOR_VERSION(reg)         (reg >> 8 & 0x7)
  80 #define CPSW_MINOR_VERSION(reg)         (reg & 0xff)
  81 #define CPSW_RTL_VERSION(reg)           ((reg >> 11) & 0x1f)
  82
  83 #define CPSW_VERSION_1          0x19010a
  84 #define CPSW_VERSION_2          0x19010c
  85 #define CPSW_VERSION_3          0x19010f
  86 #define CPSW_VERSION_4          0x190112
  87
  88 #define HOST_PORT_NUM           0
  89 #define SLIVER_SIZE             0x40
  90
  91 #define CPSW1_HOST_PORT_OFFSET  0x028
  92 #define CPSW1_SLAVE_OFFSET      0x050
  93 #define CPSW1_SLAVE_SIZE        0x040
  94 #define CPSW1_CPDMA_OFFSET      0x100
  95 #define CPSW1_STATERAM_OFFSET   0x200
  96 #define CPSW1_HW_STATS          0x400
  97 #define CPSW1_CPTS_OFFSET       0x500
  98 #define CPSW1_ALE_OFFSET        0x600
  99 #define CPSW1_SLIVER_OFFSET     0x700
 100
 101 #define CPSW2_HOST_PORT_OFFSET  0x108
 102 #define CPSW2_SLAVE_OFFSET      0x200
 103 #define CPSW2_SLAVE_SIZE        0x100
 104 #define CPSW2_CPDMA_OFFSET      0x800
 105 #define CPSW2_HW_STATS          0x900
 106 #define CPSW2_STATERAM_OFFSET   0xa00
 107 #define CPSW2_CPTS_OFFSET       0xc00
 108 #define CPSW2_ALE_OFFSET        0xd00
 109 #define CPSW2_SLIVER_OFFSET     0xd80
 110 #define CPSW2_BD_OFFSET         0x2000
 111
 112 #define CPDMA_RXTHRESH          0x0c0
 113 #define CPDMA_RXFREE            0x0e0
 114 #define CPDMA_TXHDP             0x00
 115 #define CPDMA_RXHDP             0x20
 116 #define CPDMA_TXCP              0x40
 117 #define CPDMA_RXCP              0x60
 118
 119 #define CPSW_POLL_WEIGHT        64
 120 #define CPSW_MIN_PACKET_SIZE    60
 121 #define CPSW_MAX_PACKET_SIZE    (1500 + 14 + 4 + 4)
 122
 123 #define RX_PRIORITY_MAPPING     0x76543210
 124 #define TX_PRIORITY_MAPPING     0x33221100
 125 #define CPDMA_TX_PRIORITY_MAP   0x76543210
 126
 127 #define CPSW_VLAN_AWARE         BIT(1)
 128 #define CPSW_ALE_VLAN_AWARE     1
 129
 130 #define CPSW_FIFO_NORMAL_MODE           (0 << 15)
 131 #define CPSW_FIFO_DUAL_MAC_MODE         (1 << 15)
 132 #define CPSW_FIFO_RATE_LIMIT_MODE       (2 << 15)
 133
 134 #define CPSW_INTPACEEN          (0x3f << 16)
 135 #define CPSW_INTPRESCALE_MASK   (0x7FF << 0)
 136 #define CPSW_CMINTMAX_CNT       63
 137 #define CPSW_CMINTMIN_CNT       2
 138 #define CPSW_CMINTMAX_INTVL     (1000 / CPSW_CMINTMIN_CNT)
 139 #define CPSW_CMINTMIN_INTVL     ((1000 / CPSW_CMINTMAX_CNT) + 1)
 140
 141 #define cpsw_enable_irq(priv)   \
 142         do {                    \
 143                 u32 i;          \
 144                 for (i = 0; i < priv->num_irqs; i++) \
 145                         enable_irq(priv->irqs_table[i]); \
 146         } while (0)
 147 #define cpsw_disable_irq(priv)  \
 148         do {                    \
 149                 u32 i;          \
 150                 for (i = 0; i < priv->num_irqs; i++) \
 151                         disable_irq_nosync(priv->irqs_table[i]); \
 152         } while (0)
 153
 154 #define cpsw_slave_index(priv)                          \
 155                 ((priv->data.dual_emac) ? priv->emac_port :     \
 156                 priv->data.active_slave)
 157
 158 static int debug_level;
 159 module_param(debug_level, int, 0);
 160 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
 161
 162 static int ale_ageout = 10;
 163 module_param(ale_ageout, int, 0);
 164 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
 165
 166 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
 167 module_param(rx_packet_max, int, 0);
 168 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
 169
 170 struct cpsw_wr_regs {
 171         u32     id_ver;
 172         u32     soft_reset;
 173         u32     control;
 174         u32     int_control;
 175         u32     rx_thresh_en;
 176         u32     rx_en;
 177         u32     tx_en;
 178         u32     misc_en;
 179         u32     mem_allign1[8];
 180         u32     rx_thresh_stat;
 181         u32     rx_stat;
 182         u32     tx_stat;
 183         u32     misc_stat;
 184         u32     mem_allign2[8];
 185         u32     rx_imax;
 186         u32     tx_imax;
 187
 188 };
 189
 190 struct cpsw_ss_regs {
 191         u32     id_ver;
 192         u32     control;
 193         u32     soft_reset;
 194         u32     stat_port_en;
 195         u32     ptype;
 196         u32     soft_idle;
 197         u32     thru_rate;
 198         u32     gap_thresh;
 199         u32     tx_start_wds;
 200         u32     flow_control;
 201         u32     vlan_ltype;
 202         u32     ts_ltype;
 203         u32     dlr_ltype;
 204 };
 205
 206 /* CPSW_PORT_V1 */
 207 #define CPSW1_MAX_BLKS      0x00 /* Maximum FIFO Blocks */
 208 #define CPSW1_BLK_CNT       0x04 /* FIFO Block Usage Count (Read Only) */
 209 #define CPSW1_TX_IN_CTL     0x08 /* Transmit FIFO Control */
 210 #define CPSW1_PORT_VLAN     0x0c /* VLAN Register */
 211 #define CPSW1_TX_PRI_MAP    0x10 /* Tx Header Priority to Switch Pri Mapping */
 212 #define CPSW1_TS_CTL        0x14 /* Time Sync Control */
 213 #define CPSW1_TS_SEQ_LTYPE  0x18 /* Time Sync Sequence ID Offset and Msg Type */
 214 #define CPSW1_TS_VLAN       0x1c /* Time Sync VLAN1 and VLAN2 */
 215
 216 /* CPSW_PORT_V2 */
 217 #define CPSW2_CONTROL       0x00 /* Control Register */
 218 #define CPSW2_MAX_BLKS      0x08 /* Maximum FIFO Blocks */
 219 #define CPSW2_BLK_CNT       0x0c /* FIFO Block Usage Count (Read Only) */
 220 #define CPSW2_TX_IN_CTL     0x10 /* Transmit FIFO Control */
 221 #define CPSW2_PORT_VLAN     0x14 /* VLAN Register */
 222 #define CPSW2_TX_PRI_MAP    0x18 /* Tx Header Priority to Switch Pri Mapping */
 223 #define CPSW2_TS_SEQ_MTYPE  0x1c /* Time Sync Sequence ID Offset and Msg Type */
 224
 225 /* CPSW_PORT_V1 and V2 */
 226 #define SA_LO               0x20 /* CPGMAC_SL Source Address Low */
 227 #define SA_HI               0x24 /* CPGMAC_SL Source Address High */
 228 #define SEND_PERCENT        0x28 /* Transmit Queue Send Percentages */
 229
 230 /* CPSW_PORT_V2 only */
 231 #define RX_DSCP_PRI_MAP0    0x30 /* Rx DSCP Priority to Rx Packet Mapping */
 232 #define RX_DSCP_PRI_MAP1    0x34 /* Rx DSCP Priority to Rx Packet Mapping */
 233 #define RX_DSCP_PRI_MAP2    0x38 /* Rx DSCP Priority to Rx Packet Mapping */
 234 #define RX_DSCP_PRI_MAP3    0x3c /* Rx DSCP Priority to Rx Packet Mapping */
 235 #define RX_DSCP_PRI_MAP4    0x40 /* Rx DSCP Priority to Rx Packet Mapping */
 236 #define RX_DSCP_PRI_MAP5    0x44 /* Rx DSCP Priority to Rx Packet Mapping */
 237 #define RX_DSCP_PRI_MAP6    0x48 /* Rx DSCP Priority to Rx Packet Mapping */
 238 #define RX_DSCP_PRI_MAP7    0x4c /* Rx DSCP Priority to Rx Packet Mapping */
 239
 240 /* Bit definitions for the CPSW2_CONTROL register */
 241 #define PASS_PRI_TAGGED     (1<<24) /* Pass Priority Tagged */
 242 #define VLAN_LTYPE2_EN      (1<<21) /* VLAN LTYPE 2 enable */
 243 #define VLAN_LTYPE1_EN      (1<<20) /* VLAN LTYPE 1 enable */
 244 #define DSCP_PRI_EN         (1<<16) /* DSCP Priority Enable */
 245 #define TS_320              (1<<14) /* Time Sync Dest Port 320 enable */
 246 #define TS_319              (1<<13) /* Time Sync Dest Port 319 enable */
 247 #define TS_132              (1<<12) /* Time Sync Dest IP Addr 132 enable */
 248 #define TS_131              (1<<11) /* Time Sync Dest IP Addr 131 enable */
 249 #define TS_130              (1<<10) /* Time Sync Dest IP Addr 130 enable */
 250 #define TS_129              (1<<9)  /* Time Sync Dest IP Addr 129 enable */
 251 #define TS_TTL_NONZERO      (1<<8)  /* Time Sync Time To Live Non-zero enable */
 252 #define TS_ANNEX_F_EN       (1<<6)  /* Time Sync Annex F enable */
 253 #define TS_ANNEX_D_EN       (1<<4)  /* Time Sync Annex D enable */
 254 #define TS_LTYPE2_EN        (1<<3)  /* Time Sync LTYPE 2 enable */
 255 #define TS_LTYPE1_EN        (1<<2)  /* Time Sync LTYPE 1 enable */
 256 #define TS_TX_EN            (1<<1)  /* Time Sync Transmit Enable */
 257 #define TS_RX_EN            (1<<0)  /* Time Sync Receive Enable */
 258
 259 #define CTRL_V2_TS_BITS \
 260         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 261          TS_TTL_NONZERO  | TS_ANNEX_D_EN | TS_LTYPE1_EN)
 262
 263 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
 264 #define CTRL_V2_TX_TS_BITS  (CTRL_V2_TS_BITS | TS_TX_EN)
 265 #define CTRL_V2_RX_TS_BITS  (CTRL_V2_TS_BITS | TS_RX_EN)
 266
 267
 268 #define CTRL_V3_TS_BITS \
 269         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 270          TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
 271          TS_LTYPE1_EN)
 272
 273 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
 274 #define CTRL_V3_TX_TS_BITS  (CTRL_V3_TS_BITS | TS_TX_EN)
 275 #define CTRL_V3_RX_TS_BITS  (CTRL_V3_TS_BITS | TS_RX_EN)
 276
 277 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
 278 #define TS_SEQ_ID_OFFSET_SHIFT   (16)    /* Time Sync Sequence ID Offset */
 279 #define TS_SEQ_ID_OFFSET_MASK    (0x3f)
 280 #define TS_MSG_TYPE_EN_SHIFT     (0)     /* Time Sync Message Type Enable */
 281 #define TS_MSG_TYPE_EN_MASK      (0xffff)
 282
 283 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
 284 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
 285
 286 /* Bit definitions for the CPSW1_TS_CTL register */
 287 #define CPSW_V1_TS_RX_EN                BIT(0)
 288 #define CPSW_V1_TS_TX_EN                BIT(4)
 289 #define CPSW_V1_MSG_TYPE_OFS            16
 290
 291 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
 292 #define CPSW_V1_SEQ_ID_OFS_SHIFT        16
 293
 294 struct cpsw_host_regs {
 295         u32     max_blks;
 296         u32     blk_cnt;
 297         u32     tx_in_ctl;
 298         u32     port_vlan;
 299         u32     tx_pri_map;
 300         u32     cpdma_tx_pri_map;
 301         u32     cpdma_rx_chan_map;
 302 };
 303
 304 struct cpsw_sliver_regs {
 305         u32     id_ver;
 306         u32     mac_control;
 307         u32     mac_status;
 308         u32     soft_reset;
 309         u32     rx_maxlen;
 310         u32     __reserved_0;
 311         u32     rx_pause;
 312         u32     tx_pause;
 313         u32     __reserved_1;
 314         u32     rx_pri_map;
 315 };
 316
 317 struct cpsw_hw_stats {
 318         u32     rxgoodframes;
 319         u32     rxbroadcastframes;
 320         u32     rxmulticastframes;
 321         u32     rxpauseframes;
 322         u32     rxcrcerrors;
 323         u32     rxaligncodeerrors;
 324         u32     rxoversizedframes;
 325         u32     rxjabberframes;
 326         u32     rxundersizedframes;
 327         u32     rxfragments;
 328         u32     __pad_0[2];
 329         u32     rxoctets;
 330         u32     txgoodframes;
 331         u32     txbroadcastframes;
 332         u32     txmulticastframes;
 333         u32     txpauseframes;
 334         u32     txdeferredframes;
 335         u32     txcollisionframes;
 336         u32     txsinglecollframes;
 337         u32     txmultcollframes;
 338         u32     txexcessivecollisions;
 339         u32     txlatecollisions;
 340         u32     txunderrun;
 341         u32     txcarriersenseerrors;
 342         u32     txoctets;
 343         u32     octetframes64;
 344         u32     octetframes65t127;
 345         u32     octetframes128t255;
 346         u32     octetframes256t511;
 347         u32     octetframes512t1023;
 348         u32     octetframes1024tup;
 349         u32     netoctets;
 350         u32     rxsofoverruns;
 351         u32     rxmofoverruns;
 352         u32     rxdmaoverruns;
 353 };
 354
 355 struct cpsw_slave {
 356         void __iomem                    *regs;
 357         struct cpsw_sliver_regs __iomem *sliver;
 358         int                             slave_num;
 359         u32                             mac_control;
 360         struct cpsw_slave_data          *data;
 361         struct phy_device               *phy;
 362         struct net_device               *ndev;
 363         u32                             port_vlan;
 364         u32                             open_stat;
 365 };
 366
 367 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
 368 {
 369         return __raw_readl(slave->regs + offset);
 370 }
 371
 372 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
 373 {
 374         __raw_writel(val, slave->regs + offset);
 375 }
 376
 377 struct cpsw_priv {
 378         spinlock_t                      lock;
 379         struct platform_device          *pdev;
 380         struct net_device               *ndev;
 381         struct napi_struct              napi;
 382         struct device                   *dev;
 383         struct cpsw_platform_data       data;
 384         struct cpsw_ss_regs __iomem     *regs;
 385         struct cpsw_wr_regs __iomem     *wr_regs;
 386         u8 __iomem                      *hw_stats;
 387         struct cpsw_host_regs __iomem   *host_port_regs;
 388         u32                             msg_enable;
 389         u32                             version;
 390         u32                             coal_intvl;
 391         u32                             bus_freq_mhz;
 392         int                             rx_packet_max;
 393         int                             host_port;
 394         struct clk                      *clk;
 395         u8                              mac_addr[ETH_ALEN];
 396         struct cpsw_slave               *slaves;
 397         struct cpdma_ctlr               *dma;
 398         struct cpdma_chan               *txch, *rxch;
 399         struct cpsw_ale                 *ale;
 400         /* snapshot of IRQ numbers */
 401         u32 irqs_table[4];
 402         u32 num_irqs;
 403         bool irq_enabled;
 404         struct cpts *cpts;
 405         u32 emac_port;
 406 };
 407
 408 struct cpsw_stats {
 409         char stat_string[ETH_GSTRING_LEN];
 410         int type;
 411         int sizeof_stat;
 412         int stat_offset;
 413 };
 414
 415 enum {
 416         CPSW_STATS,
 417         CPDMA_RX_STATS,
 418         CPDMA_TX_STATS,
 419 };
 420
 421 #define CPSW_STAT(m)            CPSW_STATS,                             \
 422                                 sizeof(((struct cpsw_hw_stats *)0)->m), \
 423                                 offsetof(struct cpsw_hw_stats, m)
 424 #define CPDMA_RX_STAT(m)        CPDMA_RX_STATS,                            \
 425                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 426                                 offsetof(struct cpdma_chan_stats, m)
 427 #define CPDMA_TX_STAT(m)        CPDMA_TX_STATS,                            \
 428                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 429                                 offsetof(struct cpdma_chan_stats, m)
 430
 431 static const struct cpsw_stats cpsw_gstrings_stats[] = {
 432         { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
 433         { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
 434         { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
 435         { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
 436         { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
 437         { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
 438         { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
 439         { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
 440         { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
 441         { "Rx Fragments", CPSW_STAT(rxfragments) },
 442         { "Rx Octets", CPSW_STAT(rxoctets) },
 443         { "Good Tx Frames", CPSW_STAT(txgoodframes) },
 444         { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
 445         { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
 446         { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
 447         { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
 448         { "Collisions", CPSW_STAT(txcollisionframes) },
 449         { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
 450         { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
 451         { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
 452         { "Late Collisions", CPSW_STAT(txlatecollisions) },
 453         { "Tx Underrun", CPSW_STAT(txunderrun) },
 454         { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
 455         { "Tx Octets", CPSW_STAT(txoctets) },
 456         { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
 457         { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
 458         { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
 459         { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
 460         { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
 461         { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
 462         { "Net Octets", CPSW_STAT(netoctets) },
 463         { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
 464         { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
 465         { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
 466         { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) },
 467         { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
 468         { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
 469         { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) },
 470         { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
 471         { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
 472         { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
 473         { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
 474         { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
 475         { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
 476         { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) },
 477         { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) },
 478         { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
 479         { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) },
 480         { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) },
 481         { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) },
 482         { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) },
 483         { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) },
 484         { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) },
 485         { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) },
 486         { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) },
 487         { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) },
 488         { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) },
 489         { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) },
 490         { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) },
 491         { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) },
 492 };
 493
 494 #define CPSW_STATS_LEN  ARRAY_SIZE(cpsw_gstrings_stats)
 495
 496 #define napi_to_priv(napi)      container_of(napi, struct cpsw_priv, napi)
 497 #define for_each_slave(priv, func, arg...)                              \
 498         do {                                                            \
 499                 struct cpsw_slave *slave;                               \
 500                 int n;                                                  \
 501                 if (priv->data.dual_emac)                               \
 502                         (func)((priv)->slaves + priv->emac_port, ##arg);\
 503                 else                                                    \
 504                         for (n = (priv)->data.slaves,                   \
 505                                         slave = (priv)->slaves;         \
 506                                         n; n--)                         \
 507                                 (func)(slave++, ##arg);                 \
 508         } while (0)
 509 #define cpsw_get_slave_ndev(priv, __slave_no__)                         \
 510         (priv->slaves[__slave_no__].ndev)
 511 #define cpsw_get_slave_priv(priv, __slave_no__)                         \
 512         ((priv->slaves[__slave_no__].ndev) ?                            \
 513                 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL)    \
 514
 515 #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb)         \
 516         do {                                                            \
 517                 if (!priv->data.dual_emac)                              \
 518                         break;                                          \
 519                 if (CPDMA_RX_SOURCE_PORT(status) == 1) {                \
 520                         ndev = cpsw_get_slave_ndev(priv, 0);            \
 521                         priv = netdev_priv(ndev);                       \
 522                         skb->dev = ndev;                                \
 523                 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) {         \
 524                         ndev = cpsw_get_slave_ndev(priv, 1);            \
 525                         priv = netdev_priv(ndev);                       \
 526                         skb->dev = ndev;                                \
 527                 }                                                       \
 528         } while (0)
 529 #define cpsw_add_mcast(priv, addr)                                      \
 530         do {                                                            \
 531                 if (priv->data.dual_emac) {                             \
 532                         struct cpsw_slave *slave = priv->slaves +       \
 533                                                 priv->emac_port;        \
 534                         int slave_port = cpsw_get_slave_port(priv,      \
 535                                                 slave->slave_num);      \
 536                         cpsw_ale_add_mcast(priv->ale, addr,             \
 537                                 1 << slave_port | 1 << priv->host_port, \
 538                                 ALE_VLAN, slave->port_vlan, 0);         \
 539                 } else {                                                \
 540                         cpsw_ale_add_mcast(priv->ale, addr,             \
 541                                 ALE_ALL_PORTS << priv->host_port,       \
 542                                 0, 0, 0);                               \
 543                 }                                                       \
 544         } while (0)
 545
 546 static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
 547 {
 548         if (priv->host_port == 0)
 549                 return slave_num + 1;
 550         else
 551                 return slave_num;
 552 }
 553
 554 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
 555 {
 556         struct cpsw_priv *priv = netdev_priv(ndev);
 557         struct cpsw_ale *ale = priv->ale;
 558         int i;
 559
 560         if (priv->data.dual_emac) {
 561                 bool flag = false;
 562
 563                 /* Enabling promiscuous mode for one interface will be
 564                  * common for both the interface as the interface shares
 565                  * the same hardware resource.
 566                  */
 567                 for (i = 0; i < priv->data.slaves; i++)
 568                         if (priv->slaves[i].ndev->flags & IFF_PROMISC)
 569                                 flag = true;
 570
 571                 if (!enable && flag) {
 572                         enable = true;
 573                         dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
 574                 }
 575
 576                 if (enable) {
 577                         /* Enable Bypass */
 578                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
 579
 580                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 581                 } else {
 582                         /* Disable Bypass */
 583                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
 584                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 585                 }
 586         } else {
 587                 if (enable) {
 588                         unsigned long timeout = jiffies + HZ;
 589
 590                         /* Disable Learn for all ports */
 591                         for (i = 0; i < priv->data.slaves; i++) {
 592                                 cpsw_ale_control_set(ale, i,
 593                                                      ALE_PORT_NOLEARN, 1);
 594                                 cpsw_ale_control_set(ale, i,
 595                                                      ALE_PORT_NO_SA_UPDATE, 1);
 596                         }
 597
 598                         /* Clear All Untouched entries */
 599                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 600                         do {
 601                                 cpu_relax();
 602                                 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
 603                                         break;
 604                         } while (time_after(timeout, jiffies));
 605                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 606
 607                         /* Clear all mcast from ALE */
 608                         cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS <<
 609                                                  priv->host_port);
 610
 611                         /* Flood All Unicast Packets to Host port */
 612                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
 613                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 614                 } else {
 615                         /* Flood All Unicast Packets to Host port */
 616                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
 617
 618                         /* Enable Learn for all ports */
 619                         for (i = 0; i < priv->data.slaves; i++) {
 620                                 cpsw_ale_control_set(ale, i,
 621                                                      ALE_PORT_NOLEARN, 0);
 622                                 cpsw_ale_control_set(ale, i,
 623                                                      ALE_PORT_NO_SA_UPDATE, 0);
 624                         }
 625                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 626                 }
 627         }
 628 }
 629
 630 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
 631 {
 632         struct cpsw_priv *priv = netdev_priv(ndev);
 633
 634         if (ndev->flags & IFF_PROMISC) {
 635                 /* Enable promiscuous mode */
 636                 cpsw_set_promiscious(ndev, true);
 637                 return;
 638         } else {
 639                 /* Disable promiscuous mode */
 640                 cpsw_set_promiscious(ndev, false);
 641         }
 642
 643         /* Clear all mcast from ALE */
 644         cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port);
 645
 646         if (!netdev_mc_empty(ndev)) {
 647                 struct netdev_hw_addr *ha;
 648
 649                 /* program multicast address list into ALE register */
 650                 netdev_for_each_mc_addr(ha, ndev) {
 651                         cpsw_add_mcast(priv, (u8 *)ha->addr);
 652                 }
 653         }
 654 }
 655
 656 static void cpsw_intr_enable(struct cpsw_priv *priv)
 657 {
 658         __raw_writel(0xFF, &priv->wr_regs->tx_en);
 659         __raw_writel(0xFF, &priv->wr_regs->rx_en);
 660
 661         cpdma_ctlr_int_ctrl(priv->dma, true);
 662         return;
 663 }
 664
 665 static void cpsw_intr_disable(struct cpsw_priv *priv)
 666 {
 667         __raw_writel(0, &priv->wr_regs->tx_en);
 668         __raw_writel(0, &priv->wr_regs->rx_en);
 669
 670         cpdma_ctlr_int_ctrl(priv->dma, false);
 671         return;
 672 }
 673
 674 static void cpsw_tx_handler(void *token, int len, int status)
 675 {
 676         struct sk_buff          *skb = token;
 677         struct net_device       *ndev = skb->dev;
 678         struct cpsw_priv        *priv = netdev_priv(ndev);
 679
 680         /* Check whether the queue is stopped due to stalled tx dma, if the
 681          * queue is stopped then start the queue as we have free desc for tx
 682          */
 683         if (unlikely(netif_queue_stopped(ndev)))
 684                 netif_wake_queue(ndev);
 685         cpts_tx_timestamp(priv->cpts, skb);
 686         ndev->stats.tx_packets++;
 687         ndev->stats.tx_bytes += len;
 688         dev_kfree_skb_any(skb);
 689 }
 690
 691 static void cpsw_rx_handler(void *token, int len, int status)
 692 {
 693         struct sk_buff          *skb = token;
 694         struct sk_buff          *new_skb;
 695         struct net_device       *ndev = skb->dev;
 696         struct cpsw_priv        *priv = netdev_priv(ndev);
 697         int                     ret = 0;
 698
 699         cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
 700
 701         if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
 702                 bool ndev_status = false;
 703                 struct cpsw_slave *slave = priv->slaves;
 704                 int n;
 705
 706                 if (priv->data.dual_emac) {
 707                         /* In dual emac mode check for all interfaces */
 708                         for (n = priv->data.slaves; n; n--, slave++)
 709                                 if (netif_running(slave->ndev))
 710                                         ndev_status = true;
 711                 }
 712
 713                 if (ndev_status && (status >= 0)) {
 714                         /* The packet received is for the interface which
 715                          * is already down and the other interface is up
 716                          * and running, intead of freeing which results
 717                          * in reducing of the number of rx descriptor in
 718                          * DMA engine, requeue skb back to cpdma.
 719                          */
 720                         new_skb = skb;
 721                         goto requeue;
 722                 }
 723
 724                 /* the interface is going down, skbs are purged */
 725                 dev_kfree_skb_any(skb);
 726                 return;
 727         }
 728
 729         new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
 730         if (new_skb) {
 731                 skb_put(skb, len);
 732                 cpts_rx_timestamp(priv->cpts, skb);
 733                 skb->protocol = eth_type_trans(skb, ndev);
 734                 netif_receive_skb(skb);
 735                 ndev->stats.rx_bytes += len;
 736                 ndev->stats.rx_packets++;
 737         } else {
 738                 ndev->stats.rx_dropped++;
 739                 new_skb = skb;
 740         }
 741
 742 requeue:
 743         ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
 744                         skb_tailroom(new_skb), 0);
 745         if (WARN_ON(ret < 0))
 746                 dev_kfree_skb_any(new_skb);
 747 }
 748
 749 static irqreturn_t cpsw_interrupt(int irq, void *dev_id)
 750 {
 751         struct cpsw_priv *priv = dev_id;
 752
 753         cpsw_intr_disable(priv);
 754         if (priv->irq_enabled == true) {
 755                 cpsw_disable_irq(priv);
 756                 priv->irq_enabled = false;
 757         }
 758
 759         if (netif_running(priv->ndev)) {
 760                 napi_schedule(&priv->napi);
 761                 return IRQ_HANDLED;
 762         }
 763
 764         priv = cpsw_get_slave_priv(priv, 1);
 765         if (!priv)
 766                 return IRQ_NONE;
 767
 768         if (netif_running(priv->ndev)) {
 769                 napi_schedule(&priv->napi);
 770                 return IRQ_HANDLED;
 771         }
 772         return IRQ_NONE;
 773 }
 774
 775 static int cpsw_poll(struct napi_struct *napi, int budget)
 776 {
 777         struct cpsw_priv        *priv = napi_to_priv(napi);
 778         int                     num_tx, num_rx;
 779
 780         num_tx = cpdma_chan_process(priv->txch, 128);
 781         if (num_tx)
 782                 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
 783
 784         num_rx = cpdma_chan_process(priv->rxch, budget);
 785         if (num_rx < budget) {
 786                 struct cpsw_priv *prim_cpsw;
 787
 788                 napi_complete(napi);
 789                 cpsw_intr_enable(priv);
 790                 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
 791                 prim_cpsw = cpsw_get_slave_priv(priv, 0);
 792                 if (prim_cpsw->irq_enabled == false) {
 793                         prim_cpsw->irq_enabled = true;
 794                         cpsw_enable_irq(priv);
 795                 }
 796         }
 797
 798         if (num_rx || num_tx)
 799                 cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n",
 800                          num_rx, num_tx);
 801
 802         return num_rx;
 803 }
 804
 805 static inline void soft_reset(const char *module, void __iomem *reg)
 806 {
 807         unsigned long timeout = jiffies + HZ;
 808
 809         __raw_writel(1, reg);
 810         do {
 811                 cpu_relax();
 812         } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
 813
 814         WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
 815 }
 816
 817 #define mac_hi(mac)     (((mac)[0] << 0) | ((mac)[1] << 8) |    \
 818                          ((mac)[2] << 16) | ((mac)[3] << 24))
 819 #define mac_lo(mac)     (((mac)[4] << 0) | ((mac)[5] << 8))
 820
 821 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
 822                                struct cpsw_priv *priv)
 823 {
 824         slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
 825         slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
 826 }
 827
 828 static void _cpsw_adjust_link(struct cpsw_slave *slave,
 829                               struct cpsw_priv *priv, bool *link)
 830 {
 831         struct phy_device       *phy = slave->phy;
 832         u32                     mac_control = 0;
 833         u32                     slave_port;
 834
 835         if (!phy)
 836                 return;
 837
 838         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
 839
 840         if (phy->link) {
 841                 mac_control = priv->data.mac_control;
 842
 843                 /* enable forwarding */
 844                 cpsw_ale_control_set(priv->ale, slave_port,
 845                                      ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
 846
 847                 if (phy->speed == 1000)
 848                         mac_control |= BIT(7);  /* GIGABITEN    */
 849                 if (phy->duplex)
 850                         mac_control |= BIT(0);  /* FULLDUPLEXEN */
 851
 852                 /* set speed_in input in case RMII mode is used in 100Mbps */
 853                 if (phy->speed == 100)
 854                         mac_control |= BIT(15);
 855                 else if (phy->speed == 10)
 856                         mac_control |= BIT(18); /* In Band mode */
 857
 858                 *link = true;
 859         } else {
 860                 mac_control = 0;
 861                 /* disable forwarding */
 862                 cpsw_ale_control_set(priv->ale, slave_port,
 863                                      ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
 864         }
 865
 866         if (mac_control != slave->mac_control) {
 867                 phy_print_status(phy);
 868                 __raw_writel(mac_control, &slave->sliver->mac_control);
 869         }
 870
 871         slave->mac_control = mac_control;
 872 }
 873
 874 static void cpsw_adjust_link(struct net_device *ndev)
 875 {
 876         struct cpsw_priv        *priv = netdev_priv(ndev);
 877         bool                    link = false;
 878
 879         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
 880
 881         if (link) {
 882                 netif_carrier_on(ndev);
 883                 if (netif_running(ndev))
 884                         netif_wake_queue(ndev);
 885         } else {
 886                 netif_carrier_off(ndev);
 887                 netif_stop_queue(ndev);
 888         }
 889 }
 890
 891 static int cpsw_get_coalesce(struct net_device *ndev,
 892                                 struct ethtool_coalesce *coal)
 893 {
 894         struct cpsw_priv *priv = netdev_priv(ndev);
 895
 896         coal->rx_coalesce_usecs = priv->coal_intvl;
 897         return 0;
 898 }
 899
 900 static int cpsw_set_coalesce(struct net_device *ndev,
 901                                 struct ethtool_coalesce *coal)
 902 {
 903         struct cpsw_priv *priv = netdev_priv(ndev);
 904         u32 int_ctrl;
 905         u32 num_interrupts = 0;
 906         u32 prescale = 0;
 907         u32 addnl_dvdr = 1;
 908         u32 coal_intvl = 0;
 909
 910         coal_intvl = coal->rx_coalesce_usecs;
 911
 912         int_ctrl =  readl(&priv->wr_regs->int_control);
 913         prescale = priv->bus_freq_mhz * 4;
 914
 915         if (!coal->rx_coalesce_usecs) {
 916                 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
 917                 goto update_return;
 918         }
 919
 920         if (coal_intvl < CPSW_CMINTMIN_INTVL)
 921                 coal_intvl = CPSW_CMINTMIN_INTVL;
 922
 923         if (coal_intvl > CPSW_CMINTMAX_INTVL) {
 924                 /* Interrupt pacer works with 4us Pulse, we can
 925                  * throttle further by dilating the 4us pulse.
 926                  */
 927                 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
 928
 929                 if (addnl_dvdr > 1) {
 930                         prescale *= addnl_dvdr;
 931                         if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
 932                                 coal_intvl = (CPSW_CMINTMAX_INTVL
 933                                                 * addnl_dvdr);
 934                 } else {
 935                         addnl_dvdr = 1;
 936                         coal_intvl = CPSW_CMINTMAX_INTVL;
 937                 }
 938         }
 939
 940         num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
 941         writel(num_interrupts, &priv->wr_regs->rx_imax);
 942         writel(num_interrupts, &priv->wr_regs->tx_imax);
 943
 944         int_ctrl |= CPSW_INTPACEEN;
 945         int_ctrl &= (~CPSW_INTPRESCALE_MASK);
 946         int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
 947
 948 update_return:
 949         writel(int_ctrl, &priv->wr_regs->int_control);
 950
 951         cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
 952         if (priv->data.dual_emac) {
 953                 int i;
 954
 955                 for (i = 0; i < priv->data.slaves; i++) {
 956                         priv = netdev_priv(priv->slaves[i].ndev);
 957                         priv->coal_intvl = coal_intvl;
 958                 }
 959         } else {
 960                 priv->coal_intvl = coal_intvl;
 961         }
 962
 963         return 0;
 964 }
 965
 966 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
 967 {
 968         switch (sset) {
 969         case ETH_SS_STATS:
 970                 return CPSW_STATS_LEN;
 971         default:
 972                 return -EOPNOTSUPP;
 973         }
 974 }
 975
 976 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
 977 {
 978         u8 *p = data;
 979         int i;
 980
 981         switch (stringset) {
 982         case ETH_SS_STATS:
 983                 for (i = 0; i < CPSW_STATS_LEN; i++) {
 984                         memcpy(p, cpsw_gstrings_stats[i].stat_string,
 985                                ETH_GSTRING_LEN);
 986                         p += ETH_GSTRING_LEN;
 987                 }
 988                 break;
 989         }
 990 }
 991
 992 static void cpsw_get_ethtool_stats(struct net_device *ndev,
 993                                     struct ethtool_stats *stats, u64 *data)
 994 {
 995         struct cpsw_priv *priv = netdev_priv(ndev);
 996         struct cpdma_chan_stats rx_stats;
 997         struct cpdma_chan_stats tx_stats;
 998         u32 val;
 999         u8 *p;
1000         int i;
1001
1002         /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1003         cpdma_chan_get_stats(priv->rxch, &rx_stats);
1004         cpdma_chan_get_stats(priv->txch, &tx_stats);
1005
1006         for (i = 0; i < CPSW_STATS_LEN; i++) {
1007                 switch (cpsw_gstrings_stats[i].type) {
1008                 case CPSW_STATS:
1009                         val = readl(priv->hw_stats +
1010                                     cpsw_gstrings_stats[i].stat_offset);
1011                         data[i] = val;
1012                         break;
1013
1014                 case CPDMA_RX_STATS:
1015                         p = (u8 *)&rx_stats +
1016                                 cpsw_gstrings_stats[i].stat_offset;
1017                         data[i] = *(u32 *)p;
1018                         break;
1019
1020                 case CPDMA_TX_STATS:
1021                         p = (u8 *)&tx_stats +
1022                                 cpsw_gstrings_stats[i].stat_offset;
1023                         data[i] = *(u32 *)p;
1024                         break;
1025                 }
1026         }
1027 }
1028
1029 static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
1030 {
1031         u32 i;
1032         u32 usage_count = 0;
1033
1034         if (!priv->data.dual_emac)
1035                 return 0;
1036
1037         for (i = 0; i < priv->data.slaves; i++)
1038                 if (priv->slaves[i].open_stat)
1039                         usage_count++;
1040
1041         return usage_count;
1042 }
1043
1044 static inline int cpsw_tx_packet_submit(struct net_device *ndev,
1045                         struct cpsw_priv *priv, struct sk_buff *skb)
1046 {
1047         if (!priv->data.dual_emac)
1048                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1049                                   skb->len, 0);
1050
1051         if (ndev == cpsw_get_slave_ndev(priv, 0))
1052                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1053                                   skb->len, 1);
1054         else
1055                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1056                                   skb->len, 2);
1057 }
1058
1059 static inline void cpsw_add_dual_emac_def_ale_entries(
1060                 struct cpsw_priv *priv, struct cpsw_slave *slave,
1061                 u32 slave_port)
1062 {
1063         u32 port_mask = 1 << slave_port | 1 << priv->host_port;
1064
1065         if (priv->version == CPSW_VERSION_1)
1066                 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1067         else
1068                 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1069         cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
1070                           port_mask, port_mask, 0);
1071         cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1072                            port_mask, ALE_VLAN, slave->port_vlan, 0);
1073         cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1074                 priv->host_port, ALE_VLAN, slave->port_vlan);
1075 }
1076
1077 static void soft_reset_slave(struct cpsw_slave *slave)
1078 {
1079         char name[32];
1080
1081         snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1082         soft_reset(name, &slave->sliver->soft_reset);
1083 }
1084
1085 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1086 {
1087         u32 slave_port;
1088
1089         soft_reset_slave(slave);
1090
1091         /* setup priority mapping */
1092         __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1093
1094         switch (priv->version) {
1095         case CPSW_VERSION_1:
1096                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1097                 break;
1098         case CPSW_VERSION_2:
1099         case CPSW_VERSION_3:
1100         case CPSW_VERSION_4:
1101                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1102                 break;
1103         }
1104
1105         /* setup max packet size, and mac address */
1106         __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
1107         cpsw_set_slave_mac(slave, priv);
1108
1109         slave->mac_control = 0; /* no link yet */
1110
1111         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1112
1113         if (priv->data.dual_emac)
1114                 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1115         else
1116                 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1117                                    1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1118
1119         slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
1120                                  &cpsw_adjust_link, slave->data->phy_if);
1121         if (IS_ERR(slave->phy)) {
1122                 dev_err(priv->dev, "phy %s not found on slave %d\n",
1123                         slave->data->phy_id, slave->slave_num);
1124                 slave->phy = NULL;
1125         } else {
1126                 dev_info(priv->dev, "phy found : id is : 0x%x\n",
1127                          slave->phy->phy_id);
1128                 phy_start(slave->phy);
1129
1130                 /* Configure GMII_SEL register */
1131                 cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface,
1132                              slave->slave_num);
1133         }
1134 }
1135
1136 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1137 {
1138         const int vlan = priv->data.default_vlan;
1139         const int port = priv->host_port;
1140         u32 reg;
1141         int i;
1142
1143         reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1144                CPSW2_PORT_VLAN;
1145
1146         writel(vlan, &priv->host_port_regs->port_vlan);
1147
1148         for (i = 0; i < priv->data.slaves; i++)
1149                 slave_write(priv->slaves + i, vlan, reg);
1150
1151         cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port,
1152                           ALE_ALL_PORTS << port, ALE_ALL_PORTS << port,
1153                           (ALE_PORT_1 | ALE_PORT_2) << port);
1154 }
1155
1156 static void cpsw_init_host_port(struct cpsw_priv *priv)
1157 {
1158         u32 control_reg;
1159         u32 fifo_mode;
1160
1161         /* soft reset the controller and initialize ale */
1162         soft_reset("cpsw", &priv->regs->soft_reset);
1163         cpsw_ale_start(priv->ale);
1164
1165         /* switch to vlan unaware mode */
1166         cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE,
1167                              CPSW_ALE_VLAN_AWARE);
1168         control_reg = readl(&priv->regs->control);
1169         control_reg |= CPSW_VLAN_AWARE;
1170         writel(control_reg, &priv->regs->control);
1171         fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1172                      CPSW_FIFO_NORMAL_MODE;
1173         writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
1174
1175         /* setup host port priority mapping */
1176         __raw_writel(CPDMA_TX_PRIORITY_MAP,
1177                      &priv->host_port_regs->cpdma_tx_pri_map);
1178         __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
1179
1180         cpsw_ale_control_set(priv->ale, priv->host_port,
1181                              ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1182
1183         if (!priv->data.dual_emac) {
1184                 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port,
1185                                    0, 0);
1186                 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1187                                    1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2);
1188         }
1189 }
1190
1191 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
1192 {
1193         u32 slave_port;
1194
1195         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1196
1197         if (!slave->phy)
1198                 return;
1199         phy_stop(slave->phy);
1200         phy_disconnect(slave->phy);
1201         slave->phy = NULL;
1202         cpsw_ale_control_set(priv->ale, slave_port,
1203                              ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1204 }
1205
1206 static int cpsw_ndo_open(struct net_device *ndev)
1207 {
1208         struct cpsw_priv *priv = netdev_priv(ndev);
1209         struct cpsw_priv *prim_cpsw;
1210         int i, ret;
1211         u32 reg;
1212
1213         if (!cpsw_common_res_usage_state(priv))
1214                 cpsw_intr_disable(priv);
1215         netif_carrier_off(ndev);
1216
1217         pm_runtime_get_sync(&priv->pdev->dev);
1218
1219         reg = priv->version;
1220
1221         dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1222                  CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1223                  CPSW_RTL_VERSION(reg));
1224
1225         /* initialize host and slave ports */
1226         if (!cpsw_common_res_usage_state(priv))
1227                 cpsw_init_host_port(priv);
1228         for_each_slave(priv, cpsw_slave_open, priv);
1229
1230         /* Add default VLAN */
1231         if (!priv->data.dual_emac)
1232                 cpsw_add_default_vlan(priv);
1233         else
1234                 cpsw_ale_add_vlan(priv->ale, priv->data.default_vlan,
1235                                   ALE_ALL_PORTS << priv->host_port,
1236                                   ALE_ALL_PORTS << priv->host_port, 0, 0);
1237
1238         if (!cpsw_common_res_usage_state(priv)) {
1239                 /* setup tx dma to fixed prio and zero offset */
1240                 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
1241                 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
1242
1243                 /* disable priority elevation */
1244                 __raw_writel(0, &priv->regs->ptype);
1245
1246                 /* enable statistics collection only on all ports */
1247                 __raw_writel(0x7, &priv->regs->stat_port_en);
1248
1249                 if (WARN_ON(!priv->data.rx_descs))
1250                         priv->data.rx_descs = 128;
1251
1252                 for (i = 0; i < priv->data.rx_descs; i++) {
1253                         struct sk_buff *skb;
1254
1255                         ret = -ENOMEM;
1256                         skb = __netdev_alloc_skb_ip_align(priv->ndev,
1257                                         priv->rx_packet_max, GFP_KERNEL);
1258                         if (!skb)
1259                                 goto err_cleanup;
1260                         ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
1261                                         skb_tailroom(skb), 0);
1262                         if (ret < 0) {
1263                                 kfree_skb(skb);
1264                                 goto err_cleanup;
1265                         }
1266                 }
1267                 /* continue even if we didn't manage to submit all
1268                  * receive descs
1269                  */
1270                 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
1271
1272                 if (cpts_register(&priv->pdev->dev, priv->cpts,
1273                                   priv->data.cpts_clock_mult,
1274                                   priv->data.cpts_clock_shift))
1275                         dev_err(priv->dev, "error registering cpts device\n");
1276
1277         }
1278
1279         /* Enable Interrupt pacing if configured */
1280         if (priv->coal_intvl != 0) {
1281                 struct ethtool_coalesce coal;
1282
1283                 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1284                 cpsw_set_coalesce(ndev, &coal);
1285         }
1286
1287         napi_enable(&priv->napi);
1288         cpdma_ctlr_start(priv->dma);
1289         cpsw_intr_enable(priv);
1290         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1291         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
1292
1293         prim_cpsw = cpsw_get_slave_priv(priv, 0);
1294         if (prim_cpsw->irq_enabled == false) {
1295                 if ((priv == prim_cpsw) || !netif_running(prim_cpsw->ndev)) {
1296                         prim_cpsw->irq_enabled = true;
1297                         cpsw_enable_irq(prim_cpsw);
1298                 }
1299         }
1300
1301         if (priv->data.dual_emac)
1302                 priv->slaves[priv->emac_port].open_stat = true;
1303         return 0;
1304
1305 err_cleanup:
1306         cpdma_ctlr_stop(priv->dma);
1307         for_each_slave(priv, cpsw_slave_stop, priv);
1308         pm_runtime_put_sync(&priv->pdev->dev);
1309         netif_carrier_off(priv->ndev);
1310         return ret;
1311 }
1312
1313 static int cpsw_ndo_stop(struct net_device *ndev)
1314 {
1315         struct cpsw_priv *priv = netdev_priv(ndev);
1316
1317         cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1318         netif_stop_queue(priv->ndev);
1319         napi_disable(&priv->napi);
1320         netif_carrier_off(priv->ndev);
1321
1322         if (cpsw_common_res_usage_state(priv) <= 1) {
1323                 cpts_unregister(priv->cpts);
1324                 cpsw_intr_disable(priv);
1325                 cpdma_ctlr_int_ctrl(priv->dma, false);
1326                 cpdma_ctlr_stop(priv->dma);
1327                 cpsw_ale_stop(priv->ale);
1328         }
1329         for_each_slave(priv, cpsw_slave_stop, priv);
1330         pm_runtime_put_sync(&priv->pdev->dev);
1331         if (priv->data.dual_emac)
1332                 priv->slaves[priv->emac_port].open_stat = false;
1333         return 0;
1334 }
1335
1336 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1337                                        struct net_device *ndev)
1338 {
1339         struct cpsw_priv *priv = netdev_priv(ndev);
1340         int ret;
1341
1342         ndev->trans_start = jiffies;
1343
1344         if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1345                 cpsw_err(priv, tx_err, "packet pad failed\n");
1346                 ndev->stats.tx_dropped++;
1347                 return NETDEV_TX_OK;
1348         }
1349
1350         if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1351                                 priv->cpts->tx_enable)
1352                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1353
1354         skb_tx_timestamp(skb);
1355
1356         ret = cpsw_tx_packet_submit(ndev, priv, skb);
1357         if (unlikely(ret != 0)) {
1358                 cpsw_err(priv, tx_err, "desc submit failed\n");
1359                 goto fail;
1360         }
1361
1362         /* If there is no more tx desc left free then we need to
1363          * tell the kernel to stop sending us tx frames.
1364          */
1365         if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
1366                 netif_stop_queue(ndev);
1367
1368         return NETDEV_TX_OK;
1369 fail:
1370         ndev->stats.tx_dropped++;
1371         netif_stop_queue(ndev);
1372         return NETDEV_TX_BUSY;
1373 }
1374
1375 #ifdef CONFIG_TI_CPTS
1376
1377 static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1378 {
1379         struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
1380         u32 ts_en, seq_id;
1381
1382         if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
1383                 slave_write(slave, 0, CPSW1_TS_CTL);
1384                 return;
1385         }
1386
1387         seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1388         ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1389
1390         if (priv->cpts->tx_enable)
1391                 ts_en |= CPSW_V1_TS_TX_EN;
1392
1393         if (priv->cpts->rx_enable)
1394                 ts_en |= CPSW_V1_TS_RX_EN;
1395
1396         slave_write(slave, ts_en, CPSW1_TS_CTL);
1397         slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1398 }
1399
1400 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1401 {
1402         struct cpsw_slave *slave;
1403         u32 ctrl, mtype;
1404
1405         if (priv->data.dual_emac)
1406                 slave = &priv->slaves[priv->emac_port];
1407         else
1408                 slave = &priv->slaves[priv->data.active_slave];
1409
1410         ctrl = slave_read(slave, CPSW2_CONTROL);
1411         switch (priv->version) {
1412         case CPSW_VERSION_2:
1413                 ctrl &= ~CTRL_V2_ALL_TS_MASK;
1414
1415                 if (priv->cpts->tx_enable)
1416                         ctrl |= CTRL_V2_TX_TS_BITS;
1417
1418                 if (priv->cpts->rx_enable)
1419                         ctrl |= CTRL_V2_RX_TS_BITS;
1420         break;
1421         case CPSW_VERSION_3:
1422         default:
1423                 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1424
1425                 if (priv->cpts->tx_enable)
1426                         ctrl |= CTRL_V3_TX_TS_BITS;
1427
1428                 if (priv->cpts->rx_enable)
1429                         ctrl |= CTRL_V3_RX_TS_BITS;
1430         break;
1431         }
1432
1433         mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1434
1435         slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1436         slave_write(slave, ctrl, CPSW2_CONTROL);
1437         __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
1438 }
1439
1440 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1441 {
1442         struct cpsw_priv *priv = netdev_priv(dev);
1443         struct cpts *cpts = priv->cpts;
1444         struct hwtstamp_config cfg;
1445
1446         if (priv->version != CPSW_VERSION_1 &&
1447             priv->version != CPSW_VERSION_2 &&
1448             priv->version != CPSW_VERSION_3)
1449                 return -EOPNOTSUPP;
1450
1451         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1452                 return -EFAULT;
1453
1454         /* reserved for future extensions */
1455         if (cfg.flags)
1456                 return -EINVAL;
1457
1458         if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
1459                 return -ERANGE;
1460
1461         switch (cfg.rx_filter) {
1462         case HWTSTAMP_FILTER_NONE:
1463                 cpts->rx_enable = 0;
1464                 break;
1465         case HWTSTAMP_FILTER_ALL:
1466         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1467         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1468         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1469                 return -ERANGE;
1470         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1471         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1472         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1473         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1474         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1475         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1476         case HWTSTAMP_FILTER_PTP_V2_EVENT:
1477         case HWTSTAMP_FILTER_PTP_V2_SYNC:
1478         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1479                 cpts->rx_enable = 1;
1480                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1481                 break;
1482         default:
1483                 return -ERANGE;
1484         }
1485
1486         cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;
1487
1488         switch (priv->version) {
1489         case CPSW_VERSION_1:
1490                 cpsw_hwtstamp_v1(priv);
1491                 break;
1492         case CPSW_VERSION_2:
1493         case CPSW_VERSION_3:
1494                 cpsw_hwtstamp_v2(priv);
1495                 break;
1496         default:
1497                 WARN_ON(1);
1498         }
1499
1500         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1501 }
1502
1503 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1504 {
1505         struct cpsw_priv *priv = netdev_priv(dev);
1506         struct cpts *cpts = priv->cpts;
1507         struct hwtstamp_config cfg;
1508
1509         if (priv->version != CPSW_VERSION_1 &&
1510             priv->version != CPSW_VERSION_2 &&
1511             priv->version != CPSW_VERSION_3)
1512                 return -EOPNOTSUPP;
1513
1514         cfg.flags = 0;
1515         cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1516         cfg.rx_filter = (cpts->rx_enable ?
1517                          HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1518
1519         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1520 }
1521
1522 #endif /*CONFIG_TI_CPTS*/
1523
1524 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1525 {
1526         struct cpsw_priv *priv = netdev_priv(dev);
1527         int slave_no = cpsw_slave_index(priv);
1528
1529         if (!netif_running(dev))
1530                 return -EINVAL;
1531
1532         switch (cmd) {
1533 #ifdef CONFIG_TI_CPTS
1534         case SIOCSHWTSTAMP:
1535                 return cpsw_hwtstamp_set(dev, req);
1536         case SIOCGHWTSTAMP:
1537                 return cpsw_hwtstamp_get(dev, req);
1538 #endif
1539         }
1540
1541         if (!priv->slaves[slave_no].phy)
1542                 return -EOPNOTSUPP;
1543         return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd);
1544 }
1545
1546 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1547 {
1548         struct cpsw_priv *priv = netdev_priv(ndev);
1549
1550         cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1551         ndev->stats.tx_errors++;
1552         cpsw_intr_disable(priv);
1553         cpdma_ctlr_int_ctrl(priv->dma, false);
1554         cpdma_chan_stop(priv->txch);
1555         cpdma_chan_start(priv->txch);
1556         cpdma_ctlr_int_ctrl(priv->dma, true);
1557         cpsw_intr_enable(priv);
1558         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1559         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
1560
1561 }
1562
1563 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1564 {
1565         struct cpsw_priv *priv = netdev_priv(ndev);
1566         struct sockaddr *addr = (struct sockaddr *)p;
1567         int flags = 0;
1568         u16 vid = 0;
1569
1570         if (!is_valid_ether_addr(addr->sa_data))
1571                 return -EADDRNOTAVAIL;
1572
1573         if (priv->data.dual_emac) {
1574                 vid = priv->slaves[priv->emac_port].port_vlan;
1575                 flags = ALE_VLAN;
1576         }
1577
1578         cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port,
1579                            flags, vid);
1580         cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port,
1581                            flags, vid);
1582
1583         memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1584         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1585         for_each_slave(priv, cpsw_set_slave_mac, priv);
1586
1587         return 0;
1588 }
1589
1590 #ifdef CONFIG_NET_POLL_CONTROLLER
1591 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1592 {
1593         struct cpsw_priv *priv = netdev_priv(ndev);
1594
1595         cpsw_intr_disable(priv);
1596         cpdma_ctlr_int_ctrl(priv->dma, false);
1597         cpsw_interrupt(ndev->irq, priv);
1598         cpdma_ctlr_int_ctrl(priv->dma, true);
1599         cpsw_intr_enable(priv);
1600         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1601         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
1602
1603 }
1604 #endif
1605
1606 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1607                                 unsigned short vid)
1608 {
1609         int ret;
1610
1611         ret = cpsw_ale_add_vlan(priv->ale, vid,
1612                                 ALE_ALL_PORTS << priv->host_port,
1613                                 0, ALE_ALL_PORTS << priv->host_port,
1614                                 (ALE_PORT_1 | ALE_PORT_2) << priv->host_port);
1615         if (ret != 0)
1616                 return ret;
1617
1618         ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1619                                  priv->host_port, ALE_VLAN, vid);
1620         if (ret != 0)
1621                 goto clean_vid;
1622
1623         ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1624                                  ALE_ALL_PORTS << priv->host_port,
1625                                  ALE_VLAN, vid, 0);
1626         if (ret != 0)
1627                 goto clean_vlan_ucast;
1628         return 0;
1629
1630 clean_vlan_ucast:
1631         cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1632                             priv->host_port, ALE_VLAN, vid);
1633 clean_vid:
1634         cpsw_ale_del_vlan(priv->ale, vid, 0);
1635         return ret;
1636 }
1637
1638 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1639                                     __be16 proto, u16 vid)
1640 {
1641         struct cpsw_priv *priv = netdev_priv(ndev);
1642
1643         if (vid == priv->data.default_vlan)
1644                 return 0;
1645
1646         dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1647         return cpsw_add_vlan_ale_entry(priv, vid);
1648 }
1649
1650 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1651                                      __be16 proto, u16 vid)
1652 {
1653         struct cpsw_priv *priv = netdev_priv(ndev);
1654         int ret;
1655
1656         if (vid == priv->data.default_vlan)
1657                 return 0;
1658
1659         dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1660         ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1661         if (ret != 0)
1662                 return ret;
1663
1664         ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1665                                  priv->host_port, ALE_VLAN, vid);
1666         if (ret != 0)
1667                 return ret;
1668
1669         return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1670                                   0, ALE_VLAN, vid);
1671 }
1672
1673 static const struct net_device_ops cpsw_netdev_ops = {
1674         .ndo_open               = cpsw_ndo_open,
1675         .ndo_stop               = cpsw_ndo_stop,
1676         .ndo_start_xmit         = cpsw_ndo_start_xmit,
1677         .ndo_set_mac_address    = cpsw_ndo_set_mac_address,
1678         .ndo_do_ioctl           = cpsw_ndo_ioctl,
1679         .ndo_validate_addr      = eth_validate_addr,
1680         .ndo_change_mtu         = eth_change_mtu,
1681         .ndo_tx_timeout         = cpsw_ndo_tx_timeout,
1682         .ndo_set_rx_mode        = cpsw_ndo_set_rx_mode,
1683 #ifdef CONFIG_NET_POLL_CONTROLLER
1684         .ndo_poll_controller    = cpsw_ndo_poll_controller,
1685 #endif
1686         .ndo_vlan_rx_add_vid    = cpsw_ndo_vlan_rx_add_vid,
1687         .ndo_vlan_rx_kill_vid   = cpsw_ndo_vlan_rx_kill_vid,
1688 };
1689
1690 static int cpsw_get_regs_len(struct net_device *ndev)
1691 {
1692         struct cpsw_priv *priv = netdev_priv(ndev);
1693
1694         return priv->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
1695 }
1696
1697 static void cpsw_get_regs(struct net_device *ndev,
1698                           struct ethtool_regs *regs, void *p)
1699 {
1700         struct cpsw_priv *priv = netdev_priv(ndev);
1701         u32 *reg = p;
1702
1703         /* update CPSW IP version */
1704         regs->version = priv->version;
1705
1706         cpsw_ale_dump(priv->ale, reg);
1707 }
1708
1709 static void cpsw_get_drvinfo(struct net_device *ndev,
1710                              struct ethtool_drvinfo *info)
1711 {
1712         struct cpsw_priv *priv = netdev_priv(ndev);
1713
1714         strlcpy(info->driver, "cpsw", sizeof(info->driver));
1715         strlcpy(info->version, "1.0", sizeof(info->version));
1716         strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
1717         info->regdump_len = cpsw_get_regs_len(ndev);
1718 }
1719
1720 static u32 cpsw_get_msglevel(struct net_device *ndev)
1721 {
1722         struct cpsw_priv *priv = netdev_priv(ndev);
1723         return priv->msg_enable;
1724 }
1725
1726 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1727 {
1728         struct cpsw_priv *priv = netdev_priv(ndev);
1729         priv->msg_enable = value;
1730 }
1731
1732 static int cpsw_get_ts_info(struct net_device *ndev,
1733                             struct ethtool_ts_info *info)
1734 {
1735 #ifdef CONFIG_TI_CPTS
1736         struct cpsw_priv *priv = netdev_priv(ndev);
1737
1738         info->so_timestamping =
1739                 SOF_TIMESTAMPING_TX_HARDWARE |
1740                 SOF_TIMESTAMPING_TX_SOFTWARE |
1741                 SOF_TIMESTAMPING_RX_HARDWARE |
1742                 SOF_TIMESTAMPING_RX_SOFTWARE |
1743                 SOF_TIMESTAMPING_SOFTWARE |
1744                 SOF_TIMESTAMPING_RAW_HARDWARE;
1745         info->phc_index = priv->cpts->phc_index;
1746         info->tx_types =
1747                 (1 << HWTSTAMP_TX_OFF) |
1748                 (1 << HWTSTAMP_TX_ON);
1749         info->rx_filters =
1750                 (1 << HWTSTAMP_FILTER_NONE) |
1751                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1752 #else
1753         info->so_timestamping =
1754                 SOF_TIMESTAMPING_TX_SOFTWARE |
1755                 SOF_TIMESTAMPING_RX_SOFTWARE |
1756                 SOF_TIMESTAMPING_SOFTWARE;
1757         info->phc_index = -1;
1758         info->tx_types = 0;
1759         info->rx_filters = 0;
1760 #endif
1761         return 0;
1762 }
1763
1764 static int cpsw_get_settings(struct net_device *ndev,
1765                              struct ethtool_cmd *ecmd)
1766 {
1767         struct cpsw_priv *priv = netdev_priv(ndev);
1768         int slave_no = cpsw_slave_index(priv);
1769
1770         if (priv->slaves[slave_no].phy)
1771                 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1772         else
1773                 return -EOPNOTSUPP;
1774 }
1775
1776 static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1777 {
1778         struct cpsw_priv *priv = netdev_priv(ndev);
1779         int slave_no = cpsw_slave_index(priv);
1780
1781         if (priv->slaves[slave_no].phy)
1782                 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1783         else
1784                 return -EOPNOTSUPP;
1785 }
1786
1787 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1788 {
1789         struct cpsw_priv *priv = netdev_priv(ndev);
1790         int slave_no = cpsw_slave_index(priv);
1791
1792         wol->supported = 0;
1793         wol->wolopts = 0;
1794
1795         if (priv->slaves[slave_no].phy)
1796                 phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol);
1797 }
1798
1799 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1800 {
1801         struct cpsw_priv *priv = netdev_priv(ndev);
1802         int slave_no = cpsw_slave_index(priv);
1803
1804         if (priv->slaves[slave_no].phy)
1805                 return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol);
1806         else
1807                 return -EOPNOTSUPP;
1808 }
1809
1810 static const struct ethtool_ops cpsw_ethtool_ops = {
1811         .get_drvinfo    = cpsw_get_drvinfo,
1812         .get_msglevel   = cpsw_get_msglevel,
1813         .set_msglevel   = cpsw_set_msglevel,
1814         .get_link       = ethtool_op_get_link,
1815         .get_ts_info    = cpsw_get_ts_info,
1816         .get_settings   = cpsw_get_settings,
1817         .set_settings   = cpsw_set_settings,
1818         .get_coalesce   = cpsw_get_coalesce,
1819         .set_coalesce   = cpsw_set_coalesce,
1820         .get_sset_count         = cpsw_get_sset_count,
1821         .get_strings            = cpsw_get_strings,
1822         .get_ethtool_stats      = cpsw_get_ethtool_stats,
1823         .get_wol        = cpsw_get_wol,
1824         .set_wol        = cpsw_set_wol,
1825         .get_regs_len   = cpsw_get_regs_len,
1826         .get_regs       = cpsw_get_regs,
1827 };
1828
1829 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1830                             u32 slave_reg_ofs, u32 sliver_reg_ofs)
1831 {
1832         void __iomem            *regs = priv->regs;
1833         int                     slave_num = slave->slave_num;
1834         struct cpsw_slave_data  *data = priv->data.slave_data + slave_num;
1835
1836         slave->data     = data;
1837         slave->regs     = regs + slave_reg_ofs;
1838         slave->sliver   = regs + sliver_reg_ofs;
1839         slave->port_vlan = data->dual_emac_res_vlan;
1840 }
1841
1842 static int cpsw_probe_dt(struct cpsw_platform_data *data,
1843                          struct platform_device *pdev)
1844 {
1845         struct device_node *node = pdev->dev.of_node;
1846         struct device_node *slave_node;
1847         int i = 0, ret;
1848         u32 prop;
1849
1850         if (!node)
1851                 return -EINVAL;
1852
1853         if (of_property_read_u32(node, "slaves", &prop)) {
1854                 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
1855                 return -EINVAL;
1856         }
1857         data->slaves = prop;
1858
1859         if (of_property_read_u32(node, "active_slave", &prop)) {
1860                 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
1861                 return -EINVAL;
1862         }
1863         data->active_slave = prop;
1864
1865         if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
1866                 dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n");
1867                 return -EINVAL;
1868         }
1869         data->cpts_clock_mult = prop;
1870
1871         if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
1872                 dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n");
1873                 return -EINVAL;
1874         }
1875         data->cpts_clock_shift = prop;
1876
1877         data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
1878                                         * sizeof(struct cpsw_slave_data),
1879                                         GFP_KERNEL);
1880         if (!data->slave_data)
1881                 return -ENOMEM;
1882
1883         if (of_property_read_u32(node, "cpdma_channels", &prop)) {
1884                 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
1885                 return -EINVAL;
1886         }
1887         data->channels = prop;
1888
1889         if (of_property_read_u32(node, "ale_entries", &prop)) {
1890                 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
1891                 return -EINVAL;
1892         }
1893         data->ale_entries = prop;
1894
1895         if (of_property_read_u32(node, "bd_ram_size", &prop)) {
1896                 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
1897                 return -EINVAL;
1898         }
1899         data->bd_ram_size = prop;
1900
1901         if (of_property_read_u32(node, "rx_descs", &prop)) {
1902                 dev_err(&pdev->dev, "Missing rx_descs property in the DT.\n");
1903                 return -EINVAL;
1904         }
1905         data->rx_descs = prop;
1906
1907         if (of_property_read_u32(node, "mac_control", &prop)) {
1908                 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
1909                 return -EINVAL;
1910         }
1911         data->mac_control = prop;
1912
1913         if (of_property_read_bool(node, "dual_emac"))
1914                 data->dual_emac = 1;
1915
1916         /*
1917          * Populate all the child nodes here...
1918          */
1919         ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
1920         /* We do not want to force this, as in some cases may not have child */
1921         if (ret)
1922                 dev_warn(&pdev->dev, "Doesn't have any child node\n");
1923
1924         for_each_child_of_node(node, slave_node) {
1925                 struct cpsw_slave_data *slave_data = data->slave_data + i;
1926                 const void *mac_addr = NULL;
1927                 u32 phyid;
1928                 int lenp;
1929                 const __be32 *parp;
1930                 struct device_node *mdio_node;
1931                 struct platform_device *mdio;
1932
1933                 /* This is no slave child node, continue */
1934                 if (strcmp(slave_node->name, "slave"))
1935                         continue;
1936
1937                 parp = of_get_property(slave_node, "phy_id", &lenp);
1938                 if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) {
1939                         dev_err(&pdev->dev, "Missing slave[%d] phy_id property\n", i);
1940                         return -EINVAL;
1941                 }
1942                 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
1943                 phyid = be32_to_cpup(parp+1);
1944                 mdio = of_find_device_by_node(mdio_node);
1945                 of_node_put(mdio_node);
1946                 if (!mdio) {
1947                         pr_err("Missing mdio platform device\n");
1948                         return -EINVAL;
1949                 }
1950                 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
1951                          PHY_ID_FMT, mdio->name, phyid);
1952
1953                 mac_addr = of_get_mac_address(slave_node);
1954                 if (mac_addr)
1955                         memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
1956
1957                 slave_data->phy_if = of_get_phy_mode(slave_node);
1958                 if (slave_data->phy_if < 0) {
1959                         dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
1960                                 i);
1961                         return slave_data->phy_if;
1962                 }
1963
1964                 if (data->dual_emac) {
1965                         if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
1966                                                  &prop)) {
1967                                 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
1968                                 slave_data->dual_emac_res_vlan = i+1;
1969                                 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
1970                                         slave_data->dual_emac_res_vlan, i);
1971                         } else {
1972                                 slave_data->dual_emac_res_vlan = prop;
1973                         }
1974                 }
1975
1976                 i++;
1977                 if (i == data->slaves)
1978                         break;
1979         }
1980
1981         return 0;
1982 }
1983
1984 static int cpsw_probe_dual_emac(struct platform_device *pdev,
1985                                 struct cpsw_priv *priv)
1986 {
1987         struct cpsw_platform_data       *data = &priv->data;
1988         struct net_device               *ndev;
1989         struct cpsw_priv                *priv_sl2;
1990         int ret = 0, i;
1991
1992         ndev = alloc_etherdev(sizeof(struct cpsw_priv));
1993         if (!ndev) {
1994                 dev_err(&pdev->dev, "cpsw: error allocating net_device\n");
1995                 return -ENOMEM;
1996         }
1997
1998         priv_sl2 = netdev_priv(ndev);
1999         spin_lock_init(&priv_sl2->lock);
2000         priv_sl2->data = *data;
2001         priv_sl2->pdev = pdev;
2002         priv_sl2->ndev = ndev;
2003         priv_sl2->dev  = &ndev->dev;
2004         priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2005         priv_sl2->rx_packet_max = max(rx_packet_max, 128);
2006
2007         if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2008                 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2009                         ETH_ALEN);
2010                 dev_info(&pdev->dev, "cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
2011         } else {
2012                 random_ether_addr(priv_sl2->mac_addr);
2013                 dev_info(&pdev->dev, "cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
2014         }
2015         memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2016
2017         priv_sl2->slaves = priv->slaves;
2018         priv_sl2->clk = priv->clk;
2019
2020         priv_sl2->coal_intvl = 0;
2021         priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
2022
2023         priv_sl2->regs = priv->regs;
2024         priv_sl2->host_port = priv->host_port;
2025         priv_sl2->host_port_regs = priv->host_port_regs;
2026         priv_sl2->wr_regs = priv->wr_regs;
2027         priv_sl2->hw_stats = priv->hw_stats;
2028         priv_sl2->dma = priv->dma;
2029         priv_sl2->txch = priv->txch;
2030         priv_sl2->rxch = priv->rxch;
2031         priv_sl2->ale = priv->ale;
2032         priv_sl2->emac_port = 1;
2033         priv->slaves[1].ndev = ndev;
2034         priv_sl2->cpts = priv->cpts;
2035         priv_sl2->version = priv->version;
2036
2037         for (i = 0; i < priv->num_irqs; i++) {
2038                 priv_sl2->irqs_table[i] = priv->irqs_table[i];
2039                 priv_sl2->num_irqs = priv->num_irqs;
2040         }
2041         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2042
2043         ndev->netdev_ops = &cpsw_netdev_ops;
2044         ndev->ethtool_ops = &cpsw_ethtool_ops;
2045         netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT);
2046
2047         /* register the network device */
2048         SET_NETDEV_DEV(ndev, &pdev->dev);
2049         ret = register_netdev(ndev);
2050         if (ret) {
2051                 dev_err(&pdev->dev, "cpsw: error registering net device\n");
2052                 free_netdev(ndev);
2053                 ret = -ENODEV;
2054         }
2055
2056         return ret;
2057 }
2058
2059 static int cpsw_probe(struct platform_device *pdev)
2060 {
2061         struct cpsw_platform_data       *data;
2062         struct net_device               *ndev;
2063         struct cpsw_priv                *priv;
2064         struct cpdma_params             dma_params;
2065         struct cpsw_ale_params          ale_params;
2066         void __iomem                    *ss_regs;
2067         struct resource                 *res, *ss_res;
2068         u32 slave_offset, sliver_offset, slave_size;
2069         int ret = 0, i, k = 0;
2070
2071         ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2072         if (!ndev) {
2073                 dev_err(&pdev->dev, "error allocating net_device\n");
2074                 return -ENOMEM;
2075         }
2076
2077         platform_set_drvdata(pdev, ndev);
2078         priv = netdev_priv(ndev);
2079         spin_lock_init(&priv->lock);
2080         priv->pdev = pdev;
2081         priv->ndev = ndev;
2082         priv->dev  = &ndev->dev;
2083         priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2084         priv->rx_packet_max = max(rx_packet_max, 128);
2085         priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
2086         priv->irq_enabled = true;
2087         if (!priv->cpts) {
2088                 dev_err(&pdev->dev, "error allocating cpts\n");
2089                 goto clean_ndev_ret;
2090         }
2091
2092         /*
2093          * This may be required here for child devices.
2094          */
2095         pm_runtime_enable(&pdev->dev);
2096
2097         /* Select default pin state */
2098         pinctrl_pm_select_default_state(&pdev->dev);
2099
2100         if (cpsw_probe_dt(&priv->data, pdev)) {
2101                 dev_err(&pdev->dev, "cpsw: platform data missing\n");
2102                 ret = -ENODEV;
2103                 goto clean_runtime_disable_ret;
2104         }
2105         data = &priv->data;
2106
2107         if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2108                 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
2109                 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
2110         } else {
2111                 eth_random_addr(priv->mac_addr);
2112                 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
2113         }
2114
2115         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2116
2117         priv->slaves = devm_kzalloc(&pdev->dev,
2118                                     sizeof(struct cpsw_slave) * data->slaves,
2119                                     GFP_KERNEL);
2120         if (!priv->slaves) {
2121                 ret = -ENOMEM;
2122                 goto clean_runtime_disable_ret;
2123         }
2124         for (i = 0; i < data->slaves; i++)
2125                 priv->slaves[i].slave_num = i;
2126
2127         priv->slaves[0].ndev = ndev;
2128         priv->emac_port = 0;
2129
2130         priv->clk = devm_clk_get(&pdev->dev, "fck");
2131         if (IS_ERR(priv->clk)) {
2132                 dev_err(priv->dev, "fck is not found\n");
2133                 ret = -ENODEV;
2134                 goto clean_runtime_disable_ret;
2135         }
2136         priv->coal_intvl = 0;
2137         priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
2138
2139         ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2140         ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2141         if (IS_ERR(ss_regs)) {
2142                 ret = PTR_ERR(ss_regs);
2143                 goto clean_runtime_disable_ret;
2144         }
2145         priv->regs = ss_regs;
2146         priv->host_port = HOST_PORT_NUM;
2147
2148         /* Need to enable clocks with runtime PM api to access module
2149          * registers
2150          */
2151         pm_runtime_get_sync(&pdev->dev);
2152         priv->version = readl(&priv->regs->id_ver);
2153         pm_runtime_put_sync(&pdev->dev);
2154
2155         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2156         priv->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2157         if (IS_ERR(priv->wr_regs)) {
2158                 ret = PTR_ERR(priv->wr_regs);
2159                 goto clean_runtime_disable_ret;
2160         }
2161
2162         memset(&dma_params, 0, sizeof(dma_params));
2163         memset(&ale_params, 0, sizeof(ale_params));
2164
2165         switch (priv->version) {
2166         case CPSW_VERSION_1:
2167                 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
2168                 priv->cpts->reg      = ss_regs + CPSW1_CPTS_OFFSET;
2169                 priv->hw_stats       = ss_regs + CPSW1_HW_STATS;
2170                 dma_params.dmaregs   = ss_regs + CPSW1_CPDMA_OFFSET;
2171                 dma_params.txhdp     = ss_regs + CPSW1_STATERAM_OFFSET;
2172                 ale_params.ale_regs  = ss_regs + CPSW1_ALE_OFFSET;
2173                 slave_offset         = CPSW1_SLAVE_OFFSET;
2174                 slave_size           = CPSW1_SLAVE_SIZE;
2175                 sliver_offset        = CPSW1_SLIVER_OFFSET;
2176                 dma_params.desc_mem_phys = 0;
2177                 break;
2178         case CPSW_VERSION_2:
2179         case CPSW_VERSION_3:
2180         case CPSW_VERSION_4:
2181                 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
2182                 priv->cpts->reg      = ss_regs + CPSW2_CPTS_OFFSET;
2183                 priv->hw_stats       = ss_regs + CPSW2_HW_STATS;
2184                 dma_params.dmaregs   = ss_regs + CPSW2_CPDMA_OFFSET;
2185                 dma_params.txhdp     = ss_regs + CPSW2_STATERAM_OFFSET;
2186                 ale_params.ale_regs  = ss_regs + CPSW2_ALE_OFFSET;
2187                 slave_offset         = CPSW2_SLAVE_OFFSET;
2188                 slave_size           = CPSW2_SLAVE_SIZE;
2189                 sliver_offset        = CPSW2_SLIVER_OFFSET;
2190                 dma_params.desc_mem_phys =
2191                         (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
2192                 break;
2193         default:
2194                 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
2195                 ret = -ENODEV;
2196                 goto clean_runtime_disable_ret;
2197         }
2198         for (i = 0; i < priv->data.slaves; i++) {
2199                 struct cpsw_slave *slave = &priv->slaves[i];
2200                 cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
2201                 slave_offset  += slave_size;
2202                 sliver_offset += SLIVER_SIZE;
2203         }
2204
2205         dma_params.dev          = &pdev->dev;
2206         dma_params.rxthresh     = dma_params.dmaregs + CPDMA_RXTHRESH;
2207         dma_params.rxfree       = dma_params.dmaregs + CPDMA_RXFREE;
2208         dma_params.rxhdp        = dma_params.txhdp + CPDMA_RXHDP;
2209         dma_params.txcp         = dma_params.txhdp + CPDMA_TXCP;
2210         dma_params.rxcp         = dma_params.txhdp + CPDMA_RXCP;
2211
2212         dma_params.num_chan             = data->channels;
2213         dma_params.has_soft_reset       = true;
2214         dma_params.min_packet_size      = CPSW_MIN_PACKET_SIZE;
2215         dma_params.desc_mem_size        = data->bd_ram_size;
2216         dma_params.desc_align           = 16;
2217         dma_params.has_ext_regs         = true;
2218         dma_params.desc_hw_addr         = dma_params.desc_mem_phys;
2219
2220         priv->dma = cpdma_ctlr_create(&dma_params);
2221         if (!priv->dma) {
2222                 dev_err(priv->dev, "error initializing dma\n");
2223                 ret = -ENOMEM;
2224                 goto clean_runtime_disable_ret;
2225         }
2226
2227         priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
2228                                        cpsw_tx_handler);
2229         priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
2230                                        cpsw_rx_handler);
2231
2232         if (WARN_ON(!priv->txch || !priv->rxch)) {
2233                 dev_err(priv->dev, "error initializing dma channels\n");
2234                 ret = -ENOMEM;
2235                 goto clean_dma_ret;
2236         }
2237
2238         ale_params.dev                  = &ndev->dev;
2239         ale_params.ale_ageout           = ale_ageout;
2240         ale_params.ale_entries          = data->ale_entries;
2241         ale_params.ale_ports            = data->slaves;
2242
2243         priv->ale = cpsw_ale_create(&ale_params);
2244         if (!priv->ale) {
2245                 dev_err(priv->dev, "error initializing ale engine\n");
2246                 ret = -ENODEV;
2247                 goto clean_dma_ret;
2248         }
2249
2250         ndev->irq = platform_get_irq(pdev, 0);
2251         if (ndev->irq < 0) {
2252                 dev_err(priv->dev, "error getting irq resource\n");
2253                 ret = -ENOENT;
2254                 goto clean_ale_ret;
2255         }
2256
2257         while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
2258                 for (i = res->start; i <= res->end; i++) {
2259                         if (devm_request_irq(&pdev->dev, i, cpsw_interrupt, 0,
2260                                              dev_name(&pdev->dev), priv)) {
2261                                 dev_err(priv->dev, "error attaching irq\n");
2262                                 goto clean_ale_ret;
2263                         }
2264                         priv->irqs_table[k] = i;
2265                         priv->num_irqs = k + 1;
2266                 }
2267                 k++;
2268         }
2269
2270         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2271
2272         ndev->netdev_ops = &cpsw_netdev_ops;
2273         ndev->ethtool_ops = &cpsw_ethtool_ops;
2274         netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT);
2275
2276         /* register the network device */
2277         SET_NETDEV_DEV(ndev, &pdev->dev);
2278         ret = register_netdev(ndev);
2279         if (ret) {
2280                 dev_err(priv->dev, "error registering net device\n");
2281                 ret = -ENODEV;
2282                 goto clean_ale_ret;
2283         }
2284
2285         cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
2286                     &ss_res->start, ndev->irq);
2287
2288         if (priv->data.dual_emac) {
2289                 ret = cpsw_probe_dual_emac(pdev, priv);
2290                 if (ret) {
2291                         cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
2292                         goto clean_ale_ret;
2293                 }
2294         }
2295
2296         return 0;
2297
2298 clean_ale_ret:
2299         cpsw_ale_destroy(priv->ale);
2300 clean_dma_ret:
2301         cpdma_chan_destroy(priv->txch);
2302         cpdma_chan_destroy(priv->rxch);
2303         cpdma_ctlr_destroy(priv->dma);
2304 clean_runtime_disable_ret:
2305         pm_runtime_disable(&pdev->dev);
2306 clean_ndev_ret:
2307         free_netdev(priv->ndev);
2308         return ret;
2309 }
2310
2311 static int cpsw_remove(struct platform_device *pdev)
2312 {
2313         struct net_device *ndev = platform_get_drvdata(pdev);
2314         struct cpsw_priv *priv = netdev_priv(ndev);
2315
2316         if (priv->data.dual_emac)
2317                 unregister_netdev(cpsw_get_slave_ndev(priv, 1));
2318         unregister_netdev(ndev);
2319
2320         cpsw_ale_destroy(priv->ale);
2321         cpdma_chan_destroy(priv->txch);
2322         cpdma_chan_destroy(priv->rxch);
2323         cpdma_ctlr_destroy(priv->dma);
2324         pm_runtime_disable(&pdev->dev);
2325         if (priv->data.dual_emac)
2326                 free_netdev(cpsw_get_slave_ndev(priv, 1));
2327         free_netdev(ndev);
2328         return 0;
2329 }
2330
2331 static int cpsw_suspend(struct device *dev)
2332 {
2333         struct platform_device  *pdev = to_platform_device(dev);
2334         struct net_device       *ndev = platform_get_drvdata(pdev);
2335         struct cpsw_priv        *priv = netdev_priv(ndev);
2336
2337         if (priv->data.dual_emac) {
2338                 int i;
2339
2340                 for (i = 0; i < priv->data.slaves; i++) {
2341                         if (netif_running(priv->slaves[i].ndev))
2342                                 cpsw_ndo_stop(priv->slaves[i].ndev);
2343                         soft_reset_slave(priv->slaves + i);
2344                 }
2345         } else {
2346                 if (netif_running(ndev))
2347                         cpsw_ndo_stop(ndev);
2348                 for_each_slave(priv, soft_reset_slave);
2349         }
2350
2351         pm_runtime_put_sync(&pdev->dev);
2352
2353         /* Select sleep pin state */
2354         pinctrl_pm_select_sleep_state(&pdev->dev);
2355
2356         return 0;
2357 }
2358
2359 static int cpsw_resume(struct device *dev)
2360 {
2361         struct platform_device  *pdev = to_platform_device(dev);
2362         struct net_device       *ndev = platform_get_drvdata(pdev);
2363         struct cpsw_priv        *priv = netdev_priv(ndev);
2364
2365         pm_runtime_get_sync(&pdev->dev);
2366
2367         /* Select default pin state */
2368         pinctrl_pm_select_default_state(&pdev->dev);
2369
2370         if (priv->data.dual_emac) {
2371                 int i;
2372
2373                 for (i = 0; i < priv->data.slaves; i++) {
2374                         if (netif_running(priv->slaves[i].ndev))
2375                                 cpsw_ndo_open(priv->slaves[i].ndev);
2376                 }
2377         } else {
2378                 if (netif_running(ndev))
2379                         cpsw_ndo_open(ndev);
2380         }
2381         return 0;
2382 }
2383
2384 static const struct dev_pm_ops cpsw_pm_ops = {
2385         .suspend        = cpsw_suspend,
2386         .resume         = cpsw_resume,
2387 };
2388
2389 static const struct of_device_id cpsw_of_mtable[] = {
2390         { .compatible = "ti,cpsw", },
2391         { /* sentinel */ },
2392 };
2393 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2394
2395 static struct platform_driver cpsw_driver = {
2396         .driver = {
2397                 .name    = "cpsw",
2398                 .owner   = THIS_MODULE,
2399                 .pm      = &cpsw_pm_ops,
2400                 .of_match_table = cpsw_of_mtable,
2401         },
2402         .probe = cpsw_probe,
2403         .remove = cpsw_remove,
2404 };
2405
2406 static int __init cpsw_init(void)
2407 {
2408         return platform_driver_register(&cpsw_driver);
2409 }
2410 late_initcall(cpsw_init);
2411
2412 static void __exit cpsw_exit(void)
2413 {
2414         platform_driver_unregister(&cpsw_driver);
2415 }
2416 module_exit(cpsw_exit);
2417
2418 MODULE_LICENSE("GPL");
2419 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2420 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2421 MODULE_DESCRIPTION("TI CPSW Ethernet driver");