drivers/net/ethernet/ti/cpsw.c

   1 /*
   2  * Texas Instruments Ethernet Switch Driver
   3  *
   4  * Copyright (C) 2012 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/io.h>
  18 #include <linux/clk.h>
  19 #include <linux/timer.h>
  20 #include <linux/module.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/irqreturn.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/if_ether.h>
  25 #include <linux/etherdevice.h>
  26 #include <linux/netdevice.h>
  27 #include <linux/net_tstamp.h>
  28 #include <linux/phy.h>
  29 #include <linux/workqueue.h>
  30 #include <linux/delay.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/gpio.h>
  33 #include <linux/of.h>
  34 #include <linux/of_mdio.h>
  35 #include <linux/of_net.h>
  36 #include <linux/of_device.h>
  37 #include <linux/if_vlan.h>
  38
  39 #include <linux/pinctrl/consumer.h>
  40
  41 #include "cpsw.h"
  42 #include "cpsw_ale.h"
  43 #include "cpts.h"
  44 #include "davinci_cpdma.h"
  45
  46 #define CPSW_DEBUG      (NETIF_MSG_HW           | NETIF_MSG_WOL         | \
  47                          NETIF_MSG_DRV          | NETIF_MSG_LINK        | \
  48                          NETIF_MSG_IFUP         | NETIF_MSG_INTR        | \
  49                          NETIF_MSG_PROBE        | NETIF_MSG_TIMER       | \
  50                          NETIF_MSG_IFDOWN       | NETIF_MSG_RX_ERR      | \
  51                          NETIF_MSG_TX_ERR       | NETIF_MSG_TX_DONE     | \
  52                          NETIF_MSG_PKTDATA      | NETIF_MSG_TX_QUEUED   | \
  53                          NETIF_MSG_RX_STATUS)
  54
  55 #define cpsw_info(priv, type, format, ...)              \
  56 do {                                                            \
  57         if (netif_msg_##type(priv) && net_ratelimit())          \
  58                 dev_info(priv->dev, format, ## __VA_ARGS__);    \
  59 } while (0)
  60
  61 #define cpsw_err(priv, type, format, ...)               \
  62 do {                                                            \
  63         if (netif_msg_##type(priv) && net_ratelimit())          \
  64                 dev_err(priv->dev, format, ## __VA_ARGS__);     \
  65 } while (0)
  66
  67 #define cpsw_dbg(priv, type, format, ...)               \
  68 do {                                                            \
  69         if (netif_msg_##type(priv) && net_ratelimit())          \
  70                 dev_dbg(priv->dev, format, ## __VA_ARGS__);     \
  71 } while (0)
  72
  73 #define cpsw_notice(priv, type, format, ...)            \
  74 do {                                                            \
  75         if (netif_msg_##type(priv) && net_ratelimit())          \
  76                 dev_notice(priv->dev, format, ## __VA_ARGS__);  \
  77 } while (0)
  78
  79 #define ALE_ALL_PORTS           0x7
  80
  81 #define CPSW_MAJOR_VERSION(reg)         (reg >> 8 & 0x7)
  82 #define CPSW_MINOR_VERSION(reg)         (reg & 0xff)
  83 #define CPSW_RTL_VERSION(reg)           ((reg >> 11) & 0x1f)
  84
  85 #define CPSW_VERSION_1          0x19010a
  86 #define CPSW_VERSION_2          0x19010c
  87 #define CPSW_VERSION_3          0x19010f
  88 #define CPSW_VERSION_4          0x190112
  89
  90 #define HOST_PORT_NUM           0
  91 #define CPSW_ALE_PORTS_NUM      3
  92 #define SLIVER_SIZE             0x40
  93
  94 #define CPSW1_HOST_PORT_OFFSET  0x028
  95 #define CPSW1_SLAVE_OFFSET      0x050
  96 #define CPSW1_SLAVE_SIZE        0x040
  97 #define CPSW1_CPDMA_OFFSET      0x100
  98 #define CPSW1_STATERAM_OFFSET   0x200
  99 #define CPSW1_HW_STATS          0x400
 100 #define CPSW1_CPTS_OFFSET       0x500
 101 #define CPSW1_ALE_OFFSET        0x600
 102 #define CPSW1_SLIVER_OFFSET     0x700
 103
 104 #define CPSW2_HOST_PORT_OFFSET  0x108
 105 #define CPSW2_SLAVE_OFFSET      0x200
 106 #define CPSW2_SLAVE_SIZE        0x100
 107 #define CPSW2_CPDMA_OFFSET      0x800
 108 #define CPSW2_HW_STATS          0x900
 109 #define CPSW2_STATERAM_OFFSET   0xa00
 110 #define CPSW2_CPTS_OFFSET       0xc00
 111 #define CPSW2_ALE_OFFSET        0xd00
 112 #define CPSW2_SLIVER_OFFSET     0xd80
 113 #define CPSW2_BD_OFFSET         0x2000
 114
 115 #define CPDMA_RXTHRESH          0x0c0
 116 #define CPDMA_RXFREE            0x0e0
 117 #define CPDMA_TXHDP             0x00
 118 #define CPDMA_RXHDP             0x20
 119 #define CPDMA_TXCP              0x40
 120 #define CPDMA_RXCP              0x60
 121
 122 #define CPSW_POLL_WEIGHT        64
 123 #define CPSW_MIN_PACKET_SIZE    (VLAN_ETH_ZLEN)
 124 #define CPSW_MAX_PACKET_SIZE    (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
 125
 126 #define RX_PRIORITY_MAPPING     0x76543210
 127 #define TX_PRIORITY_MAPPING     0x33221100
 128 #define CPDMA_TX_PRIORITY_MAP   0x01234567
 129
 130 #define CPSW_VLAN_AWARE         BIT(1)
 131 #define CPSW_ALE_VLAN_AWARE     1
 132
 133 #define CPSW_FIFO_NORMAL_MODE           (0 << 16)
 134 #define CPSW_FIFO_DUAL_MAC_MODE         (1 << 16)
 135 #define CPSW_FIFO_RATE_LIMIT_MODE       (2 << 16)
 136
 137 #define CPSW_INTPACEEN          (0x3f << 16)
 138 #define CPSW_INTPRESCALE_MASK   (0x7FF << 0)
 139 #define CPSW_CMINTMAX_CNT       63
 140 #define CPSW_CMINTMIN_CNT       2
 141 #define CPSW_CMINTMAX_INTVL     (1000 / CPSW_CMINTMIN_CNT)
 142 #define CPSW_CMINTMIN_INTVL     ((1000 / CPSW_CMINTMAX_CNT) + 1)
 143
 144 #define cpsw_slave_index(cpsw, priv)                            \
 145                 ((cpsw->data.dual_emac) ? priv->emac_port :     \
 146                 cpsw->data.active_slave)
 147 #define IRQ_NUM                 2
 148 #define CPSW_MAX_QUEUES         8
 149 #define CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT 256
 150
 151 static int debug_level;
 152 module_param(debug_level, int, 0);
 153 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
 154
 155 static int ale_ageout = 10;
 156 module_param(ale_ageout, int, 0);
 157 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
 158
 159 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
 160 module_param(rx_packet_max, int, 0);
 161 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
 162
 163 static int descs_pool_size = CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT;
 164 module_param(descs_pool_size, int, 0444);
 165 MODULE_PARM_DESC(descs_pool_size, "Number of CPDMA CPPI descriptors in pool");
 166
 167 struct cpsw_wr_regs {
 168         u32     id_ver;
 169         u32     soft_reset;
 170         u32     control;
 171         u32     int_control;
 172         u32     rx_thresh_en;
 173         u32     rx_en;
 174         u32     tx_en;
 175         u32     misc_en;
 176         u32     mem_allign1[8];
 177         u32     rx_thresh_stat;
 178         u32     rx_stat;
 179         u32     tx_stat;
 180         u32     misc_stat;
 181         u32     mem_allign2[8];
 182         u32     rx_imax;
 183         u32     tx_imax;
 184
 185 };
 186
 187 struct cpsw_ss_regs {
 188         u32     id_ver;
 189         u32     control;
 190         u32     soft_reset;
 191         u32     stat_port_en;
 192         u32     ptype;
 193         u32     soft_idle;
 194         u32     thru_rate;
 195         u32     gap_thresh;
 196         u32     tx_start_wds;
 197         u32     flow_control;
 198         u32     vlan_ltype;
 199         u32     ts_ltype;
 200         u32     dlr_ltype;
 201 };
 202
 203 /* CPSW_PORT_V1 */
 204 #define CPSW1_MAX_BLKS      0x00 /* Maximum FIFO Blocks */
 205 #define CPSW1_BLK_CNT       0x04 /* FIFO Block Usage Count (Read Only) */
 206 #define CPSW1_TX_IN_CTL     0x08 /* Transmit FIFO Control */
 207 #define CPSW1_PORT_VLAN     0x0c /* VLAN Register */
 208 #define CPSW1_TX_PRI_MAP    0x10 /* Tx Header Priority to Switch Pri Mapping */
 209 #define CPSW1_TS_CTL        0x14 /* Time Sync Control */
 210 #define CPSW1_TS_SEQ_LTYPE  0x18 /* Time Sync Sequence ID Offset and Msg Type */
 211 #define CPSW1_TS_VLAN       0x1c /* Time Sync VLAN1 and VLAN2 */
 212
 213 /* CPSW_PORT_V2 */
 214 #define CPSW2_CONTROL       0x00 /* Control Register */
 215 #define CPSW2_MAX_BLKS      0x08 /* Maximum FIFO Blocks */
 216 #define CPSW2_BLK_CNT       0x0c /* FIFO Block Usage Count (Read Only) */
 217 #define CPSW2_TX_IN_CTL     0x10 /* Transmit FIFO Control */
 218 #define CPSW2_PORT_VLAN     0x14 /* VLAN Register */
 219 #define CPSW2_TX_PRI_MAP    0x18 /* Tx Header Priority to Switch Pri Mapping */
 220 #define CPSW2_TS_SEQ_MTYPE  0x1c /* Time Sync Sequence ID Offset and Msg Type */
 221
 222 /* CPSW_PORT_V1 and V2 */
 223 #define SA_LO               0x20 /* CPGMAC_SL Source Address Low */
 224 #define SA_HI               0x24 /* CPGMAC_SL Source Address High */
 225 #define SEND_PERCENT        0x28 /* Transmit Queue Send Percentages */
 226
 227 /* CPSW_PORT_V2 only */
 228 #define RX_DSCP_PRI_MAP0    0x30 /* Rx DSCP Priority to Rx Packet Mapping */
 229 #define RX_DSCP_PRI_MAP1    0x34 /* Rx DSCP Priority to Rx Packet Mapping */
 230 #define RX_DSCP_PRI_MAP2    0x38 /* Rx DSCP Priority to Rx Packet Mapping */
 231 #define RX_DSCP_PRI_MAP3    0x3c /* Rx DSCP Priority to Rx Packet Mapping */
 232 #define RX_DSCP_PRI_MAP4    0x40 /* Rx DSCP Priority to Rx Packet Mapping */
 233 #define RX_DSCP_PRI_MAP5    0x44 /* Rx DSCP Priority to Rx Packet Mapping */
 234 #define RX_DSCP_PRI_MAP6    0x48 /* Rx DSCP Priority to Rx Packet Mapping */
 235 #define RX_DSCP_PRI_MAP7    0x4c /* Rx DSCP Priority to Rx Packet Mapping */
 236
 237 /* Bit definitions for the CPSW2_CONTROL register */
 238 #define PASS_PRI_TAGGED     (1<<24) /* Pass Priority Tagged */
 239 #define VLAN_LTYPE2_EN      (1<<21) /* VLAN LTYPE 2 enable */
 240 #define VLAN_LTYPE1_EN      (1<<20) /* VLAN LTYPE 1 enable */
 241 #define DSCP_PRI_EN         (1<<16) /* DSCP Priority Enable */
 242 #define TS_320              (1<<14) /* Time Sync Dest Port 320 enable */
 243 #define TS_319              (1<<13) /* Time Sync Dest Port 319 enable */
 244 #define TS_132              (1<<12) /* Time Sync Dest IP Addr 132 enable */
 245 #define TS_131              (1<<11) /* Time Sync Dest IP Addr 131 enable */
 246 #define TS_130              (1<<10) /* Time Sync Dest IP Addr 130 enable */
 247 #define TS_129              (1<<9)  /* Time Sync Dest IP Addr 129 enable */
 248 #define TS_TTL_NONZERO      (1<<8)  /* Time Sync Time To Live Non-zero enable */
 249 #define TS_ANNEX_F_EN       (1<<6)  /* Time Sync Annex F enable */
 250 #define TS_ANNEX_D_EN       (1<<4)  /* Time Sync Annex D enable */
 251 #define TS_LTYPE2_EN        (1<<3)  /* Time Sync LTYPE 2 enable */
 252 #define TS_LTYPE1_EN        (1<<2)  /* Time Sync LTYPE 1 enable */
 253 #define TS_TX_EN            (1<<1)  /* Time Sync Transmit Enable */
 254 #define TS_RX_EN            (1<<0)  /* Time Sync Receive Enable */
 255
 256 #define CTRL_V2_TS_BITS \
 257         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 258          TS_TTL_NONZERO  | TS_ANNEX_D_EN | TS_LTYPE1_EN)
 259
 260 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
 261 #define CTRL_V2_TX_TS_BITS  (CTRL_V2_TS_BITS | TS_TX_EN)
 262 #define CTRL_V2_RX_TS_BITS  (CTRL_V2_TS_BITS | TS_RX_EN)
 263
 264
 265 #define CTRL_V3_TS_BITS \
 266         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 267          TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
 268          TS_LTYPE1_EN)
 269
 270 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
 271 #define CTRL_V3_TX_TS_BITS  (CTRL_V3_TS_BITS | TS_TX_EN)
 272 #define CTRL_V3_RX_TS_BITS  (CTRL_V3_TS_BITS | TS_RX_EN)
 273
 274 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
 275 #define TS_SEQ_ID_OFFSET_SHIFT   (16)    /* Time Sync Sequence ID Offset */
 276 #define TS_SEQ_ID_OFFSET_MASK    (0x3f)
 277 #define TS_MSG_TYPE_EN_SHIFT     (0)     /* Time Sync Message Type Enable */
 278 #define TS_MSG_TYPE_EN_MASK      (0xffff)
 279
 280 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
 281 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
 282
 283 /* Bit definitions for the CPSW1_TS_CTL register */
 284 #define CPSW_V1_TS_RX_EN                BIT(0)
 285 #define CPSW_V1_TS_TX_EN                BIT(4)
 286 #define CPSW_V1_MSG_TYPE_OFS            16
 287
 288 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
 289 #define CPSW_V1_SEQ_ID_OFS_SHIFT        16
 290
 291 #define CPSW_MAX_BLKS_TX                15
 292 #define CPSW_MAX_BLKS_TX_SHIFT          4
 293 #define CPSW_MAX_BLKS_RX                5
 294
 295 struct cpsw_host_regs {
 296         u32     max_blks;
 297         u32     blk_cnt;
 298         u32     tx_in_ctl;
 299         u32     port_vlan;
 300         u32     tx_pri_map;
 301         u32     cpdma_tx_pri_map;
 302         u32     cpdma_rx_chan_map;
 303 };
 304
 305 struct cpsw_sliver_regs {
 306         u32     id_ver;
 307         u32     mac_control;
 308         u32     mac_status;
 309         u32     soft_reset;
 310         u32     rx_maxlen;
 311         u32     __reserved_0;
 312         u32     rx_pause;
 313         u32     tx_pause;
 314         u32     __reserved_1;
 315         u32     rx_pri_map;
 316 };
 317
 318 struct cpsw_hw_stats {
 319         u32     rxgoodframes;
 320         u32     rxbroadcastframes;
 321         u32     rxmulticastframes;
 322         u32     rxpauseframes;
 323         u32     rxcrcerrors;
 324         u32     rxaligncodeerrors;
 325         u32     rxoversizedframes;
 326         u32     rxjabberframes;
 327         u32     rxundersizedframes;
 328         u32     rxfragments;
 329         u32     __pad_0[2];
 330         u32     rxoctets;
 331         u32     txgoodframes;
 332         u32     txbroadcastframes;
 333         u32     txmulticastframes;
 334         u32     txpauseframes;
 335         u32     txdeferredframes;
 336         u32     txcollisionframes;
 337         u32     txsinglecollframes;
 338         u32     txmultcollframes;
 339         u32     txexcessivecollisions;
 340         u32     txlatecollisions;
 341         u32     txunderrun;
 342         u32     txcarriersenseerrors;
 343         u32     txoctets;
 344         u32     octetframes64;
 345         u32     octetframes65t127;
 346         u32     octetframes128t255;
 347         u32     octetframes256t511;
 348         u32     octetframes512t1023;
 349         u32     octetframes1024tup;
 350         u32     netoctets;
 351         u32     rxsofoverruns;
 352         u32     rxmofoverruns;
 353         u32     rxdmaoverruns;
 354 };
 355
 356 struct cpsw_slave_data {
 357         struct device_node *phy_node;
 358         char            phy_id[MII_BUS_ID_SIZE];
 359         int             phy_if;
 360         u8              mac_addr[ETH_ALEN];
 361         u16             dual_emac_res_vlan;     /* Reserved VLAN for DualEMAC */
 362 };
 363
 364 struct cpsw_platform_data {
 365         struct cpsw_slave_data  *slave_data;
 366         u32     ss_reg_ofs;     /* Subsystem control register offset */
 367         u32     channels;       /* number of cpdma channels (symmetric) */
 368         u32     slaves;         /* number of slave cpgmac ports */
 369         u32     active_slave; /* time stamping, ethtool and SIOCGMIIPHY slave */
 370         u32     ale_entries;    /* ale table size */
 371         u32     bd_ram_size;  /*buffer descriptor ram size */
 372         u32     mac_control;    /* Mac control register */
 373         u16     default_vlan;   /* Def VLAN for ALE lookup in VLAN aware mode*/
 374         bool    dual_emac;      /* Enable Dual EMAC mode */
 375 };
 376
 377 struct cpsw_slave {
 378         void __iomem                    *regs;
 379         struct cpsw_sliver_regs __iomem *sliver;
 380         int                             slave_num;
 381         u32                             mac_control;
 382         struct cpsw_slave_data          *data;
 383         struct phy_device               *phy;
 384         struct net_device               *ndev;
 385         u32                             port_vlan;
 386 };
 387
 388 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
 389 {
 390         return readl_relaxed(slave->regs + offset);
 391 }
 392
 393 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
 394 {
 395         writel_relaxed(val, slave->regs + offset);
 396 }
 397
 398 struct cpsw_vector {
 399         struct cpdma_chan *ch;
 400         int budget;
 401 };
 402
 403 struct cpsw_common {
 404         struct device                   *dev;
 405         struct cpsw_platform_data       data;
 406         struct napi_struct              napi_rx;
 407         struct napi_struct              napi_tx;
 408         struct cpsw_ss_regs __iomem     *regs;
 409         struct cpsw_wr_regs __iomem     *wr_regs;
 410         u8 __iomem                      *hw_stats;
 411         struct cpsw_host_regs __iomem   *host_port_regs;
 412         u32                             version;
 413         u32                             coal_intvl;
 414         u32                             bus_freq_mhz;
 415         int                             rx_packet_max;
 416         struct cpsw_slave               *slaves;
 417         struct cpdma_ctlr               *dma;
 418         struct cpsw_vector              txv[CPSW_MAX_QUEUES];
 419         struct cpsw_vector              rxv[CPSW_MAX_QUEUES];
 420         struct cpsw_ale                 *ale;
 421         bool                            quirk_irq;
 422         bool                            rx_irq_disabled;
 423         bool                            tx_irq_disabled;
 424         u32 irqs_table[IRQ_NUM];
 425         struct cpts                     *cpts;
 426         int                             rx_ch_num, tx_ch_num;
 427         int                             speed;
 428         int                             usage_count;
 429 };
 430
 431 struct cpsw_priv {
 432         struct net_device               *ndev;
 433         struct device                   *dev;
 434         u32                             msg_enable;
 435         u8                              mac_addr[ETH_ALEN];
 436         bool                            rx_pause;
 437         bool                            tx_pause;
 438         u32 emac_port;
 439         struct cpsw_common *cpsw;
 440 };
 441
 442 struct cpsw_stats {
 443         char stat_string[ETH_GSTRING_LEN];
 444         int type;
 445         int sizeof_stat;
 446         int stat_offset;
 447 };
 448
 449 enum {
 450         CPSW_STATS,
 451         CPDMA_RX_STATS,
 452         CPDMA_TX_STATS,
 453 };
 454
 455 #define CPSW_STAT(m)            CPSW_STATS,                             \
 456                                 sizeof(((struct cpsw_hw_stats *)0)->m), \
 457                                 offsetof(struct cpsw_hw_stats, m)
 458 #define CPDMA_RX_STAT(m)        CPDMA_RX_STATS,                            \
 459                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 460                                 offsetof(struct cpdma_chan_stats, m)
 461 #define CPDMA_TX_STAT(m)        CPDMA_TX_STATS,                            \
 462                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 463                                 offsetof(struct cpdma_chan_stats, m)
 464
 465 static const struct cpsw_stats cpsw_gstrings_stats[] = {
 466         { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
 467         { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
 468         { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
 469         { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
 470         { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
 471         { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
 472         { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
 473         { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
 474         { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
 475         { "Rx Fragments", CPSW_STAT(rxfragments) },
 476         { "Rx Octets", CPSW_STAT(rxoctets) },
 477         { "Good Tx Frames", CPSW_STAT(txgoodframes) },
 478         { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
 479         { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
 480         { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
 481         { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
 482         { "Collisions", CPSW_STAT(txcollisionframes) },
 483         { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
 484         { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
 485         { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
 486         { "Late Collisions", CPSW_STAT(txlatecollisions) },
 487         { "Tx Underrun", CPSW_STAT(txunderrun) },
 488         { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
 489         { "Tx Octets", CPSW_STAT(txoctets) },
 490         { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
 491         { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
 492         { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
 493         { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
 494         { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
 495         { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
 496         { "Net Octets", CPSW_STAT(netoctets) },
 497         { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
 498         { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
 499         { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
 500 };
 501
 502 static const struct cpsw_stats cpsw_gstrings_ch_stats[] = {
 503         { "head_enqueue", CPDMA_RX_STAT(head_enqueue) },
 504         { "tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
 505         { "pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
 506         { "misqueued", CPDMA_RX_STAT(misqueued) },
 507         { "desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
 508         { "pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
 509         { "runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
 510         { "runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
 511         { "empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
 512         { "busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
 513         { "good_dequeue", CPDMA_RX_STAT(good_dequeue) },
 514         { "requeue", CPDMA_RX_STAT(requeue) },
 515         { "teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
 516 };
 517
 518 #define CPSW_STATS_COMMON_LEN   ARRAY_SIZE(cpsw_gstrings_stats)
 519 #define CPSW_STATS_CH_LEN       ARRAY_SIZE(cpsw_gstrings_ch_stats)
 520
 521 #define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw)
 522 #define napi_to_cpsw(napi)      container_of(napi, struct cpsw_common, napi)
 523 #define for_each_slave(priv, func, arg...)                              \
 524         do {                                                            \
 525                 struct cpsw_slave *slave;                               \
 526                 struct cpsw_common *cpsw = (priv)->cpsw;                \
 527                 int n;                                                  \
 528                 if (cpsw->data.dual_emac)                               \
 529                         (func)((cpsw)->slaves + priv->emac_port, ##arg);\
 530                 else                                                    \
 531                         for (n = cpsw->data.slaves,                     \
 532                                         slave = cpsw->slaves;           \
 533                                         n; n--)                         \
 534                                 (func)(slave++, ##arg);                 \
 535         } while (0)
 536
 537 #define cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb)         \
 538         do {                                                            \
 539                 if (!cpsw->data.dual_emac)                              \
 540                         break;                                          \
 541                 if (CPDMA_RX_SOURCE_PORT(status) == 1) {                \
 542                         ndev = cpsw->slaves[0].ndev;                    \
 543                         skb->dev = ndev;                                \
 544                 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) {         \
 545                         ndev = cpsw->slaves[1].ndev;                    \
 546                         skb->dev = ndev;                                \
 547                 }                                                       \
 548         } while (0)
 549 #define cpsw_add_mcast(cpsw, priv, addr)                                \
 550         do {                                                            \
 551                 if (cpsw->data.dual_emac) {                             \
 552                         struct cpsw_slave *slave = cpsw->slaves +       \
 553                                                 priv->emac_port;        \
 554                         int slave_port = cpsw_get_slave_port(           \
 555                                                 slave->slave_num);      \
 556                         cpsw_ale_add_mcast(cpsw->ale, addr,             \
 557                                 1 << slave_port | ALE_PORT_HOST,        \
 558                                 ALE_VLAN, slave->port_vlan, 0);         \
 559                 } else {                                                \
 560                         cpsw_ale_add_mcast(cpsw->ale, addr,             \
 561                                 ALE_ALL_PORTS,                          \
 562                                 0, 0, 0);                               \
 563                 }                                                       \
 564         } while (0)
 565
 566 static inline int cpsw_get_slave_port(u32 slave_num)
 567 {
 568         return slave_num + 1;
 569 }
 570
 571 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
 572 {
 573         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
 574         struct cpsw_ale *ale = cpsw->ale;
 575         int i;
 576
 577         if (cpsw->data.dual_emac) {
 578                 bool flag = false;
 579
 580                 /* Enabling promiscuous mode for one interface will be
 581                  * common for both the interface as the interface shares
 582                  * the same hardware resource.
 583                  */
 584                 for (i = 0; i < cpsw->data.slaves; i++)
 585                         if (cpsw->slaves[i].ndev->flags & IFF_PROMISC)
 586                                 flag = true;
 587
 588                 if (!enable && flag) {
 589                         enable = true;
 590                         dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
 591                 }
 592
 593                 if (enable) {
 594                         /* Enable Bypass */
 595                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
 596
 597                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 598                 } else {
 599                         /* Disable Bypass */
 600                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
 601                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 602                 }
 603         } else {
 604                 if (enable) {
 605                         unsigned long timeout = jiffies + HZ;
 606
 607                         /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
 608                         for (i = 0; i <= cpsw->data.slaves; i++) {
 609                                 cpsw_ale_control_set(ale, i,
 610                                                      ALE_PORT_NOLEARN, 1);
 611                                 cpsw_ale_control_set(ale, i,
 612                                                      ALE_PORT_NO_SA_UPDATE, 1);
 613                         }
 614
 615                         /* Clear All Untouched entries */
 616                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 617                         do {
 618                                 cpu_relax();
 619                                 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
 620                                         break;
 621                         } while (time_after(timeout, jiffies));
 622                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 623
 624                         /* Clear all mcast from ALE */
 625                         cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS, -1);
 626
 627                         /* Flood All Unicast Packets to Host port */
 628                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
 629                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 630                 } else {
 631                         /* Don't Flood All Unicast Packets to Host port */
 632                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
 633
 634                         /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
 635                         for (i = 0; i <= cpsw->data.slaves; i++) {
 636                                 cpsw_ale_control_set(ale, i,
 637                                                      ALE_PORT_NOLEARN, 0);
 638                                 cpsw_ale_control_set(ale, i,
 639                                                      ALE_PORT_NO_SA_UPDATE, 0);
 640                         }
 641                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 642                 }
 643         }
 644 }
 645
 646 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
 647 {
 648         struct cpsw_priv *priv = netdev_priv(ndev);
 649         struct cpsw_common *cpsw = priv->cpsw;
 650         int vid;
 651
 652         if (cpsw->data.dual_emac)
 653                 vid = cpsw->slaves[priv->emac_port].port_vlan;
 654         else
 655                 vid = cpsw->data.default_vlan;
 656
 657         if (ndev->flags & IFF_PROMISC) {
 658                 /* Enable promiscuous mode */
 659                 cpsw_set_promiscious(ndev, true);
 660                 cpsw_ale_set_allmulti(cpsw->ale, IFF_ALLMULTI);
 661                 return;
 662         } else {
 663                 /* Disable promiscuous mode */
 664                 cpsw_set_promiscious(ndev, false);
 665         }
 666
 667         /* Restore allmulti on vlans if necessary */
 668         cpsw_ale_set_allmulti(cpsw->ale, priv->ndev->flags & IFF_ALLMULTI);
 669
 670         /* Clear all mcast from ALE */
 671         cpsw_ale_flush_multicast(cpsw->ale, ALE_ALL_PORTS, vid);
 672
 673         if (!netdev_mc_empty(ndev)) {
 674                 struct netdev_hw_addr *ha;
 675
 676                 /* program multicast address list into ALE register */
 677                 netdev_for_each_mc_addr(ha, ndev) {
 678                         cpsw_add_mcast(cpsw, priv, (u8 *)ha->addr);
 679                 }
 680         }
 681 }
 682
 683 static void cpsw_intr_enable(struct cpsw_common *cpsw)
 684 {
 685         writel_relaxed(0xFF, &cpsw->wr_regs->tx_en);
 686         writel_relaxed(0xFF, &cpsw->wr_regs->rx_en);
 687
 688         cpdma_ctlr_int_ctrl(cpsw->dma, true);
 689         return;
 690 }
 691
 692 static void cpsw_intr_disable(struct cpsw_common *cpsw)
 693 {
 694         writel_relaxed(0, &cpsw->wr_regs->tx_en);
 695         writel_relaxed(0, &cpsw->wr_regs->rx_en);
 696
 697         cpdma_ctlr_int_ctrl(cpsw->dma, false);
 698         return;
 699 }
 700
 701 static void cpsw_tx_handler(void *token, int len, int status)
 702 {
 703         struct netdev_queue     *txq;
 704         struct sk_buff          *skb = token;
 705         struct net_device       *ndev = skb->dev;
 706         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
 707
 708         /* Check whether the queue is stopped due to stalled tx dma, if the
 709          * queue is stopped then start the queue as we have free desc for tx
 710          */
 711         txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb));
 712         if (unlikely(netif_tx_queue_stopped(txq)))
 713                 netif_tx_wake_queue(txq);
 714
 715         cpts_tx_timestamp(cpsw->cpts, skb);
 716         ndev->stats.tx_packets++;
 717         ndev->stats.tx_bytes += len;
 718         dev_kfree_skb_any(skb);
 719 }
 720
 721 static void cpsw_rx_handler(void *token, int len, int status)
 722 {
 723         struct cpdma_chan       *ch;
 724         struct sk_buff          *skb = token;
 725         struct sk_buff          *new_skb;
 726         struct net_device       *ndev = skb->dev;
 727         int                     ret = 0;
 728         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
 729
 730         cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb);
 731
 732         if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
 733                 /* In dual emac mode check for all interfaces */
 734                 if (cpsw->data.dual_emac && cpsw->usage_count &&
 735                     (status >= 0)) {
 736                         /* The packet received is for the interface which
 737                          * is already down and the other interface is up
 738                          * and running, instead of freeing which results
 739                          * in reducing of the number of rx descriptor in
 740                          * DMA engine, requeue skb back to cpdma.
 741                          */
 742                         new_skb = skb;
 743                         goto requeue;
 744                 }
 745
 746                 /* the interface is going down, skbs are purged */
 747                 dev_kfree_skb_any(skb);
 748                 return;
 749         }
 750
 751         new_skb = netdev_alloc_skb_ip_align(ndev, cpsw->rx_packet_max);
 752         if (new_skb) {
 753                 skb_copy_queue_mapping(new_skb, skb);
 754                 skb_put(skb, len);
 755                 cpts_rx_timestamp(cpsw->cpts, skb);
 756                 skb->protocol = eth_type_trans(skb, ndev);
 757                 netif_receive_skb(skb);
 758                 ndev->stats.rx_bytes += len;
 759                 ndev->stats.rx_packets++;
 760                 kmemleak_not_leak(new_skb);
 761         } else {
 762                 ndev->stats.rx_dropped++;
 763                 new_skb = skb;
 764         }
 765
 766 requeue:
 767         if (netif_dormant(ndev)) {
 768                 dev_kfree_skb_any(new_skb);
 769                 return;
 770         }
 771
 772         ch = cpsw->rxv[skb_get_queue_mapping(new_skb)].ch;
 773         ret = cpdma_chan_submit(ch, new_skb, new_skb->data,
 774                                 skb_tailroom(new_skb), 0);
 775         if (WARN_ON(ret < 0))
 776                 dev_kfree_skb_any(new_skb);
 777 }
 778
 779 static void cpsw_split_res(struct net_device *ndev)
 780 {
 781         struct cpsw_priv *priv = netdev_priv(ndev);
 782         u32 consumed_rate = 0, bigest_rate = 0;
 783         struct cpsw_common *cpsw = priv->cpsw;
 784         struct cpsw_vector *txv = cpsw->txv;
 785         int i, ch_weight, rlim_ch_num = 0;
 786         int budget, bigest_rate_ch = 0;
 787         u32 ch_rate, max_rate;
 788         int ch_budget = 0;
 789
 790         for (i = 0; i < cpsw->tx_ch_num; i++) {
 791                 ch_rate = cpdma_chan_get_rate(txv[i].ch);
 792                 if (!ch_rate)
 793                         continue;
 794
 795                 rlim_ch_num++;
 796                 consumed_rate += ch_rate;
 797         }
 798
 799         if (cpsw->tx_ch_num == rlim_ch_num) {
 800                 max_rate = consumed_rate;
 801         } else if (!rlim_ch_num) {
 802                 ch_budget = CPSW_POLL_WEIGHT / cpsw->tx_ch_num;
 803                 bigest_rate = 0;
 804                 max_rate = consumed_rate;
 805         } else {
 806                 max_rate = cpsw->speed * 1000;
 807
 808                 /* if max_rate is less then expected due to reduced link speed,
 809                  * split proportionally according next potential max speed
 810                  */
 811                 if (max_rate < consumed_rate)
 812                         max_rate *= 10;
 813
 814                 if (max_rate < consumed_rate)
 815                         max_rate *= 10;
 816
 817                 ch_budget = (consumed_rate * CPSW_POLL_WEIGHT) / max_rate;
 818                 ch_budget = (CPSW_POLL_WEIGHT - ch_budget) /
 819                             (cpsw->tx_ch_num - rlim_ch_num);
 820                 bigest_rate = (max_rate - consumed_rate) /
 821                               (cpsw->tx_ch_num - rlim_ch_num);
 822         }
 823
 824         /* split tx weight/budget */
 825         budget = CPSW_POLL_WEIGHT;
 826         for (i = 0; i < cpsw->tx_ch_num; i++) {
 827                 ch_rate = cpdma_chan_get_rate(txv[i].ch);
 828                 if (ch_rate) {
 829                         txv[i].budget = (ch_rate * CPSW_POLL_WEIGHT) / max_rate;
 830                         if (!txv[i].budget)
 831                                 txv[i].budget++;
 832                         if (ch_rate > bigest_rate) {
 833                                 bigest_rate_ch = i;
 834                                 bigest_rate = ch_rate;
 835                         }
 836
 837                         ch_weight = (ch_rate * 100) / max_rate;
 838                         if (!ch_weight)
 839                                 ch_weight++;
 840                         cpdma_chan_set_weight(cpsw->txv[i].ch, ch_weight);
 841                 } else {
 842                         txv[i].budget = ch_budget;
 843                         if (!bigest_rate_ch)
 844                                 bigest_rate_ch = i;
 845                         cpdma_chan_set_weight(cpsw->txv[i].ch, 0);
 846                 }
 847
 848                 budget -= txv[i].budget;
 849         }
 850
 851         if (budget)
 852                 txv[bigest_rate_ch].budget += budget;
 853
 854         /* split rx budget */
 855         budget = CPSW_POLL_WEIGHT;
 856         ch_budget = budget / cpsw->rx_ch_num;
 857         for (i = 0; i < cpsw->rx_ch_num; i++) {
 858                 cpsw->rxv[i].budget = ch_budget;
 859                 budget -= ch_budget;
 860         }
 861
 862         if (budget)
 863                 cpsw->rxv[0].budget += budget;
 864 }
 865
 866 static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
 867 {
 868         struct cpsw_common *cpsw = dev_id;
 869
 870         writel(0, &cpsw->wr_regs->tx_en);
 871         cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_TX);
 872
 873         if (cpsw->quirk_irq) {
 874                 disable_irq_nosync(cpsw->irqs_table[1]);
 875                 cpsw->tx_irq_disabled = true;
 876         }
 877
 878         napi_schedule(&cpsw->napi_tx);
 879         return IRQ_HANDLED;
 880 }
 881
 882 static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
 883 {
 884         struct cpsw_common *cpsw = dev_id;
 885
 886         cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_RX);
 887         writel(0, &cpsw->wr_regs->rx_en);
 888
 889         if (cpsw->quirk_irq) {
 890                 disable_irq_nosync(cpsw->irqs_table[0]);
 891                 cpsw->rx_irq_disabled = true;
 892         }
 893
 894         napi_schedule(&cpsw->napi_rx);
 895         return IRQ_HANDLED;
 896 }
 897
 898 static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
 899 {
 900         u32                     ch_map;
 901         int                     num_tx, cur_budget, ch;
 902         struct cpsw_common      *cpsw = napi_to_cpsw(napi_tx);
 903         struct cpsw_vector      *txv;
 904
 905         /* process every unprocessed channel */
 906         ch_map = cpdma_ctrl_txchs_state(cpsw->dma);
 907         for (ch = 0, num_tx = 0; ch_map; ch_map >>= 1, ch++) {
 908                 if (!(ch_map & 0x01))
 909                         continue;
 910
 911                 txv = &cpsw->txv[ch];
 912                 if (unlikely(txv->budget > budget - num_tx))
 913                         cur_budget = budget - num_tx;
 914                 else
 915                         cur_budget = txv->budget;
 916
 917                 num_tx += cpdma_chan_process(txv->ch, cur_budget);
 918                 if (num_tx >= budget)
 919                         break;
 920         }
 921
 922         if (num_tx < budget) {
 923                 napi_complete(napi_tx);
 924                 writel(0xff, &cpsw->wr_regs->tx_en);
 925                 if (cpsw->quirk_irq && cpsw->tx_irq_disabled) {
 926                         cpsw->tx_irq_disabled = false;
 927                         enable_irq(cpsw->irqs_table[1]);
 928                 }
 929         }
 930
 931         return num_tx;
 932 }
 933
 934 static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
 935 {
 936         u32                     ch_map;
 937         int                     num_rx, cur_budget, ch;
 938         struct cpsw_common      *cpsw = napi_to_cpsw(napi_rx);
 939         struct cpsw_vector      *rxv;
 940
 941         /* process every unprocessed channel */
 942         ch_map = cpdma_ctrl_rxchs_state(cpsw->dma);
 943         for (ch = 0, num_rx = 0; ch_map; ch_map >>= 1, ch++) {
 944                 if (!(ch_map & 0x01))
 945                         continue;
 946
 947                 rxv = &cpsw->rxv[ch];
 948                 if (unlikely(rxv->budget > budget - num_rx))
 949                         cur_budget = budget - num_rx;
 950                 else
 951                         cur_budget = rxv->budget;
 952
 953                 num_rx += cpdma_chan_process(rxv->ch, cur_budget);
 954                 if (num_rx >= budget)
 955                         break;
 956         }
 957
 958         if (num_rx < budget) {
 959                 napi_complete_done(napi_rx, num_rx);
 960                 writel(0xff, &cpsw->wr_regs->rx_en);
 961                 if (cpsw->quirk_irq && cpsw->rx_irq_disabled) {
 962                         cpsw->rx_irq_disabled = false;
 963                         enable_irq(cpsw->irqs_table[0]);
 964                 }
 965         }
 966
 967         return num_rx;
 968 }
 969
 970 static inline void soft_reset(const char *module, void __iomem *reg)
 971 {
 972         unsigned long timeout = jiffies + HZ;
 973
 974         writel_relaxed(1, reg);
 975         do {
 976                 cpu_relax();
 977         } while ((readl_relaxed(reg) & 1) && time_after(timeout, jiffies));
 978
 979         WARN(readl_relaxed(reg) & 1, "failed to soft-reset %s\n", module);
 980 }
 981
 982 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
 983                                struct cpsw_priv *priv)
 984 {
 985         slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
 986         slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
 987 }
 988
 989 static void _cpsw_adjust_link(struct cpsw_slave *slave,
 990                               struct cpsw_priv *priv, bool *link)
 991 {
 992         struct phy_device       *phy = slave->phy;
 993         u32                     mac_control = 0;
 994         u32                     slave_port;
 995         struct cpsw_common *cpsw = priv->cpsw;
 996
 997         if (!phy)
 998                 return;
 999
1000         slave_port = cpsw_get_slave_port(slave->slave_num);
1001
1002         if (phy->link) {
1003                 mac_control = cpsw->data.mac_control;
1004
1005                 /* enable forwarding */
1006                 cpsw_ale_control_set(cpsw->ale, slave_port,
1007                                      ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1008
1009                 if (phy->speed == 1000)
1010                         mac_control |= BIT(7);  /* GIGABITEN    */
1011                 if (phy->duplex)
1012                         mac_control |= BIT(0);  /* FULLDUPLEXEN */
1013
1014                 /* set speed_in input in case RMII mode is used in 100Mbps */
1015                 if (phy->speed == 100)
1016                         mac_control |= BIT(15);
1017                 else if (phy->speed == 10)
1018                         mac_control |= BIT(18); /* In Band mode */
1019
1020                 if (priv->rx_pause)
1021                         mac_control |= BIT(3);
1022
1023                 if (priv->tx_pause)
1024                         mac_control |= BIT(4);
1025
1026                 *link = true;
1027         } else {
1028                 mac_control = 0;
1029                 /* disable forwarding */
1030                 cpsw_ale_control_set(cpsw->ale, slave_port,
1031                                      ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1032         }
1033
1034         if (mac_control != slave->mac_control) {
1035                 phy_print_status(phy);
1036                 writel_relaxed(mac_control, &slave->sliver->mac_control);
1037         }
1038
1039         slave->mac_control = mac_control;
1040 }
1041
1042 static int cpsw_get_common_speed(struct cpsw_common *cpsw)
1043 {
1044         int i, speed;
1045
1046         for (i = 0, speed = 0; i < cpsw->data.slaves; i++)
1047                 if (cpsw->slaves[i].phy && cpsw->slaves[i].phy->link)
1048                         speed += cpsw->slaves[i].phy->speed;
1049
1050         return speed;
1051 }
1052
1053 static int cpsw_need_resplit(struct cpsw_common *cpsw)
1054 {
1055         int i, rlim_ch_num;
1056         int speed, ch_rate;
1057
1058         /* re-split resources only in case speed was changed */
1059         speed = cpsw_get_common_speed(cpsw);
1060         if (speed == cpsw->speed || !speed)
1061                 return 0;
1062
1063         cpsw->speed = speed;
1064
1065         for (i = 0, rlim_ch_num = 0; i < cpsw->tx_ch_num; i++) {
1066                 ch_rate = cpdma_chan_get_rate(cpsw->txv[i].ch);
1067                 if (!ch_rate)
1068                         break;
1069
1070                 rlim_ch_num++;
1071         }
1072
1073         /* cases not dependent on speed */
1074         if (!rlim_ch_num || rlim_ch_num == cpsw->tx_ch_num)
1075                 return 0;
1076
1077         return 1;
1078 }
1079
1080 static void cpsw_adjust_link(struct net_device *ndev)
1081 {
1082         struct cpsw_priv        *priv = netdev_priv(ndev);
1083         struct cpsw_common      *cpsw = priv->cpsw;
1084         bool                    link = false;
1085
1086         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1087
1088         if (link) {
1089                 if (cpsw_need_resplit(cpsw))
1090                         cpsw_split_res(ndev);
1091
1092                 netif_carrier_on(ndev);
1093                 if (netif_running(ndev))
1094                         netif_tx_wake_all_queues(ndev);
1095         } else {
1096                 netif_carrier_off(ndev);
1097                 netif_tx_stop_all_queues(ndev);
1098         }
1099 }
1100
1101 static int cpsw_get_coalesce(struct net_device *ndev,
1102                                 struct ethtool_coalesce *coal)
1103 {
1104         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1105
1106         coal->rx_coalesce_usecs = cpsw->coal_intvl;
1107         return 0;
1108 }
1109
1110 static int cpsw_set_coalesce(struct net_device *ndev,
1111                                 struct ethtool_coalesce *coal)
1112 {
1113         struct cpsw_priv *priv = netdev_priv(ndev);
1114         u32 int_ctrl;
1115         u32 num_interrupts = 0;
1116         u32 prescale = 0;
1117         u32 addnl_dvdr = 1;
1118         u32 coal_intvl = 0;
1119         struct cpsw_common *cpsw = priv->cpsw;
1120
1121         coal_intvl = coal->rx_coalesce_usecs;
1122
1123         int_ctrl =  readl(&cpsw->wr_regs->int_control);
1124         prescale = cpsw->bus_freq_mhz * 4;
1125
1126         if (!coal->rx_coalesce_usecs) {
1127                 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
1128                 goto update_return;
1129         }
1130
1131         if (coal_intvl < CPSW_CMINTMIN_INTVL)
1132                 coal_intvl = CPSW_CMINTMIN_INTVL;
1133
1134         if (coal_intvl > CPSW_CMINTMAX_INTVL) {
1135                 /* Interrupt pacer works with 4us Pulse, we can
1136                  * throttle further by dilating the 4us pulse.
1137                  */
1138                 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
1139
1140                 if (addnl_dvdr > 1) {
1141                         prescale *= addnl_dvdr;
1142                         if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
1143                                 coal_intvl = (CPSW_CMINTMAX_INTVL
1144                                                 * addnl_dvdr);
1145                 } else {
1146                         addnl_dvdr = 1;
1147                         coal_intvl = CPSW_CMINTMAX_INTVL;
1148                 }
1149         }
1150
1151         num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
1152         writel(num_interrupts, &cpsw->wr_regs->rx_imax);
1153         writel(num_interrupts, &cpsw->wr_regs->tx_imax);
1154
1155         int_ctrl |= CPSW_INTPACEEN;
1156         int_ctrl &= (~CPSW_INTPRESCALE_MASK);
1157         int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
1158
1159 update_return:
1160         writel(int_ctrl, &cpsw->wr_regs->int_control);
1161
1162         cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
1163         cpsw->coal_intvl = coal_intvl;
1164
1165         return 0;
1166 }
1167
1168 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
1169 {
1170         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1171
1172         switch (sset) {
1173         case ETH_SS_STATS:
1174                 return (CPSW_STATS_COMMON_LEN +
1175                        (cpsw->rx_ch_num + cpsw->tx_ch_num) *
1176                        CPSW_STATS_CH_LEN);
1177         default:
1178                 return -EOPNOTSUPP;
1179         }
1180 }
1181
1182 static void cpsw_add_ch_strings(u8 **p, int ch_num, int rx_dir)
1183 {
1184         int ch_stats_len;
1185         int line;
1186         int i;
1187
1188         ch_stats_len = CPSW_STATS_CH_LEN * ch_num;
1189         for (i = 0; i < ch_stats_len; i++) {
1190                 line = i % CPSW_STATS_CH_LEN;
1191                 snprintf(*p, ETH_GSTRING_LEN,
1192                          "%s DMA chan %d: %s", rx_dir ? "Rx" : "Tx",
1193                          i / CPSW_STATS_CH_LEN,
1194                          cpsw_gstrings_ch_stats[line].stat_string);
1195                 *p += ETH_GSTRING_LEN;
1196         }
1197 }
1198
1199 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1200 {
1201         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1202         u8 *p = data;
1203         int i;
1204
1205         switch (stringset) {
1206         case ETH_SS_STATS:
1207                 for (i = 0; i < CPSW_STATS_COMMON_LEN; i++) {
1208                         memcpy(p, cpsw_gstrings_stats[i].stat_string,
1209                                ETH_GSTRING_LEN);
1210                         p += ETH_GSTRING_LEN;
1211                 }
1212
1213                 cpsw_add_ch_strings(&p, cpsw->rx_ch_num, 1);
1214                 cpsw_add_ch_strings(&p, cpsw->tx_ch_num, 0);
1215                 break;
1216         }
1217 }
1218
1219 static void cpsw_get_ethtool_stats(struct net_device *ndev,
1220                                     struct ethtool_stats *stats, u64 *data)
1221 {
1222         u8 *p;
1223         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1224         struct cpdma_chan_stats ch_stats;
1225         int i, l, ch;
1226
1227         /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1228         for (l = 0; l < CPSW_STATS_COMMON_LEN; l++)
1229                 data[l] = readl(cpsw->hw_stats +
1230                                 cpsw_gstrings_stats[l].stat_offset);
1231
1232         for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1233                 cpdma_chan_get_stats(cpsw->rxv[ch].ch, &ch_stats);
1234                 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1235                         p = (u8 *)&ch_stats +
1236                                 cpsw_gstrings_ch_stats[i].stat_offset;
1237                         data[l] = *(u32 *)p;
1238                 }
1239         }
1240
1241         for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
1242                 cpdma_chan_get_stats(cpsw->txv[ch].ch, &ch_stats);
1243                 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1244                         p = (u8 *)&ch_stats +
1245                                 cpsw_gstrings_ch_stats[i].stat_offset;
1246                         data[l] = *(u32 *)p;
1247                 }
1248         }
1249 }
1250
1251 static inline int cpsw_tx_packet_submit(struct cpsw_priv *priv,
1252                                         struct sk_buff *skb,
1253                                         struct cpdma_chan *txch)
1254 {
1255         struct cpsw_common *cpsw = priv->cpsw;
1256
1257         skb_tx_timestamp(skb);
1258         return cpdma_chan_submit(txch, skb, skb->data, skb->len,
1259                                  priv->emac_port + cpsw->data.dual_emac);
1260 }
1261
1262 static inline void cpsw_add_dual_emac_def_ale_entries(
1263                 struct cpsw_priv *priv, struct cpsw_slave *slave,
1264                 u32 slave_port)
1265 {
1266         struct cpsw_common *cpsw = priv->cpsw;
1267         u32 port_mask = 1 << slave_port | ALE_PORT_HOST;
1268
1269         if (cpsw->version == CPSW_VERSION_1)
1270                 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1271         else
1272                 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1273         cpsw_ale_add_vlan(cpsw->ale, slave->port_vlan, port_mask,
1274                           port_mask, port_mask, 0);
1275         cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1276                            port_mask, ALE_VLAN, slave->port_vlan, 0);
1277         cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
1278                            HOST_PORT_NUM, ALE_VLAN |
1279                            ALE_SECURE, slave->port_vlan);
1280 }
1281
1282 static void soft_reset_slave(struct cpsw_slave *slave)
1283 {
1284         char name[32];
1285
1286         snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1287         soft_reset(name, &slave->sliver->soft_reset);
1288 }
1289
1290 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1291 {
1292         u32 slave_port;
1293         struct phy_device *phy;
1294         struct cpsw_common *cpsw = priv->cpsw;
1295
1296         soft_reset_slave(slave);
1297
1298         /* setup priority mapping */
1299         writel_relaxed(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1300
1301         switch (cpsw->version) {
1302         case CPSW_VERSION_1:
1303                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1304                 /* Increase RX FIFO size to 5 for supporting fullduplex
1305                  * flow control mode
1306                  */
1307                 slave_write(slave,
1308                             (CPSW_MAX_BLKS_TX << CPSW_MAX_BLKS_TX_SHIFT) |
1309                             CPSW_MAX_BLKS_RX, CPSW1_MAX_BLKS);
1310                 break;
1311         case CPSW_VERSION_2:
1312         case CPSW_VERSION_3:
1313         case CPSW_VERSION_4:
1314                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1315                 /* Increase RX FIFO size to 5 for supporting fullduplex
1316                  * flow control mode
1317                  */
1318                 slave_write(slave,
1319                             (CPSW_MAX_BLKS_TX << CPSW_MAX_BLKS_TX_SHIFT) |
1320                             CPSW_MAX_BLKS_RX, CPSW2_MAX_BLKS);
1321                 break;
1322         }
1323
1324         /* setup max packet size, and mac address */
1325         writel_relaxed(cpsw->rx_packet_max, &slave->sliver->rx_maxlen);
1326         cpsw_set_slave_mac(slave, priv);
1327
1328         slave->mac_control = 0; /* no link yet */
1329
1330         slave_port = cpsw_get_slave_port(slave->slave_num);
1331
1332         if (cpsw->data.dual_emac)
1333                 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1334         else
1335                 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1336                                    1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1337
1338         if (slave->data->phy_node) {
1339                 phy = of_phy_connect(priv->ndev, slave->data->phy_node,
1340                                  &cpsw_adjust_link, 0, slave->data->phy_if);
1341                 if (!phy) {
1342                         dev_err(priv->dev, "phy \"%pOF\" not found on slave %d\n",
1343                                 slave->data->phy_node,
1344                                 slave->slave_num);
1345                         return;
1346                 }
1347         } else {
1348                 phy = phy_connect(priv->ndev, slave->data->phy_id,
1349                                  &cpsw_adjust_link, slave->data->phy_if);
1350                 if (IS_ERR(phy)) {
1351                         dev_err(priv->dev,
1352                                 "phy \"%s\" not found on slave %d, err %ld\n",
1353                                 slave->data->phy_id, slave->slave_num,
1354                                 PTR_ERR(phy));
1355                         return;
1356                 }
1357         }
1358
1359         slave->phy = phy;
1360
1361         phy_attached_info(slave->phy);
1362
1363         phy_start(slave->phy);
1364
1365         /* Configure GMII_SEL register */
1366         cpsw_phy_sel(cpsw->dev, slave->phy->interface, slave->slave_num);
1367 }
1368
1369 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1370 {
1371         struct cpsw_common *cpsw = priv->cpsw;
1372         const int vlan = cpsw->data.default_vlan;
1373         u32 reg;
1374         int i;
1375         int unreg_mcast_mask;
1376
1377         reg = (cpsw->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1378                CPSW2_PORT_VLAN;
1379
1380         writel(vlan, &cpsw->host_port_regs->port_vlan);
1381
1382         for (i = 0; i < cpsw->data.slaves; i++)
1383                 slave_write(cpsw->slaves + i, vlan, reg);
1384
1385         if (priv->ndev->flags & IFF_ALLMULTI)
1386                 unreg_mcast_mask = ALE_ALL_PORTS;
1387         else
1388                 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1389
1390         cpsw_ale_add_vlan(cpsw->ale, vlan, ALE_ALL_PORTS,
1391                           ALE_ALL_PORTS, ALE_ALL_PORTS,
1392                           unreg_mcast_mask);
1393 }
1394
1395 static void cpsw_init_host_port(struct cpsw_priv *priv)
1396 {
1397         u32 fifo_mode;
1398         u32 control_reg;
1399         struct cpsw_common *cpsw = priv->cpsw;
1400
1401         /* soft reset the controller and initialize ale */
1402         soft_reset("cpsw", &cpsw->regs->soft_reset);
1403         cpsw_ale_start(cpsw->ale);
1404
1405         /* switch to vlan unaware mode */
1406         cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_VLAN_AWARE,
1407                              CPSW_ALE_VLAN_AWARE);
1408         control_reg = readl(&cpsw->regs->control);
1409         control_reg |= CPSW_VLAN_AWARE;
1410         writel(control_reg, &cpsw->regs->control);
1411         fifo_mode = (cpsw->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1412                      CPSW_FIFO_NORMAL_MODE;
1413         writel(fifo_mode, &cpsw->host_port_regs->tx_in_ctl);
1414
1415         /* setup host port priority mapping */
1416         writel_relaxed(CPDMA_TX_PRIORITY_MAP,
1417                        &cpsw->host_port_regs->cpdma_tx_pri_map);
1418         writel_relaxed(0, &cpsw->host_port_regs->cpdma_rx_chan_map);
1419
1420         cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM,
1421                              ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1422
1423         if (!cpsw->data.dual_emac) {
1424                 cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
1425                                    0, 0);
1426                 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1427                                    ALE_PORT_HOST, 0, 0, ALE_MCAST_FWD_2);
1428         }
1429 }
1430
1431 static int cpsw_fill_rx_channels(struct cpsw_priv *priv)
1432 {
1433         struct cpsw_common *cpsw = priv->cpsw;
1434         struct sk_buff *skb;
1435         int ch_buf_num;
1436         int ch, i, ret;
1437
1438         for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1439                 ch_buf_num = cpdma_chan_get_rx_buf_num(cpsw->rxv[ch].ch);
1440                 for (i = 0; i < ch_buf_num; i++) {
1441                         skb = __netdev_alloc_skb_ip_align(priv->ndev,
1442                                                           cpsw->rx_packet_max,
1443                                                           GFP_KERNEL);
1444                         if (!skb) {
1445                                 cpsw_err(priv, ifup, "cannot allocate skb\n");
1446                                 return -ENOMEM;
1447                         }
1448
1449                         skb_set_queue_mapping(skb, ch);
1450                         ret = cpdma_chan_submit(cpsw->rxv[ch].ch, skb,
1451                                                 skb->data, skb_tailroom(skb),
1452                                                 0);
1453                         if (ret < 0) {
1454                                 cpsw_err(priv, ifup,
1455                                          "cannot submit skb to channel %d rx, error %d\n",
1456                                          ch, ret);
1457                                 kfree_skb(skb);
1458                                 return ret;
1459                         }
1460                         kmemleak_not_leak(skb);
1461                 }
1462
1463                 cpsw_info(priv, ifup, "ch %d rx, submitted %d descriptors\n",
1464                           ch, ch_buf_num);
1465         }
1466
1467         return 0;
1468 }
1469
1470 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_common *cpsw)
1471 {
1472         u32 slave_port;
1473
1474         slave_port = cpsw_get_slave_port(slave->slave_num);
1475
1476         if (!slave->phy)
1477                 return;
1478         phy_stop(slave->phy);
1479         phy_disconnect(slave->phy);
1480         slave->phy = NULL;
1481         cpsw_ale_control_set(cpsw->ale, slave_port,
1482                              ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1483         soft_reset_slave(slave);
1484 }
1485
1486 static int cpsw_ndo_open(struct net_device *ndev)
1487 {
1488         struct cpsw_priv *priv = netdev_priv(ndev);
1489         struct cpsw_common *cpsw = priv->cpsw;
1490         int ret;
1491         u32 reg;
1492
1493         ret = pm_runtime_get_sync(cpsw->dev);
1494         if (ret < 0) {
1495                 pm_runtime_put_noidle(cpsw->dev);
1496                 return ret;
1497         }
1498
1499         netif_carrier_off(ndev);
1500
1501         /* Notify the stack of the actual queue counts. */
1502         ret = netif_set_real_num_tx_queues(ndev, cpsw->tx_ch_num);
1503         if (ret) {
1504                 dev_err(priv->dev, "cannot set real number of tx queues\n");
1505                 goto err_cleanup;
1506         }
1507
1508         ret = netif_set_real_num_rx_queues(ndev, cpsw->rx_ch_num);
1509         if (ret) {
1510                 dev_err(priv->dev, "cannot set real number of rx queues\n");
1511                 goto err_cleanup;
1512         }
1513
1514         reg = cpsw->version;
1515
1516         dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1517                  CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1518                  CPSW_RTL_VERSION(reg));
1519
1520         /* Initialize host and slave ports */
1521         if (!cpsw->usage_count)
1522                 cpsw_init_host_port(priv);
1523         for_each_slave(priv, cpsw_slave_open, priv);
1524
1525         /* Add default VLAN */
1526         if (!cpsw->data.dual_emac)
1527                 cpsw_add_default_vlan(priv);
1528         else
1529                 cpsw_ale_add_vlan(cpsw->ale, cpsw->data.default_vlan,
1530                                   ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0);
1531
1532         /* initialize shared resources for every ndev */
1533         if (!cpsw->usage_count) {
1534                 /* disable priority elevation */
1535                 writel_relaxed(0, &cpsw->regs->ptype);
1536
1537                 /* enable statistics collection only on all ports */
1538                 writel_relaxed(0x7, &cpsw->regs->stat_port_en);
1539
1540                 /* Enable internal fifo flow control */
1541                 writel(0x7, &cpsw->regs->flow_control);
1542
1543                 napi_enable(&cpsw->napi_rx);
1544                 napi_enable(&cpsw->napi_tx);
1545
1546                 if (cpsw->tx_irq_disabled) {
1547                         cpsw->tx_irq_disabled = false;
1548                         enable_irq(cpsw->irqs_table[1]);
1549                 }
1550
1551                 if (cpsw->rx_irq_disabled) {
1552                         cpsw->rx_irq_disabled = false;
1553                         enable_irq(cpsw->irqs_table[0]);
1554                 }
1555
1556                 ret = cpsw_fill_rx_channels(priv);
1557                 if (ret < 0)
1558                         goto err_cleanup;
1559
1560                 if (cpts_register(cpsw->cpts))
1561                         dev_err(priv->dev, "error registering cpts device\n");
1562
1563         }
1564
1565         /* Enable Interrupt pacing if configured */
1566         if (cpsw->coal_intvl != 0) {
1567                 struct ethtool_coalesce coal;
1568
1569                 coal.rx_coalesce_usecs = cpsw->coal_intvl;
1570                 cpsw_set_coalesce(ndev, &coal);
1571         }
1572
1573         cpdma_ctlr_start(cpsw->dma);
1574         cpsw_intr_enable(cpsw);
1575         cpsw->usage_count++;
1576
1577         return 0;
1578
1579 err_cleanup:
1580         cpdma_ctlr_stop(cpsw->dma);
1581         for_each_slave(priv, cpsw_slave_stop, cpsw);
1582         pm_runtime_put_sync(cpsw->dev);
1583         netif_carrier_off(priv->ndev);
1584         return ret;
1585 }
1586
1587 static int cpsw_ndo_stop(struct net_device *ndev)
1588 {
1589         struct cpsw_priv *priv = netdev_priv(ndev);
1590         struct cpsw_common *cpsw = priv->cpsw;
1591
1592         cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1593         netif_tx_stop_all_queues(priv->ndev);
1594         netif_carrier_off(priv->ndev);
1595
1596         if (cpsw->usage_count <= 1) {
1597                 napi_disable(&cpsw->napi_rx);
1598                 napi_disable(&cpsw->napi_tx);
1599                 cpts_unregister(cpsw->cpts);
1600                 cpsw_intr_disable(cpsw);
1601                 cpdma_ctlr_stop(cpsw->dma);
1602                 cpsw_ale_stop(cpsw->ale);
1603         }
1604         for_each_slave(priv, cpsw_slave_stop, cpsw);
1605
1606         if (cpsw_need_resplit(cpsw))
1607                 cpsw_split_res(ndev);
1608
1609         cpsw->usage_count--;
1610         pm_runtime_put_sync(cpsw->dev);
1611         return 0;
1612 }
1613
1614 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1615                                        struct net_device *ndev)
1616 {
1617         struct cpsw_priv *priv = netdev_priv(ndev);
1618         struct cpsw_common *cpsw = priv->cpsw;
1619         struct cpts *cpts = cpsw->cpts;
1620         struct netdev_queue *txq;
1621         struct cpdma_chan *txch;
1622         int ret, q_idx;
1623
1624         if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1625                 cpsw_err(priv, tx_err, "packet pad failed\n");
1626                 ndev->stats.tx_dropped++;
1627                 return NET_XMIT_DROP;
1628         }
1629
1630         if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1631             cpts_is_tx_enabled(cpts) && cpts_can_timestamp(cpts, skb))
1632                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1633
1634         q_idx = skb_get_queue_mapping(skb);
1635         if (q_idx >= cpsw->tx_ch_num)
1636                 q_idx = q_idx % cpsw->tx_ch_num;
1637
1638         txch = cpsw->txv[q_idx].ch;
1639         txq = netdev_get_tx_queue(ndev, q_idx);
1640         ret = cpsw_tx_packet_submit(priv, skb, txch);
1641         if (unlikely(ret != 0)) {
1642                 cpsw_err(priv, tx_err, "desc submit failed\n");
1643                 goto fail;
1644         }
1645
1646         /* If there is no more tx desc left free then we need to
1647          * tell the kernel to stop sending us tx frames.
1648          */
1649         if (unlikely(!cpdma_check_free_tx_desc(txch))) {
1650                 netif_tx_stop_queue(txq);
1651
1652                 /* Barrier, so that stop_queue visible to other cpus */
1653                 smp_mb__after_atomic();
1654
1655                 if (cpdma_check_free_tx_desc(txch))
1656                         netif_tx_wake_queue(txq);
1657         }
1658
1659         return NETDEV_TX_OK;
1660 fail:
1661         ndev->stats.tx_dropped++;
1662         netif_tx_stop_queue(txq);
1663
1664         /* Barrier, so that stop_queue visible to other cpus */
1665         smp_mb__after_atomic();
1666
1667         if (cpdma_check_free_tx_desc(txch))
1668                 netif_tx_wake_queue(txq);
1669
1670         return NETDEV_TX_BUSY;
1671 }
1672
1673 #if IS_ENABLED(CONFIG_TI_CPTS)
1674
1675 static void cpsw_hwtstamp_v1(struct cpsw_common *cpsw)
1676 {
1677         struct cpsw_slave *slave = &cpsw->slaves[cpsw->data.active_slave];
1678         u32 ts_en, seq_id;
1679
1680         if (!cpts_is_tx_enabled(cpsw->cpts) &&
1681             !cpts_is_rx_enabled(cpsw->cpts)) {
1682                 slave_write(slave, 0, CPSW1_TS_CTL);
1683                 return;
1684         }
1685
1686         seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1687         ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1688
1689         if (cpts_is_tx_enabled(cpsw->cpts))
1690                 ts_en |= CPSW_V1_TS_TX_EN;
1691
1692         if (cpts_is_rx_enabled(cpsw->cpts))
1693                 ts_en |= CPSW_V1_TS_RX_EN;
1694
1695         slave_write(slave, ts_en, CPSW1_TS_CTL);
1696         slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1697 }
1698
1699 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1700 {
1701         struct cpsw_slave *slave;
1702         struct cpsw_common *cpsw = priv->cpsw;
1703         u32 ctrl, mtype;
1704
1705         slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1706
1707         ctrl = slave_read(slave, CPSW2_CONTROL);
1708         switch (cpsw->version) {
1709         case CPSW_VERSION_2:
1710                 ctrl &= ~CTRL_V2_ALL_TS_MASK;
1711
1712                 if (cpts_is_tx_enabled(cpsw->cpts))
1713                         ctrl |= CTRL_V2_TX_TS_BITS;
1714
1715                 if (cpts_is_rx_enabled(cpsw->cpts))
1716                         ctrl |= CTRL_V2_RX_TS_BITS;
1717                 break;
1718         case CPSW_VERSION_3:
1719         default:
1720                 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1721
1722                 if (cpts_is_tx_enabled(cpsw->cpts))
1723                         ctrl |= CTRL_V3_TX_TS_BITS;
1724
1725                 if (cpts_is_rx_enabled(cpsw->cpts))
1726                         ctrl |= CTRL_V3_RX_TS_BITS;
1727                 break;
1728         }
1729
1730         mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1731
1732         slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1733         slave_write(slave, ctrl, CPSW2_CONTROL);
1734         writel_relaxed(ETH_P_1588, &cpsw->regs->ts_ltype);
1735 }
1736
1737 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1738 {
1739         struct cpsw_priv *priv = netdev_priv(dev);
1740         struct hwtstamp_config cfg;
1741         struct cpsw_common *cpsw = priv->cpsw;
1742         struct cpts *cpts = cpsw->cpts;
1743
1744         if (cpsw->version != CPSW_VERSION_1 &&
1745             cpsw->version != CPSW_VERSION_2 &&
1746             cpsw->version != CPSW_VERSION_3)
1747                 return -EOPNOTSUPP;
1748
1749         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1750                 return -EFAULT;
1751
1752         /* reserved for future extensions */
1753         if (cfg.flags)
1754                 return -EINVAL;
1755
1756         if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
1757                 return -ERANGE;
1758
1759         switch (cfg.rx_filter) {
1760         case HWTSTAMP_FILTER_NONE:
1761                 cpts_rx_enable(cpts, 0);
1762                 break;
1763         case HWTSTAMP_FILTER_ALL:
1764         case HWTSTAMP_FILTER_NTP_ALL:
1765                 return -ERANGE;
1766         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1767         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1768         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1769                 cpts_rx_enable(cpts, HWTSTAMP_FILTER_PTP_V1_L4_EVENT);
1770                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
1771                 break;
1772         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1773         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1774         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1775         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1776         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1777         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1778         case HWTSTAMP_FILTER_PTP_V2_EVENT:
1779         case HWTSTAMP_FILTER_PTP_V2_SYNC:
1780         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1781                 cpts_rx_enable(cpts, HWTSTAMP_FILTER_PTP_V2_EVENT);
1782                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1783                 break;
1784         default:
1785                 return -ERANGE;
1786         }
1787
1788         cpts_tx_enable(cpts, cfg.tx_type == HWTSTAMP_TX_ON);
1789
1790         switch (cpsw->version) {
1791         case CPSW_VERSION_1:
1792                 cpsw_hwtstamp_v1(cpsw);
1793                 break;
1794         case CPSW_VERSION_2:
1795         case CPSW_VERSION_3:
1796                 cpsw_hwtstamp_v2(priv);
1797                 break;
1798         default:
1799                 WARN_ON(1);
1800         }
1801
1802         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1803 }
1804
1805 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1806 {
1807         struct cpsw_common *cpsw = ndev_to_cpsw(dev);
1808         struct cpts *cpts = cpsw->cpts;
1809         struct hwtstamp_config cfg;
1810
1811         if (cpsw->version != CPSW_VERSION_1 &&
1812             cpsw->version != CPSW_VERSION_2 &&
1813             cpsw->version != CPSW_VERSION_3)
1814                 return -EOPNOTSUPP;
1815
1816         cfg.flags = 0;
1817         cfg.tx_type = cpts_is_tx_enabled(cpts) ?
1818                       HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1819         cfg.rx_filter = (cpts_is_rx_enabled(cpts) ?
1820                          cpts->rx_enable : HWTSTAMP_FILTER_NONE);
1821
1822         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1823 }
1824 #else
1825 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1826 {
1827         return -EOPNOTSUPP;
1828 }
1829
1830 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1831 {
1832         return -EOPNOTSUPP;
1833 }
1834 #endif /*CONFIG_TI_CPTS*/
1835
1836 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1837 {
1838         struct cpsw_priv *priv = netdev_priv(dev);
1839         struct cpsw_common *cpsw = priv->cpsw;
1840         int slave_no = cpsw_slave_index(cpsw, priv);
1841
1842         if (!netif_running(dev))
1843                 return -EINVAL;
1844
1845         switch (cmd) {
1846         case SIOCSHWTSTAMP:
1847                 return cpsw_hwtstamp_set(dev, req);
1848         case SIOCGHWTSTAMP:
1849                 return cpsw_hwtstamp_get(dev, req);
1850         }
1851
1852         if (!cpsw->slaves[slave_no].phy)
1853                 return -EOPNOTSUPP;
1854         return phy_mii_ioctl(cpsw->slaves[slave_no].phy, req, cmd);
1855 }
1856
1857 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1858 {
1859         struct cpsw_priv *priv = netdev_priv(ndev);
1860         struct cpsw_common *cpsw = priv->cpsw;
1861         int ch;
1862
1863         cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1864         ndev->stats.tx_errors++;
1865         cpsw_intr_disable(cpsw);
1866         for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
1867                 cpdma_chan_stop(cpsw->txv[ch].ch);
1868                 cpdma_chan_start(cpsw->txv[ch].ch);
1869         }
1870
1871         cpsw_intr_enable(cpsw);
1872         netif_trans_update(ndev);
1873         netif_tx_wake_all_queues(ndev);
1874 }
1875
1876 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1877 {
1878         struct cpsw_priv *priv = netdev_priv(ndev);
1879         struct sockaddr *addr = (struct sockaddr *)p;
1880         struct cpsw_common *cpsw = priv->cpsw;
1881         int flags = 0;
1882         u16 vid = 0;
1883         int ret;
1884
1885         if (!is_valid_ether_addr(addr->sa_data))
1886                 return -EADDRNOTAVAIL;
1887
1888         ret = pm_runtime_get_sync(cpsw->dev);
1889         if (ret < 0) {
1890                 pm_runtime_put_noidle(cpsw->dev);
1891                 return ret;
1892         }
1893
1894         if (cpsw->data.dual_emac) {
1895                 vid = cpsw->slaves[priv->emac_port].port_vlan;
1896                 flags = ALE_VLAN;
1897         }
1898
1899         cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
1900                            flags, vid);
1901         cpsw_ale_add_ucast(cpsw->ale, addr->sa_data, HOST_PORT_NUM,
1902                            flags, vid);
1903
1904         memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1905         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1906         for_each_slave(priv, cpsw_set_slave_mac, priv);
1907
1908         pm_runtime_put(cpsw->dev);
1909
1910         return 0;
1911 }
1912
1913 #ifdef CONFIG_NET_POLL_CONTROLLER
1914 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1915 {
1916         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1917
1918         cpsw_intr_disable(cpsw);
1919         cpsw_rx_interrupt(cpsw->irqs_table[0], cpsw);
1920         cpsw_tx_interrupt(cpsw->irqs_table[1], cpsw);
1921         cpsw_intr_enable(cpsw);
1922 }
1923 #endif
1924
1925 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1926                                 unsigned short vid)
1927 {
1928         int ret;
1929         int unreg_mcast_mask = 0;
1930         u32 port_mask;
1931         struct cpsw_common *cpsw = priv->cpsw;
1932
1933         if (cpsw->data.dual_emac) {
1934                 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
1935
1936                 if (priv->ndev->flags & IFF_ALLMULTI)
1937                         unreg_mcast_mask = port_mask;
1938         } else {
1939                 port_mask = ALE_ALL_PORTS;
1940
1941                 if (priv->ndev->flags & IFF_ALLMULTI)
1942                         unreg_mcast_mask = ALE_ALL_PORTS;
1943                 else
1944                         unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1945         }
1946
1947         ret = cpsw_ale_add_vlan(cpsw->ale, vid, port_mask, 0, port_mask,
1948                                 unreg_mcast_mask);
1949         if (ret != 0)
1950                 return ret;
1951
1952         ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
1953                                  HOST_PORT_NUM, ALE_VLAN, vid);
1954         if (ret != 0)
1955                 goto clean_vid;
1956
1957         ret = cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1958                                  port_mask, ALE_VLAN, vid, 0);
1959         if (ret != 0)
1960                 goto clean_vlan_ucast;
1961         return 0;
1962
1963 clean_vlan_ucast:
1964         cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
1965                            HOST_PORT_NUM, ALE_VLAN, vid);
1966 clean_vid:
1967         cpsw_ale_del_vlan(cpsw->ale, vid, 0);
1968         return ret;
1969 }
1970
1971 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1972                                     __be16 proto, u16 vid)
1973 {
1974         struct cpsw_priv *priv = netdev_priv(ndev);
1975         struct cpsw_common *cpsw = priv->cpsw;
1976         int ret;
1977
1978         if (vid == cpsw->data.default_vlan)
1979                 return 0;
1980
1981         ret = pm_runtime_get_sync(cpsw->dev);
1982         if (ret < 0) {
1983                 pm_runtime_put_noidle(cpsw->dev);
1984                 return ret;
1985         }
1986
1987         if (cpsw->data.dual_emac) {
1988                 /* In dual EMAC, reserved VLAN id should not be used for
1989                  * creating VLAN interfaces as this can break the dual
1990                  * EMAC port separation
1991                  */
1992                 int i;
1993
1994                 for (i = 0; i < cpsw->data.slaves; i++) {
1995                         if (vid == cpsw->slaves[i].port_vlan)
1996                                 return -EINVAL;
1997                 }
1998         }
1999
2000         dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
2001         ret = cpsw_add_vlan_ale_entry(priv, vid);
2002
2003         pm_runtime_put(cpsw->dev);
2004         return ret;
2005 }
2006
2007 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
2008                                      __be16 proto, u16 vid)
2009 {
2010         struct cpsw_priv *priv = netdev_priv(ndev);
2011         struct cpsw_common *cpsw = priv->cpsw;
2012         int ret;
2013
2014         if (vid == cpsw->data.default_vlan)
2015                 return 0;
2016
2017         ret = pm_runtime_get_sync(cpsw->dev);
2018         if (ret < 0) {
2019                 pm_runtime_put_noidle(cpsw->dev);
2020                 return ret;
2021         }
2022
2023         if (cpsw->data.dual_emac) {
2024                 int i;
2025
2026                 for (i = 0; i < cpsw->data.slaves; i++) {
2027                         if (vid == cpsw->slaves[i].port_vlan)
2028                                 return -EINVAL;
2029                 }
2030         }
2031
2032         dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
2033         ret = cpsw_ale_del_vlan(cpsw->ale, vid, 0);
2034         if (ret != 0)
2035                 return ret;
2036
2037         ret = cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
2038                                  HOST_PORT_NUM, ALE_VLAN, vid);
2039         if (ret != 0)
2040                 return ret;
2041
2042         ret = cpsw_ale_del_mcast(cpsw->ale, priv->ndev->broadcast,
2043                                  0, ALE_VLAN, vid);
2044         pm_runtime_put(cpsw->dev);
2045         return ret;
2046 }
2047
2048 static int cpsw_ndo_set_tx_maxrate(struct net_device *ndev, int queue, u32 rate)
2049 {
2050         struct cpsw_priv *priv = netdev_priv(ndev);
2051         struct cpsw_common *cpsw = priv->cpsw;
2052         struct cpsw_slave *slave;
2053         u32 min_rate;
2054         u32 ch_rate;
2055         int i, ret;
2056
2057         ch_rate = netdev_get_tx_queue(ndev, queue)->tx_maxrate;
2058         if (ch_rate == rate)
2059                 return 0;
2060
2061         ch_rate = rate * 1000;
2062         min_rate = cpdma_chan_get_min_rate(cpsw->dma);
2063         if ((ch_rate < min_rate && ch_rate)) {
2064                 dev_err(priv->dev, "The channel rate cannot be less than %dMbps",
2065                         min_rate);
2066                 return -EINVAL;
2067         }
2068
2069         if (rate > cpsw->speed) {
2070                 dev_err(priv->dev, "The channel rate cannot be more than 2Gbps");
2071                 return -EINVAL;
2072         }
2073
2074         ret = pm_runtime_get_sync(cpsw->dev);
2075         if (ret < 0) {
2076                 pm_runtime_put_noidle(cpsw->dev);
2077                 return ret;
2078         }
2079
2080         ret = cpdma_chan_set_rate(cpsw->txv[queue].ch, ch_rate);
2081         pm_runtime_put(cpsw->dev);
2082
2083         if (ret)
2084                 return ret;
2085
2086         /* update rates for slaves tx queues */
2087         for (i = 0; i < cpsw->data.slaves; i++) {
2088                 slave = &cpsw->slaves[i];
2089                 if (!slave->ndev)
2090                         continue;
2091
2092                 netdev_get_tx_queue(slave->ndev, queue)->tx_maxrate = rate;
2093         }
2094
2095         cpsw_split_res(ndev);
2096         return ret;
2097 }
2098
2099 static const struct net_device_ops cpsw_netdev_ops = {
2100         .ndo_open               = cpsw_ndo_open,
2101         .ndo_stop               = cpsw_ndo_stop,
2102         .ndo_start_xmit         = cpsw_ndo_start_xmit,
2103         .ndo_set_mac_address    = cpsw_ndo_set_mac_address,
2104         .ndo_do_ioctl           = cpsw_ndo_ioctl,
2105         .ndo_validate_addr      = eth_validate_addr,
2106         .ndo_tx_timeout         = cpsw_ndo_tx_timeout,
2107         .ndo_set_rx_mode        = cpsw_ndo_set_rx_mode,
2108         .ndo_set_tx_maxrate     = cpsw_ndo_set_tx_maxrate,
2109 #ifdef CONFIG_NET_POLL_CONTROLLER
2110         .ndo_poll_controller    = cpsw_ndo_poll_controller,
2111 #endif
2112         .ndo_vlan_rx_add_vid    = cpsw_ndo_vlan_rx_add_vid,
2113         .ndo_vlan_rx_kill_vid   = cpsw_ndo_vlan_rx_kill_vid,
2114 };
2115
2116 static int cpsw_get_regs_len(struct net_device *ndev)
2117 {
2118         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2119
2120         return cpsw->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
2121 }
2122
2123 static void cpsw_get_regs(struct net_device *ndev,
2124                           struct ethtool_regs *regs, void *p)
2125 {
2126         u32 *reg = p;
2127         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2128
2129         /* update CPSW IP version */
2130         regs->version = cpsw->version;
2131
2132         cpsw_ale_dump(cpsw->ale, reg);
2133 }
2134
2135 static void cpsw_get_drvinfo(struct net_device *ndev,
2136                              struct ethtool_drvinfo *info)
2137 {
2138         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2139         struct platform_device  *pdev = to_platform_device(cpsw->dev);
2140
2141         strlcpy(info->driver, "cpsw", sizeof(info->driver));
2142         strlcpy(info->version, "1.0", sizeof(info->version));
2143         strlcpy(info->bus_info, pdev->name, sizeof(info->bus_info));
2144 }
2145
2146 static u32 cpsw_get_msglevel(struct net_device *ndev)
2147 {
2148         struct cpsw_priv *priv = netdev_priv(ndev);
2149         return priv->msg_enable;
2150 }
2151
2152 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
2153 {
2154         struct cpsw_priv *priv = netdev_priv(ndev);
2155         priv->msg_enable = value;
2156 }
2157
2158 #if IS_ENABLED(CONFIG_TI_CPTS)
2159 static int cpsw_get_ts_info(struct net_device *ndev,
2160                             struct ethtool_ts_info *info)
2161 {
2162         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2163
2164         info->so_timestamping =
2165                 SOF_TIMESTAMPING_TX_HARDWARE |
2166                 SOF_TIMESTAMPING_TX_SOFTWARE |
2167                 SOF_TIMESTAMPING_RX_HARDWARE |
2168                 SOF_TIMESTAMPING_RX_SOFTWARE |
2169                 SOF_TIMESTAMPING_SOFTWARE |
2170                 SOF_TIMESTAMPING_RAW_HARDWARE;
2171         info->phc_index = cpsw->cpts->phc_index;
2172         info->tx_types =
2173                 (1 << HWTSTAMP_TX_OFF) |
2174                 (1 << HWTSTAMP_TX_ON);
2175         info->rx_filters =
2176                 (1 << HWTSTAMP_FILTER_NONE) |
2177                 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
2178                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2179         return 0;
2180 }
2181 #else
2182 static int cpsw_get_ts_info(struct net_device *ndev,
2183                             struct ethtool_ts_info *info)
2184 {
2185         info->so_timestamping =
2186                 SOF_TIMESTAMPING_TX_SOFTWARE |
2187                 SOF_TIMESTAMPING_RX_SOFTWARE |
2188                 SOF_TIMESTAMPING_SOFTWARE;
2189         info->phc_index = -1;
2190         info->tx_types = 0;
2191         info->rx_filters = 0;
2192         return 0;
2193 }
2194 #endif
2195
2196 static int cpsw_get_link_ksettings(struct net_device *ndev,
2197                                    struct ethtool_link_ksettings *ecmd)
2198 {
2199         struct cpsw_priv *priv = netdev_priv(ndev);
2200         struct cpsw_common *cpsw = priv->cpsw;
2201         int slave_no = cpsw_slave_index(cpsw, priv);
2202
2203         if (!cpsw->slaves[slave_no].phy)
2204                 return -EOPNOTSUPP;
2205
2206         phy_ethtool_ksettings_get(cpsw->slaves[slave_no].phy, ecmd);
2207         return 0;
2208 }
2209
2210 static int cpsw_set_link_ksettings(struct net_device *ndev,
2211                                    const struct ethtool_link_ksettings *ecmd)
2212 {
2213         struct cpsw_priv *priv = netdev_priv(ndev);
2214         struct cpsw_common *cpsw = priv->cpsw;
2215         int slave_no = cpsw_slave_index(cpsw, priv);
2216
2217         if (cpsw->slaves[slave_no].phy)
2218                 return phy_ethtool_ksettings_set(cpsw->slaves[slave_no].phy,
2219                                                  ecmd);
2220         else
2221                 return -EOPNOTSUPP;
2222 }
2223
2224 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2225 {
2226         struct cpsw_priv *priv = netdev_priv(ndev);
2227         struct cpsw_common *cpsw = priv->cpsw;
2228         int slave_no = cpsw_slave_index(cpsw, priv);
2229
2230         wol->supported = 0;
2231         wol->wolopts = 0;
2232
2233         if (cpsw->slaves[slave_no].phy)
2234                 phy_ethtool_get_wol(cpsw->slaves[slave_no].phy, wol);
2235 }
2236
2237 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2238 {
2239         struct cpsw_priv *priv = netdev_priv(ndev);
2240         struct cpsw_common *cpsw = priv->cpsw;
2241         int slave_no = cpsw_slave_index(cpsw, priv);
2242
2243         if (cpsw->slaves[slave_no].phy)
2244                 return phy_ethtool_set_wol(cpsw->slaves[slave_no].phy, wol);
2245         else
2246                 return -EOPNOTSUPP;
2247 }
2248
2249 static void cpsw_get_pauseparam(struct net_device *ndev,
2250                                 struct ethtool_pauseparam *pause)
2251 {
2252         struct cpsw_priv *priv = netdev_priv(ndev);
2253
2254         pause->autoneg = AUTONEG_DISABLE;
2255         pause->rx_pause = priv->rx_pause ? true : false;
2256         pause->tx_pause = priv->tx_pause ? true : false;
2257 }
2258
2259 static int cpsw_set_pauseparam(struct net_device *ndev,
2260                                struct ethtool_pauseparam *pause)
2261 {
2262         struct cpsw_priv *priv = netdev_priv(ndev);
2263         bool link;
2264
2265         priv->rx_pause = pause->rx_pause ? true : false;
2266         priv->tx_pause = pause->tx_pause ? true : false;
2267
2268         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
2269         return 0;
2270 }
2271
2272 static int cpsw_ethtool_op_begin(struct net_device *ndev)
2273 {
2274         struct cpsw_priv *priv = netdev_priv(ndev);
2275         struct cpsw_common *cpsw = priv->cpsw;
2276         int ret;
2277
2278         ret = pm_runtime_get_sync(cpsw->dev);
2279         if (ret < 0) {
2280                 cpsw_err(priv, drv, "ethtool begin failed %d\n", ret);
2281                 pm_runtime_put_noidle(cpsw->dev);
2282         }
2283
2284         return ret;
2285 }
2286
2287 static void cpsw_ethtool_op_complete(struct net_device *ndev)
2288 {
2289         struct cpsw_priv *priv = netdev_priv(ndev);
2290         int ret;
2291
2292         ret = pm_runtime_put(priv->cpsw->dev);
2293         if (ret < 0)
2294                 cpsw_err(priv, drv, "ethtool complete failed %d\n", ret);
2295 }
2296
2297 static void cpsw_get_channels(struct net_device *ndev,
2298                               struct ethtool_channels *ch)
2299 {
2300         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2301
2302         ch->max_combined = 0;
2303         ch->max_rx = CPSW_MAX_QUEUES;
2304         ch->max_tx = CPSW_MAX_QUEUES;
2305         ch->max_other = 0;
2306         ch->other_count = 0;
2307         ch->rx_count = cpsw->rx_ch_num;
2308         ch->tx_count = cpsw->tx_ch_num;
2309         ch->combined_count = 0;
2310 }
2311
2312 static int cpsw_check_ch_settings(struct cpsw_common *cpsw,
2313                                   struct ethtool_channels *ch)
2314 {
2315         if (ch->combined_count)
2316                 return -EINVAL;
2317
2318         /* verify we have at least one channel in each direction */
2319         if (!ch->rx_count || !ch->tx_count)
2320                 return -EINVAL;
2321
2322         if (ch->rx_count > cpsw->data.channels ||
2323             ch->tx_count > cpsw->data.channels)
2324                 return -EINVAL;
2325
2326         return 0;
2327 }
2328
2329 static int cpsw_update_channels_res(struct cpsw_priv *priv, int ch_num, int rx)
2330 {
2331         struct cpsw_common *cpsw = priv->cpsw;
2332         void (*handler)(void *, int, int);
2333         struct netdev_queue *queue;
2334         struct cpsw_vector *vec;
2335         int ret, *ch;
2336
2337         if (rx) {
2338                 ch = &cpsw->rx_ch_num;
2339                 vec = cpsw->rxv;
2340                 handler = cpsw_rx_handler;
2341         } else {
2342                 ch = &cpsw->tx_ch_num;
2343                 vec = cpsw->txv;
2344                 handler = cpsw_tx_handler;
2345         }
2346
2347         while (*ch < ch_num) {
2348                 vec[*ch].ch = cpdma_chan_create(cpsw->dma, *ch, handler, rx);
2349                 queue = netdev_get_tx_queue(priv->ndev, *ch);
2350                 queue->tx_maxrate = 0;
2351
2352                 if (IS_ERR(vec[*ch].ch))
2353                         return PTR_ERR(vec[*ch].ch);
2354
2355                 if (!vec[*ch].ch)
2356                         return -EINVAL;
2357
2358                 cpsw_info(priv, ifup, "created new %d %s channel\n", *ch,
2359                           (rx ? "rx" : "tx"));
2360                 (*ch)++;
2361         }
2362
2363         while (*ch > ch_num) {
2364                 (*ch)--;
2365
2366                 ret = cpdma_chan_destroy(vec[*ch].ch);
2367                 if (ret)
2368                         return ret;
2369
2370                 cpsw_info(priv, ifup, "destroyed %d %s channel\n", *ch,
2371                           (rx ? "rx" : "tx"));
2372         }
2373
2374         return 0;
2375 }
2376
2377 static int cpsw_update_channels(struct cpsw_priv *priv,
2378                                 struct ethtool_channels *ch)
2379 {
2380         int ret;
2381
2382         ret = cpsw_update_channels_res(priv, ch->rx_count, 1);
2383         if (ret)
2384                 return ret;
2385
2386         ret = cpsw_update_channels_res(priv, ch->tx_count, 0);
2387         if (ret)
2388                 return ret;
2389
2390         return 0;
2391 }
2392
2393 static void cpsw_suspend_data_pass(struct net_device *ndev)
2394 {
2395         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2396         struct cpsw_slave *slave;
2397         int i;
2398
2399         /* Disable NAPI scheduling */
2400         cpsw_intr_disable(cpsw);
2401
2402         /* Stop all transmit queues for every network device.
2403          * Disable re-using rx descriptors with dormant_on.
2404          */
2405         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2406                 if (!(slave->ndev && netif_running(slave->ndev)))
2407                         continue;
2408
2409                 netif_tx_stop_all_queues(slave->ndev);
2410                 netif_dormant_on(slave->ndev);
2411         }
2412
2413         /* Handle rest of tx packets and stop cpdma channels */
2414         cpdma_ctlr_stop(cpsw->dma);
2415 }
2416
2417 static int cpsw_resume_data_pass(struct net_device *ndev)
2418 {
2419         struct cpsw_priv *priv = netdev_priv(ndev);
2420         struct cpsw_common *cpsw = priv->cpsw;
2421         struct cpsw_slave *slave;
2422         int i, ret;
2423
2424         /* Allow rx packets handling */
2425         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++)
2426                 if (slave->ndev && netif_running(slave->ndev))
2427                         netif_dormant_off(slave->ndev);
2428
2429         /* After this receive is started */
2430         if (cpsw->usage_count) {
2431                 ret = cpsw_fill_rx_channels(priv);
2432                 if (ret)
2433                         return ret;
2434
2435                 cpdma_ctlr_start(cpsw->dma);
2436                 cpsw_intr_enable(cpsw);
2437         }
2438
2439         /* Resume transmit for every affected interface */
2440         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++)
2441                 if (slave->ndev && netif_running(slave->ndev))
2442                         netif_tx_start_all_queues(slave->ndev);
2443
2444         return 0;
2445 }
2446
2447 static int cpsw_set_channels(struct net_device *ndev,
2448                              struct ethtool_channels *chs)
2449 {
2450         struct cpsw_priv *priv = netdev_priv(ndev);
2451         struct cpsw_common *cpsw = priv->cpsw;
2452         struct cpsw_slave *slave;
2453         int i, ret;
2454
2455         ret = cpsw_check_ch_settings(cpsw, chs);
2456         if (ret < 0)
2457                 return ret;
2458
2459         cpsw_suspend_data_pass(ndev);
2460         ret = cpsw_update_channels(priv, chs);
2461         if (ret)
2462                 goto err;
2463
2464         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2465                 if (!(slave->ndev && netif_running(slave->ndev)))
2466                         continue;
2467
2468                 /* Inform stack about new count of queues */
2469                 ret = netif_set_real_num_tx_queues(slave->ndev,
2470                                                    cpsw->tx_ch_num);
2471                 if (ret) {
2472                         dev_err(priv->dev, "cannot set real number of tx queues\n");
2473                         goto err;
2474                 }
2475
2476                 ret = netif_set_real_num_rx_queues(slave->ndev,
2477                                                    cpsw->rx_ch_num);
2478                 if (ret) {
2479                         dev_err(priv->dev, "cannot set real number of rx queues\n");
2480                         goto err;
2481                 }
2482         }
2483
2484         if (cpsw->usage_count)
2485                 cpsw_split_res(ndev);
2486
2487         ret = cpsw_resume_data_pass(ndev);
2488         if (!ret)
2489                 return 0;
2490 err:
2491         dev_err(priv->dev, "cannot update channels number, closing device\n");
2492         dev_close(ndev);
2493         return ret;
2494 }
2495
2496 static int cpsw_get_eee(struct net_device *ndev, struct ethtool_eee *edata)
2497 {
2498         struct cpsw_priv *priv = netdev_priv(ndev);
2499         struct cpsw_common *cpsw = priv->cpsw;
2500         int slave_no = cpsw_slave_index(cpsw, priv);
2501
2502         if (cpsw->slaves[slave_no].phy)
2503                 return phy_ethtool_get_eee(cpsw->slaves[slave_no].phy, edata);
2504         else
2505                 return -EOPNOTSUPP;
2506 }
2507
2508 static int cpsw_set_eee(struct net_device *ndev, struct ethtool_eee *edata)
2509 {
2510         struct cpsw_priv *priv = netdev_priv(ndev);
2511         struct cpsw_common *cpsw = priv->cpsw;
2512         int slave_no = cpsw_slave_index(cpsw, priv);
2513
2514         if (cpsw->slaves[slave_no].phy)
2515                 return phy_ethtool_set_eee(cpsw->slaves[slave_no].phy, edata);
2516         else
2517                 return -EOPNOTSUPP;
2518 }
2519
2520 static int cpsw_nway_reset(struct net_device *ndev)
2521 {
2522         struct cpsw_priv *priv = netdev_priv(ndev);
2523         struct cpsw_common *cpsw = priv->cpsw;
2524         int slave_no = cpsw_slave_index(cpsw, priv);
2525
2526         if (cpsw->slaves[slave_no].phy)
2527                 return genphy_restart_aneg(cpsw->slaves[slave_no].phy);
2528         else
2529                 return -EOPNOTSUPP;
2530 }
2531
2532 static void cpsw_get_ringparam(struct net_device *ndev,
2533                                struct ethtool_ringparam *ering)
2534 {
2535         struct cpsw_priv *priv = netdev_priv(ndev);
2536         struct cpsw_common *cpsw = priv->cpsw;
2537
2538         /* not supported */
2539         ering->tx_max_pending = 0;
2540         ering->tx_pending = cpdma_get_num_tx_descs(cpsw->dma);
2541         ering->rx_max_pending = descs_pool_size - CPSW_MAX_QUEUES;
2542         ering->rx_pending = cpdma_get_num_rx_descs(cpsw->dma);
2543 }
2544
2545 static int cpsw_set_ringparam(struct net_device *ndev,
2546                               struct ethtool_ringparam *ering)
2547 {
2548         struct cpsw_priv *priv = netdev_priv(ndev);
2549         struct cpsw_common *cpsw = priv->cpsw;
2550         int ret;
2551
2552         /* ignore ering->tx_pending - only rx_pending adjustment is supported */
2553
2554         if (ering->rx_mini_pending || ering->rx_jumbo_pending ||
2555             ering->rx_pending < CPSW_MAX_QUEUES ||
2556             ering->rx_pending > (descs_pool_size - CPSW_MAX_QUEUES))
2557                 return -EINVAL;
2558
2559         if (ering->rx_pending == cpdma_get_num_rx_descs(cpsw->dma))
2560                 return 0;
2561
2562         cpsw_suspend_data_pass(ndev);
2563
2564         cpdma_set_num_rx_descs(cpsw->dma, ering->rx_pending);
2565
2566         if (cpsw->usage_count)
2567                 cpdma_chan_split_pool(cpsw->dma);
2568
2569         ret = cpsw_resume_data_pass(ndev);
2570         if (!ret)
2571                 return 0;
2572
2573         dev_err(&ndev->dev, "cannot set ring params, closing device\n");
2574         dev_close(ndev);
2575         return ret;
2576 }
2577
2578 static const struct ethtool_ops cpsw_ethtool_ops = {
2579         .get_drvinfo    = cpsw_get_drvinfo,
2580         .get_msglevel   = cpsw_get_msglevel,
2581         .set_msglevel   = cpsw_set_msglevel,
2582         .get_link       = ethtool_op_get_link,
2583         .get_ts_info    = cpsw_get_ts_info,
2584         .get_coalesce   = cpsw_get_coalesce,
2585         .set_coalesce   = cpsw_set_coalesce,
2586         .get_sset_count         = cpsw_get_sset_count,
2587         .get_strings            = cpsw_get_strings,
2588         .get_ethtool_stats      = cpsw_get_ethtool_stats,
2589         .get_pauseparam         = cpsw_get_pauseparam,
2590         .set_pauseparam         = cpsw_set_pauseparam,
2591         .get_wol        = cpsw_get_wol,
2592         .set_wol        = cpsw_set_wol,
2593         .get_regs_len   = cpsw_get_regs_len,
2594         .get_regs       = cpsw_get_regs,
2595         .begin          = cpsw_ethtool_op_begin,
2596         .complete       = cpsw_ethtool_op_complete,
2597         .get_channels   = cpsw_get_channels,
2598         .set_channels   = cpsw_set_channels,
2599         .get_link_ksettings     = cpsw_get_link_ksettings,
2600         .set_link_ksettings     = cpsw_set_link_ksettings,
2601         .get_eee        = cpsw_get_eee,
2602         .set_eee        = cpsw_set_eee,
2603         .nway_reset     = cpsw_nway_reset,
2604         .get_ringparam = cpsw_get_ringparam,
2605         .set_ringparam = cpsw_set_ringparam,
2606 };
2607
2608 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_common *cpsw,
2609                             u32 slave_reg_ofs, u32 sliver_reg_ofs)
2610 {
2611         void __iomem            *regs = cpsw->regs;
2612         int                     slave_num = slave->slave_num;
2613         struct cpsw_slave_data  *data = cpsw->data.slave_data + slave_num;
2614
2615         slave->data     = data;
2616         slave->regs     = regs + slave_reg_ofs;
2617         slave->sliver   = regs + sliver_reg_ofs;
2618         slave->port_vlan = data->dual_emac_res_vlan;
2619 }
2620
2621 static int cpsw_probe_dt(struct cpsw_platform_data *data,
2622                          struct platform_device *pdev)
2623 {
2624         struct device_node *node = pdev->dev.of_node;
2625         struct device_node *slave_node;
2626         int i = 0, ret;
2627         u32 prop;
2628
2629         if (!node)
2630                 return -EINVAL;
2631
2632         if (of_property_read_u32(node, "slaves", &prop)) {
2633                 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
2634                 return -EINVAL;
2635         }
2636         data->slaves = prop;
2637
2638         if (of_property_read_u32(node, "active_slave", &prop)) {
2639                 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
2640                 return -EINVAL;
2641         }
2642         data->active_slave = prop;
2643
2644         data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
2645                                         * sizeof(struct cpsw_slave_data),
2646                                         GFP_KERNEL);
2647         if (!data->slave_data)
2648                 return -ENOMEM;
2649
2650         if (of_property_read_u32(node, "cpdma_channels", &prop)) {
2651                 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
2652                 return -EINVAL;
2653         }
2654         data->channels = prop;
2655
2656         if (of_property_read_u32(node, "ale_entries", &prop)) {
2657                 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
2658                 return -EINVAL;
2659         }
2660         data->ale_entries = prop;
2661
2662         if (of_property_read_u32(node, "bd_ram_size", &prop)) {
2663                 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
2664                 return -EINVAL;
2665         }
2666         data->bd_ram_size = prop;
2667
2668         if (of_property_read_u32(node, "mac_control", &prop)) {
2669                 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
2670                 return -EINVAL;
2671         }
2672         data->mac_control = prop;
2673
2674         if (of_property_read_bool(node, "dual_emac"))
2675                 data->dual_emac = 1;
2676
2677         /*
2678          * Populate all the child nodes here...
2679          */
2680         ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2681         /* We do not want to force this, as in some cases may not have child */
2682         if (ret)
2683                 dev_warn(&pdev->dev, "Doesn't have any child node\n");
2684
2685         for_each_available_child_of_node(node, slave_node) {
2686                 struct cpsw_slave_data *slave_data = data->slave_data + i;
2687                 const void *mac_addr = NULL;
2688                 int lenp;
2689                 const __be32 *parp;
2690
2691                 /* This is no slave child node, continue */
2692                 if (strcmp(slave_node->name, "slave"))
2693                         continue;
2694
2695                 slave_data->phy_node = of_parse_phandle(slave_node,
2696                                                         "phy-handle", 0);
2697                 parp = of_get_property(slave_node, "phy_id", &lenp);
2698                 if (slave_data->phy_node) {
2699                         dev_dbg(&pdev->dev,
2700                                 "slave[%d] using phy-handle=\"%pOF\"\n",
2701                                 i, slave_data->phy_node);
2702                 } else if (of_phy_is_fixed_link(slave_node)) {
2703                         /* In the case of a fixed PHY, the DT node associated
2704                          * to the PHY is the Ethernet MAC DT node.
2705                          */
2706                         ret = of_phy_register_fixed_link(slave_node);
2707                         if (ret) {
2708                                 if (ret != -EPROBE_DEFER)
2709                                         dev_err(&pdev->dev, "failed to register fixed-link phy: %d\n", ret);
2710                                 return ret;
2711                         }
2712                         slave_data->phy_node = of_node_get(slave_node);
2713                 } else if (parp) {
2714                         u32 phyid;
2715                         struct device_node *mdio_node;
2716                         struct platform_device *mdio;
2717
2718                         if (lenp != (sizeof(__be32) * 2)) {
2719                                 dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i);
2720                                 goto no_phy_slave;
2721                         }
2722                         mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2723                         phyid = be32_to_cpup(parp+1);
2724                         mdio = of_find_device_by_node(mdio_node);
2725                         of_node_put(mdio_node);
2726                         if (!mdio) {
2727                                 dev_err(&pdev->dev, "Missing mdio platform device\n");
2728                                 return -EINVAL;
2729                         }
2730                         snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2731                                  PHY_ID_FMT, mdio->name, phyid);
2732                         put_device(&mdio->dev);
2733                 } else {
2734                         dev_err(&pdev->dev,
2735                                 "No slave[%d] phy_id, phy-handle, or fixed-link property\n",
2736                                 i);
2737                         goto no_phy_slave;
2738                 }
2739                 slave_data->phy_if = of_get_phy_mode(slave_node);
2740                 if (slave_data->phy_if < 0) {
2741                         dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2742                                 i);
2743                         return slave_data->phy_if;
2744                 }
2745
2746 no_phy_slave:
2747                 mac_addr = of_get_mac_address(slave_node);
2748                 if (mac_addr) {
2749                         memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
2750                 } else {
2751                         ret = ti_cm_get_macid(&pdev->dev, i,
2752                                               slave_data->mac_addr);
2753                         if (ret)
2754                                 return ret;
2755                 }
2756                 if (data->dual_emac) {
2757                         if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
2758                                                  &prop)) {
2759                                 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
2760                                 slave_data->dual_emac_res_vlan = i+1;
2761                                 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2762                                         slave_data->dual_emac_res_vlan, i);
2763                         } else {
2764                                 slave_data->dual_emac_res_vlan = prop;
2765                         }
2766                 }
2767
2768                 i++;
2769                 if (i == data->slaves)
2770                         break;
2771         }
2772
2773         return 0;
2774 }
2775
2776 static void cpsw_remove_dt(struct platform_device *pdev)
2777 {
2778         struct net_device *ndev = platform_get_drvdata(pdev);
2779         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2780         struct cpsw_platform_data *data = &cpsw->data;
2781         struct device_node *node = pdev->dev.of_node;
2782         struct device_node *slave_node;
2783         int i = 0;
2784
2785         for_each_available_child_of_node(node, slave_node) {
2786                 struct cpsw_slave_data *slave_data = &data->slave_data[i];
2787
2788                 if (strcmp(slave_node->name, "slave"))
2789                         continue;
2790
2791                 if (of_phy_is_fixed_link(slave_node))
2792                         of_phy_deregister_fixed_link(slave_node);
2793
2794                 of_node_put(slave_data->phy_node);
2795
2796                 i++;
2797                 if (i == data->slaves)
2798                         break;
2799         }
2800
2801         of_platform_depopulate(&pdev->dev);
2802 }
2803
2804 static int cpsw_probe_dual_emac(struct cpsw_priv *priv)
2805 {
2806         struct cpsw_common              *cpsw = priv->cpsw;
2807         struct cpsw_platform_data       *data = &cpsw->data;
2808         struct net_device               *ndev;
2809         struct cpsw_priv                *priv_sl2;
2810         int ret = 0;
2811
2812         ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
2813         if (!ndev) {
2814                 dev_err(cpsw->dev, "cpsw: error allocating net_device\n");
2815                 return -ENOMEM;
2816         }
2817
2818         priv_sl2 = netdev_priv(ndev);
2819         priv_sl2->cpsw = cpsw;
2820         priv_sl2->ndev = ndev;
2821         priv_sl2->dev  = &ndev->dev;
2822         priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2823
2824         if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2825                 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2826                         ETH_ALEN);
2827                 dev_info(cpsw->dev, "cpsw: Detected MACID = %pM\n",
2828                          priv_sl2->mac_addr);
2829         } else {
2830                 random_ether_addr(priv_sl2->mac_addr);
2831                 dev_info(cpsw->dev, "cpsw: Random MACID = %pM\n",
2832                          priv_sl2->mac_addr);
2833         }
2834         memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2835
2836         priv_sl2->emac_port = 1;
2837         cpsw->slaves[1].ndev = ndev;
2838         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2839
2840         ndev->netdev_ops = &cpsw_netdev_ops;
2841         ndev->ethtool_ops = &cpsw_ethtool_ops;
2842
2843         /* register the network device */
2844         SET_NETDEV_DEV(ndev, cpsw->dev);
2845         ret = register_netdev(ndev);
2846         if (ret) {
2847                 dev_err(cpsw->dev, "cpsw: error registering net device\n");
2848                 free_netdev(ndev);
2849                 ret = -ENODEV;
2850         }
2851
2852         return ret;
2853 }
2854
2855 #define CPSW_QUIRK_IRQ          BIT(0)
2856
2857 static const struct platform_device_id cpsw_devtype[] = {
2858         {
2859                 /* keep it for existing comaptibles */
2860                 .name = "cpsw",
2861                 .driver_data = CPSW_QUIRK_IRQ,
2862         }, {
2863                 .name = "am335x-cpsw",
2864                 .driver_data = CPSW_QUIRK_IRQ,
2865         }, {
2866                 .name = "am4372-cpsw",
2867                 .driver_data = 0,
2868         }, {
2869                 .name = "dra7-cpsw",
2870                 .driver_data = 0,
2871         }, {
2872                 /* sentinel */
2873         }
2874 };
2875 MODULE_DEVICE_TABLE(platform, cpsw_devtype);
2876
2877 enum ti_cpsw_type {
2878         CPSW = 0,
2879         AM335X_CPSW,
2880         AM4372_CPSW,
2881         DRA7_CPSW,
2882 };
2883
2884 static const struct of_device_id cpsw_of_mtable[] = {
2885         { .compatible = "ti,cpsw", .data = &cpsw_devtype[CPSW], },
2886         { .compatible = "ti,am335x-cpsw", .data = &cpsw_devtype[AM335X_CPSW], },
2887         { .compatible = "ti,am4372-cpsw", .data = &cpsw_devtype[AM4372_CPSW], },
2888         { .compatible = "ti,dra7-cpsw", .data = &cpsw_devtype[DRA7_CPSW], },
2889         { /* sentinel */ },
2890 };
2891 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2892
2893 static int cpsw_probe(struct platform_device *pdev)
2894 {
2895         struct clk                      *clk;
2896         struct cpsw_platform_data       *data;
2897         struct net_device               *ndev;
2898         struct cpsw_priv                *priv;
2899         struct cpdma_params             dma_params;
2900         struct cpsw_ale_params          ale_params;
2901         void __iomem                    *ss_regs;
2902         void __iomem                    *cpts_regs;
2903         struct resource                 *res, *ss_res;
2904         const struct of_device_id       *of_id;
2905         struct gpio_descs               *mode;
2906         u32 slave_offset, sliver_offset, slave_size;
2907         struct cpsw_common              *cpsw;
2908         int ret = 0, i;
2909         int irq;
2910
2911         cpsw = devm_kzalloc(&pdev->dev, sizeof(struct cpsw_common), GFP_KERNEL);
2912         if (!cpsw)
2913                 return -ENOMEM;
2914
2915         cpsw->dev = &pdev->dev;
2916
2917         ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
2918         if (!ndev) {
2919                 dev_err(&pdev->dev, "error allocating net_device\n");
2920                 return -ENOMEM;
2921         }
2922
2923         platform_set_drvdata(pdev, ndev);
2924         priv = netdev_priv(ndev);
2925         priv->cpsw = cpsw;
2926         priv->ndev = ndev;
2927         priv->dev  = &ndev->dev;
2928         priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2929         cpsw->rx_packet_max = max(rx_packet_max, 128);
2930
2931         mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW);
2932         if (IS_ERR(mode)) {
2933                 ret = PTR_ERR(mode);
2934                 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
2935                 goto clean_ndev_ret;
2936         }
2937
2938         /*
2939          * This may be required here for child devices.
2940          */
2941         pm_runtime_enable(&pdev->dev);
2942
2943         /* Select default pin state */
2944         pinctrl_pm_select_default_state(&pdev->dev);
2945
2946         /* Need to enable clocks with runtime PM api to access module
2947          * registers
2948          */
2949         ret = pm_runtime_get_sync(&pdev->dev);
2950         if (ret < 0) {
2951                 pm_runtime_put_noidle(&pdev->dev);
2952                 goto clean_runtime_disable_ret;
2953         }
2954
2955         ret = cpsw_probe_dt(&cpsw->data, pdev);
2956         if (ret)
2957                 goto clean_dt_ret;
2958
2959         data = &cpsw->data;
2960         cpsw->rx_ch_num = 1;
2961         cpsw->tx_ch_num = 1;
2962
2963         if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2964                 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
2965                 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
2966         } else {
2967                 eth_random_addr(priv->mac_addr);
2968                 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
2969         }
2970
2971         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2972
2973         cpsw->slaves = devm_kzalloc(&pdev->dev,
2974                                     sizeof(struct cpsw_slave) * data->slaves,
2975                                     GFP_KERNEL);
2976         if (!cpsw->slaves) {
2977                 ret = -ENOMEM;
2978                 goto clean_dt_ret;
2979         }
2980         for (i = 0; i < data->slaves; i++)
2981                 cpsw->slaves[i].slave_num = i;
2982
2983         cpsw->slaves[0].ndev = ndev;
2984         priv->emac_port = 0;
2985
2986         clk = devm_clk_get(&pdev->dev, "fck");
2987         if (IS_ERR(clk)) {
2988                 dev_err(priv->dev, "fck is not found\n");
2989                 ret = -ENODEV;
2990                 goto clean_dt_ret;
2991         }
2992         cpsw->bus_freq_mhz = clk_get_rate(clk) / 1000000;
2993
2994         ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2995         ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2996         if (IS_ERR(ss_regs)) {
2997                 ret = PTR_ERR(ss_regs);
2998                 goto clean_dt_ret;
2999         }
3000         cpsw->regs = ss_regs;
3001
3002         cpsw->version = readl(&cpsw->regs->id_ver);
3003
3004         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3005         cpsw->wr_regs = devm_ioremap_resource(&pdev->dev, res);
3006         if (IS_ERR(cpsw->wr_regs)) {
3007                 ret = PTR_ERR(cpsw->wr_regs);
3008                 goto clean_dt_ret;
3009         }
3010
3011         memset(&dma_params, 0, sizeof(dma_params));
3012         memset(&ale_params, 0, sizeof(ale_params));
3013
3014         switch (cpsw->version) {
3015         case CPSW_VERSION_1:
3016                 cpsw->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
3017                 cpts_regs               = ss_regs + CPSW1_CPTS_OFFSET;
3018                 cpsw->hw_stats       = ss_regs + CPSW1_HW_STATS;
3019                 dma_params.dmaregs   = ss_regs + CPSW1_CPDMA_OFFSET;
3020                 dma_params.txhdp     = ss_regs + CPSW1_STATERAM_OFFSET;
3021                 ale_params.ale_regs  = ss_regs + CPSW1_ALE_OFFSET;
3022                 slave_offset         = CPSW1_SLAVE_OFFSET;
3023                 slave_size           = CPSW1_SLAVE_SIZE;
3024                 sliver_offset        = CPSW1_SLIVER_OFFSET;
3025                 dma_params.desc_mem_phys = 0;
3026                 break;
3027         case CPSW_VERSION_2:
3028         case CPSW_VERSION_3:
3029         case CPSW_VERSION_4:
3030                 cpsw->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
3031                 cpts_regs               = ss_regs + CPSW2_CPTS_OFFSET;
3032                 cpsw->hw_stats       = ss_regs + CPSW2_HW_STATS;
3033                 dma_params.dmaregs   = ss_regs + CPSW2_CPDMA_OFFSET;
3034                 dma_params.txhdp     = ss_regs + CPSW2_STATERAM_OFFSET;
3035                 ale_params.ale_regs  = ss_regs + CPSW2_ALE_OFFSET;
3036                 slave_offset         = CPSW2_SLAVE_OFFSET;
3037                 slave_size           = CPSW2_SLAVE_SIZE;
3038                 sliver_offset        = CPSW2_SLIVER_OFFSET;
3039                 dma_params.desc_mem_phys =
3040                         (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
3041                 break;
3042         default:
3043                 dev_err(priv->dev, "unknown version 0x%08x\n", cpsw->version);
3044                 ret = -ENODEV;
3045                 goto clean_dt_ret;
3046         }
3047         for (i = 0; i < cpsw->data.slaves; i++) {
3048                 struct cpsw_slave *slave = &cpsw->slaves[i];
3049
3050                 cpsw_slave_init(slave, cpsw, slave_offset, sliver_offset);
3051                 slave_offset  += slave_size;
3052                 sliver_offset += SLIVER_SIZE;
3053         }
3054
3055         dma_params.dev          = &pdev->dev;
3056         dma_params.rxthresh     = dma_params.dmaregs + CPDMA_RXTHRESH;
3057         dma_params.rxfree       = dma_params.dmaregs + CPDMA_RXFREE;
3058         dma_params.rxhdp        = dma_params.txhdp + CPDMA_RXHDP;
3059         dma_params.txcp         = dma_params.txhdp + CPDMA_TXCP;
3060         dma_params.rxcp         = dma_params.txhdp + CPDMA_RXCP;
3061
3062         dma_params.num_chan             = data->channels;
3063         dma_params.has_soft_reset       = true;
3064         dma_params.min_packet_size      = CPSW_MIN_PACKET_SIZE;
3065         dma_params.desc_mem_size        = data->bd_ram_size;
3066         dma_params.desc_align           = 16;
3067         dma_params.has_ext_regs         = true;
3068         dma_params.desc_hw_addr         = dma_params.desc_mem_phys;
3069         dma_params.bus_freq_mhz         = cpsw->bus_freq_mhz;
3070         dma_params.descs_pool_size      = descs_pool_size;
3071
3072         cpsw->dma = cpdma_ctlr_create(&dma_params);
3073         if (!cpsw->dma) {
3074                 dev_err(priv->dev, "error initializing dma\n");
3075                 ret = -ENOMEM;
3076                 goto clean_dt_ret;
3077         }
3078
3079         cpsw->txv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_tx_handler, 0);
3080         if (IS_ERR(cpsw->txv[0].ch)) {
3081                 dev_err(priv->dev, "error initializing tx dma channel\n");
3082                 ret = PTR_ERR(cpsw->txv[0].ch);
3083                 goto clean_dma_ret;
3084         }
3085
3086         cpsw->rxv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_rx_handler, 1);
3087         if (IS_ERR(cpsw->rxv[0].ch)) {
3088                 dev_err(priv->dev, "error initializing rx dma channel\n");
3089                 ret = PTR_ERR(cpsw->rxv[0].ch);
3090                 goto clean_dma_ret;
3091         }
3092
3093         ale_params.dev                  = &pdev->dev;
3094         ale_params.ale_ageout           = ale_ageout;
3095         ale_params.ale_entries          = data->ale_entries;
3096         ale_params.ale_ports            = CPSW_ALE_PORTS_NUM;
3097
3098         cpsw->ale = cpsw_ale_create(&ale_params);
3099         if (!cpsw->ale) {
3100                 dev_err(priv->dev, "error initializing ale engine\n");
3101                 ret = -ENODEV;
3102                 goto clean_dma_ret;
3103         }
3104
3105         cpsw->cpts = cpts_create(cpsw->dev, cpts_regs, cpsw->dev->of_node);
3106         if (IS_ERR(cpsw->cpts)) {
3107                 ret = PTR_ERR(cpsw->cpts);
3108                 goto clean_dma_ret;
3109         }
3110
3111         ndev->irq = platform_get_irq(pdev, 1);
3112         if (ndev->irq < 0) {
3113                 dev_err(priv->dev, "error getting irq resource\n");
3114                 ret = ndev->irq;
3115                 goto clean_dma_ret;
3116         }
3117
3118         of_id = of_match_device(cpsw_of_mtable, &pdev->dev);
3119         if (of_id) {
3120                 pdev->id_entry = of_id->data;
3121                 if (pdev->id_entry->driver_data)
3122                         cpsw->quirk_irq = true;
3123         }
3124
3125         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3126
3127         ndev->netdev_ops = &cpsw_netdev_ops;
3128         ndev->ethtool_ops = &cpsw_ethtool_ops;
3129         netif_napi_add(ndev, &cpsw->napi_rx, cpsw_rx_poll, CPSW_POLL_WEIGHT);
3130         netif_tx_napi_add(ndev, &cpsw->napi_tx, cpsw_tx_poll, CPSW_POLL_WEIGHT);
3131         cpsw_split_res(ndev);
3132
3133         /* register the network device */
3134         SET_NETDEV_DEV(ndev, &pdev->dev);
3135         ret = register_netdev(ndev);
3136         if (ret) {
3137                 dev_err(priv->dev, "error registering net device\n");
3138                 ret = -ENODEV;
3139                 goto clean_dma_ret;
3140         }
3141
3142         if (cpsw->data.dual_emac) {
3143                 ret = cpsw_probe_dual_emac(priv);
3144                 if (ret) {
3145                         cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
3146                         goto clean_unregister_netdev_ret;
3147                 }
3148         }
3149
3150         /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
3151          * MISC IRQs which are always kept disabled with this driver so
3152          * we will not request them.
3153          *
3154          * If anyone wants to implement support for those, make sure to
3155          * first request and append them to irqs_table array.
3156          */
3157
3158         /* RX IRQ */
3159         irq = platform_get_irq(pdev, 1);
3160         if (irq < 0) {
3161                 ret = irq;
3162                 goto clean_dma_ret;
3163         }
3164
3165         cpsw->irqs_table[0] = irq;
3166         ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
3167                                0, dev_name(&pdev->dev), cpsw);
3168         if (ret < 0) {
3169                 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
3170                 goto clean_dma_ret;
3171         }
3172
3173         /* TX IRQ */
3174         irq = platform_get_irq(pdev, 2);
3175         if (irq < 0) {
3176                 ret = irq;
3177                 goto clean_dma_ret;
3178         }
3179
3180         cpsw->irqs_table[1] = irq;
3181         ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
3182                                0, dev_name(&pdev->dev), cpsw);
3183         if (ret < 0) {
3184                 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
3185                 goto clean_dma_ret;
3186         }
3187
3188         cpsw_notice(priv, probe,
3189                     "initialized device (regs %pa, irq %d, pool size %d)\n",
3190                     &ss_res->start, ndev->irq, dma_params.descs_pool_size);
3191
3192         pm_runtime_put(&pdev->dev);
3193
3194         return 0;
3195
3196 clean_unregister_netdev_ret:
3197         unregister_netdev(ndev);
3198 clean_dma_ret:
3199         cpdma_ctlr_destroy(cpsw->dma);
3200 clean_dt_ret:
3201         cpsw_remove_dt(pdev);
3202         pm_runtime_put_sync(&pdev->dev);
3203 clean_runtime_disable_ret:
3204         pm_runtime_disable(&pdev->dev);
3205 clean_ndev_ret:
3206         free_netdev(priv->ndev);
3207         return ret;
3208 }
3209
3210 static int cpsw_remove(struct platform_device *pdev)
3211 {
3212         struct net_device *ndev = platform_get_drvdata(pdev);
3213         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
3214         int ret;
3215
3216         ret = pm_runtime_get_sync(&pdev->dev);
3217         if (ret < 0) {
3218                 pm_runtime_put_noidle(&pdev->dev);
3219                 return ret;
3220         }
3221
3222         if (cpsw->data.dual_emac)
3223                 unregister_netdev(cpsw->slaves[1].ndev);
3224         unregister_netdev(ndev);
3225
3226         cpts_release(cpsw->cpts);
3227         cpdma_ctlr_destroy(cpsw->dma);
3228         cpsw_remove_dt(pdev);
3229         pm_runtime_put_sync(&pdev->dev);
3230         pm_runtime_disable(&pdev->dev);
3231         if (cpsw->data.dual_emac)
3232                 free_netdev(cpsw->slaves[1].ndev);
3233         free_netdev(ndev);
3234         return 0;
3235 }
3236
3237 #ifdef CONFIG_PM_SLEEP
3238 static int cpsw_suspend(struct device *dev)
3239 {
3240         struct platform_device  *pdev = to_platform_device(dev);
3241         struct net_device       *ndev = platform_get_drvdata(pdev);
3242         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
3243
3244         if (cpsw->data.dual_emac) {
3245                 int i;
3246
3247                 for (i = 0; i < cpsw->data.slaves; i++) {
3248                         if (netif_running(cpsw->slaves[i].ndev))
3249                                 cpsw_ndo_stop(cpsw->slaves[i].ndev);
3250                 }
3251         } else {
3252                 if (netif_running(ndev))
3253                         cpsw_ndo_stop(ndev);
3254         }
3255
3256         /* Select sleep pin state */
3257         pinctrl_pm_select_sleep_state(dev);
3258
3259         return 0;
3260 }
3261
3262 static int cpsw_resume(struct device *dev)
3263 {
3264         struct platform_device  *pdev = to_platform_device(dev);
3265         struct net_device       *ndev = platform_get_drvdata(pdev);
3266         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
3267
3268         /* Select default pin state */
3269         pinctrl_pm_select_default_state(dev);
3270
3271         /* shut up ASSERT_RTNL() warning in netif_set_real_num_tx/rx_queues */
3272         rtnl_lock();
3273         if (cpsw->data.dual_emac) {
3274                 int i;
3275
3276                 for (i = 0; i < cpsw->data.slaves; i++) {
3277                         if (netif_running(cpsw->slaves[i].ndev))
3278                                 cpsw_ndo_open(cpsw->slaves[i].ndev);
3279                 }
3280         } else {
3281                 if (netif_running(ndev))
3282                         cpsw_ndo_open(ndev);
3283         }
3284         rtnl_unlock();
3285
3286         return 0;
3287 }
3288 #endif
3289
3290 static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
3291
3292 static struct platform_driver cpsw_driver = {
3293         .driver = {
3294                 .name    = "cpsw",
3295                 .pm      = &cpsw_pm_ops,
3296                 .of_match_table = cpsw_of_mtable,
3297         },
3298         .probe = cpsw_probe,
3299         .remove = cpsw_remove,
3300 };
3301
3302 module_platform_driver(cpsw_driver);
3303
3304 MODULE_LICENSE("GPL");
3305 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
3306 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
3307 MODULE_DESCRIPTION("TI CPSW Ethernet driver");