stmmac: fix stmmac_tx_avail should be called with TX locked
[sfrench/cifs-2.6.git] / drivers / net / ethernet / stmicro / stmmac / stmmac_main.c
1 /*******************************************************************************
2   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3   ST Ethernet IPs are built around a Synopsys IP Core.
4
5         Copyright(C) 2007-2011 STMicroelectronics Ltd
6
7   This program is free software; you can redistribute it and/or modify it
8   under the terms and conditions of the GNU General Public License,
9   version 2, as published by the Free Software Foundation.
10
11   This program is distributed in the hope it will be useful, but WITHOUT
12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14   more details.
15
16   You should have received a copy of the GNU General Public License along with
17   this program; if not, write to the Free Software Foundation, Inc.,
18   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19
20   The full GNU General Public License is included in this distribution in
21   the file called "COPYING".
22
23   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
24
25   Documentation available at:
26         http://www.stlinux.com
27   Support available at:
28         https://bugzilla.stlinux.com/
29 *******************************************************************************/
30
31 #include <linux/clk.h>
32 #include <linux/kernel.h>
33 #include <linux/interrupt.h>
34 #include <linux/ip.h>
35 #include <linux/tcp.h>
36 #include <linux/skbuff.h>
37 #include <linux/ethtool.h>
38 #include <linux/if_ether.h>
39 #include <linux/crc32.h>
40 #include <linux/mii.h>
41 #include <linux/if.h>
42 #include <linux/if_vlan.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/slab.h>
45 #include <linux/prefetch.h>
46 #include <linux/pinctrl/consumer.h>
47 #ifdef CONFIG_STMMAC_DEBUG_FS
48 #include <linux/debugfs.h>
49 #include <linux/seq_file.h>
50 #endif /* CONFIG_STMMAC_DEBUG_FS */
51 #include <linux/net_tstamp.h>
52 #include "stmmac_ptp.h"
53 #include "stmmac.h"
54 #include <linux/reset.h>
55
56 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
57
58 /* Module parameters */
59 #define TX_TIMEO        5000
60 static int watchdog = TX_TIMEO;
61 module_param(watchdog, int, S_IRUGO | S_IWUSR);
62 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
63
64 static int debug = -1;
65 module_param(debug, int, S_IRUGO | S_IWUSR);
66 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
67
68 static int phyaddr = -1;
69 module_param(phyaddr, int, S_IRUGO);
70 MODULE_PARM_DESC(phyaddr, "Physical device address");
71
72 #define DMA_TX_SIZE 256
73 static int dma_txsize = DMA_TX_SIZE;
74 module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
75 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
76
77 #define DMA_RX_SIZE 256
78 static int dma_rxsize = DMA_RX_SIZE;
79 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
80 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
81
82 static int flow_ctrl = FLOW_OFF;
83 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
84 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
85
86 static int pause = PAUSE_TIME;
87 module_param(pause, int, S_IRUGO | S_IWUSR);
88 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
89
90 #define TC_DEFAULT 64
91 static int tc = TC_DEFAULT;
92 module_param(tc, int, S_IRUGO | S_IWUSR);
93 MODULE_PARM_DESC(tc, "DMA threshold control value");
94
95 #define DEFAULT_BUFSIZE 1536
96 static int buf_sz = DEFAULT_BUFSIZE;
97 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
98 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
99
100 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
101                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
102                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
103
104 #define STMMAC_DEFAULT_LPI_TIMER        1000
105 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
106 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
107 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
108 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
109
110 /* By default the driver will use the ring mode to manage tx and rx descriptors
111  * but passing this value so user can force to use the chain instead of the ring
112  */
113 static unsigned int chain_mode;
114 module_param(chain_mode, int, S_IRUGO);
115 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
116
117 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
118
119 #ifdef CONFIG_STMMAC_DEBUG_FS
120 static int stmmac_init_fs(struct net_device *dev);
121 static void stmmac_exit_fs(void);
122 #endif
123
124 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
125
126 /**
127  * stmmac_verify_args - verify the driver parameters.
128  * Description: it verifies if some wrong parameter is passed to the driver.
129  * Note that wrong parameters are replaced with the default values.
130  */
131 static void stmmac_verify_args(void)
132 {
133         if (unlikely(watchdog < 0))
134                 watchdog = TX_TIMEO;
135         if (unlikely(dma_rxsize < 0))
136                 dma_rxsize = DMA_RX_SIZE;
137         if (unlikely(dma_txsize < 0))
138                 dma_txsize = DMA_TX_SIZE;
139         if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
140                 buf_sz = DEFAULT_BUFSIZE;
141         if (unlikely(flow_ctrl > 1))
142                 flow_ctrl = FLOW_AUTO;
143         else if (likely(flow_ctrl < 0))
144                 flow_ctrl = FLOW_OFF;
145         if (unlikely((pause < 0) || (pause > 0xffff)))
146                 pause = PAUSE_TIME;
147         if (eee_timer < 0)
148                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
149 }
150
151 /**
152  * stmmac_clk_csr_set - dynamically set the MDC clock
153  * @priv: driver private structure
154  * Description: this is to dynamically set the MDC clock according to the csr
155  * clock input.
156  * Note:
157  *      If a specific clk_csr value is passed from the platform
158  *      this means that the CSR Clock Range selection cannot be
159  *      changed at run-time and it is fixed (as reported in the driver
160  *      documentation). Viceversa the driver will try to set the MDC
161  *      clock dynamically according to the actual clock input.
162  */
163 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
164 {
165         u32 clk_rate;
166
167         clk_rate = clk_get_rate(priv->stmmac_clk);
168
169         /* Platform provided default clk_csr would be assumed valid
170          * for all other cases except for the below mentioned ones.
171          * For values higher than the IEEE 802.3 specified frequency
172          * we can not estimate the proper divider as it is not known
173          * the frequency of clk_csr_i. So we do not change the default
174          * divider.
175          */
176         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
177                 if (clk_rate < CSR_F_35M)
178                         priv->clk_csr = STMMAC_CSR_20_35M;
179                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
180                         priv->clk_csr = STMMAC_CSR_35_60M;
181                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
182                         priv->clk_csr = STMMAC_CSR_60_100M;
183                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
184                         priv->clk_csr = STMMAC_CSR_100_150M;
185                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
186                         priv->clk_csr = STMMAC_CSR_150_250M;
187                 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
188                         priv->clk_csr = STMMAC_CSR_250_300M;
189         }
190 }
191
192 static void print_pkt(unsigned char *buf, int len)
193 {
194         int j;
195         pr_debug("len = %d byte, buf addr: 0x%p", len, buf);
196         for (j = 0; j < len; j++) {
197                 if ((j % 16) == 0)
198                         pr_debug("\n %03x:", j);
199                 pr_debug(" %02x", buf[j]);
200         }
201         pr_debug("\n");
202 }
203
204 /* minimum number of free TX descriptors required to wake up TX process */
205 #define STMMAC_TX_THRESH(x)     (x->dma_tx_size/4)
206
207 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
208 {
209         return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
210 }
211
212 /**
213  * stmmac_hw_fix_mac_speed: callback for speed selection
214  * @priv: driver private structure
215  * Description: on some platforms (e.g. ST), some HW system configuraton
216  * registers have to be set according to the link speed negotiated.
217  */
218 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
219 {
220         struct phy_device *phydev = priv->phydev;
221
222         if (likely(priv->plat->fix_mac_speed))
223                 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
224 }
225
226 /**
227  * stmmac_enable_eee_mode: Check and enter in LPI mode
228  * @priv: driver private structure
229  * Description: this function is to verify and enter in LPI mode for EEE.
230  */
231 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
232 {
233         /* Check and enter in LPI mode */
234         if ((priv->dirty_tx == priv->cur_tx) &&
235             (priv->tx_path_in_lpi_mode == false))
236                 priv->hw->mac->set_eee_mode(priv->hw);
237 }
238
239 /**
240  * stmmac_disable_eee_mode: disable/exit from EEE
241  * @priv: driver private structure
242  * Description: this function is to exit and disable EEE in case of
243  * LPI state is true. This is called by the xmit.
244  */
245 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
246 {
247         priv->hw->mac->reset_eee_mode(priv->hw);
248         del_timer_sync(&priv->eee_ctrl_timer);
249         priv->tx_path_in_lpi_mode = false;
250 }
251
252 /**
253  * stmmac_eee_ctrl_timer: EEE TX SW timer.
254  * @arg : data hook
255  * Description:
256  *  if there is no data transfer and if we are not in LPI state,
257  *  then MAC Transmitter can be moved to LPI state.
258  */
259 static void stmmac_eee_ctrl_timer(unsigned long arg)
260 {
261         struct stmmac_priv *priv = (struct stmmac_priv *)arg;
262
263         stmmac_enable_eee_mode(priv);
264         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
265 }
266
267 /**
268  * stmmac_eee_init: init EEE
269  * @priv: driver private structure
270  * Description:
271  *  If the EEE support has been enabled while configuring the driver,
272  *  if the GMAC actually supports the EEE (from the HW cap reg) and the
273  *  phy can also manage EEE, so enable the LPI state and start the timer
274  *  to verify if the tx path can enter in LPI state.
275  */
276 bool stmmac_eee_init(struct stmmac_priv *priv)
277 {
278         char *phy_bus_name = priv->plat->phy_bus_name;
279         bool ret = false;
280
281         /* Using PCS we cannot dial with the phy registers at this stage
282          * so we do not support extra feature like EEE.
283          */
284         if ((priv->pcs == STMMAC_PCS_RGMII) || (priv->pcs == STMMAC_PCS_TBI) ||
285             (priv->pcs == STMMAC_PCS_RTBI))
286                 goto out;
287
288         /* Never init EEE in case of a switch is attached */
289         if (phy_bus_name && (!strcmp(phy_bus_name, "fixed")))
290                 goto out;
291
292         /* MAC core supports the EEE feature. */
293         if (priv->dma_cap.eee) {
294                 int tx_lpi_timer = priv->tx_lpi_timer;
295
296                 /* Check if the PHY supports EEE */
297                 if (phy_init_eee(priv->phydev, 1)) {
298                         /* To manage at run-time if the EEE cannot be supported
299                          * anymore (for example because the lp caps have been
300                          * changed).
301                          * In that case the driver disable own timers.
302                          */
303                         if (priv->eee_active) {
304                                 pr_debug("stmmac: disable EEE\n");
305                                 del_timer_sync(&priv->eee_ctrl_timer);
306                                 priv->hw->mac->set_eee_timer(priv->hw, 0,
307                                                              tx_lpi_timer);
308                         }
309                         priv->eee_active = 0;
310                         goto out;
311                 }
312                 /* Activate the EEE and start timers */
313                 if (!priv->eee_active) {
314                         priv->eee_active = 1;
315                         init_timer(&priv->eee_ctrl_timer);
316                         priv->eee_ctrl_timer.function = stmmac_eee_ctrl_timer;
317                         priv->eee_ctrl_timer.data = (unsigned long)priv;
318                         priv->eee_ctrl_timer.expires = STMMAC_LPI_T(eee_timer);
319                         add_timer(&priv->eee_ctrl_timer);
320
321                         priv->hw->mac->set_eee_timer(priv->hw,
322                                                      STMMAC_DEFAULT_LIT_LS,
323                                                      tx_lpi_timer);
324                 }
325                 /* Set HW EEE according to the speed */
326                 priv->hw->mac->set_eee_pls(priv->hw, priv->phydev->link);
327
328                 pr_debug("stmmac: Energy-Efficient Ethernet initialized\n");
329
330                 ret = true;
331         }
332 out:
333         return ret;
334 }
335
336 /* stmmac_get_tx_hwtstamp: get HW TX timestamps
337  * @priv: driver private structure
338  * @entry : descriptor index to be used.
339  * @skb : the socket buffer
340  * Description :
341  * This function will read timestamp from the descriptor & pass it to stack.
342  * and also perform some sanity checks.
343  */
344 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
345                                    unsigned int entry, struct sk_buff *skb)
346 {
347         struct skb_shared_hwtstamps shhwtstamp;
348         u64 ns;
349         void *desc = NULL;
350
351         if (!priv->hwts_tx_en)
352                 return;
353
354         /* exit if skb doesn't support hw tstamp */
355         if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
356                 return;
357
358         if (priv->adv_ts)
359                 desc = (priv->dma_etx + entry);
360         else
361                 desc = (priv->dma_tx + entry);
362
363         /* check tx tstamp status */
364         if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc))
365                 return;
366
367         /* get the valid tstamp */
368         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
369
370         memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
371         shhwtstamp.hwtstamp = ns_to_ktime(ns);
372         /* pass tstamp to stack */
373         skb_tstamp_tx(skb, &shhwtstamp);
374
375         return;
376 }
377
378 /* stmmac_get_rx_hwtstamp: get HW RX timestamps
379  * @priv: driver private structure
380  * @entry : descriptor index to be used.
381  * @skb : the socket buffer
382  * Description :
383  * This function will read received packet's timestamp from the descriptor
384  * and pass it to stack. It also perform some sanity checks.
385  */
386 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv,
387                                    unsigned int entry, struct sk_buff *skb)
388 {
389         struct skb_shared_hwtstamps *shhwtstamp = NULL;
390         u64 ns;
391         void *desc = NULL;
392
393         if (!priv->hwts_rx_en)
394                 return;
395
396         if (priv->adv_ts)
397                 desc = (priv->dma_erx + entry);
398         else
399                 desc = (priv->dma_rx + entry);
400
401         /* exit if rx tstamp is not valid */
402         if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts))
403                 return;
404
405         /* get valid tstamp */
406         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
407         shhwtstamp = skb_hwtstamps(skb);
408         memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
409         shhwtstamp->hwtstamp = ns_to_ktime(ns);
410 }
411
412 /**
413  *  stmmac_hwtstamp_ioctl - control hardware timestamping.
414  *  @dev: device pointer.
415  *  @ifr: An IOCTL specefic structure, that can contain a pointer to
416  *  a proprietary structure used to pass information to the driver.
417  *  Description:
418  *  This function configures the MAC to enable/disable both outgoing(TX)
419  *  and incoming(RX) packets time stamping based on user input.
420  *  Return Value:
421  *  0 on success and an appropriate -ve integer on failure.
422  */
423 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
424 {
425         struct stmmac_priv *priv = netdev_priv(dev);
426         struct hwtstamp_config config;
427         struct timespec now;
428         u64 temp = 0;
429         u32 ptp_v2 = 0;
430         u32 tstamp_all = 0;
431         u32 ptp_over_ipv4_udp = 0;
432         u32 ptp_over_ipv6_udp = 0;
433         u32 ptp_over_ethernet = 0;
434         u32 snap_type_sel = 0;
435         u32 ts_master_en = 0;
436         u32 ts_event_en = 0;
437         u32 value = 0;
438
439         if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
440                 netdev_alert(priv->dev, "No support for HW time stamping\n");
441                 priv->hwts_tx_en = 0;
442                 priv->hwts_rx_en = 0;
443
444                 return -EOPNOTSUPP;
445         }
446
447         if (copy_from_user(&config, ifr->ifr_data,
448                            sizeof(struct hwtstamp_config)))
449                 return -EFAULT;
450
451         pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
452                  __func__, config.flags, config.tx_type, config.rx_filter);
453
454         /* reserved for future extensions */
455         if (config.flags)
456                 return -EINVAL;
457
458         if (config.tx_type != HWTSTAMP_TX_OFF &&
459             config.tx_type != HWTSTAMP_TX_ON)
460                 return -ERANGE;
461
462         if (priv->adv_ts) {
463                 switch (config.rx_filter) {
464                 case HWTSTAMP_FILTER_NONE:
465                         /* time stamp no incoming packet at all */
466                         config.rx_filter = HWTSTAMP_FILTER_NONE;
467                         break;
468
469                 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
470                         /* PTP v1, UDP, any kind of event packet */
471                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
472                         /* take time stamp for all event messages */
473                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
474
475                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
476                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
477                         break;
478
479                 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
480                         /* PTP v1, UDP, Sync packet */
481                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
482                         /* take time stamp for SYNC messages only */
483                         ts_event_en = PTP_TCR_TSEVNTENA;
484
485                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
486                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
487                         break;
488
489                 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
490                         /* PTP v1, UDP, Delay_req packet */
491                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
492                         /* take time stamp for Delay_Req messages only */
493                         ts_master_en = PTP_TCR_TSMSTRENA;
494                         ts_event_en = PTP_TCR_TSEVNTENA;
495
496                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
497                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
498                         break;
499
500                 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
501                         /* PTP v2, UDP, any kind of event packet */
502                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
503                         ptp_v2 = PTP_TCR_TSVER2ENA;
504                         /* take time stamp for all event messages */
505                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
506
507                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
508                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
509                         break;
510
511                 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
512                         /* PTP v2, UDP, Sync packet */
513                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
514                         ptp_v2 = PTP_TCR_TSVER2ENA;
515                         /* take time stamp for SYNC messages only */
516                         ts_event_en = PTP_TCR_TSEVNTENA;
517
518                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
519                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
520                         break;
521
522                 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
523                         /* PTP v2, UDP, Delay_req packet */
524                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
525                         ptp_v2 = PTP_TCR_TSVER2ENA;
526                         /* take time stamp for Delay_Req messages only */
527                         ts_master_en = PTP_TCR_TSMSTRENA;
528                         ts_event_en = PTP_TCR_TSEVNTENA;
529
530                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
531                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
532                         break;
533
534                 case HWTSTAMP_FILTER_PTP_V2_EVENT:
535                         /* PTP v2/802.AS1 any layer, any kind of event packet */
536                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
537                         ptp_v2 = PTP_TCR_TSVER2ENA;
538                         /* take time stamp for all event messages */
539                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
540
541                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
542                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
543                         ptp_over_ethernet = PTP_TCR_TSIPENA;
544                         break;
545
546                 case HWTSTAMP_FILTER_PTP_V2_SYNC:
547                         /* PTP v2/802.AS1, any layer, Sync packet */
548                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
549                         ptp_v2 = PTP_TCR_TSVER2ENA;
550                         /* take time stamp for SYNC messages only */
551                         ts_event_en = PTP_TCR_TSEVNTENA;
552
553                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
554                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
555                         ptp_over_ethernet = PTP_TCR_TSIPENA;
556                         break;
557
558                 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
559                         /* PTP v2/802.AS1, any layer, Delay_req packet */
560                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
561                         ptp_v2 = PTP_TCR_TSVER2ENA;
562                         /* take time stamp for Delay_Req messages only */
563                         ts_master_en = PTP_TCR_TSMSTRENA;
564                         ts_event_en = PTP_TCR_TSEVNTENA;
565
566                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
567                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
568                         ptp_over_ethernet = PTP_TCR_TSIPENA;
569                         break;
570
571                 case HWTSTAMP_FILTER_ALL:
572                         /* time stamp any incoming packet */
573                         config.rx_filter = HWTSTAMP_FILTER_ALL;
574                         tstamp_all = PTP_TCR_TSENALL;
575                         break;
576
577                 default:
578                         return -ERANGE;
579                 }
580         } else {
581                 switch (config.rx_filter) {
582                 case HWTSTAMP_FILTER_NONE:
583                         config.rx_filter = HWTSTAMP_FILTER_NONE;
584                         break;
585                 default:
586                         /* PTP v1, UDP, any kind of event packet */
587                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
588                         break;
589                 }
590         }
591         priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
592         priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
593
594         if (!priv->hwts_tx_en && !priv->hwts_rx_en)
595                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0);
596         else {
597                 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
598                          tstamp_all | ptp_v2 | ptp_over_ethernet |
599                          ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
600                          ts_master_en | snap_type_sel);
601
602                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value);
603
604                 /* program Sub Second Increment reg */
605                 priv->hw->ptp->config_sub_second_increment(priv->ioaddr);
606
607                 /* calculate default added value:
608                  * formula is :
609                  * addend = (2^32)/freq_div_ratio;
610                  * where, freq_div_ratio = clk_ptp_ref_i/50MHz
611                  * hence, addend = ((2^32) * 50MHz)/clk_ptp_ref_i;
612                  * NOTE: clk_ptp_ref_i should be >= 50MHz to
613                  *       achive 20ns accuracy.
614                  *
615                  * 2^x * y == (y << x), hence
616                  * 2^32 * 50000000 ==> (50000000 << 32)
617                  */
618                 temp = (u64) (50000000ULL << 32);
619                 priv->default_addend = div_u64(temp, priv->clk_ptp_rate);
620                 priv->hw->ptp->config_addend(priv->ioaddr,
621                                              priv->default_addend);
622
623                 /* initialize system time */
624                 getnstimeofday(&now);
625                 priv->hw->ptp->init_systime(priv->ioaddr, now.tv_sec,
626                                             now.tv_nsec);
627         }
628
629         return copy_to_user(ifr->ifr_data, &config,
630                             sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
631 }
632
633 /**
634  * stmmac_init_ptp: init PTP
635  * @priv: driver private structure
636  * Description: this is to verify if the HW supports the PTPv1 or v2.
637  * This is done by looking at the HW cap. register.
638  * Also it registers the ptp driver.
639  */
640 static int stmmac_init_ptp(struct stmmac_priv *priv)
641 {
642         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
643                 return -EOPNOTSUPP;
644
645         /* Fall-back to main clock in case of no PTP ref is passed */
646         priv->clk_ptp_ref = devm_clk_get(priv->device, "clk_ptp_ref");
647         if (IS_ERR(priv->clk_ptp_ref)) {
648                 priv->clk_ptp_rate = clk_get_rate(priv->stmmac_clk);
649                 priv->clk_ptp_ref = NULL;
650         } else {
651                 clk_prepare_enable(priv->clk_ptp_ref);
652                 priv->clk_ptp_rate = clk_get_rate(priv->clk_ptp_ref);
653         }
654
655         priv->adv_ts = 0;
656         if (priv->dma_cap.atime_stamp && priv->extend_desc)
657                 priv->adv_ts = 1;
658
659         if (netif_msg_hw(priv) && priv->dma_cap.time_stamp)
660                 pr_debug("IEEE 1588-2002 Time Stamp supported\n");
661
662         if (netif_msg_hw(priv) && priv->adv_ts)
663                 pr_debug("IEEE 1588-2008 Advanced Time Stamp supported\n");
664
665         priv->hw->ptp = &stmmac_ptp;
666         priv->hwts_tx_en = 0;
667         priv->hwts_rx_en = 0;
668
669         return stmmac_ptp_register(priv);
670 }
671
672 static void stmmac_release_ptp(struct stmmac_priv *priv)
673 {
674         if (priv->clk_ptp_ref)
675                 clk_disable_unprepare(priv->clk_ptp_ref);
676         stmmac_ptp_unregister(priv);
677 }
678
679 /**
680  * stmmac_adjust_link
681  * @dev: net device structure
682  * Description: it adjusts the link parameters.
683  */
684 static void stmmac_adjust_link(struct net_device *dev)
685 {
686         struct stmmac_priv *priv = netdev_priv(dev);
687         struct phy_device *phydev = priv->phydev;
688         unsigned long flags;
689         int new_state = 0;
690         unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
691
692         if (phydev == NULL)
693                 return;
694
695         spin_lock_irqsave(&priv->lock, flags);
696
697         if (phydev->link) {
698                 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
699
700                 /* Now we make sure that we can be in full duplex mode.
701                  * If not, we operate in half-duplex mode. */
702                 if (phydev->duplex != priv->oldduplex) {
703                         new_state = 1;
704                         if (!(phydev->duplex))
705                                 ctrl &= ~priv->hw->link.duplex;
706                         else
707                                 ctrl |= priv->hw->link.duplex;
708                         priv->oldduplex = phydev->duplex;
709                 }
710                 /* Flow Control operation */
711                 if (phydev->pause)
712                         priv->hw->mac->flow_ctrl(priv->hw, phydev->duplex,
713                                                  fc, pause_time);
714
715                 if (phydev->speed != priv->speed) {
716                         new_state = 1;
717                         switch (phydev->speed) {
718                         case 1000:
719                                 if (likely(priv->plat->has_gmac))
720                                         ctrl &= ~priv->hw->link.port;
721                                 stmmac_hw_fix_mac_speed(priv);
722                                 break;
723                         case 100:
724                         case 10:
725                                 if (priv->plat->has_gmac) {
726                                         ctrl |= priv->hw->link.port;
727                                         if (phydev->speed == SPEED_100) {
728                                                 ctrl |= priv->hw->link.speed;
729                                         } else {
730                                                 ctrl &= ~(priv->hw->link.speed);
731                                         }
732                                 } else {
733                                         ctrl &= ~priv->hw->link.port;
734                                 }
735                                 stmmac_hw_fix_mac_speed(priv);
736                                 break;
737                         default:
738                                 if (netif_msg_link(priv))
739                                         pr_warn("%s: Speed (%d) not 10/100\n",
740                                                 dev->name, phydev->speed);
741                                 break;
742                         }
743
744                         priv->speed = phydev->speed;
745                 }
746
747                 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
748
749                 if (!priv->oldlink) {
750                         new_state = 1;
751                         priv->oldlink = 1;
752                 }
753         } else if (priv->oldlink) {
754                 new_state = 1;
755                 priv->oldlink = 0;
756                 priv->speed = 0;
757                 priv->oldduplex = -1;
758         }
759
760         if (new_state && netif_msg_link(priv))
761                 phy_print_status(phydev);
762
763         /* At this stage, it could be needed to setup the EEE or adjust some
764          * MAC related HW registers.
765          */
766         priv->eee_enabled = stmmac_eee_init(priv);
767
768         spin_unlock_irqrestore(&priv->lock, flags);
769 }
770
771 /**
772  * stmmac_check_pcs_mode: verify if RGMII/SGMII is supported
773  * @priv: driver private structure
774  * Description: this is to verify if the HW supports the PCS.
775  * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
776  * configured for the TBI, RTBI, or SGMII PHY interface.
777  */
778 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
779 {
780         int interface = priv->plat->interface;
781
782         if (priv->dma_cap.pcs) {
783                 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
784                     (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
785                     (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
786                     (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
787                         pr_debug("STMMAC: PCS RGMII support enable\n");
788                         priv->pcs = STMMAC_PCS_RGMII;
789                 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
790                         pr_debug("STMMAC: PCS SGMII support enable\n");
791                         priv->pcs = STMMAC_PCS_SGMII;
792                 }
793         }
794 }
795
796 /**
797  * stmmac_init_phy - PHY initialization
798  * @dev: net device structure
799  * Description: it initializes the driver's PHY state, and attaches the PHY
800  * to the mac driver.
801  *  Return value:
802  *  0 on success
803  */
804 static int stmmac_init_phy(struct net_device *dev)
805 {
806         struct stmmac_priv *priv = netdev_priv(dev);
807         struct phy_device *phydev;
808         char phy_id_fmt[MII_BUS_ID_SIZE + 3];
809         char bus_id[MII_BUS_ID_SIZE];
810         int interface = priv->plat->interface;
811         int max_speed = priv->plat->max_speed;
812         priv->oldlink = 0;
813         priv->speed = 0;
814         priv->oldduplex = -1;
815
816         if (priv->plat->phy_bus_name)
817                 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
818                          priv->plat->phy_bus_name, priv->plat->bus_id);
819         else
820                 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
821                          priv->plat->bus_id);
822
823         snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
824                  priv->plat->phy_addr);
825         pr_debug("stmmac_init_phy:  trying to attach to %s\n", phy_id_fmt);
826
827         phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, interface);
828
829         if (IS_ERR(phydev)) {
830                 pr_err("%s: Could not attach to PHY\n", dev->name);
831                 return PTR_ERR(phydev);
832         }
833
834         /* Stop Advertising 1000BASE Capability if interface is not GMII */
835         if ((interface == PHY_INTERFACE_MODE_MII) ||
836             (interface == PHY_INTERFACE_MODE_RMII) ||
837                 (max_speed < 1000 && max_speed > 0))
838                 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
839                                          SUPPORTED_1000baseT_Full);
840
841         /*
842          * Broken HW is sometimes missing the pull-up resistor on the
843          * MDIO line, which results in reads to non-existent devices returning
844          * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
845          * device as well.
846          * Note: phydev->phy_id is the result of reading the UID PHY registers.
847          */
848         if (phydev->phy_id == 0) {
849                 phy_disconnect(phydev);
850                 return -ENODEV;
851         }
852         pr_debug("stmmac_init_phy:  %s: attached to PHY (UID 0x%x)"
853                  " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
854
855         priv->phydev = phydev;
856
857         return 0;
858 }
859
860 /**
861  * stmmac_display_ring: display ring
862  * @head: pointer to the head of the ring passed.
863  * @size: size of the ring.
864  * @extend_desc: to verify if extended descriptors are used.
865  * Description: display the control/status and buffer descriptors.
866  */
867 static void stmmac_display_ring(void *head, int size, int extend_desc)
868 {
869         int i;
870         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
871         struct dma_desc *p = (struct dma_desc *)head;
872
873         for (i = 0; i < size; i++) {
874                 u64 x;
875                 if (extend_desc) {
876                         x = *(u64 *) ep;
877                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
878                                 i, (unsigned int)virt_to_phys(ep),
879                                 (unsigned int)x, (unsigned int)(x >> 32),
880                                 ep->basic.des2, ep->basic.des3);
881                         ep++;
882                 } else {
883                         x = *(u64 *) p;
884                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x",
885                                 i, (unsigned int)virt_to_phys(p),
886                                 (unsigned int)x, (unsigned int)(x >> 32),
887                                 p->des2, p->des3);
888                         p++;
889                 }
890                 pr_info("\n");
891         }
892 }
893
894 static void stmmac_display_rings(struct stmmac_priv *priv)
895 {
896         unsigned int txsize = priv->dma_tx_size;
897         unsigned int rxsize = priv->dma_rx_size;
898
899         if (priv->extend_desc) {
900                 pr_info("Extended RX descriptor ring:\n");
901                 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
902                 pr_info("Extended TX descriptor ring:\n");
903                 stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
904         } else {
905                 pr_info("RX descriptor ring:\n");
906                 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
907                 pr_info("TX descriptor ring:\n");
908                 stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
909         }
910 }
911
912 static int stmmac_set_bfsize(int mtu, int bufsize)
913 {
914         int ret = bufsize;
915
916         if (mtu >= BUF_SIZE_4KiB)
917                 ret = BUF_SIZE_8KiB;
918         else if (mtu >= BUF_SIZE_2KiB)
919                 ret = BUF_SIZE_4KiB;
920         else if (mtu > DEFAULT_BUFSIZE)
921                 ret = BUF_SIZE_2KiB;
922         else
923                 ret = DEFAULT_BUFSIZE;
924
925         return ret;
926 }
927
928 /**
929  * stmmac_clear_descriptors: clear descriptors
930  * @priv: driver private structure
931  * Description: this function is called to clear the tx and rx descriptors
932  * in case of both basic and extended descriptors are used.
933  */
934 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
935 {
936         int i;
937         unsigned int txsize = priv->dma_tx_size;
938         unsigned int rxsize = priv->dma_rx_size;
939
940         /* Clear the Rx/Tx descriptors */
941         for (i = 0; i < rxsize; i++)
942                 if (priv->extend_desc)
943                         priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
944                                                      priv->use_riwt, priv->mode,
945                                                      (i == rxsize - 1));
946                 else
947                         priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
948                                                      priv->use_riwt, priv->mode,
949                                                      (i == rxsize - 1));
950         for (i = 0; i < txsize; i++)
951                 if (priv->extend_desc)
952                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
953                                                      priv->mode,
954                                                      (i == txsize - 1));
955                 else
956                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
957                                                      priv->mode,
958                                                      (i == txsize - 1));
959 }
960
961 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
962                                   int i)
963 {
964         struct sk_buff *skb;
965
966         skb = __netdev_alloc_skb(priv->dev, priv->dma_buf_sz + NET_IP_ALIGN,
967                                  GFP_KERNEL);
968         if (!skb) {
969                 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
970                 return -ENOMEM;
971         }
972         skb_reserve(skb, NET_IP_ALIGN);
973         priv->rx_skbuff[i] = skb;
974         priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
975                                                 priv->dma_buf_sz,
976                                                 DMA_FROM_DEVICE);
977         if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) {
978                 pr_err("%s: DMA mapping error\n", __func__);
979                 dev_kfree_skb_any(skb);
980                 return -EINVAL;
981         }
982
983         p->des2 = priv->rx_skbuff_dma[i];
984
985         if ((priv->hw->mode->init_desc3) &&
986             (priv->dma_buf_sz == BUF_SIZE_16KiB))
987                 priv->hw->mode->init_desc3(p);
988
989         return 0;
990 }
991
992 static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i)
993 {
994         if (priv->rx_skbuff[i]) {
995                 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
996                                  priv->dma_buf_sz, DMA_FROM_DEVICE);
997                 dev_kfree_skb_any(priv->rx_skbuff[i]);
998         }
999         priv->rx_skbuff[i] = NULL;
1000 }
1001
1002 /**
1003  * init_dma_desc_rings - init the RX/TX descriptor rings
1004  * @dev: net device structure
1005  * Description:  this function initializes the DMA RX/TX descriptors
1006  * and allocates the socket buffers. It suppors the chained and ring
1007  * modes.
1008  */
1009 static int init_dma_desc_rings(struct net_device *dev)
1010 {
1011         int i;
1012         struct stmmac_priv *priv = netdev_priv(dev);
1013         unsigned int txsize = priv->dma_tx_size;
1014         unsigned int rxsize = priv->dma_rx_size;
1015         unsigned int bfsize = 0;
1016         int ret = -ENOMEM;
1017
1018         if (priv->hw->mode->set_16kib_bfsize)
1019                 bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu);
1020
1021         if (bfsize < BUF_SIZE_16KiB)
1022                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1023
1024         priv->dma_buf_sz = bfsize;
1025
1026         if (netif_msg_probe(priv))
1027                 pr_debug("%s: txsize %d, rxsize %d, bfsize %d\n", __func__,
1028                          txsize, rxsize, bfsize);
1029
1030         if (netif_msg_probe(priv)) {
1031                 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__,
1032                          (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy);
1033
1034                 /* RX INITIALIZATION */
1035                 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n");
1036         }
1037         for (i = 0; i < rxsize; i++) {
1038                 struct dma_desc *p;
1039                 if (priv->extend_desc)
1040                         p = &((priv->dma_erx + i)->basic);
1041                 else
1042                         p = priv->dma_rx + i;
1043
1044                 ret = stmmac_init_rx_buffers(priv, p, i);
1045                 if (ret)
1046                         goto err_init_rx_buffers;
1047
1048                 if (netif_msg_probe(priv))
1049                         pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
1050                                  priv->rx_skbuff[i]->data,
1051                                  (unsigned int)priv->rx_skbuff_dma[i]);
1052         }
1053         priv->cur_rx = 0;
1054         priv->dirty_rx = (unsigned int)(i - rxsize);
1055         buf_sz = bfsize;
1056
1057         /* Setup the chained descriptor addresses */
1058         if (priv->mode == STMMAC_CHAIN_MODE) {
1059                 if (priv->extend_desc) {
1060                         priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy,
1061                                              rxsize, 1);
1062                         priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy,
1063                                              txsize, 1);
1064                 } else {
1065                         priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy,
1066                                              rxsize, 0);
1067                         priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy,
1068                                              txsize, 0);
1069                 }
1070         }
1071
1072         /* TX INITIALIZATION */
1073         for (i = 0; i < txsize; i++) {
1074                 struct dma_desc *p;
1075                 if (priv->extend_desc)
1076                         p = &((priv->dma_etx + i)->basic);
1077                 else
1078                         p = priv->dma_tx + i;
1079                 p->des2 = 0;
1080                 priv->tx_skbuff_dma[i].buf = 0;
1081                 priv->tx_skbuff_dma[i].map_as_page = false;
1082                 priv->tx_skbuff[i] = NULL;
1083         }
1084
1085         priv->dirty_tx = 0;
1086         priv->cur_tx = 0;
1087
1088         stmmac_clear_descriptors(priv);
1089
1090         if (netif_msg_hw(priv))
1091                 stmmac_display_rings(priv);
1092
1093         return 0;
1094 err_init_rx_buffers:
1095         while (--i >= 0)
1096                 stmmac_free_rx_buffers(priv, i);
1097         return ret;
1098 }
1099
1100 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
1101 {
1102         int i;
1103
1104         for (i = 0; i < priv->dma_rx_size; i++)
1105                 stmmac_free_rx_buffers(priv, i);
1106 }
1107
1108 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
1109 {
1110         int i;
1111
1112         for (i = 0; i < priv->dma_tx_size; i++) {
1113                 struct dma_desc *p;
1114
1115                 if (priv->extend_desc)
1116                         p = &((priv->dma_etx + i)->basic);
1117                 else
1118                         p = priv->dma_tx + i;
1119
1120                 if (priv->tx_skbuff_dma[i].buf) {
1121                         if (priv->tx_skbuff_dma[i].map_as_page)
1122                                 dma_unmap_page(priv->device,
1123                                                priv->tx_skbuff_dma[i].buf,
1124                                                priv->hw->desc->get_tx_len(p),
1125                                                DMA_TO_DEVICE);
1126                         else
1127                                 dma_unmap_single(priv->device,
1128                                                  priv->tx_skbuff_dma[i].buf,
1129                                                  priv->hw->desc->get_tx_len(p),
1130                                                  DMA_TO_DEVICE);
1131                 }
1132
1133                 if (priv->tx_skbuff[i] != NULL) {
1134                         dev_kfree_skb_any(priv->tx_skbuff[i]);
1135                         priv->tx_skbuff[i] = NULL;
1136                         priv->tx_skbuff_dma[i].buf = 0;
1137                         priv->tx_skbuff_dma[i].map_as_page = false;
1138                 }
1139         }
1140 }
1141
1142 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1143 {
1144         unsigned int txsize = priv->dma_tx_size;
1145         unsigned int rxsize = priv->dma_rx_size;
1146         int ret = -ENOMEM;
1147
1148         priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t),
1149                                             GFP_KERNEL);
1150         if (!priv->rx_skbuff_dma)
1151                 return -ENOMEM;
1152
1153         priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *),
1154                                         GFP_KERNEL);
1155         if (!priv->rx_skbuff)
1156                 goto err_rx_skbuff;
1157
1158         priv->tx_skbuff_dma = kmalloc_array(txsize,
1159                                             sizeof(*priv->tx_skbuff_dma),
1160                                             GFP_KERNEL);
1161         if (!priv->tx_skbuff_dma)
1162                 goto err_tx_skbuff_dma;
1163
1164         priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *),
1165                                         GFP_KERNEL);
1166         if (!priv->tx_skbuff)
1167                 goto err_tx_skbuff;
1168
1169         if (priv->extend_desc) {
1170                 priv->dma_erx = dma_alloc_coherent(priv->device, rxsize *
1171                                                    sizeof(struct
1172                                                           dma_extended_desc),
1173                                                    &priv->dma_rx_phy,
1174                                                    GFP_KERNEL);
1175                 if (!priv->dma_erx)
1176                         goto err_dma;
1177
1178                 priv->dma_etx = dma_alloc_coherent(priv->device, txsize *
1179                                                    sizeof(struct
1180                                                           dma_extended_desc),
1181                                                    &priv->dma_tx_phy,
1182                                                    GFP_KERNEL);
1183                 if (!priv->dma_etx) {
1184                         dma_free_coherent(priv->device, priv->dma_rx_size *
1185                                         sizeof(struct dma_extended_desc),
1186                                         priv->dma_erx, priv->dma_rx_phy);
1187                         goto err_dma;
1188                 }
1189         } else {
1190                 priv->dma_rx = dma_alloc_coherent(priv->device, rxsize *
1191                                                   sizeof(struct dma_desc),
1192                                                   &priv->dma_rx_phy,
1193                                                   GFP_KERNEL);
1194                 if (!priv->dma_rx)
1195                         goto err_dma;
1196
1197                 priv->dma_tx = dma_alloc_coherent(priv->device, txsize *
1198                                                   sizeof(struct dma_desc),
1199                                                   &priv->dma_tx_phy,
1200                                                   GFP_KERNEL);
1201                 if (!priv->dma_tx) {
1202                         dma_free_coherent(priv->device, priv->dma_rx_size *
1203                                         sizeof(struct dma_desc),
1204                                         priv->dma_rx, priv->dma_rx_phy);
1205                         goto err_dma;
1206                 }
1207         }
1208
1209         return 0;
1210
1211 err_dma:
1212         kfree(priv->tx_skbuff);
1213 err_tx_skbuff:
1214         kfree(priv->tx_skbuff_dma);
1215 err_tx_skbuff_dma:
1216         kfree(priv->rx_skbuff);
1217 err_rx_skbuff:
1218         kfree(priv->rx_skbuff_dma);
1219         return ret;
1220 }
1221
1222 static void free_dma_desc_resources(struct stmmac_priv *priv)
1223 {
1224         /* Release the DMA TX/RX socket buffers */
1225         dma_free_rx_skbufs(priv);
1226         dma_free_tx_skbufs(priv);
1227
1228         /* Free DMA regions of consistent memory previously allocated */
1229         if (!priv->extend_desc) {
1230                 dma_free_coherent(priv->device,
1231                                   priv->dma_tx_size * sizeof(struct dma_desc),
1232                                   priv->dma_tx, priv->dma_tx_phy);
1233                 dma_free_coherent(priv->device,
1234                                   priv->dma_rx_size * sizeof(struct dma_desc),
1235                                   priv->dma_rx, priv->dma_rx_phy);
1236         } else {
1237                 dma_free_coherent(priv->device, priv->dma_tx_size *
1238                                   sizeof(struct dma_extended_desc),
1239                                   priv->dma_etx, priv->dma_tx_phy);
1240                 dma_free_coherent(priv->device, priv->dma_rx_size *
1241                                   sizeof(struct dma_extended_desc),
1242                                   priv->dma_erx, priv->dma_rx_phy);
1243         }
1244         kfree(priv->rx_skbuff_dma);
1245         kfree(priv->rx_skbuff);
1246         kfree(priv->tx_skbuff_dma);
1247         kfree(priv->tx_skbuff);
1248 }
1249
1250 /**
1251  *  stmmac_dma_operation_mode - HW DMA operation mode
1252  *  @priv: driver private structure
1253  *  Description: it sets the DMA operation mode: tx/rx DMA thresholds
1254  *  or Store-And-Forward capability.
1255  */
1256 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1257 {
1258         if (priv->plat->force_thresh_dma_mode)
1259                 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc);
1260         else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1261                 /*
1262                  * In case of GMAC, SF mode can be enabled
1263                  * to perform the TX COE in HW. This depends on:
1264                  * 1) TX COE if actually supported
1265                  * 2) There is no bugged Jumbo frame support
1266                  *    that needs to not insert csum in the TDES.
1267                  */
1268                 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE);
1269                 tc = SF_DMA_MODE;
1270         } else
1271                 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
1272 }
1273
1274 /**
1275  * stmmac_tx_clean:
1276  * @priv: driver private structure
1277  * Description: it reclaims resources after transmission completes.
1278  */
1279 static void stmmac_tx_clean(struct stmmac_priv *priv)
1280 {
1281         unsigned int txsize = priv->dma_tx_size;
1282
1283         spin_lock(&priv->tx_lock);
1284
1285         priv->xstats.tx_clean++;
1286
1287         while (priv->dirty_tx != priv->cur_tx) {
1288                 int last;
1289                 unsigned int entry = priv->dirty_tx % txsize;
1290                 struct sk_buff *skb = priv->tx_skbuff[entry];
1291                 struct dma_desc *p;
1292
1293                 if (priv->extend_desc)
1294                         p = (struct dma_desc *)(priv->dma_etx + entry);
1295                 else
1296                         p = priv->dma_tx + entry;
1297
1298                 /* Check if the descriptor is owned by the DMA. */
1299                 if (priv->hw->desc->get_tx_owner(p))
1300                         break;
1301
1302                 /* Verify tx error by looking at the last segment. */
1303                 last = priv->hw->desc->get_tx_ls(p);
1304                 if (likely(last)) {
1305                         int tx_error =
1306                             priv->hw->desc->tx_status(&priv->dev->stats,
1307                                                       &priv->xstats, p,
1308                                                       priv->ioaddr);
1309                         if (likely(tx_error == 0)) {
1310                                 priv->dev->stats.tx_packets++;
1311                                 priv->xstats.tx_pkt_n++;
1312                         } else
1313                                 priv->dev->stats.tx_errors++;
1314
1315                         stmmac_get_tx_hwtstamp(priv, entry, skb);
1316                 }
1317                 if (netif_msg_tx_done(priv))
1318                         pr_debug("%s: curr %d, dirty %d\n", __func__,
1319                                  priv->cur_tx, priv->dirty_tx);
1320
1321                 if (likely(priv->tx_skbuff_dma[entry].buf)) {
1322                         if (priv->tx_skbuff_dma[entry].map_as_page)
1323                                 dma_unmap_page(priv->device,
1324                                                priv->tx_skbuff_dma[entry].buf,
1325                                                priv->hw->desc->get_tx_len(p),
1326                                                DMA_TO_DEVICE);
1327                         else
1328                                 dma_unmap_single(priv->device,
1329                                                  priv->tx_skbuff_dma[entry].buf,
1330                                                  priv->hw->desc->get_tx_len(p),
1331                                                  DMA_TO_DEVICE);
1332                         priv->tx_skbuff_dma[entry].buf = 0;
1333                         priv->tx_skbuff_dma[entry].map_as_page = false;
1334                 }
1335                 priv->hw->mode->clean_desc3(priv, p);
1336
1337                 if (likely(skb != NULL)) {
1338                         dev_consume_skb_any(skb);
1339                         priv->tx_skbuff[entry] = NULL;
1340                 }
1341
1342                 priv->hw->desc->release_tx_desc(p, priv->mode);
1343
1344                 priv->dirty_tx++;
1345         }
1346         if (unlikely(netif_queue_stopped(priv->dev) &&
1347                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
1348                 netif_tx_lock(priv->dev);
1349                 if (netif_queue_stopped(priv->dev) &&
1350                     stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
1351                         if (netif_msg_tx_done(priv))
1352                                 pr_debug("%s: restart transmit\n", __func__);
1353                         netif_wake_queue(priv->dev);
1354                 }
1355                 netif_tx_unlock(priv->dev);
1356         }
1357
1358         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1359                 stmmac_enable_eee_mode(priv);
1360                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1361         }
1362         spin_unlock(&priv->tx_lock);
1363 }
1364
1365 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
1366 {
1367         priv->hw->dma->enable_dma_irq(priv->ioaddr);
1368 }
1369
1370 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
1371 {
1372         priv->hw->dma->disable_dma_irq(priv->ioaddr);
1373 }
1374
1375 /**
1376  * stmmac_tx_err: irq tx error mng function
1377  * @priv: driver private structure
1378  * Description: it cleans the descriptors and restarts the transmission
1379  * in case of errors.
1380  */
1381 static void stmmac_tx_err(struct stmmac_priv *priv)
1382 {
1383         int i;
1384         int txsize = priv->dma_tx_size;
1385         netif_stop_queue(priv->dev);
1386
1387         priv->hw->dma->stop_tx(priv->ioaddr);
1388         dma_free_tx_skbufs(priv);
1389         for (i = 0; i < txsize; i++)
1390                 if (priv->extend_desc)
1391                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
1392                                                      priv->mode,
1393                                                      (i == txsize - 1));
1394                 else
1395                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
1396                                                      priv->mode,
1397                                                      (i == txsize - 1));
1398         priv->dirty_tx = 0;
1399         priv->cur_tx = 0;
1400         priv->hw->dma->start_tx(priv->ioaddr);
1401
1402         priv->dev->stats.tx_errors++;
1403         netif_wake_queue(priv->dev);
1404 }
1405
1406 /**
1407  * stmmac_dma_interrupt: DMA ISR
1408  * @priv: driver private structure
1409  * Description: this is the DMA ISR. It is called by the main ISR.
1410  * It calls the dwmac dma routine to understand which type of interrupt
1411  * happened. In case of there is a Normal interrupt and either TX or RX
1412  * interrupt happened so the NAPI is scheduled.
1413  */
1414 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
1415 {
1416         int status;
1417
1418         status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
1419         if (likely((status & handle_rx)) || (status & handle_tx)) {
1420                 if (likely(napi_schedule_prep(&priv->napi))) {
1421                         stmmac_disable_dma_irq(priv);
1422                         __napi_schedule(&priv->napi);
1423                 }
1424         }
1425         if (unlikely(status & tx_hard_error_bump_tc)) {
1426                 /* Try to bump up the dma threshold on this failure */
1427                 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
1428                         tc += 64;
1429                         priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
1430                         priv->xstats.threshold = tc;
1431                 }
1432         } else if (unlikely(status == tx_hard_error))
1433                 stmmac_tx_err(priv);
1434 }
1435
1436 /**
1437  * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1438  * @priv: driver private structure
1439  * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1440  */
1441 static void stmmac_mmc_setup(struct stmmac_priv *priv)
1442 {
1443         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
1444             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1445
1446         dwmac_mmc_intr_all_mask(priv->ioaddr);
1447
1448         if (priv->dma_cap.rmon) {
1449                 dwmac_mmc_ctrl(priv->ioaddr, mode);
1450                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
1451         } else
1452                 pr_info(" No MAC Management Counters available\n");
1453 }
1454
1455 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
1456 {
1457         u32 hwid = priv->hw->synopsys_uid;
1458
1459         /* Check Synopsys Id (not available on old chips) */
1460         if (likely(hwid)) {
1461                 u32 uid = ((hwid & 0x0000ff00) >> 8);
1462                 u32 synid = (hwid & 0x000000ff);
1463
1464                 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
1465                         uid, synid);
1466
1467                 return synid;
1468         }
1469         return 0;
1470 }
1471
1472 /**
1473  * stmmac_selec_desc_mode: to select among: normal/alternate/extend descriptors
1474  * @priv: driver private structure
1475  * Description: select the Enhanced/Alternate or Normal descriptors.
1476  * In case of Enhanced/Alternate, it looks at the extended descriptors are
1477  * supported by the HW cap. register.
1478  */
1479 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
1480 {
1481         if (priv->plat->enh_desc) {
1482                 pr_info(" Enhanced/Alternate descriptors\n");
1483
1484                 /* GMAC older than 3.50 has no extended descriptors */
1485                 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
1486                         pr_info("\tEnabled extended descriptors\n");
1487                         priv->extend_desc = 1;
1488                 } else
1489                         pr_warn("Extended descriptors not supported\n");
1490
1491                 priv->hw->desc = &enh_desc_ops;
1492         } else {
1493                 pr_info(" Normal descriptors\n");
1494                 priv->hw->desc = &ndesc_ops;
1495         }
1496 }
1497
1498 /**
1499  * stmmac_get_hw_features: get MAC capabilities from the HW cap. register.
1500  * @priv: driver private structure
1501  * Description:
1502  *  new GMAC chip generations have a new register to indicate the
1503  *  presence of the optional feature/functions.
1504  *  This can be also used to override the value passed through the
1505  *  platform and necessary for old MAC10/100 and GMAC chips.
1506  */
1507 static int stmmac_get_hw_features(struct stmmac_priv *priv)
1508 {
1509         u32 hw_cap = 0;
1510
1511         if (priv->hw->dma->get_hw_feature) {
1512                 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
1513
1514                 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
1515                 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
1516                 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
1517                 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
1518                 priv->dma_cap.multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5;
1519                 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
1520                 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
1521                 priv->dma_cap.pmt_remote_wake_up =
1522                     (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
1523                 priv->dma_cap.pmt_magic_frame =
1524                     (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
1525                 /* MMC */
1526                 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
1527                 /* IEEE 1588-2002 */
1528                 priv->dma_cap.time_stamp =
1529                     (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
1530                 /* IEEE 1588-2008 */
1531                 priv->dma_cap.atime_stamp =
1532                     (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
1533                 /* 802.3az - Energy-Efficient Ethernet (EEE) */
1534                 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
1535                 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
1536                 /* TX and RX csum */
1537                 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
1538                 priv->dma_cap.rx_coe_type1 =
1539                     (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
1540                 priv->dma_cap.rx_coe_type2 =
1541                     (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
1542                 priv->dma_cap.rxfifo_over_2048 =
1543                     (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
1544                 /* TX and RX number of channels */
1545                 priv->dma_cap.number_rx_channel =
1546                     (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
1547                 priv->dma_cap.number_tx_channel =
1548                     (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
1549                 /* Alternate (enhanced) DESC mode */
1550                 priv->dma_cap.enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
1551         }
1552
1553         return hw_cap;
1554 }
1555
1556 /**
1557  * stmmac_check_ether_addr: check if the MAC addr is valid
1558  * @priv: driver private structure
1559  * Description:
1560  * it is to verify if the MAC address is valid, in case of failures it
1561  * generates a random MAC address
1562  */
1563 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
1564 {
1565         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
1566                 priv->hw->mac->get_umac_addr(priv->hw,
1567                                              priv->dev->dev_addr, 0);
1568                 if (!is_valid_ether_addr(priv->dev->dev_addr))
1569                         eth_hw_addr_random(priv->dev);
1570                 pr_info("%s: device MAC address %pM\n", priv->dev->name,
1571                         priv->dev->dev_addr);
1572         }
1573 }
1574
1575 /**
1576  * stmmac_init_dma_engine: DMA init.
1577  * @priv: driver private structure
1578  * Description:
1579  * It inits the DMA invoking the specific MAC/GMAC callback.
1580  * Some DMA parameters can be passed from the platform;
1581  * in case of these are not passed a default is kept for the MAC or GMAC.
1582  */
1583 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
1584 {
1585         int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0;
1586         int mixed_burst = 0;
1587         int atds = 0;
1588
1589         if (priv->plat->dma_cfg) {
1590                 pbl = priv->plat->dma_cfg->pbl;
1591                 fixed_burst = priv->plat->dma_cfg->fixed_burst;
1592                 mixed_burst = priv->plat->dma_cfg->mixed_burst;
1593                 burst_len = priv->plat->dma_cfg->burst_len;
1594         }
1595
1596         if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
1597                 atds = 1;
1598
1599         return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
1600                                    burst_len, priv->dma_tx_phy,
1601                                    priv->dma_rx_phy, atds);
1602 }
1603
1604 /**
1605  * stmmac_tx_timer: mitigation sw timer for tx.
1606  * @data: data pointer
1607  * Description:
1608  * This is the timer handler to directly invoke the stmmac_tx_clean.
1609  */
1610 static void stmmac_tx_timer(unsigned long data)
1611 {
1612         struct stmmac_priv *priv = (struct stmmac_priv *)data;
1613
1614         stmmac_tx_clean(priv);
1615 }
1616
1617 /**
1618  * stmmac_init_tx_coalesce: init tx mitigation options.
1619  * @priv: driver private structure
1620  * Description:
1621  * This inits the transmit coalesce parameters: i.e. timer rate,
1622  * timer handler and default threshold used for enabling the
1623  * interrupt on completion bit.
1624  */
1625 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
1626 {
1627         priv->tx_coal_frames = STMMAC_TX_FRAMES;
1628         priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
1629         init_timer(&priv->txtimer);
1630         priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
1631         priv->txtimer.data = (unsigned long)priv;
1632         priv->txtimer.function = stmmac_tx_timer;
1633         add_timer(&priv->txtimer);
1634 }
1635
1636 /**
1637  * stmmac_hw_setup: setup mac in a usable state.
1638  *  @dev : pointer to the device structure.
1639  *  Description:
1640  *  This function sets up the ip in a usable state.
1641  *  Return value:
1642  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1643  *  file on failure.
1644  */
1645 static int stmmac_hw_setup(struct net_device *dev)
1646 {
1647         struct stmmac_priv *priv = netdev_priv(dev);
1648         int ret;
1649
1650         ret = init_dma_desc_rings(dev);
1651         if (ret < 0) {
1652                 pr_err("%s: DMA descriptors initialization failed\n", __func__);
1653                 return ret;
1654         }
1655         /* DMA initialization and SW reset */
1656         ret = stmmac_init_dma_engine(priv);
1657         if (ret < 0) {
1658                 pr_err("%s: DMA engine initialization failed\n", __func__);
1659                 return ret;
1660         }
1661
1662         /* Copy the MAC addr into the HW  */
1663         priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0);
1664
1665         /* If required, perform hw setup of the bus. */
1666         if (priv->plat->bus_setup)
1667                 priv->plat->bus_setup(priv->ioaddr);
1668
1669         /* Initialize the MAC Core */
1670         priv->hw->mac->core_init(priv->hw, dev->mtu);
1671
1672         ret = priv->hw->mac->rx_ipc(priv->hw);
1673         if (!ret) {
1674                 pr_warn(" RX IPC Checksum Offload disabled\n");
1675                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
1676                 priv->hw->rx_csum = 0;
1677         }
1678
1679         /* Enable the MAC Rx/Tx */
1680         stmmac_set_mac(priv->ioaddr, true);
1681
1682         /* Set the HW DMA mode and the COE */
1683         stmmac_dma_operation_mode(priv);
1684
1685         stmmac_mmc_setup(priv);
1686
1687         ret = stmmac_init_ptp(priv);
1688         if (ret && ret != -EOPNOTSUPP)
1689                 pr_warn("%s: failed PTP initialisation\n", __func__);
1690
1691 #ifdef CONFIG_STMMAC_DEBUG_FS
1692         ret = stmmac_init_fs(dev);
1693         if (ret < 0)
1694                 pr_warn("%s: failed debugFS registration\n", __func__);
1695 #endif
1696         /* Start the ball rolling... */
1697         pr_debug("%s: DMA RX/TX processes started...\n", dev->name);
1698         priv->hw->dma->start_tx(priv->ioaddr);
1699         priv->hw->dma->start_rx(priv->ioaddr);
1700
1701         /* Dump DMA/MAC registers */
1702         if (netif_msg_hw(priv)) {
1703                 priv->hw->mac->dump_regs(priv->hw);
1704                 priv->hw->dma->dump_regs(priv->ioaddr);
1705         }
1706         priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
1707
1708         priv->eee_enabled = stmmac_eee_init(priv);
1709
1710         stmmac_init_tx_coalesce(priv);
1711
1712         if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1713                 priv->rx_riwt = MAX_DMA_RIWT;
1714                 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
1715         }
1716
1717         if (priv->pcs && priv->hw->mac->ctrl_ane)
1718                 priv->hw->mac->ctrl_ane(priv->hw, 0);
1719
1720         return 0;
1721 }
1722
1723 /**
1724  *  stmmac_open - open entry point of the driver
1725  *  @dev : pointer to the device structure.
1726  *  Description:
1727  *  This function is the open entry point of the driver.
1728  *  Return value:
1729  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1730  *  file on failure.
1731  */
1732 static int stmmac_open(struct net_device *dev)
1733 {
1734         struct stmmac_priv *priv = netdev_priv(dev);
1735         int ret;
1736
1737         stmmac_check_ether_addr(priv);
1738
1739         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
1740             priv->pcs != STMMAC_PCS_RTBI) {
1741                 ret = stmmac_init_phy(dev);
1742                 if (ret) {
1743                         pr_err("%s: Cannot attach to PHY (error: %d)\n",
1744                                __func__, ret);
1745                         return ret;
1746                 }
1747         }
1748
1749         /* Extra statistics */
1750         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1751         priv->xstats.threshold = tc;
1752
1753         /* Create and initialize the TX/RX descriptors chains. */
1754         priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
1755         priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
1756         priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1757
1758         ret = alloc_dma_desc_resources(priv);
1759         if (ret < 0) {
1760                 pr_err("%s: DMA descriptors allocation failed\n", __func__);
1761                 goto dma_desc_error;
1762         }
1763
1764         ret = stmmac_hw_setup(dev);
1765         if (ret < 0) {
1766                 pr_err("%s: Hw setup failed\n", __func__);
1767                 goto init_error;
1768         }
1769
1770         if (priv->phydev)
1771                 phy_start(priv->phydev);
1772
1773         /* Request the IRQ lines */
1774         ret = request_irq(dev->irq, stmmac_interrupt,
1775                           IRQF_SHARED, dev->name, dev);
1776         if (unlikely(ret < 0)) {
1777                 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1778                        __func__, dev->irq, ret);
1779                 goto init_error;
1780         }
1781
1782         /* Request the Wake IRQ in case of another line is used for WoL */
1783         if (priv->wol_irq != dev->irq) {
1784                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1785                                   IRQF_SHARED, dev->name, dev);
1786                 if (unlikely(ret < 0)) {
1787                         pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n",
1788                                __func__, priv->wol_irq, ret);
1789                         goto wolirq_error;
1790                 }
1791         }
1792
1793         /* Request the IRQ lines */
1794         if (priv->lpi_irq > 0) {
1795                 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1796                                   dev->name, dev);
1797                 if (unlikely(ret < 0)) {
1798                         pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1799                                __func__, priv->lpi_irq, ret);
1800                         goto lpiirq_error;
1801                 }
1802         }
1803
1804         napi_enable(&priv->napi);
1805         netif_start_queue(dev);
1806
1807         return 0;
1808
1809 lpiirq_error:
1810         if (priv->wol_irq != dev->irq)
1811                 free_irq(priv->wol_irq, dev);
1812 wolirq_error:
1813         free_irq(dev->irq, dev);
1814
1815 init_error:
1816         free_dma_desc_resources(priv);
1817 dma_desc_error:
1818         if (priv->phydev)
1819                 phy_disconnect(priv->phydev);
1820
1821         return ret;
1822 }
1823
1824 /**
1825  *  stmmac_release - close entry point of the driver
1826  *  @dev : device pointer.
1827  *  Description:
1828  *  This is the stop entry point of the driver.
1829  */
1830 static int stmmac_release(struct net_device *dev)
1831 {
1832         struct stmmac_priv *priv = netdev_priv(dev);
1833
1834         if (priv->eee_enabled)
1835                 del_timer_sync(&priv->eee_ctrl_timer);
1836
1837         /* Stop and disconnect the PHY */
1838         if (priv->phydev) {
1839                 phy_stop(priv->phydev);
1840                 phy_disconnect(priv->phydev);
1841                 priv->phydev = NULL;
1842         }
1843
1844         netif_stop_queue(dev);
1845
1846         napi_disable(&priv->napi);
1847
1848         del_timer_sync(&priv->txtimer);
1849
1850         /* Free the IRQ lines */
1851         free_irq(dev->irq, dev);
1852         if (priv->wol_irq != dev->irq)
1853                 free_irq(priv->wol_irq, dev);
1854         if (priv->lpi_irq > 0)
1855                 free_irq(priv->lpi_irq, dev);
1856
1857         /* Stop TX/RX DMA and clear the descriptors */
1858         priv->hw->dma->stop_tx(priv->ioaddr);
1859         priv->hw->dma->stop_rx(priv->ioaddr);
1860
1861         /* Release and free the Rx/Tx resources */
1862         free_dma_desc_resources(priv);
1863
1864         /* Disable the MAC Rx/Tx */
1865         stmmac_set_mac(priv->ioaddr, false);
1866
1867         netif_carrier_off(dev);
1868
1869 #ifdef CONFIG_STMMAC_DEBUG_FS
1870         stmmac_exit_fs();
1871 #endif
1872
1873         stmmac_release_ptp(priv);
1874
1875         return 0;
1876 }
1877
1878 /**
1879  *  stmmac_xmit: Tx entry point of the driver
1880  *  @skb : the socket buffer
1881  *  @dev : device pointer
1882  *  Description : this is the tx entry point of the driver.
1883  *  It programs the chain or the ring and supports oversized frames
1884  *  and SG feature.
1885  */
1886 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1887 {
1888         struct stmmac_priv *priv = netdev_priv(dev);
1889         unsigned int txsize = priv->dma_tx_size;
1890         unsigned int entry;
1891         int i, csum_insertion = 0, is_jumbo = 0;
1892         int nfrags = skb_shinfo(skb)->nr_frags;
1893         struct dma_desc *desc, *first;
1894         unsigned int nopaged_len = skb_headlen(skb);
1895         unsigned int enh_desc = priv->plat->enh_desc;
1896
1897         spin_lock(&priv->tx_lock);
1898
1899         if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1900                 spin_unlock(&priv->tx_lock);
1901                 if (!netif_queue_stopped(dev)) {
1902                         netif_stop_queue(dev);
1903                         /* This is a hard error, log it. */
1904                         pr_err("%s: Tx Ring full when queue awake\n", __func__);
1905                 }
1906                 return NETDEV_TX_BUSY;
1907         }
1908
1909         if (priv->tx_path_in_lpi_mode)
1910                 stmmac_disable_eee_mode(priv);
1911
1912         entry = priv->cur_tx % txsize;
1913
1914         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
1915
1916         if (priv->extend_desc)
1917                 desc = (struct dma_desc *)(priv->dma_etx + entry);
1918         else
1919                 desc = priv->dma_tx + entry;
1920
1921         first = desc;
1922
1923         /* To program the descriptors according to the size of the frame */
1924         if (enh_desc)
1925                 is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc);
1926
1927         if (likely(!is_jumbo)) {
1928                 desc->des2 = dma_map_single(priv->device, skb->data,
1929                                             nopaged_len, DMA_TO_DEVICE);
1930                 if (dma_mapping_error(priv->device, desc->des2))
1931                         goto dma_map_err;
1932                 priv->tx_skbuff_dma[entry].buf = desc->des2;
1933                 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1934                                                 csum_insertion, priv->mode);
1935         } else {
1936                 desc = first;
1937                 entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion);
1938                 if (unlikely(entry < 0))
1939                         goto dma_map_err;
1940         }
1941
1942         for (i = 0; i < nfrags; i++) {
1943                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1944                 int len = skb_frag_size(frag);
1945
1946                 priv->tx_skbuff[entry] = NULL;
1947                 entry = (++priv->cur_tx) % txsize;
1948                 if (priv->extend_desc)
1949                         desc = (struct dma_desc *)(priv->dma_etx + entry);
1950                 else
1951                         desc = priv->dma_tx + entry;
1952
1953                 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
1954                                               DMA_TO_DEVICE);
1955                 if (dma_mapping_error(priv->device, desc->des2))
1956                         goto dma_map_err; /* should reuse desc w/o issues */
1957
1958                 priv->tx_skbuff_dma[entry].buf = desc->des2;
1959                 priv->tx_skbuff_dma[entry].map_as_page = true;
1960                 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
1961                                                 priv->mode);
1962                 wmb();
1963                 priv->hw->desc->set_tx_owner(desc);
1964                 wmb();
1965         }
1966
1967         priv->tx_skbuff[entry] = skb;
1968
1969         /* Finalize the latest segment. */
1970         priv->hw->desc->close_tx_desc(desc);
1971
1972         wmb();
1973         /* According to the coalesce parameter the IC bit for the latest
1974          * segment could be reset and the timer re-started to invoke the
1975          * stmmac_tx function. This approach takes care about the fragments.
1976          */
1977         priv->tx_count_frames += nfrags + 1;
1978         if (priv->tx_coal_frames > priv->tx_count_frames) {
1979                 priv->hw->desc->clear_tx_ic(desc);
1980                 priv->xstats.tx_reset_ic_bit++;
1981                 mod_timer(&priv->txtimer,
1982                           STMMAC_COAL_TIMER(priv->tx_coal_timer));
1983         } else
1984                 priv->tx_count_frames = 0;
1985
1986         /* To avoid raise condition */
1987         priv->hw->desc->set_tx_owner(first);
1988         wmb();
1989
1990         priv->cur_tx++;
1991
1992         if (netif_msg_pktdata(priv)) {
1993                 pr_debug("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d",
1994                         __func__, (priv->cur_tx % txsize),
1995                         (priv->dirty_tx % txsize), entry, first, nfrags);
1996
1997                 if (priv->extend_desc)
1998                         stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
1999                 else
2000                         stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
2001
2002                 pr_debug(">>> frame to be transmitted: ");
2003                 print_pkt(skb->data, skb->len);
2004         }
2005         if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
2006                 if (netif_msg_hw(priv))
2007                         pr_debug("%s: stop transmitted packets\n", __func__);
2008                 netif_stop_queue(dev);
2009         }
2010
2011         dev->stats.tx_bytes += skb->len;
2012
2013         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2014                      priv->hwts_tx_en)) {
2015                 /* declare that device is doing timestamping */
2016                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2017                 priv->hw->desc->enable_tx_timestamp(first);
2018         }
2019
2020         if (!priv->hwts_tx_en)
2021                 skb_tx_timestamp(skb);
2022
2023         priv->hw->dma->enable_dma_transmission(priv->ioaddr);
2024
2025         spin_unlock(&priv->tx_lock);
2026         return NETDEV_TX_OK;
2027
2028 dma_map_err:
2029         dev_err(priv->device, "Tx dma map failed\n");
2030         dev_kfree_skb(skb);
2031         priv->dev->stats.tx_dropped++;
2032         return NETDEV_TX_OK;
2033 }
2034
2035 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
2036 {
2037         struct ethhdr *ehdr;
2038         u16 vlanid;
2039
2040         if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) ==
2041             NETIF_F_HW_VLAN_CTAG_RX &&
2042             !__vlan_get_tag(skb, &vlanid)) {
2043                 /* pop the vlan tag */
2044                 ehdr = (struct ethhdr *)skb->data;
2045                 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
2046                 skb_pull(skb, VLAN_HLEN);
2047                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
2048         }
2049 }
2050
2051
2052 /**
2053  * stmmac_rx_refill: refill used skb preallocated buffers
2054  * @priv: driver private structure
2055  * Description : this is to reallocate the skb for the reception process
2056  * that is based on zero-copy.
2057  */
2058 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
2059 {
2060         unsigned int rxsize = priv->dma_rx_size;
2061         int bfsize = priv->dma_buf_sz;
2062
2063         for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
2064                 unsigned int entry = priv->dirty_rx % rxsize;
2065                 struct dma_desc *p;
2066
2067                 if (priv->extend_desc)
2068                         p = (struct dma_desc *)(priv->dma_erx + entry);
2069                 else
2070                         p = priv->dma_rx + entry;
2071
2072                 if (likely(priv->rx_skbuff[entry] == NULL)) {
2073                         struct sk_buff *skb;
2074
2075                         skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
2076
2077                         if (unlikely(skb == NULL))
2078                                 break;
2079
2080                         priv->rx_skbuff[entry] = skb;
2081                         priv->rx_skbuff_dma[entry] =
2082                             dma_map_single(priv->device, skb->data, bfsize,
2083                                            DMA_FROM_DEVICE);
2084                         if (dma_mapping_error(priv->device,
2085                                               priv->rx_skbuff_dma[entry])) {
2086                                 dev_err(priv->device, "Rx dma map failed\n");
2087                                 dev_kfree_skb(skb);
2088                                 break;
2089                         }
2090                         p->des2 = priv->rx_skbuff_dma[entry];
2091
2092                         priv->hw->mode->refill_desc3(priv, p);
2093
2094                         if (netif_msg_rx_status(priv))
2095                                 pr_debug("\trefill entry #%d\n", entry);
2096                 }
2097                 wmb();
2098                 priv->hw->desc->set_rx_owner(p);
2099                 wmb();
2100         }
2101 }
2102
2103 /**
2104  * stmmac_rx_refill: refill used skb preallocated buffers
2105  * @priv: driver private structure
2106  * @limit: napi bugget.
2107  * Description :  this the function called by the napi poll method.
2108  * It gets all the frames inside the ring.
2109  */
2110 static int stmmac_rx(struct stmmac_priv *priv, int limit)
2111 {
2112         unsigned int rxsize = priv->dma_rx_size;
2113         unsigned int entry = priv->cur_rx % rxsize;
2114         unsigned int next_entry;
2115         unsigned int count = 0;
2116         int coe = priv->hw->rx_csum;
2117
2118         if (netif_msg_rx_status(priv)) {
2119                 pr_debug("%s: descriptor ring:\n", __func__);
2120                 if (priv->extend_desc)
2121                         stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
2122                 else
2123                         stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
2124         }
2125         while (count < limit) {
2126                 int status;
2127                 struct dma_desc *p;
2128
2129                 if (priv->extend_desc)
2130                         p = (struct dma_desc *)(priv->dma_erx + entry);
2131                 else
2132                         p = priv->dma_rx + entry;
2133
2134                 if (priv->hw->desc->get_rx_owner(p))
2135                         break;
2136
2137                 count++;
2138
2139                 next_entry = (++priv->cur_rx) % rxsize;
2140                 if (priv->extend_desc)
2141                         prefetch(priv->dma_erx + next_entry);
2142                 else
2143                         prefetch(priv->dma_rx + next_entry);
2144
2145                 /* read the status of the incoming frame */
2146                 status = priv->hw->desc->rx_status(&priv->dev->stats,
2147                                                    &priv->xstats, p);
2148                 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
2149                         priv->hw->desc->rx_extended_status(&priv->dev->stats,
2150                                                            &priv->xstats,
2151                                                            priv->dma_erx +
2152                                                            entry);
2153                 if (unlikely(status == discard_frame)) {
2154                         priv->dev->stats.rx_errors++;
2155                         if (priv->hwts_rx_en && !priv->extend_desc) {
2156                                 /* DESC2 & DESC3 will be overwitten by device
2157                                  * with timestamp value, hence reinitialize
2158                                  * them in stmmac_rx_refill() function so that
2159                                  * device can reuse it.
2160                                  */
2161                                 priv->rx_skbuff[entry] = NULL;
2162                                 dma_unmap_single(priv->device,
2163                                                  priv->rx_skbuff_dma[entry],
2164                                                  priv->dma_buf_sz,
2165                                                  DMA_FROM_DEVICE);
2166                         }
2167                 } else {
2168                         struct sk_buff *skb;
2169                         int frame_len;
2170
2171                         frame_len = priv->hw->desc->get_rx_frame_len(p, coe);
2172
2173                         /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
2174                          * Type frames (LLC/LLC-SNAP)
2175                          */
2176                         if (unlikely(status != llc_snap))
2177                                 frame_len -= ETH_FCS_LEN;
2178
2179                         if (netif_msg_rx_status(priv)) {
2180                                 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
2181                                          p, entry, p->des2);
2182                                 if (frame_len > ETH_FRAME_LEN)
2183                                         pr_debug("\tframe size %d, COE: %d\n",
2184                                                  frame_len, status);
2185                         }
2186                         skb = priv->rx_skbuff[entry];
2187                         if (unlikely(!skb)) {
2188                                 pr_err("%s: Inconsistent Rx descriptor chain\n",
2189                                        priv->dev->name);
2190                                 priv->dev->stats.rx_dropped++;
2191                                 break;
2192                         }
2193                         prefetch(skb->data - NET_IP_ALIGN);
2194                         priv->rx_skbuff[entry] = NULL;
2195
2196                         stmmac_get_rx_hwtstamp(priv, entry, skb);
2197
2198                         skb_put(skb, frame_len);
2199                         dma_unmap_single(priv->device,
2200                                          priv->rx_skbuff_dma[entry],
2201                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
2202
2203                         if (netif_msg_pktdata(priv)) {
2204                                 pr_debug("frame received (%dbytes)", frame_len);
2205                                 print_pkt(skb->data, frame_len);
2206                         }
2207
2208                         stmmac_rx_vlan(priv->dev, skb);
2209
2210                         skb->protocol = eth_type_trans(skb, priv->dev);
2211
2212                         if (unlikely(!coe))
2213                                 skb_checksum_none_assert(skb);
2214                         else
2215                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2216
2217                         napi_gro_receive(&priv->napi, skb);
2218
2219                         priv->dev->stats.rx_packets++;
2220                         priv->dev->stats.rx_bytes += frame_len;
2221                 }
2222                 entry = next_entry;
2223         }
2224
2225         stmmac_rx_refill(priv);
2226
2227         priv->xstats.rx_pkt_n += count;
2228
2229         return count;
2230 }
2231
2232 /**
2233  *  stmmac_poll - stmmac poll method (NAPI)
2234  *  @napi : pointer to the napi structure.
2235  *  @budget : maximum number of packets that the current CPU can receive from
2236  *            all interfaces.
2237  *  Description :
2238  *  To look at the incoming frames and clear the tx resources.
2239  */
2240 static int stmmac_poll(struct napi_struct *napi, int budget)
2241 {
2242         struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
2243         int work_done = 0;
2244
2245         priv->xstats.napi_poll++;
2246         stmmac_tx_clean(priv);
2247
2248         work_done = stmmac_rx(priv, budget);
2249         if (work_done < budget) {
2250                 napi_complete(napi);
2251                 stmmac_enable_dma_irq(priv);
2252         }
2253         return work_done;
2254 }
2255
2256 /**
2257  *  stmmac_tx_timeout
2258  *  @dev : Pointer to net device structure
2259  *  Description: this function is called when a packet transmission fails to
2260  *   complete within a reasonable time. The driver will mark the error in the
2261  *   netdev structure and arrange for the device to be reset to a sane state
2262  *   in order to transmit a new packet.
2263  */
2264 static void stmmac_tx_timeout(struct net_device *dev)
2265 {
2266         struct stmmac_priv *priv = netdev_priv(dev);
2267
2268         /* Clear Tx resources and restart transmitting again */
2269         stmmac_tx_err(priv);
2270 }
2271
2272 /**
2273  *  stmmac_set_rx_mode - entry point for multicast addressing
2274  *  @dev : pointer to the device structure
2275  *  Description:
2276  *  This function is a driver entry point which gets called by the kernel
2277  *  whenever multicast addresses must be enabled/disabled.
2278  *  Return value:
2279  *  void.
2280  */
2281 static void stmmac_set_rx_mode(struct net_device *dev)
2282 {
2283         struct stmmac_priv *priv = netdev_priv(dev);
2284
2285         spin_lock(&priv->lock);
2286         priv->hw->mac->set_filter(priv->hw, dev);
2287         spin_unlock(&priv->lock);
2288 }
2289
2290 /**
2291  *  stmmac_change_mtu - entry point to change MTU size for the device.
2292  *  @dev : device pointer.
2293  *  @new_mtu : the new MTU size for the device.
2294  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
2295  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
2296  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
2297  *  Return value:
2298  *  0 on success and an appropriate (-)ve integer as defined in errno.h
2299  *  file on failure.
2300  */
2301 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
2302 {
2303         struct stmmac_priv *priv = netdev_priv(dev);
2304         int max_mtu;
2305
2306         if (netif_running(dev)) {
2307                 pr_err("%s: must be stopped to change its MTU\n", dev->name);
2308                 return -EBUSY;
2309         }
2310
2311         if (priv->plat->enh_desc)
2312                 max_mtu = JUMBO_LEN;
2313         else
2314                 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
2315
2316         if (priv->plat->maxmtu < max_mtu)
2317                 max_mtu = priv->plat->maxmtu;
2318
2319         if ((new_mtu < 46) || (new_mtu > max_mtu)) {
2320                 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
2321                 return -EINVAL;
2322         }
2323
2324         dev->mtu = new_mtu;
2325         netdev_update_features(dev);
2326
2327         return 0;
2328 }
2329
2330 static netdev_features_t stmmac_fix_features(struct net_device *dev,
2331                                              netdev_features_t features)
2332 {
2333         struct stmmac_priv *priv = netdev_priv(dev);
2334
2335         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
2336                 features &= ~NETIF_F_RXCSUM;
2337
2338         if (!priv->plat->tx_coe)
2339                 features &= ~NETIF_F_ALL_CSUM;
2340
2341         /* Some GMAC devices have a bugged Jumbo frame support that
2342          * needs to have the Tx COE disabled for oversized frames
2343          * (due to limited buffer sizes). In this case we disable
2344          * the TX csum insertionin the TDES and not use SF.
2345          */
2346         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
2347                 features &= ~NETIF_F_ALL_CSUM;
2348
2349         return features;
2350 }
2351
2352 static int stmmac_set_features(struct net_device *netdev,
2353                                netdev_features_t features)
2354 {
2355         struct stmmac_priv *priv = netdev_priv(netdev);
2356
2357         /* Keep the COE Type in case of csum is supporting */
2358         if (features & NETIF_F_RXCSUM)
2359                 priv->hw->rx_csum = priv->plat->rx_coe;
2360         else
2361                 priv->hw->rx_csum = 0;
2362         /* No check needed because rx_coe has been set before and it will be
2363          * fixed in case of issue.
2364          */
2365         priv->hw->mac->rx_ipc(priv->hw);
2366
2367         return 0;
2368 }
2369
2370 /**
2371  *  stmmac_interrupt - main ISR
2372  *  @irq: interrupt number.
2373  *  @dev_id: to pass the net device pointer.
2374  *  Description: this is the main driver interrupt service routine.
2375  *  It calls the DMA ISR and also the core ISR to manage PMT, MMC, LPI
2376  *  interrupts.
2377  */
2378 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
2379 {
2380         struct net_device *dev = (struct net_device *)dev_id;
2381         struct stmmac_priv *priv = netdev_priv(dev);
2382
2383         if (priv->irq_wake)
2384                 pm_wakeup_event(priv->device, 0);
2385
2386         if (unlikely(!dev)) {
2387                 pr_err("%s: invalid dev pointer\n", __func__);
2388                 return IRQ_NONE;
2389         }
2390
2391         /* To handle GMAC own interrupts */
2392         if (priv->plat->has_gmac) {
2393                 int status = priv->hw->mac->host_irq_status(priv->hw,
2394                                                             &priv->xstats);
2395                 if (unlikely(status)) {
2396                         /* For LPI we need to save the tx status */
2397                         if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
2398                                 priv->tx_path_in_lpi_mode = true;
2399                         if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
2400                                 priv->tx_path_in_lpi_mode = false;
2401                 }
2402         }
2403
2404         /* To handle DMA interrupts */
2405         stmmac_dma_interrupt(priv);
2406
2407         return IRQ_HANDLED;
2408 }
2409
2410 #ifdef CONFIG_NET_POLL_CONTROLLER
2411 /* Polling receive - used by NETCONSOLE and other diagnostic tools
2412  * to allow network I/O with interrupts disabled.
2413  */
2414 static void stmmac_poll_controller(struct net_device *dev)
2415 {
2416         disable_irq(dev->irq);
2417         stmmac_interrupt(dev->irq, dev);
2418         enable_irq(dev->irq);
2419 }
2420 #endif
2421
2422 /**
2423  *  stmmac_ioctl - Entry point for the Ioctl
2424  *  @dev: Device pointer.
2425  *  @rq: An IOCTL specefic structure, that can contain a pointer to
2426  *  a proprietary structure used to pass information to the driver.
2427  *  @cmd: IOCTL command
2428  *  Description:
2429  *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
2430  */
2431 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2432 {
2433         struct stmmac_priv *priv = netdev_priv(dev);
2434         int ret = -EOPNOTSUPP;
2435
2436         if (!netif_running(dev))
2437                 return -EINVAL;
2438
2439         switch (cmd) {
2440         case SIOCGMIIPHY:
2441         case SIOCGMIIREG:
2442         case SIOCSMIIREG:
2443                 if (!priv->phydev)
2444                         return -EINVAL;
2445                 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
2446                 break;
2447         case SIOCSHWTSTAMP:
2448                 ret = stmmac_hwtstamp_ioctl(dev, rq);
2449                 break;
2450         default:
2451                 break;
2452         }
2453
2454         return ret;
2455 }
2456
2457 #ifdef CONFIG_STMMAC_DEBUG_FS
2458 static struct dentry *stmmac_fs_dir;
2459 static struct dentry *stmmac_rings_status;
2460 static struct dentry *stmmac_dma_cap;
2461
2462 static void sysfs_display_ring(void *head, int size, int extend_desc,
2463                                struct seq_file *seq)
2464 {
2465         int i;
2466         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
2467         struct dma_desc *p = (struct dma_desc *)head;
2468
2469         for (i = 0; i < size; i++) {
2470                 u64 x;
2471                 if (extend_desc) {
2472                         x = *(u64 *) ep;
2473                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2474                                    i, (unsigned int)virt_to_phys(ep),
2475                                    (unsigned int)x, (unsigned int)(x >> 32),
2476                                    ep->basic.des2, ep->basic.des3);
2477                         ep++;
2478                 } else {
2479                         x = *(u64 *) p;
2480                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2481                                    i, (unsigned int)virt_to_phys(ep),
2482                                    (unsigned int)x, (unsigned int)(x >> 32),
2483                                    p->des2, p->des3);
2484                         p++;
2485                 }
2486                 seq_printf(seq, "\n");
2487         }
2488 }
2489
2490 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
2491 {
2492         struct net_device *dev = seq->private;
2493         struct stmmac_priv *priv = netdev_priv(dev);
2494         unsigned int txsize = priv->dma_tx_size;
2495         unsigned int rxsize = priv->dma_rx_size;
2496
2497         if (priv->extend_desc) {
2498                 seq_printf(seq, "Extended RX descriptor ring:\n");
2499                 sysfs_display_ring((void *)priv->dma_erx, rxsize, 1, seq);
2500                 seq_printf(seq, "Extended TX descriptor ring:\n");
2501                 sysfs_display_ring((void *)priv->dma_etx, txsize, 1, seq);
2502         } else {
2503                 seq_printf(seq, "RX descriptor ring:\n");
2504                 sysfs_display_ring((void *)priv->dma_rx, rxsize, 0, seq);
2505                 seq_printf(seq, "TX descriptor ring:\n");
2506                 sysfs_display_ring((void *)priv->dma_tx, txsize, 0, seq);
2507         }
2508
2509         return 0;
2510 }
2511
2512 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
2513 {
2514         return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
2515 }
2516
2517 static const struct file_operations stmmac_rings_status_fops = {
2518         .owner = THIS_MODULE,
2519         .open = stmmac_sysfs_ring_open,
2520         .read = seq_read,
2521         .llseek = seq_lseek,
2522         .release = single_release,
2523 };
2524
2525 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
2526 {
2527         struct net_device *dev = seq->private;
2528         struct stmmac_priv *priv = netdev_priv(dev);
2529
2530         if (!priv->hw_cap_support) {
2531                 seq_printf(seq, "DMA HW features not supported\n");
2532                 return 0;
2533         }
2534
2535         seq_printf(seq, "==============================\n");
2536         seq_printf(seq, "\tDMA HW features\n");
2537         seq_printf(seq, "==============================\n");
2538
2539         seq_printf(seq, "\t10/100 Mbps %s\n",
2540                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
2541         seq_printf(seq, "\t1000 Mbps %s\n",
2542                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
2543         seq_printf(seq, "\tHalf duple %s\n",
2544                    (priv->dma_cap.half_duplex) ? "Y" : "N");
2545         seq_printf(seq, "\tHash Filter: %s\n",
2546                    (priv->dma_cap.hash_filter) ? "Y" : "N");
2547         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
2548                    (priv->dma_cap.multi_addr) ? "Y" : "N");
2549         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
2550                    (priv->dma_cap.pcs) ? "Y" : "N");
2551         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
2552                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
2553         seq_printf(seq, "\tPMT Remote wake up: %s\n",
2554                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
2555         seq_printf(seq, "\tPMT Magic Frame: %s\n",
2556                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
2557         seq_printf(seq, "\tRMON module: %s\n",
2558                    (priv->dma_cap.rmon) ? "Y" : "N");
2559         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
2560                    (priv->dma_cap.time_stamp) ? "Y" : "N");
2561         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
2562                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
2563         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
2564                    (priv->dma_cap.eee) ? "Y" : "N");
2565         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
2566         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
2567                    (priv->dma_cap.tx_coe) ? "Y" : "N");
2568         seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
2569                    (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
2570         seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
2571                    (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
2572         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
2573                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
2574         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
2575                    priv->dma_cap.number_rx_channel);
2576         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
2577                    priv->dma_cap.number_tx_channel);
2578         seq_printf(seq, "\tEnhanced descriptors: %s\n",
2579                    (priv->dma_cap.enh_desc) ? "Y" : "N");
2580
2581         return 0;
2582 }
2583
2584 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
2585 {
2586         return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
2587 }
2588
2589 static const struct file_operations stmmac_dma_cap_fops = {
2590         .owner = THIS_MODULE,
2591         .open = stmmac_sysfs_dma_cap_open,
2592         .read = seq_read,
2593         .llseek = seq_lseek,
2594         .release = single_release,
2595 };
2596
2597 static int stmmac_init_fs(struct net_device *dev)
2598 {
2599         /* Create debugfs entries */
2600         stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
2601
2602         if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
2603                 pr_err("ERROR %s, debugfs create directory failed\n",
2604                        STMMAC_RESOURCE_NAME);
2605
2606                 return -ENOMEM;
2607         }
2608
2609         /* Entry to report DMA RX/TX rings */
2610         stmmac_rings_status = debugfs_create_file("descriptors_status",
2611                                                   S_IRUGO, stmmac_fs_dir, dev,
2612                                                   &stmmac_rings_status_fops);
2613
2614         if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) {
2615                 pr_info("ERROR creating stmmac ring debugfs file\n");
2616                 debugfs_remove(stmmac_fs_dir);
2617
2618                 return -ENOMEM;
2619         }
2620
2621         /* Entry to report the DMA HW features */
2622         stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir,
2623                                              dev, &stmmac_dma_cap_fops);
2624
2625         if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) {
2626                 pr_info("ERROR creating stmmac MMC debugfs file\n");
2627                 debugfs_remove(stmmac_rings_status);
2628                 debugfs_remove(stmmac_fs_dir);
2629
2630                 return -ENOMEM;
2631         }
2632
2633         return 0;
2634 }
2635
2636 static void stmmac_exit_fs(void)
2637 {
2638         debugfs_remove(stmmac_rings_status);
2639         debugfs_remove(stmmac_dma_cap);
2640         debugfs_remove(stmmac_fs_dir);
2641 }
2642 #endif /* CONFIG_STMMAC_DEBUG_FS */
2643
2644 static const struct net_device_ops stmmac_netdev_ops = {
2645         .ndo_open = stmmac_open,
2646         .ndo_start_xmit = stmmac_xmit,
2647         .ndo_stop = stmmac_release,
2648         .ndo_change_mtu = stmmac_change_mtu,
2649         .ndo_fix_features = stmmac_fix_features,
2650         .ndo_set_features = stmmac_set_features,
2651         .ndo_set_rx_mode = stmmac_set_rx_mode,
2652         .ndo_tx_timeout = stmmac_tx_timeout,
2653         .ndo_do_ioctl = stmmac_ioctl,
2654 #ifdef CONFIG_NET_POLL_CONTROLLER
2655         .ndo_poll_controller = stmmac_poll_controller,
2656 #endif
2657         .ndo_set_mac_address = eth_mac_addr,
2658 };
2659
2660 /**
2661  *  stmmac_hw_init - Init the MAC device
2662  *  @priv: driver private structure
2663  *  Description: this function detects which MAC device
2664  *  (GMAC/MAC10-100) has to attached, checks the HW capability
2665  *  (if supported) and sets the driver's features (for example
2666  *  to use the ring or chaine mode or support the normal/enh
2667  *  descriptor structure).
2668  */
2669 static int stmmac_hw_init(struct stmmac_priv *priv)
2670 {
2671         struct mac_device_info *mac;
2672
2673         /* Identify the MAC HW device */
2674         if (priv->plat->has_gmac) {
2675                 priv->dev->priv_flags |= IFF_UNICAST_FLT;
2676                 mac = dwmac1000_setup(priv->ioaddr,
2677                                       priv->plat->multicast_filter_bins,
2678                                       priv->plat->unicast_filter_entries);
2679         } else {
2680                 mac = dwmac100_setup(priv->ioaddr);
2681         }
2682         if (!mac)
2683                 return -ENOMEM;
2684
2685         priv->hw = mac;
2686
2687         /* Get and dump the chip ID */
2688         priv->synopsys_id = stmmac_get_synopsys_id(priv);
2689
2690         /* To use the chained or ring mode */
2691         if (chain_mode) {
2692                 priv->hw->mode = &chain_mode_ops;
2693                 pr_info(" Chain mode enabled\n");
2694                 priv->mode = STMMAC_CHAIN_MODE;
2695         } else {
2696                 priv->hw->mode = &ring_mode_ops;
2697                 pr_info(" Ring mode enabled\n");
2698                 priv->mode = STMMAC_RING_MODE;
2699         }
2700
2701         /* Get the HW capability (new GMAC newer than 3.50a) */
2702         priv->hw_cap_support = stmmac_get_hw_features(priv);
2703         if (priv->hw_cap_support) {
2704                 pr_info(" DMA HW capability register supported");
2705
2706                 /* We can override some gmac/dma configuration fields: e.g.
2707                  * enh_desc, tx_coe (e.g. that are passed through the
2708                  * platform) with the values from the HW capability
2709                  * register (if supported).
2710                  */
2711                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
2712                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
2713
2714                 priv->plat->tx_coe = priv->dma_cap.tx_coe;
2715
2716                 if (priv->dma_cap.rx_coe_type2)
2717                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
2718                 else if (priv->dma_cap.rx_coe_type1)
2719                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
2720
2721         } else
2722                 pr_info(" No HW DMA feature register supported");
2723
2724         /* To use alternate (extended) or normal descriptor structures */
2725         stmmac_selec_desc_mode(priv);
2726
2727         if (priv->plat->rx_coe) {
2728                 priv->hw->rx_csum = priv->plat->rx_coe;
2729                 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
2730                         priv->plat->rx_coe);
2731         }
2732         if (priv->plat->tx_coe)
2733                 pr_info(" TX Checksum insertion supported\n");
2734
2735         if (priv->plat->pmt) {
2736                 pr_info(" Wake-Up On Lan supported\n");
2737                 device_set_wakeup_capable(priv->device, 1);
2738         }
2739
2740         return 0;
2741 }
2742
2743 /**
2744  * stmmac_dvr_probe
2745  * @device: device pointer
2746  * @plat_dat: platform data pointer
2747  * @addr: iobase memory address
2748  * Description: this is the main probe function used to
2749  * call the alloc_etherdev, allocate the priv structure.
2750  */
2751 struct stmmac_priv *stmmac_dvr_probe(struct device *device,
2752                                      struct plat_stmmacenet_data *plat_dat,
2753                                      void __iomem *addr)
2754 {
2755         int ret = 0;
2756         struct net_device *ndev = NULL;
2757         struct stmmac_priv *priv;
2758
2759         ndev = alloc_etherdev(sizeof(struct stmmac_priv));
2760         if (!ndev)
2761                 return NULL;
2762
2763         SET_NETDEV_DEV(ndev, device);
2764
2765         priv = netdev_priv(ndev);
2766         priv->device = device;
2767         priv->dev = ndev;
2768
2769         stmmac_set_ethtool_ops(ndev);
2770         priv->pause = pause;
2771         priv->plat = plat_dat;
2772         priv->ioaddr = addr;
2773         priv->dev->base_addr = (unsigned long)addr;
2774
2775         /* Verify driver arguments */
2776         stmmac_verify_args();
2777
2778         /* Override with kernel parameters if supplied XXX CRS XXX
2779          * this needs to have multiple instances
2780          */
2781         if ((phyaddr >= 0) && (phyaddr <= 31))
2782                 priv->plat->phy_addr = phyaddr;
2783
2784         priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME);
2785         if (IS_ERR(priv->stmmac_clk)) {
2786                 dev_warn(priv->device, "%s: warning: cannot get CSR clock\n",
2787                          __func__);
2788                 /* If failed to obtain stmmac_clk and specific clk_csr value
2789                  * is NOT passed from the platform, probe fail.
2790                  */
2791                 if (!priv->plat->clk_csr) {
2792                         ret = PTR_ERR(priv->stmmac_clk);
2793                         goto error_clk_get;
2794                 } else {
2795                         priv->stmmac_clk = NULL;
2796                 }
2797         }
2798         clk_prepare_enable(priv->stmmac_clk);
2799
2800         priv->stmmac_rst = devm_reset_control_get(priv->device,
2801                                                   STMMAC_RESOURCE_NAME);
2802         if (IS_ERR(priv->stmmac_rst)) {
2803                 if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) {
2804                         ret = -EPROBE_DEFER;
2805                         goto error_hw_init;
2806                 }
2807                 dev_info(priv->device, "no reset control found\n");
2808                 priv->stmmac_rst = NULL;
2809         }
2810         if (priv->stmmac_rst)
2811                 reset_control_deassert(priv->stmmac_rst);
2812
2813         /* Init MAC and get the capabilities */
2814         ret = stmmac_hw_init(priv);
2815         if (ret)
2816                 goto error_hw_init;
2817
2818         ndev->netdev_ops = &stmmac_netdev_ops;
2819
2820         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2821                             NETIF_F_RXCSUM;
2822         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
2823         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
2824 #ifdef STMMAC_VLAN_TAG_USED
2825         /* Both mac100 and gmac support receive VLAN tag detection */
2826         ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
2827 #endif
2828         priv->msg_enable = netif_msg_init(debug, default_msg_level);
2829
2830         if (flow_ctrl)
2831                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
2832
2833         /* Rx Watchdog is available in the COREs newer than the 3.40.
2834          * In some case, for example on bugged HW this feature
2835          * has to be disable and this can be done by passing the
2836          * riwt_off field from the platform.
2837          */
2838         if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
2839                 priv->use_riwt = 1;
2840                 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
2841         }
2842
2843         netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
2844
2845         spin_lock_init(&priv->lock);
2846         spin_lock_init(&priv->tx_lock);
2847
2848         ret = register_netdev(ndev);
2849         if (ret) {
2850                 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
2851                 goto error_netdev_register;
2852         }
2853
2854         /* If a specific clk_csr value is passed from the platform
2855          * this means that the CSR Clock Range selection cannot be
2856          * changed at run-time and it is fixed. Viceversa the driver'll try to
2857          * set the MDC clock dynamically according to the csr actual
2858          * clock input.
2859          */
2860         if (!priv->plat->clk_csr)
2861                 stmmac_clk_csr_set(priv);
2862         else
2863                 priv->clk_csr = priv->plat->clk_csr;
2864
2865         stmmac_check_pcs_mode(priv);
2866
2867         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
2868             priv->pcs != STMMAC_PCS_RTBI) {
2869                 /* MDIO bus Registration */
2870                 ret = stmmac_mdio_register(ndev);
2871                 if (ret < 0) {
2872                         pr_debug("%s: MDIO bus (id: %d) registration failed",
2873                                  __func__, priv->plat->bus_id);
2874                         goto error_mdio_register;
2875                 }
2876         }
2877
2878         return priv;
2879
2880 error_mdio_register:
2881         unregister_netdev(ndev);
2882 error_netdev_register:
2883         netif_napi_del(&priv->napi);
2884 error_hw_init:
2885         clk_disable_unprepare(priv->stmmac_clk);
2886 error_clk_get:
2887         free_netdev(ndev);
2888
2889         return ERR_PTR(ret);
2890 }
2891
2892 /**
2893  * stmmac_dvr_remove
2894  * @ndev: net device pointer
2895  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
2896  * changes the link status, releases the DMA descriptor rings.
2897  */
2898 int stmmac_dvr_remove(struct net_device *ndev)
2899 {
2900         struct stmmac_priv *priv = netdev_priv(ndev);
2901
2902         pr_info("%s:\n\tremoving driver", __func__);
2903
2904         priv->hw->dma->stop_rx(priv->ioaddr);
2905         priv->hw->dma->stop_tx(priv->ioaddr);
2906
2907         stmmac_set_mac(priv->ioaddr, false);
2908         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&