1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
4 * stmmac XGMAC support.
7 #include <linux/iopoll.h>
11 static int dwxgmac2_dma_reset(void __iomem *ioaddr)
13 u32 value = readl(ioaddr + XGMAC_DMA_MODE);
16 writel(value | XGMAC_SWR, ioaddr + XGMAC_DMA_MODE);
18 return readl_poll_timeout(ioaddr + XGMAC_DMA_MODE, value,
19 !(value & XGMAC_SWR), 0, 100000);
22 static void dwxgmac2_dma_init(void __iomem *ioaddr,
23 struct stmmac_dma_cfg *dma_cfg, int atds)
25 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);
30 writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE);
33 static void dwxgmac2_dma_init_chan(void __iomem *ioaddr,
34 struct stmmac_dma_cfg *dma_cfg, u32 chan)
36 u32 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan));
41 writel(value, ioaddr + XGMAC_DMA_CH_CONTROL(chan));
42 writel(XGMAC_DMA_INT_DEFAULT_EN, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
45 static void dwxgmac2_dma_init_rx_chan(void __iomem *ioaddr,
46 struct stmmac_dma_cfg *dma_cfg,
47 u32 dma_rx_phy, u32 chan)
49 u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
52 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
53 value &= ~XGMAC_RxPBL;
54 value |= (rxpbl << XGMAC_RxPBL_SHIFT) & XGMAC_RxPBL;
55 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
57 writel(dma_rx_phy, ioaddr + XGMAC_DMA_CH_RxDESC_LADDR(chan));
60 static void dwxgmac2_dma_init_tx_chan(void __iomem *ioaddr,
61 struct stmmac_dma_cfg *dma_cfg,
62 u32 dma_tx_phy, u32 chan)
64 u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
67 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
68 value &= ~XGMAC_TxPBL;
69 value |= (txpbl << XGMAC_TxPBL_SHIFT) & XGMAC_TxPBL;
71 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
73 writel(dma_tx_phy, ioaddr + XGMAC_DMA_CH_TxDESC_LADDR(chan));
76 static void dwxgmac2_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
78 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);
82 value |= XGMAC_EN_LPI;
84 value |= XGMAC_LPI_XIT_PKT;
86 value &= ~XGMAC_WR_OSR_LMT;
87 value |= (axi->axi_wr_osr_lmt << XGMAC_WR_OSR_LMT_SHIFT) &
90 value &= ~XGMAC_RD_OSR_LMT;
91 value |= (axi->axi_rd_osr_lmt << XGMAC_RD_OSR_LMT_SHIFT) &
95 for (i = 0; i < AXI_BLEN; i++) {
97 value &= ~XGMAC_UNDEF;
99 switch (axi->axi_blen[i]) {
101 value |= XGMAC_BLEN256;
104 value |= XGMAC_BLEN128;
107 value |= XGMAC_BLEN64;
110 value |= XGMAC_BLEN32;
113 value |= XGMAC_BLEN16;
116 value |= XGMAC_BLEN8;
119 value |= XGMAC_BLEN4;
124 writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE);
127 static void dwxgmac2_dma_rx_mode(void __iomem *ioaddr, int mode,
128 u32 channel, int fifosz, u8 qmode)
130 u32 value = readl(ioaddr + XGMAC_MTL_RXQ_OPMODE(channel));
131 unsigned int rqs = fifosz / 256 - 1;
133 if (mode == SF_DMA_MODE) {
140 value |= 0x0 << XGMAC_RTC_SHIFT;
142 value |= 0x2 << XGMAC_RTC_SHIFT;
144 value |= 0x3 << XGMAC_RTC_SHIFT;
148 value |= (rqs << XGMAC_RQS_SHIFT) & XGMAC_RQS;
150 writel(value, ioaddr + XGMAC_MTL_RXQ_OPMODE(channel));
152 /* Enable MTL RX overflow */
153 value = readl(ioaddr + XGMAC_MTL_QINTEN(channel));
154 writel(value | XGMAC_RXOIE, ioaddr + XGMAC_MTL_QINTEN(channel));
157 static void dwxgmac2_dma_tx_mode(void __iomem *ioaddr, int mode,
158 u32 channel, int fifosz, u8 qmode)
160 u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));
161 unsigned int tqs = fifosz / 256 - 1;
163 if (mode == SF_DMA_MODE) {
170 value |= 0x0 << XGMAC_TTC_SHIFT;
172 value |= 0x2 << XGMAC_TTC_SHIFT;
173 else if (mode <= 128)
174 value |= 0x3 << XGMAC_TTC_SHIFT;
175 else if (mode <= 192)
176 value |= 0x4 << XGMAC_TTC_SHIFT;
177 else if (mode <= 256)
178 value |= 0x5 << XGMAC_TTC_SHIFT;
179 else if (mode <= 384)
180 value |= 0x6 << XGMAC_TTC_SHIFT;
182 value |= 0x7 << XGMAC_TTC_SHIFT;
185 /* Use static TC to Queue mapping */
186 value |= (channel << XGMAC_Q2TCMAP_SHIFT) & XGMAC_Q2TCMAP;
188 value &= ~XGMAC_TXQEN;
189 if (qmode != MTL_QUEUE_AVB)
190 value |= 0x2 << XGMAC_TXQEN_SHIFT;
192 value |= 0x1 << XGMAC_TXQEN_SHIFT;
195 value |= (tqs << XGMAC_TQS_SHIFT) & XGMAC_TQS;
197 writel(value, ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));
200 static void dwxgmac2_enable_dma_irq(void __iomem *ioaddr, u32 chan)
202 writel(XGMAC_DMA_INT_DEFAULT_EN, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
205 static void dwxgmac2_disable_dma_irq(void __iomem *ioaddr, u32 chan)
207 writel(0, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
210 static void dwxgmac2_dma_start_tx(void __iomem *ioaddr, u32 chan)
214 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
216 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
218 value = readl(ioaddr + XGMAC_TX_CONFIG);
219 value |= XGMAC_CONFIG_TE;
220 writel(value, ioaddr + XGMAC_TX_CONFIG);
223 static void dwxgmac2_dma_stop_tx(void __iomem *ioaddr, u32 chan)
227 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
228 value &= ~XGMAC_TXST;
229 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
231 value = readl(ioaddr + XGMAC_TX_CONFIG);
232 value &= ~XGMAC_CONFIG_TE;
233 writel(value, ioaddr + XGMAC_TX_CONFIG);
236 static void dwxgmac2_dma_start_rx(void __iomem *ioaddr, u32 chan)
240 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
242 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
244 value = readl(ioaddr + XGMAC_RX_CONFIG);
245 value |= XGMAC_CONFIG_RE;
246 writel(value, ioaddr + XGMAC_RX_CONFIG);
249 static void dwxgmac2_dma_stop_rx(void __iomem *ioaddr, u32 chan)
253 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
254 value &= ~XGMAC_RXST;
255 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
257 value = readl(ioaddr + XGMAC_RX_CONFIG);
258 value &= ~XGMAC_CONFIG_RE;
259 writel(value, ioaddr + XGMAC_RX_CONFIG);
262 static int dwxgmac2_dma_interrupt(void __iomem *ioaddr,
263 struct stmmac_extra_stats *x, u32 chan)
265 u32 intr_status = readl(ioaddr + XGMAC_DMA_CH_STATUS(chan));
266 u32 intr_en = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan));
269 /* ABNORMAL interrupts */
270 if (unlikely(intr_status & XGMAC_AIS)) {
271 if (unlikely(intr_status & XGMAC_TPS)) {
272 x->tx_process_stopped_irq++;
273 ret |= tx_hard_error;
275 if (unlikely(intr_status & XGMAC_FBE)) {
276 x->fatal_bus_error_irq++;
277 ret |= tx_hard_error;
281 /* TX/RX NORMAL interrupts */
282 if (likely(intr_status & XGMAC_NIS)) {
285 if (likely(intr_status & XGMAC_RI)) {
286 if (likely(intr_en & XGMAC_RIE)) {
287 x->rx_normal_irq_n++;
291 if (likely(intr_status & XGMAC_TI)) {
292 x->tx_normal_irq_n++;
297 /* Clear interrupts */
298 writel(intr_en & intr_status, ioaddr + XGMAC_DMA_CH_STATUS(chan));
303 static void dwxgmac2_get_hw_feature(void __iomem *ioaddr,
304 struct dma_features *dma_cap)
308 /* MAC HW feature 0 */
309 hw_cap = readl(ioaddr + XGMAC_HW_FEATURE0);
310 dma_cap->rx_coe = (hw_cap & XGMAC_HWFEAT_RXCOESEL) >> 16;
311 dma_cap->tx_coe = (hw_cap & XGMAC_HWFEAT_TXCOESEL) >> 14;
312 dma_cap->atime_stamp = (hw_cap & XGMAC_HWFEAT_TSSEL) >> 12;
313 dma_cap->av = (hw_cap & XGMAC_HWFEAT_AVSEL) >> 11;
314 dma_cap->av &= (hw_cap & XGMAC_HWFEAT_RAVSEL) >> 10;
315 dma_cap->pmt_magic_frame = (hw_cap & XGMAC_HWFEAT_MGKSEL) >> 7;
316 dma_cap->pmt_remote_wake_up = (hw_cap & XGMAC_HWFEAT_RWKSEL) >> 6;
317 dma_cap->mbps_1000 = (hw_cap & XGMAC_HWFEAT_GMIISEL) >> 1;
319 /* MAC HW feature 1 */
320 hw_cap = readl(ioaddr + XGMAC_HW_FEATURE1);
321 dma_cap->tsoen = (hw_cap & XGMAC_HWFEAT_TSOEN) >> 18;
322 dma_cap->tx_fifo_size =
323 128 << ((hw_cap & XGMAC_HWFEAT_TXFIFOSIZE) >> 6);
324 dma_cap->rx_fifo_size =
325 128 << ((hw_cap & XGMAC_HWFEAT_RXFIFOSIZE) >> 0);
327 /* MAC HW feature 2 */
328 hw_cap = readl(ioaddr + XGMAC_HW_FEATURE2);
329 dma_cap->pps_out_num = (hw_cap & XGMAC_HWFEAT_PPSOUTNUM) >> 24;
330 dma_cap->number_tx_channel =
331 ((hw_cap & XGMAC_HWFEAT_TXCHCNT) >> 18) + 1;
332 dma_cap->number_rx_channel =
333 ((hw_cap & XGMAC_HWFEAT_RXCHCNT) >> 12) + 1;
334 dma_cap->number_tx_queues =
335 ((hw_cap & XGMAC_HWFEAT_TXQCNT) >> 6) + 1;
336 dma_cap->number_rx_queues =
337 ((hw_cap & XGMAC_HWFEAT_RXQCNT) >> 0) + 1;
340 static void dwxgmac2_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 nchan)
344 for (i = 0; i < nchan; i++)
345 writel(riwt & XGMAC_RWT, ioaddr + XGMAC_DMA_CH_Rx_WATCHDOG(i));
348 static void dwxgmac2_set_rx_ring_len(void __iomem *ioaddr, u32 len, u32 chan)
350 writel(len, ioaddr + XGMAC_DMA_CH_RxDESC_RING_LEN(chan));
353 static void dwxgmac2_set_tx_ring_len(void __iomem *ioaddr, u32 len, u32 chan)
355 writel(len, ioaddr + XGMAC_DMA_CH_TxDESC_RING_LEN(chan));
358 static void dwxgmac2_set_rx_tail_ptr(void __iomem *ioaddr, u32 ptr, u32 chan)
360 writel(ptr, ioaddr + XGMAC_DMA_CH_RxDESC_TAIL_LPTR(chan));
363 static void dwxgmac2_set_tx_tail_ptr(void __iomem *ioaddr, u32 ptr, u32 chan)
365 writel(ptr, ioaddr + XGMAC_DMA_CH_TxDESC_TAIL_LPTR(chan));
368 static void dwxgmac2_enable_tso(void __iomem *ioaddr, bool en, u32 chan)
370 u32 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
377 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
380 static void dwxgmac2_qmode(void __iomem *ioaddr, u32 channel, u8 qmode)
382 u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));
384 value &= ~XGMAC_TXQEN;
385 if (qmode != MTL_QUEUE_AVB) {
386 value |= 0x2 << XGMAC_TXQEN_SHIFT;
387 writel(0, ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(channel));
389 value |= 0x1 << XGMAC_TXQEN_SHIFT;
392 writel(value, ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));
395 static void dwxgmac2_set_bfsize(void __iomem *ioaddr, int bfsize, u32 chan)
399 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
400 value |= bfsize << 1;
401 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
404 const struct stmmac_dma_ops dwxgmac210_dma_ops = {
405 .reset = dwxgmac2_dma_reset,
406 .init = dwxgmac2_dma_init,
407 .init_chan = dwxgmac2_dma_init_chan,
408 .init_rx_chan = dwxgmac2_dma_init_rx_chan,
409 .init_tx_chan = dwxgmac2_dma_init_tx_chan,
410 .axi = dwxgmac2_dma_axi,
412 .dma_rx_mode = dwxgmac2_dma_rx_mode,
413 .dma_tx_mode = dwxgmac2_dma_tx_mode,
414 .enable_dma_irq = dwxgmac2_enable_dma_irq,
415 .disable_dma_irq = dwxgmac2_disable_dma_irq,
416 .start_tx = dwxgmac2_dma_start_tx,
417 .stop_tx = dwxgmac2_dma_stop_tx,
418 .start_rx = dwxgmac2_dma_start_rx,
419 .stop_rx = dwxgmac2_dma_stop_rx,
420 .dma_interrupt = dwxgmac2_dma_interrupt,
421 .get_hw_feature = dwxgmac2_get_hw_feature,
422 .rx_watchdog = dwxgmac2_rx_watchdog,
423 .set_rx_ring_len = dwxgmac2_set_rx_ring_len,
424 .set_tx_ring_len = dwxgmac2_set_tx_ring_len,
425 .set_rx_tail_ptr = dwxgmac2_set_rx_tail_ptr,
426 .set_tx_tail_ptr = dwxgmac2_set_tx_tail_ptr,
427 .enable_tso = dwxgmac2_enable_tso,
428 .qmode = dwxgmac2_qmode,
429 .set_bfsize = dwxgmac2_set_bfsize,