drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c

   1 /*
   2  * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
   3  * DWC Ether MAC version 4.00  has been used for developing this code.
   4  *
   5  * This only implements the mac core functions for this chip.
   6  *
   7  * Copyright (C) 2015  STMicroelectronics Ltd
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms and conditions of the GNU General Public License,
  11  * version 2, as published by the Free Software Foundation.
  12  *
  13  * Author: Alexandre Torgue <alexandre.torgue@st.com>
  14  */
  15
  16 #include <linux/crc32.h>
  17 #include <linux/slab.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/io.h>
  20 #include "stmmac_pcs.h"
  21 #include "dwmac4.h"
  22
  23 static void dwmac4_core_init(struct mac_device_info *hw, int mtu)
  24 {
  25         void __iomem *ioaddr = hw->pcsr;
  26         u32 value = readl(ioaddr + GMAC_CONFIG);
  27
  28         value |= GMAC_CORE_INIT;
  29
  30         if (mtu > 1500)
  31                 value |= GMAC_CONFIG_2K;
  32         if (mtu > 2000)
  33                 value |= GMAC_CONFIG_JE;
  34
  35         if (hw->ps) {
  36                 value |= GMAC_CONFIG_TE;
  37
  38                 value &= hw->link.speed_mask;
  39                 switch (hw->ps) {
  40                 case SPEED_1000:
  41                         value |= hw->link.speed1000;
  42                         break;
  43                 case SPEED_100:
  44                         value |= hw->link.speed100;
  45                         break;
  46                 case SPEED_10:
  47                         value |= hw->link.speed10;
  48                         break;
  49                 }
  50         }
  51
  52         writel(value, ioaddr + GMAC_CONFIG);
  53
  54         /* Mask GMAC interrupts */
  55         value = GMAC_INT_DEFAULT_MASK;
  56         if (hw->pmt)
  57                 value |= GMAC_INT_PMT_EN;
  58         if (hw->pcs)
  59                 value |= GMAC_PCS_IRQ_DEFAULT;
  60
  61         writel(value, ioaddr + GMAC_INT_EN);
  62 }
  63
  64 static void dwmac4_rx_queue_enable(struct mac_device_info *hw,
  65                                    u8 mode, u32 queue)
  66 {
  67         void __iomem *ioaddr = hw->pcsr;
  68         u32 value = readl(ioaddr + GMAC_RXQ_CTRL0);
  69
  70         value &= GMAC_RX_QUEUE_CLEAR(queue);
  71         if (mode == MTL_QUEUE_AVB)
  72                 value |= GMAC_RX_AV_QUEUE_ENABLE(queue);
  73         else if (mode == MTL_QUEUE_DCB)
  74                 value |= GMAC_RX_DCB_QUEUE_ENABLE(queue);
  75
  76         writel(value, ioaddr + GMAC_RXQ_CTRL0);
  77 }
  78
  79 static void dwmac4_rx_queue_priority(struct mac_device_info *hw,
  80                                      u32 prio, u32 queue)
  81 {
  82         void __iomem *ioaddr = hw->pcsr;
  83         u32 base_register;
  84         u32 value;
  85
  86         base_register = (queue < 4) ? GMAC_RXQ_CTRL2 : GMAC_RXQ_CTRL3;
  87
  88         value = readl(ioaddr + base_register);
  89
  90         value &= ~GMAC_RXQCTRL_PSRQX_MASK(queue);
  91         value |= (prio << GMAC_RXQCTRL_PSRQX_SHIFT(queue)) &
  92                                                 GMAC_RXQCTRL_PSRQX_MASK(queue);
  93         writel(value, ioaddr + base_register);
  94 }
  95
  96 static void dwmac4_tx_queue_priority(struct mac_device_info *hw,
  97                                      u32 prio, u32 queue)
  98 {
  99         void __iomem *ioaddr = hw->pcsr;
 100         u32 base_register;
 101         u32 value;
 102
 103         base_register = (queue < 4) ? GMAC_TXQ_PRTY_MAP0 : GMAC_TXQ_PRTY_MAP1;
 104
 105         value = readl(ioaddr + base_register);
 106
 107         value &= ~GMAC_TXQCTRL_PSTQX_MASK(queue);
 108         value |= (prio << GMAC_TXQCTRL_PSTQX_SHIFT(queue)) &
 109                                                 GMAC_TXQCTRL_PSTQX_MASK(queue);
 110
 111         writel(value, ioaddr + base_register);
 112 }
 113
 114 static void dwmac4_tx_queue_routing(struct mac_device_info *hw,
 115                                     u8 packet, u32 queue)
 116 {
 117         void __iomem *ioaddr = hw->pcsr;
 118         u32 value;
 119
 120         static const struct stmmac_rx_routing route_possibilities[] = {
 121                 { GMAC_RXQCTRL_AVCPQ_MASK, GMAC_RXQCTRL_AVCPQ_SHIFT },
 122                 { GMAC_RXQCTRL_PTPQ_MASK, GMAC_RXQCTRL_PTPQ_SHIFT },
 123                 { GMAC_RXQCTRL_DCBCPQ_MASK, GMAC_RXQCTRL_DCBCPQ_SHIFT },
 124                 { GMAC_RXQCTRL_UPQ_MASK, GMAC_RXQCTRL_UPQ_SHIFT },
 125                 { GMAC_RXQCTRL_MCBCQ_MASK, GMAC_RXQCTRL_MCBCQ_SHIFT },
 126         };
 127
 128         value = readl(ioaddr + GMAC_RXQ_CTRL1);
 129
 130         /* routing configuration */
 131         value &= ~route_possibilities[packet - 1].reg_mask;
 132         value |= (queue << route_possibilities[packet-1].reg_shift) &
 133                  route_possibilities[packet - 1].reg_mask;
 134
 135         /* some packets require extra ops */
 136         if (packet == PACKET_AVCPQ) {
 137                 value &= ~GMAC_RXQCTRL_TACPQE;
 138                 value |= 0x1 << GMAC_RXQCTRL_TACPQE_SHIFT;
 139         } else if (packet == PACKET_MCBCQ) {
 140                 value &= ~GMAC_RXQCTRL_MCBCQEN;
 141                 value |= 0x1 << GMAC_RXQCTRL_MCBCQEN_SHIFT;
 142         }
 143
 144         writel(value, ioaddr + GMAC_RXQ_CTRL1);
 145 }
 146
 147 static void dwmac4_prog_mtl_rx_algorithms(struct mac_device_info *hw,
 148                                           u32 rx_alg)
 149 {
 150         void __iomem *ioaddr = hw->pcsr;
 151         u32 value = readl(ioaddr + MTL_OPERATION_MODE);
 152
 153         value &= ~MTL_OPERATION_RAA;
 154         switch (rx_alg) {
 155         case MTL_RX_ALGORITHM_SP:
 156                 value |= MTL_OPERATION_RAA_SP;
 157                 break;
 158         case MTL_RX_ALGORITHM_WSP:
 159                 value |= MTL_OPERATION_RAA_WSP;
 160                 break;
 161         default:
 162                 break;
 163         }
 164
 165         writel(value, ioaddr + MTL_OPERATION_MODE);
 166 }
 167
 168 static void dwmac4_prog_mtl_tx_algorithms(struct mac_device_info *hw,
 169                                           u32 tx_alg)
 170 {
 171         void __iomem *ioaddr = hw->pcsr;
 172         u32 value = readl(ioaddr + MTL_OPERATION_MODE);
 173
 174         value &= ~MTL_OPERATION_SCHALG_MASK;
 175         switch (tx_alg) {
 176         case MTL_TX_ALGORITHM_WRR:
 177                 value |= MTL_OPERATION_SCHALG_WRR;
 178                 break;
 179         case MTL_TX_ALGORITHM_WFQ:
 180                 value |= MTL_OPERATION_SCHALG_WFQ;
 181                 break;
 182         case MTL_TX_ALGORITHM_DWRR:
 183                 value |= MTL_OPERATION_SCHALG_DWRR;
 184                 break;
 185         case MTL_TX_ALGORITHM_SP:
 186                 value |= MTL_OPERATION_SCHALG_SP;
 187                 break;
 188         default:
 189                 break;
 190         }
 191 }
 192
 193 static void dwmac4_set_mtl_tx_queue_weight(struct mac_device_info *hw,
 194                                            u32 weight, u32 queue)
 195 {
 196         void __iomem *ioaddr = hw->pcsr;
 197         u32 value = readl(ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));
 198
 199         value &= ~MTL_TXQ_WEIGHT_ISCQW_MASK;
 200         value |= weight & MTL_TXQ_WEIGHT_ISCQW_MASK;
 201         writel(value, ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));
 202 }
 203
 204 static void dwmac4_map_mtl_dma(struct mac_device_info *hw, u32 queue, u32 chan)
 205 {
 206         void __iomem *ioaddr = hw->pcsr;
 207         u32 value;
 208
 209         if (queue < 4)
 210                 value = readl(ioaddr + MTL_RXQ_DMA_MAP0);
 211         else
 212                 value = readl(ioaddr + MTL_RXQ_DMA_MAP1);
 213
 214         if (queue == 0 || queue == 4) {
 215                 value &= ~MTL_RXQ_DMA_Q04MDMACH_MASK;
 216                 value |= MTL_RXQ_DMA_Q04MDMACH(chan);
 217         } else {
 218                 value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue);
 219                 value |= MTL_RXQ_DMA_QXMDMACH(chan, queue);
 220         }
 221
 222         if (queue < 4)
 223                 writel(value, ioaddr + MTL_RXQ_DMA_MAP0);
 224         else
 225                 writel(value, ioaddr + MTL_RXQ_DMA_MAP1);
 226 }
 227
 228 static void dwmac4_config_cbs(struct mac_device_info *hw,
 229                               u32 send_slope, u32 idle_slope,
 230                               u32 high_credit, u32 low_credit, u32 queue)
 231 {
 232         void __iomem *ioaddr = hw->pcsr;
 233         u32 value;
 234
 235         pr_debug("Queue %d configured as AVB. Parameters:\n", queue);
 236         pr_debug("\tsend_slope: 0x%08x\n", send_slope);
 237         pr_debug("\tidle_slope: 0x%08x\n", idle_slope);
 238         pr_debug("\thigh_credit: 0x%08x\n", high_credit);
 239         pr_debug("\tlow_credit: 0x%08x\n", low_credit);
 240
 241         /* enable AV algorithm */
 242         value = readl(ioaddr + MTL_ETSX_CTRL_BASE_ADDR(queue));
 243         value |= MTL_ETS_CTRL_AVALG;
 244         value |= MTL_ETS_CTRL_CC;
 245         writel(value, ioaddr + MTL_ETSX_CTRL_BASE_ADDR(queue));
 246
 247         /* configure send slope */
 248         value = readl(ioaddr + MTL_SEND_SLP_CREDX_BASE_ADDR(queue));
 249         value &= ~MTL_SEND_SLP_CRED_SSC_MASK;
 250         value |= send_slope & MTL_SEND_SLP_CRED_SSC_MASK;
 251         writel(value, ioaddr + MTL_SEND_SLP_CREDX_BASE_ADDR(queue));
 252
 253         /* configure idle slope (same register as tx weight) */
 254         dwmac4_set_mtl_tx_queue_weight(hw, idle_slope, queue);
 255
 256         /* configure high credit */
 257         value = readl(ioaddr + MTL_HIGH_CREDX_BASE_ADDR(queue));
 258         value &= ~MTL_HIGH_CRED_HC_MASK;
 259         value |= high_credit & MTL_HIGH_CRED_HC_MASK;
 260         writel(value, ioaddr + MTL_HIGH_CREDX_BASE_ADDR(queue));
 261
 262         /* configure high credit */
 263         value = readl(ioaddr + MTL_LOW_CREDX_BASE_ADDR(queue));
 264         value &= ~MTL_HIGH_CRED_LC_MASK;
 265         value |= low_credit & MTL_HIGH_CRED_LC_MASK;
 266         writel(value, ioaddr + MTL_LOW_CREDX_BASE_ADDR(queue));
 267 }
 268
 269 static void dwmac4_dump_regs(struct mac_device_info *hw, u32 *reg_space)
 270 {
 271         void __iomem *ioaddr = hw->pcsr;
 272         int i;
 273
 274         for (i = 0; i < GMAC_REG_NUM; i++)
 275                 reg_space[i] = readl(ioaddr + i * 4);
 276 }
 277
 278 static int dwmac4_rx_ipc_enable(struct mac_device_info *hw)
 279 {
 280         void __iomem *ioaddr = hw->pcsr;
 281         u32 value = readl(ioaddr + GMAC_CONFIG);
 282
 283         if (hw->rx_csum)
 284                 value |= GMAC_CONFIG_IPC;
 285         else
 286                 value &= ~GMAC_CONFIG_IPC;
 287
 288         writel(value, ioaddr + GMAC_CONFIG);
 289
 290         value = readl(ioaddr + GMAC_CONFIG);
 291
 292         return !!(value & GMAC_CONFIG_IPC);
 293 }
 294
 295 static void dwmac4_pmt(struct mac_device_info *hw, unsigned long mode)
 296 {
 297         void __iomem *ioaddr = hw->pcsr;
 298         unsigned int pmt = 0;
 299
 300         if (mode & WAKE_MAGIC) {
 301                 pr_debug("GMAC: WOL Magic frame\n");
 302                 pmt |= power_down | magic_pkt_en;
 303         }
 304         if (mode & WAKE_UCAST) {
 305                 pr_debug("GMAC: WOL on global unicast\n");
 306                 pmt |= power_down | global_unicast | wake_up_frame_en;
 307         }
 308
 309         writel(pmt, ioaddr + GMAC_PMT);
 310 }
 311
 312 static void dwmac4_set_umac_addr(struct mac_device_info *hw,
 313                                  unsigned char *addr, unsigned int reg_n)
 314 {
 315         void __iomem *ioaddr = hw->pcsr;
 316
 317         stmmac_dwmac4_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
 318                                    GMAC_ADDR_LOW(reg_n));
 319 }
 320
 321 static void dwmac4_get_umac_addr(struct mac_device_info *hw,
 322                                  unsigned char *addr, unsigned int reg_n)
 323 {
 324         void __iomem *ioaddr = hw->pcsr;
 325
 326         stmmac_dwmac4_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
 327                                    GMAC_ADDR_LOW(reg_n));
 328 }
 329
 330 static void dwmac4_set_eee_mode(struct mac_device_info *hw,
 331                                 bool en_tx_lpi_clockgating)
 332 {
 333         void __iomem *ioaddr = hw->pcsr;
 334         u32 value;
 335
 336         /* Enable the link status receive on RGMII, SGMII ore SMII
 337          * receive path and instruct the transmit to enter in LPI
 338          * state.
 339          */
 340         value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 341         value |= GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA;
 342
 343         if (en_tx_lpi_clockgating)
 344                 value |= GMAC4_LPI_CTRL_STATUS_LPITCSE;
 345
 346         writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 347 }
 348
 349 static void dwmac4_reset_eee_mode(struct mac_device_info *hw)
 350 {
 351         void __iomem *ioaddr = hw->pcsr;
 352         u32 value;
 353
 354         value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 355         value &= ~(GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA);
 356         writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 357 }
 358
 359 static void dwmac4_set_eee_pls(struct mac_device_info *hw, int link)
 360 {
 361         void __iomem *ioaddr = hw->pcsr;
 362         u32 value;
 363
 364         value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 365
 366         if (link)
 367                 value |= GMAC4_LPI_CTRL_STATUS_PLS;
 368         else
 369                 value &= ~GMAC4_LPI_CTRL_STATUS_PLS;
 370
 371         writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 372 }
 373
 374 static void dwmac4_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
 375 {
 376         void __iomem *ioaddr = hw->pcsr;
 377         int value = ((tw & 0xffff)) | ((ls & 0x3ff) << 16);
 378
 379         /* Program the timers in the LPI timer control register:
 380          * LS: minimum time (ms) for which the link
 381          *  status from PHY should be ok before transmitting
 382          *  the LPI pattern.
 383          * TW: minimum time (us) for which the core waits
 384          *  after it has stopped transmitting the LPI pattern.
 385          */
 386         writel(value, ioaddr + GMAC4_LPI_TIMER_CTRL);
 387 }
 388
 389 static void dwmac4_set_filter(struct mac_device_info *hw,
 390                               struct net_device *dev)
 391 {
 392         void __iomem *ioaddr = (void __iomem *)dev->base_addr;
 393         unsigned int value = 0;
 394
 395         if (dev->flags & IFF_PROMISC) {
 396                 value = GMAC_PACKET_FILTER_PR;
 397         } else if ((dev->flags & IFF_ALLMULTI) ||
 398                         (netdev_mc_count(dev) > HASH_TABLE_SIZE)) {
 399                 /* Pass all multi */
 400                 value = GMAC_PACKET_FILTER_PM;
 401                 /* Set the 64 bits of the HASH tab. To be updated if taller
 402                  * hash table is used
 403                  */
 404                 writel(0xffffffff, ioaddr + GMAC_HASH_TAB_0_31);
 405                 writel(0xffffffff, ioaddr + GMAC_HASH_TAB_32_63);
 406         } else if (!netdev_mc_empty(dev)) {
 407                 u32 mc_filter[2];
 408                 struct netdev_hw_addr *ha;
 409
 410                 /* Hash filter for multicast */
 411                 value = GMAC_PACKET_FILTER_HMC;
 412
 413                 memset(mc_filter, 0, sizeof(mc_filter));
 414                 netdev_for_each_mc_addr(ha, dev) {
 415                         /* The upper 6 bits of the calculated CRC are used to
 416                          * index the content of the Hash Table Reg 0 and 1.
 417                          */
 418                         int bit_nr =
 419                                 (bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26);
 420                         /* The most significant bit determines the register
 421                          * to use while the other 5 bits determines the bit
 422                          * within the selected register
 423                          */
 424                         mc_filter[bit_nr >> 5] |= (1 << (bit_nr & 0x1F));
 425                 }
 426                 writel(mc_filter[0], ioaddr + GMAC_HASH_TAB_0_31);
 427                 writel(mc_filter[1], ioaddr + GMAC_HASH_TAB_32_63);
 428         }
 429
 430         /* Handle multiple unicast addresses */
 431         if (netdev_uc_count(dev) > GMAC_MAX_PERFECT_ADDRESSES) {
 432                 /* Switch to promiscuous mode if more than 128 addrs
 433                  * are required
 434                  */
 435                 value |= GMAC_PACKET_FILTER_PR;
 436         } else if (!netdev_uc_empty(dev)) {
 437                 int reg = 1;
 438                 struct netdev_hw_addr *ha;
 439
 440                 netdev_for_each_uc_addr(ha, dev) {
 441                         dwmac4_set_umac_addr(hw, ha->addr, reg);
 442                         reg++;
 443                 }
 444         }
 445
 446         writel(value, ioaddr + GMAC_PACKET_FILTER);
 447 }
 448
 449 static void dwmac4_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
 450                              unsigned int fc, unsigned int pause_time,
 451                              u32 tx_cnt)
 452 {
 453         void __iomem *ioaddr = hw->pcsr;
 454         unsigned int flow = 0;
 455         u32 queue = 0;
 456
 457         pr_debug("GMAC Flow-Control:\n");
 458         if (fc & FLOW_RX) {
 459                 pr_debug("\tReceive Flow-Control ON\n");
 460                 flow |= GMAC_RX_FLOW_CTRL_RFE;
 461                 writel(flow, ioaddr + GMAC_RX_FLOW_CTRL);
 462         }
 463         if (fc & FLOW_TX) {
 464                 pr_debug("\tTransmit Flow-Control ON\n");
 465
 466                 if (duplex)
 467                         pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
 468
 469                 for (queue = 0; queue < tx_cnt; queue++) {
 470                         flow |= GMAC_TX_FLOW_CTRL_TFE;
 471
 472                         if (duplex)
 473                                 flow |=
 474                                 (pause_time << GMAC_TX_FLOW_CTRL_PT_SHIFT);
 475
 476                         writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
 477                 }
 478         }
 479 }
 480
 481 static void dwmac4_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
 482                             bool loopback)
 483 {
 484         dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
 485 }
 486
 487 static void dwmac4_rane(void __iomem *ioaddr, bool restart)
 488 {
 489         dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
 490 }
 491
 492 static void dwmac4_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
 493 {
 494         dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
 495 }
 496
 497 /* RGMII or SMII interface */
 498 static void dwmac4_phystatus(void __iomem *ioaddr, struct stmmac_extra_stats *x)
 499 {
 500         u32 status;
 501
 502         status = readl(ioaddr + GMAC_PHYIF_CONTROL_STATUS);
 503         x->irq_rgmii_n++;
 504
 505         /* Check the link status */
 506         if (status & GMAC_PHYIF_CTRLSTATUS_LNKSTS) {
 507                 int speed_value;
 508
 509                 x->pcs_link = 1;
 510
 511                 speed_value = ((status & GMAC_PHYIF_CTRLSTATUS_SPEED) >>
 512                                GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT);
 513                 if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_125)
 514                         x->pcs_speed = SPEED_1000;
 515                 else if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_25)
 516                         x->pcs_speed = SPEED_100;
 517                 else
 518                         x->pcs_speed = SPEED_10;
 519
 520                 x->pcs_duplex = (status & GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK);
 521
 522                 pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
 523                         x->pcs_duplex ? "Full" : "Half");
 524         } else {
 525                 x->pcs_link = 0;
 526                 pr_info("Link is Down\n");
 527         }
 528 }
 529
 530 static int dwmac4_irq_mtl_status(struct mac_device_info *hw, u32 chan)
 531 {
 532         void __iomem *ioaddr = hw->pcsr;
 533         u32 mtl_int_qx_status;
 534         int ret = 0;
 535
 536         mtl_int_qx_status = readl(ioaddr + MTL_INT_STATUS);
 537
 538         /* Check MTL Interrupt */
 539         if (mtl_int_qx_status & MTL_INT_QX(chan)) {
 540                 /* read Queue x Interrupt status */
 541                 u32 status = readl(ioaddr + MTL_CHAN_INT_CTRL(chan));
 542
 543                 if (status & MTL_RX_OVERFLOW_INT) {
 544                         /*  clear Interrupt */
 545                         writel(status | MTL_RX_OVERFLOW_INT,
 546                                ioaddr + MTL_CHAN_INT_CTRL(chan));
 547                         ret = CORE_IRQ_MTL_RX_OVERFLOW;
 548                 }
 549         }
 550
 551         return ret;
 552 }
 553
 554 static int dwmac4_irq_status(struct mac_device_info *hw,
 555                              struct stmmac_extra_stats *x)
 556 {
 557         void __iomem *ioaddr = hw->pcsr;
 558         u32 intr_status;
 559         int ret = 0;
 560
 561         intr_status = readl(ioaddr + GMAC_INT_STATUS);
 562
 563         /* Not used events (e.g. MMC interrupts) are not handled. */
 564         if ((intr_status & mmc_tx_irq))
 565                 x->mmc_tx_irq_n++;
 566         if (unlikely(intr_status & mmc_rx_irq))
 567                 x->mmc_rx_irq_n++;
 568         if (unlikely(intr_status & mmc_rx_csum_offload_irq))
 569                 x->mmc_rx_csum_offload_irq_n++;
 570         /* Clear the PMT bits 5 and 6 by reading the PMT status reg */
 571         if (unlikely(intr_status & pmt_irq)) {
 572                 readl(ioaddr + GMAC_PMT);
 573                 x->irq_receive_pmt_irq_n++;
 574         }
 575
 576         dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
 577         if (intr_status & PCS_RGSMIIIS_IRQ)
 578                 dwmac4_phystatus(ioaddr, x);
 579
 580         return ret;
 581 }
 582
 583 static void dwmac4_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x,
 584                          u32 rx_queues, u32 tx_queues)
 585 {
 586         u32 value;
 587         u32 queue;
 588
 589         for (queue = 0; queue < tx_queues; queue++) {
 590                 value = readl(ioaddr + MTL_CHAN_TX_DEBUG(queue));
 591
 592                 if (value & MTL_DEBUG_TXSTSFSTS)
 593                         x->mtl_tx_status_fifo_full++;
 594                 if (value & MTL_DEBUG_TXFSTS)
 595                         x->mtl_tx_fifo_not_empty++;
 596                 if (value & MTL_DEBUG_TWCSTS)
 597                         x->mmtl_fifo_ctrl++;
 598                 if (value & MTL_DEBUG_TRCSTS_MASK) {
 599                         u32 trcsts = (value & MTL_DEBUG_TRCSTS_MASK)
 600                                      >> MTL_DEBUG_TRCSTS_SHIFT;
 601                         if (trcsts == MTL_DEBUG_TRCSTS_WRITE)
 602                                 x->mtl_tx_fifo_read_ctrl_write++;
 603                         else if (trcsts == MTL_DEBUG_TRCSTS_TXW)
 604                                 x->mtl_tx_fifo_read_ctrl_wait++;
 605                         else if (trcsts == MTL_DEBUG_TRCSTS_READ)
 606                                 x->mtl_tx_fifo_read_ctrl_read++;
 607                         else
 608                                 x->mtl_tx_fifo_read_ctrl_idle++;
 609                 }
 610                 if (value & MTL_DEBUG_TXPAUSED)
 611                         x->mac_tx_in_pause++;
 612         }
 613
 614         for (queue = 0; queue < rx_queues; queue++) {
 615                 value = readl(ioaddr + MTL_CHAN_RX_DEBUG(queue));
 616
 617                 if (value & MTL_DEBUG_RXFSTS_MASK) {
 618                         u32 rxfsts = (value & MTL_DEBUG_RXFSTS_MASK)
 619                                      >> MTL_DEBUG_RRCSTS_SHIFT;
 620
 621                         if (rxfsts == MTL_DEBUG_RXFSTS_FULL)
 622                                 x->mtl_rx_fifo_fill_level_full++;
 623                         else if (rxfsts == MTL_DEBUG_RXFSTS_AT)
 624                                 x->mtl_rx_fifo_fill_above_thresh++;
 625                         else if (rxfsts == MTL_DEBUG_RXFSTS_BT)
 626                                 x->mtl_rx_fifo_fill_below_thresh++;
 627                         else
 628                                 x->mtl_rx_fifo_fill_level_empty++;
 629                 }
 630                 if (value & MTL_DEBUG_RRCSTS_MASK) {
 631                         u32 rrcsts = (value & MTL_DEBUG_RRCSTS_MASK) >>
 632                                      MTL_DEBUG_RRCSTS_SHIFT;
 633
 634                         if (rrcsts == MTL_DEBUG_RRCSTS_FLUSH)
 635                                 x->mtl_rx_fifo_read_ctrl_flush++;
 636                         else if (rrcsts == MTL_DEBUG_RRCSTS_RSTAT)
 637                                 x->mtl_rx_fifo_read_ctrl_read_data++;
 638                         else if (rrcsts == MTL_DEBUG_RRCSTS_RDATA)
 639                                 x->mtl_rx_fifo_read_ctrl_status++;
 640                         else
 641                                 x->mtl_rx_fifo_read_ctrl_idle++;
 642                 }
 643                 if (value & MTL_DEBUG_RWCSTS)
 644                         x->mtl_rx_fifo_ctrl_active++;
 645         }
 646
 647         /* GMAC debug */
 648         value = readl(ioaddr + GMAC_DEBUG);
 649
 650         if (value & GMAC_DEBUG_TFCSTS_MASK) {
 651                 u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
 652                               >> GMAC_DEBUG_TFCSTS_SHIFT;
 653
 654                 if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
 655                         x->mac_tx_frame_ctrl_xfer++;
 656                 else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
 657                         x->mac_tx_frame_ctrl_pause++;
 658                 else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
 659                         x->mac_tx_frame_ctrl_wait++;
 660                 else
 661                         x->mac_tx_frame_ctrl_idle++;
 662         }
 663         if (value & GMAC_DEBUG_TPESTS)
 664                 x->mac_gmii_tx_proto_engine++;
 665         if (value & GMAC_DEBUG_RFCFCSTS_MASK)
 666                 x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
 667                                             >> GMAC_DEBUG_RFCFCSTS_SHIFT;
 668         if (value & GMAC_DEBUG_RPESTS)
 669                 x->mac_gmii_rx_proto_engine++;
 670 }
 671
 672 static const struct stmmac_ops dwmac4_ops = {
 673         .core_init = dwmac4_core_init,
 674         .set_mac = stmmac_set_mac,
 675         .rx_ipc = dwmac4_rx_ipc_enable,
 676         .rx_queue_enable = dwmac4_rx_queue_enable,
 677         .rx_queue_prio = dwmac4_rx_queue_priority,
 678         .tx_queue_prio = dwmac4_tx_queue_priority,
 679         .rx_queue_routing = dwmac4_tx_queue_routing,
 680         .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
 681         .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
 682         .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
 683         .map_mtl_to_dma = dwmac4_map_mtl_dma,
 684         .config_cbs = dwmac4_config_cbs,
 685         .dump_regs = dwmac4_dump_regs,
 686         .host_irq_status = dwmac4_irq_status,
 687         .host_mtl_irq_status = dwmac4_irq_mtl_status,
 688         .flow_ctrl = dwmac4_flow_ctrl,
 689         .pmt = dwmac4_pmt,
 690         .set_umac_addr = dwmac4_set_umac_addr,
 691         .get_umac_addr = dwmac4_get_umac_addr,
 692         .set_eee_mode = dwmac4_set_eee_mode,
 693         .reset_eee_mode = dwmac4_reset_eee_mode,
 694         .set_eee_timer = dwmac4_set_eee_timer,
 695         .set_eee_pls = dwmac4_set_eee_pls,
 696         .pcs_ctrl_ane = dwmac4_ctrl_ane,
 697         .pcs_rane = dwmac4_rane,
 698         .pcs_get_adv_lp = dwmac4_get_adv_lp,
 699         .debug = dwmac4_debug,
 700         .set_filter = dwmac4_set_filter,
 701 };
 702
 703 static const struct stmmac_ops dwmac410_ops = {
 704         .core_init = dwmac4_core_init,
 705         .set_mac = stmmac_dwmac4_set_mac,
 706         .rx_ipc = dwmac4_rx_ipc_enable,
 707         .rx_queue_enable = dwmac4_rx_queue_enable,
 708         .rx_queue_prio = dwmac4_rx_queue_priority,
 709         .tx_queue_prio = dwmac4_tx_queue_priority,
 710         .rx_queue_routing = dwmac4_tx_queue_routing,
 711         .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
 712         .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
 713         .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
 714         .map_mtl_to_dma = dwmac4_map_mtl_dma,
 715         .config_cbs = dwmac4_config_cbs,
 716         .dump_regs = dwmac4_dump_regs,
 717         .host_irq_status = dwmac4_irq_status,
 718         .host_mtl_irq_status = dwmac4_irq_mtl_status,
 719         .flow_ctrl = dwmac4_flow_ctrl,
 720         .pmt = dwmac4_pmt,
 721         .set_umac_addr = dwmac4_set_umac_addr,
 722         .get_umac_addr = dwmac4_get_umac_addr,
 723         .set_eee_mode = dwmac4_set_eee_mode,
 724         .reset_eee_mode = dwmac4_reset_eee_mode,
 725         .set_eee_timer = dwmac4_set_eee_timer,
 726         .set_eee_pls = dwmac4_set_eee_pls,
 727         .pcs_ctrl_ane = dwmac4_ctrl_ane,
 728         .pcs_rane = dwmac4_rane,
 729         .pcs_get_adv_lp = dwmac4_get_adv_lp,
 730         .debug = dwmac4_debug,
 731         .set_filter = dwmac4_set_filter,
 732 };
 733
 734 struct mac_device_info *dwmac4_setup(void __iomem *ioaddr, int mcbins,
 735                                      int perfect_uc_entries, int *synopsys_id)
 736 {
 737         struct mac_device_info *mac;
 738         u32 hwid = readl(ioaddr + GMAC_VERSION);
 739
 740         mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
 741         if (!mac)
 742                 return NULL;
 743
 744         mac->pcsr = ioaddr;
 745         mac->multicast_filter_bins = mcbins;
 746         mac->unicast_filter_entries = perfect_uc_entries;
 747         mac->mcast_bits_log2 = 0;
 748
 749         if (mac->multicast_filter_bins)
 750                 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
 751
 752         mac->link.duplex = GMAC_CONFIG_DM;
 753         mac->link.speed10 = GMAC_CONFIG_PS;
 754         mac->link.speed100 = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
 755         mac->link.speed1000 = 0;
 756         mac->link.speed_mask = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
 757         mac->mii.addr = GMAC_MDIO_ADDR;
 758         mac->mii.data = GMAC_MDIO_DATA;
 759         mac->mii.addr_shift = 21;
 760         mac->mii.addr_mask = GENMASK(25, 21);
 761         mac->mii.reg_shift = 16;
 762         mac->mii.reg_mask = GENMASK(20, 16);
 763         mac->mii.clk_csr_shift = 8;
 764         mac->mii.clk_csr_mask = GENMASK(11, 8);
 765
 766         /* Get and dump the chip ID */
 767         *synopsys_id = stmmac_get_synopsys_id(hwid);
 768
 769         if (*synopsys_id > DWMAC_CORE_4_00)
 770                 mac->dma = &dwmac410_dma_ops;
 771         else
 772                 mac->dma = &dwmac4_dma_ops;
 773
 774         if (*synopsys_id >= DWMAC_CORE_4_00)
 775                 mac->mac = &dwmac410_ops;
 776         else
 777                 mac->mac = &dwmac4_ops;
 778
 779         return mac;
 780 }