drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c

   1 /*
   2  * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
   3  * DWC Ether MAC version 4.00  has been used for developing this code.
   4  *
   5  * This only implements the mac core functions for this chip.
   6  *
   7  * Copyright (C) 2015  STMicroelectronics Ltd
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms and conditions of the GNU General Public License,
  11  * version 2, as published by the Free Software Foundation.
  12  *
  13  * Author: Alexandre Torgue <alexandre.torgue@st.com>
  14  */
  15
  16 #include <linux/crc32.h>
  17 #include <linux/slab.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/io.h>
  20 #include <net/dsa.h>
  21 #include "stmmac_pcs.h"
  22 #include "dwmac4.h"
  23
  24 static void dwmac4_core_init(struct mac_device_info *hw,
  25                              struct net_device *dev)
  26 {
  27         void __iomem *ioaddr = hw->pcsr;
  28         u32 value = readl(ioaddr + GMAC_CONFIG);
  29         int mtu = dev->mtu;
  30
  31         value |= GMAC_CORE_INIT;
  32
  33         /* Clear ACS bit because Ethernet switch tagging formats such as
  34          * Broadcom tags can look like invalid LLC/SNAP packets and cause the
  35          * hardware to truncate packets on reception.
  36          */
  37         if (netdev_uses_dsa(dev))
  38                 value &= ~GMAC_CONFIG_ACS;
  39
  40         if (mtu > 1500)
  41                 value |= GMAC_CONFIG_2K;
  42         if (mtu > 2000)
  43                 value |= GMAC_CONFIG_JE;
  44
  45         if (hw->ps) {
  46                 value |= GMAC_CONFIG_TE;
  47
  48                 value &= hw->link.speed_mask;
  49                 switch (hw->ps) {
  50                 case SPEED_1000:
  51                         value |= hw->link.speed1000;
  52                         break;
  53                 case SPEED_100:
  54                         value |= hw->link.speed100;
  55                         break;
  56                 case SPEED_10:
  57                         value |= hw->link.speed10;
  58                         break;
  59                 }
  60         }
  61
  62         writel(value, ioaddr + GMAC_CONFIG);
  63
  64         /* Enable GMAC interrupts */
  65         value = GMAC_INT_DEFAULT_ENABLE;
  66         if (hw->pmt)
  67                 value |= GMAC_INT_PMT_EN;
  68         if (hw->pcs)
  69                 value |= GMAC_PCS_IRQ_DEFAULT;
  70
  71         writel(value, ioaddr + GMAC_INT_EN);
  72 }
  73
  74 static void dwmac4_rx_queue_enable(struct mac_device_info *hw,
  75                                    u8 mode, u32 queue)
  76 {
  77         void __iomem *ioaddr = hw->pcsr;
  78         u32 value = readl(ioaddr + GMAC_RXQ_CTRL0);
  79
  80         value &= GMAC_RX_QUEUE_CLEAR(queue);
  81         if (mode == MTL_QUEUE_AVB)
  82                 value |= GMAC_RX_AV_QUEUE_ENABLE(queue);
  83         else if (mode == MTL_QUEUE_DCB)
  84                 value |= GMAC_RX_DCB_QUEUE_ENABLE(queue);
  85
  86         writel(value, ioaddr + GMAC_RXQ_CTRL0);
  87 }
  88
  89 static void dwmac4_rx_queue_priority(struct mac_device_info *hw,
  90                                      u32 prio, u32 queue)
  91 {
  92         void __iomem *ioaddr = hw->pcsr;
  93         u32 base_register;
  94         u32 value;
  95
  96         base_register = (queue < 4) ? GMAC_RXQ_CTRL2 : GMAC_RXQ_CTRL3;
  97
  98         value = readl(ioaddr + base_register);
  99
 100         value &= ~GMAC_RXQCTRL_PSRQX_MASK(queue);
 101         value |= (prio << GMAC_RXQCTRL_PSRQX_SHIFT(queue)) &
 102                                                 GMAC_RXQCTRL_PSRQX_MASK(queue);
 103         writel(value, ioaddr + base_register);
 104 }
 105
 106 static void dwmac4_tx_queue_priority(struct mac_device_info *hw,
 107                                      u32 prio, u32 queue)
 108 {
 109         void __iomem *ioaddr = hw->pcsr;
 110         u32 base_register;
 111         u32 value;
 112
 113         base_register = (queue < 4) ? GMAC_TXQ_PRTY_MAP0 : GMAC_TXQ_PRTY_MAP1;
 114
 115         value = readl(ioaddr + base_register);
 116
 117         value &= ~GMAC_TXQCTRL_PSTQX_MASK(queue);
 118         value |= (prio << GMAC_TXQCTRL_PSTQX_SHIFT(queue)) &
 119                                                 GMAC_TXQCTRL_PSTQX_MASK(queue);
 120
 121         writel(value, ioaddr + base_register);
 122 }
 123
 124 static void dwmac4_tx_queue_routing(struct mac_device_info *hw,
 125                                     u8 packet, u32 queue)
 126 {
 127         void __iomem *ioaddr = hw->pcsr;
 128         u32 value;
 129
 130         static const struct stmmac_rx_routing route_possibilities[] = {
 131                 { GMAC_RXQCTRL_AVCPQ_MASK, GMAC_RXQCTRL_AVCPQ_SHIFT },
 132                 { GMAC_RXQCTRL_PTPQ_MASK, GMAC_RXQCTRL_PTPQ_SHIFT },
 133                 { GMAC_RXQCTRL_DCBCPQ_MASK, GMAC_RXQCTRL_DCBCPQ_SHIFT },
 134                 { GMAC_RXQCTRL_UPQ_MASK, GMAC_RXQCTRL_UPQ_SHIFT },
 135                 { GMAC_RXQCTRL_MCBCQ_MASK, GMAC_RXQCTRL_MCBCQ_SHIFT },
 136         };
 137
 138         value = readl(ioaddr + GMAC_RXQ_CTRL1);
 139
 140         /* routing configuration */
 141         value &= ~route_possibilities[packet - 1].reg_mask;
 142         value |= (queue << route_possibilities[packet-1].reg_shift) &
 143                  route_possibilities[packet - 1].reg_mask;
 144
 145         /* some packets require extra ops */
 146         if (packet == PACKET_AVCPQ) {
 147                 value &= ~GMAC_RXQCTRL_TACPQE;
 148                 value |= 0x1 << GMAC_RXQCTRL_TACPQE_SHIFT;
 149         } else if (packet == PACKET_MCBCQ) {
 150                 value &= ~GMAC_RXQCTRL_MCBCQEN;
 151                 value |= 0x1 << GMAC_RXQCTRL_MCBCQEN_SHIFT;
 152         }
 153
 154         writel(value, ioaddr + GMAC_RXQ_CTRL1);
 155 }
 156
 157 static void dwmac4_prog_mtl_rx_algorithms(struct mac_device_info *hw,
 158                                           u32 rx_alg)
 159 {
 160         void __iomem *ioaddr = hw->pcsr;
 161         u32 value = readl(ioaddr + MTL_OPERATION_MODE);
 162
 163         value &= ~MTL_OPERATION_RAA;
 164         switch (rx_alg) {
 165         case MTL_RX_ALGORITHM_SP:
 166                 value |= MTL_OPERATION_RAA_SP;
 167                 break;
 168         case MTL_RX_ALGORITHM_WSP:
 169                 value |= MTL_OPERATION_RAA_WSP;
 170                 break;
 171         default:
 172                 break;
 173         }
 174
 175         writel(value, ioaddr + MTL_OPERATION_MODE);
 176 }
 177
 178 static void dwmac4_prog_mtl_tx_algorithms(struct mac_device_info *hw,
 179                                           u32 tx_alg)
 180 {
 181         void __iomem *ioaddr = hw->pcsr;
 182         u32 value = readl(ioaddr + MTL_OPERATION_MODE);
 183
 184         value &= ~MTL_OPERATION_SCHALG_MASK;
 185         switch (tx_alg) {
 186         case MTL_TX_ALGORITHM_WRR:
 187                 value |= MTL_OPERATION_SCHALG_WRR;
 188                 break;
 189         case MTL_TX_ALGORITHM_WFQ:
 190                 value |= MTL_OPERATION_SCHALG_WFQ;
 191                 break;
 192         case MTL_TX_ALGORITHM_DWRR:
 193                 value |= MTL_OPERATION_SCHALG_DWRR;
 194                 break;
 195         case MTL_TX_ALGORITHM_SP:
 196                 value |= MTL_OPERATION_SCHALG_SP;
 197                 break;
 198         default:
 199                 break;
 200         }
 201 }
 202
 203 static void dwmac4_set_mtl_tx_queue_weight(struct mac_device_info *hw,
 204                                            u32 weight, u32 queue)
 205 {
 206         void __iomem *ioaddr = hw->pcsr;
 207         u32 value = readl(ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));
 208
 209         value &= ~MTL_TXQ_WEIGHT_ISCQW_MASK;
 210         value |= weight & MTL_TXQ_WEIGHT_ISCQW_MASK;
 211         writel(value, ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));
 212 }
 213
 214 static void dwmac4_map_mtl_dma(struct mac_device_info *hw, u32 queue, u32 chan)
 215 {
 216         void __iomem *ioaddr = hw->pcsr;
 217         u32 value;
 218
 219         if (queue < 4)
 220                 value = readl(ioaddr + MTL_RXQ_DMA_MAP0);
 221         else
 222                 value = readl(ioaddr + MTL_RXQ_DMA_MAP1);
 223
 224         if (queue == 0 || queue == 4) {
 225                 value &= ~MTL_RXQ_DMA_Q04MDMACH_MASK;
 226                 value |= MTL_RXQ_DMA_Q04MDMACH(chan);
 227         } else {
 228                 value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue);
 229                 value |= MTL_RXQ_DMA_QXMDMACH(chan, queue);
 230         }
 231
 232         if (queue < 4)
 233                 writel(value, ioaddr + MTL_RXQ_DMA_MAP0);
 234         else
 235                 writel(value, ioaddr + MTL_RXQ_DMA_MAP1);
 236 }
 237
 238 static void dwmac4_config_cbs(struct mac_device_info *hw,
 239                               u32 send_slope, u32 idle_slope,
 240                               u32 high_credit, u32 low_credit, u32 queue)
 241 {
 242         void __iomem *ioaddr = hw->pcsr;
 243         u32 value;
 244
 245         pr_debug("Queue %d configured as AVB. Parameters:\n", queue);
 246         pr_debug("\tsend_slope: 0x%08x\n", send_slope);
 247         pr_debug("\tidle_slope: 0x%08x\n", idle_slope);
 248         pr_debug("\thigh_credit: 0x%08x\n", high_credit);
 249         pr_debug("\tlow_credit: 0x%08x\n", low_credit);
 250
 251         /* enable AV algorithm */
 252         value = readl(ioaddr + MTL_ETSX_CTRL_BASE_ADDR(queue));
 253         value |= MTL_ETS_CTRL_AVALG;
 254         value |= MTL_ETS_CTRL_CC;
 255         writel(value, ioaddr + MTL_ETSX_CTRL_BASE_ADDR(queue));
 256
 257         /* configure send slope */
 258         value = readl(ioaddr + MTL_SEND_SLP_CREDX_BASE_ADDR(queue));
 259         value &= ~MTL_SEND_SLP_CRED_SSC_MASK;
 260         value |= send_slope & MTL_SEND_SLP_CRED_SSC_MASK;
 261         writel(value, ioaddr + MTL_SEND_SLP_CREDX_BASE_ADDR(queue));
 262
 263         /* configure idle slope (same register as tx weight) */
 264         dwmac4_set_mtl_tx_queue_weight(hw, idle_slope, queue);
 265
 266         /* configure high credit */
 267         value = readl(ioaddr + MTL_HIGH_CREDX_BASE_ADDR(queue));
 268         value &= ~MTL_HIGH_CRED_HC_MASK;
 269         value |= high_credit & MTL_HIGH_CRED_HC_MASK;
 270         writel(value, ioaddr + MTL_HIGH_CREDX_BASE_ADDR(queue));
 271
 272         /* configure high credit */
 273         value = readl(ioaddr + MTL_LOW_CREDX_BASE_ADDR(queue));
 274         value &= ~MTL_HIGH_CRED_LC_MASK;
 275         value |= low_credit & MTL_HIGH_CRED_LC_MASK;
 276         writel(value, ioaddr + MTL_LOW_CREDX_BASE_ADDR(queue));
 277 }
 278
 279 static void dwmac4_dump_regs(struct mac_device_info *hw, u32 *reg_space)
 280 {
 281         void __iomem *ioaddr = hw->pcsr;
 282         int i;
 283
 284         for (i = 0; i < GMAC_REG_NUM; i++)
 285                 reg_space[i] = readl(ioaddr + i * 4);
 286 }
 287
 288 static int dwmac4_rx_ipc_enable(struct mac_device_info *hw)
 289 {
 290         void __iomem *ioaddr = hw->pcsr;
 291         u32 value = readl(ioaddr + GMAC_CONFIG);
 292
 293         if (hw->rx_csum)
 294                 value |= GMAC_CONFIG_IPC;
 295         else
 296                 value &= ~GMAC_CONFIG_IPC;
 297
 298         writel(value, ioaddr + GMAC_CONFIG);
 299
 300         value = readl(ioaddr + GMAC_CONFIG);
 301
 302         return !!(value & GMAC_CONFIG_IPC);
 303 }
 304
 305 static void dwmac4_pmt(struct mac_device_info *hw, unsigned long mode)
 306 {
 307         void __iomem *ioaddr = hw->pcsr;
 308         unsigned int pmt = 0;
 309         u32 config;
 310
 311         if (mode & WAKE_MAGIC) {
 312                 pr_debug("GMAC: WOL Magic frame\n");
 313                 pmt |= power_down | magic_pkt_en;
 314         }
 315         if (mode & WAKE_UCAST) {
 316                 pr_debug("GMAC: WOL on global unicast\n");
 317                 pmt |= power_down | global_unicast | wake_up_frame_en;
 318         }
 319
 320         if (pmt) {
 321                 /* The receiver must be enabled for WOL before powering down */
 322                 config = readl(ioaddr + GMAC_CONFIG);
 323                 config |= GMAC_CONFIG_RE;
 324                 writel(config, ioaddr + GMAC_CONFIG);
 325         }
 326         writel(pmt, ioaddr + GMAC_PMT);
 327 }
 328
 329 static void dwmac4_set_umac_addr(struct mac_device_info *hw,
 330                                  unsigned char *addr, unsigned int reg_n)
 331 {
 332         void __iomem *ioaddr = hw->pcsr;
 333
 334         stmmac_dwmac4_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
 335                                    GMAC_ADDR_LOW(reg_n));
 336 }
 337
 338 static void dwmac4_get_umac_addr(struct mac_device_info *hw,
 339                                  unsigned char *addr, unsigned int reg_n)
 340 {
 341         void __iomem *ioaddr = hw->pcsr;
 342
 343         stmmac_dwmac4_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
 344                                    GMAC_ADDR_LOW(reg_n));
 345 }
 346
 347 static void dwmac4_set_eee_mode(struct mac_device_info *hw,
 348                                 bool en_tx_lpi_clockgating)
 349 {
 350         void __iomem *ioaddr = hw->pcsr;
 351         u32 value;
 352
 353         /* Enable the link status receive on RGMII, SGMII ore SMII
 354          * receive path and instruct the transmit to enter in LPI
 355          * state.
 356          */
 357         value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 358         value |= GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA;
 359
 360         if (en_tx_lpi_clockgating)
 361                 value |= GMAC4_LPI_CTRL_STATUS_LPITCSE;
 362
 363         writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 364 }
 365
 366 static void dwmac4_reset_eee_mode(struct mac_device_info *hw)
 367 {
 368         void __iomem *ioaddr = hw->pcsr;
 369         u32 value;
 370
 371         value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 372         value &= ~(GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA);
 373         writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 374 }
 375
 376 static void dwmac4_set_eee_pls(struct mac_device_info *hw, int link)
 377 {
 378         void __iomem *ioaddr = hw->pcsr;
 379         u32 value;
 380
 381         value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 382
 383         if (link)
 384                 value |= GMAC4_LPI_CTRL_STATUS_PLS;
 385         else
 386                 value &= ~GMAC4_LPI_CTRL_STATUS_PLS;
 387
 388         writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 389 }
 390
 391 static void dwmac4_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
 392 {
 393         void __iomem *ioaddr = hw->pcsr;
 394         int value = ((tw & 0xffff)) | ((ls & 0x3ff) << 16);
 395
 396         /* Program the timers in the LPI timer control register:
 397          * LS: minimum time (ms) for which the link
 398          *  status from PHY should be ok before transmitting
 399          *  the LPI pattern.
 400          * TW: minimum time (us) for which the core waits
 401          *  after it has stopped transmitting the LPI pattern.
 402          */
 403         writel(value, ioaddr + GMAC4_LPI_TIMER_CTRL);
 404 }
 405
 406 static void dwmac4_set_filter(struct mac_device_info *hw,
 407                               struct net_device *dev)
 408 {
 409         void __iomem *ioaddr = (void __iomem *)dev->base_addr;
 410         unsigned int value = 0;
 411
 412         if (dev->flags & IFF_PROMISC) {
 413                 value = GMAC_PACKET_FILTER_PR;
 414         } else if ((dev->flags & IFF_ALLMULTI) ||
 415                         (netdev_mc_count(dev) > HASH_TABLE_SIZE)) {
 416                 /* Pass all multi */
 417                 value = GMAC_PACKET_FILTER_PM;
 418                 /* Set the 64 bits of the HASH tab. To be updated if taller
 419                  * hash table is used
 420                  */
 421                 writel(0xffffffff, ioaddr + GMAC_HASH_TAB_0_31);
 422                 writel(0xffffffff, ioaddr + GMAC_HASH_TAB_32_63);
 423         } else if (!netdev_mc_empty(dev)) {
 424                 u32 mc_filter[2];
 425                 struct netdev_hw_addr *ha;
 426
 427                 /* Hash filter for multicast */
 428                 value = GMAC_PACKET_FILTER_HMC;
 429
 430                 memset(mc_filter, 0, sizeof(mc_filter));
 431                 netdev_for_each_mc_addr(ha, dev) {
 432                         /* The upper 6 bits of the calculated CRC are used to
 433                          * index the content of the Hash Table Reg 0 and 1.
 434                          */
 435                         int bit_nr =
 436                                 (bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26);
 437                         /* The most significant bit determines the register
 438                          * to use while the other 5 bits determines the bit
 439                          * within the selected register
 440                          */
 441                         mc_filter[bit_nr >> 5] |= (1 << (bit_nr & 0x1F));
 442                 }
 443                 writel(mc_filter[0], ioaddr + GMAC_HASH_TAB_0_31);
 444                 writel(mc_filter[1], ioaddr + GMAC_HASH_TAB_32_63);
 445         }
 446
 447         /* Handle multiple unicast addresses */
 448         if (netdev_uc_count(dev) > GMAC_MAX_PERFECT_ADDRESSES) {
 449                 /* Switch to promiscuous mode if more than 128 addrs
 450                  * are required
 451                  */
 452                 value |= GMAC_PACKET_FILTER_PR;
 453         } else if (!netdev_uc_empty(dev)) {
 454                 int reg = 1;
 455                 struct netdev_hw_addr *ha;
 456
 457                 netdev_for_each_uc_addr(ha, dev) {
 458                         dwmac4_set_umac_addr(hw, ha->addr, reg);
 459                         reg++;
 460                 }
 461         }
 462
 463         writel(value, ioaddr + GMAC_PACKET_FILTER);
 464 }
 465
 466 static void dwmac4_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
 467                              unsigned int fc, unsigned int pause_time,
 468                              u32 tx_cnt)
 469 {
 470         void __iomem *ioaddr = hw->pcsr;
 471         unsigned int flow = 0;
 472         u32 queue = 0;
 473
 474         pr_debug("GMAC Flow-Control:\n");
 475         if (fc & FLOW_RX) {
 476                 pr_debug("\tReceive Flow-Control ON\n");
 477                 flow |= GMAC_RX_FLOW_CTRL_RFE;
 478                 writel(flow, ioaddr + GMAC_RX_FLOW_CTRL);
 479         }
 480         if (fc & FLOW_TX) {
 481                 pr_debug("\tTransmit Flow-Control ON\n");
 482
 483                 if (duplex)
 484                         pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
 485
 486                 for (queue = 0; queue < tx_cnt; queue++) {
 487                         flow |= GMAC_TX_FLOW_CTRL_TFE;
 488
 489                         if (duplex)
 490                                 flow |=
 491                                 (pause_time << GMAC_TX_FLOW_CTRL_PT_SHIFT);
 492
 493                         writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
 494                 }
 495         }
 496 }
 497
 498 static void dwmac4_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
 499                             bool loopback)
 500 {
 501         dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
 502 }
 503
 504 static void dwmac4_rane(void __iomem *ioaddr, bool restart)
 505 {
 506         dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
 507 }
 508
 509 static void dwmac4_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
 510 {
 511         dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
 512 }
 513
 514 /* RGMII or SMII interface */
 515 static void dwmac4_phystatus(void __iomem *ioaddr, struct stmmac_extra_stats *x)
 516 {
 517         u32 status;
 518
 519         status = readl(ioaddr + GMAC_PHYIF_CONTROL_STATUS);
 520         x->irq_rgmii_n++;
 521
 522         /* Check the link status */
 523         if (status & GMAC_PHYIF_CTRLSTATUS_LNKSTS) {
 524                 int speed_value;
 525
 526                 x->pcs_link = 1;
 527
 528                 speed_value = ((status & GMAC_PHYIF_CTRLSTATUS_SPEED) >>
 529                                GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT);
 530                 if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_125)
 531                         x->pcs_speed = SPEED_1000;
 532                 else if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_25)
 533                         x->pcs_speed = SPEED_100;
 534                 else
 535                         x->pcs_speed = SPEED_10;
 536
 537                 x->pcs_duplex = (status & GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK);
 538
 539                 pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
 540                         x->pcs_duplex ? "Full" : "Half");
 541         } else {
 542                 x->pcs_link = 0;
 543                 pr_info("Link is Down\n");
 544         }
 545 }
 546
 547 static int dwmac4_irq_mtl_status(struct mac_device_info *hw, u32 chan)
 548 {
 549         void __iomem *ioaddr = hw->pcsr;
 550         u32 mtl_int_qx_status;
 551         int ret = 0;
 552
 553         mtl_int_qx_status = readl(ioaddr + MTL_INT_STATUS);
 554
 555         /* Check MTL Interrupt */
 556         if (mtl_int_qx_status & MTL_INT_QX(chan)) {
 557                 /* read Queue x Interrupt status */
 558                 u32 status = readl(ioaddr + MTL_CHAN_INT_CTRL(chan));
 559
 560                 if (status & MTL_RX_OVERFLOW_INT) {
 561                         /*  clear Interrupt */
 562                         writel(status | MTL_RX_OVERFLOW_INT,
 563                                ioaddr + MTL_CHAN_INT_CTRL(chan));
 564                         ret = CORE_IRQ_MTL_RX_OVERFLOW;
 565                 }
 566         }
 567
 568         return ret;
 569 }
 570
 571 static int dwmac4_irq_status(struct mac_device_info *hw,
 572                              struct stmmac_extra_stats *x)
 573 {
 574         void __iomem *ioaddr = hw->pcsr;
 575         u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
 576         u32 intr_enable = readl(ioaddr + GMAC_INT_EN);
 577         int ret = 0;
 578
 579         /* Discard disabled bits */
 580         intr_status &= intr_enable;
 581
 582         /* Not used events (e.g. MMC interrupts) are not handled. */
 583         if ((intr_status & mmc_tx_irq))
 584                 x->mmc_tx_irq_n++;
 585         if (unlikely(intr_status & mmc_rx_irq))
 586                 x->mmc_rx_irq_n++;
 587         if (unlikely(intr_status & mmc_rx_csum_offload_irq))
 588                 x->mmc_rx_csum_offload_irq_n++;
 589         /* Clear the PMT bits 5 and 6 by reading the PMT status reg */
 590         if (unlikely(intr_status & pmt_irq)) {
 591                 readl(ioaddr + GMAC_PMT);
 592                 x->irq_receive_pmt_irq_n++;
 593         }
 594
 595         /* MAC tx/rx EEE LPI entry/exit interrupts */
 596         if (intr_status & lpi_irq) {
 597                 /* Clear LPI interrupt by reading MAC_LPI_Control_Status */
 598                 u32 status = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 599
 600                 if (status & GMAC4_LPI_CTRL_STATUS_TLPIEN) {
 601                         ret |= CORE_IRQ_TX_PATH_IN_LPI_MODE;
 602                         x->irq_tx_path_in_lpi_mode_n++;
 603                 }
 604                 if (status & GMAC4_LPI_CTRL_STATUS_TLPIEX) {
 605                         ret |= CORE_IRQ_TX_PATH_EXIT_LPI_MODE;
 606                         x->irq_tx_path_exit_lpi_mode_n++;
 607                 }
 608                 if (status & GMAC4_LPI_CTRL_STATUS_RLPIEN)
 609                         x->irq_rx_path_in_lpi_mode_n++;
 610                 if (status & GMAC4_LPI_CTRL_STATUS_RLPIEX)
 611                         x->irq_rx_path_exit_lpi_mode_n++;
 612         }
 613
 614         dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
 615         if (intr_status & PCS_RGSMIIIS_IRQ)
 616                 dwmac4_phystatus(ioaddr, x);
 617
 618         return ret;
 619 }
 620
 621 static void dwmac4_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x,
 622                          u32 rx_queues, u32 tx_queues)
 623 {
 624         u32 value;
 625         u32 queue;
 626
 627         for (queue = 0; queue < tx_queues; queue++) {
 628                 value = readl(ioaddr + MTL_CHAN_TX_DEBUG(queue));
 629
 630                 if (value & MTL_DEBUG_TXSTSFSTS)
 631                         x->mtl_tx_status_fifo_full++;
 632                 if (value & MTL_DEBUG_TXFSTS)
 633                         x->mtl_tx_fifo_not_empty++;
 634                 if (value & MTL_DEBUG_TWCSTS)
 635                         x->mmtl_fifo_ctrl++;
 636                 if (value & MTL_DEBUG_TRCSTS_MASK) {
 637                         u32 trcsts = (value & MTL_DEBUG_TRCSTS_MASK)
 638                                      >> MTL_DEBUG_TRCSTS_SHIFT;
 639                         if (trcsts == MTL_DEBUG_TRCSTS_WRITE)
 640                                 x->mtl_tx_fifo_read_ctrl_write++;
 641                         else if (trcsts == MTL_DEBUG_TRCSTS_TXW)
 642                                 x->mtl_tx_fifo_read_ctrl_wait++;
 643                         else if (trcsts == MTL_DEBUG_TRCSTS_READ)
 644                                 x->mtl_tx_fifo_read_ctrl_read++;
 645                         else
 646                                 x->mtl_tx_fifo_read_ctrl_idle++;
 647                 }
 648                 if (value & MTL_DEBUG_TXPAUSED)
 649                         x->mac_tx_in_pause++;
 650         }
 651
 652         for (queue = 0; queue < rx_queues; queue++) {
 653                 value = readl(ioaddr + MTL_CHAN_RX_DEBUG(queue));
 654
 655                 if (value & MTL_DEBUG_RXFSTS_MASK) {
 656                         u32 rxfsts = (value & MTL_DEBUG_RXFSTS_MASK)
 657                                      >> MTL_DEBUG_RRCSTS_SHIFT;
 658
 659                         if (rxfsts == MTL_DEBUG_RXFSTS_FULL)
 660                                 x->mtl_rx_fifo_fill_level_full++;
 661                         else if (rxfsts == MTL_DEBUG_RXFSTS_AT)
 662                                 x->mtl_rx_fifo_fill_above_thresh++;
 663                         else if (rxfsts == MTL_DEBUG_RXFSTS_BT)
 664                                 x->mtl_rx_fifo_fill_below_thresh++;
 665                         else
 666                                 x->mtl_rx_fifo_fill_level_empty++;
 667                 }
 668                 if (value & MTL_DEBUG_RRCSTS_MASK) {
 669                         u32 rrcsts = (value & MTL_DEBUG_RRCSTS_MASK) >>
 670                                      MTL_DEBUG_RRCSTS_SHIFT;
 671
 672                         if (rrcsts == MTL_DEBUG_RRCSTS_FLUSH)
 673                                 x->mtl_rx_fifo_read_ctrl_flush++;
 674                         else if (rrcsts == MTL_DEBUG_RRCSTS_RSTAT)
 675                                 x->mtl_rx_fifo_read_ctrl_read_data++;
 676                         else if (rrcsts == MTL_DEBUG_RRCSTS_RDATA)
 677                                 x->mtl_rx_fifo_read_ctrl_status++;
 678                         else
 679                                 x->mtl_rx_fifo_read_ctrl_idle++;
 680                 }
 681                 if (value & MTL_DEBUG_RWCSTS)
 682                         x->mtl_rx_fifo_ctrl_active++;
 683         }
 684
 685         /* GMAC debug */
 686         value = readl(ioaddr + GMAC_DEBUG);
 687
 688         if (value & GMAC_DEBUG_TFCSTS_MASK) {
 689                 u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
 690                               >> GMAC_DEBUG_TFCSTS_SHIFT;
 691
 692                 if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
 693                         x->mac_tx_frame_ctrl_xfer++;
 694                 else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
 695                         x->mac_tx_frame_ctrl_pause++;
 696                 else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
 697                         x->mac_tx_frame_ctrl_wait++;
 698                 else
 699                         x->mac_tx_frame_ctrl_idle++;
 700         }
 701         if (value & GMAC_DEBUG_TPESTS)
 702                 x->mac_gmii_tx_proto_engine++;
 703         if (value & GMAC_DEBUG_RFCFCSTS_MASK)
 704                 x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
 705                                             >> GMAC_DEBUG_RFCFCSTS_SHIFT;
 706         if (value & GMAC_DEBUG_RPESTS)
 707                 x->mac_gmii_rx_proto_engine++;
 708 }
 709
 710 static const struct stmmac_ops dwmac4_ops = {
 711         .core_init = dwmac4_core_init,
 712         .set_mac = stmmac_set_mac,
 713         .rx_ipc = dwmac4_rx_ipc_enable,
 714         .rx_queue_enable = dwmac4_rx_queue_enable,
 715         .rx_queue_prio = dwmac4_rx_queue_priority,
 716         .tx_queue_prio = dwmac4_tx_queue_priority,
 717         .rx_queue_routing = dwmac4_tx_queue_routing,
 718         .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
 719         .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
 720         .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
 721         .map_mtl_to_dma = dwmac4_map_mtl_dma,
 722         .config_cbs = dwmac4_config_cbs,
 723         .dump_regs = dwmac4_dump_regs,
 724         .host_irq_status = dwmac4_irq_status,
 725         .host_mtl_irq_status = dwmac4_irq_mtl_status,
 726         .flow_ctrl = dwmac4_flow_ctrl,
 727         .pmt = dwmac4_pmt,
 728         .set_umac_addr = dwmac4_set_umac_addr,
 729         .get_umac_addr = dwmac4_get_umac_addr,
 730         .set_eee_mode = dwmac4_set_eee_mode,
 731         .reset_eee_mode = dwmac4_reset_eee_mode,
 732         .set_eee_timer = dwmac4_set_eee_timer,
 733         .set_eee_pls = dwmac4_set_eee_pls,
 734         .pcs_ctrl_ane = dwmac4_ctrl_ane,
 735         .pcs_rane = dwmac4_rane,
 736         .pcs_get_adv_lp = dwmac4_get_adv_lp,
 737         .debug = dwmac4_debug,
 738         .set_filter = dwmac4_set_filter,
 739 };
 740
 741 static const struct stmmac_ops dwmac410_ops = {
 742         .core_init = dwmac4_core_init,
 743         .set_mac = stmmac_dwmac4_set_mac,
 744         .rx_ipc = dwmac4_rx_ipc_enable,
 745         .rx_queue_enable = dwmac4_rx_queue_enable,
 746         .rx_queue_prio = dwmac4_rx_queue_priority,
 747         .tx_queue_prio = dwmac4_tx_queue_priority,
 748         .rx_queue_routing = dwmac4_tx_queue_routing,
 749         .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
 750         .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
 751         .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
 752         .map_mtl_to_dma = dwmac4_map_mtl_dma,
 753         .config_cbs = dwmac4_config_cbs,
 754         .dump_regs = dwmac4_dump_regs,
 755         .host_irq_status = dwmac4_irq_status,
 756         .host_mtl_irq_status = dwmac4_irq_mtl_status,
 757         .flow_ctrl = dwmac4_flow_ctrl,
 758         .pmt = dwmac4_pmt,
 759         .set_umac_addr = dwmac4_set_umac_addr,
 760         .get_umac_addr = dwmac4_get_umac_addr,
 761         .set_eee_mode = dwmac4_set_eee_mode,
 762         .reset_eee_mode = dwmac4_reset_eee_mode,
 763         .set_eee_timer = dwmac4_set_eee_timer,
 764         .set_eee_pls = dwmac4_set_eee_pls,
 765         .pcs_ctrl_ane = dwmac4_ctrl_ane,
 766         .pcs_rane = dwmac4_rane,
 767         .pcs_get_adv_lp = dwmac4_get_adv_lp,
 768         .debug = dwmac4_debug,
 769         .set_filter = dwmac4_set_filter,
 770 };
 771
 772 struct mac_device_info *dwmac4_setup(void __iomem *ioaddr, int mcbins,
 773                                      int perfect_uc_entries, int *synopsys_id)
 774 {
 775         struct mac_device_info *mac;
 776         u32 hwid = readl(ioaddr + GMAC_VERSION);
 777
 778         mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
 779         if (!mac)
 780                 return NULL;
 781
 782         mac->pcsr = ioaddr;
 783         mac->multicast_filter_bins = mcbins;
 784         mac->unicast_filter_entries = perfect_uc_entries;
 785         mac->mcast_bits_log2 = 0;
 786
 787         if (mac->multicast_filter_bins)
 788                 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
 789
 790         mac->link.duplex = GMAC_CONFIG_DM;
 791         mac->link.speed10 = GMAC_CONFIG_PS;
 792         mac->link.speed100 = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
 793         mac->link.speed1000 = 0;
 794         mac->link.speed_mask = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
 795         mac->mii.addr = GMAC_MDIO_ADDR;
 796         mac->mii.data = GMAC_MDIO_DATA;
 797         mac->mii.addr_shift = 21;
 798         mac->mii.addr_mask = GENMASK(25, 21);
 799         mac->mii.reg_shift = 16;
 800         mac->mii.reg_mask = GENMASK(20, 16);
 801         mac->mii.clk_csr_shift = 8;
 802         mac->mii.clk_csr_mask = GENMASK(11, 8);
 803
 804         /* Get and dump the chip ID */
 805         *synopsys_id = stmmac_get_synopsys_id(hwid);
 806
 807         if (*synopsys_id > DWMAC_CORE_4_00)
 808                 mac->dma = &dwmac410_dma_ops;
 809         else
 810                 mac->dma = &dwmac4_dma_ops;
 811
 812         if (*synopsys_id >= DWMAC_CORE_4_00)
 813                 mac->mac = &dwmac410_ops;
 814         else
 815                 mac->mac = &dwmac4_ops;
 816
 817         return mac;
 818 }