1 /* SuperH Ethernet device driver
3 * Copyright (C) 2014 Renesas Electronics Corporation
4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2014 Renesas Solutions Corp.
6 * Copyright (C) 2013-2017 Cogent Embedded, Inc.
7 * Copyright (C) 2014 Codethink Limited
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/spinlock.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/etherdevice.h>
28 #include <linux/delay.h>
29 #include <linux/platform_device.h>
30 #include <linux/mdio-bitbang.h>
31 #include <linux/netdevice.h>
33 #include <linux/of_device.h>
34 #include <linux/of_irq.h>
35 #include <linux/of_net.h>
36 #include <linux/phy.h>
37 #include <linux/cache.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/slab.h>
41 #include <linux/ethtool.h>
42 #include <linux/if_vlan.h>
43 #include <linux/sh_eth.h>
44 #include <linux/of_mdio.h>
48 #define SH_ETH_DEF_MSG_ENABLE \
54 #define SH_ETH_OFFSET_INVALID ((u16)~0)
56 #define SH_ETH_OFFSET_DEFAULTS \
57 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
59 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
60 SH_ETH_OFFSET_DEFAULTS,
115 [TSU_CTRST] = 0x0004,
116 [TSU_FWEN0] = 0x0010,
117 [TSU_FWEN1] = 0x0014,
119 [TSU_BSYSL0] = 0x0020,
120 [TSU_BSYSL1] = 0x0024,
121 [TSU_PRISL0] = 0x0028,
122 [TSU_PRISL1] = 0x002c,
123 [TSU_FWSL0] = 0x0030,
124 [TSU_FWSL1] = 0x0034,
125 [TSU_FWSLC] = 0x0038,
126 [TSU_QTAGM0] = 0x0040,
127 [TSU_QTAGM1] = 0x0044,
129 [TSU_FWINMK] = 0x0054,
130 [TSU_ADQT0] = 0x0048,
131 [TSU_ADQT1] = 0x004c,
132 [TSU_VTAG0] = 0x0058,
133 [TSU_VTAG1] = 0x005c,
134 [TSU_ADSBSY] = 0x0060,
136 [TSU_POST1] = 0x0070,
137 [TSU_POST2] = 0x0074,
138 [TSU_POST3] = 0x0078,
139 [TSU_POST4] = 0x007c,
140 [TSU_ADRH0] = 0x0100,
156 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
157 SH_ETH_OFFSET_DEFAULTS,
202 [TSU_CTRST] = 0x0004,
203 [TSU_FWSLC] = 0x0038,
204 [TSU_VTAG0] = 0x0058,
205 [TSU_ADSBSY] = 0x0060,
207 [TSU_POST1] = 0x0070,
208 [TSU_POST2] = 0x0074,
209 [TSU_POST3] = 0x0078,
210 [TSU_POST4] = 0x007c,
211 [TSU_ADRH0] = 0x0100,
219 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
220 SH_ETH_OFFSET_DEFAULTS,
267 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
268 SH_ETH_OFFSET_DEFAULTS,
321 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
322 SH_ETH_OFFSET_DEFAULTS,
370 [TSU_CTRST] = 0x0004,
371 [TSU_FWEN0] = 0x0010,
372 [TSU_FWEN1] = 0x0014,
374 [TSU_BSYSL0] = 0x0020,
375 [TSU_BSYSL1] = 0x0024,
376 [TSU_PRISL0] = 0x0028,
377 [TSU_PRISL1] = 0x002c,
378 [TSU_FWSL0] = 0x0030,
379 [TSU_FWSL1] = 0x0034,
380 [TSU_FWSLC] = 0x0038,
381 [TSU_QTAGM0] = 0x0040,
382 [TSU_QTAGM1] = 0x0044,
383 [TSU_ADQT0] = 0x0048,
384 [TSU_ADQT1] = 0x004c,
386 [TSU_FWINMK] = 0x0054,
387 [TSU_ADSBSY] = 0x0060,
389 [TSU_POST1] = 0x0070,
390 [TSU_POST2] = 0x0074,
391 [TSU_POST3] = 0x0078,
392 [TSU_POST4] = 0x007c,
407 [TSU_ADRH0] = 0x0100,
410 static void sh_eth_rcv_snd_disable(struct net_device *ndev);
411 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
413 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
415 struct sh_eth_private *mdp = netdev_priv(ndev);
416 u16 offset = mdp->reg_offset[enum_index];
418 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
421 iowrite32(data, mdp->addr + offset);
424 static u32 sh_eth_read(struct net_device *ndev, int enum_index)
426 struct sh_eth_private *mdp = netdev_priv(ndev);
427 u16 offset = mdp->reg_offset[enum_index];
429 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
432 return ioread32(mdp->addr + offset);
435 static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
438 sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set,
442 static void sh_eth_tsu_write(struct sh_eth_private *mdp, u32 data,
445 u16 offset = mdp->reg_offset[enum_index];
447 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
450 iowrite32(data, mdp->tsu_addr + offset);
453 static u32 sh_eth_tsu_read(struct sh_eth_private *mdp, int enum_index)
455 u16 offset = mdp->reg_offset[enum_index];
457 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
460 return ioread32(mdp->tsu_addr + offset);
463 static void sh_eth_select_mii(struct net_device *ndev)
465 struct sh_eth_private *mdp = netdev_priv(ndev);
468 switch (mdp->phy_interface) {
469 case PHY_INTERFACE_MODE_GMII:
472 case PHY_INTERFACE_MODE_MII:
475 case PHY_INTERFACE_MODE_RMII:
480 "PHY interface mode was not setup. Set to MII.\n");
485 sh_eth_write(ndev, value, RMII_MII);
488 static void sh_eth_set_duplex(struct net_device *ndev)
490 struct sh_eth_private *mdp = netdev_priv(ndev);
492 sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0);
495 static void sh_eth_chip_reset(struct net_device *ndev)
497 struct sh_eth_private *mdp = netdev_priv(ndev);
500 sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR);
504 static int sh_eth_soft_reset(struct net_device *ndev)
506 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
508 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
513 static int sh_eth_check_soft_reset(struct net_device *ndev)
517 for (cnt = 100; cnt > 0; cnt--) {
518 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER))
523 netdev_err(ndev, "Device reset failed\n");
527 static int sh_eth_soft_reset_gether(struct net_device *ndev)
529 struct sh_eth_private *mdp = netdev_priv(ndev);
532 sh_eth_write(ndev, EDSR_ENALL, EDSR);
533 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
535 ret = sh_eth_check_soft_reset(ndev);
540 sh_eth_write(ndev, 0, TDLAR);
541 sh_eth_write(ndev, 0, TDFAR);
542 sh_eth_write(ndev, 0, TDFXR);
543 sh_eth_write(ndev, 0, TDFFR);
544 sh_eth_write(ndev, 0, RDLAR);
545 sh_eth_write(ndev, 0, RDFAR);
546 sh_eth_write(ndev, 0, RDFXR);
547 sh_eth_write(ndev, 0, RDFFR);
549 /* Reset HW CRC register */
550 if (mdp->cd->hw_checksum)
551 sh_eth_write(ndev, 0, CSMR);
553 /* Select MII mode */
554 if (mdp->cd->select_mii)
555 sh_eth_select_mii(ndev);
560 static void sh_eth_set_rate_gether(struct net_device *ndev)
562 struct sh_eth_private *mdp = netdev_priv(ndev);
564 switch (mdp->speed) {
565 case 10: /* 10BASE */
566 sh_eth_write(ndev, GECMR_10, GECMR);
568 case 100:/* 100BASE */
569 sh_eth_write(ndev, GECMR_100, GECMR);
571 case 1000: /* 1000BASE */
572 sh_eth_write(ndev, GECMR_1000, GECMR);
579 static struct sh_eth_cpu_data r7s72100_data = {
580 .soft_reset = sh_eth_soft_reset_gether,
582 .chip_reset = sh_eth_chip_reset,
583 .set_duplex = sh_eth_set_duplex,
585 .register_type = SH_ETH_REG_FAST_RZ,
587 .edtrr_trns = EDTRR_TRNS_GETHER,
588 .ecsr_value = ECSR_ICD,
589 .ecsipr_value = ECSIPR_ICDIP,
590 .eesipr_value = EESIPR_TWB1IP | EESIPR_TWBIP | EESIPR_TC1IP |
591 EESIPR_TABTIP | EESIPR_RABTIP | EESIPR_RFCOFIP |
593 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
594 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
595 EESIPR_RMAFIP | EESIPR_RRFIP |
596 EESIPR_RTLFIP | EESIPR_RTSFIP |
597 EESIPR_PREIP | EESIPR_CERFIP,
599 .tx_check = EESR_TC1 | EESR_FTC,
600 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
601 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
603 .fdr_value = 0x0000070f,
611 .rpadir_value = 2 << 16,
620 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
622 sh_eth_chip_reset(ndev);
624 sh_eth_select_mii(ndev);
628 static struct sh_eth_cpu_data r8a7740_data = {
629 .soft_reset = sh_eth_soft_reset_gether,
631 .chip_reset = sh_eth_chip_reset_r8a7740,
632 .set_duplex = sh_eth_set_duplex,
633 .set_rate = sh_eth_set_rate_gether,
635 .register_type = SH_ETH_REG_GIGABIT,
637 .edtrr_trns = EDTRR_TRNS_GETHER,
638 .ecsr_value = ECSR_ICD | ECSR_MPD,
639 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
640 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
641 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
642 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
643 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
644 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
645 EESIPR_CEEFIP | EESIPR_CELFIP |
646 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
647 EESIPR_PREIP | EESIPR_CERFIP,
649 .tx_check = EESR_TC1 | EESR_FTC,
650 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
651 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
653 .fdr_value = 0x0000070f,
661 .rpadir_value = 2 << 16,
672 /* There is CPU dependent code */
673 static void sh_eth_set_rate_rcar(struct net_device *ndev)
675 struct sh_eth_private *mdp = netdev_priv(ndev);
677 switch (mdp->speed) {
678 case 10: /* 10BASE */
679 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0);
681 case 100:/* 100BASE */
682 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB);
688 static struct sh_eth_cpu_data rcar_gen1_data = {
689 .soft_reset = sh_eth_soft_reset,
691 .set_duplex = sh_eth_set_duplex,
692 .set_rate = sh_eth_set_rate_rcar,
694 .register_type = SH_ETH_REG_FAST_RCAR,
696 .edtrr_trns = EDTRR_TRNS_ETHER,
697 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
698 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
699 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
700 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
701 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
702 EESIPR_RMAFIP | EESIPR_RRFIP |
703 EESIPR_RTLFIP | EESIPR_RTSFIP |
704 EESIPR_PREIP | EESIPR_CERFIP,
706 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
707 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
708 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
709 .fdr_value = 0x00000f0f,
718 /* R-Car Gen2 and RZ/G1 */
719 static struct sh_eth_cpu_data rcar_gen2_data = {
720 .soft_reset = sh_eth_soft_reset,
722 .set_duplex = sh_eth_set_duplex,
723 .set_rate = sh_eth_set_rate_rcar,
725 .register_type = SH_ETH_REG_FAST_RCAR,
727 .edtrr_trns = EDTRR_TRNS_ETHER,
728 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
729 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
731 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
732 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
733 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
734 EESIPR_RMAFIP | EESIPR_RRFIP |
735 EESIPR_RTLFIP | EESIPR_RTSFIP |
736 EESIPR_PREIP | EESIPR_CERFIP,
738 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
739 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
740 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
741 .fdr_value = 0x00000f0f,
743 .trscer_err_mask = DESC_I_RINT8,
753 #endif /* CONFIG_OF */
755 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
757 struct sh_eth_private *mdp = netdev_priv(ndev);
759 switch (mdp->speed) {
760 case 10: /* 10BASE */
761 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0);
763 case 100:/* 100BASE */
764 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM);
770 static struct sh_eth_cpu_data sh7724_data = {
771 .soft_reset = sh_eth_soft_reset,
773 .set_duplex = sh_eth_set_duplex,
774 .set_rate = sh_eth_set_rate_sh7724,
776 .register_type = SH_ETH_REG_FAST_SH4,
778 .edtrr_trns = EDTRR_TRNS_ETHER,
779 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
780 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
781 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
782 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
783 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
784 EESIPR_RMAFIP | EESIPR_RRFIP |
785 EESIPR_RTLFIP | EESIPR_RTSFIP |
786 EESIPR_PREIP | EESIPR_CERFIP,
788 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
789 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
790 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
797 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
800 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
802 struct sh_eth_private *mdp = netdev_priv(ndev);
804 switch (mdp->speed) {
805 case 10: /* 10BASE */
806 sh_eth_write(ndev, 0, RTRATE);
808 case 100:/* 100BASE */
809 sh_eth_write(ndev, 1, RTRATE);
815 static struct sh_eth_cpu_data sh7757_data = {
816 .soft_reset = sh_eth_soft_reset,
818 .set_duplex = sh_eth_set_duplex,
819 .set_rate = sh_eth_set_rate_sh7757,
821 .register_type = SH_ETH_REG_FAST_SH4,
823 .edtrr_trns = EDTRR_TRNS_ETHER,
824 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
825 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
826 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
827 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
828 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
829 EESIPR_CEEFIP | EESIPR_CELFIP |
830 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
831 EESIPR_PREIP | EESIPR_CERFIP,
833 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
834 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
835 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
837 .irq_flags = IRQF_SHARED,
844 .rpadir_value = 2 << 16,
849 #define SH_GIGA_ETH_BASE 0xfee00000UL
850 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
851 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
852 static void sh_eth_chip_reset_giga(struct net_device *ndev)
854 u32 mahr[2], malr[2];
857 /* save MAHR and MALR */
858 for (i = 0; i < 2; i++) {
859 malr[i] = ioread32((void *)GIGA_MALR(i));
860 mahr[i] = ioread32((void *)GIGA_MAHR(i));
863 sh_eth_chip_reset(ndev);
865 /* restore MAHR and MALR */
866 for (i = 0; i < 2; i++) {
867 iowrite32(malr[i], (void *)GIGA_MALR(i));
868 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
872 static void sh_eth_set_rate_giga(struct net_device *ndev)
874 struct sh_eth_private *mdp = netdev_priv(ndev);
876 switch (mdp->speed) {
877 case 10: /* 10BASE */
878 sh_eth_write(ndev, 0x00000000, GECMR);
880 case 100:/* 100BASE */
881 sh_eth_write(ndev, 0x00000010, GECMR);
883 case 1000: /* 1000BASE */
884 sh_eth_write(ndev, 0x00000020, GECMR);
889 /* SH7757(GETHERC) */
890 static struct sh_eth_cpu_data sh7757_data_giga = {
891 .soft_reset = sh_eth_soft_reset_gether,
893 .chip_reset = sh_eth_chip_reset_giga,
894 .set_duplex = sh_eth_set_duplex,
895 .set_rate = sh_eth_set_rate_giga,
897 .register_type = SH_ETH_REG_GIGABIT,
899 .edtrr_trns = EDTRR_TRNS_GETHER,
900 .ecsr_value = ECSR_ICD | ECSR_MPD,
901 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
902 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
903 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
904 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
905 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
906 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
907 EESIPR_CEEFIP | EESIPR_CELFIP |
908 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
909 EESIPR_PREIP | EESIPR_CERFIP,
911 .tx_check = EESR_TC1 | EESR_FTC,
912 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
913 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
915 .fdr_value = 0x0000072f,
917 .irq_flags = IRQF_SHARED,
924 .rpadir_value = 2 << 16,
934 static struct sh_eth_cpu_data sh7734_data = {
935 .soft_reset = sh_eth_soft_reset_gether,
937 .chip_reset = sh_eth_chip_reset,
938 .set_duplex = sh_eth_set_duplex,
939 .set_rate = sh_eth_set_rate_gether,
941 .register_type = SH_ETH_REG_GIGABIT,
943 .edtrr_trns = EDTRR_TRNS_GETHER,
944 .ecsr_value = ECSR_ICD | ECSR_MPD,
945 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
946 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
947 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
948 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
949 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
950 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
951 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
952 EESIPR_PREIP | EESIPR_CERFIP,
954 .tx_check = EESR_TC1 | EESR_FTC,
955 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
956 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
975 static struct sh_eth_cpu_data sh7763_data = {
976 .soft_reset = sh_eth_soft_reset_gether,
978 .chip_reset = sh_eth_chip_reset,
979 .set_duplex = sh_eth_set_duplex,
980 .set_rate = sh_eth_set_rate_gether,
982 .register_type = SH_ETH_REG_GIGABIT,
984 .edtrr_trns = EDTRR_TRNS_GETHER,
985 .ecsr_value = ECSR_ICD | ECSR_MPD,
986 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
987 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
988 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
989 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
990 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
991 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
992 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
993 EESIPR_PREIP | EESIPR_CERFIP,
995 .tx_check = EESR_TC1 | EESR_FTC,
996 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
997 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
1008 .irq_flags = IRQF_SHARED,
1014 static struct sh_eth_cpu_data sh7619_data = {
1015 .soft_reset = sh_eth_soft_reset,
1017 .register_type = SH_ETH_REG_FAST_SH3_SH2,
1019 .edtrr_trns = EDTRR_TRNS_ETHER,
1020 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1021 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1022 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1023 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
1024 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
1025 EESIPR_CEEFIP | EESIPR_CELFIP |
1026 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1027 EESIPR_PREIP | EESIPR_CERFIP,
1035 static struct sh_eth_cpu_data sh771x_data = {
1036 .soft_reset = sh_eth_soft_reset,
1038 .register_type = SH_ETH_REG_FAST_SH3_SH2,
1040 .edtrr_trns = EDTRR_TRNS_ETHER,
1041 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1042 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1043 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1044 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
1045 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
1046 EESIPR_CEEFIP | EESIPR_CELFIP |
1047 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1048 EESIPR_PREIP | EESIPR_CERFIP,
1053 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
1055 if (!cd->ecsr_value)
1056 cd->ecsr_value = DEFAULT_ECSR_INIT;
1058 if (!cd->ecsipr_value)
1059 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
1061 if (!cd->fcftr_value)
1062 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
1063 DEFAULT_FIFO_F_D_RFD;
1066 cd->fdr_value = DEFAULT_FDR_INIT;
1069 cd->tx_check = DEFAULT_TX_CHECK;
1071 if (!cd->eesr_err_check)
1072 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
1074 if (!cd->trscer_err_mask)
1075 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
1078 static void sh_eth_set_receive_align(struct sk_buff *skb)
1080 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
1083 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
1086 /* Program the hardware MAC address from dev->dev_addr. */
1087 static void update_mac_address(struct net_device *ndev)
1090 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
1091 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
1093 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
1096 /* Get MAC address from SuperH MAC address register
1098 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
1099 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
1100 * When you want use this device, you must set MAC address in bootloader.
1103 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
1105 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
1106 memcpy(ndev->dev_addr, mac, ETH_ALEN);
1108 u32 mahr = sh_eth_read(ndev, MAHR);
1109 u32 malr = sh_eth_read(ndev, MALR);
1111 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
1112 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
1113 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
1114 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
1115 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
1116 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
1121 void (*set_gate)(void *addr);
1122 struct mdiobb_ctrl ctrl;
1126 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
1128 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1131 if (bitbang->set_gate)
1132 bitbang->set_gate(bitbang->addr);
1134 pir = ioread32(bitbang->addr);
1139 iowrite32(pir, bitbang->addr);
1142 /* Data I/O pin control */
1143 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1145 sh_mdio_ctrl(ctrl, PIR_MMD, bit);
1149 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1151 sh_mdio_ctrl(ctrl, PIR_MDO, bit);
1155 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1157 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1159 if (bitbang->set_gate)
1160 bitbang->set_gate(bitbang->addr);
1162 return (ioread32(bitbang->addr) & PIR_MDI) != 0;
1165 /* MDC pin control */
1166 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1168 sh_mdio_ctrl(ctrl, PIR_MDC, bit);
1171 /* mdio bus control struct */
1172 static struct mdiobb_ops bb_ops = {
1173 .owner = THIS_MODULE,
1174 .set_mdc = sh_mdc_ctrl,
1175 .set_mdio_dir = sh_mmd_ctrl,
1176 .set_mdio_data = sh_set_mdio,
1177 .get_mdio_data = sh_get_mdio,
1180 /* free Tx skb function */
1181 static int sh_eth_tx_free(struct net_device *ndev, bool sent_only)
1183 struct sh_eth_private *mdp = netdev_priv(ndev);
1184 struct sh_eth_txdesc *txdesc;
1189 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1190 entry = mdp->dirty_tx % mdp->num_tx_ring;
1191 txdesc = &mdp->tx_ring[entry];
1192 sent = !(txdesc->status & cpu_to_le32(TD_TACT));
1193 if (sent_only && !sent)
1195 /* TACT bit must be checked before all the following reads */
1197 netif_info(mdp, tx_done, ndev,
1198 "tx entry %d status 0x%08x\n",
1199 entry, le32_to_cpu(txdesc->status));
1200 /* Free the original skb. */
1201 if (mdp->tx_skbuff[entry]) {
1202 dma_unmap_single(&mdp->pdev->dev,
1203 le32_to_cpu(txdesc->addr),
1204 le32_to_cpu(txdesc->len) >> 16,
1206 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1207 mdp->tx_skbuff[entry] = NULL;
1210 txdesc->status = cpu_to_le32(TD_TFP);
1211 if (entry >= mdp->num_tx_ring - 1)
1212 txdesc->status |= cpu_to_le32(TD_TDLE);
1215 ndev->stats.tx_packets++;
1216 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
1222 /* free skb and descriptor buffer */
1223 static void sh_eth_ring_free(struct net_device *ndev)
1225 struct sh_eth_private *mdp = netdev_priv(ndev);
1229 for (i = 0; i < mdp->num_rx_ring; i++) {
1230 if (mdp->rx_skbuff[i]) {
1231 struct sh_eth_rxdesc *rxdesc = &mdp->rx_ring[i];
1233 dma_unmap_single(&mdp->pdev->dev,
1234 le32_to_cpu(rxdesc->addr),
1235 ALIGN(mdp->rx_buf_sz, 32),
1239 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1240 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->rx_ring,
1242 mdp->rx_ring = NULL;
1245 /* Free Rx skb ringbuffer */
1246 if (mdp->rx_skbuff) {
1247 for (i = 0; i < mdp->num_rx_ring; i++)
1248 dev_kfree_skb(mdp->rx_skbuff[i]);
1250 kfree(mdp->rx_skbuff);
1251 mdp->rx_skbuff = NULL;
1254 sh_eth_tx_free(ndev, false);
1256 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1257 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->tx_ring,
1259 mdp->tx_ring = NULL;
1262 /* Free Tx skb ringbuffer */
1263 kfree(mdp->tx_skbuff);
1264 mdp->tx_skbuff = NULL;
1267 /* format skb and descriptor buffer */
1268 static void sh_eth_ring_format(struct net_device *ndev)
1270 struct sh_eth_private *mdp = netdev_priv(ndev);
1272 struct sk_buff *skb;
1273 struct sh_eth_rxdesc *rxdesc = NULL;
1274 struct sh_eth_txdesc *txdesc = NULL;
1275 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1276 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1277 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1278 dma_addr_t dma_addr;
1286 memset(mdp->rx_ring, 0, rx_ringsize);
1288 /* build Rx ring buffer */
1289 for (i = 0; i < mdp->num_rx_ring; i++) {
1291 mdp->rx_skbuff[i] = NULL;
1292 skb = netdev_alloc_skb(ndev, skbuff_size);
1295 sh_eth_set_receive_align(skb);
1297 /* The size of the buffer is a multiple of 32 bytes. */
1298 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1299 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, buf_len,
1301 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
1305 mdp->rx_skbuff[i] = skb;
1308 rxdesc = &mdp->rx_ring[i];
1309 rxdesc->len = cpu_to_le32(buf_len << 16);
1310 rxdesc->addr = cpu_to_le32(dma_addr);
1311 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
1313 /* Rx descriptor address set */
1315 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1316 if (mdp->cd->xdfar_rw)
1317 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1321 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1323 /* Mark the last entry as wrapping the ring. */
1325 rxdesc->status |= cpu_to_le32(RD_RDLE);
1327 memset(mdp->tx_ring, 0, tx_ringsize);
1329 /* build Tx ring buffer */
1330 for (i = 0; i < mdp->num_tx_ring; i++) {
1331 mdp->tx_skbuff[i] = NULL;
1332 txdesc = &mdp->tx_ring[i];
1333 txdesc->status = cpu_to_le32(TD_TFP);
1334 txdesc->len = cpu_to_le32(0);
1336 /* Tx descriptor address set */
1337 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1338 if (mdp->cd->xdfar_rw)
1339 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1343 txdesc->status |= cpu_to_le32(TD_TDLE);
1346 /* Get skb and descriptor buffer */
1347 static int sh_eth_ring_init(struct net_device *ndev)
1349 struct sh_eth_private *mdp = netdev_priv(ndev);
1350 int rx_ringsize, tx_ringsize;
1352 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1353 * card needs room to do 8 byte alignment, +2 so we can reserve
1354 * the first 2 bytes, and +16 gets room for the status word from the
1357 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1358 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1359 if (mdp->cd->rpadir)
1360 mdp->rx_buf_sz += NET_IP_ALIGN;
1362 /* Allocate RX and TX skb rings */
1363 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1365 if (!mdp->rx_skbuff)
1368 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1370 if (!mdp->tx_skbuff)
1373 /* Allocate all Rx descriptors. */
1374 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1375 mdp->rx_ring = dma_alloc_coherent(&mdp->pdev->dev, rx_ringsize,
1376 &mdp->rx_desc_dma, GFP_KERNEL);
1382 /* Allocate all Tx descriptors. */
1383 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1384 mdp->tx_ring = dma_alloc_coherent(&mdp->pdev->dev, tx_ringsize,
1385 &mdp->tx_desc_dma, GFP_KERNEL);
1391 /* Free Rx and Tx skb ring buffer and DMA buffer */
1392 sh_eth_ring_free(ndev);
1397 static int sh_eth_dev_init(struct net_device *ndev)
1399 struct sh_eth_private *mdp = netdev_priv(ndev);
1403 ret = mdp->cd->soft_reset(ndev);
1407 if (mdp->cd->rmiimode)
1408 sh_eth_write(ndev, 0x1, RMIIMODE);
1410 /* Descriptor format */
1411 sh_eth_ring_format(ndev);
1412 if (mdp->cd->rpadir)
1413 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1415 /* all sh_eth int mask */
1416 sh_eth_write(ndev, 0, EESIPR);
1418 #if defined(__LITTLE_ENDIAN)
1419 if (mdp->cd->hw_swap)
1420 sh_eth_write(ndev, EDMR_EL, EDMR);
1423 sh_eth_write(ndev, 0, EDMR);
1426 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1427 sh_eth_write(ndev, 0, TFTR);
1429 /* Frame recv control (enable multiple-packets per rx irq) */
1430 sh_eth_write(ndev, RMCR_RNC, RMCR);
1432 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1435 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
1437 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1439 if (!mdp->cd->no_trimd)
1440 sh_eth_write(ndev, 0, TRIMD);
1442 /* Recv frame limit set register */
1443 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1446 sh_eth_modify(ndev, EESR, 0, 0);
1447 mdp->irq_enabled = true;
1448 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1450 /* PAUSE Prohibition */
1451 sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |
1452 ECMR_TE | ECMR_RE, ECMR);
1454 if (mdp->cd->set_rate)
1455 mdp->cd->set_rate(ndev);
1457 /* E-MAC Status Register clear */
1458 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1460 /* E-MAC Interrupt Enable register */
1461 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1463 /* Set MAC address */
1464 update_mac_address(ndev);
1468 sh_eth_write(ndev, APR_AP, APR);
1470 sh_eth_write(ndev, MPR_MP, MPR);
1471 if (mdp->cd->tpauser)
1472 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1474 /* Setting the Rx mode will start the Rx process. */
1475 sh_eth_write(ndev, EDRRR_R, EDRRR);
1480 static void sh_eth_dev_exit(struct net_device *ndev)
1482 struct sh_eth_private *mdp = netdev_priv(ndev);
1485 /* Deactivate all TX descriptors, so DMA should stop at next
1486 * packet boundary if it's currently running
1488 for (i = 0; i < mdp->num_tx_ring; i++)
1489 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT);
1491 /* Disable TX FIFO egress to MAC */
1492 sh_eth_rcv_snd_disable(ndev);
1494 /* Stop RX DMA at next packet boundary */
1495 sh_eth_write(ndev, 0, EDRRR);
1497 /* Aside from TX DMA, we can't tell when the hardware is
1498 * really stopped, so we need to reset to make sure.
1499 * Before doing that, wait for long enough to *probably*
1500 * finish transmitting the last packet and poll stats.
1502 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1503 sh_eth_get_stats(ndev);
1504 mdp->cd->soft_reset(ndev);
1506 /* Set MAC address again */
1507 update_mac_address(ndev);
1510 /* Packet receive function */
1511 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1513 struct sh_eth_private *mdp = netdev_priv(ndev);
1514 struct sh_eth_rxdesc *rxdesc;
1516 int entry = mdp->cur_rx % mdp->num_rx_ring;
1517 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1519 struct sk_buff *skb;
1521 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1522 dma_addr_t dma_addr;
1526 boguscnt = min(boguscnt, *quota);
1528 rxdesc = &mdp->rx_ring[entry];
1529 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
1530 /* RACT bit must be checked before all the following reads */
1532 desc_status = le32_to_cpu(rxdesc->status);
1533 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL;
1538 netif_info(mdp, rx_status, ndev,
1539 "rx entry %d status 0x%08x len %d\n",
1540 entry, desc_status, pkt_len);
1542 if (!(desc_status & RDFEND))
1543 ndev->stats.rx_length_errors++;
1545 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1546 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1547 * bit 0. However, in case of the R8A7740 and R7S72100
1548 * the RFS bits are from bit 25 to bit 16. So, the
1549 * driver needs right shifting by 16.
1551 if (mdp->cd->hw_checksum)
1554 skb = mdp->rx_skbuff[entry];
1555 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1556 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1557 ndev->stats.rx_errors++;
1558 if (desc_status & RD_RFS1)
1559 ndev->stats.rx_crc_errors++;
1560 if (desc_status & RD_RFS2)
1561 ndev->stats.rx_frame_errors++;
1562 if (desc_status & RD_RFS3)
1563 ndev->stats.rx_length_errors++;
1564 if (desc_status & RD_RFS4)
1565 ndev->stats.rx_length_errors++;
1566 if (desc_status & RD_RFS6)
1567 ndev->stats.rx_missed_errors++;
1568 if (desc_status & RD_RFS10)
1569 ndev->stats.rx_over_errors++;
1571 dma_addr = le32_to_cpu(rxdesc->addr);
1572 if (!mdp->cd->hw_swap)
1574 phys_to_virt(ALIGN(dma_addr, 4)),
1576 mdp->rx_skbuff[entry] = NULL;
1577 if (mdp->cd->rpadir)
1578 skb_reserve(skb, NET_IP_ALIGN);
1579 dma_unmap_single(&mdp->pdev->dev, dma_addr,
1580 ALIGN(mdp->rx_buf_sz, 32),
1582 skb_put(skb, pkt_len);
1583 skb->protocol = eth_type_trans(skb, ndev);
1584 netif_receive_skb(skb);
1585 ndev->stats.rx_packets++;
1586 ndev->stats.rx_bytes += pkt_len;
1587 if (desc_status & RD_RFS8)
1588 ndev->stats.multicast++;
1590 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1591 rxdesc = &mdp->rx_ring[entry];
1594 /* Refill the Rx ring buffers. */
1595 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1596 entry = mdp->dirty_rx % mdp->num_rx_ring;
1597 rxdesc = &mdp->rx_ring[entry];
1598 /* The size of the buffer is 32 byte boundary. */
1599 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1600 rxdesc->len = cpu_to_le32(buf_len << 16);
1602 if (mdp->rx_skbuff[entry] == NULL) {
1603 skb = netdev_alloc_skb(ndev, skbuff_size);
1605 break; /* Better luck next round. */
1606 sh_eth_set_receive_align(skb);
1607 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data,
1608 buf_len, DMA_FROM_DEVICE);
1609 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
1613 mdp->rx_skbuff[entry] = skb;
1615 skb_checksum_none_assert(skb);
1616 rxdesc->addr = cpu_to_le32(dma_addr);
1618 dma_wmb(); /* RACT bit must be set after all the above writes */
1619 if (entry >= mdp->num_rx_ring - 1)
1621 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE);
1623 rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP);
1626 /* Restart Rx engine if stopped. */
1627 /* If we don't need to check status, don't. -KDU */
1628 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1629 /* fix the values for the next receiving if RDE is set */
1630 if (intr_status & EESR_RDE && !mdp->cd->no_xdfar) {
1631 u32 count = (sh_eth_read(ndev, RDFAR) -
1632 sh_eth_read(ndev, RDLAR)) >> 4;
1634 mdp->cur_rx = count;
1635 mdp->dirty_rx = count;
1637 sh_eth_write(ndev, EDRRR_R, EDRRR);
1640 *quota -= limit - boguscnt - 1;
1645 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1647 /* disable tx and rx */
1648 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
1651 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1653 /* enable tx and rx */
1654 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
1657 /* E-MAC interrupt handler */
1658 static void sh_eth_emac_interrupt(struct net_device *ndev)
1660 struct sh_eth_private *mdp = netdev_priv(ndev);
1664 felic_stat = sh_eth_read(ndev, ECSR) & sh_eth_read(ndev, ECSIPR);
1665 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1666 if (felic_stat & ECSR_ICD)
1667 ndev->stats.tx_carrier_errors++;
1668 if (felic_stat & ECSR_MPD)
1669 pm_wakeup_event(&mdp->pdev->dev, 0);
1670 if (felic_stat & ECSR_LCHNG) {
1672 if (mdp->cd->no_psr || mdp->no_ether_link)
1674 link_stat = sh_eth_read(ndev, PSR);
1675 if (mdp->ether_link_active_low)
1676 link_stat = ~link_stat;
1677 if (!(link_stat & PHY_ST_LINK)) {
1678 sh_eth_rcv_snd_disable(ndev);
1681 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, 0);
1683 sh_eth_modify(ndev, ECSR, 0, 0);
1684 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, EESIPR_ECIIP);
1685 /* enable tx and rx */
1686 sh_eth_rcv_snd_enable(ndev);
1691 /* error control function */
1692 static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1694 struct sh_eth_private *mdp = netdev_priv(ndev);
1697 if (intr_status & EESR_TWB) {
1698 /* Unused write back interrupt */
1699 if (intr_status & EESR_TABT) { /* Transmit Abort int */
1700 ndev->stats.tx_aborted_errors++;
1701 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1705 if (intr_status & EESR_RABT) {
1706 /* Receive Abort int */
1707 if (intr_status & EESR_RFRMER) {
1708 /* Receive Frame Overflow int */
1709 ndev->stats.rx_frame_errors++;
1713 if (intr_status & EESR_TDE) {
1714 /* Transmit Descriptor Empty int */
1715 ndev->stats.tx_fifo_errors++;
1716 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1719 if (intr_status & EESR_TFE) {
1720 /* FIFO under flow */
1721 ndev->stats.tx_fifo_errors++;
1722 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1725 if (intr_status & EESR_RDE) {
1726 /* Receive Descriptor Empty int */
1727 ndev->stats.rx_over_errors++;
1730 if (intr_status & EESR_RFE) {
1731 /* Receive FIFO Overflow int */
1732 ndev->stats.rx_fifo_errors++;
1735 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1737 ndev->stats.tx_fifo_errors++;
1738 netif_err(mdp, tx_err, ndev, "Address Error\n");
1741 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1742 if (mdp->cd->no_ade)
1744 if (intr_status & mask) {
1746 u32 edtrr = sh_eth_read(ndev, EDTRR);
1749 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1750 intr_status, mdp->cur_tx, mdp->dirty_tx,
1751 (u32)ndev->state, edtrr);
1752 /* dirty buffer free */
1753 sh_eth_tx_free(ndev, true);
1756 if (edtrr ^ mdp->cd->edtrr_trns) {
1758 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR);
1761 netif_wake_queue(ndev);
1765 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1767 struct net_device *ndev = netdev;
1768 struct sh_eth_private *mdp = netdev_priv(ndev);
1769 struct sh_eth_cpu_data *cd = mdp->cd;
1770 irqreturn_t ret = IRQ_NONE;
1771 u32 intr_status, intr_enable;
1773 spin_lock(&mdp->lock);
1775 /* Get interrupt status */
1776 intr_status = sh_eth_read(ndev, EESR);
1777 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1778 * enabled since it's the one that comes thru regardless of the mask,
1779 * and we need to fully handle it in sh_eth_emac_interrupt() in order
1780 * to quench it as it doesn't get cleared by just writing 1 to the ECI
1783 intr_enable = sh_eth_read(ndev, EESIPR);
1784 intr_status &= intr_enable | EESIPR_ECIIP;
1785 if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI |
1786 cd->eesr_err_check))
1791 if (unlikely(!mdp->irq_enabled)) {
1792 sh_eth_write(ndev, 0, EESIPR);
1796 if (intr_status & EESR_RX_CHECK) {
1797 if (napi_schedule_prep(&mdp->napi)) {
1798 /* Mask Rx interrupts */
1799 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1801 __napi_schedule(&mdp->napi);
1804 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1805 intr_status, intr_enable);
1810 if (intr_status & cd->tx_check) {
1811 /* Clear Tx interrupts */
1812 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1814 sh_eth_tx_free(ndev, true);
1815 netif_wake_queue(ndev);
1818 /* E-MAC interrupt */
1819 if (intr_status & EESR_ECI)
1820 sh_eth_emac_interrupt(ndev);
1822 if (intr_status & cd->eesr_err_check) {
1823 /* Clear error interrupts */
1824 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1826 sh_eth_error(ndev, intr_status);
1830 spin_unlock(&mdp->lock);
1835 static int sh_eth_poll(struct napi_struct *napi, int budget)
1837 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1839 struct net_device *ndev = napi->dev;
1844 intr_status = sh_eth_read(ndev, EESR);
1845 if (!(intr_status & EESR_RX_CHECK))
1847 /* Clear Rx interrupts */
1848 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1850 if (sh_eth_rx(ndev, intr_status, "a))
1854 napi_complete(napi);
1856 /* Reenable Rx interrupts */
1857 if (mdp->irq_enabled)
1858 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1860 return budget - quota;
1863 /* PHY state control function */
1864 static void sh_eth_adjust_link(struct net_device *ndev)
1866 struct sh_eth_private *mdp = netdev_priv(ndev);
1867 struct phy_device *phydev = ndev->phydev;
1871 if (phydev->duplex != mdp->duplex) {
1873 mdp->duplex = phydev->duplex;
1874 if (mdp->cd->set_duplex)
1875 mdp->cd->set_duplex(ndev);
1878 if (phydev->speed != mdp->speed) {
1880 mdp->speed = phydev->speed;
1881 if (mdp->cd->set_rate)
1882 mdp->cd->set_rate(ndev);
1885 sh_eth_modify(ndev, ECMR, ECMR_TXF, 0);
1887 mdp->link = phydev->link;
1888 if (mdp->cd->no_psr || mdp->no_ether_link)
1889 sh_eth_rcv_snd_enable(ndev);
1891 } else if (mdp->link) {
1896 if (mdp->cd->no_psr || mdp->no_ether_link)
1897 sh_eth_rcv_snd_disable(ndev);
1900 if (new_state && netif_msg_link(mdp))
1901 phy_print_status(phydev);
1904 /* PHY init function */
1905 static int sh_eth_phy_init(struct net_device *ndev)
1907 struct device_node *np = ndev->dev.parent->of_node;
1908 struct sh_eth_private *mdp = netdev_priv(ndev);
1909 struct phy_device *phydev;
1915 /* Try connect to PHY */
1917 struct device_node *pn;
1919 pn = of_parse_phandle(np, "phy-handle", 0);
1920 phydev = of_phy_connect(ndev, pn,
1921 sh_eth_adjust_link, 0,
1922 mdp->phy_interface);
1926 phydev = ERR_PTR(-ENOENT);
1928 char phy_id[MII_BUS_ID_SIZE + 3];
1930 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1931 mdp->mii_bus->id, mdp->phy_id);
1933 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1934 mdp->phy_interface);
1937 if (IS_ERR(phydev)) {
1938 netdev_err(ndev, "failed to connect PHY\n");
1939 return PTR_ERR(phydev);
1942 /* mask with MAC supported features */
1943 if (mdp->cd->register_type != SH_ETH_REG_GIGABIT) {
1944 int err = phy_set_max_speed(phydev, SPEED_100);
1946 netdev_err(ndev, "failed to limit PHY to 100 Mbit/s\n");
1947 phy_disconnect(phydev);
1952 phy_attached_info(phydev);
1957 /* PHY control start function */
1958 static int sh_eth_phy_start(struct net_device *ndev)
1962 ret = sh_eth_phy_init(ndev);
1966 phy_start(ndev->phydev);
1971 static int sh_eth_get_link_ksettings(struct net_device *ndev,
1972 struct ethtool_link_ksettings *cmd)
1974 struct sh_eth_private *mdp = netdev_priv(ndev);
1975 unsigned long flags;
1980 spin_lock_irqsave(&mdp->lock, flags);
1981 phy_ethtool_ksettings_get(ndev->phydev, cmd);
1982 spin_unlock_irqrestore(&mdp->lock, flags);
1987 static int sh_eth_set_link_ksettings(struct net_device *ndev,
1988 const struct ethtool_link_ksettings *cmd)
1990 struct sh_eth_private *mdp = netdev_priv(ndev);
1991 unsigned long flags;
1997 spin_lock_irqsave(&mdp->lock, flags);
1999 /* disable tx and rx */
2000 sh_eth_rcv_snd_disable(ndev);
2002 ret = phy_ethtool_ksettings_set(ndev->phydev, cmd);
2006 if (cmd->base.duplex == DUPLEX_FULL)
2011 if (mdp->cd->set_duplex)
2012 mdp->cd->set_duplex(ndev);
2017 /* enable tx and rx */
2018 sh_eth_rcv_snd_enable(ndev);
2020 spin_unlock_irqrestore(&mdp->lock, flags);
2025 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
2026 * version must be bumped as well. Just adding registers up to that
2027 * limit is fine, as long as the existing register indices don't
2030 #define SH_ETH_REG_DUMP_VERSION 1
2031 #define SH_ETH_REG_DUMP_MAX_REGS 256
2033 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
2035 struct sh_eth_private *mdp = netdev_priv(ndev);
2036 struct sh_eth_cpu_data *cd = mdp->cd;
2040 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
2042 /* Dump starts with a bitmap that tells ethtool which
2043 * registers are defined for this chip.
2045 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
2053 /* Add a register to the dump, if it has a defined offset.
2054 * This automatically skips most undefined registers, but for
2055 * some it is also necessary to check a capability flag in
2056 * struct sh_eth_cpu_data.
2058 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
2059 #define add_reg_from(reg, read_expr) do { \
2060 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \
2062 mark_reg_valid(reg); \
2063 *buf++ = read_expr; \
2068 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
2069 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
2135 if (cd->hw_checksum)
2141 add_tsu_reg(TSU_CTRST);
2142 add_tsu_reg(TSU_FWEN0);
2143 add_tsu_reg(TSU_FWEN1);
2144 add_tsu_reg(TSU_FCM);
2145 add_tsu_reg(TSU_BSYSL0);
2146 add_tsu_reg(TSU_BSYSL1);
2147 add_tsu_reg(TSU_PRISL0);
2148 add_tsu_reg(TSU_PRISL1);
2149 add_tsu_reg(TSU_FWSL0);
2150 add_tsu_reg(TSU_FWSL1);
2151 add_tsu_reg(TSU_FWSLC);
2152 add_tsu_reg(TSU_QTAGM0);
2153 add_tsu_reg(TSU_QTAGM1);
2154 add_tsu_reg(TSU_FWSR);
2155 add_tsu_reg(TSU_FWINMK);
2156 add_tsu_reg(TSU_ADQT0);
2157 add_tsu_reg(TSU_ADQT1);
2158 add_tsu_reg(TSU_VTAG0);
2159 add_tsu_reg(TSU_VTAG1);
2160 add_tsu_reg(TSU_ADSBSY);
2161 add_tsu_reg(TSU_TEN);
2162 add_tsu_reg(TSU_POST1);
2163 add_tsu_reg(TSU_POST2);
2164 add_tsu_reg(TSU_POST3);
2165 add_tsu_reg(TSU_POST4);
2166 /* This is the start of a table, not just a single register. */
2170 mark_reg_valid(TSU_ADRH0);
2171 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2172 *buf++ = ioread32(mdp->tsu_addr +
2173 mdp->reg_offset[TSU_ADRH0] +
2176 len += SH_ETH_TSU_CAM_ENTRIES * 2;
2179 #undef mark_reg_valid
2187 static int sh_eth_get_regs_len(struct net_device *ndev)
2189 return __sh_eth_get_regs(ndev, NULL);
2192 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2195 struct sh_eth_private *mdp = netdev_priv(ndev);
2197 regs->version = SH_ETH_REG_DUMP_VERSION;
2199 pm_runtime_get_sync(&mdp->pdev->dev);
2200 __sh_eth_get_regs(ndev, buf);
2201 pm_runtime_put_sync(&mdp->pdev->dev);
2204 static int sh_eth_nway_reset(struct net_device *ndev)
2206 struct sh_eth_private *mdp = netdev_priv(ndev);
2207 unsigned long flags;
2213 spin_lock_irqsave(&mdp->lock, flags);
2214 ret = phy_start_aneg(ndev->phydev);
2215 spin_unlock_irqrestore(&mdp->lock, flags);
2220 static u32 sh_eth_get_msglevel(struct net_device *ndev)
2222 struct sh_eth_private *mdp = netdev_priv(ndev);
2223 return mdp->msg_enable;
2226 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2228 struct sh_eth_private *mdp = netdev_priv(ndev);
2229 mdp->msg_enable = value;
2232 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2233 "rx_current", "tx_current",
2234 "rx_dirty", "tx_dirty",
2236 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
2238 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2242 return SH_ETH_STATS_LEN;
2248 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
2249 struct ethtool_stats *stats, u64 *data)
2251 struct sh_eth_private *mdp = netdev_priv(ndev);
2254 /* device-specific stats */
2255 data[i++] = mdp->cur_rx;
2256 data[i++] = mdp->cur_tx;
2257 data[i++] = mdp->dirty_rx;
2258 data[i++] = mdp->dirty_tx;
2261 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2263 switch (stringset) {
2265 memcpy(data, *sh_eth_gstrings_stats,
2266 sizeof(sh_eth_gstrings_stats));
2271 static void sh_eth_get_ringparam(struct net_device *ndev,
2272 struct ethtool_ringparam *ring)
2274 struct sh_eth_private *mdp = netdev_priv(ndev);
2276 ring->rx_max_pending = RX_RING_MAX;
2277 ring->tx_max_pending = TX_RING_MAX;
2278 ring->rx_pending = mdp->num_rx_ring;
2279 ring->tx_pending = mdp->num_tx_ring;
2282 static int sh_eth_set_ringparam(struct net_device *ndev,
2283 struct ethtool_ringparam *ring)
2285 struct sh_eth_private *mdp = netdev_priv(ndev);
2288 if (ring->tx_pending > TX_RING_MAX ||
2289 ring->rx_pending > RX_RING_MAX ||
2290 ring->tx_pending < TX_RING_MIN ||
2291 ring->rx_pending < RX_RING_MIN)
2293 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2296 if (netif_running(ndev)) {
2297 netif_device_detach(ndev);
2298 netif_tx_disable(ndev);
2300 /* Serialise with the interrupt handler and NAPI, then
2301 * disable interrupts. We have to clear the
2302 * irq_enabled flag first to ensure that interrupts
2303 * won't be re-enabled.
2305 mdp->irq_enabled = false;
2306 synchronize_irq(ndev->irq);
2307 napi_synchronize(&mdp->napi);
2308 sh_eth_write(ndev, 0x0000, EESIPR);
2310 sh_eth_dev_exit(ndev);
2312 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
2313 sh_eth_ring_free(ndev);
2316 /* Set new parameters */
2317 mdp->num_rx_ring = ring->rx_pending;
2318 mdp->num_tx_ring = ring->tx_pending;
2320 if (netif_running(ndev)) {
2321 ret = sh_eth_ring_init(ndev);
2323 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2327 ret = sh_eth_dev_init(ndev);
2329 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2334 netif_device_attach(ndev);
2340 static void sh_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2342 struct sh_eth_private *mdp = netdev_priv(ndev);
2347 if (mdp->cd->magic) {
2348 wol->supported = WAKE_MAGIC;
2349 wol->wolopts = mdp->wol_enabled ? WAKE_MAGIC : 0;
2353 static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2355 struct sh_eth_private *mdp = netdev_priv(ndev);
2357 if (!mdp->cd->magic || wol->wolopts & ~WAKE_MAGIC)
2360 mdp->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
2362 device_set_wakeup_enable(&mdp->pdev->dev, mdp->wol_enabled);
2367 static const struct ethtool_ops sh_eth_ethtool_ops = {
2368 .get_regs_len = sh_eth_get_regs_len,
2369 .get_regs = sh_eth_get_regs,
2370 .nway_reset = sh_eth_nway_reset,
2371 .get_msglevel = sh_eth_get_msglevel,
2372 .set_msglevel = sh_eth_set_msglevel,
2373 .get_link = ethtool_op_get_link,
2374 .get_strings = sh_eth_get_strings,
2375 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2376 .get_sset_count = sh_eth_get_sset_count,
2377 .get_ringparam = sh_eth_get_ringparam,
2378 .set_ringparam = sh_eth_set_ringparam,
2379 .get_link_ksettings = sh_eth_get_link_ksettings,
2380 .set_link_ksettings = sh_eth_set_link_ksettings,
2381 .get_wol = sh_eth_get_wol,
2382 .set_wol = sh_eth_set_wol,
2385 /* network device open function */
2386 static int sh_eth_open(struct net_device *ndev)
2388 struct sh_eth_private *mdp = netdev_priv(ndev);
2391 pm_runtime_get_sync(&mdp->pdev->dev);
2393 napi_enable(&mdp->napi);
2395 ret = request_irq(ndev->irq, sh_eth_interrupt,
2396 mdp->cd->irq_flags, ndev->name, ndev);
2398 netdev_err(ndev, "Can not assign IRQ number\n");
2402 /* Descriptor set */
2403 ret = sh_eth_ring_init(ndev);
2408 ret = sh_eth_dev_init(ndev);
2412 /* PHY control start*/
2413 ret = sh_eth_phy_start(ndev);
2417 netif_start_queue(ndev);
2424 free_irq(ndev->irq, ndev);
2426 napi_disable(&mdp->napi);
2427 pm_runtime_put_sync(&mdp->pdev->dev);
2431 /* Timeout function */
2432 static void sh_eth_tx_timeout(struct net_device *ndev)
2434 struct sh_eth_private *mdp = netdev_priv(ndev);
2435 struct sh_eth_rxdesc *rxdesc;
2438 netif_stop_queue(ndev);
2440 netif_err(mdp, timer, ndev,
2441 "transmit timed out, status %8.8x, resetting...\n",
2442 sh_eth_read(ndev, EESR));
2444 /* tx_errors count up */
2445 ndev->stats.tx_errors++;
2447 /* Free all the skbuffs in the Rx queue. */
2448 for (i = 0; i < mdp->num_rx_ring; i++) {
2449 rxdesc = &mdp->rx_ring[i];
2450 rxdesc->status = cpu_to_le32(0);
2451 rxdesc->addr = cpu_to_le32(0xBADF00D0);
2452 dev_kfree_skb(mdp->rx_skbuff[i]);
2453 mdp->rx_skbuff[i] = NULL;
2455 for (i = 0; i < mdp->num_tx_ring; i++) {
2456 dev_kfree_skb(mdp->tx_skbuff[i]);
2457 mdp->tx_skbuff[i] = NULL;
2461 sh_eth_dev_init(ndev);
2463 netif_start_queue(ndev);
2466 /* Packet transmit function */
2467 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2469 struct sh_eth_private *mdp = netdev_priv(ndev);
2470 struct sh_eth_txdesc *txdesc;
2471 dma_addr_t dma_addr;
2473 unsigned long flags;
2475 spin_lock_irqsave(&mdp->lock, flags);
2476 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2477 if (!sh_eth_tx_free(ndev, true)) {
2478 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2479 netif_stop_queue(ndev);
2480 spin_unlock_irqrestore(&mdp->lock, flags);
2481 return NETDEV_TX_BUSY;
2484 spin_unlock_irqrestore(&mdp->lock, flags);
2486 if (skb_put_padto(skb, ETH_ZLEN))
2487 return NETDEV_TX_OK;
2489 entry = mdp->cur_tx % mdp->num_tx_ring;
2490 mdp->tx_skbuff[entry] = skb;
2491 txdesc = &mdp->tx_ring[entry];
2493 if (!mdp->cd->hw_swap)
2494 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
2495 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, skb->len,
2497 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
2499 return NETDEV_TX_OK;
2501 txdesc->addr = cpu_to_le32(dma_addr);
2502 txdesc->len = cpu_to_le32(skb->len << 16);
2504 dma_wmb(); /* TACT bit must be set after all the above writes */
2505 if (entry >= mdp->num_tx_ring - 1)
2506 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
2508 txdesc->status |= cpu_to_le32(TD_TACT);
2512 if (!(sh_eth_read(ndev, EDTRR) & mdp->cd->edtrr_trns))
2513 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR);
2515 return NETDEV_TX_OK;
2518 /* The statistics registers have write-clear behaviour, which means we
2519 * will lose any increment between the read and write. We mitigate
2520 * this by only clearing when we read a non-zero value, so we will
2521 * never falsely report a total of zero.
2524 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2526 u32 delta = sh_eth_read(ndev, reg);
2530 sh_eth_write(ndev, 0, reg);
2534 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2536 struct sh_eth_private *mdp = netdev_priv(ndev);
2538 if (mdp->cd->no_tx_cntrs)
2539 return &ndev->stats;
2541 if (!mdp->is_opened)
2542 return &ndev->stats;
2544 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2545 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2546 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
2548 if (mdp->cd->cexcr) {
2549 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2551 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2554 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2558 return &ndev->stats;
2561 /* device close function */
2562 static int sh_eth_close(struct net_device *ndev)
2564 struct sh_eth_private *mdp = netdev_priv(ndev);
2566 netif_stop_queue(ndev);
2568 /* Serialise with the interrupt handler and NAPI, then disable
2569 * interrupts. We have to clear the irq_enabled flag first to
2570 * ensure that interrupts won't be re-enabled.
2572 mdp->irq_enabled = false;
2573 synchronize_irq(ndev->irq);
2574 napi_disable(&mdp->napi);
2575 sh_eth_write(ndev, 0x0000, EESIPR);
2577 sh_eth_dev_exit(ndev);
2579 /* PHY Disconnect */
2581 phy_stop(ndev->phydev);
2582 phy_disconnect(ndev->phydev);
2585 free_irq(ndev->irq, ndev);
2587 /* Free all the skbuffs in the Rx queue and the DMA buffer. */
2588 sh_eth_ring_free(ndev);
2590 pm_runtime_put_sync(&mdp->pdev->dev);
2597 /* ioctl to device function */
2598 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2600 struct phy_device *phydev = ndev->phydev;
2602 if (!netif_running(ndev))
2608 return phy_mii_ioctl(phydev, rq, cmd);
2611 static int sh_eth_change_mtu(struct net_device *ndev, int new_mtu)
2613 if (netif_running(ndev))
2616 ndev->mtu = new_mtu;
2617 netdev_update_features(ndev);
2622 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2623 static u32 sh_eth_tsu_get_post_mask(int entry)
2625 return 0x0f << (28 - ((entry % 8) * 4));
2628 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2630 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2633 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2636 struct sh_eth_private *mdp = netdev_priv(ndev);
2637 int reg = TSU_POST1 + entry / 8;
2640 tmp = sh_eth_tsu_read(mdp, reg);
2641 sh_eth_tsu_write(mdp, tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg);
2644 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2647 struct sh_eth_private *mdp = netdev_priv(ndev);
2648 int reg = TSU_POST1 + entry / 8;
2649 u32 post_mask, ref_mask, tmp;
2651 post_mask = sh_eth_tsu_get_post_mask(entry);
2652 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2654 tmp = sh_eth_tsu_read(mdp, reg);
2655 sh_eth_tsu_write(mdp, tmp & ~post_mask, reg);
2657 /* If other port enables, the function returns "true" */
2658 return tmp & ref_mask;
2661 static int sh_eth_tsu_busy(struct net_device *ndev)
2663 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2664 struct sh_eth_private *mdp = netdev_priv(ndev);
2666 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2670 netdev_err(ndev, "%s: timeout\n", __func__);
2678 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2683 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2684 iowrite32(val, reg);
2685 if (sh_eth_tsu_busy(ndev) < 0)
2688 val = addr[4] << 8 | addr[5];
2689 iowrite32(val, reg + 4);
2690 if (sh_eth_tsu_busy(ndev) < 0)
2696 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2700 val = ioread32(reg);
2701 addr[0] = (val >> 24) & 0xff;
2702 addr[1] = (val >> 16) & 0xff;
2703 addr[2] = (val >> 8) & 0xff;
2704 addr[3] = val & 0xff;
2705 val = ioread32(reg + 4);
2706 addr[4] = (val >> 8) & 0xff;
2707 addr[5] = val & 0xff;
2711 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2713 struct sh_eth_private *mdp = netdev_priv(ndev);
2714 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2716 u8 c_addr[ETH_ALEN];
2718 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2719 sh_eth_tsu_read_entry(reg_offset, c_addr);
2720 if (ether_addr_equal(addr, c_addr))
2727 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2732 memset(blank, 0, sizeof(blank));
2733 entry = sh_eth_tsu_find_entry(ndev, blank);
2734 return (entry < 0) ? -ENOMEM : entry;
2737 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2740 struct sh_eth_private *mdp = netdev_priv(ndev);
2741 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2745 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2746 ~(1 << (31 - entry)), TSU_TEN);
2748 memset(blank, 0, sizeof(blank));
2749 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2755 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2757 struct sh_eth_private *mdp = netdev_priv(ndev);
2758 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2764 i = sh_eth_tsu_find_entry(ndev, addr);
2766 /* No entry found, create one */
2767 i = sh_eth_tsu_find_empty(ndev);
2770 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2774 /* Enable the entry */
2775 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2776 (1 << (31 - i)), TSU_TEN);
2779 /* Entry found or created, enable POST */
2780 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2785 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2787 struct sh_eth_private *mdp = netdev_priv(ndev);
2793 i = sh_eth_tsu_find_entry(ndev, addr);
2796 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2799 /* Disable the entry if both ports was disabled */
2800 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2808 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2810 struct sh_eth_private *mdp = netdev_priv(ndev);
2816 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2817 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2820 /* Disable the entry if both ports was disabled */
2821 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2829 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2831 struct sh_eth_private *mdp = netdev_priv(ndev);
2833 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2839 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2840 sh_eth_tsu_read_entry(reg_offset, addr);
2841 if (is_multicast_ether_addr(addr))
2842 sh_eth_tsu_del_entry(ndev, addr);
2846 /* Update promiscuous flag and multicast filter */
2847 static void sh_eth_set_rx_mode(struct net_device *ndev)
2849 struct sh_eth_private *mdp = netdev_priv(ndev);
2852 unsigned long flags;
2854 spin_lock_irqsave(&mdp->lock, flags);
2855 /* Initial condition is MCT = 1, PRM = 0.
2856 * Depending on ndev->flags, set PRM or clear MCT
2858 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2860 ecmr_bits |= ECMR_MCT;
2862 if (!(ndev->flags & IFF_MULTICAST)) {
2863 sh_eth_tsu_purge_mcast(ndev);
2866 if (ndev->flags & IFF_ALLMULTI) {
2867 sh_eth_tsu_purge_mcast(ndev);
2868 ecmr_bits &= ~ECMR_MCT;
2872 if (ndev->flags & IFF_PROMISC) {
2873 sh_eth_tsu_purge_all(ndev);
2874 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2875 } else if (mdp->cd->tsu) {
2876 struct netdev_hw_addr *ha;
2877 netdev_for_each_mc_addr(ha, ndev) {
2878 if (mcast_all && is_multicast_ether_addr(ha->addr))
2881 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2883 sh_eth_tsu_purge_mcast(ndev);
2884 ecmr_bits &= ~ECMR_MCT;
2891 /* update the ethernet mode */
2892 sh_eth_write(ndev, ecmr_bits, ECMR);
2894 spin_unlock_irqrestore(&mdp->lock, flags);
2897 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2905 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2906 __be16 proto, u16 vid)
2908 struct sh_eth_private *mdp = netdev_priv(ndev);
2909 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2911 if (unlikely(!mdp->cd->tsu))
2914 /* No filtering if vid = 0 */
2918 mdp->vlan_num_ids++;
2920 /* The controller has one VLAN tag HW filter. So, if the filter is
2921 * already enabled, the driver disables it and the filte
2923 if (mdp->vlan_num_ids > 1) {
2924 /* disable VLAN filter */
2925 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2929 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2935 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2936 __be16 proto, u16 vid)
2938 struct sh_eth_private *mdp = netdev_priv(ndev);
2939 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2941 if (unlikely(!mdp->cd->tsu))
2944 /* No filtering if vid = 0 */
2948 mdp->vlan_num_ids--;
2949 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2954 /* SuperH's TSU register init function */
2955 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2957 if (!mdp->cd->dual_port) {
2958 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2959 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL,
2960 TSU_FWSLC); /* Enable POST registers */
2964 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2965 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2966 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2967 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2968 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2969 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2970 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2971 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2972 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2973 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2974 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2975 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2976 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2977 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2978 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2979 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2980 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2981 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2982 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
2985 /* MDIO bus release function */
2986 static int sh_mdio_release(struct sh_eth_private *mdp)
2988 /* unregister mdio bus */
2989 mdiobus_unregister(mdp->mii_bus);
2991 /* free bitbang info */
2992 free_mdio_bitbang(mdp->mii_bus);
2997 /* MDIO bus init function */
2998 static int sh_mdio_init(struct sh_eth_private *mdp,
2999 struct sh_eth_plat_data *pd)
3002 struct bb_info *bitbang;
3003 struct platform_device *pdev = mdp->pdev;
3004 struct device *dev = &mdp->pdev->dev;
3006 /* create bit control struct for PHY */
3007 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
3012 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
3013 bitbang->set_gate = pd->set_mdio_gate;
3014 bitbang->ctrl.ops = &bb_ops;
3016 /* MII controller setting */
3017 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
3021 /* Hook up MII support for ethtool */
3022 mdp->mii_bus->name = "sh_mii";
3023 mdp->mii_bus->parent = dev;
3024 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
3025 pdev->name, pdev->id);
3027 /* register MDIO bus */
3028 if (pd->phy_irq > 0)
3029 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
3031 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
3038 free_mdio_bitbang(mdp->mii_bus);
3042 static const u16 *sh_eth_get_register_offset(int register_type)
3044 const u16 *reg_offset = NULL;
3046 switch (register_type) {
3047 case SH_ETH_REG_GIGABIT:
3048 reg_offset = sh_eth_offset_gigabit;
3050 case SH_ETH_REG_FAST_RZ:
3051 reg_offset = sh_eth_offset_fast_rz;
3053 case SH_ETH_REG_FAST_RCAR:
3054 reg_offset = sh_eth_offset_fast_rcar;
3056 case SH_ETH_REG_FAST_SH4:
3057 reg_offset = sh_eth_offset_fast_sh4;
3059 case SH_ETH_REG_FAST_SH3_SH2:
3060 reg_offset = sh_eth_offset_fast_sh3_sh2;
3067 static const struct net_device_ops sh_eth_netdev_ops = {
3068 .ndo_open = sh_eth_open,
3069 .ndo_stop = sh_eth_close,
3070 .ndo_start_xmit = sh_eth_start_xmit,
3071 .ndo_get_stats = sh_eth_get_stats,
3072 .ndo_set_rx_mode = sh_eth_set_rx_mode,
3073 .ndo_tx_timeout = sh_eth_tx_timeout,
3074 .ndo_do_ioctl = sh_eth_do_ioctl,
3075 .ndo_change_mtu = sh_eth_change_mtu,
3076 .ndo_validate_addr = eth_validate_addr,
3077 .ndo_set_mac_address = eth_mac_addr,
3080 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
3081 .ndo_open = sh_eth_open,
3082 .ndo_stop = sh_eth_close,
3083 .ndo_start_xmit = sh_eth_start_xmit,
3084 .ndo_get_stats = sh_eth_get_stats,
3085 .ndo_set_rx_mode = sh_eth_set_rx_mode,
3086 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
3087 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
3088 .ndo_tx_timeout = sh_eth_tx_timeout,
3089 .ndo_do_ioctl = sh_eth_do_ioctl,
3090 .ndo_change_mtu = sh_eth_change_mtu,
3091 .ndo_validate_addr = eth_validate_addr,
3092 .ndo_set_mac_address = eth_mac_addr,
3096 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3098 struct device_node *np = dev->of_node;
3099 struct sh_eth_plat_data *pdata;
3100 const char *mac_addr;
3102 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3106 pdata->phy_interface = of_get_phy_mode(np);
3108 mac_addr = of_get_mac_address(np);
3110 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
3112 pdata->no_ether_link =
3113 of_property_read_bool(np, "renesas,no-ether-link");
3114 pdata->ether_link_active_low =
3115 of_property_read_bool(np, "renesas,ether-link-active-low");
3120 static const struct of_device_id sh_eth_match_table[] = {
3121 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
3122 { .compatible = "renesas,ether-r8a7743", .data = &rcar_gen2_data },
3123 { .compatible = "renesas,ether-r8a7745", .data = &rcar_gen2_data },
3124 { .compatible = "renesas,ether-r8a7778", .data = &rcar_gen1_data },
3125 { .compatible = "renesas,ether-r8a7779", .data = &rcar_gen1_data },
3126 { .compatible = "renesas,ether-r8a7790", .data = &rcar_gen2_data },
3127 { .compatible = "renesas,ether-r8a7791", .data = &rcar_gen2_data },
3128 { .compatible = "renesas,ether-r8a7793", .data = &rcar_gen2_data },
3129 { .compatible = "renesas,ether-r8a7794", .data = &rcar_gen2_data },
3130 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
3131 { .compatible = "renesas,rcar-gen1-ether", .data = &rcar_gen1_data },
3132 { .compatible = "renesas,rcar-gen2-ether", .data = &rcar_gen2_data },
3135 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
3137 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3143 static int sh_eth_drv_probe(struct platform_device *pdev)
3145 struct resource *res;
3146 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
3147 const struct platform_device_id *id = platform_get_device_id(pdev);
3148 struct sh_eth_private *mdp;
3149 struct net_device *ndev;
3153 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3155 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
3159 pm_runtime_enable(&pdev->dev);
3160 pm_runtime_get_sync(&pdev->dev);
3162 ret = platform_get_irq(pdev, 0);
3167 SET_NETDEV_DEV(ndev, &pdev->dev);
3169 mdp = netdev_priv(ndev);
3170 mdp->num_tx_ring = TX_RING_SIZE;
3171 mdp->num_rx_ring = RX_RING_SIZE;
3172 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3173 if (IS_ERR(mdp->addr)) {
3174 ret = PTR_ERR(mdp->addr);
3178 ndev->base_addr = res->start;
3180 spin_lock_init(&mdp->lock);
3183 if (pdev->dev.of_node)
3184 pd = sh_eth_parse_dt(&pdev->dev);
3186 dev_err(&pdev->dev, "no platform data\n");
3192 mdp->phy_id = pd->phy;
3193 mdp->phy_interface = pd->phy_interface;
3194 mdp->no_ether_link = pd->no_ether_link;
3195 mdp->ether_link_active_low = pd->ether_link_active_low;
3199 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3201 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev);
3203 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
3204 if (!mdp->reg_offset) {
3205 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3206 mdp->cd->register_type);
3210 sh_eth_set_default_cpu_data(mdp->cd);
3212 /* User's manual states max MTU should be 2048 but due to the
3213 * alignment calculations in sh_eth_ring_init() the practical
3214 * MTU is a bit less. Maybe this can be optimized some more.
3216 ndev->max_mtu = 2000 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
3217 ndev->min_mtu = ETH_MIN_MTU;
3221 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3223 ndev->netdev_ops = &sh_eth_netdev_ops;
3224 ndev->ethtool_ops = &sh_eth_ethtool_ops;
3225 ndev->watchdog_timeo = TX_TIMEOUT;
3227 /* debug message level */
3228 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
3230 /* read and set MAC address */
3231 read_mac_address(ndev, pd->mac_addr);
3232 if (!is_valid_ether_addr(ndev->dev_addr)) {
3233 dev_warn(&pdev->dev,
3234 "no valid MAC address supplied, using a random one.\n");
3235 eth_hw_addr_random(ndev);
3239 int port = pdev->id < 0 ? 0 : pdev->id % 2;
3240 struct resource *rtsu;
3242 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3244 dev_err(&pdev->dev, "no TSU resource\n");
3248 /* We can only request the TSU region for the first port
3249 * of the two sharing this TSU for the probe to succeed...
3252 !devm_request_mem_region(&pdev->dev, rtsu->start,
3253 resource_size(rtsu),
3254 dev_name(&pdev->dev))) {
3255 dev_err(&pdev->dev, "can't request TSU resource.\n");
3259 /* ioremap the TSU registers */
3260 mdp->tsu_addr = devm_ioremap(&pdev->dev, rtsu->start,
3261 resource_size(rtsu));
3262 if (!mdp->tsu_addr) {
3263 dev_err(&pdev->dev, "TSU region ioremap() failed.\n");
3268 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
3270 /* Need to init only the first port of the two sharing a TSU */
3272 if (mdp->cd->chip_reset)
3273 mdp->cd->chip_reset(ndev);
3275 /* TSU init (Init only)*/
3276 sh_eth_tsu_init(mdp);
3280 if (mdp->cd->rmiimode)
3281 sh_eth_write(ndev, 0x1, RMIIMODE);
3284 ret = sh_mdio_init(mdp, pd);
3286 if (ret != -EPROBE_DEFER)
3287 dev_err(&pdev->dev, "MDIO init failed: %d\n", ret);
3291 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3293 /* network device register */
3294 ret = register_netdev(ndev);
3299 device_set_wakeup_capable(&pdev->dev, 1);
3301 /* print device information */
3302 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3303 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
3305 pm_runtime_put(&pdev->dev);
3306 platform_set_drvdata(pdev, ndev);
3311 netif_napi_del(&mdp->napi);
3312 sh_mdio_release(mdp);
3318 pm_runtime_put(&pdev->dev);
3319 pm_runtime_disable(&pdev->dev);
3323 static int sh_eth_drv_remove(struct platform_device *pdev)
3325 struct net_device *ndev = platform_get_drvdata(pdev);
3326 struct sh_eth_private *mdp = netdev_priv(ndev);
3328 unregister_netdev(ndev);
3329 netif_napi_del(&mdp->napi);
3330 sh_mdio_release(mdp);
3331 pm_runtime_disable(&pdev->dev);
3338 #ifdef CONFIG_PM_SLEEP
3339 static int sh_eth_wol_setup(struct net_device *ndev)
3341 struct sh_eth_private *mdp = netdev_priv(ndev);
3343 /* Only allow ECI interrupts */
3344 synchronize_irq(ndev->irq);
3345 napi_disable(&mdp->napi);
3346 sh_eth_write(ndev, EESIPR_ECIIP, EESIPR);
3348 /* Enable MagicPacket */
3349 sh_eth_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
3351 return enable_irq_wake(ndev->irq);
3354 static int sh_eth_wol_restore(struct net_device *ndev)
3356 struct sh_eth_private *mdp = netdev_priv(ndev);
3359 napi_enable(&mdp->napi);
3361 /* Disable MagicPacket */
3362 sh_eth_modify(ndev, ECMR, ECMR_MPDE, 0);
3364 /* The device needs to be reset to restore MagicPacket logic
3365 * for next wakeup. If we close and open the device it will
3366 * both be reset and all registers restored. This is what
3367 * happens during suspend and resume without WoL enabled.
3369 ret = sh_eth_close(ndev);
3372 ret = sh_eth_open(ndev);
3376 return disable_irq_wake(ndev->irq);
3379 static int sh_eth_suspend(struct device *dev)
3381 struct net_device *ndev = dev_get_drvdata(dev);
3382 struct sh_eth_private *mdp = netdev_priv(ndev);
3385 if (!netif_running(ndev))
3388 netif_device_detach(ndev);
3390 if (mdp->wol_enabled)
3391 ret = sh_eth_wol_setup(ndev);
3393 ret = sh_eth_close(ndev);
3398 static int sh_eth_resume(struct device *dev)
3400 struct net_device *ndev = dev_get_drvdata(dev);
3401 struct sh_eth_private *mdp = netdev_priv(ndev);
3404 if (!netif_running(ndev))
3407 if (mdp->wol_enabled)
3408 ret = sh_eth_wol_restore(ndev);
3410 ret = sh_eth_open(ndev);
3415 netif_device_attach(ndev);
3421 static int sh_eth_runtime_nop(struct device *dev)
3423 /* Runtime PM callback shared between ->runtime_suspend()
3424 * and ->runtime_resume(). Simply returns success.
3426 * This driver re-initializes all registers after
3427 * pm_runtime_get_sync() anyway so there is no need
3428 * to save and restore registers here.
3433 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
3434 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
3435 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
3437 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3439 #define SH_ETH_PM_OPS NULL
3442 static const struct platform_device_id sh_eth_id_table[] = {
3443 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3444 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3445 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3446 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3447 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3448 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3449 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3452 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3454 static struct platform_driver sh_eth_driver = {
3455 .probe = sh_eth_drv_probe,
3456 .remove = sh_eth_drv_remove,
3457 .id_table = sh_eth_id_table,
3460 .pm = SH_ETH_PM_OPS,
3461 .of_match_table = of_match_ptr(sh_eth_match_table),
3465 module_platform_driver(sh_eth_driver);
3467 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3468 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3469 MODULE_LICENSE("GPL v2");