drivers/net/ethernet/renesas/sh_eth.c

   1 /*  SuperH Ethernet device driver
   2  *
   3  *  Copyright (C) 2014 Renesas Electronics Corporation
   4  *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
   5  *  Copyright (C) 2008-2014 Renesas Solutions Corp.
   6  *  Copyright (C) 2013-2017 Cogent Embedded, Inc.
   7  *  Copyright (C) 2014 Codethink Limited
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms and conditions of the GNU General Public License,
  11  *  version 2, as published by the Free Software Foundation.
  12  *
  13  *  This program is distributed in the hope it will be useful, but WITHOUT
  14  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  16  *  more details.
  17  *
  18  *  The full GNU General Public License is included in this distribution in
  19  *  the file called "COPYING".
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/etherdevice.h>
  28 #include <linux/delay.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/mdio-bitbang.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/of.h>
  33 #include <linux/of_device.h>
  34 #include <linux/of_irq.h>
  35 #include <linux/of_net.h>
  36 #include <linux/phy.h>
  37 #include <linux/cache.h>
  38 #include <linux/io.h>
  39 #include <linux/pm_runtime.h>
  40 #include <linux/slab.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/clk.h>
  44 #include <linux/sh_eth.h>
  45 #include <linux/of_mdio.h>
  46
  47 #include "sh_eth.h"
  48
  49 #define SH_ETH_DEF_MSG_ENABLE \
  50                 (NETIF_MSG_LINK | \
  51                 NETIF_MSG_TIMER | \
  52                 NETIF_MSG_RX_ERR| \
  53                 NETIF_MSG_TX_ERR)
  54
  55 #define SH_ETH_OFFSET_INVALID   ((u16)~0)
  56
  57 #define SH_ETH_OFFSET_DEFAULTS                  \
  58         [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
  59
  60 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
  61         SH_ETH_OFFSET_DEFAULTS,
  62
  63         [EDSR]          = 0x0000,
  64         [EDMR]          = 0x0400,
  65         [EDTRR]         = 0x0408,
  66         [EDRRR]         = 0x0410,
  67         [EESR]          = 0x0428,
  68         [EESIPR]        = 0x0430,
  69         [TDLAR]         = 0x0010,
  70         [TDFAR]         = 0x0014,
  71         [TDFXR]         = 0x0018,
  72         [TDFFR]         = 0x001c,
  73         [RDLAR]         = 0x0030,
  74         [RDFAR]         = 0x0034,
  75         [RDFXR]         = 0x0038,
  76         [RDFFR]         = 0x003c,
  77         [TRSCER]        = 0x0438,
  78         [RMFCR]         = 0x0440,
  79         [TFTR]          = 0x0448,
  80         [FDR]           = 0x0450,
  81         [RMCR]          = 0x0458,
  82         [RPADIR]        = 0x0460,
  83         [FCFTR]         = 0x0468,
  84         [CSMR]          = 0x04E4,
  85
  86         [ECMR]          = 0x0500,
  87         [ECSR]          = 0x0510,
  88         [ECSIPR]        = 0x0518,
  89         [PIR]           = 0x0520,
  90         [PSR]           = 0x0528,
  91         [PIPR]          = 0x052c,
  92         [RFLR]          = 0x0508,
  93         [APR]           = 0x0554,
  94         [MPR]           = 0x0558,
  95         [PFTCR]         = 0x055c,
  96         [PFRCR]         = 0x0560,
  97         [TPAUSER]       = 0x0564,
  98         [GECMR]         = 0x05b0,
  99         [BCULR]         = 0x05b4,
 100         [MAHR]          = 0x05c0,
 101         [MALR]          = 0x05c8,
 102         [TROCR]         = 0x0700,
 103         [CDCR]          = 0x0708,
 104         [LCCR]          = 0x0710,
 105         [CEFCR]         = 0x0740,
 106         [FRECR]         = 0x0748,
 107         [TSFRCR]        = 0x0750,
 108         [TLFRCR]        = 0x0758,
 109         [RFCR]          = 0x0760,
 110         [CERCR]         = 0x0768,
 111         [CEECR]         = 0x0770,
 112         [MAFCR]         = 0x0778,
 113         [RMII_MII]      = 0x0790,
 114
 115         [ARSTR]         = 0x0000,
 116         [TSU_CTRST]     = 0x0004,
 117         [TSU_FWEN0]     = 0x0010,
 118         [TSU_FWEN1]     = 0x0014,
 119         [TSU_FCM]       = 0x0018,
 120         [TSU_BSYSL0]    = 0x0020,
 121         [TSU_BSYSL1]    = 0x0024,
 122         [TSU_PRISL0]    = 0x0028,
 123         [TSU_PRISL1]    = 0x002c,
 124         [TSU_FWSL0]     = 0x0030,
 125         [TSU_FWSL1]     = 0x0034,
 126         [TSU_FWSLC]     = 0x0038,
 127         [TSU_QTAG0]     = 0x0040,
 128         [TSU_QTAG1]     = 0x0044,
 129         [TSU_FWSR]      = 0x0050,
 130         [TSU_FWINMK]    = 0x0054,
 131         [TSU_ADQT0]     = 0x0048,
 132         [TSU_ADQT1]     = 0x004c,
 133         [TSU_VTAG0]     = 0x0058,
 134         [TSU_VTAG1]     = 0x005c,
 135         [TSU_ADSBSY]    = 0x0060,
 136         [TSU_TEN]       = 0x0064,
 137         [TSU_POST1]     = 0x0070,
 138         [TSU_POST2]     = 0x0074,
 139         [TSU_POST3]     = 0x0078,
 140         [TSU_POST4]     = 0x007c,
 141         [TSU_ADRH0]     = 0x0100,
 142
 143         [TXNLCR0]       = 0x0080,
 144         [TXALCR0]       = 0x0084,
 145         [RXNLCR0]       = 0x0088,
 146         [RXALCR0]       = 0x008c,
 147         [FWNLCR0]       = 0x0090,
 148         [FWALCR0]       = 0x0094,
 149         [TXNLCR1]       = 0x00a0,
 150         [TXALCR1]       = 0x00a0,
 151         [RXNLCR1]       = 0x00a8,
 152         [RXALCR1]       = 0x00ac,
 153         [FWNLCR1]       = 0x00b0,
 154         [FWALCR1]       = 0x00b4,
 155 };
 156
 157 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
 158         SH_ETH_OFFSET_DEFAULTS,
 159
 160         [EDSR]          = 0x0000,
 161         [EDMR]          = 0x0400,
 162         [EDTRR]         = 0x0408,
 163         [EDRRR]         = 0x0410,
 164         [EESR]          = 0x0428,
 165         [EESIPR]        = 0x0430,
 166         [TDLAR]         = 0x0010,
 167         [TDFAR]         = 0x0014,
 168         [TDFXR]         = 0x0018,
 169         [TDFFR]         = 0x001c,
 170         [RDLAR]         = 0x0030,
 171         [RDFAR]         = 0x0034,
 172         [RDFXR]         = 0x0038,
 173         [RDFFR]         = 0x003c,
 174         [TRSCER]        = 0x0438,
 175         [RMFCR]         = 0x0440,
 176         [TFTR]          = 0x0448,
 177         [FDR]           = 0x0450,
 178         [RMCR]          = 0x0458,
 179         [RPADIR]        = 0x0460,
 180         [FCFTR]         = 0x0468,
 181         [CSMR]          = 0x04E4,
 182
 183         [ECMR]          = 0x0500,
 184         [RFLR]          = 0x0508,
 185         [ECSR]          = 0x0510,
 186         [ECSIPR]        = 0x0518,
 187         [PIR]           = 0x0520,
 188         [APR]           = 0x0554,
 189         [MPR]           = 0x0558,
 190         [PFTCR]         = 0x055c,
 191         [PFRCR]         = 0x0560,
 192         [TPAUSER]       = 0x0564,
 193         [MAHR]          = 0x05c0,
 194         [MALR]          = 0x05c8,
 195         [CEFCR]         = 0x0740,
 196         [FRECR]         = 0x0748,
 197         [TSFRCR]        = 0x0750,
 198         [TLFRCR]        = 0x0758,
 199         [RFCR]          = 0x0760,
 200         [MAFCR]         = 0x0778,
 201
 202         [ARSTR]         = 0x0000,
 203         [TSU_CTRST]     = 0x0004,
 204         [TSU_FWSLC]     = 0x0038,
 205         [TSU_VTAG0]     = 0x0058,
 206         [TSU_ADSBSY]    = 0x0060,
 207         [TSU_TEN]       = 0x0064,
 208         [TSU_POST1]     = 0x0070,
 209         [TSU_POST2]     = 0x0074,
 210         [TSU_POST3]     = 0x0078,
 211         [TSU_POST4]     = 0x007c,
 212         [TSU_ADRH0]     = 0x0100,
 213
 214         [TXNLCR0]       = 0x0080,
 215         [TXALCR0]       = 0x0084,
 216         [RXNLCR0]       = 0x0088,
 217         [RXALCR0]       = 0x008C,
 218 };
 219
 220 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
 221         SH_ETH_OFFSET_DEFAULTS,
 222
 223         [ECMR]          = 0x0300,
 224         [RFLR]          = 0x0308,
 225         [ECSR]          = 0x0310,
 226         [ECSIPR]        = 0x0318,
 227         [PIR]           = 0x0320,
 228         [PSR]           = 0x0328,
 229         [RDMLR]         = 0x0340,
 230         [IPGR]          = 0x0350,
 231         [APR]           = 0x0354,
 232         [MPR]           = 0x0358,
 233         [RFCF]          = 0x0360,
 234         [TPAUSER]       = 0x0364,
 235         [TPAUSECR]      = 0x0368,
 236         [MAHR]          = 0x03c0,
 237         [MALR]          = 0x03c8,
 238         [TROCR]         = 0x03d0,
 239         [CDCR]          = 0x03d4,
 240         [LCCR]          = 0x03d8,
 241         [CNDCR]         = 0x03dc,
 242         [CEFCR]         = 0x03e4,
 243         [FRECR]         = 0x03e8,
 244         [TSFRCR]        = 0x03ec,
 245         [TLFRCR]        = 0x03f0,
 246         [RFCR]          = 0x03f4,
 247         [MAFCR]         = 0x03f8,
 248
 249         [EDMR]          = 0x0200,
 250         [EDTRR]         = 0x0208,
 251         [EDRRR]         = 0x0210,
 252         [TDLAR]         = 0x0218,
 253         [RDLAR]         = 0x0220,
 254         [EESR]          = 0x0228,
 255         [EESIPR]        = 0x0230,
 256         [TRSCER]        = 0x0238,
 257         [RMFCR]         = 0x0240,
 258         [TFTR]          = 0x0248,
 259         [FDR]           = 0x0250,
 260         [RMCR]          = 0x0258,
 261         [TFUCR]         = 0x0264,
 262         [RFOCR]         = 0x0268,
 263         [RMIIMODE]      = 0x026c,
 264         [FCFTR]         = 0x0270,
 265         [TRIMD]         = 0x027c,
 266 };
 267
 268 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 269         SH_ETH_OFFSET_DEFAULTS,
 270
 271         [ECMR]          = 0x0100,
 272         [RFLR]          = 0x0108,
 273         [ECSR]          = 0x0110,
 274         [ECSIPR]        = 0x0118,
 275         [PIR]           = 0x0120,
 276         [PSR]           = 0x0128,
 277         [RDMLR]         = 0x0140,
 278         [IPGR]          = 0x0150,
 279         [APR]           = 0x0154,
 280         [MPR]           = 0x0158,
 281         [TPAUSER]       = 0x0164,
 282         [RFCF]          = 0x0160,
 283         [TPAUSECR]      = 0x0168,
 284         [BCFRR]         = 0x016c,
 285         [MAHR]          = 0x01c0,
 286         [MALR]          = 0x01c8,
 287         [TROCR]         = 0x01d0,
 288         [CDCR]          = 0x01d4,
 289         [LCCR]          = 0x01d8,
 290         [CNDCR]         = 0x01dc,
 291         [CEFCR]         = 0x01e4,
 292         [FRECR]         = 0x01e8,
 293         [TSFRCR]        = 0x01ec,
 294         [TLFRCR]        = 0x01f0,
 295         [RFCR]          = 0x01f4,
 296         [MAFCR]         = 0x01f8,
 297         [RTRATE]        = 0x01fc,
 298
 299         [EDMR]          = 0x0000,
 300         [EDTRR]         = 0x0008,
 301         [EDRRR]         = 0x0010,
 302         [TDLAR]         = 0x0018,
 303         [RDLAR]         = 0x0020,
 304         [EESR]          = 0x0028,
 305         [EESIPR]        = 0x0030,
 306         [TRSCER]        = 0x0038,
 307         [RMFCR]         = 0x0040,
 308         [TFTR]          = 0x0048,
 309         [FDR]           = 0x0050,
 310         [RMCR]          = 0x0058,
 311         [TFUCR]         = 0x0064,
 312         [RFOCR]         = 0x0068,
 313         [FCFTR]         = 0x0070,
 314         [RPADIR]        = 0x0078,
 315         [TRIMD]         = 0x007c,
 316         [RBWAR]         = 0x00c8,
 317         [RDFAR]         = 0x00cc,
 318         [TBRAR]         = 0x00d4,
 319         [TDFAR]         = 0x00d8,
 320 };
 321
 322 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
 323         SH_ETH_OFFSET_DEFAULTS,
 324
 325         [EDMR]          = 0x0000,
 326         [EDTRR]         = 0x0004,
 327         [EDRRR]         = 0x0008,
 328         [TDLAR]         = 0x000c,
 329         [RDLAR]         = 0x0010,
 330         [EESR]          = 0x0014,
 331         [EESIPR]        = 0x0018,
 332         [TRSCER]        = 0x001c,
 333         [RMFCR]         = 0x0020,
 334         [TFTR]          = 0x0024,
 335         [FDR]           = 0x0028,
 336         [RMCR]          = 0x002c,
 337         [EDOCR]         = 0x0030,
 338         [FCFTR]         = 0x0034,
 339         [RPADIR]        = 0x0038,
 340         [TRIMD]         = 0x003c,
 341         [RBWAR]         = 0x0040,
 342         [RDFAR]         = 0x0044,
 343         [TBRAR]         = 0x004c,
 344         [TDFAR]         = 0x0050,
 345
 346         [ECMR]          = 0x0160,
 347         [ECSR]          = 0x0164,
 348         [ECSIPR]        = 0x0168,
 349         [PIR]           = 0x016c,
 350         [MAHR]          = 0x0170,
 351         [MALR]          = 0x0174,
 352         [RFLR]          = 0x0178,
 353         [PSR]           = 0x017c,
 354         [TROCR]         = 0x0180,
 355         [CDCR]          = 0x0184,
 356         [LCCR]          = 0x0188,
 357         [CNDCR]         = 0x018c,
 358         [CEFCR]         = 0x0194,
 359         [FRECR]         = 0x0198,
 360         [TSFRCR]        = 0x019c,
 361         [TLFRCR]        = 0x01a0,
 362         [RFCR]          = 0x01a4,
 363         [MAFCR]         = 0x01a8,
 364         [IPGR]          = 0x01b4,
 365         [APR]           = 0x01b8,
 366         [MPR]           = 0x01bc,
 367         [TPAUSER]       = 0x01c4,
 368         [BCFR]          = 0x01cc,
 369
 370         [ARSTR]         = 0x0000,
 371         [TSU_CTRST]     = 0x0004,
 372         [TSU_FWEN0]     = 0x0010,
 373         [TSU_FWEN1]     = 0x0014,
 374         [TSU_FCM]       = 0x0018,
 375         [TSU_BSYSL0]    = 0x0020,
 376         [TSU_BSYSL1]    = 0x0024,
 377         [TSU_PRISL0]    = 0x0028,
 378         [TSU_PRISL1]    = 0x002c,
 379         [TSU_FWSL0]     = 0x0030,
 380         [TSU_FWSL1]     = 0x0034,
 381         [TSU_FWSLC]     = 0x0038,
 382         [TSU_QTAGM0]    = 0x0040,
 383         [TSU_QTAGM1]    = 0x0044,
 384         [TSU_ADQT0]     = 0x0048,
 385         [TSU_ADQT1]     = 0x004c,
 386         [TSU_FWSR]      = 0x0050,
 387         [TSU_FWINMK]    = 0x0054,
 388         [TSU_ADSBSY]    = 0x0060,
 389         [TSU_TEN]       = 0x0064,
 390         [TSU_POST1]     = 0x0070,
 391         [TSU_POST2]     = 0x0074,
 392         [TSU_POST3]     = 0x0078,
 393         [TSU_POST4]     = 0x007c,
 394
 395         [TXNLCR0]       = 0x0080,
 396         [TXALCR0]       = 0x0084,
 397         [RXNLCR0]       = 0x0088,
 398         [RXALCR0]       = 0x008c,
 399         [FWNLCR0]       = 0x0090,
 400         [FWALCR0]       = 0x0094,
 401         [TXNLCR1]       = 0x00a0,
 402         [TXALCR1]       = 0x00a0,
 403         [RXNLCR1]       = 0x00a8,
 404         [RXALCR1]       = 0x00ac,
 405         [FWNLCR1]       = 0x00b0,
 406         [FWALCR1]       = 0x00b4,
 407
 408         [TSU_ADRH0]     = 0x0100,
 409 };
 410
 411 static void sh_eth_rcv_snd_disable(struct net_device *ndev);
 412 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
 413
 414 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
 415 {
 416         struct sh_eth_private *mdp = netdev_priv(ndev);
 417         u16 offset = mdp->reg_offset[enum_index];
 418
 419         if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
 420                 return;
 421
 422         iowrite32(data, mdp->addr + offset);
 423 }
 424
 425 static u32 sh_eth_read(struct net_device *ndev, int enum_index)
 426 {
 427         struct sh_eth_private *mdp = netdev_priv(ndev);
 428         u16 offset = mdp->reg_offset[enum_index];
 429
 430         if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
 431                 return ~0U;
 432
 433         return ioread32(mdp->addr + offset);
 434 }
 435
 436 static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
 437                           u32 set)
 438 {
 439         sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set,
 440                      enum_index);
 441 }
 442
 443 static bool sh_eth_is_gether(struct sh_eth_private *mdp)
 444 {
 445         return mdp->reg_offset == sh_eth_offset_gigabit;
 446 }
 447
 448 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
 449 {
 450         return mdp->reg_offset == sh_eth_offset_fast_rz;
 451 }
 452
 453 static void sh_eth_select_mii(struct net_device *ndev)
 454 {
 455         struct sh_eth_private *mdp = netdev_priv(ndev);
 456         u32 value;
 457
 458         switch (mdp->phy_interface) {
 459         case PHY_INTERFACE_MODE_GMII:
 460                 value = 0x2;
 461                 break;
 462         case PHY_INTERFACE_MODE_MII:
 463                 value = 0x1;
 464                 break;
 465         case PHY_INTERFACE_MODE_RMII:
 466                 value = 0x0;
 467                 break;
 468         default:
 469                 netdev_warn(ndev,
 470                             "PHY interface mode was not setup. Set to MII.\n");
 471                 value = 0x1;
 472                 break;
 473         }
 474
 475         sh_eth_write(ndev, value, RMII_MII);
 476 }
 477
 478 static void sh_eth_set_duplex(struct net_device *ndev)
 479 {
 480         struct sh_eth_private *mdp = netdev_priv(ndev);
 481
 482         sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0);
 483 }
 484
 485 static void sh_eth_chip_reset(struct net_device *ndev)
 486 {
 487         struct sh_eth_private *mdp = netdev_priv(ndev);
 488
 489         /* reset device */
 490         sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR);
 491         mdelay(1);
 492 }
 493
 494 static void sh_eth_set_rate_gether(struct net_device *ndev)
 495 {
 496         struct sh_eth_private *mdp = netdev_priv(ndev);
 497
 498         switch (mdp->speed) {
 499         case 10: /* 10BASE */
 500                 sh_eth_write(ndev, GECMR_10, GECMR);
 501                 break;
 502         case 100:/* 100BASE */
 503                 sh_eth_write(ndev, GECMR_100, GECMR);
 504                 break;
 505         case 1000: /* 1000BASE */
 506                 sh_eth_write(ndev, GECMR_1000, GECMR);
 507                 break;
 508         }
 509 }
 510
 511 #ifdef CONFIG_OF
 512 /* R7S72100 */
 513 static struct sh_eth_cpu_data r7s72100_data = {
 514         .chip_reset     = sh_eth_chip_reset,
 515         .set_duplex     = sh_eth_set_duplex,
 516
 517         .register_type  = SH_ETH_REG_FAST_RZ,
 518
 519         .ecsr_value     = ECSR_ICD,
 520         .ecsipr_value   = ECSIPR_ICDIP,
 521         .eesipr_value   = EESIPR_TWB1IP | EESIPR_TWBIP | EESIPR_TC1IP |
 522                           EESIPR_TABTIP | EESIPR_RABTIP | EESIPR_RFCOFIP |
 523                           EESIPR_ECIIP |
 524                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 525                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 526                           EESIPR_RMAFIP | EESIPR_RRFIP |
 527                           EESIPR_RTLFIP | EESIPR_RTSFIP |
 528                           EESIPR_PREIP | EESIPR_CERFIP,
 529
 530         .tx_check       = EESR_TC1 | EESR_FTC,
 531         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 532                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 533                           EESR_TDE,
 534         .fdr_value      = 0x0000070f,
 535
 536         .no_psr         = 1,
 537         .apr            = 1,
 538         .mpr            = 1,
 539         .tpauser        = 1,
 540         .hw_swap        = 1,
 541         .rpadir         = 1,
 542         .rpadir_value   = 2 << 16,
 543         .no_trimd       = 1,
 544         .no_ade         = 1,
 545         .hw_checksum    = 1,
 546         .tsu            = 1,
 547 };
 548
 549 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
 550 {
 551         sh_eth_chip_reset(ndev);
 552
 553         sh_eth_select_mii(ndev);
 554 }
 555
 556 /* R8A7740 */
 557 static struct sh_eth_cpu_data r8a7740_data = {
 558         .chip_reset     = sh_eth_chip_reset_r8a7740,
 559         .set_duplex     = sh_eth_set_duplex,
 560         .set_rate       = sh_eth_set_rate_gether,
 561
 562         .register_type  = SH_ETH_REG_GIGABIT,
 563
 564         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 565         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 566         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
 567                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 568                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 569                           0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
 570                           EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
 571                           EESIPR_CEEFIP | EESIPR_CELFIP |
 572                           EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
 573                           EESIPR_PREIP | EESIPR_CERFIP,
 574
 575         .tx_check       = EESR_TC1 | EESR_FTC,
 576         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 577                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 578                           EESR_TDE,
 579         .fdr_value      = 0x0000070f,
 580
 581         .apr            = 1,
 582         .mpr            = 1,
 583         .tpauser        = 1,
 584         .bculr          = 1,
 585         .hw_swap        = 1,
 586         .rpadir         = 1,
 587         .rpadir_value   = 2 << 16,
 588         .no_trimd       = 1,
 589         .no_ade         = 1,
 590         .hw_checksum    = 1,
 591         .tsu            = 1,
 592         .select_mii     = 1,
 593         .magic          = 1,
 594 };
 595
 596 /* There is CPU dependent code */
 597 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
 598 {
 599         struct sh_eth_private *mdp = netdev_priv(ndev);
 600
 601         switch (mdp->speed) {
 602         case 10: /* 10BASE */
 603                 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0);
 604                 break;
 605         case 100:/* 100BASE */
 606                 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB);
 607                 break;
 608         }
 609 }
 610
 611 /* R8A7778/9 */
 612 static struct sh_eth_cpu_data r8a777x_data = {
 613         .set_duplex     = sh_eth_set_duplex,
 614         .set_rate       = sh_eth_set_rate_r8a777x,
 615
 616         .register_type  = SH_ETH_REG_FAST_RCAR,
 617
 618         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 619         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 620         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
 621                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 622                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 623                           EESIPR_RMAFIP | EESIPR_RRFIP |
 624                           EESIPR_RTLFIP | EESIPR_RTSFIP |
 625                           EESIPR_PREIP | EESIPR_CERFIP,
 626
 627         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 628         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 629                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
 630         .fdr_value      = 0x00000f0f,
 631
 632         .apr            = 1,
 633         .mpr            = 1,
 634         .tpauser        = 1,
 635         .hw_swap        = 1,
 636 };
 637
 638 /* R8A7790/1 */
 639 static struct sh_eth_cpu_data r8a779x_data = {
 640         .set_duplex     = sh_eth_set_duplex,
 641         .set_rate       = sh_eth_set_rate_r8a777x,
 642
 643         .register_type  = SH_ETH_REG_FAST_RCAR,
 644
 645         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
 646         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
 647                           ECSIPR_MPDIP,
 648         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
 649                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 650                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 651                           EESIPR_RMAFIP | EESIPR_RRFIP |
 652                           EESIPR_RTLFIP | EESIPR_RTSFIP |
 653                           EESIPR_PREIP | EESIPR_CERFIP,
 654
 655         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 656         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 657                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
 658         .fdr_value      = 0x00000f0f,
 659
 660         .trscer_err_mask = DESC_I_RINT8,
 661
 662         .apr            = 1,
 663         .mpr            = 1,
 664         .tpauser        = 1,
 665         .hw_swap        = 1,
 666         .rmiimode       = 1,
 667         .magic          = 1,
 668 };
 669 #endif /* CONFIG_OF */
 670
 671 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
 672 {
 673         struct sh_eth_private *mdp = netdev_priv(ndev);
 674
 675         switch (mdp->speed) {
 676         case 10: /* 10BASE */
 677                 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0);
 678                 break;
 679         case 100:/* 100BASE */
 680                 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM);
 681                 break;
 682         }
 683 }
 684
 685 /* SH7724 */
 686 static struct sh_eth_cpu_data sh7724_data = {
 687         .set_duplex     = sh_eth_set_duplex,
 688         .set_rate       = sh_eth_set_rate_sh7724,
 689
 690         .register_type  = SH_ETH_REG_FAST_SH4,
 691
 692         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 693         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 694         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
 695                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 696                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 697                           EESIPR_RMAFIP | EESIPR_RRFIP |
 698                           EESIPR_RTLFIP | EESIPR_RTSFIP |
 699                           EESIPR_PREIP | EESIPR_CERFIP,
 700
 701         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 702         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 703                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
 704
 705         .apr            = 1,
 706         .mpr            = 1,
 707         .tpauser        = 1,
 708         .hw_swap        = 1,
 709         .rpadir         = 1,
 710         .rpadir_value   = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
 711 };
 712
 713 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
 714 {
 715         struct sh_eth_private *mdp = netdev_priv(ndev);
 716
 717         switch (mdp->speed) {
 718         case 10: /* 10BASE */
 719                 sh_eth_write(ndev, 0, RTRATE);
 720                 break;
 721         case 100:/* 100BASE */
 722                 sh_eth_write(ndev, 1, RTRATE);
 723                 break;
 724         }
 725 }
 726
 727 /* SH7757 */
 728 static struct sh_eth_cpu_data sh7757_data = {
 729         .set_duplex     = sh_eth_set_duplex,
 730         .set_rate       = sh_eth_set_rate_sh7757,
 731
 732         .register_type  = SH_ETH_REG_FAST_SH4,
 733
 734         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
 735                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 736                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 737                           0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
 738                           EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
 739                           EESIPR_CEEFIP | EESIPR_CELFIP |
 740                           EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
 741                           EESIPR_PREIP | EESIPR_CERFIP,
 742
 743         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 744         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 745                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
 746
 747         .irq_flags      = IRQF_SHARED,
 748         .apr            = 1,
 749         .mpr            = 1,
 750         .tpauser        = 1,
 751         .hw_swap        = 1,
 752         .no_ade         = 1,
 753         .rpadir         = 1,
 754         .rpadir_value   = 2 << 16,
 755         .rtrate         = 1,
 756 };
 757
 758 #define SH_GIGA_ETH_BASE        0xfee00000UL
 759 #define GIGA_MALR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
 760 #define GIGA_MAHR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
 761 static void sh_eth_chip_reset_giga(struct net_device *ndev)
 762 {
 763         u32 mahr[2], malr[2];
 764         int i;
 765
 766         /* save MAHR and MALR */
 767         for (i = 0; i < 2; i++) {
 768                 malr[i] = ioread32((void *)GIGA_MALR(i));
 769                 mahr[i] = ioread32((void *)GIGA_MAHR(i));
 770         }
 771
 772         sh_eth_chip_reset(ndev);
 773
 774         /* restore MAHR and MALR */
 775         for (i = 0; i < 2; i++) {
 776                 iowrite32(malr[i], (void *)GIGA_MALR(i));
 777                 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
 778         }
 779 }
 780
 781 static void sh_eth_set_rate_giga(struct net_device *ndev)
 782 {
 783         struct sh_eth_private *mdp = netdev_priv(ndev);
 784
 785         switch (mdp->speed) {
 786         case 10: /* 10BASE */
 787                 sh_eth_write(ndev, 0x00000000, GECMR);
 788                 break;
 789         case 100:/* 100BASE */
 790                 sh_eth_write(ndev, 0x00000010, GECMR);
 791                 break;
 792         case 1000: /* 1000BASE */
 793                 sh_eth_write(ndev, 0x00000020, GECMR);
 794                 break;
 795         }
 796 }
 797
 798 /* SH7757(GETHERC) */
 799 static struct sh_eth_cpu_data sh7757_data_giga = {
 800         .chip_reset     = sh_eth_chip_reset_giga,
 801         .set_duplex     = sh_eth_set_duplex,
 802         .set_rate       = sh_eth_set_rate_giga,
 803
 804         .register_type  = SH_ETH_REG_GIGABIT,
 805
 806         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 807         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 808         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
 809                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 810                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 811                           0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
 812                           EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
 813                           EESIPR_CEEFIP | EESIPR_CELFIP |
 814                           EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
 815                           EESIPR_PREIP | EESIPR_CERFIP,
 816
 817         .tx_check       = EESR_TC1 | EESR_FTC,
 818         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 819                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 820                           EESR_TDE,
 821         .fdr_value      = 0x0000072f,
 822
 823         .irq_flags      = IRQF_SHARED,
 824         .apr            = 1,
 825         .mpr            = 1,
 826         .tpauser        = 1,
 827         .bculr          = 1,
 828         .hw_swap        = 1,
 829         .rpadir         = 1,
 830         .rpadir_value   = 2 << 16,
 831         .no_trimd       = 1,
 832         .no_ade         = 1,
 833         .tsu            = 1,
 834 };
 835
 836 /* SH7734 */
 837 static struct sh_eth_cpu_data sh7734_data = {
 838         .chip_reset     = sh_eth_chip_reset,
 839         .set_duplex     = sh_eth_set_duplex,
 840         .set_rate       = sh_eth_set_rate_gether,
 841
 842         .register_type  = SH_ETH_REG_GIGABIT,
 843
 844         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 845         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 846         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
 847                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 848                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 849                           EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
 850                           EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
 851                           EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
 852                           EESIPR_PREIP | EESIPR_CERFIP,
 853
 854         .tx_check       = EESR_TC1 | EESR_FTC,
 855         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 856                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 857                           EESR_TDE,
 858
 859         .apr            = 1,
 860         .mpr            = 1,
 861         .tpauser        = 1,
 862         .bculr          = 1,
 863         .hw_swap        = 1,
 864         .no_trimd       = 1,
 865         .no_ade         = 1,
 866         .tsu            = 1,
 867         .hw_checksum    = 1,
 868         .select_mii     = 1,
 869         .magic          = 1,
 870 };
 871
 872 /* SH7763 */
 873 static struct sh_eth_cpu_data sh7763_data = {
 874         .chip_reset     = sh_eth_chip_reset,
 875         .set_duplex     = sh_eth_set_duplex,
 876         .set_rate       = sh_eth_set_rate_gether,
 877
 878         .register_type  = SH_ETH_REG_GIGABIT,
 879
 880         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 881         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 882         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
 883                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 884                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 885                           EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
 886                           EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
 887                           EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
 888                           EESIPR_PREIP | EESIPR_CERFIP,
 889
 890         .tx_check       = EESR_TC1 | EESR_FTC,
 891         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 892                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
 893
 894         .apr            = 1,
 895         .mpr            = 1,
 896         .tpauser        = 1,
 897         .bculr          = 1,
 898         .hw_swap        = 1,
 899         .no_trimd       = 1,
 900         .no_ade         = 1,
 901         .tsu            = 1,
 902         .irq_flags      = IRQF_SHARED,
 903         .magic          = 1,
 904 };
 905
 906 static struct sh_eth_cpu_data sh7619_data = {
 907         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
 908
 909         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
 910                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 911                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 912                           0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
 913                           EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
 914                           EESIPR_CEEFIP | EESIPR_CELFIP |
 915                           EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
 916                           EESIPR_PREIP | EESIPR_CERFIP,
 917
 918         .apr            = 1,
 919         .mpr            = 1,
 920         .tpauser        = 1,
 921         .hw_swap        = 1,
 922 };
 923
 924 static struct sh_eth_cpu_data sh771x_data = {
 925         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
 926
 927         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
 928                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 929                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 930                           0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
 931                           EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
 932                           EESIPR_CEEFIP | EESIPR_CELFIP |
 933                           EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
 934                           EESIPR_PREIP | EESIPR_CERFIP,
 935         .tsu            = 1,
 936 };
 937
 938 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
 939 {
 940         if (!cd->ecsr_value)
 941                 cd->ecsr_value = DEFAULT_ECSR_INIT;
 942
 943         if (!cd->ecsipr_value)
 944                 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
 945
 946         if (!cd->fcftr_value)
 947                 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
 948                                   DEFAULT_FIFO_F_D_RFD;
 949
 950         if (!cd->fdr_value)
 951                 cd->fdr_value = DEFAULT_FDR_INIT;
 952
 953         if (!cd->tx_check)
 954                 cd->tx_check = DEFAULT_TX_CHECK;
 955
 956         if (!cd->eesr_err_check)
 957                 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
 958
 959         if (!cd->trscer_err_mask)
 960                 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
 961 }
 962
 963 static int sh_eth_check_reset(struct net_device *ndev)
 964 {
 965         int ret = 0;
 966         int cnt = 100;
 967
 968         while (cnt > 0) {
 969                 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER))
 970                         break;
 971                 mdelay(1);
 972                 cnt--;
 973         }
 974         if (cnt <= 0) {
 975                 netdev_err(ndev, "Device reset failed\n");
 976                 ret = -ETIMEDOUT;
 977         }
 978         return ret;
 979 }
 980
 981 static int sh_eth_reset(struct net_device *ndev)
 982 {
 983         struct sh_eth_private *mdp = netdev_priv(ndev);
 984         int ret = 0;
 985
 986         if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
 987                 sh_eth_write(ndev, EDSR_ENALL, EDSR);
 988                 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
 989
 990                 ret = sh_eth_check_reset(ndev);
 991                 if (ret)
 992                         return ret;
 993
 994                 /* Table Init */
 995                 sh_eth_write(ndev, 0x0, TDLAR);
 996                 sh_eth_write(ndev, 0x0, TDFAR);
 997                 sh_eth_write(ndev, 0x0, TDFXR);
 998                 sh_eth_write(ndev, 0x0, TDFFR);
 999                 sh_eth_write(ndev, 0x0, RDLAR);
1000                 sh_eth_write(ndev, 0x0, RDFAR);
1001                 sh_eth_write(ndev, 0x0, RDFXR);
1002                 sh_eth_write(ndev, 0x0, RDFFR);
1003
1004                 /* Reset HW CRC register */
1005                 if (mdp->cd->hw_checksum)
1006                         sh_eth_write(ndev, 0x0, CSMR);
1007
1008                 /* Select MII mode */
1009                 if (mdp->cd->select_mii)
1010                         sh_eth_select_mii(ndev);
1011         } else {
1012                 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
1013                 mdelay(3);
1014                 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
1015         }
1016
1017         return ret;
1018 }
1019
1020 static void sh_eth_set_receive_align(struct sk_buff *skb)
1021 {
1022         uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
1023
1024         if (reserve)
1025                 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
1026 }
1027
1028 /* Program the hardware MAC address from dev->dev_addr. */
1029 static void update_mac_address(struct net_device *ndev)
1030 {
1031         sh_eth_write(ndev,
1032                      (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
1033                      (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
1034         sh_eth_write(ndev,
1035                      (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
1036 }
1037
1038 /* Get MAC address from SuperH MAC address register
1039  *
1040  * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
1041  * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
1042  * When you want use this device, you must set MAC address in bootloader.
1043  *
1044  */
1045 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
1046 {
1047         if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
1048                 memcpy(ndev->dev_addr, mac, ETH_ALEN);
1049         } else {
1050                 u32 mahr = sh_eth_read(ndev, MAHR);
1051                 u32 malr = sh_eth_read(ndev, MALR);
1052
1053                 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
1054                 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
1055                 ndev->dev_addr[2] = (mahr >>  8) & 0xFF;
1056                 ndev->dev_addr[3] = (mahr >>  0) & 0xFF;
1057                 ndev->dev_addr[4] = (malr >>  8) & 0xFF;
1058                 ndev->dev_addr[5] = (malr >>  0) & 0xFF;
1059         }
1060 }
1061
1062 static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
1063 {
1064         if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
1065                 return EDTRR_TRNS_GETHER;
1066         else
1067                 return EDTRR_TRNS_ETHER;
1068 }
1069
1070 struct bb_info {
1071         void (*set_gate)(void *addr);
1072         struct mdiobb_ctrl ctrl;
1073         void *addr;
1074 };
1075
1076 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
1077 {
1078         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1079         u32 pir;
1080
1081         if (bitbang->set_gate)
1082                 bitbang->set_gate(bitbang->addr);
1083
1084         pir = ioread32(bitbang->addr);
1085         if (set)
1086                 pir |=  mask;
1087         else
1088                 pir &= ~mask;
1089         iowrite32(pir, bitbang->addr);
1090 }
1091
1092 /* Data I/O pin control */
1093 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1094 {
1095         sh_mdio_ctrl(ctrl, PIR_MMD, bit);
1096 }
1097
1098 /* Set bit data*/
1099 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1100 {
1101         sh_mdio_ctrl(ctrl, PIR_MDO, bit);
1102 }
1103
1104 /* Get bit data*/
1105 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1106 {
1107         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1108
1109         if (bitbang->set_gate)
1110                 bitbang->set_gate(bitbang->addr);
1111
1112         return (ioread32(bitbang->addr) & PIR_MDI) != 0;
1113 }
1114
1115 /* MDC pin control */
1116 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1117 {
1118         sh_mdio_ctrl(ctrl, PIR_MDC, bit);
1119 }
1120
1121 /* mdio bus control struct */
1122 static struct mdiobb_ops bb_ops = {
1123         .owner = THIS_MODULE,
1124         .set_mdc = sh_mdc_ctrl,
1125         .set_mdio_dir = sh_mmd_ctrl,
1126         .set_mdio_data = sh_set_mdio,
1127         .get_mdio_data = sh_get_mdio,
1128 };
1129
1130 /* free Tx skb function */
1131 static int sh_eth_tx_free(struct net_device *ndev, bool sent_only)
1132 {
1133         struct sh_eth_private *mdp = netdev_priv(ndev);
1134         struct sh_eth_txdesc *txdesc;
1135         int free_num = 0;
1136         int entry;
1137         bool sent;
1138
1139         for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1140                 entry = mdp->dirty_tx % mdp->num_tx_ring;
1141                 txdesc = &mdp->tx_ring[entry];
1142                 sent = !(txdesc->status & cpu_to_le32(TD_TACT));
1143                 if (sent_only && !sent)
1144                         break;
1145                 /* TACT bit must be checked before all the following reads */
1146                 dma_rmb();
1147                 netif_info(mdp, tx_done, ndev,
1148                            "tx entry %d status 0x%08x\n",
1149                            entry, le32_to_cpu(txdesc->status));
1150                 /* Free the original skb. */
1151                 if (mdp->tx_skbuff[entry]) {
1152                         dma_unmap_single(&ndev->dev, le32_to_cpu(txdesc->addr),
1153                                          le32_to_cpu(txdesc->len) >> 16,
1154                                          DMA_TO_DEVICE);
1155                         dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1156                         mdp->tx_skbuff[entry] = NULL;
1157                         free_num++;
1158                 }
1159                 txdesc->status = cpu_to_le32(TD_TFP);
1160                 if (entry >= mdp->num_tx_ring - 1)
1161                         txdesc->status |= cpu_to_le32(TD_TDLE);
1162
1163                 if (sent) {
1164                         ndev->stats.tx_packets++;
1165                         ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
1166                 }
1167         }
1168         return free_num;
1169 }
1170
1171 /* free skb and descriptor buffer */
1172 static void sh_eth_ring_free(struct net_device *ndev)
1173 {
1174         struct sh_eth_private *mdp = netdev_priv(ndev);
1175         int ringsize, i;
1176
1177         if (mdp->rx_ring) {
1178                 for (i = 0; i < mdp->num_rx_ring; i++) {
1179                         if (mdp->rx_skbuff[i]) {
1180                                 struct sh_eth_rxdesc *rxdesc = &mdp->rx_ring[i];
1181
1182                                 dma_unmap_single(&ndev->dev,
1183                                                  le32_to_cpu(rxdesc->addr),
1184                                                  ALIGN(mdp->rx_buf_sz, 32),
1185                                                  DMA_FROM_DEVICE);
1186                         }
1187                 }
1188                 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1189                 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1190                                   mdp->rx_desc_dma);
1191                 mdp->rx_ring = NULL;
1192         }
1193
1194         /* Free Rx skb ringbuffer */
1195         if (mdp->rx_skbuff) {
1196                 for (i = 0; i < mdp->num_rx_ring; i++)
1197                         dev_kfree_skb(mdp->rx_skbuff[i]);
1198         }
1199         kfree(mdp->rx_skbuff);
1200         mdp->rx_skbuff = NULL;
1201
1202         if (mdp->tx_ring) {
1203                 sh_eth_tx_free(ndev, false);
1204
1205                 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1206                 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1207                                   mdp->tx_desc_dma);
1208                 mdp->tx_ring = NULL;
1209         }
1210
1211         /* Free Tx skb ringbuffer */
1212         kfree(mdp->tx_skbuff);
1213         mdp->tx_skbuff = NULL;
1214 }
1215
1216 /* format skb and descriptor buffer */
1217 static void sh_eth_ring_format(struct net_device *ndev)
1218 {
1219         struct sh_eth_private *mdp = netdev_priv(ndev);
1220         int i;
1221         struct sk_buff *skb;
1222         struct sh_eth_rxdesc *rxdesc = NULL;
1223         struct sh_eth_txdesc *txdesc = NULL;
1224         int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1225         int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1226         int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1227         dma_addr_t dma_addr;
1228         u32 buf_len;
1229
1230         mdp->cur_rx = 0;
1231         mdp->cur_tx = 0;
1232         mdp->dirty_rx = 0;
1233         mdp->dirty_tx = 0;
1234
1235         memset(mdp->rx_ring, 0, rx_ringsize);
1236
1237         /* build Rx ring buffer */
1238         for (i = 0; i < mdp->num_rx_ring; i++) {
1239                 /* skb */
1240                 mdp->rx_skbuff[i] = NULL;
1241                 skb = netdev_alloc_skb(ndev, skbuff_size);
1242                 if (skb == NULL)
1243                         break;
1244                 sh_eth_set_receive_align(skb);
1245
1246                 /* The size of the buffer is a multiple of 32 bytes. */
1247                 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1248                 dma_addr = dma_map_single(&ndev->dev, skb->data, buf_len,
1249                                           DMA_FROM_DEVICE);
1250                 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1251                         kfree_skb(skb);
1252                         break;
1253                 }
1254                 mdp->rx_skbuff[i] = skb;
1255
1256                 /* RX descriptor */
1257                 rxdesc = &mdp->rx_ring[i];
1258                 rxdesc->len = cpu_to_le32(buf_len << 16);
1259                 rxdesc->addr = cpu_to_le32(dma_addr);
1260                 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
1261
1262                 /* Rx descriptor address set */
1263                 if (i == 0) {
1264                         sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1265                         if (sh_eth_is_gether(mdp) ||
1266                             sh_eth_is_rz_fast_ether(mdp))
1267                                 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1268                 }
1269         }
1270
1271         mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1272
1273         /* Mark the last entry as wrapping the ring. */
1274         if (rxdesc)
1275                 rxdesc->status |= cpu_to_le32(RD_RDLE);
1276
1277         memset(mdp->tx_ring, 0, tx_ringsize);
1278
1279         /* build Tx ring buffer */
1280         for (i = 0; i < mdp->num_tx_ring; i++) {
1281                 mdp->tx_skbuff[i] = NULL;
1282                 txdesc = &mdp->tx_ring[i];
1283                 txdesc->status = cpu_to_le32(TD_TFP);
1284                 txdesc->len = cpu_to_le32(0);
1285                 if (i == 0) {
1286                         /* Tx descriptor address set */
1287                         sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1288                         if (sh_eth_is_gether(mdp) ||
1289                             sh_eth_is_rz_fast_ether(mdp))
1290                                 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1291                 }
1292         }
1293
1294         txdesc->status |= cpu_to_le32(TD_TDLE);
1295 }
1296
1297 /* Get skb and descriptor buffer */
1298 static int sh_eth_ring_init(struct net_device *ndev)
1299 {
1300         struct sh_eth_private *mdp = netdev_priv(ndev);
1301         int rx_ringsize, tx_ringsize;
1302
1303         /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1304          * card needs room to do 8 byte alignment, +2 so we can reserve
1305          * the first 2 bytes, and +16 gets room for the status word from the
1306          * card.
1307          */
1308         mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1309                           (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1310         if (mdp->cd->rpadir)
1311                 mdp->rx_buf_sz += NET_IP_ALIGN;
1312
1313         /* Allocate RX and TX skb rings */
1314         mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1315                                  GFP_KERNEL);
1316         if (!mdp->rx_skbuff)
1317                 return -ENOMEM;
1318
1319         mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1320                                  GFP_KERNEL);
1321         if (!mdp->tx_skbuff)
1322                 goto ring_free;
1323
1324         /* Allocate all Rx descriptors. */
1325         rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1326         mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1327                                           GFP_KERNEL);
1328         if (!mdp->rx_ring)
1329                 goto ring_free;
1330
1331         mdp->dirty_rx = 0;
1332
1333         /* Allocate all Tx descriptors. */
1334         tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1335         mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1336                                           GFP_KERNEL);
1337         if (!mdp->tx_ring)
1338                 goto ring_free;
1339         return 0;
1340
1341 ring_free:
1342         /* Free Rx and Tx skb ring buffer and DMA buffer */
1343         sh_eth_ring_free(ndev);
1344
1345         return -ENOMEM;
1346 }
1347
1348 static int sh_eth_dev_init(struct net_device *ndev)
1349 {
1350         struct sh_eth_private *mdp = netdev_priv(ndev);
1351         int ret;
1352
1353         /* Soft Reset */
1354         ret = sh_eth_reset(ndev);
1355         if (ret)
1356                 return ret;
1357
1358         if (mdp->cd->rmiimode)
1359                 sh_eth_write(ndev, 0x1, RMIIMODE);
1360
1361         /* Descriptor format */
1362         sh_eth_ring_format(ndev);
1363         if (mdp->cd->rpadir)
1364                 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1365
1366         /* all sh_eth int mask */
1367         sh_eth_write(ndev, 0, EESIPR);
1368
1369 #if defined(__LITTLE_ENDIAN)
1370         if (mdp->cd->hw_swap)
1371                 sh_eth_write(ndev, EDMR_EL, EDMR);
1372         else
1373 #endif
1374                 sh_eth_write(ndev, 0, EDMR);
1375
1376         /* FIFO size set */
1377         sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1378         sh_eth_write(ndev, 0, TFTR);
1379
1380         /* Frame recv control (enable multiple-packets per rx irq) */
1381         sh_eth_write(ndev, RMCR_RNC, RMCR);
1382
1383         sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1384
1385         if (mdp->cd->bculr)
1386                 sh_eth_write(ndev, 0x800, BCULR);       /* Burst sycle set */
1387
1388         sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1389
1390         if (!mdp->cd->no_trimd)
1391                 sh_eth_write(ndev, 0, TRIMD);
1392
1393         /* Recv frame limit set register */
1394         sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1395                      RFLR);
1396
1397         sh_eth_modify(ndev, EESR, 0, 0);
1398         mdp->irq_enabled = true;
1399         sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1400
1401         /* PAUSE Prohibition */
1402         sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |
1403                      ECMR_TE | ECMR_RE, ECMR);
1404
1405         if (mdp->cd->set_rate)
1406                 mdp->cd->set_rate(ndev);
1407
1408         /* E-MAC Status Register clear */
1409         sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1410
1411         /* E-MAC Interrupt Enable register */
1412         sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1413
1414         /* Set MAC address */
1415         update_mac_address(ndev);
1416
1417         /* mask reset */
1418         if (mdp->cd->apr)
1419                 sh_eth_write(ndev, APR_AP, APR);
1420         if (mdp->cd->mpr)
1421                 sh_eth_write(ndev, MPR_MP, MPR);
1422         if (mdp->cd->tpauser)
1423                 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1424
1425         /* Setting the Rx mode will start the Rx process. */
1426         sh_eth_write(ndev, EDRRR_R, EDRRR);
1427
1428         return ret;
1429 }
1430
1431 static void sh_eth_dev_exit(struct net_device *ndev)
1432 {
1433         struct sh_eth_private *mdp = netdev_priv(ndev);
1434         int i;
1435
1436         /* Deactivate all TX descriptors, so DMA should stop at next
1437          * packet boundary if it's currently running
1438          */
1439         for (i = 0; i < mdp->num_tx_ring; i++)
1440                 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT);
1441
1442         /* Disable TX FIFO egress to MAC */
1443         sh_eth_rcv_snd_disable(ndev);
1444
1445         /* Stop RX DMA at next packet boundary */
1446         sh_eth_write(ndev, 0, EDRRR);
1447
1448         /* Aside from TX DMA, we can't tell when the hardware is
1449          * really stopped, so we need to reset to make sure.
1450          * Before doing that, wait for long enough to *probably*
1451          * finish transmitting the last packet and poll stats.
1452          */
1453         msleep(2); /* max frame time at 10 Mbps < 1250 us */
1454         sh_eth_get_stats(ndev);
1455         sh_eth_reset(ndev);
1456
1457         /* Set MAC address again */
1458         update_mac_address(ndev);
1459 }
1460
1461 /* Packet receive function */
1462 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1463 {
1464         struct sh_eth_private *mdp = netdev_priv(ndev);
1465         struct sh_eth_rxdesc *rxdesc;
1466
1467         int entry = mdp->cur_rx % mdp->num_rx_ring;
1468         int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1469         int limit;
1470         struct sk_buff *skb;
1471         u32 desc_status;
1472         int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1473         dma_addr_t dma_addr;
1474         u16 pkt_len;
1475         u32 buf_len;
1476
1477         boguscnt = min(boguscnt, *quota);
1478         limit = boguscnt;
1479         rxdesc = &mdp->rx_ring[entry];
1480         while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
1481                 /* RACT bit must be checked before all the following reads */
1482                 dma_rmb();
1483                 desc_status = le32_to_cpu(rxdesc->status);
1484                 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL;
1485
1486                 if (--boguscnt < 0)
1487                         break;
1488
1489                 netif_info(mdp, rx_status, ndev,
1490                            "rx entry %d status 0x%08x len %d\n",
1491                            entry, desc_status, pkt_len);
1492
1493                 if (!(desc_status & RDFEND))
1494                         ndev->stats.rx_length_errors++;
1495
1496                 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1497                  * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1498                  * bit 0. However, in case of the R8A7740 and R7S72100
1499                  * the RFS bits are from bit 25 to bit 16. So, the
1500                  * driver needs right shifting by 16.
1501                  */
1502                 if (mdp->cd->hw_checksum)
1503                         desc_status >>= 16;
1504
1505                 skb = mdp->rx_skbuff[entry];
1506                 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1507                                    RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1508                         ndev->stats.rx_errors++;
1509                         if (desc_status & RD_RFS1)
1510                                 ndev->stats.rx_crc_errors++;
1511                         if (desc_status & RD_RFS2)
1512                                 ndev->stats.rx_frame_errors++;
1513                         if (desc_status & RD_RFS3)
1514                                 ndev->stats.rx_length_errors++;
1515                         if (desc_status & RD_RFS4)
1516                                 ndev->stats.rx_length_errors++;
1517                         if (desc_status & RD_RFS6)
1518                                 ndev->stats.rx_missed_errors++;
1519                         if (desc_status & RD_RFS10)
1520                                 ndev->stats.rx_over_errors++;
1521                 } else  if (skb) {
1522                         dma_addr = le32_to_cpu(rxdesc->addr);
1523                         if (!mdp->cd->hw_swap)
1524                                 sh_eth_soft_swap(
1525                                         phys_to_virt(ALIGN(dma_addr, 4)),
1526                                         pkt_len + 2);
1527                         mdp->rx_skbuff[entry] = NULL;
1528                         if (mdp->cd->rpadir)
1529                                 skb_reserve(skb, NET_IP_ALIGN);
1530                         dma_unmap_single(&ndev->dev, dma_addr,
1531                                          ALIGN(mdp->rx_buf_sz, 32),
1532                                          DMA_FROM_DEVICE);
1533                         skb_put(skb, pkt_len);
1534                         skb->protocol = eth_type_trans(skb, ndev);
1535                         netif_receive_skb(skb);
1536                         ndev->stats.rx_packets++;
1537                         ndev->stats.rx_bytes += pkt_len;
1538                         if (desc_status & RD_RFS8)
1539                                 ndev->stats.multicast++;
1540                 }
1541                 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1542                 rxdesc = &mdp->rx_ring[entry];
1543         }
1544
1545         /* Refill the Rx ring buffers. */
1546         for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1547                 entry = mdp->dirty_rx % mdp->num_rx_ring;
1548                 rxdesc = &mdp->rx_ring[entry];
1549                 /* The size of the buffer is 32 byte boundary. */
1550                 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1551                 rxdesc->len = cpu_to_le32(buf_len << 16);
1552
1553                 if (mdp->rx_skbuff[entry] == NULL) {
1554                         skb = netdev_alloc_skb(ndev, skbuff_size);
1555                         if (skb == NULL)
1556                                 break;  /* Better luck next round. */
1557                         sh_eth_set_receive_align(skb);
1558                         dma_addr = dma_map_single(&ndev->dev, skb->data,
1559                                                   buf_len, DMA_FROM_DEVICE);
1560                         if (dma_mapping_error(&ndev->dev, dma_addr)) {
1561                                 kfree_skb(skb);
1562                                 break;
1563                         }
1564                         mdp->rx_skbuff[entry] = skb;
1565
1566                         skb_checksum_none_assert(skb);
1567                         rxdesc->addr = cpu_to_le32(dma_addr);
1568                 }
1569                 dma_wmb(); /* RACT bit must be set after all the above writes */
1570                 if (entry >= mdp->num_rx_ring - 1)
1571                         rxdesc->status |=
1572                                 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE);
1573                 else
1574                         rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP);
1575         }
1576
1577         /* Restart Rx engine if stopped. */
1578         /* If we don't need to check status, don't. -KDU */
1579         if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1580                 /* fix the values for the next receiving if RDE is set */
1581                 if (intr_status & EESR_RDE &&
1582                     mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) {
1583                         u32 count = (sh_eth_read(ndev, RDFAR) -
1584                                      sh_eth_read(ndev, RDLAR)) >> 4;
1585
1586                         mdp->cur_rx = count;
1587                         mdp->dirty_rx = count;
1588                 }
1589                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1590         }
1591
1592         *quota -= limit - boguscnt - 1;
1593
1594         return *quota <= 0;
1595 }
1596
1597 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1598 {
1599         /* disable tx and rx */
1600         sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
1601 }
1602
1603 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1604 {
1605         /* enable tx and rx */
1606         sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
1607 }
1608
1609 /* E-MAC interrupt handler */
1610 static void sh_eth_emac_interrupt(struct net_device *ndev)
1611 {
1612         struct sh_eth_private *mdp = netdev_priv(ndev);
1613         u32 felic_stat;
1614         u32 link_stat;
1615
1616         felic_stat = sh_eth_read(ndev, ECSR) & sh_eth_read(ndev, ECSIPR);
1617         sh_eth_write(ndev, felic_stat, ECSR);   /* clear int */
1618         if (felic_stat & ECSR_ICD)
1619                 ndev->stats.tx_carrier_errors++;
1620         if (felic_stat & ECSR_MPD)
1621                 pm_wakeup_event(&mdp->pdev->dev, 0);
1622         if (felic_stat & ECSR_LCHNG) {
1623                 /* Link Changed */
1624                 if (mdp->cd->no_psr || mdp->no_ether_link)
1625                         return;
1626                 link_stat = sh_eth_read(ndev, PSR);
1627                 if (mdp->ether_link_active_low)
1628                         link_stat = ~link_stat;
1629                 if (!(link_stat & PHY_ST_LINK)) {
1630                         sh_eth_rcv_snd_disable(ndev);
1631                 } else {
1632                         /* Link Up */
1633                         sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, 0);
1634                         /* clear int */
1635                         sh_eth_modify(ndev, ECSR, 0, 0);
1636                         sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, EESIPR_ECIIP);
1637                         /* enable tx and rx */
1638                         sh_eth_rcv_snd_enable(ndev);
1639                 }
1640         }
1641 }
1642
1643 /* error control function */
1644 static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1645 {
1646         struct sh_eth_private *mdp = netdev_priv(ndev);
1647         u32 mask;
1648
1649         if (intr_status & EESR_TWB) {
1650                 /* Unused write back interrupt */
1651                 if (intr_status & EESR_TABT) {  /* Transmit Abort int */
1652                         ndev->stats.tx_aborted_errors++;
1653                         netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1654                 }
1655         }
1656
1657         if (intr_status & EESR_RABT) {
1658                 /* Receive Abort int */
1659                 if (intr_status & EESR_RFRMER) {
1660                         /* Receive Frame Overflow int */
1661                         ndev->stats.rx_frame_errors++;
1662                 }
1663         }
1664
1665         if (intr_status & EESR_TDE) {
1666                 /* Transmit Descriptor Empty int */
1667                 ndev->stats.tx_fifo_errors++;
1668                 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1669         }
1670
1671         if (intr_status & EESR_TFE) {
1672                 /* FIFO under flow */
1673                 ndev->stats.tx_fifo_errors++;
1674                 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1675         }
1676
1677         if (intr_status & EESR_RDE) {
1678                 /* Receive Descriptor Empty int */
1679                 ndev->stats.rx_over_errors++;
1680         }
1681
1682         if (intr_status & EESR_RFE) {
1683                 /* Receive FIFO Overflow int */
1684                 ndev->stats.rx_fifo_errors++;
1685         }
1686
1687         if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1688                 /* Address Error */
1689                 ndev->stats.tx_fifo_errors++;
1690                 netif_err(mdp, tx_err, ndev, "Address Error\n");
1691         }
1692
1693         mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1694         if (mdp->cd->no_ade)
1695                 mask &= ~EESR_ADE;
1696         if (intr_status & mask) {
1697                 /* Tx error */
1698                 u32 edtrr = sh_eth_read(ndev, EDTRR);
1699
1700                 /* dmesg */
1701                 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1702                            intr_status, mdp->cur_tx, mdp->dirty_tx,
1703                            (u32)ndev->state, edtrr);
1704                 /* dirty buffer free */
1705                 sh_eth_tx_free(ndev, true);
1706
1707                 /* SH7712 BUG */
1708                 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1709                         /* tx dma start */
1710                         sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1711                 }
1712                 /* wakeup */
1713                 netif_wake_queue(ndev);
1714         }
1715 }
1716
1717 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1718 {
1719         struct net_device *ndev = netdev;
1720         struct sh_eth_private *mdp = netdev_priv(ndev);
1721         struct sh_eth_cpu_data *cd = mdp->cd;
1722         irqreturn_t ret = IRQ_NONE;
1723         u32 intr_status, intr_enable;
1724
1725         spin_lock(&mdp->lock);
1726
1727         /* Get interrupt status */
1728         intr_status = sh_eth_read(ndev, EESR);
1729         /* Mask it with the interrupt mask, forcing ECI interrupt  to be always
1730          * enabled since it's the one that  comes  thru regardless of the mask,
1731          * and  we need to fully handle it  in sh_eth_emac_interrupt() in order
1732          * to quench it as it doesn't get cleared by just writing 1 to the  ECI
1733          * bit...
1734          */
1735         intr_enable = sh_eth_read(ndev, EESIPR);
1736         intr_status &= intr_enable | EESIPR_ECIIP;
1737         if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI |
1738                            cd->eesr_err_check))
1739                 ret = IRQ_HANDLED;
1740         else
1741                 goto out;
1742
1743         if (unlikely(!mdp->irq_enabled)) {
1744                 sh_eth_write(ndev, 0, EESIPR);
1745                 goto out;
1746         }
1747
1748         if (intr_status & EESR_RX_CHECK) {
1749                 if (napi_schedule_prep(&mdp->napi)) {
1750                         /* Mask Rx interrupts */
1751                         sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1752                                      EESIPR);
1753                         __napi_schedule(&mdp->napi);
1754                 } else {
1755                         netdev_warn(ndev,
1756                                     "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1757                                     intr_status, intr_enable);
1758                 }
1759         }
1760
1761         /* Tx Check */
1762         if (intr_status & cd->tx_check) {
1763                 /* Clear Tx interrupts */
1764                 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1765
1766                 sh_eth_tx_free(ndev, true);
1767                 netif_wake_queue(ndev);
1768         }
1769
1770         /* E-MAC interrupt */
1771         if (intr_status & EESR_ECI)
1772                 sh_eth_emac_interrupt(ndev);
1773
1774         if (intr_status & cd->eesr_err_check) {
1775                 /* Clear error interrupts */
1776                 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1777
1778                 sh_eth_error(ndev, intr_status);
1779         }
1780
1781 out:
1782         spin_unlock(&mdp->lock);
1783
1784         return ret;
1785 }
1786
1787 static int sh_eth_poll(struct napi_struct *napi, int budget)
1788 {
1789         struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1790                                                   napi);
1791         struct net_device *ndev = napi->dev;
1792         int quota = budget;
1793         u32 intr_status;
1794
1795         for (;;) {
1796                 intr_status = sh_eth_read(ndev, EESR);
1797                 if (!(intr_status & EESR_RX_CHECK))
1798                         break;
1799                 /* Clear Rx interrupts */
1800                 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1801
1802                 if (sh_eth_rx(ndev, intr_status, &quota))
1803                         goto out;
1804         }
1805
1806         napi_complete(napi);
1807
1808         /* Reenable Rx interrupts */
1809         if (mdp->irq_enabled)
1810                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1811 out:
1812         return budget - quota;
1813 }
1814
1815 /* PHY state control function */
1816 static void sh_eth_adjust_link(struct net_device *ndev)
1817 {
1818         struct sh_eth_private *mdp = netdev_priv(ndev);
1819         struct phy_device *phydev = ndev->phydev;
1820         int new_state = 0;
1821
1822         if (phydev->link) {
1823                 if (phydev->duplex != mdp->duplex) {
1824                         new_state = 1;
1825                         mdp->duplex = phydev->duplex;
1826                         if (mdp->cd->set_duplex)
1827                                 mdp->cd->set_duplex(ndev);
1828                 }
1829
1830                 if (phydev->speed != mdp->speed) {
1831                         new_state = 1;
1832                         mdp->speed = phydev->speed;
1833                         if (mdp->cd->set_rate)
1834                                 mdp->cd->set_rate(ndev);
1835                 }
1836                 if (!mdp->link) {
1837                         sh_eth_modify(ndev, ECMR, ECMR_TXF, 0);
1838                         new_state = 1;
1839                         mdp->link = phydev->link;
1840                         if (mdp->cd->no_psr || mdp->no_ether_link)
1841                                 sh_eth_rcv_snd_enable(ndev);
1842                 }
1843         } else if (mdp->link) {
1844                 new_state = 1;
1845                 mdp->link = 0;
1846                 mdp->speed = 0;
1847                 mdp->duplex = -1;
1848                 if (mdp->cd->no_psr || mdp->no_ether_link)
1849                         sh_eth_rcv_snd_disable(ndev);
1850         }
1851
1852         if (new_state && netif_msg_link(mdp))
1853                 phy_print_status(phydev);
1854 }
1855
1856 /* PHY init function */
1857 static int sh_eth_phy_init(struct net_device *ndev)
1858 {
1859         struct device_node *np = ndev->dev.parent->of_node;
1860         struct sh_eth_private *mdp = netdev_priv(ndev);
1861         struct phy_device *phydev;
1862
1863         mdp->link = 0;
1864         mdp->speed = 0;
1865         mdp->duplex = -1;
1866
1867         /* Try connect to PHY */
1868         if (np) {
1869                 struct device_node *pn;
1870
1871                 pn = of_parse_phandle(np, "phy-handle", 0);
1872                 phydev = of_phy_connect(ndev, pn,
1873                                         sh_eth_adjust_link, 0,
1874                                         mdp->phy_interface);
1875
1876                 of_node_put(pn);
1877                 if (!phydev)
1878                         phydev = ERR_PTR(-ENOENT);
1879         } else {
1880                 char phy_id[MII_BUS_ID_SIZE + 3];
1881
1882                 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1883                          mdp->mii_bus->id, mdp->phy_id);
1884
1885                 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1886                                      mdp->phy_interface);
1887         }
1888
1889         if (IS_ERR(phydev)) {
1890                 netdev_err(ndev, "failed to connect PHY\n");
1891                 return PTR_ERR(phydev);
1892         }
1893
1894         phy_attached_info(phydev);
1895
1896         return 0;
1897 }
1898
1899 /* PHY control start function */
1900 static int sh_eth_phy_start(struct net_device *ndev)
1901 {
1902         int ret;
1903
1904         ret = sh_eth_phy_init(ndev);
1905         if (ret)
1906                 return ret;
1907
1908         phy_start(ndev->phydev);
1909
1910         return 0;
1911 }
1912
1913 static int sh_eth_get_link_ksettings(struct net_device *ndev,
1914                                      struct ethtool_link_ksettings *cmd)
1915 {
1916         struct sh_eth_private *mdp = netdev_priv(ndev);
1917         unsigned long flags;
1918         int ret;
1919
1920         if (!ndev->phydev)
1921                 return -ENODEV;
1922
1923         spin_lock_irqsave(&mdp->lock, flags);
1924         ret = phy_ethtool_ksettings_get(ndev->phydev, cmd);
1925         spin_unlock_irqrestore(&mdp->lock, flags);
1926
1927         return ret;
1928 }
1929
1930 static int sh_eth_set_link_ksettings(struct net_device *ndev,
1931                                      const struct ethtool_link_ksettings *cmd)
1932 {
1933         struct sh_eth_private *mdp = netdev_priv(ndev);
1934         unsigned long flags;
1935         int ret;
1936
1937         if (!ndev->phydev)
1938                 return -ENODEV;
1939
1940         spin_lock_irqsave(&mdp->lock, flags);
1941
1942         /* disable tx and rx */
1943         sh_eth_rcv_snd_disable(ndev);
1944
1945         ret = phy_ethtool_ksettings_set(ndev->phydev, cmd);
1946         if (ret)
1947                 goto error_exit;
1948
1949         if (cmd->base.duplex == DUPLEX_FULL)
1950                 mdp->duplex = 1;
1951         else
1952                 mdp->duplex = 0;
1953
1954         if (mdp->cd->set_duplex)
1955                 mdp->cd->set_duplex(ndev);
1956
1957 error_exit:
1958         mdelay(1);
1959
1960         /* enable tx and rx */
1961         sh_eth_rcv_snd_enable(ndev);
1962
1963         spin_unlock_irqrestore(&mdp->lock, flags);
1964
1965         return ret;
1966 }
1967
1968 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
1969  * version must be bumped as well.  Just adding registers up to that
1970  * limit is fine, as long as the existing register indices don't
1971  * change.
1972  */
1973 #define SH_ETH_REG_DUMP_VERSION         1
1974 #define SH_ETH_REG_DUMP_MAX_REGS        256
1975
1976 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
1977 {
1978         struct sh_eth_private *mdp = netdev_priv(ndev);
1979         struct sh_eth_cpu_data *cd = mdp->cd;
1980         u32 *valid_map;
1981         size_t len;
1982
1983         BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
1984
1985         /* Dump starts with a bitmap that tells ethtool which
1986          * registers are defined for this chip.
1987          */
1988         len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
1989         if (buf) {
1990                 valid_map = buf;
1991                 buf += len;
1992         } else {
1993                 valid_map = NULL;
1994         }
1995
1996         /* Add a register to the dump, if it has a defined offset.
1997          * This automatically skips most undefined registers, but for
1998          * some it is also necessary to check a capability flag in
1999          * struct sh_eth_cpu_data.
2000          */
2001 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
2002 #define add_reg_from(reg, read_expr) do {                               \
2003                 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) {    \
2004                         if (buf) {                                      \
2005                                 mark_reg_valid(reg);                    \
2006                                 *buf++ = read_expr;                     \
2007                         }                                               \
2008                         ++len;                                          \
2009                 }                                                       \
2010         } while (0)
2011 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
2012 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
2013
2014         add_reg(EDSR);
2015         add_reg(EDMR);
2016         add_reg(EDTRR);
2017         add_reg(EDRRR);
2018         add_reg(EESR);
2019         add_reg(EESIPR);
2020         add_reg(TDLAR);
2021         add_reg(TDFAR);
2022         add_reg(TDFXR);
2023         add_reg(TDFFR);
2024         add_reg(RDLAR);
2025         add_reg(RDFAR);
2026         add_reg(RDFXR);
2027         add_reg(RDFFR);
2028         add_reg(TRSCER);
2029         add_reg(RMFCR);
2030         add_reg(TFTR);
2031         add_reg(FDR);
2032         add_reg(RMCR);
2033         add_reg(TFUCR);
2034         add_reg(RFOCR);
2035         if (cd->rmiimode)
2036                 add_reg(RMIIMODE);
2037         add_reg(FCFTR);
2038         if (cd->rpadir)
2039                 add_reg(RPADIR);
2040         if (!cd->no_trimd)
2041                 add_reg(TRIMD);
2042         add_reg(ECMR);
2043         add_reg(ECSR);
2044         add_reg(ECSIPR);
2045         add_reg(PIR);
2046         if (!cd->no_psr)
2047                 add_reg(PSR);
2048         add_reg(RDMLR);
2049         add_reg(RFLR);
2050         add_reg(IPGR);
2051         if (cd->apr)
2052                 add_reg(APR);
2053         if (cd->mpr)
2054                 add_reg(MPR);
2055         add_reg(RFCR);
2056         add_reg(RFCF);
2057         if (cd->tpauser)
2058                 add_reg(TPAUSER);
2059         add_reg(TPAUSECR);
2060         add_reg(GECMR);
2061         if (cd->bculr)
2062                 add_reg(BCULR);
2063         add_reg(MAHR);
2064         add_reg(MALR);
2065         add_reg(TROCR);
2066         add_reg(CDCR);
2067         add_reg(LCCR);
2068         add_reg(CNDCR);
2069         add_reg(CEFCR);
2070         add_reg(FRECR);
2071         add_reg(TSFRCR);
2072         add_reg(TLFRCR);
2073         add_reg(CERCR);
2074         add_reg(CEECR);
2075         add_reg(MAFCR);
2076         if (cd->rtrate)
2077                 add_reg(RTRATE);
2078         if (cd->hw_checksum)
2079                 add_reg(CSMR);
2080         if (cd->select_mii)
2081                 add_reg(RMII_MII);
2082         add_reg(ARSTR);
2083         if (cd->tsu) {
2084                 add_tsu_reg(TSU_CTRST);
2085                 add_tsu_reg(TSU_FWEN0);
2086                 add_tsu_reg(TSU_FWEN1);
2087                 add_tsu_reg(TSU_FCM);
2088                 add_tsu_reg(TSU_BSYSL0);
2089                 add_tsu_reg(TSU_BSYSL1);
2090                 add_tsu_reg(TSU_PRISL0);
2091                 add_tsu_reg(TSU_PRISL1);
2092                 add_tsu_reg(TSU_FWSL0);
2093                 add_tsu_reg(TSU_FWSL1);
2094                 add_tsu_reg(TSU_FWSLC);
2095                 add_tsu_reg(TSU_QTAG0);
2096                 add_tsu_reg(TSU_QTAG1);
2097                 add_tsu_reg(TSU_QTAGM0);
2098                 add_tsu_reg(TSU_QTAGM1);
2099                 add_tsu_reg(TSU_FWSR);
2100                 add_tsu_reg(TSU_FWINMK);
2101                 add_tsu_reg(TSU_ADQT0);
2102                 add_tsu_reg(TSU_ADQT1);
2103                 add_tsu_reg(TSU_VTAG0);
2104                 add_tsu_reg(TSU_VTAG1);
2105                 add_tsu_reg(TSU_ADSBSY);
2106                 add_tsu_reg(TSU_TEN);
2107                 add_tsu_reg(TSU_POST1);
2108                 add_tsu_reg(TSU_POST2);
2109                 add_tsu_reg(TSU_POST3);
2110                 add_tsu_reg(TSU_POST4);
2111                 if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) {
2112                         /* This is the start of a table, not just a single
2113                          * register.
2114                          */
2115                         if (buf) {
2116                                 unsigned int i;
2117
2118                                 mark_reg_valid(TSU_ADRH0);
2119                                 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2120                                         *buf++ = ioread32(
2121                                                 mdp->tsu_addr +
2122                                                 mdp->reg_offset[TSU_ADRH0] +
2123                                                 i * 4);
2124                         }
2125                         len += SH_ETH_TSU_CAM_ENTRIES * 2;
2126                 }
2127         }
2128
2129 #undef mark_reg_valid
2130 #undef add_reg_from
2131 #undef add_reg
2132 #undef add_tsu_reg
2133
2134         return len * 4;
2135 }
2136
2137 static int sh_eth_get_regs_len(struct net_device *ndev)
2138 {
2139         return __sh_eth_get_regs(ndev, NULL);
2140 }
2141
2142 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2143                             void *buf)
2144 {
2145         struct sh_eth_private *mdp = netdev_priv(ndev);
2146
2147         regs->version = SH_ETH_REG_DUMP_VERSION;
2148
2149         pm_runtime_get_sync(&mdp->pdev->dev);
2150         __sh_eth_get_regs(ndev, buf);
2151         pm_runtime_put_sync(&mdp->pdev->dev);
2152 }
2153
2154 static int sh_eth_nway_reset(struct net_device *ndev)
2155 {
2156         struct sh_eth_private *mdp = netdev_priv(ndev);
2157         unsigned long flags;
2158         int ret;
2159
2160         if (!ndev->phydev)
2161                 return -ENODEV;
2162
2163         spin_lock_irqsave(&mdp->lock, flags);
2164         ret = phy_start_aneg(ndev->phydev);
2165         spin_unlock_irqrestore(&mdp->lock, flags);
2166
2167         return ret;
2168 }
2169
2170 static u32 sh_eth_get_msglevel(struct net_device *ndev)
2171 {
2172         struct sh_eth_private *mdp = netdev_priv(ndev);
2173         return mdp->msg_enable;
2174 }
2175
2176 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2177 {
2178         struct sh_eth_private *mdp = netdev_priv(ndev);
2179         mdp->msg_enable = value;
2180 }
2181
2182 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2183         "rx_current", "tx_current",
2184         "rx_dirty", "tx_dirty",
2185 };
2186 #define SH_ETH_STATS_LEN  ARRAY_SIZE(sh_eth_gstrings_stats)
2187
2188 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2189 {
2190         switch (sset) {
2191         case ETH_SS_STATS:
2192                 return SH_ETH_STATS_LEN;
2193         default:
2194                 return -EOPNOTSUPP;
2195         }
2196 }
2197
2198 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
2199                                      struct ethtool_stats *stats, u64 *data)
2200 {
2201         struct sh_eth_private *mdp = netdev_priv(ndev);
2202         int i = 0;
2203
2204         /* device-specific stats */
2205         data[i++] = mdp->cur_rx;
2206         data[i++] = mdp->cur_tx;
2207         data[i++] = mdp->dirty_rx;
2208         data[i++] = mdp->dirty_tx;
2209 }
2210
2211 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2212 {
2213         switch (stringset) {
2214         case ETH_SS_STATS:
2215                 memcpy(data, *sh_eth_gstrings_stats,
2216                        sizeof(sh_eth_gstrings_stats));
2217                 break;
2218         }
2219 }
2220
2221 static void sh_eth_get_ringparam(struct net_device *ndev,
2222                                  struct ethtool_ringparam *ring)
2223 {
2224         struct sh_eth_private *mdp = netdev_priv(ndev);
2225
2226         ring->rx_max_pending = RX_RING_MAX;
2227         ring->tx_max_pending = TX_RING_MAX;
2228         ring->rx_pending = mdp->num_rx_ring;
2229         ring->tx_pending = mdp->num_tx_ring;
2230 }
2231
2232 static int sh_eth_set_ringparam(struct net_device *ndev,
2233                                 struct ethtool_ringparam *ring)
2234 {
2235         struct sh_eth_private *mdp = netdev_priv(ndev);
2236         int ret;
2237
2238         if (ring->tx_pending > TX_RING_MAX ||
2239             ring->rx_pending > RX_RING_MAX ||
2240             ring->tx_pending < TX_RING_MIN ||
2241             ring->rx_pending < RX_RING_MIN)
2242                 return -EINVAL;
2243         if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2244                 return -EINVAL;
2245
2246         if (netif_running(ndev)) {
2247                 netif_device_detach(ndev);
2248                 netif_tx_disable(ndev);
2249
2250                 /* Serialise with the interrupt handler and NAPI, then
2251                  * disable interrupts.  We have to clear the
2252                  * irq_enabled flag first to ensure that interrupts
2253                  * won't be re-enabled.
2254                  */
2255                 mdp->irq_enabled = false;
2256                 synchronize_irq(ndev->irq);
2257                 napi_synchronize(&mdp->napi);
2258                 sh_eth_write(ndev, 0x0000, EESIPR);
2259
2260                 sh_eth_dev_exit(ndev);
2261
2262                 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
2263                 sh_eth_ring_free(ndev);
2264         }
2265
2266         /* Set new parameters */
2267         mdp->num_rx_ring = ring->rx_pending;
2268         mdp->num_tx_ring = ring->tx_pending;
2269
2270         if (netif_running(ndev)) {
2271                 ret = sh_eth_ring_init(ndev);
2272                 if (ret < 0) {
2273                         netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2274                                    __func__);
2275                         return ret;
2276                 }
2277                 ret = sh_eth_dev_init(ndev);
2278                 if (ret < 0) {
2279                         netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2280                                    __func__);
2281                         return ret;
2282                 }
2283
2284                 netif_device_attach(ndev);
2285         }
2286
2287         return 0;
2288 }
2289
2290 static void sh_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2291 {
2292         struct sh_eth_private *mdp = netdev_priv(ndev);
2293
2294         wol->supported = 0;
2295         wol->wolopts = 0;
2296
2297         if (mdp->cd->magic && mdp->clk) {
2298                 wol->supported = WAKE_MAGIC;
2299                 wol->wolopts = mdp->wol_enabled ? WAKE_MAGIC : 0;
2300         }
2301 }
2302
2303 static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2304 {
2305         struct sh_eth_private *mdp = netdev_priv(ndev);
2306
2307         if (!mdp->cd->magic || !mdp->clk || wol->wolopts & ~WAKE_MAGIC)
2308                 return -EOPNOTSUPP;
2309
2310         mdp->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
2311
2312         device_set_wakeup_enable(&mdp->pdev->dev, mdp->wol_enabled);
2313
2314         return 0;
2315 }
2316
2317 static const struct ethtool_ops sh_eth_ethtool_ops = {
2318         .get_regs_len   = sh_eth_get_regs_len,
2319         .get_regs       = sh_eth_get_regs,
2320         .nway_reset     = sh_eth_nway_reset,
2321         .get_msglevel   = sh_eth_get_msglevel,
2322         .set_msglevel   = sh_eth_set_msglevel,
2323         .get_link       = ethtool_op_get_link,
2324         .get_strings    = sh_eth_get_strings,
2325         .get_ethtool_stats  = sh_eth_get_ethtool_stats,
2326         .get_sset_count     = sh_eth_get_sset_count,
2327         .get_ringparam  = sh_eth_get_ringparam,
2328         .set_ringparam  = sh_eth_set_ringparam,
2329         .get_link_ksettings = sh_eth_get_link_ksettings,
2330         .set_link_ksettings = sh_eth_set_link_ksettings,
2331         .get_wol        = sh_eth_get_wol,
2332         .set_wol        = sh_eth_set_wol,
2333 };
2334
2335 /* network device open function */
2336 static int sh_eth_open(struct net_device *ndev)
2337 {
2338         struct sh_eth_private *mdp = netdev_priv(ndev);
2339         int ret;
2340
2341         pm_runtime_get_sync(&mdp->pdev->dev);
2342
2343         napi_enable(&mdp->napi);
2344
2345         ret = request_irq(ndev->irq, sh_eth_interrupt,
2346                           mdp->cd->irq_flags, ndev->name, ndev);
2347         if (ret) {
2348                 netdev_err(ndev, "Can not assign IRQ number\n");
2349                 goto out_napi_off;
2350         }
2351
2352         /* Descriptor set */
2353         ret = sh_eth_ring_init(ndev);
2354         if (ret)
2355                 goto out_free_irq;
2356
2357         /* device init */
2358         ret = sh_eth_dev_init(ndev);
2359         if (ret)
2360                 goto out_free_irq;
2361
2362         /* PHY control start*/
2363         ret = sh_eth_phy_start(ndev);
2364         if (ret)
2365                 goto out_free_irq;
2366
2367         netif_start_queue(ndev);
2368
2369         mdp->is_opened = 1;
2370
2371         return ret;
2372
2373 out_free_irq:
2374         free_irq(ndev->irq, ndev);
2375 out_napi_off:
2376         napi_disable(&mdp->napi);
2377         pm_runtime_put_sync(&mdp->pdev->dev);
2378         return ret;
2379 }
2380
2381 /* Timeout function */
2382 static void sh_eth_tx_timeout(struct net_device *ndev)
2383 {
2384         struct sh_eth_private *mdp = netdev_priv(ndev);
2385         struct sh_eth_rxdesc *rxdesc;
2386         int i;
2387
2388         netif_stop_queue(ndev);
2389
2390         netif_err(mdp, timer, ndev,
2391                   "transmit timed out, status %8.8x, resetting...\n",
2392                   sh_eth_read(ndev, EESR));
2393
2394         /* tx_errors count up */
2395         ndev->stats.tx_errors++;
2396
2397         /* Free all the skbuffs in the Rx queue. */
2398         for (i = 0; i < mdp->num_rx_ring; i++) {
2399                 rxdesc = &mdp->rx_ring[i];
2400                 rxdesc->status = cpu_to_le32(0);
2401                 rxdesc->addr = cpu_to_le32(0xBADF00D0);
2402                 dev_kfree_skb(mdp->rx_skbuff[i]);
2403                 mdp->rx_skbuff[i] = NULL;
2404         }
2405         for (i = 0; i < mdp->num_tx_ring; i++) {
2406                 dev_kfree_skb(mdp->tx_skbuff[i]);
2407                 mdp->tx_skbuff[i] = NULL;
2408         }
2409
2410         /* device init */
2411         sh_eth_dev_init(ndev);
2412
2413         netif_start_queue(ndev);
2414 }
2415
2416 /* Packet transmit function */
2417 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2418 {
2419         struct sh_eth_private *mdp = netdev_priv(ndev);
2420         struct sh_eth_txdesc *txdesc;
2421         dma_addr_t dma_addr;
2422         u32 entry;
2423         unsigned long flags;
2424
2425         spin_lock_irqsave(&mdp->lock, flags);
2426         if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2427                 if (!sh_eth_tx_free(ndev, true)) {
2428                         netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2429                         netif_stop_queue(ndev);
2430                         spin_unlock_irqrestore(&mdp->lock, flags);
2431                         return NETDEV_TX_BUSY;
2432                 }
2433         }
2434         spin_unlock_irqrestore(&mdp->lock, flags);
2435
2436         if (skb_put_padto(skb, ETH_ZLEN))
2437                 return NETDEV_TX_OK;
2438
2439         entry = mdp->cur_tx % mdp->num_tx_ring;
2440         mdp->tx_skbuff[entry] = skb;
2441         txdesc = &mdp->tx_ring[entry];
2442         /* soft swap. */
2443         if (!mdp->cd->hw_swap)
2444                 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
2445         dma_addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2446                                   DMA_TO_DEVICE);
2447         if (dma_mapping_error(&ndev->dev, dma_addr)) {
2448                 kfree_skb(skb);
2449                 return NETDEV_TX_OK;
2450         }
2451         txdesc->addr = cpu_to_le32(dma_addr);
2452         txdesc->len  = cpu_to_le32(skb->len << 16);
2453
2454         dma_wmb(); /* TACT bit must be set after all the above writes */
2455         if (entry >= mdp->num_tx_ring - 1)
2456                 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
2457         else
2458                 txdesc->status |= cpu_to_le32(TD_TACT);
2459
2460         mdp->cur_tx++;
2461
2462         if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2463                 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2464
2465         return NETDEV_TX_OK;
2466 }
2467
2468 /* The statistics registers have write-clear behaviour, which means we
2469  * will lose any increment between the read and write.  We mitigate
2470  * this by only clearing when we read a non-zero value, so we will
2471  * never falsely report a total of zero.
2472  */
2473 static void
2474 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2475 {
2476         u32 delta = sh_eth_read(ndev, reg);
2477
2478         if (delta) {
2479                 *stat += delta;
2480                 sh_eth_write(ndev, 0, reg);
2481         }
2482 }
2483
2484 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2485 {
2486         struct sh_eth_private *mdp = netdev_priv(ndev);
2487
2488         if (sh_eth_is_rz_fast_ether(mdp))
2489                 return &ndev->stats;
2490
2491         if (!mdp->is_opened)
2492                 return &ndev->stats;
2493
2494         sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2495         sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2496         sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
2497
2498         if (sh_eth_is_gether(mdp)) {
2499                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2500                                    CERCR);
2501                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2502                                    CEECR);
2503         } else {
2504                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2505                                    CNDCR);
2506         }
2507
2508         return &ndev->stats;
2509 }
2510
2511 /* device close function */
2512 static int sh_eth_close(struct net_device *ndev)
2513 {
2514         struct sh_eth_private *mdp = netdev_priv(ndev);
2515
2516         netif_stop_queue(ndev);
2517
2518         /* Serialise with the interrupt handler and NAPI, then disable
2519          * interrupts.  We have to clear the irq_enabled flag first to
2520          * ensure that interrupts won't be re-enabled.
2521          */
2522         mdp->irq_enabled = false;
2523         synchronize_irq(ndev->irq);
2524         napi_disable(&mdp->napi);
2525         sh_eth_write(ndev, 0x0000, EESIPR);
2526
2527         sh_eth_dev_exit(ndev);
2528
2529         /* PHY Disconnect */
2530         if (ndev->phydev) {
2531                 phy_stop(ndev->phydev);
2532                 phy_disconnect(ndev->phydev);
2533         }
2534
2535         free_irq(ndev->irq, ndev);
2536
2537         /* Free all the skbuffs in the Rx queue and the DMA buffer. */
2538         sh_eth_ring_free(ndev);
2539
2540         pm_runtime_put_sync(&mdp->pdev->dev);
2541
2542         mdp->is_opened = 0;
2543
2544         return 0;
2545 }
2546
2547 /* ioctl to device function */
2548 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2549 {
2550         struct phy_device *phydev = ndev->phydev;
2551
2552         if (!netif_running(ndev))
2553                 return -EINVAL;
2554
2555         if (!phydev)
2556                 return -ENODEV;
2557
2558         return phy_mii_ioctl(phydev, rq, cmd);
2559 }
2560
2561 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2562 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2563                                             int entry)
2564 {
2565         return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2566 }
2567
2568 static u32 sh_eth_tsu_get_post_mask(int entry)
2569 {
2570         return 0x0f << (28 - ((entry % 8) * 4));
2571 }
2572
2573 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2574 {
2575         return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2576 }
2577
2578 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2579                                              int entry)
2580 {
2581         struct sh_eth_private *mdp = netdev_priv(ndev);
2582         u32 tmp;
2583         void *reg_offset;
2584
2585         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2586         tmp = ioread32(reg_offset);
2587         iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2588 }
2589
2590 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2591                                               int entry)
2592 {
2593         struct sh_eth_private *mdp = netdev_priv(ndev);
2594         u32 post_mask, ref_mask, tmp;
2595         void *reg_offset;
2596
2597         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2598         post_mask = sh_eth_tsu_get_post_mask(entry);
2599         ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2600
2601         tmp = ioread32(reg_offset);
2602         iowrite32(tmp & ~post_mask, reg_offset);
2603
2604         /* If other port enables, the function returns "true" */
2605         return tmp & ref_mask;
2606 }
2607
2608 static int sh_eth_tsu_busy(struct net_device *ndev)
2609 {
2610         int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2611         struct sh_eth_private *mdp = netdev_priv(ndev);
2612
2613         while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2614                 udelay(10);
2615                 timeout--;
2616                 if (timeout <= 0) {
2617                         netdev_err(ndev, "%s: timeout\n", __func__);
2618                         return -ETIMEDOUT;
2619                 }
2620         }
2621
2622         return 0;
2623 }
2624
2625 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2626                                   const u8 *addr)
2627 {
2628         u32 val;
2629
2630         val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2631         iowrite32(val, reg);
2632         if (sh_eth_tsu_busy(ndev) < 0)
2633                 return -EBUSY;
2634
2635         val = addr[4] << 8 | addr[5];
2636         iowrite32(val, reg + 4);
2637         if (sh_eth_tsu_busy(ndev) < 0)
2638                 return -EBUSY;
2639
2640         return 0;
2641 }
2642
2643 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2644 {
2645         u32 val;
2646
2647         val = ioread32(reg);
2648         addr[0] = (val >> 24) & 0xff;
2649         addr[1] = (val >> 16) & 0xff;
2650         addr[2] = (val >> 8) & 0xff;
2651         addr[3] = val & 0xff;
2652         val = ioread32(reg + 4);
2653         addr[4] = (val >> 8) & 0xff;
2654         addr[5] = val & 0xff;
2655 }
2656
2657
2658 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2659 {
2660         struct sh_eth_private *mdp = netdev_priv(ndev);
2661         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2662         int i;
2663         u8 c_addr[ETH_ALEN];
2664
2665         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2666                 sh_eth_tsu_read_entry(reg_offset, c_addr);
2667                 if (ether_addr_equal(addr, c_addr))
2668                         return i;
2669         }
2670
2671         return -ENOENT;
2672 }
2673
2674 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2675 {
2676         u8 blank[ETH_ALEN];
2677         int entry;
2678
2679         memset(blank, 0, sizeof(blank));
2680         entry = sh_eth_tsu_find_entry(ndev, blank);
2681         return (entry < 0) ? -ENOMEM : entry;
2682 }
2683
2684 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2685                                               int entry)
2686 {
2687         struct sh_eth_private *mdp = netdev_priv(ndev);
2688         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2689         int ret;
2690         u8 blank[ETH_ALEN];
2691
2692         sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2693                          ~(1 << (31 - entry)), TSU_TEN);
2694
2695         memset(blank, 0, sizeof(blank));
2696         ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2697         if (ret < 0)
2698                 return ret;
2699         return 0;
2700 }
2701
2702 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2703 {
2704         struct sh_eth_private *mdp = netdev_priv(ndev);
2705         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2706         int i, ret;
2707
2708         if (!mdp->cd->tsu)
2709                 return 0;
2710
2711         i = sh_eth_tsu_find_entry(ndev, addr);
2712         if (i < 0) {
2713                 /* No entry found, create one */
2714                 i = sh_eth_tsu_find_empty(ndev);
2715                 if (i < 0)
2716                         return -ENOMEM;
2717                 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2718                 if (ret < 0)
2719                         return ret;
2720
2721                 /* Enable the entry */
2722                 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2723                                  (1 << (31 - i)), TSU_TEN);
2724         }
2725
2726         /* Entry found or created, enable POST */
2727         sh_eth_tsu_enable_cam_entry_post(ndev, i);
2728
2729         return 0;
2730 }
2731
2732 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2733 {
2734         struct sh_eth_private *mdp = netdev_priv(ndev);
2735         int i, ret;
2736
2737         if (!mdp->cd->tsu)
2738                 return 0;
2739
2740         i = sh_eth_tsu_find_entry(ndev, addr);
2741         if (i) {
2742                 /* Entry found */
2743                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2744                         goto done;
2745
2746                 /* Disable the entry if both ports was disabled */
2747                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2748                 if (ret < 0)
2749                         return ret;
2750         }
2751 done:
2752         return 0;
2753 }
2754
2755 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2756 {
2757         struct sh_eth_private *mdp = netdev_priv(ndev);
2758         int i, ret;
2759
2760         if (!mdp->cd->tsu)
2761                 return 0;
2762
2763         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2764                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2765                         continue;
2766
2767                 /* Disable the entry if both ports was disabled */
2768                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2769                 if (ret < 0)
2770                         return ret;
2771         }
2772
2773         return 0;
2774 }
2775
2776 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2777 {
2778         struct sh_eth_private *mdp = netdev_priv(ndev);
2779         u8 addr[ETH_ALEN];
2780         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2781         int i;
2782
2783         if (!mdp->cd->tsu)
2784                 return;
2785
2786         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2787                 sh_eth_tsu_read_entry(reg_offset, addr);
2788                 if (is_multicast_ether_addr(addr))
2789                         sh_eth_tsu_del_entry(ndev, addr);
2790         }
2791 }
2792
2793 /* Update promiscuous flag and multicast filter */
2794 static void sh_eth_set_rx_mode(struct net_device *ndev)
2795 {
2796         struct sh_eth_private *mdp = netdev_priv(ndev);
2797         u32 ecmr_bits;
2798         int mcast_all = 0;
2799         unsigned long flags;
2800
2801         spin_lock_irqsave(&mdp->lock, flags);
2802         /* Initial condition is MCT = 1, PRM = 0.
2803          * Depending on ndev->flags, set PRM or clear MCT
2804          */
2805         ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2806         if (mdp->cd->tsu)
2807                 ecmr_bits |= ECMR_MCT;
2808
2809         if (!(ndev->flags & IFF_MULTICAST)) {
2810                 sh_eth_tsu_purge_mcast(ndev);
2811                 mcast_all = 1;
2812         }
2813         if (ndev->flags & IFF_ALLMULTI) {
2814                 sh_eth_tsu_purge_mcast(ndev);
2815                 ecmr_bits &= ~ECMR_MCT;
2816                 mcast_all = 1;
2817         }
2818
2819         if (ndev->flags & IFF_PROMISC) {
2820                 sh_eth_tsu_purge_all(ndev);
2821                 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2822         } else if (mdp->cd->tsu) {
2823                 struct netdev_hw_addr *ha;
2824                 netdev_for_each_mc_addr(ha, ndev) {
2825                         if (mcast_all && is_multicast_ether_addr(ha->addr))
2826                                 continue;
2827
2828                         if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2829                                 if (!mcast_all) {
2830                                         sh_eth_tsu_purge_mcast(ndev);
2831                                         ecmr_bits &= ~ECMR_MCT;
2832                                         mcast_all = 1;
2833                                 }
2834                         }
2835                 }
2836         }
2837
2838         /* update the ethernet mode */
2839         sh_eth_write(ndev, ecmr_bits, ECMR);
2840
2841         spin_unlock_irqrestore(&mdp->lock, flags);
2842 }
2843
2844 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2845 {
2846         if (!mdp->port)
2847                 return TSU_VTAG0;
2848         else
2849                 return TSU_VTAG1;
2850 }
2851
2852 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2853                                   __be16 proto, u16 vid)
2854 {
2855         struct sh_eth_private *mdp = netdev_priv(ndev);
2856         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2857
2858         if (unlikely(!mdp->cd->tsu))
2859                 return -EPERM;
2860
2861         /* No filtering if vid = 0 */
2862         if (!vid)
2863                 return 0;
2864
2865         mdp->vlan_num_ids++;
2866
2867         /* The controller has one VLAN tag HW filter. So, if the filter is
2868          * already enabled, the driver disables it and the filte
2869          */
2870         if (mdp->vlan_num_ids > 1) {
2871                 /* disable VLAN filter */
2872                 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2873                 return 0;
2874         }
2875
2876         sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2877                          vtag_reg_index);
2878
2879         return 0;
2880 }
2881
2882 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2883                                    __be16 proto, u16 vid)
2884 {
2885         struct sh_eth_private *mdp = netdev_priv(ndev);
2886         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2887
2888         if (unlikely(!mdp->cd->tsu))
2889                 return -EPERM;
2890
2891         /* No filtering if vid = 0 */
2892         if (!vid)
2893                 return 0;
2894
2895         mdp->vlan_num_ids--;
2896         sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2897
2898         return 0;
2899 }
2900
2901 /* SuperH's TSU register init function */
2902 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2903 {
2904         if (sh_eth_is_rz_fast_ether(mdp)) {
2905                 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2906                 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL,
2907                                  TSU_FWSLC);    /* Enable POST registers */
2908                 return;
2909         }
2910
2911         sh_eth_tsu_write(mdp, 0, TSU_FWEN0);    /* Disable forward(0->1) */
2912         sh_eth_tsu_write(mdp, 0, TSU_FWEN1);    /* Disable forward(1->0) */
2913         sh_eth_tsu_write(mdp, 0, TSU_FCM);      /* forward fifo 3k-3k */
2914         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2915         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2916         sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2917         sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2918         sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2919         sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2920         sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2921         if (sh_eth_is_gether(mdp)) {
2922                 sh_eth_tsu_write(mdp, 0, TSU_QTAG0);    /* Disable QTAG(0->1) */
2923                 sh_eth_tsu_write(mdp, 0, TSU_QTAG1);    /* Disable QTAG(1->0) */
2924         } else {
2925                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0);   /* Disable QTAG(0->1) */
2926                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1);   /* Disable QTAG(1->0) */
2927         }
2928         sh_eth_tsu_write(mdp, 0, TSU_FWSR);     /* all interrupt status clear */
2929         sh_eth_tsu_write(mdp, 0, TSU_FWINMK);   /* Disable all interrupt */
2930         sh_eth_tsu_write(mdp, 0, TSU_TEN);      /* Disable all CAM entry */
2931         sh_eth_tsu_write(mdp, 0, TSU_POST1);    /* Disable CAM entry [ 0- 7] */
2932         sh_eth_tsu_write(mdp, 0, TSU_POST2);    /* Disable CAM entry [ 8-15] */
2933         sh_eth_tsu_write(mdp, 0, TSU_POST3);    /* Disable CAM entry [16-23] */
2934         sh_eth_tsu_write(mdp, 0, TSU_POST4);    /* Disable CAM entry [24-31] */
2935 }
2936
2937 /* MDIO bus release function */
2938 static int sh_mdio_release(struct sh_eth_private *mdp)
2939 {
2940         /* unregister mdio bus */
2941         mdiobus_unregister(mdp->mii_bus);
2942
2943         /* free bitbang info */
2944         free_mdio_bitbang(mdp->mii_bus);
2945
2946         return 0;
2947 }
2948
2949 /* MDIO bus init function */
2950 static int sh_mdio_init(struct sh_eth_private *mdp,
2951                         struct sh_eth_plat_data *pd)
2952 {
2953         int ret;
2954         struct bb_info *bitbang;
2955         struct platform_device *pdev = mdp->pdev;
2956         struct device *dev = &mdp->pdev->dev;
2957
2958         /* create bit control struct for PHY */
2959         bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
2960         if (!bitbang)
2961                 return -ENOMEM;
2962
2963         /* bitbang init */
2964         bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2965         bitbang->set_gate = pd->set_mdio_gate;
2966         bitbang->ctrl.ops = &bb_ops;
2967
2968         /* MII controller setting */
2969         mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2970         if (!mdp->mii_bus)
2971                 return -ENOMEM;
2972
2973         /* Hook up MII support for ethtool */
2974         mdp->mii_bus->name = "sh_mii";
2975         mdp->mii_bus->parent = dev;
2976         snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2977                  pdev->name, pdev->id);
2978
2979         /* register MDIO bus */
2980         if (dev->of_node) {
2981                 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
2982         } else {
2983                 if (pd->phy_irq > 0)
2984                         mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2985
2986                 ret = mdiobus_register(mdp->mii_bus);
2987         }
2988
2989         if (ret)
2990                 goto out_free_bus;
2991
2992         return 0;
2993
2994 out_free_bus:
2995         free_mdio_bitbang(mdp->mii_bus);
2996         return ret;
2997 }
2998
2999 static const u16 *sh_eth_get_register_offset(int register_type)
3000 {
3001         const u16 *reg_offset = NULL;
3002
3003         switch (register_type) {
3004         case SH_ETH_REG_GIGABIT:
3005                 reg_offset = sh_eth_offset_gigabit;
3006                 break;
3007         case SH_ETH_REG_FAST_RZ:
3008                 reg_offset = sh_eth_offset_fast_rz;
3009                 break;
3010         case SH_ETH_REG_FAST_RCAR:
3011                 reg_offset = sh_eth_offset_fast_rcar;
3012                 break;
3013         case SH_ETH_REG_FAST_SH4:
3014                 reg_offset = sh_eth_offset_fast_sh4;
3015                 break;
3016         case SH_ETH_REG_FAST_SH3_SH2:
3017                 reg_offset = sh_eth_offset_fast_sh3_sh2;
3018                 break;
3019         }
3020
3021         return reg_offset;
3022 }
3023
3024 static const struct net_device_ops sh_eth_netdev_ops = {
3025         .ndo_open               = sh_eth_open,
3026         .ndo_stop               = sh_eth_close,
3027         .ndo_start_xmit         = sh_eth_start_xmit,
3028         .ndo_get_stats          = sh_eth_get_stats,
3029         .ndo_set_rx_mode        = sh_eth_set_rx_mode,
3030         .ndo_tx_timeout         = sh_eth_tx_timeout,
3031         .ndo_do_ioctl           = sh_eth_do_ioctl,
3032         .ndo_validate_addr      = eth_validate_addr,
3033         .ndo_set_mac_address    = eth_mac_addr,
3034 };
3035
3036 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
3037         .ndo_open               = sh_eth_open,
3038         .ndo_stop               = sh_eth_close,
3039         .ndo_start_xmit         = sh_eth_start_xmit,
3040         .ndo_get_stats          = sh_eth_get_stats,
3041         .ndo_set_rx_mode        = sh_eth_set_rx_mode,
3042         .ndo_vlan_rx_add_vid    = sh_eth_vlan_rx_add_vid,
3043         .ndo_vlan_rx_kill_vid   = sh_eth_vlan_rx_kill_vid,
3044         .ndo_tx_timeout         = sh_eth_tx_timeout,
3045         .ndo_do_ioctl           = sh_eth_do_ioctl,
3046         .ndo_validate_addr      = eth_validate_addr,
3047         .ndo_set_mac_address    = eth_mac_addr,
3048 };
3049
3050 #ifdef CONFIG_OF
3051 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3052 {
3053         struct device_node *np = dev->of_node;
3054         struct sh_eth_plat_data *pdata;
3055         const char *mac_addr;
3056
3057         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3058         if (!pdata)
3059                 return NULL;
3060
3061         pdata->phy_interface = of_get_phy_mode(np);
3062
3063         mac_addr = of_get_mac_address(np);
3064         if (mac_addr)
3065                 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
3066
3067         pdata->no_ether_link =
3068                 of_property_read_bool(np, "renesas,no-ether-link");
3069         pdata->ether_link_active_low =
3070                 of_property_read_bool(np, "renesas,ether-link-active-low");
3071
3072         return pdata;
3073 }
3074
3075 static const struct of_device_id sh_eth_match_table[] = {
3076         { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
3077         { .compatible = "renesas,ether-r8a7743", .data = &r8a779x_data },
3078         { .compatible = "renesas,ether-r8a7745", .data = &r8a779x_data },
3079         { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
3080         { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
3081         { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
3082         { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
3083         { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
3084         { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
3085         { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
3086         { }
3087 };
3088 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
3089 #else
3090 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3091 {
3092         return NULL;
3093 }
3094 #endif
3095
3096 static int sh_eth_drv_probe(struct platform_device *pdev)
3097 {
3098         struct resource *res;
3099         struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
3100         const struct platform_device_id *id = platform_get_device_id(pdev);
3101         struct sh_eth_private *mdp;
3102         struct net_device *ndev;
3103         int ret, devno;
3104
3105         /* get base addr */
3106         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3107
3108         ndev = alloc_etherdev(sizeof(struct sh_eth_private));
3109         if (!ndev)
3110                 return -ENOMEM;
3111
3112         pm_runtime_enable(&pdev->dev);
3113         pm_runtime_get_sync(&pdev->dev);
3114
3115         devno = pdev->id;
3116         if (devno < 0)
3117                 devno = 0;
3118
3119         ret = platform_get_irq(pdev, 0);
3120         if (ret < 0)
3121                 goto out_release;
3122         ndev->irq = ret;
3123
3124         SET_NETDEV_DEV(ndev, &pdev->dev);
3125
3126         mdp = netdev_priv(ndev);
3127         mdp->num_tx_ring = TX_RING_SIZE;
3128         mdp->num_rx_ring = RX_RING_SIZE;
3129         mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3130         if (IS_ERR(mdp->addr)) {
3131                 ret = PTR_ERR(mdp->addr);
3132                 goto out_release;
3133         }
3134
3135         /* Get clock, if not found that's OK but Wake-On-Lan is unavailable */
3136         mdp->clk = devm_clk_get(&pdev->dev, NULL);
3137         if (IS_ERR(mdp->clk))
3138                 mdp->clk = NULL;
3139
3140         ndev->base_addr = res->start;
3141
3142         spin_lock_init(&mdp->lock);
3143         mdp->pdev = pdev;
3144
3145         if (pdev->dev.of_node)
3146                 pd = sh_eth_parse_dt(&pdev->dev);
3147         if (!pd) {
3148                 dev_err(&pdev->dev, "no platform data\n");
3149                 ret = -EINVAL;
3150                 goto out_release;
3151         }
3152
3153         /* get PHY ID */
3154         mdp->phy_id = pd->phy;
3155         mdp->phy_interface = pd->phy_interface;
3156         mdp->no_ether_link = pd->no_ether_link;
3157         mdp->ether_link_active_low = pd->ether_link_active_low;
3158
3159         /* set cpu data */
3160         if (id)
3161                 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3162         else
3163                 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev);
3164
3165         mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
3166         if (!mdp->reg_offset) {
3167                 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3168                         mdp->cd->register_type);
3169                 ret = -EINVAL;
3170                 goto out_release;
3171         }
3172         sh_eth_set_default_cpu_data(mdp->cd);
3173
3174         /* set function */
3175         if (mdp->cd->tsu)
3176                 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3177         else
3178                 ndev->netdev_ops = &sh_eth_netdev_ops;
3179         ndev->ethtool_ops = &sh_eth_ethtool_ops;
3180         ndev->watchdog_timeo = TX_TIMEOUT;
3181
3182         /* debug message level */
3183         mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
3184
3185         /* read and set MAC address */
3186         read_mac_address(ndev, pd->mac_addr);
3187         if (!is_valid_ether_addr(ndev->dev_addr)) {
3188                 dev_warn(&pdev->dev,
3189                          "no valid MAC address supplied, using a random one.\n");
3190                 eth_hw_addr_random(ndev);
3191         }
3192
3193         /* ioremap the TSU registers */
3194         if (mdp->cd->tsu) {
3195                 struct resource *rtsu;
3196                 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3197                 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
3198                 if (IS_ERR(mdp->tsu_addr)) {
3199                         ret = PTR_ERR(mdp->tsu_addr);
3200                         goto out_release;
3201                 }
3202                 mdp->port = devno % 2;
3203                 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
3204         }
3205
3206         /* initialize first or needed device */
3207         if (!devno || pd->needs_init) {
3208                 if (mdp->cd->chip_reset)
3209                         mdp->cd->chip_reset(ndev);
3210
3211                 if (mdp->cd->tsu) {
3212                         /* TSU init (Init only)*/
3213                         sh_eth_tsu_init(mdp);
3214                 }
3215         }
3216
3217         if (mdp->cd->rmiimode)
3218                 sh_eth_write(ndev, 0x1, RMIIMODE);
3219
3220         /* MDIO bus init */
3221         ret = sh_mdio_init(mdp, pd);
3222         if (ret) {
3223                 if (ret != -EPROBE_DEFER)
3224                         dev_err(&pdev->dev, "MDIO init failed: %d\n", ret);
3225                 goto out_release;
3226         }
3227
3228         netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3229
3230         /* network device register */
3231         ret = register_netdev(ndev);
3232         if (ret)
3233                 goto out_napi_del;
3234
3235         if (mdp->cd->magic && mdp->clk)
3236                 device_set_wakeup_capable(&pdev->dev, 1);
3237
3238         /* print device information */
3239         netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3240                     (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
3241
3242         pm_runtime_put(&pdev->dev);
3243         platform_set_drvdata(pdev, ndev);
3244
3245         return ret;
3246
3247 out_napi_del:
3248         netif_napi_del(&mdp->napi);
3249         sh_mdio_release(mdp);
3250
3251 out_release:
3252         /* net_dev free */
3253         if (ndev)
3254                 free_netdev(ndev);
3255
3256         pm_runtime_put(&pdev->dev);
3257         pm_runtime_disable(&pdev->dev);
3258         return ret;
3259 }
3260
3261 static int sh_eth_drv_remove(struct platform_device *pdev)
3262 {
3263         struct net_device *ndev = platform_get_drvdata(pdev);
3264         struct sh_eth_private *mdp = netdev_priv(ndev);
3265
3266         unregister_netdev(ndev);
3267         netif_napi_del(&mdp->napi);
3268         sh_mdio_release(mdp);
3269         pm_runtime_disable(&pdev->dev);
3270         free_netdev(ndev);
3271
3272         return 0;
3273 }
3274
3275 #ifdef CONFIG_PM
3276 #ifdef CONFIG_PM_SLEEP
3277 static int sh_eth_wol_setup(struct net_device *ndev)
3278 {
3279         struct sh_eth_private *mdp = netdev_priv(ndev);
3280
3281         /* Only allow ECI interrupts */
3282         synchronize_irq(ndev->irq);
3283         napi_disable(&mdp->napi);
3284         sh_eth_write(ndev, EESIPR_ECIIP, EESIPR);
3285
3286         /* Enable MagicPacket */
3287         sh_eth_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
3288
3289         /* Increased clock usage so device won't be suspended */
3290         clk_enable(mdp->clk);
3291
3292         return enable_irq_wake(ndev->irq);
3293 }
3294
3295 static int sh_eth_wol_restore(struct net_device *ndev)
3296 {
3297         struct sh_eth_private *mdp = netdev_priv(ndev);
3298         int ret;
3299
3300         napi_enable(&mdp->napi);
3301
3302         /* Disable MagicPacket */
3303         sh_eth_modify(ndev, ECMR, ECMR_MPDE, 0);
3304
3305         /* The device needs to be reset to restore MagicPacket logic
3306          * for next wakeup. If we close and open the device it will
3307          * both be reset and all registers restored. This is what
3308          * happens during suspend and resume without WoL enabled.
3309          */
3310         ret = sh_eth_close(ndev);
3311         if (ret < 0)
3312                 return ret;
3313         ret = sh_eth_open(ndev);
3314         if (ret < 0)
3315                 return ret;
3316
3317         /* Restore clock usage count */
3318         clk_disable(mdp->clk);
3319
3320         return disable_irq_wake(ndev->irq);
3321 }
3322
3323 static int sh_eth_suspend(struct device *dev)
3324 {
3325         struct net_device *ndev = dev_get_drvdata(dev);
3326         struct sh_eth_private *mdp = netdev_priv(ndev);
3327         int ret = 0;
3328
3329         if (!netif_running(ndev))
3330                 return 0;
3331
3332         netif_device_detach(ndev);
3333
3334         if (mdp->wol_enabled)
3335                 ret = sh_eth_wol_setup(ndev);
3336         else
3337                 ret = sh_eth_close(ndev);
3338
3339         return ret;
3340 }
3341
3342 static int sh_eth_resume(struct device *dev)
3343 {
3344         struct net_device *ndev = dev_get_drvdata(dev);
3345         struct sh_eth_private *mdp = netdev_priv(ndev);
3346         int ret = 0;
3347
3348         if (!netif_running(ndev))
3349                 return 0;
3350
3351         if (mdp->wol_enabled)
3352                 ret = sh_eth_wol_restore(ndev);
3353         else
3354                 ret = sh_eth_open(ndev);
3355
3356         if (ret < 0)
3357                 return ret;
3358
3359         netif_device_attach(ndev);
3360
3361         return ret;
3362 }
3363 #endif
3364
3365 static int sh_eth_runtime_nop(struct device *dev)
3366 {
3367         /* Runtime PM callback shared between ->runtime_suspend()
3368          * and ->runtime_resume(). Simply returns success.
3369          *
3370          * This driver re-initializes all registers after
3371          * pm_runtime_get_sync() anyway so there is no need
3372          * to save and restore registers here.
3373          */
3374         return 0;
3375 }
3376
3377 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
3378         SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
3379         SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
3380 };
3381 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3382 #else
3383 #define SH_ETH_PM_OPS NULL
3384 #endif
3385
3386 static struct platform_device_id sh_eth_id_table[] = {
3387         { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3388         { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3389         { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3390         { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3391         { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3392         { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3393         { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3394         { }
3395 };
3396 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3397
3398 static struct platform_driver sh_eth_driver = {
3399         .probe = sh_eth_drv_probe,
3400         .remove = sh_eth_drv_remove,
3401         .id_table = sh_eth_id_table,
3402         .driver = {
3403                    .name = CARDNAME,
3404                    .pm = SH_ETH_PM_OPS,
3405                    .of_match_table = of_match_ptr(sh_eth_match_table),
3406         },
3407 };
3408
3409 module_platform_driver(sh_eth_driver);
3410
3411 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3412 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3413 MODULE_LICENSE("GPL v2");