drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/firmware.h>
  28 #include <linux/pci-aspm.h>
  29 #include <linux/prefetch.h>
  30 #include <linux/ipv6.h>
  31 #include <net/ip6_checksum.h>
  32
  33 #include <asm/io.h>
  34 #include <asm/irq.h>
  35
  36 #define RTL8169_VERSION "2.3LK-NAPI"
  37 #define MODULENAME "r8169"
  38 #define PFX MODULENAME ": "
  39
  40 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  41 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  42 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  43 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  44 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  45 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  46 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  47 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  48 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  49 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  50 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  51 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  52 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  53 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  54 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  55 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  56 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  57 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  58 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  59
  60 #ifdef RTL8169_DEBUG
  61 #define assert(expr) \
  62         if (!(expr)) {                                  \
  63                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  64                 #expr,__FILE__,__func__,__LINE__);              \
  65         }
  66 #define dprintk(fmt, args...) \
  67         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  68 #else
  69 #define assert(expr) do {} while (0)
  70 #define dprintk(fmt, args...)   do {} while (0)
  71 #endif /* RTL8169_DEBUG */
  72
  73 #define R8169_MSG_DEFAULT \
  74         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  75
  76 #define TX_SLOTS_AVAIL(tp) \
  77         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  78
  79 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  80 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  81         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  82
  83 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  84    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  85 static const int multicast_filter_limit = 32;
  86
  87 #define MAX_READ_REQUEST_SHIFT  12
  88 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  89 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  90
  91 #define R8169_REGS_SIZE         256
  92 #define R8169_NAPI_WEIGHT       64
  93 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  94 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  95 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  96 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  97
  98 #define RTL8169_TX_TIMEOUT      (6*HZ)
  99 #define RTL8169_PHY_TIMEOUT     (10*HZ)
 100
 101 /* write/read MMIO register */
 102 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
 103 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
 104 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
 105 #define RTL_R8(reg)             readb (ioaddr + (reg))
 106 #define RTL_R16(reg)            readw (ioaddr + (reg))
 107 #define RTL_R32(reg)            readl (ioaddr + (reg))
 108
 109 enum mac_version {
 110         RTL_GIGA_MAC_VER_01 = 0,
 111         RTL_GIGA_MAC_VER_02,
 112         RTL_GIGA_MAC_VER_03,
 113         RTL_GIGA_MAC_VER_04,
 114         RTL_GIGA_MAC_VER_05,
 115         RTL_GIGA_MAC_VER_06,
 116         RTL_GIGA_MAC_VER_07,
 117         RTL_GIGA_MAC_VER_08,
 118         RTL_GIGA_MAC_VER_09,
 119         RTL_GIGA_MAC_VER_10,
 120         RTL_GIGA_MAC_VER_11,
 121         RTL_GIGA_MAC_VER_12,
 122         RTL_GIGA_MAC_VER_13,
 123         RTL_GIGA_MAC_VER_14,
 124         RTL_GIGA_MAC_VER_15,
 125         RTL_GIGA_MAC_VER_16,
 126         RTL_GIGA_MAC_VER_17,
 127         RTL_GIGA_MAC_VER_18,
 128         RTL_GIGA_MAC_VER_19,
 129         RTL_GIGA_MAC_VER_20,
 130         RTL_GIGA_MAC_VER_21,
 131         RTL_GIGA_MAC_VER_22,
 132         RTL_GIGA_MAC_VER_23,
 133         RTL_GIGA_MAC_VER_24,
 134         RTL_GIGA_MAC_VER_25,
 135         RTL_GIGA_MAC_VER_26,
 136         RTL_GIGA_MAC_VER_27,
 137         RTL_GIGA_MAC_VER_28,
 138         RTL_GIGA_MAC_VER_29,
 139         RTL_GIGA_MAC_VER_30,
 140         RTL_GIGA_MAC_VER_31,
 141         RTL_GIGA_MAC_VER_32,
 142         RTL_GIGA_MAC_VER_33,
 143         RTL_GIGA_MAC_VER_34,
 144         RTL_GIGA_MAC_VER_35,
 145         RTL_GIGA_MAC_VER_36,
 146         RTL_GIGA_MAC_VER_37,
 147         RTL_GIGA_MAC_VER_38,
 148         RTL_GIGA_MAC_VER_39,
 149         RTL_GIGA_MAC_VER_40,
 150         RTL_GIGA_MAC_VER_41,
 151         RTL_GIGA_MAC_VER_42,
 152         RTL_GIGA_MAC_VER_43,
 153         RTL_GIGA_MAC_VER_44,
 154         RTL_GIGA_MAC_VER_45,
 155         RTL_GIGA_MAC_VER_46,
 156         RTL_GIGA_MAC_VER_47,
 157         RTL_GIGA_MAC_VER_48,
 158         RTL_GIGA_MAC_VER_49,
 159         RTL_GIGA_MAC_VER_50,
 160         RTL_GIGA_MAC_VER_51,
 161         RTL_GIGA_MAC_NONE   = 0xff,
 162 };
 163
 164 enum rtl_tx_desc_version {
 165         RTL_TD_0        = 0,
 166         RTL_TD_1        = 1,
 167 };
 168
 169 #define JUMBO_1K        ETH_DATA_LEN
 170 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 171 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 172 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 173 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 174
 175 #define _R(NAME,TD,FW,SZ,B) {   \
 176         .name = NAME,           \
 177         .txd_version = TD,      \
 178         .fw_name = FW,          \
 179         .jumbo_max = SZ,        \
 180         .jumbo_tx_csum = B      \
 181 }
 182
 183 static const struct {
 184         const char *name;
 185         enum rtl_tx_desc_version txd_version;
 186         const char *fw_name;
 187         u16 jumbo_max;
 188         bool jumbo_tx_csum;
 189 } rtl_chip_infos[] = {
 190         /* PCI devices. */
 191         [RTL_GIGA_MAC_VER_01] =
 192                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K, true),
 193         [RTL_GIGA_MAC_VER_02] =
 194                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K, true),
 195         [RTL_GIGA_MAC_VER_03] =
 196                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K, true),
 197         [RTL_GIGA_MAC_VER_04] =
 198                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K, true),
 199         [RTL_GIGA_MAC_VER_05] =
 200                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 201         [RTL_GIGA_MAC_VER_06] =
 202                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 203         /* PCI-E devices. */
 204         [RTL_GIGA_MAC_VER_07] =
 205                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 206         [RTL_GIGA_MAC_VER_08] =
 207                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 208         [RTL_GIGA_MAC_VER_09] =
 209                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 210         [RTL_GIGA_MAC_VER_10] =
 211                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 212         [RTL_GIGA_MAC_VER_11] =
 213                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 214         [RTL_GIGA_MAC_VER_12] =
 215                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 216         [RTL_GIGA_MAC_VER_13] =
 217                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 218         [RTL_GIGA_MAC_VER_14] =
 219                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 220         [RTL_GIGA_MAC_VER_15] =
 221                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 222         [RTL_GIGA_MAC_VER_16] =
 223                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 224         [RTL_GIGA_MAC_VER_17] =
 225                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 226         [RTL_GIGA_MAC_VER_18] =
 227                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 228         [RTL_GIGA_MAC_VER_19] =
 229                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 230         [RTL_GIGA_MAC_VER_20] =
 231                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 232         [RTL_GIGA_MAC_VER_21] =
 233                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 234         [RTL_GIGA_MAC_VER_22] =
 235                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 236         [RTL_GIGA_MAC_VER_23] =
 237                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 238         [RTL_GIGA_MAC_VER_24] =
 239                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 240         [RTL_GIGA_MAC_VER_25] =
 241                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1,
 242                                                         JUMBO_9K, false),
 243         [RTL_GIGA_MAC_VER_26] =
 244                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2,
 245                                                         JUMBO_9K, false),
 246         [RTL_GIGA_MAC_VER_27] =
 247                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 248         [RTL_GIGA_MAC_VER_28] =
 249                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 250         [RTL_GIGA_MAC_VER_29] =
 251                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 252                                                         JUMBO_1K, true),
 253         [RTL_GIGA_MAC_VER_30] =
 254                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 255                                                         JUMBO_1K, true),
 256         [RTL_GIGA_MAC_VER_31] =
 257                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 258         [RTL_GIGA_MAC_VER_32] =
 259                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1,
 260                                                         JUMBO_9K, false),
 261         [RTL_GIGA_MAC_VER_33] =
 262                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2,
 263                                                         JUMBO_9K, false),
 264         [RTL_GIGA_MAC_VER_34] =
 265                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
 266                                                         JUMBO_9K, false),
 267         [RTL_GIGA_MAC_VER_35] =
 268                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1,
 269                                                         JUMBO_9K, false),
 270         [RTL_GIGA_MAC_VER_36] =
 271                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2,
 272                                                         JUMBO_9K, false),
 273         [RTL_GIGA_MAC_VER_37] =
 274                 _R("RTL8402",           RTL_TD_1, FIRMWARE_8402_1,
 275                                                         JUMBO_1K, true),
 276         [RTL_GIGA_MAC_VER_38] =
 277                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_1,
 278                                                         JUMBO_9K, false),
 279         [RTL_GIGA_MAC_VER_39] =
 280                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_1,
 281                                                         JUMBO_1K, true),
 282         [RTL_GIGA_MAC_VER_40] =
 283                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_2,
 284                                                         JUMBO_9K, false),
 285         [RTL_GIGA_MAC_VER_41] =
 286                 _R("RTL8168g/8111g",    RTL_TD_1, NULL, JUMBO_9K, false),
 287         [RTL_GIGA_MAC_VER_42] =
 288                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_3,
 289                                                         JUMBO_9K, false),
 290         [RTL_GIGA_MAC_VER_43] =
 291                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_2,
 292                                                         JUMBO_1K, true),
 293         [RTL_GIGA_MAC_VER_44] =
 294                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_2,
 295                                                         JUMBO_9K, false),
 296         [RTL_GIGA_MAC_VER_45] =
 297                 _R("RTL8168h/8111h",    RTL_TD_1, FIRMWARE_8168H_1,
 298                                                         JUMBO_9K, false),
 299         [RTL_GIGA_MAC_VER_46] =
 300                 _R("RTL8168h/8111h",    RTL_TD_1, FIRMWARE_8168H_2,
 301                                                         JUMBO_9K, false),
 302         [RTL_GIGA_MAC_VER_47] =
 303                 _R("RTL8107e",          RTL_TD_1, FIRMWARE_8107E_1,
 304                                                         JUMBO_1K, false),
 305         [RTL_GIGA_MAC_VER_48] =
 306                 _R("RTL8107e",          RTL_TD_1, FIRMWARE_8107E_2,
 307                                                         JUMBO_1K, false),
 308         [RTL_GIGA_MAC_VER_49] =
 309                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL,
 310                                                         JUMBO_9K, false),
 311         [RTL_GIGA_MAC_VER_50] =
 312                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL,
 313                                                         JUMBO_9K, false),
 314         [RTL_GIGA_MAC_VER_51] =
 315                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL,
 316                                                         JUMBO_9K, false),
 317 };
 318 #undef _R
 319
 320 enum cfg_version {
 321         RTL_CFG_0 = 0x00,
 322         RTL_CFG_1,
 323         RTL_CFG_2
 324 };
 325
 326 static const struct pci_device_id rtl8169_pci_tbl[] = {
 327         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 328         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 329         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8161), 0, 0, RTL_CFG_1 },
 330         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 331         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 332         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 333         { PCI_VENDOR_ID_DLINK,                  0x4300,
 334                 PCI_VENDOR_ID_DLINK, 0x4b10,             0, 0, RTL_CFG_1 },
 335         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 336         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 337         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 338         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 339         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 340                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 341         { 0x0001,                               0x8168,
 342                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 343         {0,},
 344 };
 345
 346 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 347
 348 static int rx_buf_sz = 16383;
 349 static int use_dac = -1;
 350 static struct {
 351         u32 msg_enable;
 352 } debug = { -1 };
 353
 354 enum rtl_registers {
 355         MAC0            = 0,    /* Ethernet hardware address. */
 356         MAC4            = 4,
 357         MAR0            = 8,    /* Multicast filter. */
 358         CounterAddrLow          = 0x10,
 359         CounterAddrHigh         = 0x14,
 360         TxDescStartAddrLow      = 0x20,
 361         TxDescStartAddrHigh     = 0x24,
 362         TxHDescStartAddrLow     = 0x28,
 363         TxHDescStartAddrHigh    = 0x2c,
 364         FLASH           = 0x30,
 365         ERSR            = 0x36,
 366         ChipCmd         = 0x37,
 367         TxPoll          = 0x38,
 368         IntrMask        = 0x3c,
 369         IntrStatus      = 0x3e,
 370
 371         TxConfig        = 0x40,
 372 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 373 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 374
 375         RxConfig        = 0x44,
 376 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 377 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 378 #define RXCFG_FIFO_SHIFT                13
 379                                         /* No threshold before first PCI xfer */
 380 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 381 #define RX_EARLY_OFF                    (1 << 11)
 382 #define RXCFG_DMA_SHIFT                 8
 383                                         /* Unlimited maximum PCI burst. */
 384 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 385
 386         RxMissed        = 0x4c,
 387         Cfg9346         = 0x50,
 388         Config0         = 0x51,
 389         Config1         = 0x52,
 390         Config2         = 0x53,
 391 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 392
 393         Config3         = 0x54,
 394         Config4         = 0x55,
 395         Config5         = 0x56,
 396         MultiIntr       = 0x5c,
 397         PHYAR           = 0x60,
 398         PHYstatus       = 0x6c,
 399         RxMaxSize       = 0xda,
 400         CPlusCmd        = 0xe0,
 401         IntrMitigate    = 0xe2,
 402
 403 #define RTL_COALESCE_MASK       0x0f
 404 #define RTL_COALESCE_SHIFT      4
 405 #define RTL_COALESCE_T_MAX      (RTL_COALESCE_MASK)
 406 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_MASK << 2)
 407
 408         RxDescAddrLow   = 0xe4,
 409         RxDescAddrHigh  = 0xe8,
 410         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 411
 412 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 413
 414         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 415
 416 #define TxPacketMax     (8064 >> 7)
 417 #define EarlySize       0x27
 418
 419         FuncEvent       = 0xf0,
 420         FuncEventMask   = 0xf4,
 421         FuncPresetState = 0xf8,
 422         IBCR0           = 0xf8,
 423         IBCR2           = 0xf9,
 424         IBIMR0          = 0xfa,
 425         IBISR0          = 0xfb,
 426         FuncForceEvent  = 0xfc,
 427 };
 428
 429 enum rtl8110_registers {
 430         TBICSR                  = 0x64,
 431         TBI_ANAR                = 0x68,
 432         TBI_LPAR                = 0x6a,
 433 };
 434
 435 enum rtl8168_8101_registers {
 436         CSIDR                   = 0x64,
 437         CSIAR                   = 0x68,
 438 #define CSIAR_FLAG                      0x80000000
 439 #define CSIAR_WRITE_CMD                 0x80000000
 440 #define CSIAR_BYTE_ENABLE               0x0f
 441 #define CSIAR_BYTE_ENABLE_SHIFT         12
 442 #define CSIAR_ADDR_MASK                 0x0fff
 443 #define CSIAR_FUNC_CARD                 0x00000000
 444 #define CSIAR_FUNC_SDIO                 0x00010000
 445 #define CSIAR_FUNC_NIC                  0x00020000
 446 #define CSIAR_FUNC_NIC2                 0x00010000
 447         PMCH                    = 0x6f,
 448         EPHYAR                  = 0x80,
 449 #define EPHYAR_FLAG                     0x80000000
 450 #define EPHYAR_WRITE_CMD                0x80000000
 451 #define EPHYAR_REG_MASK                 0x1f
 452 #define EPHYAR_REG_SHIFT                16
 453 #define EPHYAR_DATA_MASK                0xffff
 454         DLLPR                   = 0xd0,
 455 #define PFM_EN                          (1 << 6)
 456 #define TX_10M_PS_EN                    (1 << 7)
 457         DBG_REG                 = 0xd1,
 458 #define FIX_NAK_1                       (1 << 4)
 459 #define FIX_NAK_2                       (1 << 3)
 460         TWSI                    = 0xd2,
 461         MCU                     = 0xd3,
 462 #define NOW_IS_OOB                      (1 << 7)
 463 #define TX_EMPTY                        (1 << 5)
 464 #define RX_EMPTY                        (1 << 4)
 465 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 466 #define EN_NDP                          (1 << 3)
 467 #define EN_OOB_RESET                    (1 << 2)
 468 #define LINK_LIST_RDY                   (1 << 1)
 469         EFUSEAR                 = 0xdc,
 470 #define EFUSEAR_FLAG                    0x80000000
 471 #define EFUSEAR_WRITE_CMD               0x80000000
 472 #define EFUSEAR_READ_CMD                0x00000000
 473 #define EFUSEAR_REG_MASK                0x03ff
 474 #define EFUSEAR_REG_SHIFT               8
 475 #define EFUSEAR_DATA_MASK               0xff
 476         MISC_1                  = 0xf2,
 477 #define PFM_D3COLD_EN                   (1 << 6)
 478 };
 479
 480 enum rtl8168_registers {
 481         LED_FREQ                = 0x1a,
 482         EEE_LED                 = 0x1b,
 483         ERIDR                   = 0x70,
 484         ERIAR                   = 0x74,
 485 #define ERIAR_FLAG                      0x80000000
 486 #define ERIAR_WRITE_CMD                 0x80000000
 487 #define ERIAR_READ_CMD                  0x00000000
 488 #define ERIAR_ADDR_BYTE_ALIGN           4
 489 #define ERIAR_TYPE_SHIFT                16
 490 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 491 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 492 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 493 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 494 #define ERIAR_MASK_SHIFT                12
 495 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 496 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 497 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 498 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 499 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 500         EPHY_RXER_NUM           = 0x7c,
 501         OCPDR                   = 0xb0, /* OCP GPHY access */
 502 #define OCPDR_WRITE_CMD                 0x80000000
 503 #define OCPDR_READ_CMD                  0x00000000
 504 #define OCPDR_REG_MASK                  0x7f
 505 #define OCPDR_GPHY_REG_SHIFT            16
 506 #define OCPDR_DATA_MASK                 0xffff
 507         OCPAR                   = 0xb4,
 508 #define OCPAR_FLAG                      0x80000000
 509 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 510 #define OCPAR_GPHY_READ_CMD             0x0000f060
 511         GPHY_OCP                = 0xb8,
 512         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 513         MISC                    = 0xf0, /* 8168e only. */
 514 #define TXPLA_RST                       (1 << 29)
 515 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 516 #define PWM_EN                          (1 << 22)
 517 #define RXDV_GATED_EN                   (1 << 19)
 518 #define EARLY_TALLY_EN                  (1 << 16)
 519 };
 520
 521 enum rtl_register_content {
 522         /* InterruptStatusBits */
 523         SYSErr          = 0x8000,
 524         PCSTimeout      = 0x4000,
 525         SWInt           = 0x0100,
 526         TxDescUnavail   = 0x0080,
 527         RxFIFOOver      = 0x0040,
 528         LinkChg         = 0x0020,
 529         RxOverflow      = 0x0010,
 530         TxErr           = 0x0008,
 531         TxOK            = 0x0004,
 532         RxErr           = 0x0002,
 533         RxOK            = 0x0001,
 534
 535         /* RxStatusDesc */
 536         RxBOVF  = (1 << 24),
 537         RxFOVF  = (1 << 23),
 538         RxRWT   = (1 << 22),
 539         RxRES   = (1 << 21),
 540         RxRUNT  = (1 << 20),
 541         RxCRC   = (1 << 19),
 542
 543         /* ChipCmdBits */
 544         StopReq         = 0x80,
 545         CmdReset        = 0x10,
 546         CmdRxEnb        = 0x08,
 547         CmdTxEnb        = 0x04,
 548         RxBufEmpty      = 0x01,
 549
 550         /* TXPoll register p.5 */
 551         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 552         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 553         FSWInt          = 0x01,         /* Forced software interrupt */
 554
 555         /* Cfg9346Bits */
 556         Cfg9346_Lock    = 0x00,
 557         Cfg9346_Unlock  = 0xc0,
 558
 559         /* rx_mode_bits */
 560         AcceptErr       = 0x20,
 561         AcceptRunt      = 0x10,
 562         AcceptBroadcast = 0x08,
 563         AcceptMulticast = 0x04,
 564         AcceptMyPhys    = 0x02,
 565         AcceptAllPhys   = 0x01,
 566 #define RX_CONFIG_ACCEPT_MASK           0x3f
 567
 568         /* TxConfigBits */
 569         TxInterFrameGapShift = 24,
 570         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 571
 572         /* Config1 register p.24 */
 573         LEDS1           = (1 << 7),
 574         LEDS0           = (1 << 6),
 575         Speed_down      = (1 << 4),
 576         MEMMAP          = (1 << 3),
 577         IOMAP           = (1 << 2),
 578         VPD             = (1 << 1),
 579         PMEnable        = (1 << 0),     /* Power Management Enable */
 580
 581         /* Config2 register p. 25 */
 582         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 583         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 584         PCI_Clock_66MHz = 0x01,
 585         PCI_Clock_33MHz = 0x00,
 586
 587         /* Config3 register p.25 */
 588         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 589         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 590         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 591         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 592         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 593
 594         /* Config4 register */
 595         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 596
 597         /* Config5 register p.27 */
 598         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 599         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 600         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 601         Spi_en          = (1 << 3),
 602         LanWake         = (1 << 1),     /* LanWake enable/disable */
 603         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 604         ASPM_en         = (1 << 0),     /* ASPM enable */
 605
 606         /* TBICSR p.28 */
 607         TBIReset        = 0x80000000,
 608         TBILoopback     = 0x40000000,
 609         TBINwEnable     = 0x20000000,
 610         TBINwRestart    = 0x10000000,
 611         TBILinkOk       = 0x02000000,
 612         TBINwComplete   = 0x01000000,
 613
 614         /* CPlusCmd p.31 */
 615         EnableBist      = (1 << 15),    // 8168 8101
 616         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 617         Normal_mode     = (1 << 13),    // unused
 618         Force_half_dup  = (1 << 12),    // 8168 8101
 619         Force_rxflow_en = (1 << 11),    // 8168 8101
 620         Force_txflow_en = (1 << 10),    // 8168 8101
 621         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 622         ASF             = (1 << 8),     // 8168 8101
 623         PktCntrDisable  = (1 << 7),     // 8168 8101
 624         Mac_dbgo_sel    = 0x001c,       // 8168
 625         RxVlan          = (1 << 6),
 626         RxChkSum        = (1 << 5),
 627         PCIDAC          = (1 << 4),
 628         PCIMulRW        = (1 << 3),
 629         INTT_0          = 0x0000,       // 8168
 630         INTT_1          = 0x0001,       // 8168
 631         INTT_2          = 0x0002,       // 8168
 632         INTT_3          = 0x0003,       // 8168
 633
 634         /* rtl8169_PHYstatus */
 635         TBI_Enable      = 0x80,
 636         TxFlowCtrl      = 0x40,
 637         RxFlowCtrl      = 0x20,
 638         _1000bpsF       = 0x10,
 639         _100bps         = 0x08,
 640         _10bps          = 0x04,
 641         LinkStatus      = 0x02,
 642         FullDup         = 0x01,
 643
 644         /* _TBICSRBit */
 645         TBILinkOK       = 0x02000000,
 646
 647         /* ResetCounterCommand */
 648         CounterReset    = 0x1,
 649
 650         /* DumpCounterCommand */
 651         CounterDump     = 0x8,
 652
 653         /* magic enable v2 */
 654         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 655 };
 656
 657 enum rtl_desc_bit {
 658         /* First doubleword. */
 659         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 660         RingEnd         = (1 << 30), /* End of descriptor ring */
 661         FirstFrag       = (1 << 29), /* First segment of a packet */
 662         LastFrag        = (1 << 28), /* Final segment of a packet */
 663 };
 664
 665 /* Generic case. */
 666 enum rtl_tx_desc_bit {
 667         /* First doubleword. */
 668         TD_LSO          = (1 << 27),            /* Large Send Offload */
 669 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 670
 671         /* Second doubleword. */
 672         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 673 };
 674
 675 /* 8169, 8168b and 810x except 8102e. */
 676 enum rtl_tx_desc_bit_0 {
 677         /* First doubleword. */
 678 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 679         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 680         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 681         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 682 };
 683
 684 /* 8102e, 8168c and beyond. */
 685 enum rtl_tx_desc_bit_1 {
 686         /* First doubleword. */
 687         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 688         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 689 #define GTTCPHO_SHIFT                   18
 690 #define GTTCPHO_MAX                     0x7fU
 691
 692         /* Second doubleword. */
 693 #define TCPHO_SHIFT                     18
 694 #define TCPHO_MAX                       0x3ffU
 695 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 696         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 697         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 698         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 699         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 700 };
 701
 702 enum rtl_rx_desc_bit {
 703         /* Rx private */
 704         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 705         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 706
 707 #define RxProtoUDP      (PID1)
 708 #define RxProtoTCP      (PID0)
 709 #define RxProtoIP       (PID1 | PID0)
 710 #define RxProtoMask     RxProtoIP
 711
 712         IPFail          = (1 << 16), /* IP checksum failed */
 713         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 714         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 715         RxVlanTag       = (1 << 16), /* VLAN tag available */
 716 };
 717
 718 #define RsvdMask        0x3fffc000
 719
 720 struct TxDesc {
 721         __le32 opts1;
 722         __le32 opts2;
 723         __le64 addr;
 724 };
 725
 726 struct RxDesc {
 727         __le32 opts1;
 728         __le32 opts2;
 729         __le64 addr;
 730 };
 731
 732 struct ring_info {
 733         struct sk_buff  *skb;
 734         u32             len;
 735         u8              __pad[sizeof(void *) - sizeof(u32)];
 736 };
 737
 738 enum features {
 739         RTL_FEATURE_WOL         = (1 << 0),
 740         RTL_FEATURE_MSI         = (1 << 1),
 741         RTL_FEATURE_GMII        = (1 << 2),
 742 };
 743
 744 struct rtl8169_counters {
 745         __le64  tx_packets;
 746         __le64  rx_packets;
 747         __le64  tx_errors;
 748         __le32  rx_errors;
 749         __le16  rx_missed;
 750         __le16  align_errors;
 751         __le32  tx_one_collision;
 752         __le32  tx_multi_collision;
 753         __le64  rx_unicast;
 754         __le64  rx_broadcast;
 755         __le32  rx_multicast;
 756         __le16  tx_aborted;
 757         __le16  tx_underun;
 758 };
 759
 760 struct rtl8169_tc_offsets {
 761         bool    inited;
 762         __le64  tx_errors;
 763         __le32  tx_multi_collision;
 764         __le16  tx_aborted;
 765 };
 766
 767 enum rtl_flag {
 768         RTL_FLAG_TASK_ENABLED,
 769         RTL_FLAG_TASK_SLOW_PENDING,
 770         RTL_FLAG_TASK_RESET_PENDING,
 771         RTL_FLAG_TASK_PHY_PENDING,
 772         RTL_FLAG_MAX
 773 };
 774
 775 struct rtl8169_stats {
 776         u64                     packets;
 777         u64                     bytes;
 778         struct u64_stats_sync   syncp;
 779 };
 780
 781 struct rtl8169_private {
 782         void __iomem *mmio_addr;        /* memory map physical address */
 783         struct pci_dev *pci_dev;
 784         struct net_device *dev;
 785         struct napi_struct napi;
 786         u32 msg_enable;
 787         u16 txd_version;
 788         u16 mac_version;
 789         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 790         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 791         u32 dirty_tx;
 792         struct rtl8169_stats rx_stats;
 793         struct rtl8169_stats tx_stats;
 794         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 795         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 796         dma_addr_t TxPhyAddr;
 797         dma_addr_t RxPhyAddr;
 798         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 799         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 800         struct timer_list timer;
 801         u16 cp_cmd;
 802
 803         u16 event_slow;
 804         const struct rtl_coalesce_info *coalesce_info;
 805
 806         struct mdio_ops {
 807                 void (*write)(struct rtl8169_private *, int, int);
 808                 int (*read)(struct rtl8169_private *, int);
 809         } mdio_ops;
 810
 811         struct pll_power_ops {
 812                 void (*down)(struct rtl8169_private *);
 813                 void (*up)(struct rtl8169_private *);
 814         } pll_power_ops;
 815
 816         struct jumbo_ops {
 817                 void (*enable)(struct rtl8169_private *);
 818                 void (*disable)(struct rtl8169_private *);
 819         } jumbo_ops;
 820
 821         struct csi_ops {
 822                 void (*write)(struct rtl8169_private *, int, int);
 823                 u32 (*read)(struct rtl8169_private *, int);
 824         } csi_ops;
 825
 826         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 827         int (*get_link_ksettings)(struct net_device *,
 828                                   struct ethtool_link_ksettings *);
 829         void (*phy_reset_enable)(struct rtl8169_private *tp);
 830         void (*hw_start)(struct net_device *);
 831         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 832         unsigned int (*link_ok)(void __iomem *);
 833         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 834         bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
 835
 836         struct {
 837                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 838                 struct mutex mutex;
 839                 struct work_struct work;
 840         } wk;
 841
 842         unsigned features;
 843
 844         struct mii_if_info mii;
 845         dma_addr_t counters_phys_addr;
 846         struct rtl8169_counters *counters;
 847         struct rtl8169_tc_offsets tc_offset;
 848         u32 saved_wolopts;
 849         u32 opts1_mask;
 850
 851         struct rtl_fw {
 852                 const struct firmware *fw;
 853
 854 #define RTL_VER_SIZE            32
 855
 856                 char version[RTL_VER_SIZE];
 857
 858                 struct rtl_fw_phy_action {
 859                         __le32 *code;
 860                         size_t size;
 861                 } phy_action;
 862         } *rtl_fw;
 863 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 864
 865         u32 ocp_base;
 866 };
 867
 868 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 869 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 870 module_param(use_dac, int, 0);
 871 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 872 module_param_named(debug, debug.msg_enable, int, 0);
 873 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 874 MODULE_LICENSE("GPL");
 875 MODULE_VERSION(RTL8169_VERSION);
 876 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 877 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 878 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 879 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 880 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 881 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 882 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 883 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 884 MODULE_FIRMWARE(FIRMWARE_8402_1);
 885 MODULE_FIRMWARE(FIRMWARE_8411_1);
 886 MODULE_FIRMWARE(FIRMWARE_8411_2);
 887 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 888 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 889 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 890 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 891 MODULE_FIRMWARE(FIRMWARE_8168H_1);
 892 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 893 MODULE_FIRMWARE(FIRMWARE_8107E_1);
 894 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 895
 896 static void rtl_lock_work(struct rtl8169_private *tp)
 897 {
 898         mutex_lock(&tp->wk.mutex);
 899 }
 900
 901 static void rtl_unlock_work(struct rtl8169_private *tp)
 902 {
 903         mutex_unlock(&tp->wk.mutex);
 904 }
 905
 906 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
 907 {
 908         pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
 909                                            PCI_EXP_DEVCTL_READRQ, force);
 910 }
 911
 912 struct rtl_cond {
 913         bool (*check)(struct rtl8169_private *);
 914         const char *msg;
 915 };
 916
 917 static void rtl_udelay(unsigned int d)
 918 {
 919         udelay(d);
 920 }
 921
 922 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 923                           void (*delay)(unsigned int), unsigned int d, int n,
 924                           bool high)
 925 {
 926         int i;
 927
 928         for (i = 0; i < n; i++) {
 929                 delay(d);
 930                 if (c->check(tp) == high)
 931                         return true;
 932         }
 933         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 934                   c->msg, !high, n, d);
 935         return false;
 936 }
 937
 938 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 939                                       const struct rtl_cond *c,
 940                                       unsigned int d, int n)
 941 {
 942         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 943 }
 944
 945 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 946                                      const struct rtl_cond *c,
 947                                      unsigned int d, int n)
 948 {
 949         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 950 }
 951
 952 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 953                                       const struct rtl_cond *c,
 954                                       unsigned int d, int n)
 955 {
 956         return rtl_loop_wait(tp, c, msleep, d, n, true);
 957 }
 958
 959 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 960                                      const struct rtl_cond *c,
 961                                      unsigned int d, int n)
 962 {
 963         return rtl_loop_wait(tp, c, msleep, d, n, false);
 964 }
 965
 966 #define DECLARE_RTL_COND(name)                          \
 967 static bool name ## _check(struct rtl8169_private *);   \
 968                                                         \
 969 static const struct rtl_cond name = {                   \
 970         .check  = name ## _check,                       \
 971         .msg    = #name                                 \
 972 };                                                      \
 973                                                         \
 974 static bool name ## _check(struct rtl8169_private *tp)
 975
 976 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 977 {
 978         if (reg & 0xffff0001) {
 979                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 980                 return true;
 981         }
 982         return false;
 983 }
 984
 985 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 986 {
 987         void __iomem *ioaddr = tp->mmio_addr;
 988
 989         return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
 990 }
 991
 992 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 993 {
 994         void __iomem *ioaddr = tp->mmio_addr;
 995
 996         if (rtl_ocp_reg_failure(tp, reg))
 997                 return;
 998
 999         RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
1000
1001         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
1002 }
1003
1004 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1005 {
1006         void __iomem *ioaddr = tp->mmio_addr;
1007
1008         if (rtl_ocp_reg_failure(tp, reg))
1009                 return 0;
1010
1011         RTL_W32(GPHY_OCP, reg << 15);
1012
1013         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1014                 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1015 }
1016
1017 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1018 {
1019         void __iomem *ioaddr = tp->mmio_addr;
1020
1021         if (rtl_ocp_reg_failure(tp, reg))
1022                 return;
1023
1024         RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
1025 }
1026
1027 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1028 {
1029         void __iomem *ioaddr = tp->mmio_addr;
1030
1031         if (rtl_ocp_reg_failure(tp, reg))
1032                 return 0;
1033
1034         RTL_W32(OCPDR, reg << 15);
1035
1036         return RTL_R32(OCPDR);
1037 }
1038
1039 #define OCP_STD_PHY_BASE        0xa400
1040
1041 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1042 {
1043         if (reg == 0x1f) {
1044                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1045                 return;
1046         }
1047
1048         if (tp->ocp_base != OCP_STD_PHY_BASE)
1049                 reg -= 0x10;
1050
1051         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1052 }
1053
1054 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1055 {
1056         if (tp->ocp_base != OCP_STD_PHY_BASE)
1057                 reg -= 0x10;
1058
1059         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1060 }
1061
1062 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1063 {
1064         if (reg == 0x1f) {
1065                 tp->ocp_base = value << 4;
1066                 return;
1067         }
1068
1069         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1070 }
1071
1072 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1073 {
1074         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1075 }
1076
1077 DECLARE_RTL_COND(rtl_phyar_cond)
1078 {
1079         void __iomem *ioaddr = tp->mmio_addr;
1080
1081         return RTL_R32(PHYAR) & 0x80000000;
1082 }
1083
1084 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1085 {
1086         void __iomem *ioaddr = tp->mmio_addr;
1087
1088         RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1089
1090         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1091         /*
1092          * According to hardware specs a 20us delay is required after write
1093          * complete indication, but before sending next command.
1094          */
1095         udelay(20);
1096 }
1097
1098 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1099 {
1100         void __iomem *ioaddr = tp->mmio_addr;
1101         int value;
1102
1103         RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1104
1105         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1106                 RTL_R32(PHYAR) & 0xffff : ~0;
1107
1108         /*
1109          * According to hardware specs a 20us delay is required after read
1110          * complete indication, but before sending next command.
1111          */
1112         udelay(20);
1113
1114         return value;
1115 }
1116
1117 DECLARE_RTL_COND(rtl_ocpar_cond)
1118 {
1119         void __iomem *ioaddr = tp->mmio_addr;
1120
1121         return RTL_R32(OCPAR) & OCPAR_FLAG;
1122 }
1123
1124 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1125 {
1126         void __iomem *ioaddr = tp->mmio_addr;
1127
1128         RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1129         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1130         RTL_W32(EPHY_RXER_NUM, 0);
1131
1132         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1133 }
1134
1135 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1136 {
1137         r8168dp_1_mdio_access(tp, reg,
1138                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1139 }
1140
1141 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1142 {
1143         void __iomem *ioaddr = tp->mmio_addr;
1144
1145         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1146
1147         mdelay(1);
1148         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1149         RTL_W32(EPHY_RXER_NUM, 0);
1150
1151         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1152                 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
1153 }
1154
1155 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
1156
1157 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1158 {
1159         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1160 }
1161
1162 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1163 {
1164         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1165 }
1166
1167 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1168 {
1169         void __iomem *ioaddr = tp->mmio_addr;
1170
1171         r8168dp_2_mdio_start(ioaddr);
1172
1173         r8169_mdio_write(tp, reg, value);
1174
1175         r8168dp_2_mdio_stop(ioaddr);
1176 }
1177
1178 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1179 {
1180         void __iomem *ioaddr = tp->mmio_addr;
1181         int value;
1182
1183         r8168dp_2_mdio_start(ioaddr);
1184
1185         value = r8169_mdio_read(tp, reg);
1186
1187         r8168dp_2_mdio_stop(ioaddr);
1188
1189         return value;
1190 }
1191
1192 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1193 {
1194         tp->mdio_ops.write(tp, location, val);
1195 }
1196
1197 static int rtl_readphy(struct rtl8169_private *tp, int location)
1198 {
1199         return tp->mdio_ops.read(tp, location);
1200 }
1201
1202 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1203 {
1204         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1205 }
1206
1207 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1208 {
1209         int val;
1210
1211         val = rtl_readphy(tp, reg_addr);
1212         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1213 }
1214
1215 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1216                            int val)
1217 {
1218         struct rtl8169_private *tp = netdev_priv(dev);
1219
1220         rtl_writephy(tp, location, val);
1221 }
1222
1223 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1224 {
1225         struct rtl8169_private *tp = netdev_priv(dev);
1226
1227         return rtl_readphy(tp, location);
1228 }
1229
1230 DECLARE_RTL_COND(rtl_ephyar_cond)
1231 {
1232         void __iomem *ioaddr = tp->mmio_addr;
1233
1234         return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1235 }
1236
1237 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1238 {
1239         void __iomem *ioaddr = tp->mmio_addr;
1240
1241         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1242                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1243
1244         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1245
1246         udelay(10);
1247 }
1248
1249 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1250 {
1251         void __iomem *ioaddr = tp->mmio_addr;
1252
1253         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1254
1255         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1256                 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
1257 }
1258
1259 DECLARE_RTL_COND(rtl_eriar_cond)
1260 {
1261         void __iomem *ioaddr = tp->mmio_addr;
1262
1263         return RTL_R32(ERIAR) & ERIAR_FLAG;
1264 }
1265
1266 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1267                           u32 val, int type)
1268 {
1269         void __iomem *ioaddr = tp->mmio_addr;
1270
1271         BUG_ON((addr & 3) || (mask == 0));
1272         RTL_W32(ERIDR, val);
1273         RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1274
1275         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1276 }
1277
1278 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1279 {
1280         void __iomem *ioaddr = tp->mmio_addr;
1281
1282         RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1283
1284         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1285                 RTL_R32(ERIDR) : ~0;
1286 }
1287
1288 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1289                          u32 m, int type)
1290 {
1291         u32 val;
1292
1293         val = rtl_eri_read(tp, addr, type);
1294         rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1295 }
1296
1297 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1298 {
1299         void __iomem *ioaddr = tp->mmio_addr;
1300
1301         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1302         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1303                 RTL_R32(OCPDR) : ~0;
1304 }
1305
1306 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1307 {
1308         return rtl_eri_read(tp, reg, ERIAR_OOB);
1309 }
1310
1311 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1312 {
1313         switch (tp->mac_version) {
1314         case RTL_GIGA_MAC_VER_27:
1315         case RTL_GIGA_MAC_VER_28:
1316         case RTL_GIGA_MAC_VER_31:
1317                 return r8168dp_ocp_read(tp, mask, reg);
1318         case RTL_GIGA_MAC_VER_49:
1319         case RTL_GIGA_MAC_VER_50:
1320         case RTL_GIGA_MAC_VER_51:
1321                 return r8168ep_ocp_read(tp, mask, reg);
1322         default:
1323                 BUG();
1324                 return ~0;
1325         }
1326 }
1327
1328 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1329                               u32 data)
1330 {
1331         void __iomem *ioaddr = tp->mmio_addr;
1332
1333         RTL_W32(OCPDR, data);
1334         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1335         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1336 }
1337
1338 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1339                               u32 data)
1340 {
1341         rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1342                       data, ERIAR_OOB);
1343 }
1344
1345 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1346 {
1347         switch (tp->mac_version) {
1348         case RTL_GIGA_MAC_VER_27:
1349         case RTL_GIGA_MAC_VER_28:
1350         case RTL_GIGA_MAC_VER_31:
1351                 r8168dp_ocp_write(tp, mask, reg, data);
1352                 break;
1353         case RTL_GIGA_MAC_VER_49:
1354         case RTL_GIGA_MAC_VER_50:
1355         case RTL_GIGA_MAC_VER_51:
1356                 r8168ep_ocp_write(tp, mask, reg, data);
1357                 break;
1358         default:
1359                 BUG();
1360                 break;
1361         }
1362 }
1363
1364 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1365 {
1366         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1367
1368         ocp_write(tp, 0x1, 0x30, 0x00000001);
1369 }
1370
1371 #define OOB_CMD_RESET           0x00
1372 #define OOB_CMD_DRIVER_START    0x05
1373 #define OOB_CMD_DRIVER_STOP     0x06
1374
1375 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1376 {
1377         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1378 }
1379
1380 DECLARE_RTL_COND(rtl_ocp_read_cond)
1381 {
1382         u16 reg;
1383
1384         reg = rtl8168_get_ocp_reg(tp);
1385
1386         return ocp_read(tp, 0x0f, reg) & 0x00000800;
1387 }
1388
1389 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1390 {
1391         return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1392 }
1393
1394 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1395 {
1396         void __iomem *ioaddr = tp->mmio_addr;
1397
1398         return RTL_R8(IBISR0) & 0x02;
1399 }
1400
1401 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1402 {
1403         void __iomem *ioaddr = tp->mmio_addr;
1404
1405         RTL_W8(IBCR2, RTL_R8(IBCR2) & ~0x01);
1406         rtl_msleep_loop_wait_low(tp, &rtl_ocp_tx_cond, 50, 2000);
1407         RTL_W8(IBISR0, RTL_R8(IBISR0) | 0x20);
1408         RTL_W8(IBCR0, RTL_R8(IBCR0) & ~0x01);
1409 }
1410
1411 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1412 {
1413         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1414         rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1415 }
1416
1417 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1418 {
1419         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1420         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1421         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1422 }
1423
1424 static void rtl8168_driver_start(struct rtl8169_private *tp)
1425 {
1426         switch (tp->mac_version) {
1427         case RTL_GIGA_MAC_VER_27:
1428         case RTL_GIGA_MAC_VER_28:
1429         case RTL_GIGA_MAC_VER_31:
1430                 rtl8168dp_driver_start(tp);
1431                 break;
1432         case RTL_GIGA_MAC_VER_49:
1433         case RTL_GIGA_MAC_VER_50:
1434         case RTL_GIGA_MAC_VER_51:
1435                 rtl8168ep_driver_start(tp);
1436                 break;
1437         default:
1438                 BUG();
1439                 break;
1440         }
1441 }
1442
1443 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1444 {
1445         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1446         rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1447 }
1448
1449 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1450 {
1451         rtl8168ep_stop_cmac(tp);
1452         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1453         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1454         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1455 }
1456
1457 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1458 {
1459         switch (tp->mac_version) {
1460         case RTL_GIGA_MAC_VER_27:
1461         case RTL_GIGA_MAC_VER_28:
1462         case RTL_GIGA_MAC_VER_31:
1463                 rtl8168dp_driver_stop(tp);
1464                 break;
1465         case RTL_GIGA_MAC_VER_49:
1466         case RTL_GIGA_MAC_VER_50:
1467         case RTL_GIGA_MAC_VER_51:
1468                 rtl8168ep_driver_stop(tp);
1469                 break;
1470         default:
1471                 BUG();
1472                 break;
1473         }
1474 }
1475
1476 static int r8168dp_check_dash(struct rtl8169_private *tp)
1477 {
1478         u16 reg = rtl8168_get_ocp_reg(tp);
1479
1480         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
1481 }
1482
1483 static int r8168ep_check_dash(struct rtl8169_private *tp)
1484 {
1485         return (ocp_read(tp, 0x0f, 0x128) & 0x00000001) ? 1 : 0;
1486 }
1487
1488 static int r8168_check_dash(struct rtl8169_private *tp)
1489 {
1490         switch (tp->mac_version) {
1491         case RTL_GIGA_MAC_VER_27:
1492         case RTL_GIGA_MAC_VER_28:
1493         case RTL_GIGA_MAC_VER_31:
1494                 return r8168dp_check_dash(tp);
1495         case RTL_GIGA_MAC_VER_49:
1496         case RTL_GIGA_MAC_VER_50:
1497         case RTL_GIGA_MAC_VER_51:
1498                 return r8168ep_check_dash(tp);
1499         default:
1500                 return 0;
1501         }
1502 }
1503
1504 struct exgmac_reg {
1505         u16 addr;
1506         u16 mask;
1507         u32 val;
1508 };
1509
1510 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1511                                    const struct exgmac_reg *r, int len)
1512 {
1513         while (len-- > 0) {
1514                 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1515                 r++;
1516         }
1517 }
1518
1519 DECLARE_RTL_COND(rtl_efusear_cond)
1520 {
1521         void __iomem *ioaddr = tp->mmio_addr;
1522
1523         return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1524 }
1525
1526 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1527 {
1528         void __iomem *ioaddr = tp->mmio_addr;
1529
1530         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1531
1532         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1533                 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1534 }
1535
1536 static u16 rtl_get_events(struct rtl8169_private *tp)
1537 {
1538         void __iomem *ioaddr = tp->mmio_addr;
1539
1540         return RTL_R16(IntrStatus);
1541 }
1542
1543 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1544 {
1545         void __iomem *ioaddr = tp->mmio_addr;
1546
1547         RTL_W16(IntrStatus, bits);
1548         mmiowb();
1549 }
1550
1551 static void rtl_irq_disable(struct rtl8169_private *tp)
1552 {
1553         void __iomem *ioaddr = tp->mmio_addr;
1554
1555         RTL_W16(IntrMask, 0);
1556         mmiowb();
1557 }
1558
1559 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1560 {
1561         void __iomem *ioaddr = tp->mmio_addr;
1562
1563         RTL_W16(IntrMask, bits);
1564 }
1565
1566 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1567 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1568 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1569
1570 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1571 {
1572         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1573 }
1574
1575 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1576 {
1577         void __iomem *ioaddr = tp->mmio_addr;
1578
1579         rtl_irq_disable(tp);
1580         rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1581         RTL_R8(ChipCmd);
1582 }
1583
1584 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1585 {
1586         void __iomem *ioaddr = tp->mmio_addr;
1587
1588         return RTL_R32(TBICSR) & TBIReset;
1589 }
1590
1591 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1592 {
1593         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1594 }
1595
1596 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1597 {
1598         return RTL_R32(TBICSR) & TBILinkOk;
1599 }
1600
1601 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1602 {
1603         return RTL_R8(PHYstatus) & LinkStatus;
1604 }
1605
1606 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1607 {
1608         void __iomem *ioaddr = tp->mmio_addr;
1609
1610         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1611 }
1612
1613 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1614 {
1615         unsigned int val;
1616
1617         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1618         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1619 }
1620
1621 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1622 {
1623         void __iomem *ioaddr = tp->mmio_addr;
1624         struct net_device *dev = tp->dev;
1625
1626         if (!netif_running(dev))
1627                 return;
1628
1629         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1630             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1631                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1632                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1633                                       ERIAR_EXGMAC);
1634                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1635                                       ERIAR_EXGMAC);
1636                 } else if (RTL_R8(PHYstatus) & _100bps) {
1637                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1638                                       ERIAR_EXGMAC);
1639                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1640                                       ERIAR_EXGMAC);
1641                 } else {
1642                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1643                                       ERIAR_EXGMAC);
1644                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1645                                       ERIAR_EXGMAC);
1646                 }
1647                 /* Reset packet filter */
1648                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1649                              ERIAR_EXGMAC);
1650                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1651                              ERIAR_EXGMAC);
1652         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1653                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1654                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1655                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1656                                       ERIAR_EXGMAC);
1657                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1658                                       ERIAR_EXGMAC);
1659                 } else {
1660                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1661                                       ERIAR_EXGMAC);
1662                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1663                                       ERIAR_EXGMAC);
1664                 }
1665         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1666                 if (RTL_R8(PHYstatus) & _10bps) {
1667                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1668                                       ERIAR_EXGMAC);
1669                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1670                                       ERIAR_EXGMAC);
1671                 } else {
1672                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1673                                       ERIAR_EXGMAC);
1674                 }
1675         }
1676 }
1677
1678 static void __rtl8169_check_link_status(struct net_device *dev,
1679                                         struct rtl8169_private *tp,
1680                                         void __iomem *ioaddr, bool pm)
1681 {
1682         if (tp->link_ok(ioaddr)) {
1683                 rtl_link_chg_patch(tp);
1684                 /* This is to cancel a scheduled suspend if there's one. */
1685                 if (pm)
1686                         pm_request_resume(&tp->pci_dev->dev);
1687                 netif_carrier_on(dev);
1688                 if (net_ratelimit())
1689                         netif_info(tp, ifup, dev, "link up\n");
1690         } else {
1691                 netif_carrier_off(dev);
1692                 netif_info(tp, ifdown, dev, "link down\n");
1693                 if (pm)
1694                         pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1695         }
1696 }
1697
1698 static void rtl8169_check_link_status(struct net_device *dev,
1699                                       struct rtl8169_private *tp,
1700                                       void __iomem *ioaddr)
1701 {
1702         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1703 }
1704
1705 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1706
1707 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1708 {
1709         void __iomem *ioaddr = tp->mmio_addr;
1710         u8 options;
1711         u32 wolopts = 0;
1712
1713         options = RTL_R8(Config1);
1714         if (!(options & PMEnable))
1715                 return 0;
1716
1717         options = RTL_R8(Config3);
1718         if (options & LinkUp)
1719                 wolopts |= WAKE_PHY;
1720         switch (tp->mac_version) {
1721         case RTL_GIGA_MAC_VER_34:
1722         case RTL_GIGA_MAC_VER_35:
1723         case RTL_GIGA_MAC_VER_36:
1724         case RTL_GIGA_MAC_VER_37:
1725         case RTL_GIGA_MAC_VER_38:
1726         case RTL_GIGA_MAC_VER_40:
1727         case RTL_GIGA_MAC_VER_41:
1728         case RTL_GIGA_MAC_VER_42:
1729         case RTL_GIGA_MAC_VER_43:
1730         case RTL_GIGA_MAC_VER_44:
1731         case RTL_GIGA_MAC_VER_45:
1732         case RTL_GIGA_MAC_VER_46:
1733         case RTL_GIGA_MAC_VER_47:
1734         case RTL_GIGA_MAC_VER_48:
1735         case RTL_GIGA_MAC_VER_49:
1736         case RTL_GIGA_MAC_VER_50:
1737         case RTL_GIGA_MAC_VER_51:
1738                 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1739                         wolopts |= WAKE_MAGIC;
1740                 break;
1741         default:
1742                 if (options & MagicPacket)
1743                         wolopts |= WAKE_MAGIC;
1744                 break;
1745         }
1746
1747         options = RTL_R8(Config5);
1748         if (options & UWF)
1749                 wolopts |= WAKE_UCAST;
1750         if (options & BWF)
1751                 wolopts |= WAKE_BCAST;
1752         if (options & MWF)
1753                 wolopts |= WAKE_MCAST;
1754
1755         return wolopts;
1756 }
1757
1758 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1759 {
1760         struct rtl8169_private *tp = netdev_priv(dev);
1761         struct device *d = &tp->pci_dev->dev;
1762
1763         pm_runtime_get_noresume(d);
1764
1765         rtl_lock_work(tp);
1766
1767         wol->supported = WAKE_ANY;
1768         if (pm_runtime_active(d))
1769                 wol->wolopts = __rtl8169_get_wol(tp);
1770         else
1771                 wol->wolopts = tp->saved_wolopts;
1772
1773         rtl_unlock_work(tp);
1774
1775         pm_runtime_put_noidle(d);
1776 }
1777
1778 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1779 {
1780         void __iomem *ioaddr = tp->mmio_addr;
1781         unsigned int i, tmp;
1782         static const struct {
1783                 u32 opt;
1784                 u16 reg;
1785                 u8  mask;
1786         } cfg[] = {
1787                 { WAKE_PHY,   Config3, LinkUp },
1788                 { WAKE_UCAST, Config5, UWF },
1789                 { WAKE_BCAST, Config5, BWF },
1790                 { WAKE_MCAST, Config5, MWF },
1791                 { WAKE_ANY,   Config5, LanWake },
1792                 { WAKE_MAGIC, Config3, MagicPacket }
1793         };
1794         u8 options;
1795
1796         RTL_W8(Cfg9346, Cfg9346_Unlock);
1797
1798         switch (tp->mac_version) {
1799         case RTL_GIGA_MAC_VER_34:
1800         case RTL_GIGA_MAC_VER_35:
1801         case RTL_GIGA_MAC_VER_36:
1802         case RTL_GIGA_MAC_VER_37:
1803         case RTL_GIGA_MAC_VER_38:
1804         case RTL_GIGA_MAC_VER_40:
1805         case RTL_GIGA_MAC_VER_41:
1806         case RTL_GIGA_MAC_VER_42:
1807         case RTL_GIGA_MAC_VER_43:
1808         case RTL_GIGA_MAC_VER_44:
1809         case RTL_GIGA_MAC_VER_45:
1810         case RTL_GIGA_MAC_VER_46:
1811         case RTL_GIGA_MAC_VER_47:
1812         case RTL_GIGA_MAC_VER_48:
1813         case RTL_GIGA_MAC_VER_49:
1814         case RTL_GIGA_MAC_VER_50:
1815         case RTL_GIGA_MAC_VER_51:
1816                 tmp = ARRAY_SIZE(cfg) - 1;
1817                 if (wolopts & WAKE_MAGIC)
1818                         rtl_w0w1_eri(tp,
1819                                      0x0dc,
1820                                      ERIAR_MASK_0100,
1821                                      MagicPacket_v2,
1822                                      0x0000,
1823                                      ERIAR_EXGMAC);
1824                 else
1825                         rtl_w0w1_eri(tp,
1826                                      0x0dc,
1827                                      ERIAR_MASK_0100,
1828                                      0x0000,
1829                                      MagicPacket_v2,
1830                                      ERIAR_EXGMAC);
1831                 break;
1832         default:
1833                 tmp = ARRAY_SIZE(cfg);
1834                 break;
1835         }
1836
1837         for (i = 0; i < tmp; i++) {
1838                 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1839                 if (wolopts & cfg[i].opt)
1840                         options |= cfg[i].mask;
1841                 RTL_W8(cfg[i].reg, options);
1842         }
1843
1844         switch (tp->mac_version) {
1845         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1846                 options = RTL_R8(Config1) & ~PMEnable;
1847                 if (wolopts)
1848                         options |= PMEnable;
1849                 RTL_W8(Config1, options);
1850                 break;
1851         default:
1852                 options = RTL_R8(Config2) & ~PME_SIGNAL;
1853                 if (wolopts)
1854                         options |= PME_SIGNAL;
1855                 RTL_W8(Config2, options);
1856                 break;
1857         }
1858
1859         RTL_W8(Cfg9346, Cfg9346_Lock);
1860 }
1861
1862 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1863 {
1864         struct rtl8169_private *tp = netdev_priv(dev);
1865         struct device *d = &tp->pci_dev->dev;
1866
1867         pm_runtime_get_noresume(d);
1868
1869         rtl_lock_work(tp);
1870
1871         if (wol->wolopts)
1872                 tp->features |= RTL_FEATURE_WOL;
1873         else
1874                 tp->features &= ~RTL_FEATURE_WOL;
1875         if (pm_runtime_active(d))
1876                 __rtl8169_set_wol(tp, wol->wolopts);
1877         else
1878                 tp->saved_wolopts = wol->wolopts;
1879
1880         rtl_unlock_work(tp);
1881
1882         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1883
1884         pm_runtime_put_noidle(d);
1885
1886         return 0;
1887 }
1888
1889 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1890 {
1891         return rtl_chip_infos[tp->mac_version].fw_name;
1892 }
1893
1894 static void rtl8169_get_drvinfo(struct net_device *dev,
1895                                 struct ethtool_drvinfo *info)
1896 {
1897         struct rtl8169_private *tp = netdev_priv(dev);
1898         struct rtl_fw *rtl_fw = tp->rtl_fw;
1899
1900         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1901         strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1902         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1903         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1904         if (!IS_ERR_OR_NULL(rtl_fw))
1905                 strlcpy(info->fw_version, rtl_fw->version,
1906                         sizeof(info->fw_version));
1907 }
1908
1909 static int rtl8169_get_regs_len(struct net_device *dev)
1910 {
1911         return R8169_REGS_SIZE;
1912 }
1913
1914 static int rtl8169_set_speed_tbi(struct net_device *dev,
1915                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1916 {
1917         struct rtl8169_private *tp = netdev_priv(dev);
1918         void __iomem *ioaddr = tp->mmio_addr;
1919         int ret = 0;
1920         u32 reg;
1921
1922         reg = RTL_R32(TBICSR);
1923         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1924             (duplex == DUPLEX_FULL)) {
1925                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1926         } else if (autoneg == AUTONEG_ENABLE)
1927                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1928         else {
1929                 netif_warn(tp, link, dev,
1930                            "incorrect speed setting refused in TBI mode\n");
1931                 ret = -EOPNOTSUPP;
1932         }
1933
1934         return ret;
1935 }
1936
1937 static int rtl8169_set_speed_xmii(struct net_device *dev,
1938                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1939 {
1940         struct rtl8169_private *tp = netdev_priv(dev);
1941         int giga_ctrl, bmcr;
1942         int rc = -EINVAL;
1943
1944         rtl_writephy(tp, 0x1f, 0x0000);
1945
1946         if (autoneg == AUTONEG_ENABLE) {
1947                 int auto_nego;
1948
1949                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1950                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1951                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1952
1953                 if (adv & ADVERTISED_10baseT_Half)
1954                         auto_nego |= ADVERTISE_10HALF;
1955                 if (adv & ADVERTISED_10baseT_Full)
1956                         auto_nego |= ADVERTISE_10FULL;
1957                 if (adv & ADVERTISED_100baseT_Half)
1958                         auto_nego |= ADVERTISE_100HALF;
1959                 if (adv & ADVERTISED_100baseT_Full)
1960                         auto_nego |= ADVERTISE_100FULL;
1961
1962                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1963
1964                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1965                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1966
1967                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1968                 if (tp->mii.supports_gmii) {
1969                         if (adv & ADVERTISED_1000baseT_Half)
1970                                 giga_ctrl |= ADVERTISE_1000HALF;
1971                         if (adv & ADVERTISED_1000baseT_Full)
1972                                 giga_ctrl |= ADVERTISE_1000FULL;
1973                 } else if (adv & (ADVERTISED_1000baseT_Half |
1974                                   ADVERTISED_1000baseT_Full)) {
1975                         netif_info(tp, link, dev,
1976                                    "PHY does not support 1000Mbps\n");
1977                         goto out;
1978                 }
1979
1980                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1981
1982                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1983                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1984         } else {
1985                 if (speed == SPEED_10)
1986                         bmcr = 0;
1987                 else if (speed == SPEED_100)
1988                         bmcr = BMCR_SPEED100;
1989                 else
1990                         goto out;
1991
1992                 if (duplex == DUPLEX_FULL)
1993                         bmcr |= BMCR_FULLDPLX;
1994         }
1995
1996         rtl_writephy(tp, MII_BMCR, bmcr);
1997
1998         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1999             tp->mac_version == RTL_GIGA_MAC_VER_03) {
2000                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
2001                         rtl_writephy(tp, 0x17, 0x2138);
2002                         rtl_writephy(tp, 0x0e, 0x0260);
2003                 } else {
2004                         rtl_writephy(tp, 0x17, 0x2108);
2005                         rtl_writephy(tp, 0x0e, 0x0000);
2006                 }
2007         }
2008
2009         rc = 0;
2010 out:
2011         return rc;
2012 }
2013
2014 static int rtl8169_set_speed(struct net_device *dev,
2015                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
2016 {
2017         struct rtl8169_private *tp = netdev_priv(dev);
2018         int ret;
2019
2020         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
2021         if (ret < 0)
2022                 goto out;
2023
2024         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
2025             (advertising & ADVERTISED_1000baseT_Full) &&
2026             !pci_is_pcie(tp->pci_dev)) {
2027                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
2028         }
2029 out:
2030         return ret;
2031 }
2032
2033 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
2034         netdev_features_t features)
2035 {
2036         struct rtl8169_private *tp = netdev_priv(dev);
2037
2038         if (dev->mtu > TD_MSS_MAX)
2039                 features &= ~NETIF_F_ALL_TSO;
2040
2041         if (dev->mtu > JUMBO_1K &&
2042             !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
2043                 features &= ~NETIF_F_IP_CSUM;
2044
2045         return features;
2046 }
2047
2048 static void __rtl8169_set_features(struct net_device *dev,
2049                                    netdev_features_t features)
2050 {
2051         struct rtl8169_private *tp = netdev_priv(dev);
2052         void __iomem *ioaddr = tp->mmio_addr;
2053         u32 rx_config;
2054
2055         rx_config = RTL_R32(RxConfig);
2056         if (features & NETIF_F_RXALL)
2057                 rx_config |= (AcceptErr | AcceptRunt);
2058         else
2059                 rx_config &= ~(AcceptErr | AcceptRunt);
2060
2061         RTL_W32(RxConfig, rx_config);
2062
2063         if (features & NETIF_F_RXCSUM)
2064                 tp->cp_cmd |= RxChkSum;
2065         else
2066                 tp->cp_cmd &= ~RxChkSum;
2067
2068         if (features & NETIF_F_HW_VLAN_CTAG_RX)
2069                 tp->cp_cmd |= RxVlan;
2070         else
2071                 tp->cp_cmd &= ~RxVlan;
2072
2073         tp->cp_cmd |= RTL_R16(CPlusCmd) & ~(RxVlan | RxChkSum);
2074
2075         RTL_W16(CPlusCmd, tp->cp_cmd);
2076         RTL_R16(CPlusCmd);
2077 }
2078
2079 static int rtl8169_set_features(struct net_device *dev,
2080                                 netdev_features_t features)
2081 {
2082         struct rtl8169_private *tp = netdev_priv(dev);
2083
2084         features &= NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX;
2085
2086         rtl_lock_work(tp);
2087         if (features ^ dev->features)
2088                 __rtl8169_set_features(dev, features);
2089         rtl_unlock_work(tp);
2090
2091         return 0;
2092 }
2093
2094
2095 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
2096 {
2097         return (skb_vlan_tag_present(skb)) ?
2098                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
2099 }
2100
2101 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
2102 {
2103         u32 opts2 = le32_to_cpu(desc->opts2);
2104
2105         if (opts2 & RxVlanTag)
2106                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
2107 }
2108
2109 static int rtl8169_get_link_ksettings_tbi(struct net_device *dev,
2110                                           struct ethtool_link_ksettings *cmd)
2111 {
2112         struct rtl8169_private *tp = netdev_priv(dev);
2113         void __iomem *ioaddr = tp->mmio_addr;
2114         u32 status;
2115         u32 supported, advertising;
2116
2117         supported =
2118                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
2119         cmd->base.port = PORT_FIBRE;
2120
2121         status = RTL_R32(TBICSR);
2122         advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
2123         cmd->base.autoneg = !!(status & TBINwEnable);
2124
2125         cmd->base.speed = SPEED_1000;
2126         cmd->base.duplex = DUPLEX_FULL; /* Always set */
2127
2128         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
2129                                                 supported);
2130         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
2131                                                 advertising);
2132
2133         return 0;
2134 }
2135
2136 static int rtl8169_get_link_ksettings_xmii(struct net_device *dev,
2137                                            struct ethtool_link_ksettings *cmd)
2138 {
2139         struct rtl8169_private *tp = netdev_priv(dev);
2140
2141         mii_ethtool_get_link_ksettings(&tp->mii, cmd);
2142
2143         return 0;
2144 }
2145
2146 static int rtl8169_get_link_ksettings(struct net_device *dev,
2147                                       struct ethtool_link_ksettings *cmd)
2148 {
2149         struct rtl8169_private *tp = netdev_priv(dev);
2150         int rc;
2151
2152         rtl_lock_work(tp);
2153         rc = tp->get_link_ksettings(dev, cmd);
2154         rtl_unlock_work(tp);
2155
2156         return rc;
2157 }
2158
2159 static int rtl8169_set_link_ksettings(struct net_device *dev,
2160                                       const struct ethtool_link_ksettings *cmd)
2161 {
2162         struct rtl8169_private *tp = netdev_priv(dev);
2163         int rc;
2164         u32 advertising;
2165
2166         if (!ethtool_convert_link_mode_to_legacy_u32(&advertising,
2167             cmd->link_modes.advertising))
2168                 return -EINVAL;
2169
2170         del_timer_sync(&tp->timer);
2171
2172         rtl_lock_work(tp);
2173         rc = rtl8169_set_speed(dev, cmd->base.autoneg, cmd->base.speed,
2174                                cmd->base.duplex, advertising);
2175         rtl_unlock_work(tp);
2176
2177         return rc;
2178 }
2179
2180 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2181                              void *p)
2182 {
2183         struct rtl8169_private *tp = netdev_priv(dev);
2184         u32 __iomem *data = tp->mmio_addr;
2185         u32 *dw = p;
2186         int i;
2187
2188         rtl_lock_work(tp);
2189         for (i = 0; i < R8169_REGS_SIZE; i += 4)
2190                 memcpy_fromio(dw++, data++, 4);
2191         rtl_unlock_work(tp);
2192 }
2193
2194 static u32 rtl8169_get_msglevel(struct net_device *dev)
2195 {
2196         struct rtl8169_private *tp = netdev_priv(dev);
2197
2198         return tp->msg_enable;
2199 }
2200
2201 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
2202 {
2203         struct rtl8169_private *tp = netdev_priv(dev);
2204
2205         tp->msg_enable = value;
2206 }
2207
2208 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
2209         "tx_packets",
2210         "rx_packets",
2211         "tx_errors",
2212         "rx_errors",
2213         "rx_missed",
2214         "align_errors",
2215         "tx_single_collisions",
2216         "tx_multi_collisions",
2217         "unicast",
2218         "broadcast",
2219         "multicast",
2220         "tx_aborted",
2221         "tx_underrun",
2222 };
2223
2224 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
2225 {
2226         switch (sset) {
2227         case ETH_SS_STATS:
2228                 return ARRAY_SIZE(rtl8169_gstrings);
2229         default:
2230                 return -EOPNOTSUPP;
2231         }
2232 }
2233
2234 DECLARE_RTL_COND(rtl_counters_cond)
2235 {
2236         void __iomem *ioaddr = tp->mmio_addr;
2237
2238         return RTL_R32(CounterAddrLow) & (CounterReset | CounterDump);
2239 }
2240
2241 static bool rtl8169_do_counters(struct net_device *dev, u32 counter_cmd)
2242 {
2243         struct rtl8169_private *tp = netdev_priv(dev);
2244         void __iomem *ioaddr = tp->mmio_addr;
2245         dma_addr_t paddr = tp->counters_phys_addr;
2246         u32 cmd;
2247
2248         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
2249         RTL_R32(CounterAddrHigh);
2250         cmd = (u64)paddr & DMA_BIT_MASK(32);
2251         RTL_W32(CounterAddrLow, cmd);
2252         RTL_W32(CounterAddrLow, cmd | counter_cmd);
2253
2254         return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
2255 }
2256
2257 static bool rtl8169_reset_counters(struct net_device *dev)
2258 {
2259         struct rtl8169_private *tp = netdev_priv(dev);
2260
2261         /*
2262          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
2263          * tally counters.
2264          */
2265         if (tp->mac_version < RTL_GIGA_MAC_VER_19)
2266                 return true;
2267
2268         return rtl8169_do_counters(dev, CounterReset);
2269 }
2270
2271 static bool rtl8169_update_counters(struct net_device *dev)
2272 {
2273         struct rtl8169_private *tp = netdev_priv(dev);
2274         void __iomem *ioaddr = tp->mmio_addr;
2275
2276         /*
2277          * Some chips are unable to dump tally counters when the receiver
2278          * is disabled.
2279          */
2280         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
2281                 return true;
2282
2283         return rtl8169_do_counters(dev, CounterDump);
2284 }
2285
2286 static bool rtl8169_init_counter_offsets(struct net_device *dev)
2287 {
2288         struct rtl8169_private *tp = netdev_priv(dev);
2289         struct rtl8169_counters *counters = tp->counters;
2290         bool ret = false;
2291
2292         /*
2293          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
2294          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
2295          * reset by a power cycle, while the counter values collected by the
2296          * driver are reset at every driver unload/load cycle.
2297          *
2298          * To make sure the HW values returned by @get_stats64 match the SW
2299          * values, we collect the initial values at first open(*) and use them
2300          * as offsets to normalize the values returned by @get_stats64.
2301          *
2302          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
2303          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
2304          * set at open time by rtl_hw_start.
2305          */
2306
2307         if (tp->tc_offset.inited)
2308                 return true;
2309
2310         /* If both, reset and update fail, propagate to caller. */
2311         if (rtl8169_reset_counters(dev))
2312                 ret = true;
2313
2314         if (rtl8169_update_counters(dev))
2315                 ret = true;
2316
2317         tp->tc_offset.tx_errors = counters->tx_errors;
2318         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
2319         tp->tc_offset.tx_aborted = counters->tx_aborted;
2320         tp->tc_offset.inited = true;
2321
2322         return ret;
2323 }
2324
2325 static void rtl8169_get_ethtool_stats(struct net_device *dev,
2326                                       struct ethtool_stats *stats, u64 *data)
2327 {
2328         struct rtl8169_private *tp = netdev_priv(dev);
2329         struct device *d = &tp->pci_dev->dev;
2330         struct rtl8169_counters *counters = tp->counters;
2331
2332         ASSERT_RTNL();
2333
2334         pm_runtime_get_noresume(d);
2335
2336         if (pm_runtime_active(d))
2337                 rtl8169_update_counters(dev);
2338
2339         pm_runtime_put_noidle(d);
2340
2341         data[0] = le64_to_cpu(counters->tx_packets);
2342         data[1] = le64_to_cpu(counters->rx_packets);
2343         data[2] = le64_to_cpu(counters->tx_errors);
2344         data[3] = le32_to_cpu(counters->rx_errors);
2345         data[4] = le16_to_cpu(counters->rx_missed);
2346         data[5] = le16_to_cpu(counters->align_errors);
2347         data[6] = le32_to_cpu(counters->tx_one_collision);
2348         data[7] = le32_to_cpu(counters->tx_multi_collision);
2349         data[8] = le64_to_cpu(counters->rx_unicast);
2350         data[9] = le64_to_cpu(counters->rx_broadcast);
2351         data[10] = le32_to_cpu(counters->rx_multicast);
2352         data[11] = le16_to_cpu(counters->tx_aborted);
2353         data[12] = le16_to_cpu(counters->tx_underun);
2354 }
2355
2356 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2357 {
2358         switch(stringset) {
2359         case ETH_SS_STATS:
2360                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2361                 break;
2362         }
2363 }
2364
2365 static int rtl8169_nway_reset(struct net_device *dev)
2366 {
2367         struct rtl8169_private *tp = netdev_priv(dev);
2368
2369         return mii_nway_restart(&tp->mii);
2370 }
2371
2372 /*
2373  * Interrupt coalescing
2374  *
2375  * > 1 - the availability of the IntrMitigate (0xe2) register through the
2376  * >     8169, 8168 and 810x line of chipsets
2377  *
2378  * 8169, 8168, and 8136(810x) serial chipsets support it.
2379  *
2380  * > 2 - the Tx timer unit at gigabit speed
2381  *
2382  * The unit of the timer depends on both the speed and the setting of CPlusCmd
2383  * (0xe0) bit 1 and bit 0.
2384  *
2385  * For 8169
2386  * bit[1:0] \ speed        1000M           100M            10M
2387  * 0 0                     320ns           2.56us          40.96us
2388  * 0 1                     2.56us          20.48us         327.7us
2389  * 1 0                     5.12us          40.96us         655.4us
2390  * 1 1                     10.24us         81.92us         1.31ms
2391  *
2392  * For the other
2393  * bit[1:0] \ speed        1000M           100M            10M
2394  * 0 0                     5us             2.56us          40.96us
2395  * 0 1                     40us            20.48us         327.7us
2396  * 1 0                     80us            40.96us         655.4us
2397  * 1 1                     160us           81.92us         1.31ms
2398  */
2399
2400 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
2401 struct rtl_coalesce_scale {
2402         /* Rx / Tx */
2403         u32 nsecs[2];
2404 };
2405
2406 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
2407 struct rtl_coalesce_info {
2408         u32 speed;
2409         struct rtl_coalesce_scale scalev[4];    /* each CPlusCmd[0:1] case */
2410 };
2411
2412 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
2413 #define rxtx_x1822(r, t) {              \
2414         {{(r),          (t)}},          \
2415         {{(r)*8,        (t)*8}},        \
2416         {{(r)*8*2,      (t)*8*2}},      \
2417         {{(r)*8*2*2,    (t)*8*2*2}},    \
2418 }
2419 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
2420         /* speed        delays:     rx00   tx00 */
2421         { SPEED_10,     rxtx_x1822(40960, 40960)        },
2422         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
2423         { SPEED_1000,   rxtx_x1822(  320,   320)        },
2424         { 0 },
2425 };
2426
2427 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
2428         /* speed        delays:     rx00   tx00 */
2429         { SPEED_10,     rxtx_x1822(40960, 40960)        },
2430         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
2431         { SPEED_1000,   rxtx_x1822( 5000,  5000)        },
2432         { 0 },
2433 };
2434 #undef rxtx_x1822
2435
2436 /* get rx/tx scale vector corresponding to current speed */
2437 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
2438 {
2439         struct rtl8169_private *tp = netdev_priv(dev);
2440         struct ethtool_link_ksettings ecmd;
2441         const struct rtl_coalesce_info *ci;
2442         int rc;
2443
2444         rc = rtl8169_get_link_ksettings(dev, &ecmd);
2445         if (rc < 0)
2446                 return ERR_PTR(rc);
2447
2448         for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
2449                 if (ecmd.base.speed == ci->speed) {
2450                         return ci;
2451                 }
2452         }
2453
2454         return ERR_PTR(-ELNRNG);
2455 }
2456
2457 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
2458 {
2459         struct rtl8169_private *tp = netdev_priv(dev);
2460         void __iomem *ioaddr = tp->mmio_addr;
2461         const struct rtl_coalesce_info *ci;
2462         const struct rtl_coalesce_scale *scale;
2463         struct {
2464                 u32 *max_frames;
2465                 u32 *usecs;
2466         } coal_settings [] = {
2467                 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
2468                 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
2469         }, *p = coal_settings;
2470         int i;
2471         u16 w;
2472
2473         memset(ec, 0, sizeof(*ec));
2474
2475         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
2476         ci = rtl_coalesce_info(dev);
2477         if (IS_ERR(ci))
2478                 return PTR_ERR(ci);
2479
2480         scale = &ci->scalev[RTL_R16(CPlusCmd) & 3];
2481
2482         /* read IntrMitigate and adjust according to scale */
2483         for (w = RTL_R16(IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
2484                 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
2485                 w >>= RTL_COALESCE_SHIFT;
2486                 *p->usecs = w & RTL_COALESCE_MASK;
2487         }
2488
2489         for (i = 0; i < 2; i++) {
2490                 p = coal_settings + i;
2491                 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
2492
2493                 /*
2494                  * ethtool_coalesce says it is illegal to set both usecs and
2495                  * max_frames to 0.
2496                  */
2497                 if (!*p->usecs && !*p->max_frames)
2498                         *p->max_frames = 1;
2499         }
2500
2501         return 0;
2502 }
2503
2504 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
2505 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
2506                         struct net_device *dev, u32 nsec, u16 *cp01)
2507 {
2508         const struct rtl_coalesce_info *ci;
2509         u16 i;
2510
2511         ci = rtl_coalesce_info(dev);
2512         if (IS_ERR(ci))
2513                 return ERR_CAST(ci);
2514
2515         for (i = 0; i < 4; i++) {
2516                 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
2517                                         ci->scalev[i].nsecs[1]);
2518                 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
2519                         *cp01 = i;
2520                         return &ci->scalev[i];
2521                 }
2522         }
2523
2524         return ERR_PTR(-EINVAL);
2525 }
2526
2527 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
2528 {
2529         struct rtl8169_private *tp = netdev_priv(dev);
2530         void __iomem *ioaddr = tp->mmio_addr;
2531         const struct rtl_coalesce_scale *scale;
2532         struct {
2533                 u32 frames;
2534                 u32 usecs;
2535         } coal_settings [] = {
2536                 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
2537                 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
2538         }, *p = coal_settings;
2539         u16 w = 0, cp01;
2540         int i;
2541
2542         scale = rtl_coalesce_choose_scale(dev,
2543                         max(p[0].usecs, p[1].usecs) * 1000, &cp01);
2544         if (IS_ERR(scale))
2545                 return PTR_ERR(scale);
2546
2547         for (i = 0; i < 2; i++, p++) {
2548                 u32 units;
2549
2550                 /*
2551                  * accept max_frames=1 we returned in rtl_get_coalesce.
2552                  * accept it not only when usecs=0 because of e.g. the following scenario:
2553                  *
2554                  * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
2555                  * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2556                  * - then user does `ethtool -C eth0 rx-usecs 100`
2557                  *
2558                  * since ethtool sends to kernel whole ethtool_coalesce
2559                  * settings, if we do not handle rx_usecs=!0, rx_frames=1
2560                  * we'll reject it below in `frames % 4 != 0`.
2561                  */
2562                 if (p->frames == 1) {
2563                         p->frames = 0;
2564                 }
2565
2566                 units = p->usecs * 1000 / scale->nsecs[i];
2567                 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2568                         return -EINVAL;
2569
2570                 w <<= RTL_COALESCE_SHIFT;
2571                 w |= units;
2572                 w <<= RTL_COALESCE_SHIFT;
2573                 w |= p->frames >> 2;
2574         }
2575
2576         rtl_lock_work(tp);
2577
2578         RTL_W16(IntrMitigate, swab16(w));
2579
2580         tp->cp_cmd = (tp->cp_cmd & ~3) | cp01;
2581         RTL_W16(CPlusCmd, tp->cp_cmd);
2582         RTL_R16(CPlusCmd);
2583
2584         rtl_unlock_work(tp);
2585
2586         return 0;
2587 }
2588
2589 static const struct ethtool_ops rtl8169_ethtool_ops = {
2590         .get_drvinfo            = rtl8169_get_drvinfo,
2591         .get_regs_len           = rtl8169_get_regs_len,
2592         .get_link               = ethtool_op_get_link,
2593         .get_coalesce           = rtl_get_coalesce,
2594         .set_coalesce           = rtl_set_coalesce,
2595         .get_msglevel           = rtl8169_get_msglevel,
2596         .set_msglevel           = rtl8169_set_msglevel,
2597         .get_regs               = rtl8169_get_regs,
2598         .get_wol                = rtl8169_get_wol,
2599         .set_wol                = rtl8169_set_wol,
2600         .get_strings            = rtl8169_get_strings,
2601         .get_sset_count         = rtl8169_get_sset_count,
2602         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2603         .get_ts_info            = ethtool_op_get_ts_info,
2604         .nway_reset             = rtl8169_nway_reset,
2605         .get_link_ksettings     = rtl8169_get_link_ksettings,
2606         .set_link_ksettings     = rtl8169_set_link_ksettings,
2607 };
2608
2609 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2610                                     struct net_device *dev, u8 default_version)
2611 {
2612         void __iomem *ioaddr = tp->mmio_addr;
2613         /*
2614          * The driver currently handles the 8168Bf and the 8168Be identically
2615          * but they can be identified more specifically through the test below
2616          * if needed:
2617          *
2618          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2619          *
2620          * Same thing for the 8101Eb and the 8101Ec:
2621          *
2622          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2623          */
2624         static const struct rtl_mac_info {
2625                 u32 mask;
2626                 u32 val;
2627                 int mac_version;
2628         } mac_info[] = {
2629                 /* 8168EP family. */
2630                 { 0x7cf00000, 0x50200000,       RTL_GIGA_MAC_VER_51 },
2631                 { 0x7cf00000, 0x50100000,       RTL_GIGA_MAC_VER_50 },
2632                 { 0x7cf00000, 0x50000000,       RTL_GIGA_MAC_VER_49 },
2633
2634                 /* 8168H family. */
2635                 { 0x7cf00000, 0x54100000,       RTL_GIGA_MAC_VER_46 },
2636                 { 0x7cf00000, 0x54000000,       RTL_GIGA_MAC_VER_45 },
2637
2638                 /* 8168G family. */
2639                 { 0x7cf00000, 0x5c800000,       RTL_GIGA_MAC_VER_44 },
2640                 { 0x7cf00000, 0x50900000,       RTL_GIGA_MAC_VER_42 },
2641                 { 0x7cf00000, 0x4c100000,       RTL_GIGA_MAC_VER_41 },
2642                 { 0x7cf00000, 0x4c000000,       RTL_GIGA_MAC_VER_40 },
2643
2644                 /* 8168F family. */
2645                 { 0x7c800000, 0x48800000,       RTL_GIGA_MAC_VER_38 },
2646                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
2647                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
2648
2649                 /* 8168E family. */
2650                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
2651                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
2652                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
2653                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
2654
2655                 /* 8168D family. */
2656                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
2657                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
2658                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
2659
2660                 /* 8168DP family. */
2661                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
2662                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
2663                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
2664
2665                 /* 8168C family. */
2666                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
2667                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
2668                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
2669                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
2670                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
2671                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
2672                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
2673                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
2674                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
2675
2676                 /* 8168B family. */
2677                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
2678                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
2679                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
2680                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
2681
2682                 /* 8101 family. */
2683                 { 0x7cf00000, 0x44900000,       RTL_GIGA_MAC_VER_39 },
2684                 { 0x7c800000, 0x44800000,       RTL_GIGA_MAC_VER_39 },
2685                 { 0x7c800000, 0x44000000,       RTL_GIGA_MAC_VER_37 },
2686                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
2687                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
2688                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
2689                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
2690                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
2691                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
2692                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
2693                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
2694                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
2695                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
2696                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
2697                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
2698                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
2699                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
2700                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
2701                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
2702                 /* FIXME: where did these entries come from ? -- FR */
2703                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
2704                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
2705
2706                 /* 8110 family. */
2707                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
2708                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
2709                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
2710                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
2711                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
2712                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
2713
2714                 /* Catch-all */
2715                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
2716         };
2717         const struct rtl_mac_info *p = mac_info;
2718         u32 reg;
2719
2720         reg = RTL_R32(TxConfig);
2721         while ((reg & p->mask) != p->val)
2722                 p++;
2723         tp->mac_version = p->mac_version;
2724
2725         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2726                 netif_notice(tp, probe, dev,
2727                              "unknown MAC, using family default\n");
2728                 tp->mac_version = default_version;
2729         } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2730                 tp->mac_version = tp->mii.supports_gmii ?
2731                                   RTL_GIGA_MAC_VER_42 :
2732                                   RTL_GIGA_MAC_VER_43;
2733         } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2734                 tp->mac_version = tp->mii.supports_gmii ?
2735                                   RTL_GIGA_MAC_VER_45 :
2736                                   RTL_GIGA_MAC_VER_47;
2737         } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2738                 tp->mac_version = tp->mii.supports_gmii ?
2739                                   RTL_GIGA_MAC_VER_46 :
2740                                   RTL_GIGA_MAC_VER_48;
2741         }
2742 }
2743
2744 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2745 {
2746         dprintk("mac_version = 0x%02x\n", tp->mac_version);
2747 }
2748
2749 struct phy_reg {
2750         u16 reg;
2751         u16 val;
2752 };
2753
2754 static void rtl_writephy_batch(struct rtl8169_private *tp,
2755                                const struct phy_reg *regs, int len)
2756 {
2757         while (len-- > 0) {
2758                 rtl_writephy(tp, regs->reg, regs->val);
2759                 regs++;
2760         }
2761 }
2762
2763 #define PHY_READ                0x00000000
2764 #define PHY_DATA_OR             0x10000000
2765 #define PHY_DATA_AND            0x20000000
2766 #define PHY_BJMPN               0x30000000
2767 #define PHY_MDIO_CHG            0x40000000
2768 #define PHY_CLEAR_READCOUNT     0x70000000
2769 #define PHY_WRITE               0x80000000
2770 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2771 #define PHY_COMP_EQ_SKIPN       0xa0000000
2772 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2773 #define PHY_WRITE_PREVIOUS      0xc0000000
2774 #define PHY_SKIPN               0xd0000000
2775 #define PHY_DELAY_MS            0xe0000000
2776
2777 struct fw_info {
2778         u32     magic;
2779         char    version[RTL_VER_SIZE];
2780         __le32  fw_start;
2781         __le32  fw_len;
2782         u8      chksum;
2783 } __packed;
2784
2785 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2786
2787 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2788 {
2789         const struct firmware *fw = rtl_fw->fw;
2790         struct fw_info *fw_info = (struct fw_info *)fw->data;
2791         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2792         char *version = rtl_fw->version;
2793         bool rc = false;
2794
2795         if (fw->size < FW_OPCODE_SIZE)
2796                 goto out;
2797
2798         if (!fw_info->magic) {
2799                 size_t i, size, start;
2800                 u8 checksum = 0;
2801
2802                 if (fw->size < sizeof(*fw_info))
2803                         goto out;
2804
2805                 for (i = 0; i < fw->size; i++)
2806                         checksum += fw->data[i];
2807                 if (checksum != 0)
2808                         goto out;
2809
2810                 start = le32_to_cpu(fw_info->fw_start);
2811                 if (start > fw->size)
2812                         goto out;
2813
2814                 size = le32_to_cpu(fw_info->fw_len);
2815                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2816                         goto out;
2817
2818                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2819
2820                 pa->code = (__le32 *)(fw->data + start);
2821                 pa->size = size;
2822         } else {
2823                 if (fw->size % FW_OPCODE_SIZE)
2824                         goto out;
2825
2826                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2827
2828                 pa->code = (__le32 *)fw->data;
2829                 pa->size = fw->size / FW_OPCODE_SIZE;
2830         }
2831         version[RTL_VER_SIZE - 1] = 0;
2832
2833         rc = true;
2834 out:
2835         return rc;
2836 }
2837
2838 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2839                            struct rtl_fw_phy_action *pa)
2840 {
2841         bool rc = false;
2842         size_t index;
2843
2844         for (index = 0; index < pa->size; index++) {
2845                 u32 action = le32_to_cpu(pa->code[index]);
2846                 u32 regno = (action & 0x0fff0000) >> 16;
2847
2848                 switch(action & 0xf0000000) {
2849                 case PHY_READ:
2850                 case PHY_DATA_OR:
2851                 case PHY_DATA_AND:
2852                 case PHY_MDIO_CHG:
2853                 case PHY_CLEAR_READCOUNT:
2854                 case PHY_WRITE:
2855                 case PHY_WRITE_PREVIOUS:
2856                 case PHY_DELAY_MS:
2857                         break;
2858
2859                 case PHY_BJMPN:
2860                         if (regno > index) {
2861                                 netif_err(tp, ifup, tp->dev,
2862                                           "Out of range of firmware\n");
2863                                 goto out;
2864                         }
2865                         break;
2866                 case PHY_READCOUNT_EQ_SKIP:
2867                         if (index + 2 >= pa->size) {
2868                                 netif_err(tp, ifup, tp->dev,
2869                                           "Out of range of firmware\n");
2870                                 goto out;
2871                         }
2872                         break;
2873                 case PHY_COMP_EQ_SKIPN:
2874                 case PHY_COMP_NEQ_SKIPN:
2875                 case PHY_SKIPN:
2876                         if (index + 1 + regno >= pa->size) {
2877                                 netif_err(tp, ifup, tp->dev,
2878                                           "Out of range of firmware\n");
2879                                 goto out;
2880                         }
2881                         break;
2882
2883                 default:
2884                         netif_err(tp, ifup, tp->dev,
2885                                   "Invalid action 0x%08x\n", action);
2886                         goto out;
2887                 }
2888         }
2889         rc = true;
2890 out:
2891         return rc;
2892 }
2893
2894 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2895 {
2896         struct net_device *dev = tp->dev;
2897         int rc = -EINVAL;
2898
2899         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2900                 netif_err(tp, ifup, dev, "invalid firmware\n");
2901                 goto out;
2902         }
2903
2904         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2905                 rc = 0;
2906 out:
2907         return rc;
2908 }
2909
2910 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2911 {
2912         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2913         struct mdio_ops org, *ops = &tp->mdio_ops;
2914         u32 predata, count;
2915         size_t index;
2916
2917         predata = count = 0;
2918         org.write = ops->write;
2919         org.read = ops->read;
2920
2921         for (index = 0; index < pa->size; ) {
2922                 u32 action = le32_to_cpu(pa->code[index]);
2923                 u32 data = action & 0x0000ffff;
2924                 u32 regno = (action & 0x0fff0000) >> 16;
2925
2926                 if (!action)
2927                         break;
2928
2929                 switch(action & 0xf0000000) {
2930                 case PHY_READ:
2931                         predata = rtl_readphy(tp, regno);
2932                         count++;
2933                         index++;
2934                         break;
2935                 case PHY_DATA_OR:
2936                         predata |= data;
2937                         index++;
2938                         break;
2939                 case PHY_DATA_AND:
2940                         predata &= data;
2941                         index++;
2942                         break;
2943                 case PHY_BJMPN:
2944                         index -= regno;
2945                         break;
2946                 case PHY_MDIO_CHG:
2947                         if (data == 0) {
2948                                 ops->write = org.write;
2949                                 ops->read = org.read;
2950                         } else if (data == 1) {
2951                                 ops->write = mac_mcu_write;
2952                                 ops->read = mac_mcu_read;
2953                         }
2954
2955                         index++;
2956                         break;
2957                 case PHY_CLEAR_READCOUNT:
2958                         count = 0;
2959                         index++;
2960                         break;
2961                 case PHY_WRITE:
2962                         rtl_writephy(tp, regno, data);
2963                         index++;
2964                         break;
2965                 case PHY_READCOUNT_EQ_SKIP:
2966                         index += (count == data) ? 2 : 1;
2967                         break;
2968                 case PHY_COMP_EQ_SKIPN:
2969                         if (predata == data)
2970                                 index += regno;
2971                         index++;
2972                         break;
2973                 case PHY_COMP_NEQ_SKIPN:
2974                         if (predata != data)
2975                                 index += regno;
2976                         index++;
2977                         break;
2978                 case PHY_WRITE_PREVIOUS:
2979                         rtl_writephy(tp, regno, predata);
2980                         index++;
2981                         break;
2982                 case PHY_SKIPN:
2983                         index += regno + 1;
2984                         break;
2985                 case PHY_DELAY_MS:
2986                         mdelay(data);
2987                         index++;
2988                         break;
2989
2990                 default:
2991                         BUG();
2992                 }
2993         }
2994
2995         ops->write = org.write;
2996         ops->read = org.read;
2997 }
2998
2999 static void rtl_release_firmware(struct rtl8169_private *tp)
3000 {
3001         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
3002                 release_firmware(tp->rtl_fw->fw);
3003                 kfree(tp->rtl_fw);
3004         }
3005         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
3006 }
3007
3008 static void rtl_apply_firmware(struct rtl8169_private *tp)
3009 {
3010         struct rtl_fw *rtl_fw = tp->rtl_fw;
3011
3012         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
3013         if (!IS_ERR_OR_NULL(rtl_fw))
3014                 rtl_phy_write_fw(tp, rtl_fw);
3015 }
3016
3017 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
3018 {
3019         if (rtl_readphy(tp, reg) != val)
3020                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
3021         else
3022                 rtl_apply_firmware(tp);
3023 }
3024
3025 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
3026 {
3027         static const struct phy_reg phy_reg_init[] = {
3028                 { 0x1f, 0x0001 },
3029                 { 0x06, 0x006e },
3030                 { 0x08, 0x0708 },
3031                 { 0x15, 0x4000 },
3032                 { 0x18, 0x65c7 },
3033
3034                 { 0x1f, 0x0001 },
3035                 { 0x03, 0x00a1 },
3036                 { 0x02, 0x0008 },
3037                 { 0x01, 0x0120 },
3038                 { 0x00, 0x1000 },
3039                 { 0x04, 0x0800 },
3040                 { 0x04, 0x0000 },
3041
3042                 { 0x03, 0xff41 },
3043                 { 0x02, 0xdf60 },
3044                 { 0x01, 0x0140 },
3045                 { 0x00, 0x0077 },
3046                 { 0x04, 0x7800 },
3047                 { 0x04, 0x7000 },
3048
3049                 { 0x03, 0x802f },
3050                 { 0x02, 0x4f02 },
3051                 { 0x01, 0x0409 },
3052                 { 0x00, 0xf0f9 },
3053                 { 0x04, 0x9800 },
3054                 { 0x04, 0x9000 },
3055
3056                 { 0x03, 0xdf01 },
3057                 { 0x02, 0xdf20 },
3058                 { 0x01, 0xff95 },
3059                 { 0x00, 0xba00 },
3060                 { 0x04, 0xa800 },
3061                 { 0x04, 0xa000 },
3062
3063                 { 0x03, 0xff41 },
3064                 { 0x02, 0xdf20 },
3065                 { 0x01, 0x0140 },
3066                 { 0x00, 0x00bb },
3067                 { 0x04, 0xb800 },
3068                 { 0x04, 0xb000 },
3069
3070                 { 0x03, 0xdf41 },
3071                 { 0x02, 0xdc60 },
3072                 { 0x01, 0x6340 },
3073                 { 0x00, 0x007d },
3074                 { 0x04, 0xd800 },
3075                 { 0x04, 0xd000 },
3076
3077                 { 0x03, 0xdf01 },
3078                 { 0x02, 0xdf20 },
3079                 { 0x01, 0x100a },
3080                 { 0x00, 0xa0ff },
3081                 { 0x04, 0xf800 },
3082                 { 0x04, 0xf000 },
3083
3084                 { 0x1f, 0x0000 },
3085                 { 0x0b, 0x0000 },
3086                 { 0x00, 0x9200 }
3087         };
3088
3089         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3090 }
3091
3092 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
3093 {
3094         static const struct phy_reg phy_reg_init[] = {
3095                 { 0x1f, 0x0002 },
3096                 { 0x01, 0x90d0 },
3097                 { 0x1f, 0x0000 }
3098         };
3099
3100         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3101 }
3102
3103 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
3104 {
3105         struct pci_dev *pdev = tp->pci_dev;
3106
3107         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
3108             (pdev->subsystem_device != 0xe000))
3109                 return;
3110
3111         rtl_writephy(tp, 0x1f, 0x0001);
3112         rtl_writephy(tp, 0x10, 0xf01b);
3113         rtl_writephy(tp, 0x1f, 0x0000);
3114 }
3115
3116 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
3117 {
3118         static const struct phy_reg phy_reg_init[] = {
3119                 { 0x1f, 0x0001 },
3120                 { 0x04, 0x0000 },
3121                 { 0x03, 0x00a1 },
3122                 { 0x02, 0x0008 },
3123                 { 0x01, 0x0120 },
3124                 { 0x00, 0x1000 },
3125                 { 0x04, 0x0800 },
3126                 { 0x04, 0x9000 },
3127                 { 0x03, 0x802f },
3128                 { 0x02, 0x4f02 },
3129                 { 0x01, 0x0409 },
3130                 { 0x00, 0xf099 },
3131                 { 0x04, 0x9800 },
3132                 { 0x04, 0xa000 },
3133                 { 0x03, 0xdf01 },
3134                 { 0x02, 0xdf20 },
3135                 { 0x01, 0xff95 },
3136                 { 0x00, 0xba00 },
3137                 { 0x04, 0xa800 },
3138                 { 0x04, 0xf000 },
3139                 { 0x03, 0xdf01 },
3140                 { 0x02, 0xdf20 },
3141                 { 0x01, 0x101a },
3142                 { 0x00, 0xa0ff },
3143                 { 0x04, 0xf800 },
3144                 { 0x04, 0x0000 },
3145                 { 0x1f, 0x0000 },
3146
3147                 { 0x1f, 0x0001 },
3148                 { 0x10, 0xf41b },
3149                 { 0x14, 0xfb54 },
3150                 { 0x18, 0xf5c7 },
3151                 { 0x1f, 0x0000 },
3152
3153                 { 0x1f, 0x0001 },
3154                 { 0x17, 0x0cc0 },
3155                 { 0x1f, 0x0000 }
3156         };
3157
3158         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3159
3160         rtl8169scd_hw_phy_config_quirk(tp);
3161 }
3162
3163 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
3164 {
3165         static const struct phy_reg phy_reg_init[] = {
3166                 { 0x1f, 0x0001 },
3167                 { 0x04, 0x0000 },
3168                 { 0x03, 0x00a1 },
3169                 { 0x02, 0x0008 },
3170                 { 0x01, 0x0120 },
3171                 { 0x00, 0x1000 },
3172                 { 0x04, 0x0800 },
3173                 { 0x04, 0x9000 },
3174                 { 0x03, 0x802f },
3175                 { 0x02, 0x4f02 },
3176                 { 0x01, 0x0409 },
3177                 { 0x00, 0xf099 },
3178                 { 0x04, 0x9800 },
3179                 { 0x04, 0xa000 },
3180                 { 0x03, 0xdf01 },
3181                 { 0x02, 0xdf20 },
3182                 { 0x01, 0xff95 },
3183                 { 0x00, 0xba00 },
3184                 { 0x04, 0xa800 },
3185                 { 0x04, 0xf000 },
3186                 { 0x03, 0xdf01 },
3187                 { 0x02, 0xdf20 },
3188                 { 0x01, 0x101a },
3189                 { 0x00, 0xa0ff },
3190                 { 0x04, 0xf800 },
3191                 { 0x04, 0x0000 },
3192                 { 0x1f, 0x0000 },
3193
3194                 { 0x1f, 0x0001 },
3195                 { 0x0b, 0x8480 },
3196                 { 0x1f, 0x0000 },
3197
3198                 { 0x1f, 0x0001 },
3199                 { 0x18, 0x67c7 },
3200                 { 0x04, 0x2000 },
3201                 { 0x03, 0x002f },
3202                 { 0x02, 0x4360 },
3203                 { 0x01, 0x0109 },
3204                 { 0x00, 0x3022 },
3205                 { 0x04, 0x2800 },
3206                 { 0x1f, 0x0000 },
3207
3208                 { 0x1f, 0x0001 },
3209                 { 0x17, 0x0cc0 },
3210                 { 0x1f, 0x0000 }
3211         };
3212
3213         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3214 }
3215
3216 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
3217 {
3218         static const struct phy_reg phy_reg_init[] = {
3219                 { 0x10, 0xf41b },
3220                 { 0x1f, 0x0000 }
3221         };
3222
3223         rtl_writephy(tp, 0x1f, 0x0001);
3224         rtl_patchphy(tp, 0x16, 1 << 0);
3225
3226         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3227 }
3228
3229 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
3230 {
3231         static const struct phy_reg phy_reg_init[] = {
3232                 { 0x1f, 0x0001 },
3233                 { 0x10, 0xf41b },
3234                 { 0x1f, 0x0000 }
3235         };
3236
3237         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3238 }
3239
3240 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
3241 {
3242         static const struct phy_reg phy_reg_init[] = {
3243                 { 0x1f, 0x0000 },
3244                 { 0x1d, 0x0f00 },
3245                 { 0x1f, 0x0002 },
3246                 { 0x0c, 0x1ec8 },
3247                 { 0x1f, 0x0000 }
3248         };
3249
3250         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3251 }
3252
3253 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
3254 {
3255         static const struct phy_reg phy_reg_init[] = {
3256                 { 0x1f, 0x0001 },
3257                 { 0x1d, 0x3d98 },
3258                 { 0x1f, 0x0000 }
3259         };
3260
3261         rtl_writephy(tp, 0x1f, 0x0000);
3262         rtl_patchphy(tp, 0x14, 1 << 5);
3263         rtl_patchphy(tp, 0x0d, 1 << 5);
3264
3265         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3266 }
3267
3268 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
3269 {
3270         static const struct phy_reg phy_reg_init[] = {
3271                 { 0x1f, 0x0001 },
3272                 { 0x12, 0x2300 },
3273                 { 0x1f, 0x0002 },
3274                 { 0x00, 0x88d4 },
3275                 { 0x01, 0x82b1 },
3276                 { 0x03, 0x7002 },
3277                 { 0x08, 0x9e30 },
3278                 { 0x09, 0x01f0 },
3279                 { 0x0a, 0x5500 },
3280                 { 0x0c, 0x00c8 },
3281                 { 0x1f, 0x0003 },
3282                 { 0x12, 0xc096 },
3283                 { 0x16, 0x000a },
3284                 { 0x1f, 0x0000 },
3285                 { 0x1f, 0x0000 },
3286                 { 0x09, 0x2000 },
3287                 { 0x09, 0x0000 }
3288         };
3289
3290         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3291
3292         rtl_patchphy(tp, 0x14, 1 << 5);
3293         rtl_patchphy(tp, 0x0d, 1 << 5);
3294         rtl_writephy(tp, 0x1f, 0x0000);
3295 }
3296
3297 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
3298 {
3299         static const struct phy_reg phy_reg_init[] = {
3300                 { 0x1f, 0x0001 },
3301                 { 0x12, 0x2300 },
3302                 { 0x03, 0x802f },
3303                 { 0x02, 0x4f02 },
3304                 { 0x01, 0x0409 },
3305                 { 0x00, 0xf099 },
3306                 { 0x04, 0x9800 },
3307                 { 0x04, 0x9000 },
3308                 { 0x1d, 0x3d98 },
3309                 { 0x1f, 0x0002 },
3310                 { 0x0c, 0x7eb8 },
3311                 { 0x06, 0x0761 },
3312                 { 0x1f, 0x0003 },
3313                 { 0x16, 0x0f0a },
3314                 { 0x1f, 0x0000 }
3315         };
3316
3317         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3318
3319         rtl_patchphy(tp, 0x16, 1 << 0);
3320         rtl_patchphy(tp, 0x14, 1 << 5);
3321         rtl_patchphy(tp, 0x0d, 1 << 5);
3322         rtl_writephy(tp, 0x1f, 0x0000);
3323 }
3324
3325 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
3326 {
3327         static const struct phy_reg phy_reg_init[] = {
3328                 { 0x1f, 0x0001 },
3329                 { 0x12, 0x2300 },
3330                 { 0x1d, 0x3d98 },
3331                 { 0x1f, 0x0002 },
3332                 { 0x0c, 0x7eb8 },
3333                 { 0x06, 0x5461 },
3334                 { 0x1f, 0x0003 },
3335                 { 0x16, 0x0f0a },
3336                 { 0x1f, 0x0000 }
3337         };
3338
3339         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3340
3341         rtl_patchphy(tp, 0x16, 1 << 0);
3342         rtl_patchphy(tp, 0x14, 1 << 5);
3343         rtl_patchphy(tp, 0x0d, 1 << 5);
3344         rtl_writephy(tp, 0x1f, 0x0000);
3345 }
3346
3347 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
3348 {
3349         rtl8168c_3_hw_phy_config(tp);
3350 }
3351
3352 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
3353 {
3354         static const struct phy_reg phy_reg_init_0[] = {
3355                 /* Channel Estimation */
3356                 { 0x1f, 0x0001 },
3357                 { 0x06, 0x4064 },
3358                 { 0x07, 0x2863 },
3359                 { 0x08, 0x059c },
3360                 { 0x09, 0x26b4 },
3361                 { 0x0a, 0x6a19 },
3362                 { 0x0b, 0xdcc8 },
3363                 { 0x10, 0xf06d },
3364                 { 0x14, 0x7f68 },
3365                 { 0x18, 0x7fd9 },
3366                 { 0x1c, 0xf0ff },
3367                 { 0x1d, 0x3d9c },
3368                 { 0x1f, 0x0003 },
3369                 { 0x12, 0xf49f },
3370                 { 0x13, 0x070b },
3371                 { 0x1a, 0x05ad },
3372                 { 0x14, 0x94c0 },
3373
3374                 /*
3375                  * Tx Error Issue
3376                  * Enhance line driver power
3377                  */
3378                 { 0x1f, 0x0002 },
3379                 { 0x06, 0x5561 },
3380                 { 0x1f, 0x0005 },
3381                 { 0x05, 0x8332 },
3382                 { 0x06, 0x5561 },
3383
3384                 /*
3385                  * Can not link to 1Gbps with bad cable
3386                  * Decrease SNR threshold form 21.07dB to 19.04dB
3387                  */
3388                 { 0x1f, 0x0001 },
3389                 { 0x17, 0x0cc0 },
3390
3391                 { 0x1f, 0x0000 },
3392                 { 0x0d, 0xf880 }
3393         };
3394
3395         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3396
3397         /*
3398          * Rx Error Issue
3399          * Fine Tune Switching regulator parameter
3400          */
3401         rtl_writephy(tp, 0x1f, 0x0002);
3402         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
3403         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
3404
3405         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3406                 static const struct phy_reg phy_reg_init[] = {
3407                         { 0x1f, 0x0002 },
3408                         { 0x05, 0x669a },
3409                         { 0x1f, 0x0005 },
3410                         { 0x05, 0x8330 },
3411                         { 0x06, 0x669a },
3412                         { 0x1f, 0x0002 }
3413                 };
3414                 int val;
3415
3416                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3417
3418                 val = rtl_readphy(tp, 0x0d);
3419
3420                 if ((val & 0x00ff) != 0x006c) {
3421                         static const u32 set[] = {
3422                                 0x0065, 0x0066, 0x0067, 0x0068,
3423                                 0x0069, 0x006a, 0x006b, 0x006c
3424                         };
3425                         int i;
3426
3427                         rtl_writephy(tp, 0x1f, 0x0002);
3428
3429                         val &= 0xff00;
3430                         for (i = 0; i < ARRAY_SIZE(set); i++)
3431                                 rtl_writephy(tp, 0x0d, val | set[i]);
3432                 }
3433         } else {
3434                 static const struct phy_reg phy_reg_init[] = {
3435                         { 0x1f, 0x0002 },
3436                         { 0x05, 0x6662 },
3437                         { 0x1f, 0x0005 },
3438                         { 0x05, 0x8330 },
3439                         { 0x06, 0x6662 }
3440                 };
3441
3442                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3443         }
3444
3445         /* RSET couple improve */
3446         rtl_writephy(tp, 0x1f, 0x0002);
3447         rtl_patchphy(tp, 0x0d, 0x0300);
3448         rtl_patchphy(tp, 0x0f, 0x0010);
3449
3450         /* Fine tune PLL performance */
3451         rtl_writephy(tp, 0x1f, 0x0002);
3452         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3453         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3454
3455         rtl_writephy(tp, 0x1f, 0x0005);
3456         rtl_writephy(tp, 0x05, 0x001b);
3457
3458         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
3459
3460         rtl_writephy(tp, 0x1f, 0x0000);
3461 }
3462
3463 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
3464 {
3465         static const struct phy_reg phy_reg_init_0[] = {
3466                 /* Channel Estimation */
3467                 { 0x1f, 0x0001 },
3468                 { 0x06, 0x4064 },
3469                 { 0x07, 0x2863 },
3470                 { 0x08, 0x059c },
3471                 { 0x09, 0x26b4 },
3472                 { 0x0a, 0x6a19 },
3473                 { 0x0b, 0xdcc8 },
3474                 { 0x10, 0xf06d },
3475                 { 0x14, 0x7f68 },
3476                 { 0x18, 0x7fd9 },
3477                 { 0x1c, 0xf0ff },
3478                 { 0x1d, 0x3d9c },
3479                 { 0x1f, 0x0003 },
3480                 { 0x12, 0xf49f },
3481                 { 0x13, 0x070b },
3482                 { 0x1a, 0x05ad },
3483                 { 0x14, 0x94c0 },
3484
3485                 /*
3486                  * Tx Error Issue
3487                  * Enhance line driver power
3488                  */
3489                 { 0x1f, 0x0002 },
3490                 { 0x06, 0x5561 },
3491                 { 0x1f, 0x0005 },
3492                 { 0x05, 0x8332 },
3493                 { 0x06, 0x5561 },
3494
3495                 /*
3496                  * Can not link to 1Gbps with bad cable
3497                  * Decrease SNR threshold form 21.07dB to 19.04dB
3498                  */
3499                 { 0x1f, 0x0001 },
3500                 { 0x17, 0x0cc0 },
3501
3502                 { 0x1f, 0x0000 },
3503                 { 0x0d, 0xf880 }
3504         };
3505
3506         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3507
3508         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3509                 static const struct phy_reg phy_reg_init[] = {
3510                         { 0x1f, 0x0002 },
3511                         { 0x05, 0x669a },
3512                         { 0x1f, 0x0005 },
3513                         { 0x05, 0x8330 },
3514                         { 0x06, 0x669a },
3515
3516                         { 0x1f, 0x0002 }
3517                 };
3518                 int val;
3519
3520                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3521
3522                 val = rtl_readphy(tp, 0x0d);
3523                 if ((val & 0x00ff) != 0x006c) {
3524                         static const u32 set[] = {
3525                                 0x0065, 0x0066, 0x0067, 0x0068,
3526                                 0x0069, 0x006a, 0x006b, 0x006c
3527                         };
3528                         int i;
3529
3530                         rtl_writephy(tp, 0x1f, 0x0002);
3531
3532                         val &= 0xff00;
3533                         for (i = 0; i < ARRAY_SIZE(set); i++)
3534                                 rtl_writephy(tp, 0x0d, val | set[i]);
3535                 }
3536         } else {
3537                 static const struct phy_reg phy_reg_init[] = {
3538                         { 0x1f, 0x0002 },
3539                         { 0x05, 0x2642 },
3540                         { 0x1f, 0x0005 },
3541                         { 0x05, 0x8330 },
3542                         { 0x06, 0x2642 }
3543                 };
3544
3545                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3546         }
3547
3548         /* Fine tune PLL performance */
3549         rtl_writephy(tp, 0x1f, 0x0002);
3550         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3551         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3552
3553         /* Switching regulator Slew rate */
3554         rtl_writephy(tp, 0x1f, 0x0002);
3555         rtl_patchphy(tp, 0x0f, 0x0017);
3556
3557         rtl_writephy(tp, 0x1f, 0x0005);
3558         rtl_writephy(tp, 0x05, 0x001b);
3559
3560         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3561
3562         rtl_writephy(tp, 0x1f, 0x0000);
3563 }
3564
3565 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3566 {
3567         static const struct phy_reg phy_reg_init[] = {
3568                 { 0x1f, 0x0002 },
3569                 { 0x10, 0x0008 },
3570                 { 0x0d, 0x006c },
3571
3572                 { 0x1f, 0x0000 },
3573                 { 0x0d, 0xf880 },
3574
3575                 { 0x1f, 0x0001 },
3576                 { 0x17, 0x0cc0 },
3577
3578                 { 0x1f, 0x0001 },
3579                 { 0x0b, 0xa4d8 },
3580                 { 0x09, 0x281c },
3581                 { 0x07, 0x2883 },
3582                 { 0x0a, 0x6b35 },
3583                 { 0x1d, 0x3da4 },
3584                 { 0x1c, 0xeffd },
3585                 { 0x14, 0x7f52 },
3586                 { 0x18, 0x7fc6 },
3587                 { 0x08, 0x0601 },
3588                 { 0x06, 0x4063 },
3589                 { 0x10, 0xf074 },
3590                 { 0x1f, 0x0003 },
3591                 { 0x13, 0x0789 },
3592                 { 0x12, 0xf4bd },
3593                 { 0x1a, 0x04fd },
3594                 { 0x14, 0x84b0 },
3595                 { 0x1f, 0x0000 },
3596                 { 0x00, 0x9200 },
3597
3598                 { 0x1f, 0x0005 },
3599                 { 0x01, 0x0340 },
3600                 { 0x1f, 0x0001 },
3601                 { 0x04, 0x4000 },
3602                 { 0x03, 0x1d21 },
3603                 { 0x02, 0x0c32 },
3604                 { 0x01, 0x0200 },
3605                 { 0x00, 0x5554 },
3606                 { 0x04, 0x4800 },
3607                 { 0x04, 0x4000 },
3608                 { 0x04, 0xf000 },
3609                 { 0x03, 0xdf01 },
3610                 { 0x02, 0xdf20 },
3611                 { 0x01, 0x101a },
3612                 { 0x00, 0xa0ff },
3613                 { 0x04, 0xf800 },
3614                 { 0x04, 0xf000 },
3615                 { 0x1f, 0x0000 },
3616
3617                 { 0x1f, 0x0007 },
3618                 { 0x1e, 0x0023 },
3619                 { 0x16, 0x0000 },
3620                 { 0x1f, 0x0000 }
3621         };
3622
3623         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3624 }
3625
3626 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3627 {
3628         static const struct phy_reg phy_reg_init[] = {
3629                 { 0x1f, 0x0001 },
3630                 { 0x17, 0x0cc0 },
3631
3632                 { 0x1f, 0x0007 },
3633                 { 0x1e, 0x002d },
3634                 { 0x18, 0x0040 },
3635                 { 0x1f, 0x0000 }
3636         };
3637
3638         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3639         rtl_patchphy(tp, 0x0d, 1 << 5);
3640 }
3641
3642 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3643 {
3644         static const struct phy_reg phy_reg_init[] = {
3645                 /* Enable Delay cap */
3646                 { 0x1f, 0x0005 },
3647                 { 0x05, 0x8b80 },
3648                 { 0x06, 0xc896 },
3649                 { 0x1f, 0x0000 },
3650
3651                 /* Channel estimation fine tune */
3652                 { 0x1f, 0x0001 },
3653                 { 0x0b, 0x6c20 },
3654                 { 0x07, 0x2872 },
3655                 { 0x1c, 0xefff },
3656                 { 0x1f, 0x0003 },
3657                 { 0x14, 0x6420 },
3658                 { 0x1f, 0x0000 },
3659
3660                 /* Update PFM & 10M TX idle timer */
3661                 { 0x1f, 0x0007 },
3662                 { 0x1e, 0x002f },
3663                 { 0x15, 0x1919 },
3664                 { 0x1f, 0x0000 },
3665
3666                 { 0x1f, 0x0007 },
3667                 { 0x1e, 0x00ac },
3668                 { 0x18, 0x0006 },
3669                 { 0x1f, 0x0000 }
3670         };
3671
3672         rtl_apply_firmware(tp);
3673
3674         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3675
3676         /* DCO enable for 10M IDLE Power */
3677         rtl_writephy(tp, 0x1f, 0x0007);
3678         rtl_writephy(tp, 0x1e, 0x0023);
3679         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3680         rtl_writephy(tp, 0x1f, 0x0000);
3681
3682         /* For impedance matching */
3683         rtl_writephy(tp, 0x1f, 0x0002);
3684         rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3685         rtl_writephy(tp, 0x1f, 0x0000);
3686
3687         /* PHY auto speed down */
3688         rtl_writephy(tp, 0x1f, 0x0007);
3689         rtl_writephy(tp, 0x1e, 0x002d);
3690         rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3691         rtl_writephy(tp, 0x1f, 0x0000);
3692         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3693
3694         rtl_writephy(tp, 0x1f, 0x0005);
3695         rtl_writephy(tp, 0x05, 0x8b86);
3696         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3697         rtl_writephy(tp, 0x1f, 0x0000);
3698
3699         rtl_writephy(tp, 0x1f, 0x0005);
3700         rtl_writephy(tp, 0x05, 0x8b85);
3701         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3702         rtl_writephy(tp, 0x1f, 0x0007);
3703         rtl_writephy(tp, 0x1e, 0x0020);
3704         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3705         rtl_writephy(tp, 0x1f, 0x0006);
3706         rtl_writephy(tp, 0x00, 0x5a00);
3707         rtl_writephy(tp, 0x1f, 0x0000);
3708         rtl_writephy(tp, 0x0d, 0x0007);
3709         rtl_writephy(tp, 0x0e, 0x003c);
3710         rtl_writephy(tp, 0x0d, 0x4007);
3711         rtl_writephy(tp, 0x0e, 0x0000);
3712         rtl_writephy(tp, 0x0d, 0x0000);
3713 }
3714
3715 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3716 {
3717         const u16 w[] = {
3718                 addr[0] | (addr[1] << 8),
3719                 addr[2] | (addr[3] << 8),
3720                 addr[4] | (addr[5] << 8)
3721         };
3722         const struct exgmac_reg e[] = {
3723                 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3724                 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3725                 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3726                 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3727         };
3728
3729         rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3730 }
3731
3732 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3733 {
3734         static const struct phy_reg phy_reg_init[] = {
3735                 /* Enable Delay cap */
3736                 { 0x1f, 0x0004 },
3737                 { 0x1f, 0x0007 },
3738                 { 0x1e, 0x00ac },
3739                 { 0x18, 0x0006 },
3740                 { 0x1f, 0x0002 },
3741                 { 0x1f, 0x0000 },
3742                 { 0x1f, 0x0000 },
3743
3744                 /* Channel estimation fine tune */
3745                 { 0x1f, 0x0003 },
3746                 { 0x09, 0xa20f },
3747                 { 0x1f, 0x0000 },
3748                 { 0x1f, 0x0000 },
3749
3750                 /* Green Setting */
3751                 { 0x1f, 0x0005 },
3752                 { 0x05, 0x8b5b },
3753                 { 0x06, 0x9222 },
3754                 { 0x05, 0x8b6d },
3755                 { 0x06, 0x8000 },
3756                 { 0x05, 0x8b76 },
3757                 { 0x06, 0x8000 },
3758                 { 0x1f, 0x0000 }
3759         };
3760
3761         rtl_apply_firmware(tp);
3762
3763         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3764
3765         /* For 4-corner performance improve */
3766         rtl_writephy(tp, 0x1f, 0x0005);
3767         rtl_writephy(tp, 0x05, 0x8b80);
3768         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3769         rtl_writephy(tp, 0x1f, 0x0000);
3770
3771         /* PHY auto speed down */
3772         rtl_writephy(tp, 0x1f, 0x0004);
3773         rtl_writephy(tp, 0x1f, 0x0007);
3774         rtl_writephy(tp, 0x1e, 0x002d);
3775         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3776         rtl_writephy(tp, 0x1f, 0x0002);
3777         rtl_writephy(tp, 0x1f, 0x0000);
3778         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3779
3780         /* improve 10M EEE waveform */
3781         rtl_writephy(tp, 0x1f, 0x0005);
3782         rtl_writephy(tp, 0x05, 0x8b86);
3783         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3784         rtl_writephy(tp, 0x1f, 0x0000);
3785
3786         /* Improve 2-pair detection performance */
3787         rtl_writephy(tp, 0x1f, 0x0005);
3788         rtl_writephy(tp, 0x05, 0x8b85);
3789         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3790         rtl_writephy(tp, 0x1f, 0x0000);
3791
3792         /* EEE setting */
3793         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
3794         rtl_writephy(tp, 0x1f, 0x0005);
3795         rtl_writephy(tp, 0x05, 0x8b85);
3796         rtl_w0w1_phy(tp, 0x06, 0x2000, 0x0000);
3797         rtl_writephy(tp, 0x1f, 0x0004);
3798         rtl_writephy(tp, 0x1f, 0x0007);
3799         rtl_writephy(tp, 0x1e, 0x0020);
3800         rtl_w0w1_phy(tp, 0x15, 0x0100, 0x0000);
3801         rtl_writephy(tp, 0x1f, 0x0002);
3802         rtl_writephy(tp, 0x1f, 0x0000);
3803         rtl_writephy(tp, 0x0d, 0x0007);
3804         rtl_writephy(tp, 0x0e, 0x003c);
3805         rtl_writephy(tp, 0x0d, 0x4007);
3806         rtl_writephy(tp, 0x0e, 0x0006);
3807         rtl_writephy(tp, 0x0d, 0x0000);
3808
3809         /* Green feature */
3810         rtl_writephy(tp, 0x1f, 0x0003);
3811         rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3812         rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3813         rtl_writephy(tp, 0x1f, 0x0000);
3814         rtl_writephy(tp, 0x1f, 0x0005);
3815         rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3816         rtl_writephy(tp, 0x1f, 0x0000);
3817         /* soft-reset phy */
3818         rtl_writephy(tp, MII_BMCR, BMCR_RESET | BMCR_ANENABLE | BMCR_ANRESTART);
3819
3820         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3821         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3822 }
3823
3824 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3825 {
3826         /* For 4-corner performance improve */
3827         rtl_writephy(tp, 0x1f, 0x0005);
3828         rtl_writephy(tp, 0x05, 0x8b80);
3829         rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3830         rtl_writephy(tp, 0x1f, 0x0000);
3831
3832         /* PHY auto speed down */
3833         rtl_writephy(tp, 0x1f, 0x0007);
3834         rtl_writephy(tp, 0x1e, 0x002d);
3835         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3836         rtl_writephy(tp, 0x1f, 0x0000);
3837         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3838
3839         /* Improve 10M EEE waveform */
3840         rtl_writephy(tp, 0x1f, 0x0005);
3841         rtl_writephy(tp, 0x05, 0x8b86);
3842         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3843         rtl_writephy(tp, 0x1f, 0x0000);
3844 }
3845
3846 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3847 {
3848         static const struct phy_reg phy_reg_init[] = {
3849                 /* Channel estimation fine tune */
3850                 { 0x1f, 0x0003 },
3851                 { 0x09, 0xa20f },
3852                 { 0x1f, 0x0000 },
3853
3854                 /* Modify green table for giga & fnet */
3855                 { 0x1f, 0x0005 },
3856                 { 0x05, 0x8b55 },
3857                 { 0x06, 0x0000 },
3858                 { 0x05, 0x8b5e },
3859                 { 0x06, 0x0000 },
3860                 { 0x05, 0x8b67 },
3861                 { 0x06, 0x0000 },
3862                 { 0x05, 0x8b70 },
3863                 { 0x06, 0x0000 },
3864                 { 0x1f, 0x0000 },
3865                 { 0x1f, 0x0007 },
3866                 { 0x1e, 0x0078 },
3867                 { 0x17, 0x0000 },
3868                 { 0x19, 0x00fb },
3869                 { 0x1f, 0x0000 },
3870
3871                 /* Modify green table for 10M */
3872                 { 0x1f, 0x0005 },
3873                 { 0x05, 0x8b79 },
3874                 { 0x06, 0xaa00 },
3875                 { 0x1f, 0x0000 },
3876
3877                 /* Disable hiimpedance detection (RTCT) */
3878                 { 0x1f, 0x0003 },
3879                 { 0x01, 0x328a },
3880                 { 0x1f, 0x0000 }
3881         };
3882
3883         rtl_apply_firmware(tp);
3884
3885         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3886
3887         rtl8168f_hw_phy_config(tp);
3888
3889         /* Improve 2-pair detection performance */
3890         rtl_writephy(tp, 0x1f, 0x0005);
3891         rtl_writephy(tp, 0x05, 0x8b85);
3892         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3893         rtl_writephy(tp, 0x1f, 0x0000);
3894 }
3895
3896 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3897 {
3898         rtl_apply_firmware(tp);
3899
3900         rtl8168f_hw_phy_config(tp);
3901 }
3902
3903 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3904 {
3905         static const struct phy_reg phy_reg_init[] = {
3906                 /* Channel estimation fine tune */
3907                 { 0x1f, 0x0003 },
3908                 { 0x09, 0xa20f },
3909                 { 0x1f, 0x0000 },
3910
3911                 /* Modify green table for giga & fnet */
3912                 { 0x1f, 0x0005 },
3913                 { 0x05, 0x8b55 },
3914                 { 0x06, 0x0000 },
3915                 { 0x05, 0x8b5e },
3916                 { 0x06, 0x0000 },
3917                 { 0x05, 0x8b67 },
3918                 { 0x06, 0x0000 },
3919                 { 0x05, 0x8b70 },
3920                 { 0x06, 0x0000 },
3921                 { 0x1f, 0x0000 },
3922                 { 0x1f, 0x0007 },
3923                 { 0x1e, 0x0078 },
3924                 { 0x17, 0x0000 },
3925                 { 0x19, 0x00aa },
3926                 { 0x1f, 0x0000 },
3927
3928                 /* Modify green table for 10M */
3929                 { 0x1f, 0x0005 },
3930                 { 0x05, 0x8b79 },
3931                 { 0x06, 0xaa00 },
3932                 { 0x1f, 0x0000 },
3933
3934                 /* Disable hiimpedance detection (RTCT) */
3935                 { 0x1f, 0x0003 },
3936                 { 0x01, 0x328a },
3937                 { 0x1f, 0x0000 }
3938         };
3939
3940
3941         rtl_apply_firmware(tp);
3942
3943         rtl8168f_hw_phy_config(tp);
3944
3945         /* Improve 2-pair detection performance */
3946         rtl_writephy(tp, 0x1f, 0x0005);
3947         rtl_writephy(tp, 0x05, 0x8b85);
3948         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3949         rtl_writephy(tp, 0x1f, 0x0000);
3950
3951         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3952
3953         /* Modify green table for giga */
3954         rtl_writephy(tp, 0x1f, 0x0005);
3955         rtl_writephy(tp, 0x05, 0x8b54);
3956         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3957         rtl_writephy(tp, 0x05, 0x8b5d);
3958         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3959         rtl_writephy(tp, 0x05, 0x8a7c);
3960         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3961         rtl_writephy(tp, 0x05, 0x8a7f);
3962         rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3963         rtl_writephy(tp, 0x05, 0x8a82);
3964         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3965         rtl_writephy(tp, 0x05, 0x8a85);
3966         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3967         rtl_writephy(tp, 0x05, 0x8a88);
3968         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3969         rtl_writephy(tp, 0x1f, 0x0000);
3970
3971         /* uc same-seed solution */
3972         rtl_writephy(tp, 0x1f, 0x0005);
3973         rtl_writephy(tp, 0x05, 0x8b85);
3974         rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3975         rtl_writephy(tp, 0x1f, 0x0000);
3976
3977         /* eee setting */
3978         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3979         rtl_writephy(tp, 0x1f, 0x0005);
3980         rtl_writephy(tp, 0x05, 0x8b85);
3981         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3982         rtl_writephy(tp, 0x1f, 0x0004);
3983         rtl_writephy(tp, 0x1f, 0x0007);
3984         rtl_writephy(tp, 0x1e, 0x0020);
3985         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3986         rtl_writephy(tp, 0x1f, 0x0000);
3987         rtl_writephy(tp, 0x0d, 0x0007);
3988         rtl_writephy(tp, 0x0e, 0x003c);
3989         rtl_writephy(tp, 0x0d, 0x4007);
3990         rtl_writephy(tp, 0x0e, 0x0000);
3991         rtl_writephy(tp, 0x0d, 0x0000);
3992
3993         /* Green feature */
3994         rtl_writephy(tp, 0x1f, 0x0003);
3995         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3996         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3997         rtl_writephy(tp, 0x1f, 0x0000);
3998 }
3999
4000 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
4001 {
4002         rtl_apply_firmware(tp);
4003
4004         rtl_writephy(tp, 0x1f, 0x0a46);
4005         if (rtl_readphy(tp, 0x10) & 0x0100) {
4006                 rtl_writephy(tp, 0x1f, 0x0bcc);
4007                 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
4008         } else {
4009                 rtl_writephy(tp, 0x1f, 0x0bcc);
4010                 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
4011         }
4012
4013         rtl_writephy(tp, 0x1f, 0x0a46);
4014         if (rtl_readphy(tp, 0x13) & 0x0100) {
4015                 rtl_writephy(tp, 0x1f, 0x0c41);
4016                 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
4017         } else {
4018                 rtl_writephy(tp, 0x1f, 0x0c41);
4019                 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
4020         }
4021
4022         /* Enable PHY auto speed down */
4023         rtl_writephy(tp, 0x1f, 0x0a44);
4024         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
4025
4026         rtl_writephy(tp, 0x1f, 0x0bcc);
4027         rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
4028         rtl_writephy(tp, 0x1f, 0x0a44);
4029         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4030         rtl_writephy(tp, 0x1f, 0x0a43);
4031         rtl_writephy(tp, 0x13, 0x8084);
4032         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4033         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4034
4035         /* EEE auto-fallback function */
4036         rtl_writephy(tp, 0x1f, 0x0a4b);
4037         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
4038
4039         /* Enable UC LPF tune function */
4040         rtl_writephy(tp, 0x1f, 0x0a43);
4041         rtl_writephy(tp, 0x13, 0x8012);
4042         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4043
4044         rtl_writephy(tp, 0x1f, 0x0c42);
4045         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4046
4047         /* Improve SWR Efficiency */
4048         rtl_writephy(tp, 0x1f, 0x0bcd);
4049         rtl_writephy(tp, 0x14, 0x5065);
4050         rtl_writephy(tp, 0x14, 0xd065);
4051         rtl_writephy(tp, 0x1f, 0x0bc8);
4052         rtl_writephy(tp, 0x11, 0x5655);
4053         rtl_writephy(tp, 0x1f, 0x0bcd);
4054         rtl_writephy(tp, 0x14, 0x1065);
4055         rtl_writephy(tp, 0x14, 0x9065);
4056         rtl_writephy(tp, 0x14, 0x1065);
4057
4058         /* Check ALDPS bit, disable it if enabled */
4059         rtl_writephy(tp, 0x1f, 0x0a43);
4060         if (rtl_readphy(tp, 0x10) & 0x0004)
4061                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4062
4063         rtl_writephy(tp, 0x1f, 0x0000);
4064 }
4065
4066 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
4067 {
4068         rtl_apply_firmware(tp);
4069 }
4070
4071 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
4072 {
4073         u16 dout_tapbin;
4074         u32 data;
4075
4076         rtl_apply_firmware(tp);
4077
4078         /* CHN EST parameters adjust - giga master */
4079         rtl_writephy(tp, 0x1f, 0x0a43);
4080         rtl_writephy(tp, 0x13, 0x809b);
4081         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
4082         rtl_writephy(tp, 0x13, 0x80a2);
4083         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
4084         rtl_writephy(tp, 0x13, 0x80a4);
4085         rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
4086         rtl_writephy(tp, 0x13, 0x809c);
4087         rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
4088         rtl_writephy(tp, 0x1f, 0x0000);
4089
4090         /* CHN EST parameters adjust - giga slave */
4091         rtl_writephy(tp, 0x1f, 0x0a43);
4092         rtl_writephy(tp, 0x13, 0x80ad);
4093         rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
4094         rtl_writephy(tp, 0x13, 0x80b4);
4095         rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
4096         rtl_writephy(tp, 0x13, 0x80ac);
4097         rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
4098         rtl_writephy(tp, 0x1f, 0x0000);
4099
4100         /* CHN EST parameters adjust - fnet */
4101         rtl_writephy(tp, 0x1f, 0x0a43);
4102         rtl_writephy(tp, 0x13, 0x808e);
4103         rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
4104         rtl_writephy(tp, 0x13, 0x8090);
4105         rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
4106         rtl_writephy(tp, 0x13, 0x8092);
4107         rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
4108         rtl_writephy(tp, 0x1f, 0x0000);
4109
4110         /* enable R-tune & PGA-retune function */
4111         dout_tapbin = 0;
4112         rtl_writephy(tp, 0x1f, 0x0a46);
4113         data = rtl_readphy(tp, 0x13);
4114         data &= 3;
4115         data <<= 2;
4116         dout_tapbin |= data;
4117         data = rtl_readphy(tp, 0x12);
4118         data &= 0xc000;
4119         data >>= 14;
4120         dout_tapbin |= data;
4121         dout_tapbin = ~(dout_tapbin^0x08);
4122         dout_tapbin <<= 12;
4123         dout_tapbin &= 0xf000;
4124         rtl_writephy(tp, 0x1f, 0x0a43);
4125         rtl_writephy(tp, 0x13, 0x827a);
4126         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
4127         rtl_writephy(tp, 0x13, 0x827b);
4128         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
4129         rtl_writephy(tp, 0x13, 0x827c);
4130         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
4131         rtl_writephy(tp, 0x13, 0x827d);
4132         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
4133
4134         rtl_writephy(tp, 0x1f, 0x0a43);
4135         rtl_writephy(tp, 0x13, 0x0811);
4136         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
4137         rtl_writephy(tp, 0x1f, 0x0a42);
4138         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
4139         rtl_writephy(tp, 0x1f, 0x0000);
4140
4141         /* enable GPHY 10M */
4142         rtl_writephy(tp, 0x1f, 0x0a44);
4143         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
4144         rtl_writephy(tp, 0x1f, 0x0000);
4145
4146         /* SAR ADC performance */
4147         rtl_writephy(tp, 0x1f, 0x0bca);
4148         rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
4149         rtl_writephy(tp, 0x1f, 0x0000);
4150
4151         rtl_writephy(tp, 0x1f, 0x0a43);
4152         rtl_writephy(tp, 0x13, 0x803f);
4153         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
4154         rtl_writephy(tp, 0x13, 0x8047);
4155         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
4156         rtl_writephy(tp, 0x13, 0x804f);
4157         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
4158         rtl_writephy(tp, 0x13, 0x8057);
4159         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
4160         rtl_writephy(tp, 0x13, 0x805f);
4161         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
4162         rtl_writephy(tp, 0x13, 0x8067);
4163         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
4164         rtl_writephy(tp, 0x13, 0x806f);
4165         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
4166         rtl_writephy(tp, 0x1f, 0x0000);
4167
4168         /* disable phy pfm mode */
4169         rtl_writephy(tp, 0x1f, 0x0a44);
4170         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
4171         rtl_writephy(tp, 0x1f, 0x0000);
4172
4173         /* Check ALDPS bit, disable it if enabled */
4174         rtl_writephy(tp, 0x1f, 0x0a43);
4175         if (rtl_readphy(tp, 0x10) & 0x0004)
4176                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4177
4178         rtl_writephy(tp, 0x1f, 0x0000);
4179 }
4180
4181 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
4182 {
4183         u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
4184         u16 rlen;
4185         u32 data;
4186
4187         rtl_apply_firmware(tp);
4188
4189         /* CHIN EST parameter update */
4190         rtl_writephy(tp, 0x1f, 0x0a43);
4191         rtl_writephy(tp, 0x13, 0x808a);
4192         rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
4193         rtl_writephy(tp, 0x1f, 0x0000);
4194
4195         /* enable R-tune & PGA-retune function */
4196         rtl_writephy(tp, 0x1f, 0x0a43);
4197         rtl_writephy(tp, 0x13, 0x0811);
4198         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
4199         rtl_writephy(tp, 0x1f, 0x0a42);
4200         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
4201         rtl_writephy(tp, 0x1f, 0x0000);
4202
4203         /* enable GPHY 10M */
4204         rtl_writephy(tp, 0x1f, 0x0a44);
4205         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
4206         rtl_writephy(tp, 0x1f, 0x0000);
4207
4208         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
4209         data = r8168_mac_ocp_read(tp, 0xdd02);
4210         ioffset_p3 = ((data & 0x80)>>7);
4211         ioffset_p3 <<= 3;
4212
4213         data = r8168_mac_ocp_read(tp, 0xdd00);
4214         ioffset_p3 |= ((data & (0xe000))>>13);
4215         ioffset_p2 = ((data & (0x1e00))>>9);
4216         ioffset_p1 = ((data & (0x01e0))>>5);
4217         ioffset_p0 = ((data & 0x0010)>>4);
4218         ioffset_p0 <<= 3;
4219         ioffset_p0 |= (data & (0x07));
4220         data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
4221
4222         if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
4223             (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
4224                 rtl_writephy(tp, 0x1f, 0x0bcf);
4225                 rtl_writephy(tp, 0x16, data);
4226                 rtl_writephy(tp, 0x1f, 0x0000);
4227         }
4228
4229         /* Modify rlen (TX LPF corner frequency) level */
4230         rtl_writephy(tp, 0x1f, 0x0bcd);
4231         data = rtl_readphy(tp, 0x16);
4232         data &= 0x000f;
4233         rlen = 0;
4234         if (data > 3)
4235                 rlen = data - 3;
4236         data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
4237         rtl_writephy(tp, 0x17, data);
4238         rtl_writephy(tp, 0x1f, 0x0bcd);
4239         rtl_writephy(tp, 0x1f, 0x0000);
4240
4241         /* disable phy pfm mode */
4242         rtl_writephy(tp, 0x1f, 0x0a44);
4243         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
4244         rtl_writephy(tp, 0x1f, 0x0000);
4245
4246         /* Check ALDPS bit, disable it if enabled */
4247         rtl_writephy(tp, 0x1f, 0x0a43);
4248         if (rtl_readphy(tp, 0x10) & 0x0004)
4249                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4250
4251         rtl_writephy(tp, 0x1f, 0x0000);
4252 }
4253
4254 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
4255 {
4256         /* Enable PHY auto speed down */
4257         rtl_writephy(tp, 0x1f, 0x0a44);
4258         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
4259         rtl_writephy(tp, 0x1f, 0x0000);
4260
4261         /* patch 10M & ALDPS */
4262         rtl_writephy(tp, 0x1f, 0x0bcc);
4263         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4264         rtl_writephy(tp, 0x1f, 0x0a44);
4265         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4266         rtl_writephy(tp, 0x1f, 0x0a43);
4267         rtl_writephy(tp, 0x13, 0x8084);
4268         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4269         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4270         rtl_writephy(tp, 0x1f, 0x0000);
4271
4272         /* Enable EEE auto-fallback function */
4273         rtl_writephy(tp, 0x1f, 0x0a4b);
4274         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
4275         rtl_writephy(tp, 0x1f, 0x0000);
4276
4277         /* Enable UC LPF tune function */
4278         rtl_writephy(tp, 0x1f, 0x0a43);
4279         rtl_writephy(tp, 0x13, 0x8012);
4280         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4281         rtl_writephy(tp, 0x1f, 0x0000);
4282
4283         /* set rg_sel_sdm_rate */
4284         rtl_writephy(tp, 0x1f, 0x0c42);
4285         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4286         rtl_writephy(tp, 0x1f, 0x0000);
4287
4288         /* Check ALDPS bit, disable it if enabled */
4289         rtl_writephy(tp, 0x1f, 0x0a43);
4290         if (rtl_readphy(tp, 0x10) & 0x0004)
4291                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4292
4293         rtl_writephy(tp, 0x1f, 0x0000);
4294 }
4295
4296 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
4297 {
4298         /* patch 10M & ALDPS */
4299         rtl_writephy(tp, 0x1f, 0x0bcc);
4300         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4301         rtl_writephy(tp, 0x1f, 0x0a44);
4302         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4303         rtl_writephy(tp, 0x1f, 0x0a43);
4304         rtl_writephy(tp, 0x13, 0x8084);
4305         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4306         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4307         rtl_writephy(tp, 0x1f, 0x0000);
4308
4309         /* Enable UC LPF tune function */
4310         rtl_writephy(tp, 0x1f, 0x0a43);
4311         rtl_writephy(tp, 0x13, 0x8012);
4312         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4313         rtl_writephy(tp, 0x1f, 0x0000);
4314
4315         /* Set rg_sel_sdm_rate */
4316         rtl_writephy(tp, 0x1f, 0x0c42);
4317         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4318         rtl_writephy(tp, 0x1f, 0x0000);
4319
4320         /* Channel estimation parameters */
4321         rtl_writephy(tp, 0x1f, 0x0a43);
4322         rtl_writephy(tp, 0x13, 0x80f3);
4323         rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
4324         rtl_writephy(tp, 0x13, 0x80f0);
4325         rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
4326         rtl_writephy(tp, 0x13, 0x80ef);
4327         rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
4328         rtl_writephy(tp, 0x13, 0x80f6);
4329         rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
4330         rtl_writephy(tp, 0x13, 0x80ec);
4331         rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
4332         rtl_writephy(tp, 0x13, 0x80ed);
4333         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4334         rtl_writephy(tp, 0x13, 0x80f2);
4335         rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
4336         rtl_writephy(tp, 0x13, 0x80f4);
4337         rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
4338         rtl_writephy(tp, 0x1f, 0x0a43);
4339         rtl_writephy(tp, 0x13, 0x8110);
4340         rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
4341         rtl_writephy(tp, 0x13, 0x810f);
4342         rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
4343         rtl_writephy(tp, 0x13, 0x8111);
4344         rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
4345         rtl_writephy(tp, 0x13, 0x8113);
4346         rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
4347         rtl_writephy(tp, 0x13, 0x8115);
4348         rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
4349         rtl_writephy(tp, 0x13, 0x810e);
4350         rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
4351         rtl_writephy(tp, 0x13, 0x810c);
4352         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4353         rtl_writephy(tp, 0x13, 0x810b);
4354         rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
4355         rtl_writephy(tp, 0x1f, 0x0a43);
4356         rtl_writephy(tp, 0x13, 0x80d1);
4357         rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
4358         rtl_writephy(tp, 0x13, 0x80cd);
4359         rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
4360         rtl_writephy(tp, 0x13, 0x80d3);
4361         rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
4362         rtl_writephy(tp, 0x13, 0x80d5);
4363         rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
4364         rtl_writephy(tp, 0x13, 0x80d7);
4365         rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
4366
4367         /* Force PWM-mode */
4368         rtl_writephy(tp, 0x1f, 0x0bcd);
4369         rtl_writephy(tp, 0x14, 0x5065);
4370         rtl_writephy(tp, 0x14, 0xd065);
4371         rtl_writephy(tp, 0x1f, 0x0bc8);
4372         rtl_writephy(tp, 0x12, 0x00ed);
4373         rtl_writephy(tp, 0x1f, 0x0bcd);
4374         rtl_writephy(tp, 0x14, 0x1065);
4375         rtl_writephy(tp, 0x14, 0x9065);
4376         rtl_writephy(tp, 0x14, 0x1065);
4377         rtl_writephy(tp, 0x1f, 0x0000);
4378
4379         /* Check ALDPS bit, disable it if enabled */
4380         rtl_writephy(tp, 0x1f, 0x0a43);
4381         if (rtl_readphy(tp, 0x10) & 0x0004)
4382                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4383
4384         rtl_writephy(tp, 0x1f, 0x0000);
4385 }
4386
4387 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
4388 {
4389         static const struct phy_reg phy_reg_init[] = {
4390                 { 0x1f, 0x0003 },
4391                 { 0x08, 0x441d },
4392                 { 0x01, 0x9100 },
4393                 { 0x1f, 0x0000 }
4394         };
4395
4396         rtl_writephy(tp, 0x1f, 0x0000);
4397         rtl_patchphy(tp, 0x11, 1 << 12);
4398         rtl_patchphy(tp, 0x19, 1 << 13);
4399         rtl_patchphy(tp, 0x10, 1 << 15);
4400
4401         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4402 }
4403
4404 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
4405 {
4406         static const struct phy_reg phy_reg_init[] = {
4407                 { 0x1f, 0x0005 },
4408                 { 0x1a, 0x0000 },
4409                 { 0x1f, 0x0000 },
4410
4411                 { 0x1f, 0x0004 },
4412                 { 0x1c, 0x0000 },
4413                 { 0x1f, 0x0000 },
4414
4415                 { 0x1f, 0x0001 },
4416                 { 0x15, 0x7701 },
4417                 { 0x1f, 0x0000 }
4418         };
4419
4420         /* Disable ALDPS before ram code */
4421         rtl_writephy(tp, 0x1f, 0x0000);
4422         rtl_writephy(tp, 0x18, 0x0310);
4423         msleep(100);
4424
4425         rtl_apply_firmware(tp);
4426
4427         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4428 }
4429
4430 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
4431 {
4432         /* Disable ALDPS before setting firmware */
4433         rtl_writephy(tp, 0x1f, 0x0000);
4434         rtl_writephy(tp, 0x18, 0x0310);
4435         msleep(20);
4436
4437         rtl_apply_firmware(tp);
4438
4439         /* EEE setting */
4440         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4441         rtl_writephy(tp, 0x1f, 0x0004);
4442         rtl_writephy(tp, 0x10, 0x401f);
4443         rtl_writephy(tp, 0x19, 0x7030);
4444         rtl_writephy(tp, 0x1f, 0x0000);
4445 }
4446
4447 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
4448 {
4449         static const struct phy_reg phy_reg_init[] = {
4450                 { 0x1f, 0x0004 },
4451                 { 0x10, 0xc07f },
4452                 { 0x19, 0x7030 },
4453                 { 0x1f, 0x0000 }
4454         };
4455
4456         /* Disable ALDPS before ram code */
4457         rtl_writephy(tp, 0x1f, 0x0000);
4458         rtl_writephy(tp, 0x18, 0x0310);
4459         msleep(100);
4460
4461         rtl_apply_firmware(tp);
4462
4463         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4464         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4465
4466         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4467 }
4468
4469 static void rtl_hw_phy_config(struct net_device *dev)
4470 {
4471         struct rtl8169_private *tp = netdev_priv(dev);
4472
4473         rtl8169_print_mac_version(tp);
4474
4475         switch (tp->mac_version) {
4476         case RTL_GIGA_MAC_VER_01:
4477                 break;
4478         case RTL_GIGA_MAC_VER_02:
4479         case RTL_GIGA_MAC_VER_03:
4480                 rtl8169s_hw_phy_config(tp);
4481                 break;
4482         case RTL_GIGA_MAC_VER_04:
4483                 rtl8169sb_hw_phy_config(tp);
4484                 break;
4485         case RTL_GIGA_MAC_VER_05:
4486                 rtl8169scd_hw_phy_config(tp);
4487                 break;
4488         case RTL_GIGA_MAC_VER_06:
4489                 rtl8169sce_hw_phy_config(tp);
4490                 break;
4491         case RTL_GIGA_MAC_VER_07:
4492         case RTL_GIGA_MAC_VER_08:
4493         case RTL_GIGA_MAC_VER_09:
4494                 rtl8102e_hw_phy_config(tp);
4495                 break;
4496         case RTL_GIGA_MAC_VER_11:
4497                 rtl8168bb_hw_phy_config(tp);
4498                 break;
4499         case RTL_GIGA_MAC_VER_12:
4500                 rtl8168bef_hw_phy_config(tp);
4501                 break;
4502         case RTL_GIGA_MAC_VER_17:
4503                 rtl8168bef_hw_phy_config(tp);
4504                 break;
4505         case RTL_GIGA_MAC_VER_18:
4506                 rtl8168cp_1_hw_phy_config(tp);
4507                 break;
4508         case RTL_GIGA_MAC_VER_19:
4509                 rtl8168c_1_hw_phy_config(tp);
4510                 break;
4511         case RTL_GIGA_MAC_VER_20:
4512                 rtl8168c_2_hw_phy_config(tp);
4513                 break;
4514         case RTL_GIGA_MAC_VER_21:
4515                 rtl8168c_3_hw_phy_config(tp);
4516                 break;
4517         case RTL_GIGA_MAC_VER_22:
4518                 rtl8168c_4_hw_phy_config(tp);
4519                 break;
4520         case RTL_GIGA_MAC_VER_23:
4521         case RTL_GIGA_MAC_VER_24:
4522                 rtl8168cp_2_hw_phy_config(tp);
4523                 break;
4524         case RTL_GIGA_MAC_VER_25:
4525                 rtl8168d_1_hw_phy_config(tp);
4526                 break;
4527         case RTL_GIGA_MAC_VER_26:
4528                 rtl8168d_2_hw_phy_config(tp);
4529                 break;
4530         case RTL_GIGA_MAC_VER_27:
4531                 rtl8168d_3_hw_phy_config(tp);
4532                 break;
4533         case RTL_GIGA_MAC_VER_28:
4534                 rtl8168d_4_hw_phy_config(tp);
4535                 break;
4536         case RTL_GIGA_MAC_VER_29:
4537         case RTL_GIGA_MAC_VER_30:
4538                 rtl8105e_hw_phy_config(tp);
4539                 break;
4540         case RTL_GIGA_MAC_VER_31:
4541                 /* None. */
4542                 break;
4543         case RTL_GIGA_MAC_VER_32:
4544         case RTL_GIGA_MAC_VER_33:
4545                 rtl8168e_1_hw_phy_config(tp);
4546                 break;
4547         case RTL_GIGA_MAC_VER_34:
4548                 rtl8168e_2_hw_phy_config(tp);
4549                 break;
4550         case RTL_GIGA_MAC_VER_35:
4551                 rtl8168f_1_hw_phy_config(tp);
4552                 break;
4553         case RTL_GIGA_MAC_VER_36:
4554                 rtl8168f_2_hw_phy_config(tp);
4555                 break;
4556
4557         case RTL_GIGA_MAC_VER_37:
4558                 rtl8402_hw_phy_config(tp);
4559                 break;
4560
4561         case RTL_GIGA_MAC_VER_38:
4562                 rtl8411_hw_phy_config(tp);
4563                 break;
4564
4565         case RTL_GIGA_MAC_VER_39:
4566                 rtl8106e_hw_phy_config(tp);
4567                 break;
4568
4569         case RTL_GIGA_MAC_VER_40:
4570                 rtl8168g_1_hw_phy_config(tp);
4571                 break;
4572         case RTL_GIGA_MAC_VER_42:
4573         case RTL_GIGA_MAC_VER_43:
4574         case RTL_GIGA_MAC_VER_44:
4575                 rtl8168g_2_hw_phy_config(tp);
4576                 break;
4577         case RTL_GIGA_MAC_VER_45:
4578         case RTL_GIGA_MAC_VER_47:
4579                 rtl8168h_1_hw_phy_config(tp);
4580                 break;
4581         case RTL_GIGA_MAC_VER_46:
4582         case RTL_GIGA_MAC_VER_48:
4583                 rtl8168h_2_hw_phy_config(tp);
4584                 break;
4585
4586         case RTL_GIGA_MAC_VER_49:
4587                 rtl8168ep_1_hw_phy_config(tp);
4588                 break;
4589         case RTL_GIGA_MAC_VER_50:
4590         case RTL_GIGA_MAC_VER_51:
4591                 rtl8168ep_2_hw_phy_config(tp);
4592                 break;
4593
4594         case RTL_GIGA_MAC_VER_41:
4595         default:
4596                 break;
4597         }
4598 }
4599
4600 static void rtl_phy_work(struct rtl8169_private *tp)
4601 {
4602         struct timer_list *timer = &tp->timer;
4603         void __iomem *ioaddr = tp->mmio_addr;
4604         unsigned long timeout = RTL8169_PHY_TIMEOUT;
4605
4606         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
4607
4608         if (tp->phy_reset_pending(tp)) {
4609                 /*
4610                  * A busy loop could burn quite a few cycles on nowadays CPU.
4611                  * Let's delay the execution of the timer for a few ticks.
4612                  */
4613                 timeout = HZ/10;
4614                 goto out_mod_timer;
4615         }
4616
4617         if (tp->link_ok(ioaddr))
4618                 return;
4619
4620         netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
4621
4622         tp->phy_reset_enable(tp);
4623
4624 out_mod_timer:
4625         mod_timer(timer, jiffies + timeout);
4626 }
4627
4628 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4629 {
4630         if (!test_and_set_bit(flag, tp->wk.flags))
4631                 schedule_work(&tp->wk.work);
4632 }
4633
4634 static void rtl8169_phy_timer(struct timer_list *t)
4635 {
4636         struct rtl8169_private *tp = from_timer(tp, t, timer);
4637
4638         rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
4639 }
4640
4641 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
4642                                   void __iomem *ioaddr)
4643 {
4644         iounmap(ioaddr);
4645         pci_release_regions(pdev);
4646         pci_clear_mwi(pdev);
4647         pci_disable_device(pdev);
4648         free_netdev(dev);
4649 }
4650
4651 DECLARE_RTL_COND(rtl_phy_reset_cond)
4652 {
4653         return tp->phy_reset_pending(tp);
4654 }
4655
4656 static void rtl8169_phy_reset(struct net_device *dev,
4657                               struct rtl8169_private *tp)
4658 {
4659         tp->phy_reset_enable(tp);
4660         rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
4661 }
4662
4663 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4664 {
4665         void __iomem *ioaddr = tp->mmio_addr;
4666
4667         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4668             (RTL_R8(PHYstatus) & TBI_Enable);
4669 }
4670
4671 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4672 {
4673         void __iomem *ioaddr = tp->mmio_addr;
4674
4675         rtl_hw_phy_config(dev);
4676
4677         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4678                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4679                 RTL_W8(0x82, 0x01);
4680         }
4681
4682         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4683
4684         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4685                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4686
4687         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4688                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4689                 RTL_W8(0x82, 0x01);
4690                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4691                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4692         }
4693
4694         rtl8169_phy_reset(dev, tp);
4695
4696         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4697                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4698                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4699                           (tp->mii.supports_gmii ?
4700                            ADVERTISED_1000baseT_Half |
4701                            ADVERTISED_1000baseT_Full : 0));
4702
4703         if (rtl_tbi_enabled(tp))
4704                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4705 }
4706
4707 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4708 {
4709         void __iomem *ioaddr = tp->mmio_addr;
4710
4711         rtl_lock_work(tp);
4712
4713         RTL_W8(Cfg9346, Cfg9346_Unlock);
4714
4715         RTL_W32(MAC4, addr[4] | addr[5] << 8);
4716         RTL_R32(MAC4);
4717
4718         RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4719         RTL_R32(MAC0);
4720
4721         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4722                 rtl_rar_exgmac_set(tp, addr);
4723
4724         RTL_W8(Cfg9346, Cfg9346_Lock);
4725
4726         rtl_unlock_work(tp);
4727 }
4728
4729 static int rtl_set_mac_address(struct net_device *dev, void *p)
4730 {
4731         struct rtl8169_private *tp = netdev_priv(dev);
4732         struct device *d = &tp->pci_dev->dev;
4733         struct sockaddr *addr = p;
4734
4735         if (!is_valid_ether_addr(addr->sa_data))
4736                 return -EADDRNOTAVAIL;
4737
4738         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4739
4740         pm_runtime_get_noresume(d);
4741
4742         if (pm_runtime_active(d))
4743                 rtl_rar_set(tp, dev->dev_addr);
4744
4745         pm_runtime_put_noidle(d);
4746
4747         return 0;
4748 }
4749
4750 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4751 {
4752         struct rtl8169_private *tp = netdev_priv(dev);
4753         struct mii_ioctl_data *data = if_mii(ifr);
4754
4755         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
4756 }
4757
4758 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
4759                           struct mii_ioctl_data *data, int cmd)
4760 {
4761         switch (cmd) {
4762         case SIOCGMIIPHY:
4763                 data->phy_id = 32; /* Internal PHY */
4764                 return 0;
4765
4766         case SIOCGMIIREG:
4767                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
4768                 return 0;
4769
4770         case SIOCSMIIREG:
4771                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
4772                 return 0;
4773         }
4774         return -EOPNOTSUPP;
4775 }
4776
4777 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
4778 {
4779         return -EOPNOTSUPP;
4780 }
4781
4782 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
4783 {
4784         if (tp->features & RTL_FEATURE_MSI) {
4785                 pci_disable_msi(pdev);
4786                 tp->features &= ~RTL_FEATURE_MSI;
4787         }
4788 }
4789
4790 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4791 {
4792         struct mdio_ops *ops = &tp->mdio_ops;
4793
4794         switch (tp->mac_version) {
4795         case RTL_GIGA_MAC_VER_27:
4796                 ops->write      = r8168dp_1_mdio_write;
4797                 ops->read       = r8168dp_1_mdio_read;
4798                 break;
4799         case RTL_GIGA_MAC_VER_28:
4800         case RTL_GIGA_MAC_VER_31:
4801                 ops->write      = r8168dp_2_mdio_write;
4802                 ops->read       = r8168dp_2_mdio_read;
4803                 break;
4804         case RTL_GIGA_MAC_VER_40:
4805         case RTL_GIGA_MAC_VER_41:
4806         case RTL_GIGA_MAC_VER_42:
4807         case RTL_GIGA_MAC_VER_43:
4808         case RTL_GIGA_MAC_VER_44:
4809         case RTL_GIGA_MAC_VER_45:
4810         case RTL_GIGA_MAC_VER_46:
4811         case RTL_GIGA_MAC_VER_47:
4812         case RTL_GIGA_MAC_VER_48:
4813         case RTL_GIGA_MAC_VER_49:
4814         case RTL_GIGA_MAC_VER_50:
4815         case RTL_GIGA_MAC_VER_51:
4816                 ops->write      = r8168g_mdio_write;
4817                 ops->read       = r8168g_mdio_read;
4818                 break;
4819         default:
4820                 ops->write      = r8169_mdio_write;
4821                 ops->read       = r8169_mdio_read;
4822                 break;
4823         }
4824 }
4825
4826 static void rtl_speed_down(struct rtl8169_private *tp)
4827 {
4828         u32 adv;
4829         int lpa;
4830
4831         rtl_writephy(tp, 0x1f, 0x0000);
4832         lpa = rtl_readphy(tp, MII_LPA);
4833
4834         if (lpa & (LPA_10HALF | LPA_10FULL))
4835                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
4836         else if (lpa & (LPA_100HALF | LPA_100FULL))
4837                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4838                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4839         else
4840                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4841                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4842                       (tp->mii.supports_gmii ?
4843                        ADVERTISED_1000baseT_Half |
4844                        ADVERTISED_1000baseT_Full : 0);
4845
4846         rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4847                           adv);
4848 }
4849
4850 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4851 {
4852         void __iomem *ioaddr = tp->mmio_addr;
4853
4854         switch (tp->mac_version) {
4855         case RTL_GIGA_MAC_VER_25:
4856         case RTL_GIGA_MAC_VER_26:
4857         case RTL_GIGA_MAC_VER_29:
4858         case RTL_GIGA_MAC_VER_30:
4859         case RTL_GIGA_MAC_VER_32:
4860         case RTL_GIGA_MAC_VER_33:
4861         case RTL_GIGA_MAC_VER_34:
4862         case RTL_GIGA_MAC_VER_37:
4863         case RTL_GIGA_MAC_VER_38:
4864         case RTL_GIGA_MAC_VER_39:
4865         case RTL_GIGA_MAC_VER_40:
4866         case RTL_GIGA_MAC_VER_41:
4867         case RTL_GIGA_MAC_VER_42:
4868         case RTL_GIGA_MAC_VER_43:
4869         case RTL_GIGA_MAC_VER_44:
4870         case RTL_GIGA_MAC_VER_45:
4871         case RTL_GIGA_MAC_VER_46:
4872         case RTL_GIGA_MAC_VER_47:
4873         case RTL_GIGA_MAC_VER_48:
4874         case RTL_GIGA_MAC_VER_49:
4875         case RTL_GIGA_MAC_VER_50:
4876         case RTL_GIGA_MAC_VER_51:
4877                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
4878                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4879                 break;
4880         default:
4881                 break;
4882         }
4883 }
4884
4885 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4886 {
4887         if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
4888                 return false;
4889
4890         rtl_speed_down(tp);
4891         rtl_wol_suspend_quirk(tp);
4892
4893         return true;
4894 }
4895
4896 static void r810x_phy_power_down(struct rtl8169_private *tp)
4897 {
4898         rtl_writephy(tp, 0x1f, 0x0000);
4899         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4900 }
4901
4902 static void r810x_phy_power_up(struct rtl8169_private *tp)
4903 {
4904         rtl_writephy(tp, 0x1f, 0x0000);
4905         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4906 }
4907
4908 static void r810x_pll_power_down(struct rtl8169_private *tp)
4909 {
4910         void __iomem *ioaddr = tp->mmio_addr;
4911
4912         if (rtl_wol_pll_power_down(tp))
4913                 return;
4914
4915         r810x_phy_power_down(tp);
4916
4917         switch (tp->mac_version) {
4918         case RTL_GIGA_MAC_VER_07:
4919         case RTL_GIGA_MAC_VER_08:
4920         case RTL_GIGA_MAC_VER_09:
4921         case RTL_GIGA_MAC_VER_10:
4922         case RTL_GIGA_MAC_VER_13:
4923         case RTL_GIGA_MAC_VER_16:
4924                 break;
4925         default:
4926                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4927                 break;
4928         }
4929 }
4930
4931 static void r810x_pll_power_up(struct rtl8169_private *tp)
4932 {
4933         void __iomem *ioaddr = tp->mmio_addr;
4934
4935         r810x_phy_power_up(tp);
4936
4937         switch (tp->mac_version) {
4938         case RTL_GIGA_MAC_VER_07:
4939         case RTL_GIGA_MAC_VER_08:
4940         case RTL_GIGA_MAC_VER_09:
4941         case RTL_GIGA_MAC_VER_10:
4942         case RTL_GIGA_MAC_VER_13:
4943         case RTL_GIGA_MAC_VER_16:
4944                 break;
4945         case RTL_GIGA_MAC_VER_47:
4946         case RTL_GIGA_MAC_VER_48:
4947                 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4948                 break;
4949         default:
4950                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4951                 break;
4952         }
4953 }
4954
4955 static void r8168_phy_power_up(struct rtl8169_private *tp)
4956 {
4957         rtl_writephy(tp, 0x1f, 0x0000);
4958         switch (tp->mac_version) {
4959         case RTL_GIGA_MAC_VER_11:
4960         case RTL_GIGA_MAC_VER_12:
4961         case RTL_GIGA_MAC_VER_17:
4962         case RTL_GIGA_MAC_VER_18:
4963         case RTL_GIGA_MAC_VER_19:
4964         case RTL_GIGA_MAC_VER_20:
4965         case RTL_GIGA_MAC_VER_21:
4966         case RTL_GIGA_MAC_VER_22:
4967         case RTL_GIGA_MAC_VER_23:
4968         case RTL_GIGA_MAC_VER_24:
4969         case RTL_GIGA_MAC_VER_25:
4970         case RTL_GIGA_MAC_VER_26:
4971         case RTL_GIGA_MAC_VER_27:
4972         case RTL_GIGA_MAC_VER_28:
4973         case RTL_GIGA_MAC_VER_31:
4974                 rtl_writephy(tp, 0x0e, 0x0000);
4975                 break;
4976         default:
4977                 break;
4978         }
4979         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4980 }
4981
4982 static void r8168_phy_power_down(struct rtl8169_private *tp)
4983 {
4984         rtl_writephy(tp, 0x1f, 0x0000);
4985         switch (tp->mac_version) {
4986         case RTL_GIGA_MAC_VER_32:
4987         case RTL_GIGA_MAC_VER_33:
4988         case RTL_GIGA_MAC_VER_40:
4989         case RTL_GIGA_MAC_VER_41:
4990                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4991                 break;
4992
4993         case RTL_GIGA_MAC_VER_11:
4994         case RTL_GIGA_MAC_VER_12:
4995         case RTL_GIGA_MAC_VER_17:
4996         case RTL_GIGA_MAC_VER_18:
4997         case RTL_GIGA_MAC_VER_19:
4998         case RTL_GIGA_MAC_VER_20:
4999         case RTL_GIGA_MAC_VER_21:
5000         case RTL_GIGA_MAC_VER_22:
5001         case RTL_GIGA_MAC_VER_23:
5002         case RTL_GIGA_MAC_VER_24:
5003         case RTL_GIGA_MAC_VER_25:
5004         case RTL_GIGA_MAC_VER_26:
5005         case RTL_GIGA_MAC_VER_27:
5006         case RTL_GIGA_MAC_VER_28:
5007         case RTL_GIGA_MAC_VER_31:
5008                 rtl_writephy(tp, 0x0e, 0x0200);
5009         default:
5010                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
5011                 break;
5012         }
5013 }
5014
5015 static void r8168_pll_power_down(struct rtl8169_private *tp)
5016 {
5017         void __iomem *ioaddr = tp->mmio_addr;
5018
5019         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
5020              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
5021              tp->mac_version == RTL_GIGA_MAC_VER_31 ||
5022              tp->mac_version == RTL_GIGA_MAC_VER_49 ||
5023              tp->mac_version == RTL_GIGA_MAC_VER_50 ||
5024              tp->mac_version == RTL_GIGA_MAC_VER_51) &&
5025             r8168_check_dash(tp)) {
5026                 return;
5027         }
5028
5029         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
5030              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
5031             (RTL_R16(CPlusCmd) & ASF)) {
5032                 return;
5033         }
5034
5035         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
5036             tp->mac_version == RTL_GIGA_MAC_VER_33)
5037                 rtl_ephy_write(tp, 0x19, 0xff64);
5038
5039         if (rtl_wol_pll_power_down(tp))
5040                 return;
5041
5042         r8168_phy_power_down(tp);
5043
5044         switch (tp->mac_version) {
5045         case RTL_GIGA_MAC_VER_25:
5046         case RTL_GIGA_MAC_VER_26:
5047         case RTL_GIGA_MAC_VER_27:
5048         case RTL_GIGA_MAC_VER_28:
5049         case RTL_GIGA_MAC_VER_31:
5050         case RTL_GIGA_MAC_VER_32:
5051         case RTL_GIGA_MAC_VER_33:
5052         case RTL_GIGA_MAC_VER_44:
5053         case RTL_GIGA_MAC_VER_45:
5054         case RTL_GIGA_MAC_VER_46:
5055         case RTL_GIGA_MAC_VER_50:
5056         case RTL_GIGA_MAC_VER_51:
5057                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
5058                 break;
5059         case RTL_GIGA_MAC_VER_40:
5060         case RTL_GIGA_MAC_VER_41:
5061         case RTL_GIGA_MAC_VER_49:
5062                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
5063                              0xfc000000, ERIAR_EXGMAC);
5064                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
5065                 break;
5066         }
5067 }
5068
5069 static void r8168_pll_power_up(struct rtl8169_private *tp)
5070 {
5071         void __iomem *ioaddr = tp->mmio_addr;
5072
5073         switch (tp->mac_version) {
5074         case RTL_GIGA_MAC_VER_25:
5075         case RTL_GIGA_MAC_VER_26:
5076         case RTL_GIGA_MAC_VER_27:
5077         case RTL_GIGA_MAC_VER_28:
5078         case RTL_GIGA_MAC_VER_31:
5079         case RTL_GIGA_MAC_VER_32:
5080         case RTL_GIGA_MAC_VER_33:
5081                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
5082                 break;
5083         case RTL_GIGA_MAC_VER_44:
5084         case RTL_GIGA_MAC_VER_45:
5085         case RTL_GIGA_MAC_VER_46:
5086         case RTL_GIGA_MAC_VER_50:
5087         case RTL_GIGA_MAC_VER_51:
5088                 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
5089                 break;
5090         case RTL_GIGA_MAC_VER_40:
5091         case RTL_GIGA_MAC_VER_41:
5092         case RTL_GIGA_MAC_VER_49:
5093                 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
5094                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
5095                              0x00000000, ERIAR_EXGMAC);
5096                 break;
5097         }
5098
5099         r8168_phy_power_up(tp);
5100 }
5101
5102 static void rtl_generic_op(struct rtl8169_private *tp,
5103                            void (*op)(struct rtl8169_private *))
5104 {
5105         if (op)
5106                 op(tp);
5107 }
5108
5109 static void rtl_pll_power_down(struct rtl8169_private *tp)
5110 {
5111         rtl_generic_op(tp, tp->pll_power_ops.down);
5112 }
5113
5114 static void rtl_pll_power_up(struct rtl8169_private *tp)
5115 {
5116         rtl_generic_op(tp, tp->pll_power_ops.up);
5117 }
5118
5119 static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
5120 {
5121         struct pll_power_ops *ops = &tp->pll_power_ops;
5122
5123         switch (tp->mac_version) {
5124         case RTL_GIGA_MAC_VER_07:
5125         case RTL_GIGA_MAC_VER_08:
5126         case RTL_GIGA_MAC_VER_09:
5127         case RTL_GIGA_MAC_VER_10:
5128         case RTL_GIGA_MAC_VER_16:
5129         case RTL_GIGA_MAC_VER_29:
5130         case RTL_GIGA_MAC_VER_30:
5131         case RTL_GIGA_MAC_VER_37:
5132         case RTL_GIGA_MAC_VER_39:
5133         case RTL_GIGA_MAC_VER_43:
5134         case RTL_GIGA_MAC_VER_47:
5135         case RTL_GIGA_MAC_VER_48:
5136                 ops->down       = r810x_pll_power_down;
5137                 ops->up         = r810x_pll_power_up;
5138                 break;
5139
5140         case RTL_GIGA_MAC_VER_11:
5141         case RTL_GIGA_MAC_VER_12:
5142         case RTL_GIGA_MAC_VER_17:
5143         case RTL_GIGA_MAC_VER_18:
5144         case RTL_GIGA_MAC_VER_19:
5145         case RTL_GIGA_MAC_VER_20:
5146         case RTL_GIGA_MAC_VER_21:
5147         case RTL_GIGA_MAC_VER_22:
5148         case RTL_GIGA_MAC_VER_23:
5149         case RTL_GIGA_MAC_VER_24:
5150         case RTL_GIGA_MAC_VER_25:
5151         case RTL_GIGA_MAC_VER_26:
5152         case RTL_GIGA_MAC_VER_27:
5153         case RTL_GIGA_MAC_VER_28:
5154         case RTL_GIGA_MAC_VER_31:
5155         case RTL_GIGA_MAC_VER_32:
5156         case RTL_GIGA_MAC_VER_33:
5157         case RTL_GIGA_MAC_VER_34:
5158         case RTL_GIGA_MAC_VER_35:
5159         case RTL_GIGA_MAC_VER_36:
5160         case RTL_GIGA_MAC_VER_38:
5161         case RTL_GIGA_MAC_VER_40:
5162         case RTL_GIGA_MAC_VER_41:
5163         case RTL_GIGA_MAC_VER_42:
5164         case RTL_GIGA_MAC_VER_44:
5165         case RTL_GIGA_MAC_VER_45:
5166         case RTL_GIGA_MAC_VER_46:
5167         case RTL_GIGA_MAC_VER_49:
5168         case RTL_GIGA_MAC_VER_50:
5169         case RTL_GIGA_MAC_VER_51:
5170                 ops->down       = r8168_pll_power_down;
5171                 ops->up         = r8168_pll_power_up;
5172                 break;
5173
5174         default:
5175                 ops->down       = NULL;
5176                 ops->up         = NULL;
5177                 break;
5178         }
5179 }
5180
5181 static void rtl_init_rxcfg(struct rtl8169_private *tp)
5182 {
5183         void __iomem *ioaddr = tp->mmio_addr;
5184
5185         switch (tp->mac_version) {
5186         case RTL_GIGA_MAC_VER_01:
5187         case RTL_GIGA_MAC_VER_02:
5188         case RTL_GIGA_MAC_VER_03:
5189         case RTL_GIGA_MAC_VER_04:
5190         case RTL_GIGA_MAC_VER_05:
5191         case RTL_GIGA_MAC_VER_06:
5192         case RTL_GIGA_MAC_VER_10:
5193         case RTL_GIGA_MAC_VER_11:
5194         case RTL_GIGA_MAC_VER_12:
5195         case RTL_GIGA_MAC_VER_13:
5196         case RTL_GIGA_MAC_VER_14:
5197         case RTL_GIGA_MAC_VER_15:
5198         case RTL_GIGA_MAC_VER_16:
5199         case RTL_GIGA_MAC_VER_17:
5200                 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
5201                 break;
5202         case RTL_GIGA_MAC_VER_18:
5203         case RTL_GIGA_MAC_VER_19:
5204         case RTL_GIGA_MAC_VER_20:
5205         case RTL_GIGA_MAC_VER_21:
5206         case RTL_GIGA_MAC_VER_22:
5207         case RTL_GIGA_MAC_VER_23:
5208         case RTL_GIGA_MAC_VER_24:
5209         case RTL_GIGA_MAC_VER_34:
5210         case RTL_GIGA_MAC_VER_35:
5211                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
5212                 break;
5213         case RTL_GIGA_MAC_VER_40:
5214         case RTL_GIGA_MAC_VER_41:
5215         case RTL_GIGA_MAC_VER_42:
5216         case RTL_GIGA_MAC_VER_43:
5217         case RTL_GIGA_MAC_VER_44:
5218         case RTL_GIGA_MAC_VER_45:
5219         case RTL_GIGA_MAC_VER_46:
5220         case RTL_GIGA_MAC_VER_47:
5221         case RTL_GIGA_MAC_VER_48:
5222         case RTL_GIGA_MAC_VER_49:
5223         case RTL_GIGA_MAC_VER_50:
5224         case RTL_GIGA_MAC_VER_51:
5225                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
5226                 break;
5227         default:
5228                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
5229                 break;
5230         }
5231 }
5232
5233 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
5234 {
5235         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
5236 }
5237
5238 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
5239 {
5240         void __iomem *ioaddr = tp->mmio_addr;
5241
5242         RTL_W8(Cfg9346, Cfg9346_Unlock);
5243         rtl_generic_op(tp, tp->jumbo_ops.enable);
5244         RTL_W8(Cfg9346, Cfg9346_Lock);
5245 }
5246
5247 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
5248 {
5249         void __iomem *ioaddr = tp->mmio_addr;
5250
5251         RTL_W8(Cfg9346, Cfg9346_Unlock);
5252         rtl_generic_op(tp, tp->jumbo_ops.disable);
5253         RTL_W8(Cfg9346, Cfg9346_Lock);
5254 }
5255
5256 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
5257 {
5258         void __iomem *ioaddr = tp->mmio_addr;
5259
5260         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5261         RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
5262         rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
5263 }
5264
5265 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
5266 {
5267         void __iomem *ioaddr = tp->mmio_addr;
5268
5269         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5270         RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
5271         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5272 }
5273
5274 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
5275 {
5276         void __iomem *ioaddr = tp->mmio_addr;
5277
5278         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5279 }
5280
5281 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
5282 {
5283         void __iomem *ioaddr = tp->mmio_addr;
5284
5285         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5286 }
5287
5288 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
5289 {
5290         void __iomem *ioaddr = tp->mmio_addr;
5291
5292         RTL_W8(MaxTxPacketSize, 0x3f);
5293         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5294         RTL_W8(Config4, RTL_R8(Config4) | 0x01);
5295         rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
5296 }
5297
5298 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
5299 {
5300         void __iomem *ioaddr = tp->mmio_addr;
5301
5302         RTL_W8(MaxTxPacketSize, 0x0c);
5303         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5304         RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
5305         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5306 }
5307
5308 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
5309 {
5310         rtl_tx_performance_tweak(tp->pci_dev,
5311                 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
5312 }
5313
5314 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
5315 {
5316         rtl_tx_performance_tweak(tp->pci_dev,
5317                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
5318 }
5319
5320 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
5321 {
5322         void __iomem *ioaddr = tp->mmio_addr;
5323
5324         r8168b_0_hw_jumbo_enable(tp);
5325
5326         RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
5327 }
5328
5329 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
5330 {
5331         void __iomem *ioaddr = tp->mmio_addr;
5332
5333         r8168b_0_hw_jumbo_disable(tp);
5334
5335         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5336 }
5337
5338 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
5339 {
5340         struct jumbo_ops *ops = &tp->jumbo_ops;
5341
5342         switch (tp->mac_version) {
5343         case RTL_GIGA_MAC_VER_11:
5344                 ops->disable    = r8168b_0_hw_jumbo_disable;
5345                 ops->enable     = r8168b_0_hw_jumbo_enable;
5346                 break;
5347         case RTL_GIGA_MAC_VER_12:
5348         case RTL_GIGA_MAC_VER_17:
5349                 ops->disable    = r8168b_1_hw_jumbo_disable;
5350                 ops->enable     = r8168b_1_hw_jumbo_enable;
5351                 break;
5352         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
5353         case RTL_GIGA_MAC_VER_19:
5354         case RTL_GIGA_MAC_VER_20:
5355         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
5356         case RTL_GIGA_MAC_VER_22:
5357         case RTL_GIGA_MAC_VER_23:
5358         case RTL_GIGA_MAC_VER_24:
5359         case RTL_GIGA_MAC_VER_25:
5360         case RTL_GIGA_MAC_VER_26:
5361                 ops->disable    = r8168c_hw_jumbo_disable;
5362                 ops->enable     = r8168c_hw_jumbo_enable;
5363                 break;
5364         case RTL_GIGA_MAC_VER_27:
5365         case RTL_GIGA_MAC_VER_28:
5366                 ops->disable    = r8168dp_hw_jumbo_disable;
5367                 ops->enable     = r8168dp_hw_jumbo_enable;
5368                 break;
5369         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
5370         case RTL_GIGA_MAC_VER_32:
5371         case RTL_GIGA_MAC_VER_33:
5372         case RTL_GIGA_MAC_VER_34:
5373                 ops->disable    = r8168e_hw_jumbo_disable;
5374                 ops->enable     = r8168e_hw_jumbo_enable;
5375                 break;
5376
5377         /*
5378          * No action needed for jumbo frames with 8169.
5379          * No jumbo for 810x at all.
5380          */
5381         case RTL_GIGA_MAC_VER_40:
5382         case RTL_GIGA_MAC_VER_41:
5383         case RTL_GIGA_MAC_VER_42:
5384         case RTL_GIGA_MAC_VER_43:
5385         case RTL_GIGA_MAC_VER_44:
5386         case RTL_GIGA_MAC_VER_45:
5387         case RTL_GIGA_MAC_VER_46:
5388         case RTL_GIGA_MAC_VER_47:
5389         case RTL_GIGA_MAC_VER_48:
5390         case RTL_GIGA_MAC_VER_49:
5391         case RTL_GIGA_MAC_VER_50:
5392         case RTL_GIGA_MAC_VER_51:
5393         default:
5394                 ops->disable    = NULL;
5395                 ops->enable     = NULL;
5396                 break;
5397         }
5398 }
5399
5400 DECLARE_RTL_COND(rtl_chipcmd_cond)
5401 {
5402         void __iomem *ioaddr = tp->mmio_addr;
5403
5404         return RTL_R8(ChipCmd) & CmdReset;
5405 }
5406
5407 static void rtl_hw_reset(struct rtl8169_private *tp)
5408 {
5409         void __iomem *ioaddr = tp->mmio_addr;
5410
5411         RTL_W8(ChipCmd, CmdReset);
5412
5413         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
5414 }
5415
5416 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
5417 {
5418         struct rtl_fw *rtl_fw;
5419         const char *name;
5420         int rc = -ENOMEM;
5421
5422         name = rtl_lookup_firmware_name(tp);
5423         if (!name)
5424                 goto out_no_firmware;
5425
5426         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
5427         if (!rtl_fw)
5428                 goto err_warn;
5429
5430         rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
5431         if (rc < 0)
5432                 goto err_free;
5433
5434         rc = rtl_check_firmware(tp, rtl_fw);
5435         if (rc < 0)
5436                 goto err_release_firmware;
5437
5438         tp->rtl_fw = rtl_fw;
5439 out:
5440         return;
5441
5442 err_release_firmware:
5443         release_firmware(rtl_fw->fw);
5444 err_free:
5445         kfree(rtl_fw);
5446 err_warn:
5447         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
5448                    name, rc);
5449 out_no_firmware:
5450         tp->rtl_fw = NULL;
5451         goto out;
5452 }
5453
5454 static void rtl_request_firmware(struct rtl8169_private *tp)
5455 {
5456         if (IS_ERR(tp->rtl_fw))
5457                 rtl_request_uncached_firmware(tp);
5458 }
5459
5460 static void rtl_rx_close(struct rtl8169_private *tp)
5461 {
5462         void __iomem *ioaddr = tp->mmio_addr;
5463
5464         RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
5465 }
5466
5467 DECLARE_RTL_COND(rtl_npq_cond)
5468 {
5469         void __iomem *ioaddr = tp->mmio_addr;
5470
5471         return RTL_R8(TxPoll) & NPQ;
5472 }
5473
5474 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
5475 {
5476         void __iomem *ioaddr = tp->mmio_addr;
5477
5478         return RTL_R32(TxConfig) & TXCFG_EMPTY;
5479 }
5480
5481 static void rtl8169_hw_reset(struct rtl8169_private *tp)
5482 {
5483         void __iomem *ioaddr = tp->mmio_addr;
5484
5485         /* Disable interrupts */
5486         rtl8169_irq_mask_and_ack(tp);
5487
5488         rtl_rx_close(tp);
5489
5490         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
5491             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
5492             tp->mac_version == RTL_GIGA_MAC_VER_31) {
5493                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
5494         } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
5495                    tp->mac_version == RTL_GIGA_MAC_VER_35 ||
5496                    tp->mac_version == RTL_GIGA_MAC_VER_36 ||
5497                    tp->mac_version == RTL_GIGA_MAC_VER_37 ||
5498                    tp->mac_version == RTL_GIGA_MAC_VER_38 ||
5499                    tp->mac_version == RTL_GIGA_MAC_VER_40 ||
5500                    tp->mac_version == RTL_GIGA_MAC_VER_41 ||
5501                    tp->mac_version == RTL_GIGA_MAC_VER_42 ||
5502                    tp->mac_version == RTL_GIGA_MAC_VER_43 ||
5503                    tp->mac_version == RTL_GIGA_MAC_VER_44 ||
5504                    tp->mac_version == RTL_GIGA_MAC_VER_45 ||
5505                    tp->mac_version == RTL_GIGA_MAC_VER_46 ||
5506                    tp->mac_version == RTL_GIGA_MAC_VER_47 ||
5507                    tp->mac_version == RTL_GIGA_MAC_VER_48 ||
5508                    tp->mac_version == RTL_GIGA_MAC_VER_49 ||
5509                    tp->mac_version == RTL_GIGA_MAC_VER_50 ||
5510                    tp->mac_version == RTL_GIGA_MAC_VER_51) {
5511                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5512                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
5513         } else {
5514                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5515                 udelay(100);
5516         }
5517
5518         rtl_hw_reset(tp);
5519 }
5520
5521 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
5522 {
5523         void __iomem *ioaddr = tp->mmio_addr;
5524
5525         /* Set DMA burst size and Interframe Gap Time */
5526         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
5527                 (InterFrameGap << TxInterFrameGapShift));
5528 }
5529
5530 static void rtl_hw_start(struct net_device *dev)
5531 {
5532         struct rtl8169_private *tp = netdev_priv(dev);
5533
5534         tp->hw_start(dev);
5535
5536         rtl_irq_enable_all(tp);
5537 }
5538
5539 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
5540                                          void __iomem *ioaddr)
5541 {
5542         /*
5543          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
5544          * register to be written before TxDescAddrLow to work.
5545          * Switching from MMIO to I/O access fixes the issue as well.
5546          */
5547         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
5548         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
5549         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
5550         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
5551 }
5552
5553 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
5554 {
5555         u16 cmd;
5556
5557         cmd = RTL_R16(CPlusCmd);
5558         RTL_W16(CPlusCmd, cmd);
5559         return cmd;
5560 }
5561
5562 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
5563 {
5564         /* Low hurts. Let's disable the filtering. */
5565         RTL_W16(RxMaxSize, rx_buf_sz + 1);
5566 }
5567
5568 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
5569 {
5570         static const struct rtl_cfg2_info {
5571                 u32 mac_version;
5572                 u32 clk;
5573                 u32 val;
5574         } cfg2_info [] = {
5575                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
5576                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
5577                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
5578                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
5579         };
5580         const struct rtl_cfg2_info *p = cfg2_info;
5581         unsigned int i;
5582         u32 clk;
5583
5584         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
5585         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
5586                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
5587                         RTL_W32(0x7c, p->val);
5588                         break;
5589                 }
5590         }
5591 }
5592
5593 static void rtl_set_rx_mode(struct net_device *dev)
5594 {
5595         struct rtl8169_private *tp = netdev_priv(dev);
5596         void __iomem *ioaddr = tp->mmio_addr;
5597         u32 mc_filter[2];       /* Multicast hash filter */
5598         int rx_mode;
5599         u32 tmp = 0;
5600
5601         if (dev->flags & IFF_PROMISC) {
5602                 /* Unconditionally log net taps. */
5603                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5604                 rx_mode =
5605                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5606                     AcceptAllPhys;
5607                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5608         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5609                    (dev->flags & IFF_ALLMULTI)) {
5610                 /* Too many to filter perfectly -- accept all multicasts. */
5611                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5612                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5613         } else {
5614                 struct netdev_hw_addr *ha;
5615
5616                 rx_mode = AcceptBroadcast | AcceptMyPhys;
5617                 mc_filter[1] = mc_filter[0] = 0;
5618                 netdev_for_each_mc_addr(ha, dev) {
5619                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5620                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5621                         rx_mode |= AcceptMulticast;
5622                 }
5623         }
5624
5625         if (dev->features & NETIF_F_RXALL)
5626                 rx_mode |= (AcceptErr | AcceptRunt);
5627
5628         tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
5629
5630         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5631                 u32 data = mc_filter[0];
5632
5633                 mc_filter[0] = swab32(mc_filter[1]);
5634                 mc_filter[1] = swab32(data);
5635         }
5636
5637         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
5638                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5639
5640         RTL_W32(MAR0 + 4, mc_filter[1]);
5641         RTL_W32(MAR0 + 0, mc_filter[0]);
5642
5643         RTL_W32(RxConfig, tmp);
5644 }
5645
5646 static void rtl_hw_start_8169(struct net_device *dev)
5647 {
5648         struct rtl8169_private *tp = netdev_priv(dev);
5649         void __iomem *ioaddr = tp->mmio_addr;
5650         struct pci_dev *pdev = tp->pci_dev;
5651
5652         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
5653                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
5654                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
5655         }
5656
5657         RTL_W8(Cfg9346, Cfg9346_Unlock);
5658         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5659             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5660             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5661             tp->mac_version == RTL_GIGA_MAC_VER_04)
5662                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5663
5664         rtl_init_rxcfg(tp);
5665
5666         RTL_W8(EarlyTxThres, NoEarlyTx);
5667
5668         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5669
5670         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5671             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5672             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5673             tp->mac_version == RTL_GIGA_MAC_VER_04)
5674                 rtl_set_rx_tx_config_registers(tp);
5675
5676         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
5677
5678         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5679             tp->mac_version == RTL_GIGA_MAC_VER_03) {
5680                 dprintk("Set MAC Reg C+CR Offset 0xe0. "
5681                         "Bit-3 and bit-14 MUST be 1\n");
5682                 tp->cp_cmd |= (1 << 14);
5683         }
5684
5685         RTL_W16(CPlusCmd, tp->cp_cmd);
5686
5687         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
5688
5689         /*
5690          * Undocumented corner. Supposedly:
5691          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
5692          */
5693         RTL_W16(IntrMitigate, 0x0000);
5694
5695         rtl_set_rx_tx_desc_registers(tp, ioaddr);
5696
5697         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
5698             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
5699             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
5700             tp->mac_version != RTL_GIGA_MAC_VER_04) {
5701                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5702                 rtl_set_rx_tx_config_registers(tp);
5703         }
5704
5705         RTL_W8(Cfg9346, Cfg9346_Lock);
5706
5707         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5708         RTL_R8(IntrMask);
5709
5710         RTL_W32(RxMissed, 0);
5711
5712         rtl_set_rx_mode(dev);
5713
5714         /* no early-rx interrupts */
5715         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5716 }
5717
5718 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
5719 {
5720         if (tp->csi_ops.write)
5721                 tp->csi_ops.write(tp, addr, value);
5722 }
5723
5724 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
5725 {
5726         return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
5727 }
5728
5729 static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
5730 {
5731         u32 csi;
5732
5733         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
5734         rtl_csi_write(tp, 0x070c, csi | bits);
5735 }
5736
5737 static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
5738 {
5739         rtl_csi_access_enable(tp, 0x17000000);
5740 }
5741
5742 static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
5743 {
5744         rtl_csi_access_enable(tp, 0x27000000);
5745 }
5746
5747 DECLARE_RTL_COND(rtl_csiar_cond)
5748 {
5749         void __iomem *ioaddr = tp->mmio_addr;
5750
5751         return RTL_R32(CSIAR) & CSIAR_FLAG;
5752 }
5753
5754 static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
5755 {
5756         void __iomem *ioaddr = tp->mmio_addr;
5757
5758         RTL_W32(CSIDR, value);
5759         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5760                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5761
5762         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5763 }
5764
5765 static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
5766 {
5767         void __iomem *ioaddr = tp->mmio_addr;
5768
5769         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
5770                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5771
5772         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5773                 RTL_R32(CSIDR) : ~0;
5774 }
5775
5776 static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
5777 {
5778         void __iomem *ioaddr = tp->mmio_addr;
5779
5780         RTL_W32(CSIDR, value);
5781         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5782                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5783                 CSIAR_FUNC_NIC);
5784
5785         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5786 }
5787
5788 static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
5789 {
5790         void __iomem *ioaddr = tp->mmio_addr;
5791
5792         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
5793                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5794
5795         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5796                 RTL_R32(CSIDR) : ~0;
5797 }
5798
5799 static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
5800 {
5801         void __iomem *ioaddr = tp->mmio_addr;
5802
5803         RTL_W32(CSIDR, value);
5804         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5805                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5806                 CSIAR_FUNC_NIC2);
5807
5808         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5809 }
5810
5811 static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
5812 {
5813         void __iomem *ioaddr = tp->mmio_addr;
5814
5815         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
5816                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5817
5818         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5819                 RTL_R32(CSIDR) : ~0;
5820 }
5821
5822 static void rtl_init_csi_ops(struct rtl8169_private *tp)
5823 {
5824         struct csi_ops *ops = &tp->csi_ops;
5825
5826         switch (tp->mac_version) {
5827         case RTL_GIGA_MAC_VER_01:
5828         case RTL_GIGA_MAC_VER_02:
5829         case RTL_GIGA_MAC_VER_03:
5830         case RTL_GIGA_MAC_VER_04:
5831         case RTL_GIGA_MAC_VER_05:
5832         case RTL_GIGA_MAC_VER_06:
5833         case RTL_GIGA_MAC_VER_10:
5834         case RTL_GIGA_MAC_VER_11:
5835         case RTL_GIGA_MAC_VER_12:
5836         case RTL_GIGA_MAC_VER_13:
5837         case RTL_GIGA_MAC_VER_14:
5838         case RTL_GIGA_MAC_VER_15:
5839         case RTL_GIGA_MAC_VER_16:
5840         case RTL_GIGA_MAC_VER_17:
5841                 ops->write      = NULL;
5842                 ops->read       = NULL;
5843                 break;
5844
5845         case RTL_GIGA_MAC_VER_37:
5846         case RTL_GIGA_MAC_VER_38:
5847                 ops->write      = r8402_csi_write;
5848                 ops->read       = r8402_csi_read;
5849                 break;
5850
5851         case RTL_GIGA_MAC_VER_44:
5852                 ops->write      = r8411_csi_write;
5853                 ops->read       = r8411_csi_read;
5854                 break;
5855
5856         default:
5857                 ops->write      = r8169_csi_write;
5858                 ops->read       = r8169_csi_read;
5859                 break;
5860         }
5861 }
5862
5863 struct ephy_info {
5864         unsigned int offset;
5865         u16 mask;
5866         u16 bits;
5867 };
5868
5869 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
5870                           int len)
5871 {
5872         u16 w;
5873
5874         while (len-- > 0) {
5875                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
5876                 rtl_ephy_write(tp, e->offset, w);
5877                 e++;
5878         }
5879 }
5880
5881 static void rtl_disable_clock_request(struct pci_dev *pdev)
5882 {
5883         pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
5884                                    PCI_EXP_LNKCTL_CLKREQ_EN);
5885 }
5886
5887 static void rtl_enable_clock_request(struct pci_dev *pdev)
5888 {
5889         pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
5890                                  PCI_EXP_LNKCTL_CLKREQ_EN);
5891 }
5892
5893 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
5894 {
5895         void __iomem *ioaddr = tp->mmio_addr;
5896         u8 data;
5897
5898         data = RTL_R8(Config3);
5899
5900         if (enable)
5901                 data |= Rdy_to_L23;
5902         else
5903                 data &= ~Rdy_to_L23;
5904
5905         RTL_W8(Config3, data);
5906 }
5907
5908 #define R8168_CPCMD_QUIRK_MASK (\
5909         EnableBist | \
5910         Mac_dbgo_oe | \
5911         Force_half_dup | \
5912         Force_rxflow_en | \
5913         Force_txflow_en | \
5914         Cxpl_dbg_sel | \
5915         ASF | \
5916         PktCntrDisable | \
5917         Mac_dbgo_sel)
5918
5919 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
5920 {
5921         void __iomem *ioaddr = tp->mmio_addr;
5922         struct pci_dev *pdev = tp->pci_dev;
5923
5924         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5925
5926         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5927
5928         if (tp->dev->mtu <= ETH_DATA_LEN) {
5929                 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
5930                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5931         }
5932 }
5933
5934 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
5935 {
5936         void __iomem *ioaddr = tp->mmio_addr;
5937
5938         rtl_hw_start_8168bb(tp);
5939
5940         RTL_W8(MaxTxPacketSize, TxPacketMax);
5941
5942         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5943 }
5944
5945 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
5946 {
5947         void __iomem *ioaddr = tp->mmio_addr;
5948         struct pci_dev *pdev = tp->pci_dev;
5949
5950         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
5951
5952         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5953
5954         if (tp->dev->mtu <= ETH_DATA_LEN)
5955                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5956
5957         rtl_disable_clock_request(pdev);
5958
5959         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5960 }
5961
5962 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
5963 {
5964         static const struct ephy_info e_info_8168cp[] = {
5965                 { 0x01, 0,      0x0001 },
5966                 { 0x02, 0x0800, 0x1000 },
5967                 { 0x03, 0,      0x0042 },
5968                 { 0x06, 0x0080, 0x0000 },
5969                 { 0x07, 0,      0x2000 }
5970         };
5971
5972         rtl_csi_access_enable_2(tp);
5973
5974         rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
5975
5976         __rtl_hw_start_8168cp(tp);
5977 }
5978
5979 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
5980 {
5981         void __iomem *ioaddr = tp->mmio_addr;
5982         struct pci_dev *pdev = tp->pci_dev;
5983
5984         rtl_csi_access_enable_2(tp);
5985
5986         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5987
5988         if (tp->dev->mtu <= ETH_DATA_LEN)
5989                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5990
5991         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5992 }
5993
5994 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
5995 {
5996         void __iomem *ioaddr = tp->mmio_addr;
5997         struct pci_dev *pdev = tp->pci_dev;
5998
5999         rtl_csi_access_enable_2(tp);
6000
6001         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6002
6003         /* Magic. */
6004         RTL_W8(DBG_REG, 0x20);
6005
6006         RTL_W8(MaxTxPacketSize, TxPacketMax);
6007
6008         if (tp->dev->mtu <= ETH_DATA_LEN)
6009                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6010
6011         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
6012 }
6013
6014 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
6015 {
6016         void __iomem *ioaddr = tp->mmio_addr;
6017         static const struct ephy_info e_info_8168c_1[] = {
6018                 { 0x02, 0x0800, 0x1000 },
6019                 { 0x03, 0,      0x0002 },
6020                 { 0x06, 0x0080, 0x0000 }
6021         };
6022
6023         rtl_csi_access_enable_2(tp);
6024
6025         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
6026
6027         rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
6028
6029         __rtl_hw_start_8168cp(tp);
6030 }
6031
6032 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
6033 {
6034         static const struct ephy_info e_info_8168c_2[] = {
6035                 { 0x01, 0,      0x0001 },
6036                 { 0x03, 0x0400, 0x0220 }
6037         };
6038
6039         rtl_csi_access_enable_2(tp);
6040
6041         rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
6042
6043         __rtl_hw_start_8168cp(tp);
6044 }
6045
6046 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
6047 {
6048         rtl_hw_start_8168c_2(tp);
6049 }
6050
6051 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
6052 {
6053         rtl_csi_access_enable_2(tp);
6054
6055         __rtl_hw_start_8168cp(tp);
6056 }
6057
6058 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
6059 {
6060         void __iomem *ioaddr = tp->mmio_addr;
6061         struct pci_dev *pdev = tp->pci_dev;
6062
6063         rtl_csi_access_enable_2(tp);
6064
6065         rtl_disable_clock_request(pdev);
6066
6067         RTL_W8(MaxTxPacketSize, TxPacketMax);
6068
6069         if (tp->dev->mtu <= ETH_DATA_LEN)
6070                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6071
6072         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
6073 }
6074
6075 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
6076 {
6077         void __iomem *ioaddr = tp->mmio_addr;
6078         struct pci_dev *pdev = tp->pci_dev;
6079
6080         rtl_csi_access_enable_1(tp);
6081
6082         if (tp->dev->mtu <= ETH_DATA_LEN)
6083                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6084
6085         RTL_W8(MaxTxPacketSize, TxPacketMax);
6086
6087         rtl_disable_clock_request(pdev);
6088 }
6089
6090 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
6091 {
6092         void __iomem *ioaddr = tp->mmio_addr;
6093         struct pci_dev *pdev = tp->pci_dev;
6094         static const struct ephy_info e_info_8168d_4[] = {
6095                 { 0x0b, 0x0000, 0x0048 },
6096                 { 0x19, 0x0020, 0x0050 },
6097                 { 0x0c, 0x0100, 0x0020 }
6098         };
6099
6100         rtl_csi_access_enable_1(tp);
6101
6102         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6103
6104         RTL_W8(MaxTxPacketSize, TxPacketMax);
6105
6106         rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
6107
6108         rtl_enable_clock_request(pdev);
6109 }
6110
6111 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
6112 {
6113         void __iomem *ioaddr = tp->mmio_addr;
6114         struct pci_dev *pdev = tp->pci_dev;
6115         static const struct ephy_info e_info_8168e_1[] = {
6116                 { 0x00, 0x0200, 0x0100 },
6117                 { 0x00, 0x0000, 0x0004 },
6118                 { 0x06, 0x0002, 0x0001 },
6119                 { 0x06, 0x0000, 0x0030 },
6120                 { 0x07, 0x0000, 0x2000 },
6121                 { 0x00, 0x0000, 0x0020 },
6122                 { 0x03, 0x5800, 0x2000 },
6123                 { 0x03, 0x0000, 0x0001 },
6124                 { 0x01, 0x0800, 0x1000 },
6125                 { 0x07, 0x0000, 0x4000 },
6126                 { 0x1e, 0x0000, 0x2000 },
6127                 { 0x19, 0xffff, 0xfe6c },
6128                 { 0x0a, 0x0000, 0x0040 }
6129         };
6130
6131         rtl_csi_access_enable_2(tp);
6132
6133         rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
6134
6135         if (tp->dev->mtu <= ETH_DATA_LEN)
6136                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6137
6138         RTL_W8(MaxTxPacketSize, TxPacketMax);
6139
6140         rtl_disable_clock_request(pdev);
6141
6142         /* Reset tx FIFO pointer */
6143         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
6144         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
6145
6146         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
6147 }
6148
6149 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
6150 {
6151         void __iomem *ioaddr = tp->mmio_addr;
6152         struct pci_dev *pdev = tp->pci_dev;
6153         static const struct ephy_info e_info_8168e_2[] = {
6154                 { 0x09, 0x0000, 0x0080 },
6155                 { 0x19, 0x0000, 0x0224 }
6156         };
6157
6158         rtl_csi_access_enable_1(tp);
6159
6160         rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
6161
6162         if (tp->dev->mtu <= ETH_DATA_LEN)
6163                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6164
6165         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6166         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6167         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
6168         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6169         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
6170         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
6171         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
6172         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
6173
6174         RTL_W8(MaxTxPacketSize, EarlySize);
6175
6176         rtl_disable_clock_request(pdev);
6177
6178         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6179         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6180
6181         /* Adjust EEE LED frequency */
6182         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6183
6184         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
6185         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
6186         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
6187 }
6188
6189 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
6190 {
6191         void __iomem *ioaddr = tp->mmio_addr;
6192         struct pci_dev *pdev = tp->pci_dev;
6193
6194         rtl_csi_access_enable_2(tp);
6195
6196         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6197
6198         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6199         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6200         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
6201         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6202         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6203         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6204         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
6205         rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
6206         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
6207         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
6208
6209         RTL_W8(MaxTxPacketSize, EarlySize);
6210
6211         rtl_disable_clock_request(pdev);
6212
6213         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6214         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6215         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
6216         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
6217         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
6218 }
6219
6220 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
6221 {
6222         void __iomem *ioaddr = tp->mmio_addr;
6223         static const struct ephy_info e_info_8168f_1[] = {
6224                 { 0x06, 0x00c0, 0x0020 },
6225                 { 0x08, 0x0001, 0x0002 },
6226                 { 0x09, 0x0000, 0x0080 },
6227                 { 0x19, 0x0000, 0x0224 }
6228         };
6229
6230         rtl_hw_start_8168f(tp);
6231
6232         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
6233
6234         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
6235
6236         /* Adjust EEE LED frequency */
6237         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6238 }
6239
6240 static void rtl_hw_start_8411(struct rtl8169_private *tp)
6241 {
6242         static const struct ephy_info e_info_8168f_1[] = {
6243                 { 0x06, 0x00c0, 0x0020 },
6244                 { 0x0f, 0xffff, 0x5200 },
6245                 { 0x1e, 0x0000, 0x4000 },
6246                 { 0x19, 0x0000, 0x0224 }
6247         };
6248
6249         rtl_hw_start_8168f(tp);
6250         rtl_pcie_state_l2l3_enable(tp, false);
6251
6252         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
6253
6254         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
6255 }
6256
6257 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
6258 {
6259         void __iomem *ioaddr = tp->mmio_addr;
6260         struct pci_dev *pdev = tp->pci_dev;
6261
6262         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6263
6264         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
6265         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6266         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6267         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6268
6269         rtl_csi_access_enable_1(tp);
6270
6271         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6272
6273         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6274         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6275         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
6276
6277         RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6278         RTL_W8(MaxTxPacketSize, EarlySize);
6279
6280         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6281         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6282
6283         /* Adjust EEE LED frequency */
6284         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6285
6286         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6287         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6288
6289         rtl_pcie_state_l2l3_enable(tp, false);
6290 }
6291
6292 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
6293 {
6294         void __iomem *ioaddr = tp->mmio_addr;
6295         static const struct ephy_info e_info_8168g_1[] = {
6296                 { 0x00, 0x0000, 0x0008 },
6297                 { 0x0c, 0x37d0, 0x0820 },
6298                 { 0x1e, 0x0000, 0x0001 },
6299                 { 0x19, 0x8000, 0x0000 }
6300         };
6301
6302         rtl_hw_start_8168g(tp);
6303
6304         /* disable aspm and clock request before access ephy */
6305         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6306         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6307         rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
6308 }
6309
6310 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
6311 {
6312         void __iomem *ioaddr = tp->mmio_addr;
6313         static const struct ephy_info e_info_8168g_2[] = {
6314                 { 0x00, 0x0000, 0x0008 },
6315                 { 0x0c, 0x3df0, 0x0200 },
6316                 { 0x19, 0xffff, 0xfc00 },
6317                 { 0x1e, 0xffff, 0x20eb }
6318         };
6319
6320         rtl_hw_start_8168g(tp);
6321
6322         /* disable aspm and clock request before access ephy */
6323         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6324         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6325         rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
6326 }
6327
6328 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
6329 {
6330         void __iomem *ioaddr = tp->mmio_addr;
6331         static const struct ephy_info e_info_8411_2[] = {
6332                 { 0x00, 0x0000, 0x0008 },
6333                 { 0x0c, 0x3df0, 0x0200 },
6334                 { 0x0f, 0xffff, 0x5200 },
6335                 { 0x19, 0x0020, 0x0000 },
6336                 { 0x1e, 0x0000, 0x2000 }
6337         };
6338
6339         rtl_hw_start_8168g(tp);
6340
6341         /* disable aspm and clock request before access ephy */
6342         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6343         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6344         rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
6345 }
6346
6347 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
6348 {
6349         void __iomem *ioaddr = tp->mmio_addr;
6350         struct pci_dev *pdev = tp->pci_dev;
6351         int rg_saw_cnt;
6352         u32 data;
6353         static const struct ephy_info e_info_8168h_1[] = {
6354                 { 0x1e, 0x0800, 0x0001 },
6355                 { 0x1d, 0x0000, 0x0800 },
6356                 { 0x05, 0xffff, 0x2089 },
6357                 { 0x06, 0xffff, 0x5881 },
6358                 { 0x04, 0xffff, 0x154a },
6359                 { 0x01, 0xffff, 0x068b }
6360         };
6361
6362         /* disable aspm and clock request before access ephy */
6363         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6364         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6365         rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
6366
6367         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6368
6369         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6370         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6371         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6372         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6373
6374         rtl_csi_access_enable_1(tp);
6375
6376         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6377
6378         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6379         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6380
6381         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
6382
6383         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
6384
6385         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6386
6387         RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6388         RTL_W8(MaxTxPacketSize, EarlySize);
6389
6390         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6391         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6392
6393         /* Adjust EEE LED frequency */
6394         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6395
6396         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6397         RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6398
6399         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6400
6401         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6402
6403         rtl_pcie_state_l2l3_enable(tp, false);
6404
6405         rtl_writephy(tp, 0x1f, 0x0c42);
6406         rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
6407         rtl_writephy(tp, 0x1f, 0x0000);
6408         if (rg_saw_cnt > 0) {
6409                 u16 sw_cnt_1ms_ini;
6410
6411                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
6412                 sw_cnt_1ms_ini &= 0x0fff;
6413                 data = r8168_mac_ocp_read(tp, 0xd412);
6414                 data &= ~0x0fff;
6415                 data |= sw_cnt_1ms_ini;
6416                 r8168_mac_ocp_write(tp, 0xd412, data);
6417         }
6418
6419         data = r8168_mac_ocp_read(tp, 0xe056);
6420         data &= ~0xf0;
6421         data |= 0x70;
6422         r8168_mac_ocp_write(tp, 0xe056, data);
6423
6424         data = r8168_mac_ocp_read(tp, 0xe052);
6425         data &= ~0x6000;
6426         data |= 0x8008;
6427         r8168_mac_ocp_write(tp, 0xe052, data);
6428
6429         data = r8168_mac_ocp_read(tp, 0xe0d6);
6430         data &= ~0x01ff;
6431         data |= 0x017f;
6432         r8168_mac_ocp_write(tp, 0xe0d6, data);
6433
6434         data = r8168_mac_ocp_read(tp, 0xd420);
6435         data &= ~0x0fff;
6436         data |= 0x047f;
6437         r8168_mac_ocp_write(tp, 0xd420, data);
6438
6439         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
6440         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
6441         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
6442         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
6443 }
6444
6445 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
6446 {
6447         void __iomem *ioaddr = tp->mmio_addr;
6448         struct pci_dev *pdev = tp->pci_dev;
6449
6450         rtl8168ep_stop_cmac(tp);
6451
6452         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6453
6454         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6455         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
6456         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
6457         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6458
6459         rtl_csi_access_enable_1(tp);
6460
6461         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6462
6463         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6464         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6465
6466         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
6467
6468         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6469
6470         RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6471         RTL_W8(MaxTxPacketSize, EarlySize);
6472
6473         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6474         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6475
6476         /* Adjust EEE LED frequency */
6477         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6478
6479         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6480
6481         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6482
6483         rtl_pcie_state_l2l3_enable(tp, false);
6484 }
6485
6486 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
6487 {
6488         void __iomem *ioaddr = tp->mmio_addr;
6489         static const struct ephy_info e_info_8168ep_1[] = {
6490                 { 0x00, 0xffff, 0x10ab },
6491                 { 0x06, 0xffff, 0xf030 },
6492                 { 0x08, 0xffff, 0x2006 },
6493                 { 0x0d, 0xffff, 0x1666 },
6494                 { 0x0c, 0x3ff0, 0x0000 }
6495         };
6496
6497         /* disable aspm and clock request before access ephy */
6498         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6499         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6500         rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
6501
6502         rtl_hw_start_8168ep(tp);
6503 }
6504
6505 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
6506 {
6507         void __iomem *ioaddr = tp->mmio_addr;
6508         static const struct ephy_info e_info_8168ep_2[] = {
6509                 { 0x00, 0xffff, 0x10a3 },
6510                 { 0x19, 0xffff, 0xfc00 },
6511                 { 0x1e, 0xffff, 0x20ea }
6512         };
6513
6514         /* disable aspm and clock request before access ephy */
6515         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6516         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6517         rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
6518
6519         rtl_hw_start_8168ep(tp);
6520
6521         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6522         RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6523 }
6524
6525 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
6526 {
6527         void __iomem *ioaddr = tp->mmio_addr;
6528         u32 data;
6529         static const struct ephy_info e_info_8168ep_3[] = {
6530                 { 0x00, 0xffff, 0x10a3 },
6531                 { 0x19, 0xffff, 0x7c00 },
6532                 { 0x1e, 0xffff, 0x20eb },
6533                 { 0x0d, 0xffff, 0x1666 }
6534         };
6535
6536         /* disable aspm and clock request before access ephy */
6537         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6538         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6539         rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
6540
6541         rtl_hw_start_8168ep(tp);
6542
6543         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6544         RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6545
6546         data = r8168_mac_ocp_read(tp, 0xd3e2);
6547         data &= 0xf000;
6548         data |= 0x0271;
6549         r8168_mac_ocp_write(tp, 0xd3e2, data);
6550
6551         data = r8168_mac_ocp_read(tp, 0xd3e4);
6552         data &= 0xff00;
6553         r8168_mac_ocp_write(tp, 0xd3e4, data);
6554
6555         data = r8168_mac_ocp_read(tp, 0xe860);
6556         data |= 0x0080;
6557         r8168_mac_ocp_write(tp, 0xe860, data);
6558 }
6559
6560 static void rtl_hw_start_8168(struct net_device *dev)
6561 {
6562         struct rtl8169_private *tp = netdev_priv(dev);
6563         void __iomem *ioaddr = tp->mmio_addr;
6564
6565         RTL_W8(Cfg9346, Cfg9346_Unlock);
6566
6567         RTL_W8(MaxTxPacketSize, TxPacketMax);
6568
6569         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6570
6571         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
6572
6573         RTL_W16(CPlusCmd, tp->cp_cmd);
6574
6575         RTL_W16(IntrMitigate, 0x5151);
6576
6577         /* Work around for RxFIFO overflow. */
6578         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
6579                 tp->event_slow |= RxFIFOOver | PCSTimeout;
6580                 tp->event_slow &= ~RxOverflow;
6581         }
6582
6583         rtl_set_rx_tx_desc_registers(tp, ioaddr);
6584
6585         rtl_set_rx_tx_config_registers(tp);
6586
6587         RTL_R8(IntrMask);
6588
6589         switch (tp->mac_version) {
6590         case RTL_GIGA_MAC_VER_11:
6591                 rtl_hw_start_8168bb(tp);
6592                 break;
6593
6594         case RTL_GIGA_MAC_VER_12:
6595         case RTL_GIGA_MAC_VER_17:
6596                 rtl_hw_start_8168bef(tp);
6597                 break;
6598
6599         case RTL_GIGA_MAC_VER_18:
6600                 rtl_hw_start_8168cp_1(tp);
6601                 break;
6602
6603         case RTL_GIGA_MAC_VER_19:
6604                 rtl_hw_start_8168c_1(tp);
6605                 break;
6606
6607         case RTL_GIGA_MAC_VER_20:
6608                 rtl_hw_start_8168c_2(tp);
6609                 break;
6610
6611         case RTL_GIGA_MAC_VER_21:
6612                 rtl_hw_start_8168c_3(tp);
6613                 break;
6614
6615         case RTL_GIGA_MAC_VER_22:
6616                 rtl_hw_start_8168c_4(tp);
6617                 break;
6618
6619         case RTL_GIGA_MAC_VER_23:
6620                 rtl_hw_start_8168cp_2(tp);
6621                 break;
6622
6623         case RTL_GIGA_MAC_VER_24:
6624                 rtl_hw_start_8168cp_3(tp);
6625                 break;
6626
6627         case RTL_GIGA_MAC_VER_25:
6628         case RTL_GIGA_MAC_VER_26:
6629         case RTL_GIGA_MAC_VER_27:
6630                 rtl_hw_start_8168d(tp);
6631                 break;
6632
6633         case RTL_GIGA_MAC_VER_28:
6634                 rtl_hw_start_8168d_4(tp);
6635                 break;
6636
6637         case RTL_GIGA_MAC_VER_31:
6638                 rtl_hw_start_8168dp(tp);
6639                 break;
6640
6641         case RTL_GIGA_MAC_VER_32:
6642         case RTL_GIGA_MAC_VER_33:
6643                 rtl_hw_start_8168e_1(tp);
6644                 break;
6645         case RTL_GIGA_MAC_VER_34:
6646                 rtl_hw_start_8168e_2(tp);
6647                 break;
6648
6649         case RTL_GIGA_MAC_VER_35:
6650         case RTL_GIGA_MAC_VER_36:
6651                 rtl_hw_start_8168f_1(tp);
6652                 break;
6653
6654         case RTL_GIGA_MAC_VER_38:
6655                 rtl_hw_start_8411(tp);
6656                 break;
6657
6658         case RTL_GIGA_MAC_VER_40:
6659         case RTL_GIGA_MAC_VER_41:
6660                 rtl_hw_start_8168g_1(tp);
6661                 break;
6662         case RTL_GIGA_MAC_VER_42:
6663                 rtl_hw_start_8168g_2(tp);
6664                 break;
6665
6666         case RTL_GIGA_MAC_VER_44:
6667                 rtl_hw_start_8411_2(tp);
6668                 break;
6669
6670         case RTL_GIGA_MAC_VER_45:
6671         case RTL_GIGA_MAC_VER_46:
6672                 rtl_hw_start_8168h_1(tp);
6673                 break;
6674
6675         case RTL_GIGA_MAC_VER_49:
6676                 rtl_hw_start_8168ep_1(tp);
6677                 break;
6678
6679         case RTL_GIGA_MAC_VER_50:
6680                 rtl_hw_start_8168ep_2(tp);
6681                 break;
6682
6683         case RTL_GIGA_MAC_VER_51:
6684                 rtl_hw_start_8168ep_3(tp);
6685                 break;
6686
6687         default:
6688                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
6689                         dev->name, tp->mac_version);
6690                 break;
6691         }
6692
6693         RTL_W8(Cfg9346, Cfg9346_Lock);
6694
6695         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6696
6697         rtl_set_rx_mode(dev);
6698
6699         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6700 }
6701
6702 #define R810X_CPCMD_QUIRK_MASK (\
6703         EnableBist | \
6704         Mac_dbgo_oe | \
6705         Force_half_dup | \
6706         Force_rxflow_en | \
6707         Force_txflow_en | \
6708         Cxpl_dbg_sel | \
6709         ASF | \
6710         PktCntrDisable | \
6711         Mac_dbgo_sel)
6712
6713 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
6714 {
6715         void __iomem *ioaddr = tp->mmio_addr;
6716         struct pci_dev *pdev = tp->pci_dev;
6717         static const struct ephy_info e_info_8102e_1[] = {
6718                 { 0x01, 0, 0x6e65 },
6719                 { 0x02, 0, 0x091f },
6720                 { 0x03, 0, 0xc2f9 },
6721                 { 0x06, 0, 0xafb5 },
6722                 { 0x07, 0, 0x0e00 },
6723                 { 0x19, 0, 0xec80 },
6724                 { 0x01, 0, 0x2e65 },
6725                 { 0x01, 0, 0x6e65 }
6726         };
6727         u8 cfg1;
6728
6729         rtl_csi_access_enable_2(tp);
6730
6731         RTL_W8(DBG_REG, FIX_NAK_1);
6732
6733         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6734
6735         RTL_W8(Config1,
6736                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
6737         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6738
6739         cfg1 = RTL_R8(Config1);
6740         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
6741                 RTL_W8(Config1, cfg1 & ~LEDS0);
6742
6743         rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
6744 }
6745
6746 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
6747 {
6748         void __iomem *ioaddr = tp->mmio_addr;
6749         struct pci_dev *pdev = tp->pci_dev;
6750
6751         rtl_csi_access_enable_2(tp);
6752
6753         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6754
6755         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
6756         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6757 }
6758
6759 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
6760 {
6761         rtl_hw_start_8102e_2(tp);
6762
6763         rtl_ephy_write(tp, 0x03, 0xc2f9);
6764 }
6765
6766 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
6767 {
6768         void __iomem *ioaddr = tp->mmio_addr;
6769         static const struct ephy_info e_info_8105e_1[] = {
6770                 { 0x07, 0, 0x4000 },
6771                 { 0x19, 0, 0x0200 },
6772                 { 0x19, 0, 0x0020 },
6773                 { 0x1e, 0, 0x2000 },
6774                 { 0x03, 0, 0x0001 },
6775                 { 0x19, 0, 0x0100 },
6776                 { 0x19, 0, 0x0004 },
6777                 { 0x0a, 0, 0x0020 }
6778         };
6779
6780         /* Force LAN exit from ASPM if Rx/Tx are not idle */
6781         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6782
6783         /* Disable Early Tally Counter */
6784         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
6785
6786         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6787         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
6788
6789         rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
6790
6791         rtl_pcie_state_l2l3_enable(tp, false);
6792 }
6793
6794 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
6795 {
6796         rtl_hw_start_8105e_1(tp);
6797         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
6798 }
6799
6800 static void rtl_hw_start_8402(struct rtl8169_private *tp)
6801 {
6802         void __iomem *ioaddr = tp->mmio_addr;
6803         static const struct ephy_info e_info_8402[] = {
6804                 { 0x19, 0xffff, 0xff64 },
6805                 { 0x1e, 0, 0x4000 }
6806         };
6807
6808         rtl_csi_access_enable_2(tp);
6809
6810         /* Force LAN exit from ASPM if Rx/Tx are not idle */
6811         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6812
6813         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6814         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6815
6816         rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
6817
6818         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
6819
6820         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
6821         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
6822         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6823         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6824         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6825         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6826         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
6827
6828         rtl_pcie_state_l2l3_enable(tp, false);
6829 }
6830
6831 static void rtl_hw_start_8106(struct rtl8169_private *tp)
6832 {
6833         void __iomem *ioaddr = tp->mmio_addr;
6834
6835         /* Force LAN exit from ASPM if Rx/Tx are not idle */
6836         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6837
6838         RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
6839         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6840         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6841
6842         rtl_pcie_state_l2l3_enable(tp, false);
6843 }
6844
6845 static void rtl_hw_start_8101(struct net_device *dev)
6846 {
6847         struct rtl8169_private *tp = netdev_priv(dev);
6848         void __iomem *ioaddr = tp->mmio_addr;
6849         struct pci_dev *pdev = tp->pci_dev;
6850
6851         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
6852                 tp->event_slow &= ~RxFIFOOver;
6853
6854         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
6855             tp->mac_version == RTL_GIGA_MAC_VER_16)
6856                 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
6857                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
6858
6859         RTL_W8(Cfg9346, Cfg9346_Unlock);
6860
6861         RTL_W8(MaxTxPacketSize, TxPacketMax);
6862
6863         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6864
6865         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
6866         RTL_W16(CPlusCmd, tp->cp_cmd);
6867
6868         rtl_set_rx_tx_desc_registers(tp, ioaddr);
6869
6870         rtl_set_rx_tx_config_registers(tp);
6871
6872         switch (tp->mac_version) {
6873         case RTL_GIGA_MAC_VER_07:
6874                 rtl_hw_start_8102e_1(tp);
6875                 break;
6876
6877         case RTL_GIGA_MAC_VER_08:
6878                 rtl_hw_start_8102e_3(tp);
6879                 break;
6880
6881         case RTL_GIGA_MAC_VER_09:
6882                 rtl_hw_start_8102e_2(tp);
6883                 break;
6884
6885         case RTL_GIGA_MAC_VER_29:
6886                 rtl_hw_start_8105e_1(tp);
6887                 break;
6888         case RTL_GIGA_MAC_VER_30:
6889                 rtl_hw_start_8105e_2(tp);
6890                 break;
6891
6892         case RTL_GIGA_MAC_VER_37:
6893                 rtl_hw_start_8402(tp);
6894                 break;
6895
6896         case RTL_GIGA_MAC_VER_39:
6897                 rtl_hw_start_8106(tp);
6898                 break;
6899         case RTL_GIGA_MAC_VER_43:
6900                 rtl_hw_start_8168g_2(tp);
6901                 break;
6902         case RTL_GIGA_MAC_VER_47:
6903         case RTL_GIGA_MAC_VER_48:
6904                 rtl_hw_start_8168h_1(tp);
6905                 break;
6906         }
6907
6908         RTL_W8(Cfg9346, Cfg9346_Lock);
6909
6910         RTL_W16(IntrMitigate, 0x0000);
6911
6912         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6913
6914         rtl_set_rx_mode(dev);
6915
6916         RTL_R8(IntrMask);
6917
6918         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6919 }
6920
6921 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
6922 {
6923         struct rtl8169_private *tp = netdev_priv(dev);
6924
6925         if (new_mtu > ETH_DATA_LEN)
6926                 rtl_hw_jumbo_enable(tp);
6927         else
6928                 rtl_hw_jumbo_disable(tp);
6929
6930         dev->mtu = new_mtu;
6931         netdev_update_features(dev);
6932
6933         return 0;
6934 }
6935
6936 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
6937 {
6938         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
6939         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
6940 }
6941
6942 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
6943                                      void **data_buff, struct RxDesc *desc)
6944 {
6945         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
6946                          DMA_FROM_DEVICE);
6947
6948         kfree(*data_buff);
6949         *data_buff = NULL;
6950         rtl8169_make_unusable_by_asic(desc);
6951 }
6952
6953 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
6954 {
6955         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
6956
6957         /* Force memory writes to complete before releasing descriptor */
6958         dma_wmb();
6959
6960         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
6961 }
6962
6963 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
6964                                        u32 rx_buf_sz)
6965 {
6966         desc->addr = cpu_to_le64(mapping);
6967         rtl8169_mark_to_asic(desc, rx_buf_sz);
6968 }
6969
6970 static inline void *rtl8169_align(void *data)
6971 {
6972         return (void *)ALIGN((long)data, 16);
6973 }
6974
6975 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
6976                                              struct RxDesc *desc)
6977 {
6978         void *data;
6979         dma_addr_t mapping;
6980         struct device *d = &tp->pci_dev->dev;
6981         struct net_device *dev = tp->dev;
6982         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
6983
6984         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
6985         if (!data)
6986                 return NULL;
6987
6988         if (rtl8169_align(data) != data) {
6989                 kfree(data);
6990                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
6991                 if (!data)
6992                         return NULL;
6993         }
6994
6995         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
6996                                  DMA_FROM_DEVICE);
6997         if (unlikely(dma_mapping_error(d, mapping))) {
6998                 if (net_ratelimit())
6999                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
7000                 goto err_out;
7001         }
7002
7003         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
7004         return data;
7005
7006 err_out:
7007         kfree(data);
7008         return NULL;
7009 }
7010
7011 static void rtl8169_rx_clear(struct rtl8169_private *tp)
7012 {
7013         unsigned int i;
7014
7015         for (i = 0; i < NUM_RX_DESC; i++) {
7016                 if (tp->Rx_databuff[i]) {
7017                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
7018                                             tp->RxDescArray + i);
7019                 }
7020         }
7021 }
7022
7023 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
7024 {
7025         desc->opts1 |= cpu_to_le32(RingEnd);
7026 }
7027
7028 static int rtl8169_rx_fill(struct rtl8169_private *tp)
7029 {
7030         unsigned int i;
7031
7032         for (i = 0; i < NUM_RX_DESC; i++) {
7033                 void *data;
7034
7035                 if (tp->Rx_databuff[i])
7036                         continue;
7037
7038                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
7039                 if (!data) {
7040                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
7041                         goto err_out;
7042                 }
7043                 tp->Rx_databuff[i] = data;
7044         }
7045
7046         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
7047         return 0;
7048
7049 err_out:
7050         rtl8169_rx_clear(tp);
7051         return -ENOMEM;
7052 }
7053
7054 static int rtl8169_init_ring(struct net_device *dev)
7055 {
7056         struct rtl8169_private *tp = netdev_priv(dev);
7057
7058         rtl8169_init_ring_indexes(tp);
7059
7060         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
7061         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
7062
7063         return rtl8169_rx_fill(tp);
7064 }
7065
7066 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
7067                                  struct TxDesc *desc)
7068 {
7069         unsigned int len = tx_skb->len;
7070
7071         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
7072
7073         desc->opts1 = 0x00;
7074         desc->opts2 = 0x00;
7075         desc->addr = 0x00;
7076         tx_skb->len = 0;
7077 }
7078
7079 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
7080                                    unsigned int n)
7081 {
7082         unsigned int i;
7083
7084         for (i = 0; i < n; i++) {
7085                 unsigned int entry = (start + i) % NUM_TX_DESC;
7086                 struct ring_info *tx_skb = tp->tx_skb + entry;
7087                 unsigned int len = tx_skb->len;
7088
7089                 if (len) {
7090                         struct sk_buff *skb = tx_skb->skb;
7091
7092                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
7093                                              tp->TxDescArray + entry);
7094                         if (skb) {
7095                                 dev_consume_skb_any(skb);
7096                                 tx_skb->skb = NULL;
7097                         }
7098                 }
7099         }
7100 }
7101
7102 static void rtl8169_tx_clear(struct rtl8169_private *tp)
7103 {
7104         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
7105         tp->cur_tx = tp->dirty_tx = 0;
7106 }
7107
7108 static void rtl_reset_work(struct rtl8169_private *tp)
7109 {
7110         struct net_device *dev = tp->dev;
7111         int i;
7112
7113         napi_disable(&tp->napi);
7114         netif_stop_queue(dev);
7115         synchronize_sched();
7116
7117         rtl8169_hw_reset(tp);
7118
7119         for (i = 0; i < NUM_RX_DESC; i++)
7120                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
7121
7122         rtl8169_tx_clear(tp);
7123         rtl8169_init_ring_indexes(tp);
7124
7125         napi_enable(&tp->napi);
7126         rtl_hw_start(dev);
7127         netif_wake_queue(dev);
7128         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
7129 }
7130
7131 static void rtl8169_tx_timeout(struct net_device *dev)
7132 {
7133         struct rtl8169_private *tp = netdev_priv(dev);
7134
7135         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7136 }
7137
7138 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
7139                               u32 *opts)
7140 {
7141         struct skb_shared_info *info = skb_shinfo(skb);
7142         unsigned int cur_frag, entry;
7143         struct TxDesc *uninitialized_var(txd);
7144         struct device *d = &tp->pci_dev->dev;
7145
7146         entry = tp->cur_tx;
7147         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
7148                 const skb_frag_t *frag = info->frags + cur_frag;
7149                 dma_addr_t mapping;
7150                 u32 status, len;
7151                 void *addr;
7152
7153                 entry = (entry + 1) % NUM_TX_DESC;
7154
7155                 txd = tp->TxDescArray + entry;
7156                 len = skb_frag_size(frag);
7157                 addr = skb_frag_address(frag);
7158                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
7159                 if (unlikely(dma_mapping_error(d, mapping))) {
7160                         if (net_ratelimit())
7161                                 netif_err(tp, drv, tp->dev,
7162                                           "Failed to map TX fragments DMA!\n");
7163                         goto err_out;
7164                 }
7165
7166                 /* Anti gcc 2.95.3 bugware (sic) */
7167                 status = opts[0] | len |
7168                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
7169
7170                 txd->opts1 = cpu_to_le32(status);
7171                 txd->opts2 = cpu_to_le32(opts[1]);
7172                 txd->addr = cpu_to_le64(mapping);
7173
7174                 tp->tx_skb[entry].len = len;
7175         }
7176
7177         if (cur_frag) {
7178                 tp->tx_skb[entry].skb = skb;
7179                 txd->opts1 |= cpu_to_le32(LastFrag);
7180         }
7181
7182         return cur_frag;
7183
7184 err_out:
7185         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
7186         return -EIO;
7187 }
7188
7189 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
7190 {
7191         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
7192 }
7193
7194 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
7195                                       struct net_device *dev);
7196 /* r8169_csum_workaround()
7197  * The hw limites the value the transport offset. When the offset is out of the
7198  * range, calculate the checksum by sw.
7199  */
7200 static void r8169_csum_workaround(struct rtl8169_private *tp,
7201                                   struct sk_buff *skb)
7202 {
7203         if (skb_shinfo(skb)->gso_size) {
7204                 netdev_features_t features = tp->dev->features;
7205                 struct sk_buff *segs, *nskb;
7206
7207                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
7208                 segs = skb_gso_segment(skb, features);
7209                 if (IS_ERR(segs) || !segs)
7210                         goto drop;
7211
7212                 do {
7213                         nskb = segs;
7214                         segs = segs->next;
7215                         nskb->next = NULL;
7216                         rtl8169_start_xmit(nskb, tp->dev);
7217                 } while (segs);
7218
7219                 dev_consume_skb_any(skb);
7220         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7221                 if (skb_checksum_help(skb) < 0)
7222                         goto drop;
7223
7224                 rtl8169_start_xmit(skb, tp->dev);
7225         } else {
7226                 struct net_device_stats *stats;
7227
7228 drop:
7229                 stats = &tp->dev->stats;
7230                 stats->tx_dropped++;
7231                 dev_kfree_skb_any(skb);
7232         }
7233 }
7234
7235 /* msdn_giant_send_check()
7236  * According to the document of microsoft, the TCP Pseudo Header excludes the
7237  * packet length for IPv6 TCP large packets.
7238  */
7239 static int msdn_giant_send_check(struct sk_buff *skb)
7240 {
7241         const struct ipv6hdr *ipv6h;
7242         struct tcphdr *th;
7243         int ret;
7244
7245         ret = skb_cow_head(skb, 0);
7246         if (ret)
7247                 return ret;
7248
7249         ipv6h = ipv6_hdr(skb);
7250         th = tcp_hdr(skb);
7251
7252         th->check = 0;
7253         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
7254
7255         return ret;
7256 }
7257
7258 static inline __be16 get_protocol(struct sk_buff *skb)
7259 {
7260         __be16 protocol;
7261
7262         if (skb->protocol == htons(ETH_P_8021Q))
7263                 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
7264         else
7265                 protocol = skb->protocol;
7266
7267         return protocol;
7268 }
7269
7270 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
7271                                 struct sk_buff *skb, u32 *opts)
7272 {
7273         u32 mss = skb_shinfo(skb)->gso_size;
7274
7275         if (mss) {
7276                 opts[0] |= TD_LSO;
7277                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
7278         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7279                 const struct iphdr *ip = ip_hdr(skb);
7280
7281                 if (ip->protocol == IPPROTO_TCP)
7282                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
7283                 else if (ip->protocol == IPPROTO_UDP)
7284                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
7285                 else
7286                         WARN_ON_ONCE(1);
7287         }
7288
7289         return true;
7290 }
7291
7292 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
7293                                 struct sk_buff *skb, u32 *opts)
7294 {
7295         u32 transport_offset = (u32)skb_transport_offset(skb);
7296         u32 mss = skb_shinfo(skb)->gso_size;
7297
7298         if (mss) {
7299                 if (transport_offset > GTTCPHO_MAX) {
7300                         netif_warn(tp, tx_err, tp->dev,
7301                                    "Invalid transport offset 0x%x for TSO\n",
7302                                    transport_offset);
7303                         return false;
7304                 }
7305
7306                 switch (get_protocol(skb)) {
7307                 case htons(ETH_P_IP):
7308                         opts[0] |= TD1_GTSENV4;
7309                         break;
7310
7311                 case htons(ETH_P_IPV6):
7312                         if (msdn_giant_send_check(skb))
7313                                 return false;
7314
7315                         opts[0] |= TD1_GTSENV6;
7316                         break;
7317
7318                 default:
7319                         WARN_ON_ONCE(1);
7320                         break;
7321                 }
7322
7323                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
7324                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
7325         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7326                 u8 ip_protocol;
7327
7328                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
7329                         return !(skb_checksum_help(skb) || eth_skb_pad(skb));
7330
7331                 if (transport_offset > TCPHO_MAX) {
7332                         netif_warn(tp, tx_err, tp->dev,
7333                                    "Invalid transport offset 0x%x\n",
7334                                    transport_offset);
7335                         return false;
7336                 }
7337
7338                 switch (get_protocol(skb)) {
7339                 case htons(ETH_P_IP):
7340                         opts[1] |= TD1_IPv4_CS;
7341                         ip_protocol = ip_hdr(skb)->protocol;
7342                         break;
7343
7344                 case htons(ETH_P_IPV6):
7345                         opts[1] |= TD1_IPv6_CS;
7346                         ip_protocol = ipv6_hdr(skb)->nexthdr;
7347                         break;
7348
7349                 default:
7350                         ip_protocol = IPPROTO_RAW;
7351                         break;
7352                 }
7353
7354                 if (ip_protocol == IPPROTO_TCP)
7355                         opts[1] |= TD1_TCP_CS;
7356                 else if (ip_protocol == IPPROTO_UDP)
7357                         opts[1] |= TD1_UDP_CS;
7358                 else
7359                         WARN_ON_ONCE(1);
7360
7361                 opts[1] |= transport_offset << TCPHO_SHIFT;
7362         } else {
7363                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
7364                         return !eth_skb_pad(skb);
7365         }
7366
7367         return true;
7368 }
7369
7370 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
7371                                       struct net_device *dev)
7372 {
7373         struct rtl8169_private *tp = netdev_priv(dev);
7374         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
7375         struct TxDesc *txd = tp->TxDescArray + entry;
7376         void __iomem *ioaddr = tp->mmio_addr;
7377         struct device *d = &tp->pci_dev->dev;
7378         dma_addr_t mapping;
7379         u32 status, len;
7380         u32 opts[2];
7381         int frags;
7382
7383         if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
7384                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
7385                 goto err_stop_0;
7386         }
7387
7388         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
7389                 goto err_stop_0;
7390
7391         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
7392         opts[0] = DescOwn;
7393
7394         if (!tp->tso_csum(tp, skb, opts)) {
7395                 r8169_csum_workaround(tp, skb);
7396                 return NETDEV_TX_OK;
7397         }
7398
7399         len = skb_headlen(skb);
7400         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
7401         if (unlikely(dma_mapping_error(d, mapping))) {
7402                 if (net_ratelimit())
7403                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
7404                 goto err_dma_0;
7405         }
7406
7407         tp->tx_skb[entry].len = len;
7408         txd->addr = cpu_to_le64(mapping);
7409
7410         frags = rtl8169_xmit_frags(tp, skb, opts);
7411         if (frags < 0)
7412                 goto err_dma_1;
7413         else if (frags)
7414                 opts[0] |= FirstFrag;
7415         else {
7416                 opts[0] |= FirstFrag | LastFrag;
7417                 tp->tx_skb[entry].skb = skb;
7418         }
7419
7420         txd->opts2 = cpu_to_le32(opts[1]);
7421
7422         skb_tx_timestamp(skb);
7423
7424         /* Force memory writes to complete before releasing descriptor */
7425         dma_wmb();
7426
7427         /* Anti gcc 2.95.3 bugware (sic) */
7428         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
7429         txd->opts1 = cpu_to_le32(status);
7430
7431         /* Force all memory writes to complete before notifying device */
7432         wmb();
7433
7434         tp->cur_tx += frags + 1;
7435
7436         RTL_W8(TxPoll, NPQ);
7437
7438         mmiowb();
7439
7440         if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7441                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
7442                  * not miss a ring update when it notices a stopped queue.
7443                  */
7444                 smp_wmb();
7445                 netif_stop_queue(dev);
7446                 /* Sync with rtl_tx:
7447                  * - publish queue status and cur_tx ring index (write barrier)
7448                  * - refresh dirty_tx ring index (read barrier).
7449                  * May the current thread have a pessimistic view of the ring
7450                  * status and forget to wake up queue, a racing rtl_tx thread
7451                  * can't.
7452                  */
7453                 smp_mb();
7454                 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
7455                         netif_wake_queue(dev);
7456         }
7457
7458         return NETDEV_TX_OK;
7459
7460 err_dma_1:
7461         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
7462 err_dma_0:
7463         dev_kfree_skb_any(skb);
7464         dev->stats.tx_dropped++;
7465         return NETDEV_TX_OK;
7466
7467 err_stop_0:
7468         netif_stop_queue(dev);
7469         dev->stats.tx_dropped++;
7470         return NETDEV_TX_BUSY;
7471 }
7472
7473 static void rtl8169_pcierr_interrupt(struct net_device *dev)
7474 {
7475         struct rtl8169_private *tp = netdev_priv(dev);
7476         struct pci_dev *pdev = tp->pci_dev;
7477         u16 pci_status, pci_cmd;
7478
7479         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
7480         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
7481
7482         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
7483                   pci_cmd, pci_status);
7484
7485         /*
7486          * The recovery sequence below admits a very elaborated explanation:
7487          * - it seems to work;
7488          * - I did not see what else could be done;
7489          * - it makes iop3xx happy.
7490          *
7491          * Feel free to adjust to your needs.
7492          */
7493         if (pdev->broken_parity_status)
7494                 pci_cmd &= ~PCI_COMMAND_PARITY;
7495         else
7496                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
7497
7498         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
7499
7500         pci_write_config_word(pdev, PCI_STATUS,
7501                 pci_status & (PCI_STATUS_DETECTED_PARITY |
7502                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
7503                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
7504
7505         /* The infamous DAC f*ckup only happens at boot time */
7506         if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
7507                 void __iomem *ioaddr = tp->mmio_addr;
7508
7509                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
7510                 tp->cp_cmd &= ~PCIDAC;
7511                 RTL_W16(CPlusCmd, tp->cp_cmd);
7512                 dev->features &= ~NETIF_F_HIGHDMA;
7513         }
7514
7515         rtl8169_hw_reset(tp);
7516
7517         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7518 }
7519
7520 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
7521 {
7522         unsigned int dirty_tx, tx_left;
7523
7524         dirty_tx = tp->dirty_tx;
7525         smp_rmb();
7526         tx_left = tp->cur_tx - dirty_tx;
7527
7528         while (tx_left > 0) {
7529                 unsigned int entry = dirty_tx % NUM_TX_DESC;
7530                 struct ring_info *tx_skb = tp->tx_skb + entry;
7531                 u32 status;
7532
7533                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
7534                 if (status & DescOwn)
7535                         break;
7536
7537                 /* This barrier is needed to keep us from reading
7538                  * any other fields out of the Tx descriptor until
7539                  * we know the status of DescOwn
7540                  */
7541                 dma_rmb();
7542
7543                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
7544                                      tp->TxDescArray + entry);
7545                 if (status & LastFrag) {
7546                         u64_stats_update_begin(&tp->tx_stats.syncp);
7547                         tp->tx_stats.packets++;
7548                         tp->tx_stats.bytes += tx_skb->skb->len;
7549                         u64_stats_update_end(&tp->tx_stats.syncp);
7550                         dev_consume_skb_any(tx_skb->skb);
7551                         tx_skb->skb = NULL;
7552                 }
7553                 dirty_tx++;
7554                 tx_left--;
7555         }
7556
7557         if (tp->dirty_tx != dirty_tx) {
7558                 tp->dirty_tx = dirty_tx;
7559                 /* Sync with rtl8169_start_xmit:
7560                  * - publish dirty_tx ring index (write barrier)
7561                  * - refresh cur_tx ring index and queue status (read barrier)
7562                  * May the current thread miss the stopped queue condition,
7563                  * a racing xmit thread can only have a right view of the
7564                  * ring status.
7565                  */
7566                 smp_mb();
7567                 if (netif_queue_stopped(dev) &&
7568                     TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7569                         netif_wake_queue(dev);
7570                 }
7571                 /*
7572                  * 8168 hack: TxPoll requests are lost when the Tx packets are
7573                  * too close. Let's kick an extra TxPoll request when a burst
7574                  * of start_xmit activity is detected (if it is not detected,
7575                  * it is slow enough). -- FR
7576                  */
7577                 if (tp->cur_tx != dirty_tx) {
7578                         void __iomem *ioaddr = tp->mmio_addr;
7579
7580                         RTL_W8(TxPoll, NPQ);
7581                 }
7582         }
7583 }
7584
7585 static inline int rtl8169_fragmented_frame(u32 status)
7586 {
7587         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
7588 }
7589
7590 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
7591 {
7592         u32 status = opts1 & RxProtoMask;
7593
7594         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
7595             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
7596                 skb->ip_summed = CHECKSUM_UNNECESSARY;
7597         else
7598                 skb_checksum_none_assert(skb);
7599 }
7600
7601 static struct sk_buff *rtl8169_try_rx_copy(void *data,
7602                                            struct rtl8169_private *tp,
7603                                            int pkt_size,
7604                                            dma_addr_t addr)
7605 {
7606         struct sk_buff *skb;
7607         struct device *d = &tp->pci_dev->dev;
7608
7609         data = rtl8169_align(data);
7610         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
7611         prefetch(data);
7612         skb = napi_alloc_skb(&tp->napi, pkt_size);
7613         if (skb)
7614                 memcpy(skb->data, data, pkt_size);
7615         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
7616
7617         return skb;
7618 }
7619
7620 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
7621 {
7622         unsigned int cur_rx, rx_left;
7623         unsigned int count;
7624
7625         cur_rx = tp->cur_rx;
7626
7627         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
7628                 unsigned int entry = cur_rx % NUM_RX_DESC;
7629                 struct RxDesc *desc = tp->RxDescArray + entry;
7630                 u32 status;
7631
7632                 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
7633                 if (status & DescOwn)
7634                         break;
7635
7636                 /* This barrier is needed to keep us from reading
7637                  * any other fields out of the Rx descriptor until
7638                  * we know the status of DescOwn
7639                  */
7640                 dma_rmb();
7641
7642                 if (unlikely(status & RxRES)) {
7643                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
7644                                    status);
7645                         dev->stats.rx_errors++;
7646                         if (status & (RxRWT | RxRUNT))
7647                                 dev->stats.rx_length_errors++;
7648                         if (status & RxCRC)
7649                                 dev->stats.rx_crc_errors++;
7650                         if (status & RxFOVF) {
7651                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7652                                 dev->stats.rx_fifo_errors++;
7653                         }
7654                         if ((status & (RxRUNT | RxCRC)) &&
7655                             !(status & (RxRWT | RxFOVF)) &&
7656                             (dev->features & NETIF_F_RXALL))
7657                                 goto process_pkt;
7658                 } else {
7659                         struct sk_buff *skb;
7660                         dma_addr_t addr;
7661                         int pkt_size;
7662
7663 process_pkt:
7664                         addr = le64_to_cpu(desc->addr);
7665                         if (likely(!(dev->features & NETIF_F_RXFCS)))
7666                                 pkt_size = (status & 0x00003fff) - 4;
7667                         else
7668                                 pkt_size = status & 0x00003fff;
7669
7670                         /*
7671                          * The driver does not support incoming fragmented
7672                          * frames. They are seen as a symptom of over-mtu
7673                          * sized frames.
7674                          */
7675                         if (unlikely(rtl8169_fragmented_frame(status))) {
7676                                 dev->stats.rx_dropped++;
7677                                 dev->stats.rx_length_errors++;
7678                                 goto release_descriptor;
7679                         }
7680
7681                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
7682                                                   tp, pkt_size, addr);
7683                         if (!skb) {
7684                                 dev->stats.rx_dropped++;
7685                                 goto release_descriptor;
7686                         }
7687
7688                         rtl8169_rx_csum(skb, status);
7689                         skb_put(skb, pkt_size);
7690                         skb->protocol = eth_type_trans(skb, dev);
7691
7692                         rtl8169_rx_vlan_tag(desc, skb);
7693
7694                         if (skb->pkt_type == PACKET_MULTICAST)
7695                                 dev->stats.multicast++;
7696
7697                         napi_gro_receive(&tp->napi, skb);
7698
7699                         u64_stats_update_begin(&tp->rx_stats.syncp);
7700                         tp->rx_stats.packets++;
7701                         tp->rx_stats.bytes += pkt_size;
7702                         u64_stats_update_end(&tp->rx_stats.syncp);
7703                 }
7704 release_descriptor:
7705                 desc->opts2 = 0;
7706                 rtl8169_mark_to_asic(desc, rx_buf_sz);
7707         }
7708
7709         count = cur_rx - tp->cur_rx;
7710         tp->cur_rx = cur_rx;
7711
7712         return count;
7713 }
7714
7715 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
7716 {
7717         struct net_device *dev = dev_instance;
7718         struct rtl8169_private *tp = netdev_priv(dev);
7719         int handled = 0;
7720         u16 status;
7721
7722         status = rtl_get_events(tp);
7723         if (status && status != 0xffff) {
7724                 status &= RTL_EVENT_NAPI | tp->event_slow;
7725                 if (status) {
7726                         handled = 1;
7727
7728                         rtl_irq_disable(tp);
7729                         napi_schedule(&tp->napi);
7730                 }
7731         }
7732         return IRQ_RETVAL(handled);
7733 }
7734
7735 /*
7736  * Workqueue context.
7737  */
7738 static void rtl_slow_event_work(struct rtl8169_private *tp)
7739 {
7740         struct net_device *dev = tp->dev;
7741         u16 status;
7742
7743         status = rtl_get_events(tp) & tp->event_slow;
7744         rtl_ack_events(tp, status);
7745
7746         if (unlikely(status & RxFIFOOver)) {
7747                 switch (tp->mac_version) {
7748                 /* Work around for rx fifo overflow */
7749                 case RTL_GIGA_MAC_VER_11:
7750                         netif_stop_queue(dev);
7751                         /* XXX - Hack alert. See rtl_task(). */
7752                         set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
7753                 default:
7754                         break;
7755                 }
7756         }
7757
7758         if (unlikely(status & SYSErr))
7759                 rtl8169_pcierr_interrupt(dev);
7760
7761         if (status & LinkChg)
7762                 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
7763
7764         rtl_irq_enable_all(tp);
7765 }
7766
7767 static void rtl_task(struct work_struct *work)
7768 {
7769         static const struct {
7770                 int bitnr;
7771                 void (*action)(struct rtl8169_private *);
7772         } rtl_work[] = {
7773                 /* XXX - keep rtl_slow_event_work() as first element. */
7774                 { RTL_FLAG_TASK_SLOW_PENDING,   rtl_slow_event_work },
7775                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
7776                 { RTL_FLAG_TASK_PHY_PENDING,    rtl_phy_work }
7777         };
7778         struct rtl8169_private *tp =
7779                 container_of(work, struct rtl8169_private, wk.work);
7780         struct net_device *dev = tp->dev;
7781         int i;
7782
7783         rtl_lock_work(tp);
7784
7785         if (!netif_running(dev) ||
7786             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
7787                 goto out_unlock;
7788
7789         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
7790                 bool pending;
7791
7792                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
7793                 if (pending)
7794                         rtl_work[i].action(tp);
7795         }
7796
7797 out_unlock:
7798         rtl_unlock_work(tp);
7799 }
7800
7801 static int rtl8169_poll(struct napi_struct *napi, int budget)
7802 {
7803         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
7804         struct net_device *dev = tp->dev;
7805         u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
7806         int work_done= 0;
7807         u16 status;
7808
7809         status = rtl_get_events(tp);
7810         rtl_ack_events(tp, status & ~tp->event_slow);
7811
7812         if (status & RTL_EVENT_NAPI_RX)
7813                 work_done = rtl_rx(dev, tp, (u32) budget);
7814
7815         if (status & RTL_EVENT_NAPI_TX)
7816                 rtl_tx(dev, tp);
7817
7818         if (status & tp->event_slow) {
7819                 enable_mask &= ~tp->event_slow;
7820
7821                 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
7822         }
7823
7824         if (work_done < budget) {
7825                 napi_complete_done(napi, work_done);
7826
7827                 rtl_irq_enable(tp, enable_mask);
7828                 mmiowb();
7829         }
7830
7831         return work_done;
7832 }
7833
7834 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
7835 {
7836         struct rtl8169_private *tp = netdev_priv(dev);
7837
7838         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
7839                 return;
7840
7841         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
7842         RTL_W32(RxMissed, 0);
7843 }
7844
7845 static void rtl8169_down(struct net_device *dev)
7846 {
7847         struct rtl8169_private *tp = netdev_priv(dev);
7848         void __iomem *ioaddr = tp->mmio_addr;
7849
7850         del_timer_sync(&tp->timer);
7851
7852         napi_disable(&tp->napi);
7853         netif_stop_queue(dev);
7854
7855         rtl8169_hw_reset(tp);
7856         /*
7857          * At this point device interrupts can not be enabled in any function,
7858          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
7859          * and napi is disabled (rtl8169_poll).
7860          */
7861         rtl8169_rx_missed(dev, ioaddr);
7862
7863         /* Give a racing hard_start_xmit a few cycles to complete. */
7864         synchronize_sched();
7865
7866         rtl8169_tx_clear(tp);
7867
7868         rtl8169_rx_clear(tp);
7869
7870         rtl_pll_power_down(tp);
7871 }
7872
7873 static int rtl8169_close(struct net_device *dev)
7874 {
7875         struct rtl8169_private *tp = netdev_priv(dev);
7876         struct pci_dev *pdev = tp->pci_dev;
7877
7878         pm_runtime_get_sync(&pdev->dev);
7879
7880         /* Update counters before going down */
7881         rtl8169_update_counters(dev);
7882
7883         rtl_lock_work(tp);
7884         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7885
7886         rtl8169_down(dev);
7887         rtl_unlock_work(tp);
7888
7889         cancel_work_sync(&tp->wk.work);
7890
7891         free_irq(pdev->irq, dev);
7892
7893         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7894                           tp->RxPhyAddr);
7895         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7896                           tp->TxPhyAddr);
7897         tp->TxDescArray = NULL;
7898         tp->RxDescArray = NULL;
7899
7900         pm_runtime_put_sync(&pdev->dev);
7901
7902         return 0;
7903 }
7904
7905 #ifdef CONFIG_NET_POLL_CONTROLLER
7906 static void rtl8169_netpoll(struct net_device *dev)
7907 {
7908         struct rtl8169_private *tp = netdev_priv(dev);
7909
7910         rtl8169_interrupt(tp->pci_dev->irq, dev);
7911 }
7912 #endif
7913
7914 static int rtl_open(struct net_device *dev)
7915 {
7916         struct rtl8169_private *tp = netdev_priv(dev);
7917         void __iomem *ioaddr = tp->mmio_addr;
7918         struct pci_dev *pdev = tp->pci_dev;
7919         int retval = -ENOMEM;
7920
7921         pm_runtime_get_sync(&pdev->dev);
7922
7923         /*
7924          * Rx and Tx descriptors needs 256 bytes alignment.
7925          * dma_alloc_coherent provides more.
7926          */
7927         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
7928                                              &tp->TxPhyAddr, GFP_KERNEL);
7929         if (!tp->TxDescArray)
7930                 goto err_pm_runtime_put;
7931
7932         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
7933                                              &tp->RxPhyAddr, GFP_KERNEL);
7934         if (!tp->RxDescArray)
7935                 goto err_free_tx_0;
7936
7937         retval = rtl8169_init_ring(dev);
7938         if (retval < 0)
7939                 goto err_free_rx_1;
7940
7941         INIT_WORK(&tp->wk.work, rtl_task);
7942
7943         smp_mb();
7944
7945         rtl_request_firmware(tp);
7946
7947         retval = request_irq(pdev->irq, rtl8169_interrupt,
7948                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
7949                              dev->name, dev);
7950         if (retval < 0)
7951                 goto err_release_fw_2;
7952
7953         rtl_lock_work(tp);
7954
7955         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7956
7957         napi_enable(&tp->napi);
7958
7959         rtl8169_init_phy(dev, tp);
7960
7961         __rtl8169_set_features(dev, dev->features);
7962
7963         rtl_pll_power_up(tp);
7964
7965         rtl_hw_start(dev);
7966
7967         if (!rtl8169_init_counter_offsets(dev))
7968                 netif_warn(tp, hw, dev, "counter reset/update failed\n");
7969
7970         netif_start_queue(dev);
7971
7972         rtl_unlock_work(tp);
7973
7974         tp->saved_wolopts = 0;
7975         pm_runtime_put_noidle(&pdev->dev);
7976
7977         rtl8169_check_link_status(dev, tp, ioaddr);
7978 out:
7979         return retval;
7980
7981 err_release_fw_2:
7982         rtl_release_firmware(tp);
7983         rtl8169_rx_clear(tp);
7984 err_free_rx_1:
7985         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7986                           tp->RxPhyAddr);
7987         tp->RxDescArray = NULL;
7988 err_free_tx_0:
7989         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7990                           tp->TxPhyAddr);
7991         tp->TxDescArray = NULL;
7992 err_pm_runtime_put:
7993         pm_runtime_put_noidle(&pdev->dev);
7994         goto out;
7995 }
7996
7997 static void
7998 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
7999 {
8000         struct rtl8169_private *tp = netdev_priv(dev);
8001         void __iomem *ioaddr = tp->mmio_addr;
8002         struct pci_dev *pdev = tp->pci_dev;
8003         struct rtl8169_counters *counters = tp->counters;
8004         unsigned int start;
8005
8006         pm_runtime_get_noresume(&pdev->dev);
8007
8008         if (netif_running(dev) && pm_runtime_active(&pdev->dev))
8009                 rtl8169_rx_missed(dev, ioaddr);
8010
8011         do {
8012                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
8013                 stats->rx_packets = tp->rx_stats.packets;
8014                 stats->rx_bytes = tp->rx_stats.bytes;
8015         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
8016
8017         do {
8018                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
8019                 stats->tx_packets = tp->tx_stats.packets;
8020                 stats->tx_bytes = tp->tx_stats.bytes;
8021         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
8022
8023         stats->rx_dropped       = dev->stats.rx_dropped;
8024         stats->tx_dropped       = dev->stats.tx_dropped;
8025         stats->rx_length_errors = dev->stats.rx_length_errors;
8026         stats->rx_errors        = dev->stats.rx_errors;
8027         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
8028         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
8029         stats->rx_missed_errors = dev->stats.rx_missed_errors;
8030         stats->multicast        = dev->stats.multicast;
8031
8032         /*
8033          * Fetch additonal counter values missing in stats collected by driver
8034          * from tally counters.
8035          */
8036         if (pm_runtime_active(&pdev->dev))
8037                 rtl8169_update_counters(dev);
8038
8039         /*
8040          * Subtract values fetched during initalization.
8041          * See rtl8169_init_counter_offsets for a description why we do that.
8042          */
8043         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
8044                 le64_to_cpu(tp->tc_offset.tx_errors);
8045         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
8046                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
8047         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
8048                 le16_to_cpu(tp->tc_offset.tx_aborted);
8049
8050         pm_runtime_put_noidle(&pdev->dev);
8051 }
8052
8053 static void rtl8169_net_suspend(struct net_device *dev)
8054 {
8055         struct rtl8169_private *tp = netdev_priv(dev);
8056
8057         if (!netif_running(dev))
8058                 return;
8059
8060         netif_device_detach(dev);
8061         netif_stop_queue(dev);
8062
8063         rtl_lock_work(tp);
8064         napi_disable(&tp->napi);
8065         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
8066         rtl_unlock_work(tp);
8067
8068         rtl_pll_power_down(tp);
8069 }
8070
8071 #ifdef CONFIG_PM
8072
8073 static int rtl8169_suspend(struct device *device)
8074 {
8075         struct pci_dev *pdev = to_pci_dev(device);
8076         struct net_device *dev = pci_get_drvdata(pdev);
8077
8078         rtl8169_net_suspend(dev);
8079
8080         return 0;
8081 }
8082
8083 static void __rtl8169_resume(struct net_device *dev)
8084 {
8085         struct rtl8169_private *tp = netdev_priv(dev);
8086
8087         netif_device_attach(dev);
8088
8089         rtl_pll_power_up(tp);
8090
8091         rtl_lock_work(tp);
8092         napi_enable(&tp->napi);
8093         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
8094         rtl_unlock_work(tp);
8095
8096         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
8097 }
8098
8099 static int rtl8169_resume(struct device *device)
8100 {
8101         struct pci_dev *pdev = to_pci_dev(device);
8102         struct net_device *dev = pci_get_drvdata(pdev);
8103         struct rtl8169_private *tp = netdev_priv(dev);
8104
8105         rtl8169_init_phy(dev, tp);
8106
8107         if (netif_running(dev))
8108                 __rtl8169_resume(dev);
8109
8110         return 0;
8111 }
8112
8113 static int rtl8169_runtime_suspend(struct device *device)
8114 {
8115         struct pci_dev *pdev = to_pci_dev(device);
8116         struct net_device *dev = pci_get_drvdata(pdev);
8117         struct rtl8169_private *tp = netdev_priv(dev);
8118
8119         if (!tp->TxDescArray)
8120                 return 0;
8121
8122         rtl_lock_work(tp);
8123         tp->saved_wolopts = __rtl8169_get_wol(tp);
8124         __rtl8169_set_wol(tp, WAKE_ANY);
8125         rtl_unlock_work(tp);
8126
8127         rtl8169_net_suspend(dev);
8128
8129         /* Update counters before going runtime suspend */
8130         rtl8169_rx_missed(dev, tp->mmio_addr);
8131         rtl8169_update_counters(dev);
8132
8133         return 0;
8134 }
8135
8136 static int rtl8169_runtime_resume(struct device *device)
8137 {
8138         struct pci_dev *pdev = to_pci_dev(device);
8139         struct net_device *dev = pci_get_drvdata(pdev);
8140         struct rtl8169_private *tp = netdev_priv(dev);
8141         rtl_rar_set(tp, dev->dev_addr);
8142
8143         if (!tp->TxDescArray)
8144                 return 0;
8145
8146         rtl_lock_work(tp);
8147         __rtl8169_set_wol(tp, tp->saved_wolopts);
8148         tp->saved_wolopts = 0;
8149         rtl_unlock_work(tp);
8150
8151         rtl8169_init_phy(dev, tp);
8152
8153         __rtl8169_resume(dev);
8154
8155         return 0;
8156 }
8157
8158 static int rtl8169_runtime_idle(struct device *device)
8159 {
8160         struct pci_dev *pdev = to_pci_dev(device);
8161         struct net_device *dev = pci_get_drvdata(pdev);
8162         struct rtl8169_private *tp = netdev_priv(dev);
8163
8164         return tp->TxDescArray ? -EBUSY : 0;
8165 }
8166
8167 static const struct dev_pm_ops rtl8169_pm_ops = {
8168         .suspend                = rtl8169_suspend,
8169         .resume                 = rtl8169_resume,
8170         .freeze                 = rtl8169_suspend,
8171         .thaw                   = rtl8169_resume,
8172         .poweroff               = rtl8169_suspend,
8173         .restore                = rtl8169_resume,
8174         .runtime_suspend        = rtl8169_runtime_suspend,
8175         .runtime_resume         = rtl8169_runtime_resume,
8176         .runtime_idle           = rtl8169_runtime_idle,
8177 };
8178
8179 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
8180
8181 #else /* !CONFIG_PM */
8182
8183 #define RTL8169_PM_OPS  NULL
8184
8185 #endif /* !CONFIG_PM */
8186
8187 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
8188 {
8189         void __iomem *ioaddr = tp->mmio_addr;
8190
8191         /* WoL fails with 8168b when the receiver is disabled. */
8192         switch (tp->mac_version) {
8193         case RTL_GIGA_MAC_VER_11:
8194         case RTL_GIGA_MAC_VER_12:
8195         case RTL_GIGA_MAC_VER_17:
8196                 pci_clear_master(tp->pci_dev);
8197
8198                 RTL_W8(ChipCmd, CmdRxEnb);
8199                 /* PCI commit */
8200                 RTL_R8(ChipCmd);
8201                 break;
8202         default:
8203                 break;
8204         }
8205 }
8206
8207 static void rtl_shutdown(struct pci_dev *pdev)
8208 {
8209         struct net_device *dev = pci_get_drvdata(pdev);
8210         struct rtl8169_private *tp = netdev_priv(dev);
8211         struct device *d = &pdev->dev;
8212
8213         pm_runtime_get_sync(d);
8214
8215         rtl8169_net_suspend(dev);
8216
8217         /* Restore original MAC address */
8218         rtl_rar_set(tp, dev->perm_addr);
8219
8220         rtl8169_hw_reset(tp);
8221
8222         if (system_state == SYSTEM_POWER_OFF) {
8223                 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
8224                         rtl_wol_suspend_quirk(tp);
8225                         rtl_wol_shutdown_quirk(tp);
8226                 }
8227
8228                 pci_wake_from_d3(pdev, true);
8229                 pci_set_power_state(pdev, PCI_D3hot);
8230         }
8231
8232         pm_runtime_put_noidle(d);
8233 }
8234
8235 static void rtl_remove_one(struct pci_dev *pdev)
8236 {
8237         struct net_device *dev = pci_get_drvdata(pdev);
8238         struct rtl8169_private *tp = netdev_priv(dev);
8239
8240         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
8241              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
8242              tp->mac_version == RTL_GIGA_MAC_VER_31 ||
8243              tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8244              tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8245              tp->mac_version == RTL_GIGA_MAC_VER_51) &&
8246             r8168_check_dash(tp)) {
8247                 rtl8168_driver_stop(tp);
8248         }
8249
8250         netif_napi_del(&tp->napi);
8251
8252         unregister_netdev(dev);
8253
8254         dma_free_coherent(&tp->pci_dev->dev, sizeof(*tp->counters),
8255                           tp->counters, tp->counters_phys_addr);
8256
8257         rtl_release_firmware(tp);
8258
8259         if (pci_dev_run_wake(pdev))
8260                 pm_runtime_get_noresume(&pdev->dev);
8261
8262         /* restore original MAC address */
8263         rtl_rar_set(tp, dev->perm_addr);
8264
8265         rtl_disable_msi(pdev, tp);
8266         rtl8169_release_board(pdev, dev, tp->mmio_addr);
8267 }
8268
8269 static const struct net_device_ops rtl_netdev_ops = {
8270         .ndo_open               = rtl_open,
8271         .ndo_stop               = rtl8169_close,
8272         .ndo_get_stats64        = rtl8169_get_stats64,
8273         .ndo_start_xmit         = rtl8169_start_xmit,
8274         .ndo_tx_timeout         = rtl8169_tx_timeout,
8275         .ndo_validate_addr      = eth_validate_addr,
8276         .ndo_change_mtu         = rtl8169_change_mtu,
8277         .ndo_fix_features       = rtl8169_fix_features,
8278         .ndo_set_features       = rtl8169_set_features,
8279         .ndo_set_mac_address    = rtl_set_mac_address,
8280         .ndo_do_ioctl           = rtl8169_ioctl,
8281         .ndo_set_rx_mode        = rtl_set_rx_mode,
8282 #ifdef CONFIG_NET_POLL_CONTROLLER
8283         .ndo_poll_controller    = rtl8169_netpoll,
8284 #endif
8285
8286 };
8287
8288 static const struct rtl_cfg_info {
8289         void (*hw_start)(struct net_device *);
8290         unsigned int region;
8291         unsigned int align;
8292         u16 event_slow;
8293         unsigned features;
8294         const struct rtl_coalesce_info *coalesce_info;
8295         u8 default_ver;
8296 } rtl_cfg_infos [] = {
8297         [RTL_CFG_0] = {
8298                 .hw_start       = rtl_hw_start_8169,
8299                 .region         = 1,
8300                 .align          = 0,
8301                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
8302                 .features       = RTL_FEATURE_GMII,
8303                 .coalesce_info  = rtl_coalesce_info_8169,
8304                 .default_ver    = RTL_GIGA_MAC_VER_01,
8305         },
8306         [RTL_CFG_1] = {
8307                 .hw_start       = rtl_hw_start_8168,
8308                 .region         = 2,
8309                 .align          = 8,
8310                 .event_slow     = SYSErr | LinkChg | RxOverflow,
8311                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
8312                 .coalesce_info  = rtl_coalesce_info_8168_8136,
8313                 .default_ver    = RTL_GIGA_MAC_VER_11,
8314         },
8315         [RTL_CFG_2] = {
8316                 .hw_start       = rtl_hw_start_8101,
8317                 .region         = 2,
8318                 .align          = 8,
8319                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
8320                                   PCSTimeout,
8321                 .features       = RTL_FEATURE_MSI,
8322                 .coalesce_info  = rtl_coalesce_info_8168_8136,
8323                 .default_ver    = RTL_GIGA_MAC_VER_13,
8324         }
8325 };
8326
8327 /* Cfg9346_Unlock assumed. */
8328 static unsigned rtl_try_msi(struct rtl8169_private *tp,
8329                             const struct rtl_cfg_info *cfg)
8330 {
8331         void __iomem *ioaddr = tp->mmio_addr;
8332         unsigned msi = 0;
8333         u8 cfg2;
8334
8335         cfg2 = RTL_R8(Config2) & ~MSIEnable;
8336         if (cfg->features & RTL_FEATURE_MSI) {
8337                 if (pci_enable_msi(tp->pci_dev)) {
8338                         netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
8339                 } else {
8340                         cfg2 |= MSIEnable;
8341                         msi = RTL_FEATURE_MSI;
8342                 }
8343         }
8344         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
8345                 RTL_W8(Config2, cfg2);
8346         return msi;
8347 }
8348
8349 DECLARE_RTL_COND(rtl_link_list_ready_cond)
8350 {
8351         void __iomem *ioaddr = tp->mmio_addr;
8352
8353         return RTL_R8(MCU) & LINK_LIST_RDY;
8354 }
8355
8356 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
8357 {
8358         void __iomem *ioaddr = tp->mmio_addr;
8359
8360         return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
8361 }
8362
8363 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
8364 {
8365         void __iomem *ioaddr = tp->mmio_addr;
8366         u32 data;
8367
8368         tp->ocp_base = OCP_STD_PHY_BASE;
8369
8370         RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
8371
8372         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
8373                 return;
8374
8375         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
8376                 return;
8377
8378         RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
8379         msleep(1);
8380         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
8381
8382         data = r8168_mac_ocp_read(tp, 0xe8de);
8383         data &= ~(1 << 14);
8384         r8168_mac_ocp_write(tp, 0xe8de, data);
8385
8386         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8387                 return;
8388
8389         data = r8168_mac_ocp_read(tp, 0xe8de);
8390         data |= (1 << 15);
8391         r8168_mac_ocp_write(tp, 0xe8de, data);
8392
8393         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8394                 return;
8395 }
8396
8397 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
8398 {
8399         rtl8168ep_stop_cmac(tp);
8400         rtl_hw_init_8168g(tp);
8401 }
8402
8403 static void rtl_hw_initialize(struct rtl8169_private *tp)
8404 {
8405         switch (tp->mac_version) {
8406         case RTL_GIGA_MAC_VER_40:
8407         case RTL_GIGA_MAC_VER_41:
8408         case RTL_GIGA_MAC_VER_42:
8409         case RTL_GIGA_MAC_VER_43:
8410         case RTL_GIGA_MAC_VER_44:
8411         case RTL_GIGA_MAC_VER_45:
8412         case RTL_GIGA_MAC_VER_46:
8413         case RTL_GIGA_MAC_VER_47:
8414         case RTL_GIGA_MAC_VER_48:
8415                 rtl_hw_init_8168g(tp);
8416                 break;
8417         case RTL_GIGA_MAC_VER_49:
8418         case RTL_GIGA_MAC_VER_50:
8419         case RTL_GIGA_MAC_VER_51:
8420                 rtl_hw_init_8168ep(tp);
8421                 break;
8422         default:
8423                 break;
8424         }
8425 }
8426
8427 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8428 {
8429         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
8430         const unsigned int region = cfg->region;
8431         struct rtl8169_private *tp;
8432         struct mii_if_info *mii;
8433         struct net_device *dev;
8434         void __iomem *ioaddr;
8435         int chipset, i;
8436         int rc;
8437
8438         if (netif_msg_drv(&debug)) {
8439                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
8440                        MODULENAME, RTL8169_VERSION);
8441         }
8442
8443         dev = alloc_etherdev(sizeof (*tp));
8444         if (!dev) {
8445                 rc = -ENOMEM;
8446                 goto out;
8447         }
8448
8449         SET_NETDEV_DEV(dev, &pdev->dev);
8450         dev->netdev_ops = &rtl_netdev_ops;
8451         tp = netdev_priv(dev);
8452         tp->dev = dev;
8453         tp->pci_dev = pdev;
8454         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
8455
8456         mii = &tp->mii;
8457         mii->dev = dev;
8458         mii->mdio_read = rtl_mdio_read;
8459         mii->mdio_write = rtl_mdio_write;
8460         mii->phy_id_mask = 0x1f;
8461         mii->reg_num_mask = 0x1f;
8462         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
8463
8464         /* disable ASPM completely as that cause random device stop working
8465          * problems as well as full system hangs for some PCIe devices users */
8466         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
8467                                      PCIE_LINK_STATE_CLKPM);
8468
8469         /* enable device (incl. PCI PM wakeup and hotplug setup) */
8470         rc = pci_enable_device(pdev);
8471         if (rc < 0) {
8472                 netif_err(tp, probe, dev, "enable failure\n");
8473                 goto err_out_free_dev_1;
8474         }
8475
8476         if (pci_set_mwi(pdev) < 0)
8477                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
8478
8479         /* make sure PCI base addr 1 is MMIO */
8480         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
8481                 netif_err(tp, probe, dev,
8482                           "region #%d not an MMIO resource, aborting\n",
8483                           region);
8484                 rc = -ENODEV;
8485                 goto err_out_mwi_2;
8486         }
8487
8488         /* check for weird/broken PCI region reporting */
8489         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
8490                 netif_err(tp, probe, dev,
8491                           "Invalid PCI region size(s), aborting\n");
8492                 rc = -ENODEV;
8493                 goto err_out_mwi_2;
8494         }
8495
8496         rc = pci_request_regions(pdev, MODULENAME);
8497         if (rc < 0) {
8498                 netif_err(tp, probe, dev, "could not request regions\n");
8499                 goto err_out_mwi_2;
8500         }
8501
8502         /* ioremap MMIO region */
8503         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
8504         if (!ioaddr) {
8505                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
8506                 rc = -EIO;
8507                 goto err_out_free_res_3;
8508         }
8509         tp->mmio_addr = ioaddr;
8510
8511         if (!pci_is_pcie(pdev))
8512                 netif_info(tp, probe, dev, "not PCI Express\n");
8513
8514         /* Identify chip attached to board */
8515         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
8516
8517         tp->cp_cmd = 0;
8518
8519         if ((sizeof(dma_addr_t) > 4) &&
8520             (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) &&
8521                               tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
8522             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
8523             !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
8524
8525                 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
8526                 if (!pci_is_pcie(pdev))
8527                         tp->cp_cmd |= PCIDAC;
8528                 dev->features |= NETIF_F_HIGHDMA;
8529         } else {
8530                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8531                 if (rc < 0) {
8532                         netif_err(tp, probe, dev, "DMA configuration failed\n");
8533                         goto err_out_unmap_4;
8534                 }
8535         }
8536
8537         rtl_init_rxcfg(tp);
8538
8539         rtl_irq_disable(tp);
8540
8541         rtl_hw_initialize(tp);
8542
8543         rtl_hw_reset(tp);
8544
8545         rtl_ack_events(tp, 0xffff);
8546
8547         pci_set_master(pdev);
8548
8549         rtl_init_mdio_ops(tp);
8550         rtl_init_pll_power_ops(tp);
8551         rtl_init_jumbo_ops(tp);
8552         rtl_init_csi_ops(tp);
8553
8554         rtl8169_print_mac_version(tp);
8555
8556         chipset = tp->mac_version;
8557         tp->txd_version = rtl_chip_infos[chipset].txd_version;
8558
8559         RTL_W8(Cfg9346, Cfg9346_Unlock);
8560         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
8561         RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus));
8562         switch (tp->mac_version) {
8563         case RTL_GIGA_MAC_VER_34:
8564         case RTL_GIGA_MAC_VER_35:
8565         case RTL_GIGA_MAC_VER_36:
8566         case RTL_GIGA_MAC_VER_37:
8567         case RTL_GIGA_MAC_VER_38:
8568         case RTL_GIGA_MAC_VER_40:
8569         case RTL_GIGA_MAC_VER_41:
8570         case RTL_GIGA_MAC_VER_42:
8571         case RTL_GIGA_MAC_VER_43:
8572         case RTL_GIGA_MAC_VER_44:
8573         case RTL_GIGA_MAC_VER_45:
8574         case RTL_GIGA_MAC_VER_46:
8575         case RTL_GIGA_MAC_VER_47:
8576         case RTL_GIGA_MAC_VER_48:
8577         case RTL_GIGA_MAC_VER_49:
8578         case RTL_GIGA_MAC_VER_50:
8579         case RTL_GIGA_MAC_VER_51:
8580                 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
8581                         tp->features |= RTL_FEATURE_WOL;
8582                 if ((RTL_R8(Config3) & LinkUp) != 0)
8583                         tp->features |= RTL_FEATURE_WOL;
8584                 break;
8585         default:
8586                 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
8587                         tp->features |= RTL_FEATURE_WOL;
8588                 break;
8589         }
8590         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
8591                 tp->features |= RTL_FEATURE_WOL;
8592         tp->features |= rtl_try_msi(tp, cfg);
8593         RTL_W8(Cfg9346, Cfg9346_Lock);
8594
8595         if (rtl_tbi_enabled(tp)) {
8596                 tp->set_speed = rtl8169_set_speed_tbi;
8597                 tp->get_link_ksettings = rtl8169_get_link_ksettings_tbi;
8598                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
8599                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
8600                 tp->link_ok = rtl8169_tbi_link_ok;
8601                 tp->do_ioctl = rtl_tbi_ioctl;
8602         } else {
8603                 tp->set_speed = rtl8169_set_speed_xmii;
8604                 tp->get_link_ksettings = rtl8169_get_link_ksettings_xmii;
8605                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
8606                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
8607                 tp->link_ok = rtl8169_xmii_link_ok;
8608                 tp->do_ioctl = rtl_xmii_ioctl;
8609         }
8610
8611         mutex_init(&tp->wk.mutex);
8612         u64_stats_init(&tp->rx_stats.syncp);
8613         u64_stats_init(&tp->tx_stats.syncp);
8614
8615         /* Get MAC address */
8616         if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
8617             tp->mac_version == RTL_GIGA_MAC_VER_36 ||
8618             tp->mac_version == RTL_GIGA_MAC_VER_37 ||
8619             tp->mac_version == RTL_GIGA_MAC_VER_38 ||
8620             tp->mac_version == RTL_GIGA_MAC_VER_40 ||
8621             tp->mac_version == RTL_GIGA_MAC_VER_41 ||
8622             tp->mac_version == RTL_GIGA_MAC_VER_42 ||
8623             tp->mac_version == RTL_GIGA_MAC_VER_43 ||
8624             tp->mac_version == RTL_GIGA_MAC_VER_44 ||
8625             tp->mac_version == RTL_GIGA_MAC_VER_45 ||
8626             tp->mac_version == RTL_GIGA_MAC_VER_46 ||
8627             tp->mac_version == RTL_GIGA_MAC_VER_47 ||
8628             tp->mac_version == RTL_GIGA_MAC_VER_48 ||
8629             tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8630             tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8631             tp->mac_version == RTL_GIGA_MAC_VER_51) {
8632                 u16 mac_addr[3];
8633
8634                 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
8635                 *(u16 *)&mac_addr[2] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
8636
8637                 if (is_valid_ether_addr((u8 *)mac_addr))
8638                         rtl_rar_set(tp, (u8 *)mac_addr);
8639         }
8640         for (i = 0; i < ETH_ALEN; i++)
8641                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
8642
8643         dev->ethtool_ops = &rtl8169_ethtool_ops;
8644         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
8645
8646         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
8647
8648         /* don't enable SG, IP_CSUM and TSO by default - it might not work
8649          * properly for all devices */
8650         dev->features |= NETIF_F_RXCSUM |
8651                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
8652
8653         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8654                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
8655                 NETIF_F_HW_VLAN_CTAG_RX;
8656         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8657                 NETIF_F_HIGHDMA;
8658
8659         tp->cp_cmd |= RxChkSum | RxVlan;
8660
8661         /*
8662          * Pretend we are using VLANs; This bypasses a nasty bug where
8663          * Interrupts stop flowing on high load on 8110SCd controllers.
8664          */
8665         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
8666                 /* Disallow toggling */
8667                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
8668
8669         if (tp->txd_version == RTL_TD_0)
8670                 tp->tso_csum = rtl8169_tso_csum_v1;
8671         else if (tp->txd_version == RTL_TD_1) {
8672                 tp->tso_csum = rtl8169_tso_csum_v2;
8673                 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
8674         } else
8675                 WARN_ON_ONCE(1);
8676
8677         dev->hw_features |= NETIF_F_RXALL;
8678         dev->hw_features |= NETIF_F_RXFCS;
8679
8680         /* MTU range: 60 - hw-specific max */
8681         dev->min_mtu = ETH_ZLEN;
8682         dev->max_mtu = rtl_chip_infos[chipset].jumbo_max;
8683
8684         tp->hw_start = cfg->hw_start;
8685         tp->event_slow = cfg->event_slow;
8686         tp->coalesce_info = cfg->coalesce_info;
8687
8688         tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
8689                 ~(RxBOVF | RxFOVF) : ~0;
8690
8691         timer_setup(&tp->timer, rtl8169_phy_timer, 0);
8692
8693         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
8694
8695         tp->counters = dma_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
8696                                            &tp->counters_phys_addr, GFP_KERNEL);
8697         if (!tp->counters) {
8698                 rc = -ENOMEM;
8699                 goto err_out_msi_5;
8700         }
8701
8702         rc = register_netdev(dev);
8703         if (rc < 0)
8704                 goto err_out_cnt_6;
8705
8706         pci_set_drvdata(pdev, dev);
8707
8708         netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
8709                    rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
8710                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
8711         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
8712                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
8713                            "tx checksumming: %s]\n",
8714                            rtl_chip_infos[chipset].jumbo_max,
8715                            rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
8716         }
8717
8718         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
8719              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
8720              tp->mac_version == RTL_GIGA_MAC_VER_31 ||
8721              tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8722              tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8723              tp->mac_version == RTL_GIGA_MAC_VER_51) &&
8724             r8168_check_dash(tp)) {
8725                 rtl8168_driver_start(tp);
8726         }
8727
8728         if (pci_dev_run_wake(pdev))
8729                 pm_runtime_put_noidle(&pdev->dev);
8730
8731         netif_carrier_off(dev);
8732
8733 out:
8734         return rc;
8735
8736 err_out_cnt_6:
8737         dma_free_coherent(&pdev->dev, sizeof(*tp->counters), tp->counters,
8738                           tp->counters_phys_addr);
8739 err_out_msi_5:
8740         netif_napi_del(&tp->napi);
8741         rtl_disable_msi(pdev, tp);
8742 err_out_unmap_4:
8743         iounmap(ioaddr);
8744 err_out_free_res_3:
8745         pci_release_regions(pdev);
8746 err_out_mwi_2:
8747         pci_clear_mwi(pdev);
8748         pci_disable_device(pdev);
8749 err_out_free_dev_1:
8750         free_netdev(dev);
8751         goto out;
8752 }
8753
8754 static struct pci_driver rtl8169_pci_driver = {
8755         .name           = MODULENAME,
8756         .id_table       = rtl8169_pci_tbl,
8757         .probe          = rtl_init_one,
8758         .remove         = rtl_remove_one,
8759         .shutdown       = rtl_shutdown,
8760         .driver.pm      = RTL8169_PM_OPS,
8761 };
8762
8763 module_pci_driver(rtl8169_pci_driver);