drivers/net/ethernet/nvidia/forcedeth.c

   1 /*
   2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
   3  *
   4  * Note: This driver is a cleanroom reimplementation based on reverse
   5  *      engineered documentation written by Carl-Daniel Hailfinger
   6  *      and Andrew de Quincey.
   7  *
   8  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
   9  * trademarks of NVIDIA Corporation in the United States and other
  10  * countries.
  11  *
  12  * Copyright (C) 2003,4,5 Manfred Spraul
  13  * Copyright (C) 2004 Andrew de Quincey (wol support)
  14  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  15  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
  16  * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License as published by
  20  * the Free Software Foundation; either version 2 of the License, or
  21  * (at your option) any later version.
  22  *
  23  * This program is distributed in the hope that it will be useful,
  24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  26  * GNU General Public License for more details.
  27  *
  28  * You should have received a copy of the GNU General Public License
  29  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  30  *
  31  * Known bugs:
  32  * We suspect that on some hardware no TX done interrupts are generated.
  33  * This means recovery from netif_stop_queue only happens if the hw timer
  34  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
  35  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
  36  * If your hardware reliably generates tx done interrupts, then you can remove
  37  * DEV_NEED_TIMERIRQ from the driver_data flags.
  38  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
  39  * superfluous timer interrupts from the nic.
  40  */
  41
  42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  43
  44 #define FORCEDETH_VERSION               "0.64"
  45 #define DRV_NAME                        "forcedeth"
  46
  47 #include <linux/module.h>
  48 #include <linux/types.h>
  49 #include <linux/pci.h>
  50 #include <linux/interrupt.h>
  51 #include <linux/netdevice.h>
  52 #include <linux/etherdevice.h>
  53 #include <linux/delay.h>
  54 #include <linux/sched.h>
  55 #include <linux/spinlock.h>
  56 #include <linux/ethtool.h>
  57 #include <linux/timer.h>
  58 #include <linux/skbuff.h>
  59 #include <linux/mii.h>
  60 #include <linux/random.h>
  61 #include <linux/if_vlan.h>
  62 #include <linux/dma-mapping.h>
  63 #include <linux/slab.h>
  64 #include <linux/uaccess.h>
  65 #include <linux/prefetch.h>
  66 #include <linux/u64_stats_sync.h>
  67 #include <linux/io.h>
  68
  69 #include <asm/irq.h>
  70
  71 #define TX_WORK_PER_LOOP  64
  72 #define RX_WORK_PER_LOOP  64
  73
  74 /*
  75  * Hardware access:
  76  */
  77
  78 #define DEV_NEED_TIMERIRQ          0x0000001  /* set the timer irq flag in the irq mask */
  79 #define DEV_NEED_LINKTIMER         0x0000002  /* poll link settings. Relies on the timer irq */
  80 #define DEV_HAS_LARGEDESC          0x0000004  /* device supports jumbo frames and needs packet format 2 */
  81 #define DEV_HAS_HIGH_DMA           0x0000008  /* device supports 64bit dma */
  82 #define DEV_HAS_CHECKSUM           0x0000010  /* device supports tx and rx checksum offloads */
  83 #define DEV_HAS_VLAN               0x0000020  /* device supports vlan tagging and striping */
  84 #define DEV_HAS_MSI                0x0000040  /* device supports MSI */
  85 #define DEV_HAS_MSI_X              0x0000080  /* device supports MSI-X */
  86 #define DEV_HAS_POWER_CNTRL        0x0000100  /* device supports power savings */
  87 #define DEV_HAS_STATISTICS_V1      0x0000200  /* device supports hw statistics version 1 */
  88 #define DEV_HAS_STATISTICS_V2      0x0000400  /* device supports hw statistics version 2 */
  89 #define DEV_HAS_STATISTICS_V3      0x0000800  /* device supports hw statistics version 3 */
  90 #define DEV_HAS_STATISTICS_V12     0x0000600  /* device supports hw statistics version 1 and 2 */
  91 #define DEV_HAS_STATISTICS_V123    0x0000e00  /* device supports hw statistics version 1, 2, and 3 */
  92 #define DEV_HAS_TEST_EXTENDED      0x0001000  /* device supports extended diagnostic test */
  93 #define DEV_HAS_MGMT_UNIT          0x0002000  /* device supports management unit */
  94 #define DEV_HAS_CORRECT_MACADDR    0x0004000  /* device supports correct mac address order */
  95 #define DEV_HAS_COLLISION_FIX      0x0008000  /* device supports tx collision fix */
  96 #define DEV_HAS_PAUSEFRAME_TX_V1   0x0010000  /* device supports tx pause frames version 1 */
  97 #define DEV_HAS_PAUSEFRAME_TX_V2   0x0020000  /* device supports tx pause frames version 2 */
  98 #define DEV_HAS_PAUSEFRAME_TX_V3   0x0040000  /* device supports tx pause frames version 3 */
  99 #define DEV_NEED_TX_LIMIT          0x0080000  /* device needs to limit tx */
 100 #define DEV_NEED_TX_LIMIT2         0x0180000  /* device needs to limit tx, expect for some revs */
 101 #define DEV_HAS_GEAR_MODE          0x0200000  /* device supports gear mode */
 102 #define DEV_NEED_PHY_INIT_FIX      0x0400000  /* device needs specific phy workaround */
 103 #define DEV_NEED_LOW_POWER_FIX     0x0800000  /* device needs special power up workaround */
 104 #define DEV_NEED_MSI_FIX           0x1000000  /* device needs msi workaround */
 105
 106 enum {
 107         NvRegIrqStatus = 0x000,
 108 #define NVREG_IRQSTAT_MIIEVENT  0x040
 109 #define NVREG_IRQSTAT_MASK              0x83ff
 110         NvRegIrqMask = 0x004,
 111 #define NVREG_IRQ_RX_ERROR              0x0001
 112 #define NVREG_IRQ_RX                    0x0002
 113 #define NVREG_IRQ_RX_NOBUF              0x0004
 114 #define NVREG_IRQ_TX_ERR                0x0008
 115 #define NVREG_IRQ_TX_OK                 0x0010
 116 #define NVREG_IRQ_TIMER                 0x0020
 117 #define NVREG_IRQ_LINK                  0x0040
 118 #define NVREG_IRQ_RX_FORCED             0x0080
 119 #define NVREG_IRQ_TX_FORCED             0x0100
 120 #define NVREG_IRQ_RECOVER_ERROR         0x8200
 121 #define NVREG_IRQMASK_THROUGHPUT        0x00df
 122 #define NVREG_IRQMASK_CPU               0x0060
 123 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
 124 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
 125 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
 126
 127         NvRegUnknownSetupReg6 = 0x008,
 128 #define NVREG_UNKSETUP6_VAL             3
 129
 130 /*
 131  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
 132  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
 133  */
 134         NvRegPollingInterval = 0x00c,
 135 #define NVREG_POLL_DEFAULT_THROUGHPUT   65535 /* backup tx cleanup if loop max reached */
 136 #define NVREG_POLL_DEFAULT_CPU  13
 137         NvRegMSIMap0 = 0x020,
 138         NvRegMSIMap1 = 0x024,
 139         NvRegMSIIrqMask = 0x030,
 140 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
 141         NvRegMisc1 = 0x080,
 142 #define NVREG_MISC1_PAUSE_TX    0x01
 143 #define NVREG_MISC1_HD          0x02
 144 #define NVREG_MISC1_FORCE       0x3b0f3c
 145
 146         NvRegMacReset = 0x34,
 147 #define NVREG_MAC_RESET_ASSERT  0x0F3
 148         NvRegTransmitterControl = 0x084,
 149 #define NVREG_XMITCTL_START     0x01
 150 #define NVREG_XMITCTL_MGMT_ST   0x40000000
 151 #define NVREG_XMITCTL_SYNC_MASK         0x000f0000
 152 #define NVREG_XMITCTL_SYNC_NOT_READY    0x0
 153 #define NVREG_XMITCTL_SYNC_PHY_INIT     0x00040000
 154 #define NVREG_XMITCTL_MGMT_SEMA_MASK    0x00000f00
 155 #define NVREG_XMITCTL_MGMT_SEMA_FREE    0x0
 156 #define NVREG_XMITCTL_HOST_SEMA_MASK    0x0000f000
 157 #define NVREG_XMITCTL_HOST_SEMA_ACQ     0x0000f000
 158 #define NVREG_XMITCTL_HOST_LOADED       0x00004000
 159 #define NVREG_XMITCTL_TX_PATH_EN        0x01000000
 160 #define NVREG_XMITCTL_DATA_START        0x00100000
 161 #define NVREG_XMITCTL_DATA_READY        0x00010000
 162 #define NVREG_XMITCTL_DATA_ERROR        0x00020000
 163         NvRegTransmitterStatus = 0x088,
 164 #define NVREG_XMITSTAT_BUSY     0x01
 165
 166         NvRegPacketFilterFlags = 0x8c,
 167 #define NVREG_PFF_PAUSE_RX      0x08
 168 #define NVREG_PFF_ALWAYS        0x7F0000
 169 #define NVREG_PFF_PROMISC       0x80
 170 #define NVREG_PFF_MYADDR        0x20
 171 #define NVREG_PFF_LOOPBACK      0x10
 172
 173         NvRegOffloadConfig = 0x90,
 174 #define NVREG_OFFLOAD_HOMEPHY   0x601
 175 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
 176         NvRegReceiverControl = 0x094,
 177 #define NVREG_RCVCTL_START      0x01
 178 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
 179         NvRegReceiverStatus = 0x98,
 180 #define NVREG_RCVSTAT_BUSY      0x01
 181
 182         NvRegSlotTime = 0x9c,
 183 #define NVREG_SLOTTIME_LEGBF_ENABLED    0x80000000
 184 #define NVREG_SLOTTIME_10_100_FULL      0x00007f00
 185 #define NVREG_SLOTTIME_1000_FULL        0x0003ff00
 186 #define NVREG_SLOTTIME_HALF             0x0000ff00
 187 #define NVREG_SLOTTIME_DEFAULT          0x00007f00
 188 #define NVREG_SLOTTIME_MASK             0x000000ff
 189
 190         NvRegTxDeferral = 0xA0,
 191 #define NVREG_TX_DEFERRAL_DEFAULT               0x15050f
 192 #define NVREG_TX_DEFERRAL_RGMII_10_100          0x16070f
 193 #define NVREG_TX_DEFERRAL_RGMII_1000            0x14050f
 194 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10      0x16190f
 195 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100     0x16300f
 196 #define NVREG_TX_DEFERRAL_MII_STRETCH           0x152000
 197         NvRegRxDeferral = 0xA4,
 198 #define NVREG_RX_DEFERRAL_DEFAULT       0x16
 199         NvRegMacAddrA = 0xA8,
 200         NvRegMacAddrB = 0xAC,
 201         NvRegMulticastAddrA = 0xB0,
 202 #define NVREG_MCASTADDRA_FORCE  0x01
 203         NvRegMulticastAddrB = 0xB4,
 204         NvRegMulticastMaskA = 0xB8,
 205 #define NVREG_MCASTMASKA_NONE           0xffffffff
 206         NvRegMulticastMaskB = 0xBC,
 207 #define NVREG_MCASTMASKB_NONE           0xffff
 208
 209         NvRegPhyInterface = 0xC0,
 210 #define PHY_RGMII               0x10000000
 211         NvRegBackOffControl = 0xC4,
 212 #define NVREG_BKOFFCTRL_DEFAULT                 0x70000000
 213 #define NVREG_BKOFFCTRL_SEED_MASK               0x000003ff
 214 #define NVREG_BKOFFCTRL_SELECT                  24
 215 #define NVREG_BKOFFCTRL_GEAR                    12
 216
 217         NvRegTxRingPhysAddr = 0x100,
 218         NvRegRxRingPhysAddr = 0x104,
 219         NvRegRingSizes = 0x108,
 220 #define NVREG_RINGSZ_TXSHIFT 0
 221 #define NVREG_RINGSZ_RXSHIFT 16
 222         NvRegTransmitPoll = 0x10c,
 223 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
 224         NvRegLinkSpeed = 0x110,
 225 #define NVREG_LINKSPEED_FORCE 0x10000
 226 #define NVREG_LINKSPEED_10      1000
 227 #define NVREG_LINKSPEED_100     100
 228 #define NVREG_LINKSPEED_1000    50
 229 #define NVREG_LINKSPEED_MASK    (0xFFF)
 230         NvRegUnknownSetupReg5 = 0x130,
 231 #define NVREG_UNKSETUP5_BIT31   (1<<31)
 232         NvRegTxWatermark = 0x13c,
 233 #define NVREG_TX_WM_DESC1_DEFAULT       0x0200010
 234 #define NVREG_TX_WM_DESC2_3_DEFAULT     0x1e08000
 235 #define NVREG_TX_WM_DESC2_3_1000        0xfe08000
 236         NvRegTxRxControl = 0x144,
 237 #define NVREG_TXRXCTL_KICK      0x0001
 238 #define NVREG_TXRXCTL_BIT1      0x0002
 239 #define NVREG_TXRXCTL_BIT2      0x0004
 240 #define NVREG_TXRXCTL_IDLE      0x0008
 241 #define NVREG_TXRXCTL_RESET     0x0010
 242 #define NVREG_TXRXCTL_RXCHECK   0x0400
 243 #define NVREG_TXRXCTL_DESC_1    0
 244 #define NVREG_TXRXCTL_DESC_2    0x002100
 245 #define NVREG_TXRXCTL_DESC_3    0xc02200
 246 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
 247 #define NVREG_TXRXCTL_VLANINS   0x00080
 248         NvRegTxRingPhysAddrHigh = 0x148,
 249         NvRegRxRingPhysAddrHigh = 0x14C,
 250         NvRegTxPauseFrame = 0x170,
 251 #define NVREG_TX_PAUSEFRAME_DISABLE     0x0fff0080
 252 #define NVREG_TX_PAUSEFRAME_ENABLE_V1   0x01800010
 253 #define NVREG_TX_PAUSEFRAME_ENABLE_V2   0x056003f0
 254 #define NVREG_TX_PAUSEFRAME_ENABLE_V3   0x09f00880
 255         NvRegTxPauseFrameLimit = 0x174,
 256 #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
 257         NvRegMIIStatus = 0x180,
 258 #define NVREG_MIISTAT_ERROR             0x0001
 259 #define NVREG_MIISTAT_LINKCHANGE        0x0008
 260 #define NVREG_MIISTAT_MASK_RW           0x0007
 261 #define NVREG_MIISTAT_MASK_ALL          0x000f
 262         NvRegMIIMask = 0x184,
 263 #define NVREG_MII_LINKCHANGE            0x0008
 264
 265         NvRegAdapterControl = 0x188,
 266 #define NVREG_ADAPTCTL_START    0x02
 267 #define NVREG_ADAPTCTL_LINKUP   0x04
 268 #define NVREG_ADAPTCTL_PHYVALID 0x40000
 269 #define NVREG_ADAPTCTL_RUNNING  0x100000
 270 #define NVREG_ADAPTCTL_PHYSHIFT 24
 271         NvRegMIISpeed = 0x18c,
 272 #define NVREG_MIISPEED_BIT8     (1<<8)
 273 #define NVREG_MIIDELAY  5
 274         NvRegMIIControl = 0x190,
 275 #define NVREG_MIICTL_INUSE      0x08000
 276 #define NVREG_MIICTL_WRITE      0x00400
 277 #define NVREG_MIICTL_ADDRSHIFT  5
 278         NvRegMIIData = 0x194,
 279         NvRegTxUnicast = 0x1a0,
 280         NvRegTxMulticast = 0x1a4,
 281         NvRegTxBroadcast = 0x1a8,
 282         NvRegWakeUpFlags = 0x200,
 283 #define NVREG_WAKEUPFLAGS_VAL           0x7770
 284 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
 285 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
 286 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
 287 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
 288 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
 289 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
 290 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
 291 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
 292 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
 293 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
 294
 295         NvRegMgmtUnitGetVersion = 0x204,
 296 #define NVREG_MGMTUNITGETVERSION        0x01
 297         NvRegMgmtUnitVersion = 0x208,
 298 #define NVREG_MGMTUNITVERSION           0x08
 299         NvRegPowerCap = 0x268,
 300 #define NVREG_POWERCAP_D3SUPP   (1<<30)
 301 #define NVREG_POWERCAP_D2SUPP   (1<<26)
 302 #define NVREG_POWERCAP_D1SUPP   (1<<25)
 303         NvRegPowerState = 0x26c,
 304 #define NVREG_POWERSTATE_POWEREDUP      0x8000
 305 #define NVREG_POWERSTATE_VALID          0x0100
 306 #define NVREG_POWERSTATE_MASK           0x0003
 307 #define NVREG_POWERSTATE_D0             0x0000
 308 #define NVREG_POWERSTATE_D1             0x0001
 309 #define NVREG_POWERSTATE_D2             0x0002
 310 #define NVREG_POWERSTATE_D3             0x0003
 311         NvRegMgmtUnitControl = 0x278,
 312 #define NVREG_MGMTUNITCONTROL_INUSE     0x20000
 313         NvRegTxCnt = 0x280,
 314         NvRegTxZeroReXmt = 0x284,
 315         NvRegTxOneReXmt = 0x288,
 316         NvRegTxManyReXmt = 0x28c,
 317         NvRegTxLateCol = 0x290,
 318         NvRegTxUnderflow = 0x294,
 319         NvRegTxLossCarrier = 0x298,
 320         NvRegTxExcessDef = 0x29c,
 321         NvRegTxRetryErr = 0x2a0,
 322         NvRegRxFrameErr = 0x2a4,
 323         NvRegRxExtraByte = 0x2a8,
 324         NvRegRxLateCol = 0x2ac,
 325         NvRegRxRunt = 0x2b0,
 326         NvRegRxFrameTooLong = 0x2b4,
 327         NvRegRxOverflow = 0x2b8,
 328         NvRegRxFCSErr = 0x2bc,
 329         NvRegRxFrameAlignErr = 0x2c0,
 330         NvRegRxLenErr = 0x2c4,
 331         NvRegRxUnicast = 0x2c8,
 332         NvRegRxMulticast = 0x2cc,
 333         NvRegRxBroadcast = 0x2d0,
 334         NvRegTxDef = 0x2d4,
 335         NvRegTxFrame = 0x2d8,
 336         NvRegRxCnt = 0x2dc,
 337         NvRegTxPause = 0x2e0,
 338         NvRegRxPause = 0x2e4,
 339         NvRegRxDropFrame = 0x2e8,
 340         NvRegVlanControl = 0x300,
 341 #define NVREG_VLANCONTROL_ENABLE        0x2000
 342         NvRegMSIXMap0 = 0x3e0,
 343         NvRegMSIXMap1 = 0x3e4,
 344         NvRegMSIXIrqStatus = 0x3f0,
 345
 346         NvRegPowerState2 = 0x600,
 347 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F15
 348 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
 349 #define NVREG_POWERSTATE2_PHY_RESET             0x0004
 350 #define NVREG_POWERSTATE2_GATE_CLOCKS           0x0F00
 351 };
 352
 353 /* Big endian: should work, but is untested */
 354 struct ring_desc {
 355         __le32 buf;
 356         __le32 flaglen;
 357 };
 358
 359 struct ring_desc_ex {
 360         __le32 bufhigh;
 361         __le32 buflow;
 362         __le32 txvlan;
 363         __le32 flaglen;
 364 };
 365
 366 union ring_type {
 367         struct ring_desc *orig;
 368         struct ring_desc_ex *ex;
 369 };
 370
 371 #define FLAG_MASK_V1 0xffff0000
 372 #define FLAG_MASK_V2 0xffffc000
 373 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
 374 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
 375
 376 #define NV_TX_LASTPACKET        (1<<16)
 377 #define NV_TX_RETRYERROR        (1<<19)
 378 #define NV_TX_RETRYCOUNT_MASK   (0xF<<20)
 379 #define NV_TX_FORCED_INTERRUPT  (1<<24)
 380 #define NV_TX_DEFERRED          (1<<26)
 381 #define NV_TX_CARRIERLOST       (1<<27)
 382 #define NV_TX_LATECOLLISION     (1<<28)
 383 #define NV_TX_UNDERFLOW         (1<<29)
 384 #define NV_TX_ERROR             (1<<30)
 385 #define NV_TX_VALID             (1<<31)
 386
 387 #define NV_TX2_LASTPACKET       (1<<29)
 388 #define NV_TX2_RETRYERROR       (1<<18)
 389 #define NV_TX2_RETRYCOUNT_MASK  (0xF<<19)
 390 #define NV_TX2_FORCED_INTERRUPT (1<<30)
 391 #define NV_TX2_DEFERRED         (1<<25)
 392 #define NV_TX2_CARRIERLOST      (1<<26)
 393 #define NV_TX2_LATECOLLISION    (1<<27)
 394 #define NV_TX2_UNDERFLOW        (1<<28)
 395 /* error and valid are the same for both */
 396 #define NV_TX2_ERROR            (1<<30)
 397 #define NV_TX2_VALID            (1<<31)
 398 #define NV_TX2_TSO              (1<<28)
 399 #define NV_TX2_TSO_SHIFT        14
 400 #define NV_TX2_TSO_MAX_SHIFT    14
 401 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
 402 #define NV_TX2_CHECKSUM_L3      (1<<27)
 403 #define NV_TX2_CHECKSUM_L4      (1<<26)
 404
 405 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
 406
 407 #define NV_RX_DESCRIPTORVALID   (1<<16)
 408 #define NV_RX_MISSEDFRAME       (1<<17)
 409 #define NV_RX_SUBTRACT1         (1<<18)
 410 #define NV_RX_ERROR1            (1<<23)
 411 #define NV_RX_ERROR2            (1<<24)
 412 #define NV_RX_ERROR3            (1<<25)
 413 #define NV_RX_ERROR4            (1<<26)
 414 #define NV_RX_CRCERR            (1<<27)
 415 #define NV_RX_OVERFLOW          (1<<28)
 416 #define NV_RX_FRAMINGERR        (1<<29)
 417 #define NV_RX_ERROR             (1<<30)
 418 #define NV_RX_AVAIL             (1<<31)
 419 #define NV_RX_ERROR_MASK        (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
 420
 421 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
 422 #define NV_RX2_CHECKSUM_IP      (0x10000000)
 423 #define NV_RX2_CHECKSUM_IP_TCP  (0x14000000)
 424 #define NV_RX2_CHECKSUM_IP_UDP  (0x18000000)
 425 #define NV_RX2_DESCRIPTORVALID  (1<<29)
 426 #define NV_RX2_SUBTRACT1        (1<<25)
 427 #define NV_RX2_ERROR1           (1<<18)
 428 #define NV_RX2_ERROR2           (1<<19)
 429 #define NV_RX2_ERROR3           (1<<20)
 430 #define NV_RX2_ERROR4           (1<<21)
 431 #define NV_RX2_CRCERR           (1<<22)
 432 #define NV_RX2_OVERFLOW         (1<<23)
 433 #define NV_RX2_FRAMINGERR       (1<<24)
 434 /* error and avail are the same for both */
 435 #define NV_RX2_ERROR            (1<<30)
 436 #define NV_RX2_AVAIL            (1<<31)
 437 #define NV_RX2_ERROR_MASK       (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
 438
 439 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
 440 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
 441
 442 /* Miscellaneous hardware related defines: */
 443 #define NV_PCI_REGSZ_VER1       0x270
 444 #define NV_PCI_REGSZ_VER2       0x2d4
 445 #define NV_PCI_REGSZ_VER3       0x604
 446 #define NV_PCI_REGSZ_MAX        0x604
 447
 448 /* various timeout delays: all in usec */
 449 #define NV_TXRX_RESET_DELAY     4
 450 #define NV_TXSTOP_DELAY1        10
 451 #define NV_TXSTOP_DELAY1MAX     500000
 452 #define NV_TXSTOP_DELAY2        100
 453 #define NV_RXSTOP_DELAY1        10
 454 #define NV_RXSTOP_DELAY1MAX     500000
 455 #define NV_RXSTOP_DELAY2        100
 456 #define NV_SETUP5_DELAY         5
 457 #define NV_SETUP5_DELAYMAX      50000
 458 #define NV_POWERUP_DELAY        5
 459 #define NV_POWERUP_DELAYMAX     5000
 460 #define NV_MIIBUSY_DELAY        50
 461 #define NV_MIIPHY_DELAY 10
 462 #define NV_MIIPHY_DELAYMAX      10000
 463 #define NV_MAC_RESET_DELAY      64
 464
 465 #define NV_WAKEUPPATTERNS       5
 466 #define NV_WAKEUPMASKENTRIES    4
 467
 468 /* General driver defaults */
 469 #define NV_WATCHDOG_TIMEO       (5*HZ)
 470
 471 #define RX_RING_DEFAULT         512
 472 #define TX_RING_DEFAULT         256
 473 #define RX_RING_MIN             128
 474 #define TX_RING_MIN             64
 475 #define RING_MAX_DESC_VER_1     1024
 476 #define RING_MAX_DESC_VER_2_3   16384
 477
 478 /* rx/tx mac addr + type + vlan + align + slack*/
 479 #define NV_RX_HEADERS           (64)
 480 /* even more slack. */
 481 #define NV_RX_ALLOC_PAD         (64)
 482
 483 /* maximum mtu size */
 484 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
 485 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
 486
 487 #define OOM_REFILL      (1+HZ/20)
 488 #define POLL_WAIT       (1+HZ/100)
 489 #define LINK_TIMEOUT    (3*HZ)
 490 #define STATS_INTERVAL  (10*HZ)
 491
 492 /*
 493  * desc_ver values:
 494  * The nic supports three different descriptor types:
 495  * - DESC_VER_1: Original
 496  * - DESC_VER_2: support for jumbo frames.
 497  * - DESC_VER_3: 64-bit format.
 498  */
 499 #define DESC_VER_1      1
 500 #define DESC_VER_2      2
 501 #define DESC_VER_3      3
 502
 503 /* PHY defines */
 504 #define PHY_OUI_MARVELL         0x5043
 505 #define PHY_OUI_CICADA          0x03f1
 506 #define PHY_OUI_VITESSE         0x01c1
 507 #define PHY_OUI_REALTEK         0x0732
 508 #define PHY_OUI_REALTEK2        0x0020
 509 #define PHYID1_OUI_MASK 0x03ff
 510 #define PHYID1_OUI_SHFT 6
 511 #define PHYID2_OUI_MASK 0xfc00
 512 #define PHYID2_OUI_SHFT 10
 513 #define PHYID2_MODEL_MASK               0x03f0
 514 #define PHY_MODEL_REALTEK_8211          0x0110
 515 #define PHY_REV_MASK                    0x0001
 516 #define PHY_REV_REALTEK_8211B           0x0000
 517 #define PHY_REV_REALTEK_8211C           0x0001
 518 #define PHY_MODEL_REALTEK_8201          0x0200
 519 #define PHY_MODEL_MARVELL_E3016         0x0220
 520 #define PHY_MARVELL_E3016_INITMASK      0x0300
 521 #define PHY_CICADA_INIT1        0x0f000
 522 #define PHY_CICADA_INIT2        0x0e00
 523 #define PHY_CICADA_INIT3        0x01000
 524 #define PHY_CICADA_INIT4        0x0200
 525 #define PHY_CICADA_INIT5        0x0004
 526 #define PHY_CICADA_INIT6        0x02000
 527 #define PHY_VITESSE_INIT_REG1   0x1f
 528 #define PHY_VITESSE_INIT_REG2   0x10
 529 #define PHY_VITESSE_INIT_REG3   0x11
 530 #define PHY_VITESSE_INIT_REG4   0x12
 531 #define PHY_VITESSE_INIT_MSK1   0xc
 532 #define PHY_VITESSE_INIT_MSK2   0x0180
 533 #define PHY_VITESSE_INIT1       0x52b5
 534 #define PHY_VITESSE_INIT2       0xaf8a
 535 #define PHY_VITESSE_INIT3       0x8
 536 #define PHY_VITESSE_INIT4       0x8f8a
 537 #define PHY_VITESSE_INIT5       0xaf86
 538 #define PHY_VITESSE_INIT6       0x8f86
 539 #define PHY_VITESSE_INIT7       0xaf82
 540 #define PHY_VITESSE_INIT8       0x0100
 541 #define PHY_VITESSE_INIT9       0x8f82
 542 #define PHY_VITESSE_INIT10      0x0
 543 #define PHY_REALTEK_INIT_REG1   0x1f
 544 #define PHY_REALTEK_INIT_REG2   0x19
 545 #define PHY_REALTEK_INIT_REG3   0x13
 546 #define PHY_REALTEK_INIT_REG4   0x14
 547 #define PHY_REALTEK_INIT_REG5   0x18
 548 #define PHY_REALTEK_INIT_REG6   0x11
 549 #define PHY_REALTEK_INIT_REG7   0x01
 550 #define PHY_REALTEK_INIT1       0x0000
 551 #define PHY_REALTEK_INIT2       0x8e00
 552 #define PHY_REALTEK_INIT3       0x0001
 553 #define PHY_REALTEK_INIT4       0xad17
 554 #define PHY_REALTEK_INIT5       0xfb54
 555 #define PHY_REALTEK_INIT6       0xf5c7
 556 #define PHY_REALTEK_INIT7       0x1000
 557 #define PHY_REALTEK_INIT8       0x0003
 558 #define PHY_REALTEK_INIT9       0x0008
 559 #define PHY_REALTEK_INIT10      0x0005
 560 #define PHY_REALTEK_INIT11      0x0200
 561 #define PHY_REALTEK_INIT_MSK1   0x0003
 562
 563 #define PHY_GIGABIT     0x0100
 564
 565 #define PHY_TIMEOUT     0x1
 566 #define PHY_ERROR       0x2
 567
 568 #define PHY_100 0x1
 569 #define PHY_1000        0x2
 570 #define PHY_HALF        0x100
 571
 572 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
 573 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
 574 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
 575 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
 576 #define NV_PAUSEFRAME_RX_REQ     0x0010
 577 #define NV_PAUSEFRAME_TX_REQ     0x0020
 578 #define NV_PAUSEFRAME_AUTONEG    0x0040
 579
 580 /* MSI/MSI-X defines */
 581 #define NV_MSI_X_MAX_VECTORS  8
 582 #define NV_MSI_X_VECTORS_MASK 0x000f
 583 #define NV_MSI_CAPABLE        0x0010
 584 #define NV_MSI_X_CAPABLE      0x0020
 585 #define NV_MSI_ENABLED        0x0040
 586 #define NV_MSI_X_ENABLED      0x0080
 587
 588 #define NV_MSI_X_VECTOR_ALL   0x0
 589 #define NV_MSI_X_VECTOR_RX    0x0
 590 #define NV_MSI_X_VECTOR_TX    0x1
 591 #define NV_MSI_X_VECTOR_OTHER 0x2
 592
 593 #define NV_MSI_PRIV_OFFSET 0x68
 594 #define NV_MSI_PRIV_VALUE  0xffffffff
 595
 596 #define NV_RESTART_TX         0x1
 597 #define NV_RESTART_RX         0x2
 598
 599 #define NV_TX_LIMIT_COUNT     16
 600
 601 #define NV_DYNAMIC_THRESHOLD        4
 602 #define NV_DYNAMIC_MAX_QUIET_COUNT  2048
 603
 604 /* statistics */
 605 struct nv_ethtool_str {
 606         char name[ETH_GSTRING_LEN];
 607 };
 608
 609 static const struct nv_ethtool_str nv_estats_str[] = {
 610         { "tx_bytes" }, /* includes Ethernet FCS CRC */
 611         { "tx_zero_rexmt" },
 612         { "tx_one_rexmt" },
 613         { "tx_many_rexmt" },
 614         { "tx_late_collision" },
 615         { "tx_fifo_errors" },
 616         { "tx_carrier_errors" },
 617         { "tx_excess_deferral" },
 618         { "tx_retry_error" },
 619         { "rx_frame_error" },
 620         { "rx_extra_byte" },
 621         { "rx_late_collision" },
 622         { "rx_runt" },
 623         { "rx_frame_too_long" },
 624         { "rx_over_errors" },
 625         { "rx_crc_errors" },
 626         { "rx_frame_align_error" },
 627         { "rx_length_error" },
 628         { "rx_unicast" },
 629         { "rx_multicast" },
 630         { "rx_broadcast" },
 631         { "rx_packets" },
 632         { "rx_errors_total" },
 633         { "tx_errors_total" },
 634
 635         /* version 2 stats */
 636         { "tx_deferral" },
 637         { "tx_packets" },
 638         { "rx_bytes" }, /* includes Ethernet FCS CRC */
 639         { "tx_pause" },
 640         { "rx_pause" },
 641         { "rx_drop_frame" },
 642
 643         /* version 3 stats */
 644         { "tx_unicast" },
 645         { "tx_multicast" },
 646         { "tx_broadcast" }
 647 };
 648
 649 struct nv_ethtool_stats {
 650         u64 tx_bytes; /* should be ifconfig->tx_bytes + 4*tx_packets */
 651         u64 tx_zero_rexmt;
 652         u64 tx_one_rexmt;
 653         u64 tx_many_rexmt;
 654         u64 tx_late_collision;
 655         u64 tx_fifo_errors;
 656         u64 tx_carrier_errors;
 657         u64 tx_excess_deferral;
 658         u64 tx_retry_error;
 659         u64 rx_frame_error;
 660         u64 rx_extra_byte;
 661         u64 rx_late_collision;
 662         u64 rx_runt;
 663         u64 rx_frame_too_long;
 664         u64 rx_over_errors;
 665         u64 rx_crc_errors;
 666         u64 rx_frame_align_error;
 667         u64 rx_length_error;
 668         u64 rx_unicast;
 669         u64 rx_multicast;
 670         u64 rx_broadcast;
 671         u64 rx_packets; /* should be ifconfig->rx_packets */
 672         u64 rx_errors_total;
 673         u64 tx_errors_total;
 674
 675         /* version 2 stats */
 676         u64 tx_deferral;
 677         u64 tx_packets; /* should be ifconfig->tx_packets */
 678         u64 rx_bytes;   /* should be ifconfig->rx_bytes + 4*rx_packets */
 679         u64 tx_pause;
 680         u64 rx_pause;
 681         u64 rx_drop_frame;
 682
 683         /* version 3 stats */
 684         u64 tx_unicast;
 685         u64 tx_multicast;
 686         u64 tx_broadcast;
 687 };
 688
 689 #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
 690 #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
 691 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
 692
 693 /* diagnostics */
 694 #define NV_TEST_COUNT_BASE 3
 695 #define NV_TEST_COUNT_EXTENDED 4
 696
 697 static const struct nv_ethtool_str nv_etests_str[] = {
 698         { "link      (online/offline)" },
 699         { "register  (offline)       " },
 700         { "interrupt (offline)       " },
 701         { "loopback  (offline)       " }
 702 };
 703
 704 struct register_test {
 705         __u32 reg;
 706         __u32 mask;
 707 };
 708
 709 static const struct register_test nv_registers_test[] = {
 710         { NvRegUnknownSetupReg6, 0x01 },
 711         { NvRegMisc1, 0x03c },
 712         { NvRegOffloadConfig, 0x03ff },
 713         { NvRegMulticastAddrA, 0xffffffff },
 714         { NvRegTxWatermark, 0x0ff },
 715         { NvRegWakeUpFlags, 0x07777 },
 716         { 0, 0 }
 717 };
 718
 719 struct nv_skb_map {
 720         struct sk_buff *skb;
 721         dma_addr_t dma;
 722         unsigned int dma_len:31;
 723         unsigned int dma_single:1;
 724         struct ring_desc_ex *first_tx_desc;
 725         struct nv_skb_map *next_tx_ctx;
 726 };
 727
 728 /*
 729  * SMP locking:
 730  * All hardware access under netdev_priv(dev)->lock, except the performance
 731  * critical parts:
 732  * - rx is (pseudo-) lockless: it relies on the single-threading provided
 733  *      by the arch code for interrupts.
 734  * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
 735  *      needs netdev_priv(dev)->lock :-(
 736  * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
 737  *
 738  * Hardware stats updates are protected by hwstats_lock:
 739  * - updated by nv_do_stats_poll (timer). This is meant to avoid
 740  *   integer wraparound in the NIC stats registers, at low frequency
 741  *   (0.1 Hz)
 742  * - updated by nv_get_ethtool_stats + nv_get_stats64
 743  *
 744  * Software stats are accessed only through 64b synchronization points
 745  * and are not subject to other synchronization techniques (single
 746  * update thread on the TX or RX paths).
 747  */
 748
 749 /* in dev: base, irq */
 750 struct fe_priv {
 751         spinlock_t lock;
 752
 753         struct net_device *dev;
 754         struct napi_struct napi;
 755
 756         /* hardware stats are updated in syscall and timer */
 757         spinlock_t hwstats_lock;
 758         struct nv_ethtool_stats estats;
 759
 760         int in_shutdown;
 761         u32 linkspeed;
 762         int duplex;
 763         int autoneg;
 764         int fixed_mode;
 765         int phyaddr;
 766         int wolenabled;
 767         unsigned int phy_oui;
 768         unsigned int phy_model;
 769         unsigned int phy_rev;
 770         u16 gigabit;
 771         int intr_test;
 772         int recover_error;
 773         int quiet_count;
 774
 775         /* General data: RO fields */
 776         dma_addr_t ring_addr;
 777         struct pci_dev *pci_dev;
 778         u32 orig_mac[2];
 779         u32 events;
 780         u32 irqmask;
 781         u32 desc_ver;
 782         u32 txrxctl_bits;
 783         u32 vlanctl_bits;
 784         u32 driver_data;
 785         u32 device_id;
 786         u32 register_size;
 787         u32 mac_in_use;
 788         int mgmt_version;
 789         int mgmt_sema;
 790
 791         void __iomem *base;
 792
 793         /* rx specific fields.
 794          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 795          */
 796         union ring_type get_rx, put_rx, first_rx, last_rx;
 797         struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
 798         struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
 799         struct nv_skb_map *rx_skb;
 800
 801         union ring_type rx_ring;
 802         unsigned int rx_buf_sz;
 803         unsigned int pkt_limit;
 804         struct timer_list oom_kick;
 805         struct timer_list nic_poll;
 806         struct timer_list stats_poll;
 807         u32 nic_poll_irq;
 808         int rx_ring_size;
 809
 810         /* RX software stats */
 811         struct u64_stats_sync swstats_rx_syncp;
 812         u64 stat_rx_packets;
 813         u64 stat_rx_bytes; /* not always available in HW */
 814         u64 stat_rx_missed_errors;
 815         u64 stat_rx_dropped;
 816
 817         /* media detection workaround.
 818          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 819          */
 820         int need_linktimer;
 821         unsigned long link_timeout;
 822         /*
 823          * tx specific fields.
 824          */
 825         union ring_type get_tx, put_tx, first_tx, last_tx;
 826         struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
 827         struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
 828         struct nv_skb_map *tx_skb;
 829
 830         union ring_type tx_ring;
 831         u32 tx_flags;
 832         int tx_ring_size;
 833         int tx_limit;
 834         u32 tx_pkts_in_progress;
 835         struct nv_skb_map *tx_change_owner;
 836         struct nv_skb_map *tx_end_flip;
 837         int tx_stop;
 838
 839         /* TX software stats */
 840         struct u64_stats_sync swstats_tx_syncp;
 841         u64 stat_tx_packets; /* not always available in HW */
 842         u64 stat_tx_bytes;
 843         u64 stat_tx_dropped;
 844
 845         /* msi/msi-x fields */
 846         u32 msi_flags;
 847         struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
 848
 849         /* flow control */
 850         u32 pause_flags;
 851
 852         /* power saved state */
 853         u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
 854
 855         /* for different msi-x irq type */
 856         char name_rx[IFNAMSIZ + 3];       /* -rx    */
 857         char name_tx[IFNAMSIZ + 3];       /* -tx    */
 858         char name_other[IFNAMSIZ + 6];    /* -other */
 859 };
 860
 861 /*
 862  * Maximum number of loops until we assume that a bit in the irq mask
 863  * is stuck. Overridable with module param.
 864  */
 865 static int max_interrupt_work = 4;
 866
 867 /*
 868  * Optimization can be either throuput mode or cpu mode
 869  *
 870  * Throughput Mode: Every tx and rx packet will generate an interrupt.
 871  * CPU Mode: Interrupts are controlled by a timer.
 872  */
 873 enum {
 874         NV_OPTIMIZATION_MODE_THROUGHPUT,
 875         NV_OPTIMIZATION_MODE_CPU,
 876         NV_OPTIMIZATION_MODE_DYNAMIC
 877 };
 878 static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC;
 879
 880 /*
 881  * Poll interval for timer irq
 882  *
 883  * This interval determines how frequent an interrupt is generated.
 884  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
 885  * Min = 0, and Max = 65535
 886  */
 887 static int poll_interval = -1;
 888
 889 /*
 890  * MSI interrupts
 891  */
 892 enum {
 893         NV_MSI_INT_DISABLED,
 894         NV_MSI_INT_ENABLED
 895 };
 896 static int msi = NV_MSI_INT_ENABLED;
 897
 898 /*
 899  * MSIX interrupts
 900  */
 901 enum {
 902         NV_MSIX_INT_DISABLED,
 903         NV_MSIX_INT_ENABLED
 904 };
 905 static int msix = NV_MSIX_INT_ENABLED;
 906
 907 /*
 908  * DMA 64bit
 909  */
 910 enum {
 911         NV_DMA_64BIT_DISABLED,
 912         NV_DMA_64BIT_ENABLED
 913 };
 914 static int dma_64bit = NV_DMA_64BIT_ENABLED;
 915
 916 /*
 917  * Debug output control for tx_timeout
 918  */
 919 static bool debug_tx_timeout = false;
 920
 921 /*
 922  * Crossover Detection
 923  * Realtek 8201 phy + some OEM boards do not work properly.
 924  */
 925 enum {
 926         NV_CROSSOVER_DETECTION_DISABLED,
 927         NV_CROSSOVER_DETECTION_ENABLED
 928 };
 929 static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
 930
 931 /*
 932  * Power down phy when interface is down (persists through reboot;
 933  * older Linux and other OSes may not power it up again)
 934  */
 935 static int phy_power_down;
 936
 937 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
 938 {
 939         return netdev_priv(dev);
 940 }
 941
 942 static inline u8 __iomem *get_hwbase(struct net_device *dev)
 943 {
 944         return ((struct fe_priv *)netdev_priv(dev))->base;
 945 }
 946
 947 static inline void pci_push(u8 __iomem *base)
 948 {
 949         /* force out pending posted writes */
 950         readl(base);
 951 }
 952
 953 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
 954 {
 955         return le32_to_cpu(prd->flaglen)
 956                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
 957 }
 958
 959 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
 960 {
 961         return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
 962 }
 963
 964 static bool nv_optimized(struct fe_priv *np)
 965 {
 966         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 967                 return false;
 968         return true;
 969 }
 970
 971 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
 972                      int delay, int delaymax)
 973 {
 974         u8 __iomem *base = get_hwbase(dev);
 975
 976         pci_push(base);
 977         do {
 978                 udelay(delay);
 979                 delaymax -= delay;
 980                 if (delaymax < 0)
 981                         return 1;
 982         } while ((readl(base + offset) & mask) != target);
 983         return 0;
 984 }
 985
 986 #define NV_SETUP_RX_RING 0x01
 987 #define NV_SETUP_TX_RING 0x02
 988
 989 static inline u32 dma_low(dma_addr_t addr)
 990 {
 991         return addr;
 992 }
 993
 994 static inline u32 dma_high(dma_addr_t addr)
 995 {
 996         return addr>>31>>1;     /* 0 if 32bit, shift down by 32 if 64bit */
 997 }
 998
 999 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
1000 {
1001         struct fe_priv *np = get_nvpriv(dev);
1002         u8 __iomem *base = get_hwbase(dev);
1003
1004         if (!nv_optimized(np)) {
1005                 if (rxtx_flags & NV_SETUP_RX_RING)
1006                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
1007                 if (rxtx_flags & NV_SETUP_TX_RING)
1008                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1009         } else {
1010                 if (rxtx_flags & NV_SETUP_RX_RING) {
1011                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
1012                         writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
1013                 }
1014                 if (rxtx_flags & NV_SETUP_TX_RING) {
1015                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
1016                         writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
1017                 }
1018         }
1019 }
1020
1021 static void free_rings(struct net_device *dev)
1022 {
1023         struct fe_priv *np = get_nvpriv(dev);
1024
1025         if (!nv_optimized(np)) {
1026                 if (np->rx_ring.orig)
1027                         dma_free_coherent(&np->pci_dev->dev,
1028                                           sizeof(struct ring_desc) *
1029                                           (np->rx_ring_size +
1030                                           np->tx_ring_size),
1031                                           np->rx_ring.orig, np->ring_addr);
1032         } else {
1033                 if (np->rx_ring.ex)
1034                         dma_free_coherent(&np->pci_dev->dev,
1035                                           sizeof(struct ring_desc_ex) *
1036                                           (np->rx_ring_size +
1037                                           np->tx_ring_size),
1038                                           np->rx_ring.ex, np->ring_addr);
1039         }
1040         kfree(np->rx_skb);
1041         kfree(np->tx_skb);
1042 }
1043
1044 static int using_multi_irqs(struct net_device *dev)
1045 {
1046         struct fe_priv *np = get_nvpriv(dev);
1047
1048         if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
1049             ((np->msi_flags & NV_MSI_X_ENABLED) &&
1050              ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
1051                 return 0;
1052         else
1053                 return 1;
1054 }
1055
1056 static void nv_txrx_gate(struct net_device *dev, bool gate)
1057 {
1058         struct fe_priv *np = get_nvpriv(dev);
1059         u8 __iomem *base = get_hwbase(dev);
1060         u32 powerstate;
1061
1062         if (!np->mac_in_use &&
1063             (np->driver_data & DEV_HAS_POWER_CNTRL)) {
1064                 powerstate = readl(base + NvRegPowerState2);
1065                 if (gate)
1066                         powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS;
1067                 else
1068                         powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS;
1069                 writel(powerstate, base + NvRegPowerState2);
1070         }
1071 }
1072
1073 static void nv_enable_irq(struct net_device *dev)
1074 {
1075         struct fe_priv *np = get_nvpriv(dev);
1076
1077         if (!using_multi_irqs(dev)) {
1078                 if (np->msi_flags & NV_MSI_X_ENABLED)
1079                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1080                 else
1081                         enable_irq(np->pci_dev->irq);
1082         } else {
1083                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1084                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1085                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1086         }
1087 }
1088
1089 static void nv_disable_irq(struct net_device *dev)
1090 {
1091         struct fe_priv *np = get_nvpriv(dev);
1092
1093         if (!using_multi_irqs(dev)) {
1094                 if (np->msi_flags & NV_MSI_X_ENABLED)
1095                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1096                 else
1097                         disable_irq(np->pci_dev->irq);
1098         } else {
1099                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1100                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1101                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1102         }
1103 }
1104
1105 /* In MSIX mode, a write to irqmask behaves as XOR */
1106 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1107 {
1108         u8 __iomem *base = get_hwbase(dev);
1109
1110         writel(mask, base + NvRegIrqMask);
1111 }
1112
1113 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1114 {
1115         struct fe_priv *np = get_nvpriv(dev);
1116         u8 __iomem *base = get_hwbase(dev);
1117
1118         if (np->msi_flags & NV_MSI_X_ENABLED) {
1119                 writel(mask, base + NvRegIrqMask);
1120         } else {
1121                 if (np->msi_flags & NV_MSI_ENABLED)
1122                         writel(0, base + NvRegMSIIrqMask);
1123                 writel(0, base + NvRegIrqMask);
1124         }
1125 }
1126
1127 static void nv_napi_enable(struct net_device *dev)
1128 {
1129         struct fe_priv *np = get_nvpriv(dev);
1130
1131         napi_enable(&np->napi);
1132 }
1133
1134 static void nv_napi_disable(struct net_device *dev)
1135 {
1136         struct fe_priv *np = get_nvpriv(dev);
1137
1138         napi_disable(&np->napi);
1139 }
1140
1141 #define MII_READ        (-1)
1142 /* mii_rw: read/write a register on the PHY.
1143  *
1144  * Caller must guarantee serialization
1145  */
1146 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1147 {
1148         u8 __iomem *base = get_hwbase(dev);
1149         u32 reg;
1150         int retval;
1151
1152         writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1153
1154         reg = readl(base + NvRegMIIControl);
1155         if (reg & NVREG_MIICTL_INUSE) {
1156                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1157                 udelay(NV_MIIBUSY_DELAY);
1158         }
1159
1160         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1161         if (value != MII_READ) {
1162                 writel(value, base + NvRegMIIData);
1163                 reg |= NVREG_MIICTL_WRITE;
1164         }
1165         writel(reg, base + NvRegMIIControl);
1166
1167         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1168                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX)) {
1169                 retval = -1;
1170         } else if (value != MII_READ) {
1171                 /* it was a write operation - fewer failures are detectable */
1172                 retval = 0;
1173         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1174                 retval = -1;
1175         } else {
1176                 retval = readl(base + NvRegMIIData);
1177         }
1178
1179         return retval;
1180 }
1181
1182 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1183 {
1184         struct fe_priv *np = netdev_priv(dev);
1185         u32 miicontrol;
1186         unsigned int tries = 0;
1187
1188         miicontrol = BMCR_RESET | bmcr_setup;
1189         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol))
1190                 return -1;
1191
1192         /* wait for 500ms */
1193         msleep(500);
1194
1195         /* must wait till reset is deasserted */
1196         while (miicontrol & BMCR_RESET) {
1197                 usleep_range(10000, 20000);
1198                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1199                 /* FIXME: 100 tries seem excessive */
1200                 if (tries++ > 100)
1201                         return -1;
1202         }
1203         return 0;
1204 }
1205
1206 static int init_realtek_8211b(struct net_device *dev, struct fe_priv *np)
1207 {
1208         static const struct {
1209                 int reg;
1210                 int init;
1211         } ri[] = {
1212                 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1213                 { PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2 },
1214                 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3 },
1215                 { PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4 },
1216                 { PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5 },
1217                 { PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6 },
1218                 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1219         };
1220         int i;
1221
1222         for (i = 0; i < ARRAY_SIZE(ri); i++) {
1223                 if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init))
1224                         return PHY_ERROR;
1225         }
1226
1227         return 0;
1228 }
1229
1230 static int init_realtek_8211c(struct net_device *dev, struct fe_priv *np)
1231 {
1232         u32 reg;
1233         u8 __iomem *base = get_hwbase(dev);
1234         u32 powerstate = readl(base + NvRegPowerState2);
1235
1236         /* need to perform hw phy reset */
1237         powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1238         writel(powerstate, base + NvRegPowerState2);
1239         msleep(25);
1240
1241         powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1242         writel(powerstate, base + NvRegPowerState2);
1243         msleep(25);
1244
1245         reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1246         reg |= PHY_REALTEK_INIT9;
1247         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg))
1248                 return PHY_ERROR;
1249         if (mii_rw(dev, np->phyaddr,
1250                    PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10))
1251                 return PHY_ERROR;
1252         reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1253         if (!(reg & PHY_REALTEK_INIT11)) {
1254                 reg |= PHY_REALTEK_INIT11;
1255                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg))
1256                         return PHY_ERROR;
1257         }
1258         if (mii_rw(dev, np->phyaddr,
1259                    PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1260                 return PHY_ERROR;
1261
1262         return 0;
1263 }
1264
1265 static int init_realtek_8201(struct net_device *dev, struct fe_priv *np)
1266 {
1267         u32 phy_reserved;
1268
1269         if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1270                 phy_reserved = mii_rw(dev, np->phyaddr,
1271                                       PHY_REALTEK_INIT_REG6, MII_READ);
1272                 phy_reserved |= PHY_REALTEK_INIT7;
1273                 if (mii_rw(dev, np->phyaddr,
1274                            PHY_REALTEK_INIT_REG6, phy_reserved))
1275                         return PHY_ERROR;
1276         }
1277
1278         return 0;
1279 }
1280
1281 static int init_realtek_8201_cross(struct net_device *dev, struct fe_priv *np)
1282 {
1283         u32 phy_reserved;
1284
1285         if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1286                 if (mii_rw(dev, np->phyaddr,
1287                            PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3))
1288                         return PHY_ERROR;
1289                 phy_reserved = mii_rw(dev, np->phyaddr,
1290                                       PHY_REALTEK_INIT_REG2, MII_READ);
1291                 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1292                 phy_reserved |= PHY_REALTEK_INIT3;
1293                 if (mii_rw(dev, np->phyaddr,
1294                            PHY_REALTEK_INIT_REG2, phy_reserved))
1295                         return PHY_ERROR;
1296                 if (mii_rw(dev, np->phyaddr,
1297                            PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1298                         return PHY_ERROR;
1299         }
1300
1301         return 0;
1302 }
1303
1304 static int init_cicada(struct net_device *dev, struct fe_priv *np,
1305                        u32 phyinterface)
1306 {
1307         u32 phy_reserved;
1308
1309         if (phyinterface & PHY_RGMII) {
1310                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1311                 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1312                 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1313                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved))
1314                         return PHY_ERROR;
1315                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1316                 phy_reserved |= PHY_CICADA_INIT5;
1317                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved))
1318                         return PHY_ERROR;
1319         }
1320         phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1321         phy_reserved |= PHY_CICADA_INIT6;
1322         if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved))
1323                 return PHY_ERROR;
1324
1325         return 0;
1326 }
1327
1328 static int init_vitesse(struct net_device *dev, struct fe_priv *np)
1329 {
1330         u32 phy_reserved;
1331
1332         if (mii_rw(dev, np->phyaddr,
1333                    PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1))
1334                 return PHY_ERROR;
1335         if (mii_rw(dev, np->phyaddr,
1336                    PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2))
1337                 return PHY_ERROR;
1338         phy_reserved = mii_rw(dev, np->phyaddr,
1339                               PHY_VITESSE_INIT_REG4, MII_READ);
1340         if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1341                 return PHY_ERROR;
1342         phy_reserved = mii_rw(dev, np->phyaddr,
1343                               PHY_VITESSE_INIT_REG3, MII_READ);
1344         phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1345         phy_reserved |= PHY_VITESSE_INIT3;
1346         if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1347                 return PHY_ERROR;
1348         if (mii_rw(dev, np->phyaddr,
1349                    PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4))
1350                 return PHY_ERROR;
1351         if (mii_rw(dev, np->phyaddr,
1352                    PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5))
1353                 return PHY_ERROR;
1354         phy_reserved = mii_rw(dev, np->phyaddr,
1355                               PHY_VITESSE_INIT_REG4, MII_READ);
1356         phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1357         phy_reserved |= PHY_VITESSE_INIT3;
1358         if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1359                 return PHY_ERROR;
1360         phy_reserved = mii_rw(dev, np->phyaddr,
1361                               PHY_VITESSE_INIT_REG3, MII_READ);
1362         if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1363                 return PHY_ERROR;
1364         if (mii_rw(dev, np->phyaddr,
1365                    PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6))
1366                 return PHY_ERROR;
1367         if (mii_rw(dev, np->phyaddr,
1368                    PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7))
1369                 return PHY_ERROR;
1370         phy_reserved = mii_rw(dev, np->phyaddr,
1371                               PHY_VITESSE_INIT_REG4, MII_READ);
1372         if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1373                 return PHY_ERROR;
1374         phy_reserved = mii_rw(dev, np->phyaddr,
1375                               PHY_VITESSE_INIT_REG3, MII_READ);
1376         phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1377         phy_reserved |= PHY_VITESSE_INIT8;
1378         if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1379                 return PHY_ERROR;
1380         if (mii_rw(dev, np->phyaddr,
1381                    PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9))
1382                 return PHY_ERROR;
1383         if (mii_rw(dev, np->phyaddr,
1384                    PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10))
1385                 return PHY_ERROR;
1386
1387         return 0;
1388 }
1389
1390 static int phy_init(struct net_device *dev)
1391 {
1392         struct fe_priv *np = get_nvpriv(dev);
1393         u8 __iomem *base = get_hwbase(dev);
1394         u32 phyinterface;
1395         u32 mii_status, mii_control, mii_control_1000, reg;
1396
1397         /* phy errata for E3016 phy */
1398         if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1399                 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1400                 reg &= ~PHY_MARVELL_E3016_INITMASK;
1401                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1402                         netdev_info(dev, "%s: phy write to errata reg failed\n",
1403                                     pci_name(np->pci_dev));
1404                         return PHY_ERROR;
1405                 }
1406         }
1407         if (np->phy_oui == PHY_OUI_REALTEK) {
1408                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1409                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1410                         if (init_realtek_8211b(dev, np)) {
1411                                 netdev_info(dev, "%s: phy init failed\n",
1412                                             pci_name(np->pci_dev));
1413                                 return PHY_ERROR;
1414                         }
1415                 } else if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1416                            np->phy_rev == PHY_REV_REALTEK_8211C) {
1417                         if (init_realtek_8211c(dev, np)) {
1418                                 netdev_info(dev, "%s: phy init failed\n",
1419                                             pci_name(np->pci_dev));
1420                                 return PHY_ERROR;
1421                         }
1422                 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1423                         if (init_realtek_8201(dev, np)) {
1424                                 netdev_info(dev, "%s: phy init failed\n",
1425                                             pci_name(np->pci_dev));
1426                                 return PHY_ERROR;
1427                         }
1428                 }
1429         }
1430
1431         /* set advertise register */
1432         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1433         reg |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
1434                 ADVERTISE_100HALF | ADVERTISE_100FULL |
1435                 ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1436         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1437                 netdev_info(dev, "%s: phy write to advertise failed\n",
1438                             pci_name(np->pci_dev));
1439                 return PHY_ERROR;
1440         }
1441
1442         /* get phy interface type */
1443         phyinterface = readl(base + NvRegPhyInterface);
1444
1445         /* see if gigabit phy */
1446         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1447         if (mii_status & PHY_GIGABIT) {
1448                 np->gigabit = PHY_GIGABIT;
1449                 mii_control_1000 = mii_rw(dev, np->phyaddr,
1450                                           MII_CTRL1000, MII_READ);
1451                 mii_control_1000 &= ~ADVERTISE_1000HALF;
1452                 if (phyinterface & PHY_RGMII)
1453                         mii_control_1000 |= ADVERTISE_1000FULL;
1454                 else
1455                         mii_control_1000 &= ~ADVERTISE_1000FULL;
1456
1457                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1458                         netdev_info(dev, "%s: phy init failed\n",
1459                                     pci_name(np->pci_dev));
1460                         return PHY_ERROR;
1461                 }
1462         } else
1463                 np->gigabit = 0;
1464
1465         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1466         mii_control |= BMCR_ANENABLE;
1467
1468         if (np->phy_oui == PHY_OUI_REALTEK &&
1469             np->phy_model == PHY_MODEL_REALTEK_8211 &&
1470             np->phy_rev == PHY_REV_REALTEK_8211C) {
1471                 /* start autoneg since we already performed hw reset above */
1472                 mii_control |= BMCR_ANRESTART;
1473                 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1474                         netdev_info(dev, "%s: phy init failed\n",
1475                                     pci_name(np->pci_dev));
1476                         return PHY_ERROR;
1477                 }
1478         } else {
1479                 /* reset the phy
1480                  * (certain phys need bmcr to be setup with reset)
1481                  */
1482                 if (phy_reset(dev, mii_control)) {
1483                         netdev_info(dev, "%s: phy reset failed\n",
1484                                     pci_name(np->pci_dev));
1485                         return PHY_ERROR;
1486                 }
1487         }
1488
1489         /* phy vendor specific configuration */
1490         if (np->phy_oui == PHY_OUI_CICADA) {
1491                 if (init_cicada(dev, np, phyinterface)) {
1492                         netdev_info(dev, "%s: phy init failed\n",
1493                                     pci_name(np->pci_dev));
1494                         return PHY_ERROR;
1495                 }
1496         } else if (np->phy_oui == PHY_OUI_VITESSE) {
1497                 if (init_vitesse(dev, np)) {
1498                         netdev_info(dev, "%s: phy init failed\n",
1499                                     pci_name(np->pci_dev));
1500                         return PHY_ERROR;
1501                 }
1502         } else if (np->phy_oui == PHY_OUI_REALTEK) {
1503                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1504                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1505                         /* reset could have cleared these out, set them back */
1506                         if (init_realtek_8211b(dev, np)) {
1507                                 netdev_info(dev, "%s: phy init failed\n",
1508                                             pci_name(np->pci_dev));
1509                                 return PHY_ERROR;
1510                         }
1511                 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1512                         if (init_realtek_8201(dev, np) ||
1513                             init_realtek_8201_cross(dev, np)) {
1514                                 netdev_info(dev, "%s: phy init failed\n",
1515                                             pci_name(np->pci_dev));
1516                                 return PHY_ERROR;
1517                         }
1518                 }
1519         }
1520
1521         /* some phys clear out pause advertisement on reset, set it back */
1522         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1523
1524         /* restart auto negotiation, power down phy */
1525         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1526         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1527         if (phy_power_down)
1528                 mii_control |= BMCR_PDOWN;
1529         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control))
1530                 return PHY_ERROR;
1531
1532         return 0;
1533 }
1534
1535 static void nv_start_rx(struct net_device *dev)
1536 {
1537         struct fe_priv *np = netdev_priv(dev);
1538         u8 __iomem *base = get_hwbase(dev);
1539         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1540
1541         /* Already running? Stop it. */
1542         if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1543                 rx_ctrl &= ~NVREG_RCVCTL_START;
1544                 writel(rx_ctrl, base + NvRegReceiverControl);
1545                 pci_push(base);
1546         }
1547         writel(np->linkspeed, base + NvRegLinkSpeed);
1548         pci_push(base);
1549         rx_ctrl |= NVREG_RCVCTL_START;
1550         if (np->mac_in_use)
1551                 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1552         writel(rx_ctrl, base + NvRegReceiverControl);
1553         pci_push(base);
1554 }
1555
1556 static void nv_stop_rx(struct net_device *dev)
1557 {
1558         struct fe_priv *np = netdev_priv(dev);
1559         u8 __iomem *base = get_hwbase(dev);
1560         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1561
1562         if (!np->mac_in_use)
1563                 rx_ctrl &= ~NVREG_RCVCTL_START;
1564         else
1565                 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1566         writel(rx_ctrl, base + NvRegReceiverControl);
1567         if (reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1568                       NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX))
1569                 netdev_info(dev, "%s: ReceiverStatus remained busy\n",
1570                             __func__);
1571
1572         udelay(NV_RXSTOP_DELAY2);
1573         if (!np->mac_in_use)
1574                 writel(0, base + NvRegLinkSpeed);
1575 }
1576
1577 static void nv_start_tx(struct net_device *dev)
1578 {
1579         struct fe_priv *np = netdev_priv(dev);
1580         u8 __iomem *base = get_hwbase(dev);
1581         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1582
1583         tx_ctrl |= NVREG_XMITCTL_START;
1584         if (np->mac_in_use)
1585                 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1586         writel(tx_ctrl, base + NvRegTransmitterControl);
1587         pci_push(base);
1588 }
1589
1590 static void nv_stop_tx(struct net_device *dev)
1591 {
1592         struct fe_priv *np = netdev_priv(dev);
1593         u8 __iomem *base = get_hwbase(dev);
1594         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1595
1596         if (!np->mac_in_use)
1597                 tx_ctrl &= ~NVREG_XMITCTL_START;
1598         else
1599                 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1600         writel(tx_ctrl, base + NvRegTransmitterControl);
1601         if (reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1602                       NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX))
1603                 netdev_info(dev, "%s: TransmitterStatus remained busy\n",
1604                             __func__);
1605
1606         udelay(NV_TXSTOP_DELAY2);
1607         if (!np->mac_in_use)
1608                 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1609                        base + NvRegTransmitPoll);
1610 }
1611
1612 static void nv_start_rxtx(struct net_device *dev)
1613 {
1614         nv_start_rx(dev);
1615         nv_start_tx(dev);
1616 }
1617
1618 static void nv_stop_rxtx(struct net_device *dev)
1619 {
1620         nv_stop_rx(dev);
1621         nv_stop_tx(dev);
1622 }
1623
1624 static void nv_txrx_reset(struct net_device *dev)
1625 {
1626         struct fe_priv *np = netdev_priv(dev);
1627         u8 __iomem *base = get_hwbase(dev);
1628
1629         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1630         pci_push(base);
1631         udelay(NV_TXRX_RESET_DELAY);
1632         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1633         pci_push(base);
1634 }
1635
1636 static void nv_mac_reset(struct net_device *dev)
1637 {
1638         struct fe_priv *np = netdev_priv(dev);
1639         u8 __iomem *base = get_hwbase(dev);
1640         u32 temp1, temp2, temp3;
1641
1642         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1643         pci_push(base);
1644
1645         /* save registers since they will be cleared on reset */
1646         temp1 = readl(base + NvRegMacAddrA);
1647         temp2 = readl(base + NvRegMacAddrB);
1648         temp3 = readl(base + NvRegTransmitPoll);
1649
1650         writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1651         pci_push(base);
1652         udelay(NV_MAC_RESET_DELAY);
1653         writel(0, base + NvRegMacReset);
1654         pci_push(base);
1655         udelay(NV_MAC_RESET_DELAY);
1656
1657         /* restore saved registers */
1658         writel(temp1, base + NvRegMacAddrA);
1659         writel(temp2, base + NvRegMacAddrB);
1660         writel(temp3, base + NvRegTransmitPoll);
1661
1662         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1663         pci_push(base);
1664 }
1665
1666 /* Caller must appropriately lock netdev_priv(dev)->hwstats_lock */
1667 static void nv_update_stats(struct net_device *dev)
1668 {
1669         struct fe_priv *np = netdev_priv(dev);
1670         u8 __iomem *base = get_hwbase(dev);
1671
1672         /* If it happens that this is run in top-half context, then
1673          * replace the spin_lock of hwstats_lock with
1674          * spin_lock_irqsave() in calling functions. */
1675         WARN_ONCE(in_irq(), "forcedeth: estats spin_lock(_bh) from top-half");
1676         assert_spin_locked(&np->hwstats_lock);
1677
1678         /* query hardware */
1679         np->estats.tx_bytes += readl(base + NvRegTxCnt);
1680         np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1681         np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1682         np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1683         np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1684         np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1685         np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1686         np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1687         np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1688         np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1689         np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1690         np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1691         np->estats.rx_runt += readl(base + NvRegRxRunt);
1692         np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1693         np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1694         np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1695         np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1696         np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1697         np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1698         np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1699         np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1700         np->estats.rx_packets =
1701                 np->estats.rx_unicast +
1702                 np->estats.rx_multicast +
1703                 np->estats.rx_broadcast;
1704         np->estats.rx_errors_total =
1705                 np->estats.rx_crc_errors +
1706                 np->estats.rx_over_errors +
1707                 np->estats.rx_frame_error +
1708                 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1709                 np->estats.rx_late_collision +
1710                 np->estats.rx_runt +
1711                 np->estats.rx_frame_too_long;
1712         np->estats.tx_errors_total =
1713                 np->estats.tx_late_collision +
1714                 np->estats.tx_fifo_errors +
1715                 np->estats.tx_carrier_errors +
1716                 np->estats.tx_excess_deferral +
1717                 np->estats.tx_retry_error;
1718
1719         if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1720                 np->estats.tx_deferral += readl(base + NvRegTxDef);
1721                 np->estats.tx_packets += readl(base + NvRegTxFrame);
1722                 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1723                 np->estats.tx_pause += readl(base + NvRegTxPause);
1724                 np->estats.rx_pause += readl(base + NvRegRxPause);
1725                 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1726                 np->estats.rx_errors_total += np->estats.rx_drop_frame;
1727         }
1728
1729         if (np->driver_data & DEV_HAS_STATISTICS_V3) {
1730                 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1731                 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1732                 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
1733         }
1734 }
1735
1736 /*
1737  * nv_get_stats64: dev->ndo_get_stats64 function
1738  * Get latest stats value from the nic.
1739  * Called with read_lock(&dev_base_lock) held for read -
1740  * only synchronized against unregister_netdevice.
1741  */
1742 static void
1743 nv_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *storage)
1744         __acquires(&netdev_priv(dev)->hwstats_lock)
1745         __releases(&netdev_priv(dev)->hwstats_lock)
1746 {
1747         struct fe_priv *np = netdev_priv(dev);
1748         unsigned int syncp_start;
1749
1750         /*
1751          * Note: because HW stats are not always available and for
1752          * consistency reasons, the following ifconfig stats are
1753          * managed by software: rx_bytes, tx_bytes, rx_packets and
1754          * tx_packets. The related hardware stats reported by ethtool
1755          * should be equivalent to these ifconfig stats, with 4
1756          * additional bytes per packet (Ethernet FCS CRC), except for
1757          * tx_packets when TSO kicks in.
1758          */
1759
1760         /* software stats */
1761         do {
1762                 syncp_start = u64_stats_fetch_begin_irq(&np->swstats_rx_syncp);
1763                 storage->rx_packets       = np->stat_rx_packets;
1764                 storage->rx_bytes         = np->stat_rx_bytes;
1765                 storage->rx_dropped       = np->stat_rx_dropped;
1766                 storage->rx_missed_errors = np->stat_rx_missed_errors;
1767         } while (u64_stats_fetch_retry_irq(&np->swstats_rx_syncp, syncp_start));
1768
1769         do {
1770                 syncp_start = u64_stats_fetch_begin_irq(&np->swstats_tx_syncp);
1771                 storage->tx_packets = np->stat_tx_packets;
1772                 storage->tx_bytes   = np->stat_tx_bytes;
1773                 storage->tx_dropped = np->stat_tx_dropped;
1774         } while (u64_stats_fetch_retry_irq(&np->swstats_tx_syncp, syncp_start));
1775
1776         /* If the nic supports hw counters then retrieve latest values */
1777         if (np->driver_data & DEV_HAS_STATISTICS_V123) {
1778                 spin_lock_bh(&np->hwstats_lock);
1779
1780                 nv_update_stats(dev);
1781
1782                 /* generic stats */
1783                 storage->rx_errors = np->estats.rx_errors_total;
1784                 storage->tx_errors = np->estats.tx_errors_total;
1785
1786                 /* meaningful only when NIC supports stats v3 */
1787                 storage->multicast = np->estats.rx_multicast;
1788
1789                 /* detailed rx_errors */
1790                 storage->rx_length_errors = np->estats.rx_length_error;
1791                 storage->rx_over_errors   = np->estats.rx_over_errors;
1792                 storage->rx_crc_errors    = np->estats.rx_crc_errors;
1793                 storage->rx_frame_errors  = np->estats.rx_frame_align_error;
1794                 storage->rx_fifo_errors   = np->estats.rx_drop_frame;
1795
1796                 /* detailed tx_errors */
1797                 storage->tx_carrier_errors = np->estats.tx_carrier_errors;
1798                 storage->tx_fifo_errors    = np->estats.tx_fifo_errors;
1799
1800                 spin_unlock_bh(&np->hwstats_lock);
1801         }
1802 }
1803
1804 /*
1805  * nv_alloc_rx: fill rx ring entries.
1806  * Return 1 if the allocations for the skbs failed and the
1807  * rx engine is without Available descriptors
1808  */
1809 static int nv_alloc_rx(struct net_device *dev)
1810 {
1811         struct fe_priv *np = netdev_priv(dev);
1812         struct ring_desc *less_rx;
1813
1814         less_rx = np->get_rx.orig;
1815         if (less_rx-- == np->first_rx.orig)
1816                 less_rx = np->last_rx.orig;
1817
1818         while (np->put_rx.orig != less_rx) {
1819                 struct sk_buff *skb = netdev_alloc_skb(dev, np->rx_buf_sz + NV_RX_ALLOC_PAD);
1820                 if (skb) {
1821                         np->put_rx_ctx->skb = skb;
1822                         np->put_rx_ctx->dma = dma_map_single(&np->pci_dev->dev,
1823                                                              skb->data,
1824                                                              skb_tailroom(skb),
1825                                                              DMA_FROM_DEVICE);
1826                         if (unlikely(dma_mapping_error(&np->pci_dev->dev,
1827                                                        np->put_rx_ctx->dma))) {
1828                                 kfree_skb(skb);
1829                                 goto packet_dropped;
1830                         }
1831                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1832                         np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1833                         wmb();
1834                         np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1835                         if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1836                                 np->put_rx.orig = np->first_rx.orig;
1837                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1838                                 np->put_rx_ctx = np->first_rx_ctx;
1839                 } else {
1840 packet_dropped:
1841                         u64_stats_update_begin(&np->swstats_rx_syncp);
1842                         np->stat_rx_dropped++;
1843                         u64_stats_update_end(&np->swstats_rx_syncp);
1844                         return 1;
1845                 }
1846         }
1847         return 0;
1848 }
1849
1850 static int nv_alloc_rx_optimized(struct net_device *dev)
1851 {
1852         struct fe_priv *np = netdev_priv(dev);
1853         struct ring_desc_ex *less_rx;
1854
1855         less_rx = np->get_rx.ex;
1856         if (less_rx-- == np->first_rx.ex)
1857                 less_rx = np->last_rx.ex;
1858
1859         while (np->put_rx.ex != less_rx) {
1860                 struct sk_buff *skb = netdev_alloc_skb(dev, np->rx_buf_sz + NV_RX_ALLOC_PAD);
1861                 if (skb) {
1862                         np->put_rx_ctx->skb = skb;
1863                         np->put_rx_ctx->dma = dma_map_single(&np->pci_dev->dev,
1864                                                              skb->data,
1865                                                              skb_tailroom(skb),
1866                                                              DMA_FROM_DEVICE);
1867                         if (unlikely(dma_mapping_error(&np->pci_dev->dev,
1868                                                        np->put_rx_ctx->dma))) {
1869                                 kfree_skb(skb);
1870                                 goto packet_dropped;
1871                         }
1872                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1873                         np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1874                         np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
1875                         wmb();
1876                         np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1877                         if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1878                                 np->put_rx.ex = np->first_rx.ex;
1879                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1880                                 np->put_rx_ctx = np->first_rx_ctx;
1881                 } else {
1882 packet_dropped:
1883                         u64_stats_update_begin(&np->swstats_rx_syncp);
1884                         np->stat_rx_dropped++;
1885                         u64_stats_update_end(&np->swstats_rx_syncp);
1886                         return 1;
1887                 }
1888         }
1889         return 0;
1890 }
1891
1892 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1893 static void nv_do_rx_refill(struct timer_list *t)
1894 {
1895         struct fe_priv *np = from_timer(np, t, oom_kick);
1896
1897         /* Just reschedule NAPI rx processing */
1898         napi_schedule(&np->napi);
1899 }
1900
1901 static void nv_init_rx(struct net_device *dev)
1902 {
1903         struct fe_priv *np = netdev_priv(dev);
1904         int i;
1905
1906         np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1907
1908         if (!nv_optimized(np))
1909                 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1910         else
1911                 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1912         np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1913         np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1914
1915         for (i = 0; i < np->rx_ring_size; i++) {
1916                 if (!nv_optimized(np)) {
1917                         np->rx_ring.orig[i].flaglen = 0;
1918                         np->rx_ring.orig[i].buf = 0;
1919                 } else {
1920                         np->rx_ring.ex[i].flaglen = 0;
1921                         np->rx_ring.ex[i].txvlan = 0;
1922                         np->rx_ring.ex[i].bufhigh = 0;
1923                         np->rx_ring.ex[i].buflow = 0;
1924                 }
1925                 np->rx_skb[i].skb = NULL;
1926                 np->rx_skb[i].dma = 0;
1927         }
1928 }
1929
1930 static void nv_init_tx(struct net_device *dev)
1931 {
1932         struct fe_priv *np = netdev_priv(dev);
1933         int i;
1934
1935         np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1936
1937         if (!nv_optimized(np))
1938                 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1939         else
1940                 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1941         np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1942         np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1943         netdev_reset_queue(np->dev);
1944         np->tx_pkts_in_progress = 0;
1945         np->tx_change_owner = NULL;
1946         np->tx_end_flip = NULL;
1947         np->tx_stop = 0;
1948
1949         for (i = 0; i < np->tx_ring_size; i++) {
1950                 if (!nv_optimized(np)) {
1951                         np->tx_ring.orig[i].flaglen = 0;
1952                         np->tx_ring.orig[i].buf = 0;
1953                 } else {
1954                         np->tx_ring.ex[i].flaglen = 0;
1955                         np->tx_ring.ex[i].txvlan = 0;
1956                         np->tx_ring.ex[i].bufhigh = 0;
1957                         np->tx_ring.ex[i].buflow = 0;
1958                 }
1959                 np->tx_skb[i].skb = NULL;
1960                 np->tx_skb[i].dma = 0;
1961                 np->tx_skb[i].dma_len = 0;
1962                 np->tx_skb[i].dma_single = 0;
1963                 np->tx_skb[i].first_tx_desc = NULL;
1964                 np->tx_skb[i].next_tx_ctx = NULL;
1965         }
1966 }
1967
1968 static int nv_init_ring(struct net_device *dev)
1969 {
1970         struct fe_priv *np = netdev_priv(dev);
1971
1972         nv_init_tx(dev);
1973         nv_init_rx(dev);
1974
1975         if (!nv_optimized(np))
1976                 return nv_alloc_rx(dev);
1977         else
1978                 return nv_alloc_rx_optimized(dev);
1979 }
1980
1981 static void nv_unmap_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1982 {
1983         if (tx_skb->dma) {
1984                 if (tx_skb->dma_single)
1985                         dma_unmap_single(&np->pci_dev->dev, tx_skb->dma,
1986                                          tx_skb->dma_len,
1987                                          DMA_TO_DEVICE);
1988                 else
1989                         dma_unmap_page(&np->pci_dev->dev, tx_skb->dma,
1990                                        tx_skb->dma_len,
1991                                        DMA_TO_DEVICE);
1992                 tx_skb->dma = 0;
1993         }
1994 }
1995
1996 static int nv_release_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1997 {
1998         nv_unmap_txskb(np, tx_skb);
1999         if (tx_skb->skb) {
2000                 dev_kfree_skb_any(tx_skb->skb);
2001                 tx_skb->skb = NULL;
2002                 return 1;
2003         }
2004         return 0;
2005 }
2006
2007 static void nv_drain_tx(struct net_device *dev)
2008 {
2009         struct fe_priv *np = netdev_priv(dev);
2010         unsigned int i;
2011
2012         for (i = 0; i < np->tx_ring_size; i++) {
2013                 if (!nv_optimized(np)) {
2014                         np->tx_ring.orig[i].flaglen = 0;
2015                         np->tx_ring.orig[i].buf = 0;
2016                 } else {
2017                         np->tx_ring.ex[i].flaglen = 0;
2018                         np->tx_ring.ex[i].txvlan = 0;
2019                         np->tx_ring.ex[i].bufhigh = 0;
2020                         np->tx_ring.ex[i].buflow = 0;
2021                 }
2022                 if (nv_release_txskb(np, &np->tx_skb[i])) {
2023                         u64_stats_update_begin(&np->swstats_tx_syncp);
2024                         np->stat_tx_dropped++;
2025                         u64_stats_update_end(&np->swstats_tx_syncp);
2026                 }
2027                 np->tx_skb[i].dma = 0;
2028                 np->tx_skb[i].dma_len = 0;
2029                 np->tx_skb[i].dma_single = 0;
2030                 np->tx_skb[i].first_tx_desc = NULL;
2031                 np->tx_skb[i].next_tx_ctx = NULL;
2032         }
2033         np->tx_pkts_in_progress = 0;
2034         np->tx_change_owner = NULL;
2035         np->tx_end_flip = NULL;
2036 }
2037
2038 static void nv_drain_rx(struct net_device *dev)
2039 {
2040         struct fe_priv *np = netdev_priv(dev);
2041         int i;
2042
2043         for (i = 0; i < np->rx_ring_size; i++) {
2044                 if (!nv_optimized(np)) {
2045                         np->rx_ring.orig[i].flaglen = 0;
2046                         np->rx_ring.orig[i].buf = 0;
2047                 } else {
2048                         np->rx_ring.ex[i].flaglen = 0;
2049                         np->rx_ring.ex[i].txvlan = 0;
2050                         np->rx_ring.ex[i].bufhigh = 0;
2051                         np->rx_ring.ex[i].buflow = 0;
2052                 }
2053                 wmb();
2054                 if (np->rx_skb[i].skb) {
2055                         dma_unmap_single(&np->pci_dev->dev, np->rx_skb[i].dma,
2056                                          (skb_end_pointer(np->rx_skb[i].skb) -
2057                                          np->rx_skb[i].skb->data),
2058                                          DMA_FROM_DEVICE);
2059                         dev_kfree_skb(np->rx_skb[i].skb);
2060                         np->rx_skb[i].skb = NULL;
2061                 }
2062         }
2063 }
2064
2065 static void nv_drain_rxtx(struct net_device *dev)
2066 {
2067         nv_drain_tx(dev);
2068         nv_drain_rx(dev);
2069 }
2070
2071 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
2072 {
2073         return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
2074 }
2075
2076 static void nv_legacybackoff_reseed(struct net_device *dev)
2077 {
2078         u8 __iomem *base = get_hwbase(dev);
2079         u32 reg;
2080         u32 low;
2081         int tx_status = 0;
2082
2083         reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
2084         get_random_bytes(&low, sizeof(low));
2085         reg |= low & NVREG_SLOTTIME_MASK;
2086
2087         /* Need to stop tx before change takes effect.
2088          * Caller has already gained np->lock.
2089          */
2090         tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
2091         if (tx_status)
2092                 nv_stop_tx(dev);
2093         nv_stop_rx(dev);
2094         writel(reg, base + NvRegSlotTime);
2095         if (tx_status)
2096                 nv_start_tx(dev);
2097         nv_start_rx(dev);
2098 }
2099
2100 /* Gear Backoff Seeds */
2101 #define BACKOFF_SEEDSET_ROWS    8
2102 #define BACKOFF_SEEDSET_LFSRS   15
2103
2104 /* Known Good seed sets */
2105 static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2106         {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2107         {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
2108         {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2109         {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2110         {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2111         {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2112         {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800,  84},
2113         {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184} };
2114
2115 static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2116         {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2117         {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2118         {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2119         {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2120         {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2121         {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2122         {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2123         {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395} };
2124
2125 static void nv_gear_backoff_reseed(struct net_device *dev)
2126 {
2127         u8 __iomem *base = get_hwbase(dev);
2128         u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
2129         u32 temp, seedset, combinedSeed;
2130         int i;
2131
2132         /* Setup seed for free running LFSR */
2133         /* We are going to read the time stamp counter 3 times
2134            and swizzle bits around to increase randomness */
2135         get_random_bytes(&miniseed1, sizeof(miniseed1));
2136         miniseed1 &= 0x0fff;
2137         if (miniseed1 == 0)
2138                 miniseed1 = 0xabc;
2139
2140         get_random_bytes(&miniseed2, sizeof(miniseed2));
2141         miniseed2 &= 0x0fff;
2142         if (miniseed2 == 0)
2143                 miniseed2 = 0xabc;
2144         miniseed2_reversed =
2145                 ((miniseed2 & 0xF00) >> 8) |
2146                  (miniseed2 & 0x0F0) |
2147                  ((miniseed2 & 0x00F) << 8);
2148
2149         get_random_bytes(&miniseed3, sizeof(miniseed3));
2150         miniseed3 &= 0x0fff;
2151         if (miniseed3 == 0)
2152                 miniseed3 = 0xabc;
2153         miniseed3_reversed =
2154                 ((miniseed3 & 0xF00) >> 8) |
2155                  (miniseed3 & 0x0F0) |
2156                  ((miniseed3 & 0x00F) << 8);
2157
2158         combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
2159                        (miniseed2 ^ miniseed3_reversed);
2160
2161         /* Seeds can not be zero */
2162         if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
2163                 combinedSeed |= 0x08;
2164         if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
2165                 combinedSeed |= 0x8000;
2166
2167         /* No need to disable tx here */
2168         temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
2169         temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
2170         temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
2171         writel(temp, base + NvRegBackOffControl);
2172
2173         /* Setup seeds for all gear LFSRs. */
2174         get_random_bytes(&seedset, sizeof(seedset));
2175         seedset = seedset % BACKOFF_SEEDSET_ROWS;
2176         for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++) {
2177                 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
2178                 temp |= main_seedset[seedset][i-1] & 0x3ff;
2179                 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
2180                 writel(temp, base + NvRegBackOffControl);
2181         }
2182 }
2183
2184 /*
2185  * nv_start_xmit: dev->hard_start_xmit function
2186  * Called with netif_tx_lock held.
2187  */
2188 static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
2189 {
2190         struct fe_priv *np = netdev_priv(dev);
2191         u32 tx_flags = 0;
2192         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2193         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2194         unsigned int i;
2195         u32 offset = 0;
2196         u32 bcnt;
2197         u32 size = skb_headlen(skb);
2198         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2199         u32 empty_slots;
2200         struct ring_desc *put_tx;
2201         struct ring_desc *start_tx;
2202         struct ring_desc *prev_tx;
2203         struct nv_skb_map *prev_tx_ctx;
2204         struct nv_skb_map *tmp_tx_ctx = NULL, *start_tx_ctx = NULL;
2205         unsigned long flags;
2206
2207         /* add fragments to entries count */
2208         for (i = 0; i < fragments; i++) {
2209                 u32 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[i]);
2210
2211                 entries += (frag_size >> NV_TX2_TSO_MAX_SHIFT) +
2212                            ((frag_size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2213         }
2214
2215         spin_lock_irqsave(&np->lock, flags);
2216         empty_slots = nv_get_empty_tx_slots(np);
2217         if (unlikely(empty_slots <= entries)) {
2218                 netif_stop_queue(dev);
2219                 np->tx_stop = 1;
2220                 spin_unlock_irqrestore(&np->lock, flags);
2221                 return NETDEV_TX_BUSY;
2222         }
2223         spin_unlock_irqrestore(&np->lock, flags);
2224
2225         start_tx = put_tx = np->put_tx.orig;
2226
2227         /* setup the header buffer */
2228         do {
2229                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2230                 np->put_tx_ctx->dma = dma_map_single(&np->pci_dev->dev,
2231                                                      skb->data + offset, bcnt,
2232                                                      DMA_TO_DEVICE);
2233                 if (unlikely(dma_mapping_error(&np->pci_dev->dev,
2234                                                np->put_tx_ctx->dma))) {
2235                         /* on DMA mapping error - drop the packet */
2236                         dev_kfree_skb_any(skb);
2237                         u64_stats_update_begin(&np->swstats_tx_syncp);
2238                         np->stat_tx_dropped++;
2239                         u64_stats_update_end(&np->swstats_tx_syncp);
2240                         return NETDEV_TX_OK;
2241                 }
2242                 np->put_tx_ctx->dma_len = bcnt;
2243                 np->put_tx_ctx->dma_single = 1;
2244                 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2245                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2246
2247                 tx_flags = np->tx_flags;
2248                 offset += bcnt;
2249                 size -= bcnt;
2250                 if (unlikely(put_tx++ == np->last_tx.orig))
2251                         put_tx = np->first_tx.orig;
2252                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2253                         np->put_tx_ctx = np->first_tx_ctx;
2254         } while (size);
2255
2256         /* setup the fragments */
2257         for (i = 0; i < fragments; i++) {
2258                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2259                 u32 frag_size = skb_frag_size(frag);
2260                 offset = 0;
2261
2262                 do {
2263                         if (!start_tx_ctx)
2264                                 start_tx_ctx = tmp_tx_ctx = np->put_tx_ctx;
2265
2266                         bcnt = (frag_size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : frag_size;
2267                         np->put_tx_ctx->dma = skb_frag_dma_map(
2268                                                         &np->pci_dev->dev,
2269                                                         frag, offset,
2270                                                         bcnt,
2271                                                         DMA_TO_DEVICE);
2272                         if (unlikely(dma_mapping_error(&np->pci_dev->dev,
2273                                                        np->put_tx_ctx->dma))) {
2274
2275                                 /* Unwind the mapped fragments */
2276                                 do {
2277                                         nv_unmap_txskb(np, start_tx_ctx);
2278                                         if (unlikely(tmp_tx_ctx++ == np->last_tx_ctx))
2279                                                 tmp_tx_ctx = np->first_tx_ctx;
2280                                 } while (tmp_tx_ctx != np->put_tx_ctx);
2281                                 dev_kfree_skb_any(skb);
2282                                 np->put_tx_ctx = start_tx_ctx;
2283                                 u64_stats_update_begin(&np->swstats_tx_syncp);
2284                                 np->stat_tx_dropped++;
2285                                 u64_stats_update_end(&np->swstats_tx_syncp);
2286                                 return NETDEV_TX_OK;
2287                         }
2288
2289                         np->put_tx_ctx->dma_len = bcnt;
2290                         np->put_tx_ctx->dma_single = 0;
2291                         put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2292                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2293
2294                         offset += bcnt;
2295                         frag_size -= bcnt;
2296                         if (unlikely(put_tx++ == np->last_tx.orig))
2297                                 put_tx = np->first_tx.orig;
2298                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2299                                 np->put_tx_ctx = np->first_tx_ctx;
2300                 } while (frag_size);
2301         }
2302
2303         if (unlikely(put_tx == np->first_tx.orig))
2304                 prev_tx = np->last_tx.orig;
2305         else
2306                 prev_tx = put_tx - 1;
2307
2308         if (unlikely(np->put_tx_ctx == np->first_tx_ctx))
2309                 prev_tx_ctx = np->last_tx_ctx;
2310         else
2311                 prev_tx_ctx = np->put_tx_ctx - 1;
2312
2313         /* set last fragment flag  */
2314         prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
2315
2316         /* save skb in this slot's context area */
2317         prev_tx_ctx->skb = skb;
2318
2319         if (skb_is_gso(skb))
2320                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2321         else
2322                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2323                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2324
2325         spin_lock_irqsave(&np->lock, flags);
2326
2327         /* set tx flags */
2328         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2329
2330         netdev_sent_queue(np->dev, skb->len);
2331
2332         skb_tx_timestamp(skb);
2333
2334         np->put_tx.orig = put_tx;
2335
2336         spin_unlock_irqrestore(&np->lock, flags);
2337
2338         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2339         return NETDEV_TX_OK;
2340 }
2341
2342 static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb,
2343                                            struct net_device *dev)
2344 {
2345         struct fe_priv *np = netdev_priv(dev);
2346         u32 tx_flags = 0;
2347         u32 tx_flags_extra;
2348         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2349         unsigned int i;
2350         u32 offset = 0;
2351         u32 bcnt;
2352         u32 size = skb_headlen(skb);
2353         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2354         u32 empty_slots;
2355         struct ring_desc_ex *put_tx;
2356         struct ring_desc_ex *start_tx;
2357         struct ring_desc_ex *prev_tx;
2358         struct nv_skb_map *prev_tx_ctx;
2359         struct nv_skb_map *start_tx_ctx = NULL;
2360         struct nv_skb_map *tmp_tx_ctx = NULL;
2361         unsigned long flags;
2362
2363         /* add fragments to entries count */
2364         for (i = 0; i < fragments; i++) {
2365                 u32 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[i]);
2366
2367                 entries += (frag_size >> NV_TX2_TSO_MAX_SHIFT) +
2368                            ((frag_size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2369         }
2370
2371         spin_lock_irqsave(&np->lock, flags);
2372         empty_slots = nv_get_empty_tx_slots(np);
2373         if (unlikely(empty_slots <= entries)) {
2374                 netif_stop_queue(dev);
2375                 np->tx_stop = 1;
2376                 spin_unlock_irqrestore(&np->lock, flags);
2377                 return NETDEV_TX_BUSY;
2378         }
2379         spin_unlock_irqrestore(&np->lock, flags);
2380
2381         start_tx = put_tx = np->put_tx.ex;
2382         start_tx_ctx = np->put_tx_ctx;
2383
2384         /* setup the header buffer */
2385         do {
2386                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2387                 np->put_tx_ctx->dma = dma_map_single(&np->pci_dev->dev,
2388                                                      skb->data + offset, bcnt,
2389                                                      DMA_TO_DEVICE);
2390                 if (unlikely(dma_mapping_error(&np->pci_dev->dev,
2391                                                np->put_tx_ctx->dma))) {
2392                         /* on DMA mapping error - drop the packet */
2393                         dev_kfree_skb_any(skb);
2394                         u64_stats_update_begin(&np->swstats_tx_syncp);
2395                         np->stat_tx_dropped++;
2396                         u64_stats_update_end(&np->swstats_tx_syncp);
2397                         return NETDEV_TX_OK;
2398                 }
2399                 np->put_tx_ctx->dma_len = bcnt;
2400                 np->put_tx_ctx->dma_single = 1;
2401                 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2402                 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2403                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2404
2405                 tx_flags = NV_TX2_VALID;
2406                 offset += bcnt;
2407                 size -= bcnt;
2408                 if (unlikely(put_tx++ == np->last_tx.ex))
2409                         put_tx = np->first_tx.ex;
2410                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2411                         np->put_tx_ctx = np->first_tx_ctx;
2412         } while (size);
2413
2414         /* setup the fragments */
2415         for (i = 0; i < fragments; i++) {
2416                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2417                 u32 frag_size = skb_frag_size(frag);
2418                 offset = 0;
2419
2420                 do {
2421                         bcnt = (frag_size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : frag_size;
2422                         if (!start_tx_ctx)
2423                                 start_tx_ctx = tmp_tx_ctx = np->put_tx_ctx;
2424                         np->put_tx_ctx->dma = skb_frag_dma_map(
2425                                                         &np->pci_dev->dev,
2426                                                         frag, offset,
2427                                                         bcnt,
2428                                                         DMA_TO_DEVICE);
2429
2430                         if (unlikely(dma_mapping_error(&np->pci_dev->dev,
2431                                                        np->put_tx_ctx->dma))) {
2432
2433                                 /* Unwind the mapped fragments */
2434                                 do {
2435                                         nv_unmap_txskb(np, start_tx_ctx);
2436                                         if (unlikely(tmp_tx_ctx++ == np->last_tx_ctx))
2437                                                 tmp_tx_ctx = np->first_tx_ctx;
2438                                 } while (tmp_tx_ctx != np->put_tx_ctx);
2439                                 dev_kfree_skb_any(skb);
2440                                 np->put_tx_ctx = start_tx_ctx;
2441                                 u64_stats_update_begin(&np->swstats_tx_syncp);
2442                                 np->stat_tx_dropped++;
2443                                 u64_stats_update_end(&np->swstats_tx_syncp);
2444                                 return NETDEV_TX_OK;
2445                         }
2446                         np->put_tx_ctx->dma_len = bcnt;
2447                         np->put_tx_ctx->dma_single = 0;
2448                         put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2449                         put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2450                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2451
2452                         offset += bcnt;
2453                         frag_size -= bcnt;
2454                         if (unlikely(put_tx++ == np->last_tx.ex))
2455                                 put_tx = np->first_tx.ex;
2456                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2457                                 np->put_tx_ctx = np->first_tx_ctx;
2458                 } while (frag_size);
2459         }
2460
2461         if (unlikely(put_tx == np->first_tx.ex))
2462                 prev_tx = np->last_tx.ex;
2463         else
2464                 prev_tx = put_tx - 1;
2465
2466         if (unlikely(np->put_tx_ctx == np->first_tx_ctx))
2467                 prev_tx_ctx = np->last_tx_ctx;
2468         else
2469                 prev_tx_ctx = np->put_tx_ctx - 1;
2470
2471         /* set last fragment flag  */
2472         prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
2473
2474         /* save skb in this slot's context area */
2475         prev_tx_ctx->skb = skb;
2476
2477         if (skb_is_gso(skb))
2478                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2479         else
2480                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2481                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2482
2483         /* vlan tag */
2484         if (skb_vlan_tag_present(skb))
2485                 start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT |
2486                                         skb_vlan_tag_get(skb));
2487         else
2488                 start_tx->txvlan = 0;
2489
2490         spin_lock_irqsave(&np->lock, flags);
2491
2492         if (np->tx_limit) {
2493                 /* Limit the number of outstanding tx. Setup all fragments, but
2494                  * do not set the VALID bit on the first descriptor. Save a pointer
2495                  * to that descriptor and also for next skb_map element.
2496                  */
2497
2498                 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2499                         if (!np->tx_change_owner)
2500                                 np->tx_change_owner = start_tx_ctx;
2501
2502                         /* remove VALID bit */
2503                         tx_flags &= ~NV_TX2_VALID;
2504                         start_tx_ctx->first_tx_desc = start_tx;
2505                         start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2506                         np->tx_end_flip = np->put_tx_ctx;
2507                 } else {
2508                         np->tx_pkts_in_progress++;
2509                 }
2510         }
2511
2512         /* set tx flags */
2513         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2514
2515         netdev_sent_queue(np->dev, skb->len);
2516
2517         skb_tx_timestamp(skb);
2518
2519         np->put_tx.ex = put_tx;
2520
2521         spin_unlock_irqrestore(&np->lock, flags);
2522
2523         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2524         return NETDEV_TX_OK;
2525 }
2526
2527 static inline void nv_tx_flip_ownership(struct net_device *dev)
2528 {
2529         struct fe_priv *np = netdev_priv(dev);
2530
2531         np->tx_pkts_in_progress--;
2532         if (np->tx_change_owner) {
2533                 np->tx_change_owner->first_tx_desc->flaglen |=
2534                         cpu_to_le32(NV_TX2_VALID);
2535                 np->tx_pkts_in_progress++;
2536
2537                 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2538                 if (np->tx_change_owner == np->tx_end_flip)
2539                         np->tx_change_owner = NULL;
2540
2541                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2542         }
2543 }
2544
2545 /*
2546  * nv_tx_done: check for completed packets, release the skbs.
2547  *
2548  * Caller must own np->lock.
2549  */
2550 static int nv_tx_done(struct net_device *dev, int limit)
2551 {
2552         struct fe_priv *np = netdev_priv(dev);
2553         u32 flags;
2554         int tx_work = 0;
2555         struct ring_desc *orig_get_tx = np->get_tx.orig;
2556         unsigned int bytes_compl = 0;
2557
2558         while ((np->get_tx.orig != np->put_tx.orig) &&
2559                !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) &&
2560                (tx_work < limit)) {
2561
2562                 nv_unmap_txskb(np, np->get_tx_ctx);
2563
2564                 if (np->desc_ver == DESC_VER_1) {
2565                         if (flags & NV_TX_LASTPACKET) {
2566                                 if (flags & NV_TX_ERROR) {
2567                                         if ((flags & NV_TX_RETRYERROR)
2568                                             && !(flags & NV_TX_RETRYCOUNT_MASK))
2569                                                 nv_legacybackoff_reseed(dev);
2570                                 } else {
2571                                         u64_stats_update_begin(&np->swstats_tx_syncp);
2572                                         np->stat_tx_packets++;
2573                                         np->stat_tx_bytes += np->get_tx_ctx->skb->len;
2574                                         u64_stats_update_end(&np->swstats_tx_syncp);
2575                                 }
2576                                 bytes_compl += np->get_tx_ctx->skb->len;
2577                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2578                                 np->get_tx_ctx->skb = NULL;
2579                                 tx_work++;
2580                         }
2581                 } else {
2582                         if (flags & NV_TX2_LASTPACKET) {
2583                                 if (flags & NV_TX2_ERROR) {
2584                                         if ((flags & NV_TX2_RETRYERROR)
2585                                             && !(flags & NV_TX2_RETRYCOUNT_MASK))
2586                                                 nv_legacybackoff_reseed(dev);
2587                                 } else {
2588                                         u64_stats_update_begin(&np->swstats_tx_syncp);
2589                                         np->stat_tx_packets++;
2590                                         np->stat_tx_bytes += np->get_tx_ctx->skb->len;
2591                                         u64_stats_update_end(&np->swstats_tx_syncp);
2592                                 }
2593                                 bytes_compl += np->get_tx_ctx->skb->len;
2594                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2595                                 np->get_tx_ctx->skb = NULL;
2596                                 tx_work++;
2597                         }
2598                 }
2599                 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2600                         np->get_tx.orig = np->first_tx.orig;
2601                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2602                         np->get_tx_ctx = np->first_tx_ctx;
2603         }
2604
2605         netdev_completed_queue(np->dev, tx_work, bytes_compl);
2606
2607         if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2608                 np->tx_stop = 0;
2609                 netif_wake_queue(dev);
2610         }
2611         return tx_work;
2612 }
2613
2614 static int nv_tx_done_optimized(struct net_device *dev, int limit)
2615 {
2616         struct fe_priv *np = netdev_priv(dev);
2617         u32 flags;
2618         int tx_work = 0;
2619         struct ring_desc_ex *orig_get_tx = np->get_tx.ex;
2620         unsigned long bytes_cleaned = 0;
2621
2622         while ((np->get_tx.ex != np->put_tx.ex) &&
2623                !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX2_VALID) &&
2624                (tx_work < limit)) {
2625
2626                 nv_unmap_txskb(np, np->get_tx_ctx);
2627
2628                 if (flags & NV_TX2_LASTPACKET) {
2629                         if (flags & NV_TX2_ERROR) {
2630                                 if ((flags & NV_TX2_RETRYERROR)
2631                                     && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2632                                         if (np->driver_data & DEV_HAS_GEAR_MODE)
2633                                                 nv_gear_backoff_reseed(dev);
2634                                         else
2635                                                 nv_legacybackoff_reseed(dev);
2636                                 }
2637                         } else {
2638                                 u64_stats_update_begin(&np->swstats_tx_syncp);
2639                                 np->stat_tx_packets++;
2640                                 np->stat_tx_bytes += np->get_tx_ctx->skb->len;
2641                                 u64_stats_update_end(&np->swstats_tx_syncp);
2642                         }
2643
2644                         bytes_cleaned += np->get_tx_ctx->skb->len;
2645                         dev_kfree_skb_any(np->get_tx_ctx->skb);
2646                         np->get_tx_ctx->skb = NULL;
2647                         tx_work++;
2648
2649                         if (np->tx_limit)
2650                                 nv_tx_flip_ownership(dev);
2651                 }
2652
2653                 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2654                         np->get_tx.ex = np->first_tx.ex;
2655                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2656                         np->get_tx_ctx = np->first_tx_ctx;
2657         }
2658
2659         netdev_completed_queue(np->dev, tx_work, bytes_cleaned);
2660
2661         if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2662                 np->tx_stop = 0;
2663                 netif_wake_queue(dev);
2664         }
2665         return tx_work;
2666 }
2667
2668 /*
2669  * nv_tx_timeout: dev->tx_timeout function
2670  * Called with netif_tx_lock held.
2671  */
2672 static void nv_tx_timeout(struct net_device *dev)
2673 {
2674         struct fe_priv *np = netdev_priv(dev);
2675         u8 __iomem *base = get_hwbase(dev);
2676         u32 status;
2677         union ring_type put_tx;
2678         int saved_tx_limit;
2679
2680         if (np->msi_flags & NV_MSI_X_ENABLED)
2681                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2682         else
2683                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2684
2685         netdev_warn(dev, "Got tx_timeout. irq status: %08x\n", status);
2686
2687         if (unlikely(debug_tx_timeout)) {
2688                 int i;
2689
2690                 netdev_info(dev, "Ring at %lx\n", (unsigned long)np->ring_addr);
2691                 netdev_info(dev, "Dumping tx registers\n");
2692                 for (i = 0; i <= np->register_size; i += 32) {
2693                         netdev_info(dev,
2694                                     "%3x: %08x %08x %08x %08x "
2695                                     "%08x %08x %08x %08x\n",
2696                                     i,
2697                                     readl(base + i + 0), readl(base + i + 4),
2698                                     readl(base + i + 8), readl(base + i + 12),
2699                                     readl(base + i + 16), readl(base + i + 20),
2700                                     readl(base + i + 24), readl(base + i + 28));
2701                 }
2702                 netdev_info(dev, "Dumping tx ring\n");
2703                 for (i = 0; i < np->tx_ring_size; i += 4) {
2704                         if (!nv_optimized(np)) {
2705                                 netdev_info(dev,
2706                                             "%03x: %08x %08x // %08x %08x "
2707                                             "// %08x %08x // %08x %08x\n",
2708                                             i,
2709                                             le32_to_cpu(np->tx_ring.orig[i].buf),
2710                                             le32_to_cpu(np->tx_ring.orig[i].flaglen),
2711                                             le32_to_cpu(np->tx_ring.orig[i+1].buf),
2712                                             le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2713                                             le32_to_cpu(np->tx_ring.orig[i+2].buf),
2714                                             le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2715                                             le32_to_cpu(np->tx_ring.orig[i+3].buf),
2716                                             le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2717                         } else {
2718                                 netdev_info(dev,
2719                                             "%03x: %08x %08x %08x "
2720                                             "// %08x %08x %08x "
2721                                             "// %08x %08x %08x "
2722                                             "// %08x %08x %08x\n",
2723                                             i,
2724                                             le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2725                                             le32_to_cpu(np->tx_ring.ex[i].buflow),
2726                                             le32_to_cpu(np->tx_ring.ex[i].flaglen),
2727                                             le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2728                                             le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2729                                             le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2730                                             le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2731                                             le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2732                                             le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2733                                             le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2734                                             le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2735                                             le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2736                         }
2737                 }
2738         }
2739
2740         spin_lock_irq(&np->lock);
2741
2742         /* 1) stop tx engine */
2743         nv_stop_tx(dev);
2744
2745         /* 2) complete any outstanding tx and do not give HW any limited tx pkts */
2746         saved_tx_limit = np->tx_limit;
2747         np->tx_limit = 0; /* prevent giving HW any limited pkts */
2748         np->tx_stop = 0;  /* prevent waking tx queue */
2749         if (!nv_optimized(np))
2750                 nv_tx_done(dev, np->tx_ring_size);
2751         else
2752                 nv_tx_done_optimized(dev, np->tx_ring_size);
2753
2754         /* save current HW position */
2755         if (np->tx_change_owner)
2756                 put_tx.ex = np->tx_change_owner->first_tx_desc;
2757         else
2758                 put_tx = np->put_tx;
2759
2760         /* 3) clear all tx state */
2761         nv_drain_tx(dev);
2762         nv_init_tx(dev);
2763
2764         /* 4) restore state to current HW position */
2765         np->get_tx = np->put_tx = put_tx;
2766         np->tx_limit = saved_tx_limit;
2767
2768         /* 5) restart tx engine */
2769         nv_start_tx(dev);
2770         netif_wake_queue(dev);
2771         spin_unlock_irq(&np->lock);
2772 }
2773
2774 /*
2775  * Called when the nic notices a mismatch between the actual data len on the
2776  * wire and the len indicated in the 802 header
2777  */
2778 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2779 {
2780         int hdrlen;     /* length of the 802 header */
2781         int protolen;   /* length as stored in the proto field */
2782
2783         /* 1) calculate len according to header */
2784         if (((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2785                 protolen = ntohs(((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto);
2786                 hdrlen = VLAN_HLEN;
2787         } else {
2788                 protolen = ntohs(((struct ethhdr *)packet)->h_proto);
2789                 hdrlen = ETH_HLEN;
2790         }
2791         if (protolen > ETH_DATA_LEN)
2792                 return datalen; /* Value in proto field not a len, no checks possible */
2793
2794         protolen += hdrlen;
2795         /* consistency checks: */
2796         if (datalen > ETH_ZLEN) {
2797                 if (datalen >= protolen) {
2798                         /* more data on wire than in 802 header, trim of
2799                          * additional data.
2800                          */
2801                         return protolen;
2802                 } else {
2803                         /* less data on wire than mentioned in header.
2804                          * Discard the packet.
2805                          */
2806                         return -1;
2807                 }
2808         } else {
2809                 /* short packet. Accept only if 802 values are also short */
2810                 if (protolen > ETH_ZLEN) {
2811                         return -1;
2812                 }
2813                 return datalen;
2814         }
2815 }
2816
2817 static int nv_rx_process(struct net_device *dev, int limit)
2818 {
2819         struct fe_priv *np = netdev_priv(dev);
2820         u32 flags;
2821         int rx_work = 0;
2822         struct sk_buff *skb;
2823         int len;
2824
2825         while ((np->get_rx.orig != np->put_rx.orig) &&
2826               !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2827                 (rx_work < limit)) {
2828
2829                 /*
2830                  * the packet is for us - immediately tear down the pci mapping.
2831                  * TODO: check if a prefetch of the first cacheline improves
2832                  * the performance.
2833                  */
2834                 dma_unmap_single(&np->pci_dev->dev, np->get_rx_ctx->dma,
2835                                  np->get_rx_ctx->dma_len,
2836                                  DMA_FROM_DEVICE);
2837                 skb = np->get_rx_ctx->skb;
2838                 np->get_rx_ctx->skb = NULL;
2839
2840                 /* look at what we actually got: */
2841                 if (np->desc_ver == DESC_VER_1) {
2842                         if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2843                                 len = flags & LEN_MASK_V1;
2844                                 if (unlikely(flags & NV_RX_ERROR)) {
2845                                         if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
2846                                                 len = nv_getlen(dev, skb->data, len);
2847                                                 if (len < 0) {
2848                                                         dev_kfree_skb(skb);
2849                                                         goto next_pkt;
2850                                                 }
2851                                         }
2852                                         /* framing errors are soft errors */
2853                                         else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
2854                                                 if (flags & NV_RX_SUBTRACT1)
2855                                                         len--;
2856                                         }
2857                                         /* the rest are hard errors */
2858                                         else {
2859                                                 if (flags & NV_RX_MISSEDFRAME) {
2860                                                         u64_stats_update_begin(&np->swstats_rx_syncp);
2861                                                         np->stat_rx_missed_errors++;
2862                                                         u64_stats_update_end(&np->swstats_rx_syncp);
2863                                                 }
2864                                                 dev_kfree_skb(skb);
2865                                                 goto next_pkt;
2866                                         }
2867                                 }
2868                         } else {
2869                                 dev_kfree_skb(skb);
2870                                 goto next_pkt;
2871                         }
2872                 } else {
2873                         if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2874                                 len = flags & LEN_MASK_V2;
2875                                 if (unlikely(flags & NV_RX2_ERROR)) {
2876                                         if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2877                                                 len = nv_getlen(dev, skb->data, len);
2878                                                 if (len < 0) {
2879                                                         dev_kfree_skb(skb);
2880                                                         goto next_pkt;
2881                                                 }
2882                                         }
2883                                         /* framing errors are soft errors */
2884                                         else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2885                                                 if (flags & NV_RX2_SUBTRACT1)
2886                                                         len--;
2887                                         }
2888                                         /* the rest are hard errors */
2889                                         else {
2890                                                 dev_kfree_skb(skb);
2891                                                 goto next_pkt;
2892                                         }
2893                                 }
2894                                 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2895                                     ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2896                                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2897                         } else {
2898                                 dev_kfree_skb(skb);
2899                                 goto next_pkt;
2900                         }
2901                 }
2902                 /* got a valid packet - forward it to the network core */
2903                 skb_put(skb, len);
2904                 skb->protocol = eth_type_trans(skb, dev);
2905                 napi_gro_receive(&np->napi, skb);
2906                 u64_stats_update_begin(&np->swstats_rx_syncp);
2907                 np->stat_rx_packets++;
2908                 np->stat_rx_bytes += len;
2909                 u64_stats_update_end(&np->swstats_rx_syncp);
2910 next_pkt:
2911                 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2912                         np->get_rx.orig = np->first_rx.orig;
2913                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2914                         np->get_rx_ctx = np->first_rx_ctx;
2915
2916                 rx_work++;
2917         }
2918
2919         return rx_work;
2920 }
2921
2922 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2923 {
2924         struct fe_priv *np = netdev_priv(dev);
2925         u32 flags;
2926         u32 vlanflags = 0;
2927         int rx_work = 0;
2928         struct sk_buff *skb;
2929         int len;
2930
2931         while ((np->get_rx.ex != np->put_rx.ex) &&
2932               !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2933               (rx_work < limit)) {
2934
2935                 /*
2936                  * the packet is for us - immediately tear down the pci mapping.
2937                  * TODO: check if a prefetch of the first cacheline improves
2938                  * the performance.
2939                  */
2940                 dma_unmap_single(&np->pci_dev->dev, np->get_rx_ctx->dma,
2941                                  np->get_rx_ctx->dma_len,
2942                                  DMA_FROM_DEVICE);
2943                 skb = np->get_rx_ctx->skb;
2944                 np->get_rx_ctx->skb = NULL;
2945
2946                 /* look at what we actually got: */
2947                 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2948                         len = flags & LEN_MASK_V2;
2949                         if (unlikely(flags & NV_RX2_ERROR)) {
2950                                 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2951                                         len = nv_getlen(dev, skb->data, len);
2952                                         if (len < 0) {
2953                                                 dev_kfree_skb(skb);
2954                                                 goto next_pkt;
2955                                         }
2956                                 }
2957                                 /* framing errors are soft errors */
2958                                 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2959                                         if (flags & NV_RX2_SUBTRACT1)
2960                                                 len--;
2961                                 }
2962                                 /* the rest are hard errors */
2963                                 else {
2964                                         dev_kfree_skb(skb);
2965                                         goto next_pkt;
2966                                 }
2967                         }
2968
2969                         if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2970                             ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2971                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2972
2973                         /* got a valid packet - forward it to the network core */
2974                         skb_put(skb, len);
2975                         skb->protocol = eth_type_trans(skb, dev);
2976                         prefetch(skb->data);
2977
2978                         vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2979
2980                         /*
2981                          * There's need to check for NETIF_F_HW_VLAN_CTAG_RX
2982                          * here. Even if vlan rx accel is disabled,
2983                          * NV_RX3_VLAN_TAG_PRESENT is pseudo randomly set.
2984                          */
2985                         if (dev->features & NETIF_F_HW_VLAN_CTAG_RX &&
2986                             vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2987                                 u16 vid = vlanflags & NV_RX3_VLAN_TAG_MASK;
2988
2989                                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
2990                         }
2991                         napi_gro_receive(&np->napi, skb);
2992                         u64_stats_update_begin(&np->swstats_rx_syncp);
2993                         np->stat_rx_packets++;
2994                         np->stat_rx_bytes += len;
2995                         u64_stats_update_end(&np->swstats_rx_syncp);
2996                 } else {
2997                         dev_kfree_skb(skb);
2998                 }
2999 next_pkt:
3000                 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
3001                         np->get_rx.ex = np->first_rx.ex;
3002                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
3003                         np->get_rx_ctx = np->first_rx_ctx;
3004
3005                 rx_work++;
3006         }
3007
3008         return rx_work;
3009 }
3010
3011 static void set_bufsize(struct net_device *dev)
3012 {
3013         struct fe_priv *np = netdev_priv(dev);
3014
3015         if (dev->mtu <= ETH_DATA_LEN)
3016                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
3017         else
3018                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
3019 }
3020
3021 /*
3022  * nv_change_mtu: dev->change_mtu function
3023  * Called with dev_base_lock held for read.
3024  */
3025 static int nv_change_mtu(struct net_device *dev, int new_mtu)
3026 {
3027         struct fe_priv *np = netdev_priv(dev);
3028         int old_mtu;
3029
3030         old_mtu = dev->mtu;
3031         dev->mtu = new_mtu;
3032
3033         /* return early if the buffer sizes will not change */
3034         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
3035                 return 0;
3036
3037         /* synchronized against open : rtnl_lock() held by caller */
3038         if (netif_running(dev)) {
3039                 u8 __iomem *base = get_hwbase(dev);
3040                 /*
3041                  * It seems that the nic preloads valid ring entries into an
3042                  * internal buffer. The procedure for flushing everything is
3043                  * guessed, there is probably a simpler approach.
3044                  * Changing the MTU is a rare event, it shouldn't matter.
3045                  */
3046                 nv_disable_irq(dev);
3047                 nv_napi_disable(dev);
3048                 netif_tx_lock_bh(dev);
3049                 netif_addr_lock(dev);
3050                 spin_lock(&np->lock);
3051                 /* stop engines */
3052                 nv_stop_rxtx(dev);
3053                 nv_txrx_reset(dev);
3054                 /* drain rx queue */
3055                 nv_drain_rxtx(dev);
3056                 /* reinit driver view of the rx queue */
3057                 set_bufsize(dev);
3058                 if (nv_init_ring(dev)) {
3059                         if (!np->in_shutdown)
3060                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3061                 }
3062                 /* reinit nic view of the rx queue */
3063                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3064                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3065                 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3066                         base + NvRegRingSizes);
3067                 pci_push(base);
3068                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3069                 pci_push(base);
3070
3071                 /* restart rx engine */
3072                 nv_start_rxtx(dev);
3073                 spin_unlock(&np->lock);
3074                 netif_addr_unlock(dev);
3075                 netif_tx_unlock_bh(dev);
3076                 nv_napi_enable(dev);
3077                 nv_enable_irq(dev);
3078         }
3079         return 0;
3080 }
3081
3082 static void nv_copy_mac_to_hw(struct net_device *dev)
3083 {
3084         u8 __iomem *base = get_hwbase(dev);
3085         u32 mac[2];
3086
3087         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
3088                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
3089         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
3090
3091         writel(mac[0], base + NvRegMacAddrA);
3092         writel(mac[1], base + NvRegMacAddrB);
3093 }
3094
3095 /*
3096  * nv_set_mac_address: dev->set_mac_address function
3097  * Called with rtnl_lock() held.
3098  */
3099 static int nv_set_mac_address(struct net_device *dev, void *addr)
3100 {
3101         struct fe_priv *np = netdev_priv(dev);
3102         struct sockaddr *macaddr = (struct sockaddr *)addr;
3103
3104         if (!is_valid_ether_addr(macaddr->sa_data))
3105                 return -EADDRNOTAVAIL;
3106
3107         /* synchronized against open : rtnl_lock() held by caller */
3108         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
3109
3110         if (netif_running(dev)) {
3111                 netif_tx_lock_bh(dev);
3112                 netif_addr_lock(dev);
3113                 spin_lock_irq(&np->lock);
3114
3115                 /* stop rx engine */
3116                 nv_stop_rx(dev);
3117
3118                 /* set mac address */
3119                 nv_copy_mac_to_hw(dev);
3120
3121                 /* restart rx engine */
3122                 nv_start_rx(dev);
3123                 spin_unlock_irq(&np->lock);
3124                 netif_addr_unlock(dev);
3125                 netif_tx_unlock_bh(dev);
3126         } else {
3127                 nv_copy_mac_to_hw(dev);
3128         }
3129         return 0;
3130 }
3131
3132 /*
3133  * nv_set_multicast: dev->set_multicast function
3134  * Called with netif_tx_lock held.
3135  */
3136 static void nv_set_multicast(struct net_device *dev)
3137 {
3138         struct fe_priv *np = netdev_priv(dev);
3139         u8 __iomem *base = get_hwbase(dev);
3140         u32 addr[2];
3141         u32 mask[2];
3142         u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
3143
3144         memset(addr, 0, sizeof(addr));
3145         memset(mask, 0, sizeof(mask));
3146
3147         if (dev->flags & IFF_PROMISC) {
3148                 pff |= NVREG_PFF_PROMISC;
3149         } else {
3150                 pff |= NVREG_PFF_MYADDR;
3151
3152                 if (dev->flags & IFF_ALLMULTI || !netdev_mc_empty(dev)) {
3153                         u32 alwaysOff[2];
3154                         u32 alwaysOn[2];
3155
3156                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
3157                         if (dev->flags & IFF_ALLMULTI) {
3158                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
3159                         } else {
3160                                 struct netdev_hw_addr *ha;
3161
3162                                 netdev_for_each_mc_addr(ha, dev) {
3163                                         unsigned char *hw_addr = ha->addr;
3164                                         u32 a, b;
3165
3166                                         a = le32_to_cpu(*(__le32 *) hw_addr);
3167                                         b = le16_to_cpu(*(__le16 *) (&hw_addr[4]));
3168                                         alwaysOn[0] &= a;
3169                                         alwaysOff[0] &= ~a;
3170                                         alwaysOn[1] &= b;
3171                                         alwaysOff[1] &= ~b;
3172                                 }
3173                         }
3174                         addr[0] = alwaysOn[0];
3175                         addr[1] = alwaysOn[1];
3176                         mask[0] = alwaysOn[0] | alwaysOff[0];
3177                         mask[1] = alwaysOn[1] | alwaysOff[1];
3178                 } else {
3179                         mask[0] = NVREG_MCASTMASKA_NONE;
3180                         mask[1] = NVREG_MCASTMASKB_NONE;
3181                 }
3182         }
3183         addr[0] |= NVREG_MCASTADDRA_FORCE;
3184         pff |= NVREG_PFF_ALWAYS;
3185         spin_lock_irq(&np->lock);
3186         nv_stop_rx(dev);
3187         writel(addr[0], base + NvRegMulticastAddrA);
3188         writel(addr[1], base + NvRegMulticastAddrB);
3189         writel(mask[0], base + NvRegMulticastMaskA);
3190         writel(mask[1], base + NvRegMulticastMaskB);
3191         writel(pff, base + NvRegPacketFilterFlags);
3192         nv_start_rx(dev);
3193         spin_unlock_irq(&np->lock);
3194 }
3195
3196 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
3197 {
3198         struct fe_priv *np = netdev_priv(dev);
3199         u8 __iomem *base = get_hwbase(dev);
3200
3201         np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
3202
3203         if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
3204                 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
3205                 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
3206                         writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
3207                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3208                 } else {
3209                         writel(pff, base + NvRegPacketFilterFlags);
3210                 }
3211         }
3212         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
3213                 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
3214                 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
3215                         u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
3216                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
3217                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
3218                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
3219                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
3220                                 /* limit the number of tx pause frames to a default of 8 */
3221                                 writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
3222                         }
3223                         writel(pause_enable,  base + NvRegTxPauseFrame);
3224                         writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3225                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3226                 } else {
3227                         writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
3228                         writel(regmisc, base + NvRegMisc1);
3229                 }
3230         }
3231 }
3232
3233 static void nv_force_linkspeed(struct net_device *dev, int speed, int duplex)
3234 {
3235         struct fe_priv *np = netdev_priv(dev);
3236         u8 __iomem *base = get_hwbase(dev);
3237         u32 phyreg, txreg;
3238         int mii_status;
3239
3240         np->linkspeed = NVREG_LINKSPEED_FORCE|speed;
3241         np->duplex = duplex;
3242
3243         /* see if gigabit phy */
3244         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3245         if (mii_status & PHY_GIGABIT) {
3246                 np->gigabit = PHY_GIGABIT;
3247                 phyreg = readl(base + NvRegSlotTime);
3248                 phyreg &= ~(0x3FF00);
3249                 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
3250                         phyreg |= NVREG_SLOTTIME_10_100_FULL;
3251                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
3252                         phyreg |= NVREG_SLOTTIME_10_100_FULL;
3253                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3254                         phyreg |= NVREG_SLOTTIME_1000_FULL;
3255                 writel(phyreg, base + NvRegSlotTime);
3256         }
3257
3258         phyreg = readl(base + NvRegPhyInterface);
3259         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3260         if (np->duplex == 0)
3261                 phyreg |= PHY_HALF;
3262         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3263                 phyreg |= PHY_100;
3264         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) ==
3265                                                         NVREG_LINKSPEED_1000)
3266                 phyreg |= PHY_1000;
3267         writel(phyreg, base + NvRegPhyInterface);
3268
3269         if (phyreg & PHY_RGMII) {
3270                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) ==
3271                                                         NVREG_LINKSPEED_1000)
3272                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3273                 else
3274                         txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3275         } else {
3276                 txreg = NVREG_TX_DEFERRAL_DEFAULT;
3277         }
3278         writel(txreg, base + NvRegTxDeferral);
3279
3280         if (np->desc_ver == DESC_VER_1) {
3281                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3282         } else {
3283                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) ==
3284                                          NVREG_LINKSPEED_1000)
3285                         txreg = NVREG_TX_WM_DESC2_3_1000;
3286                 else
3287                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3288         }
3289         writel(txreg, base + NvRegTxWatermark);
3290
3291         writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
3292                         base + NvRegMisc1);
3293         pci_push(base);
3294         writel(np->linkspeed, base + NvRegLinkSpeed);
3295         pci_push(base);
3296 }
3297
3298 /**
3299  * nv_update_linkspeed - Setup the MAC according to the link partner
3300  * @dev: Network device to be configured
3301  *
3302  * The function queries the PHY and checks if there is a link partner.
3303  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3304  * set to 10 MBit HD.
3305  *
3306  * The function returns 0 if there is no link partner and 1 if there is
3307  * a good link partner.
3308  */
3309 static int nv_update_linkspeed(struct net_device *dev)
3310 {
3311         struct fe_priv *np = netdev_priv(dev);
3312         u8 __iomem *base = get_hwbase(dev);
3313         int adv = 0;
3314         int lpa = 0;
3315         int adv_lpa, adv_pause, lpa_pause;
3316         int newls = np->linkspeed;
3317         int newdup = np->duplex;
3318         int mii_status;
3319         u32 bmcr;
3320         int retval = 0;
3321         u32 control_1000, status_1000, phyreg, pause_flags, txreg;
3322         u32 txrxFlags = 0;
3323         u32 phy_exp;
3324
3325         /* If device loopback is enabled, set carrier on and enable max link
3326          * speed.
3327          */
3328         bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3329         if (bmcr & BMCR_LOOPBACK) {
3330                 if (netif_running(dev)) {
3331                         nv_force_linkspeed(dev, NVREG_LINKSPEED_1000, 1);
3332                         if (!netif_carrier_ok(dev))
3333                                 netif_carrier_on(dev);
3334                 }
3335                 return 1;
3336         }
3337
3338         /* BMSR_LSTATUS is latched, read it twice:
3339          * we want the current value.
3340          */
3341         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3342         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3343
3344         if (!(mii_status & BMSR_LSTATUS)) {
3345                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3346                 newdup = 0;
3347                 retval = 0;
3348                 goto set_speed;
3349         }
3350
3351         if (np->autoneg == 0) {
3352                 if (np->fixed_mode & LPA_100FULL) {
3353                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3354                         newdup = 1;
3355                 } else if (np->fixed_mode & LPA_100HALF) {
3356                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3357                         newdup = 0;
3358                 } else if (np->fixed_mode & LPA_10FULL) {
3359                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3360                         newdup = 1;
3361                 } else {
3362                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3363                         newdup = 0;
3364                 }
3365                 retval = 1;
3366                 goto set_speed;
3367         }
3368         /* check auto negotiation is complete */
3369         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3370                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3371                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3372                 newdup = 0;
3373                 retval = 0;
3374                 goto set_speed;
3375         }
3376
3377         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3378         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3379
3380         retval = 1;
3381         if (np->gigabit == PHY_GIGABIT) {
3382                 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3383                 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
3384
3385                 if ((control_1000 & ADVERTISE_1000FULL) &&
3386                         (status_1000 & LPA_1000FULL)) {
3387                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3388                         newdup = 1;
3389                         goto set_speed;
3390                 }
3391         }
3392
3393         /* FIXME: handle parallel detection properly */
3394         adv_lpa = lpa & adv;
3395         if (adv_lpa & LPA_100FULL) {
3396                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3397                 newdup = 1;
3398         } else if (adv_lpa & LPA_100HALF) {
3399                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3400                 newdup = 0;
3401         } else if (adv_lpa & LPA_10FULL) {
3402                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3403                 newdup = 1;
3404         } else if (adv_lpa & LPA_10HALF) {
3405                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3406                 newdup = 0;
3407         } else {
3408                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3409                 newdup = 0;
3410         }
3411
3412 set_speed:
3413         if (np->duplex == newdup && np->linkspeed == newls)
3414                 return retval;
3415
3416         np->duplex = newdup;
3417         np->linkspeed = newls;
3418
3419         /* The transmitter and receiver must be restarted for safe update */
3420         if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3421                 txrxFlags |= NV_RESTART_TX;
3422                 nv_stop_tx(dev);
3423         }
3424         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3425                 txrxFlags |= NV_RESTART_RX;
3426                 nv_stop_rx(dev);
3427         }
3428
3429         if (np->gigabit == PHY_GIGABIT) {
3430                 phyreg = readl(base + NvRegSlotTime);
3431                 phyreg &= ~(0x3FF00);
3432                 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3433                     ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3434                         phyreg |= NVREG_SLOTTIME_10_100_FULL;
3435                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3436                         phyreg |= NVREG_SLOTTIME_1000_FULL;
3437                 writel(phyreg, base + NvRegSlotTime);
3438         }
3439
3440         phyreg = readl(base + NvRegPhyInterface);
3441         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3442         if (np->duplex == 0)
3443                 phyreg |= PHY_HALF;
3444         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3445                 phyreg |= PHY_100;
3446         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3447                 phyreg |= PHY_1000;
3448         writel(phyreg, base + NvRegPhyInterface);
3449
3450         phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
3451         if (phyreg & PHY_RGMII) {
3452                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
3453                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3454                 } else {
3455                         if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3456                                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3457                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3458                                 else
3459                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3460                         } else {
3461                                 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3462                         }
3463                 }
3464         } else {
3465                 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3466                         txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3467                 else
3468                         txreg = NVREG_TX_DEFERRAL_DEFAULT;
3469         }
3470         writel(txreg, base + NvRegTxDeferral);
3471
3472         if (np->desc_ver == DESC_VER_1) {
3473                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3474         } else {
3475                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3476                         txreg = NVREG_TX_WM_DESC2_3_1000;
3477                 else
3478                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3479         }
3480         writel(txreg, base + NvRegTxWatermark);
3481
3482         writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
3483                 base + NvRegMisc1);
3484         pci_push(base);
3485         writel(np->linkspeed, base + NvRegLinkSpeed);
3486         pci_push(base);
3487
3488         pause_flags = 0;
3489         /* setup pause frame */
3490         if (netif_running(dev) && (np->duplex != 0)) {
3491                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3492                         adv_pause = adv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3493                         lpa_pause = lpa & (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
3494
3495                         switch (adv_pause) {
3496                         case ADVERTISE_PAUSE_CAP:
3497                                 if (lpa_pause & LPA_PAUSE_CAP) {
3498                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3499                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3500                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3501                                 }
3502                                 break;
3503                         case ADVERTISE_PAUSE_ASYM:
3504                                 if (lpa_pause == (LPA_PAUSE_CAP | LPA_PAUSE_ASYM))
3505                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3506                                 break;
3507                         case ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM:
3508                                 if (lpa_pause & LPA_PAUSE_CAP) {
3509                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
3510                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3511                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3512                                 }
3513                                 if (lpa_pause == LPA_PAUSE_ASYM)
3514                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3515                                 break;
3516                         }
3517                 } else {
3518                         pause_flags = np->pause_flags;
3519                 }
3520         }
3521         nv_update_pause(dev, pause_flags);
3522
3523         if (txrxFlags & NV_RESTART_TX)
3524                 nv_start_tx(dev);
3525         if (txrxFlags & NV_RESTART_RX)
3526                 nv_start_rx(dev);
3527
3528         return retval;
3529 }
3530
3531 static void nv_linkchange(struct net_device *dev)
3532 {
3533         if (nv_update_linkspeed(dev)) {
3534                 if (!netif_carrier_ok(dev)) {
3535                         netif_carrier_on(dev);
3536                         netdev_info(dev, "link up\n");
3537                         nv_txrx_gate(dev, false);
3538                         nv_start_rx(dev);
3539                 }
3540         } else {
3541                 if (netif_carrier_ok(dev)) {
3542                         netif_carrier_off(dev);
3543                         netdev_info(dev, "link down\n");
3544                         nv_txrx_gate(dev, true);
3545                         nv_stop_rx(dev);
3546                 }
3547         }
3548 }
3549
3550 static void nv_link_irq(struct net_device *dev)
3551 {
3552         u8 __iomem *base = get_hwbase(dev);
3553         u32 miistat;
3554
3555         miistat = readl(base + NvRegMIIStatus);
3556         writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3557
3558         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3559                 nv_linkchange(dev);
3560 }
3561
3562 static void nv_msi_workaround(struct fe_priv *np)
3563 {
3564
3565         /* Need to toggle the msi irq mask within the ethernet device,
3566          * otherwise, future interrupts will not be detected.
3567          */
3568         if (np->msi_flags & NV_MSI_ENABLED) {
3569                 u8 __iomem *base = np->base;
3570
3571                 writel(0, base + NvRegMSIIrqMask);
3572                 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3573         }
3574 }
3575
3576 static inline int nv_change_interrupt_mode(struct net_device *dev, int total_work)
3577 {
3578         struct fe_priv *np = netdev_priv(dev);
3579
3580         if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC) {
3581                 if (total_work > NV_DYNAMIC_THRESHOLD) {
3582                         /* transition to poll based interrupts */
3583                         np->quiet_count = 0;
3584                         if (np->irqmask != NVREG_IRQMASK_CPU) {
3585                                 np->irqmask = NVREG_IRQMASK_CPU;
3586                                 return 1;
3587                         }
3588                 } else {
3589                         if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) {
3590                                 np->quiet_count++;
3591                         } else {
3592                                 /* reached a period of low activity, switch
3593                                    to per tx/rx packet interrupts */
3594                                 if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) {
3595                                         np->irqmask = NVREG_IRQMASK_THROUGHPUT;
3596                                         return 1;
3597                                 }
3598                         }
3599                 }
3600         }
3601         return 0;
3602 }
3603
3604 static irqreturn_t nv_nic_irq(int foo, void *data)
3605 {
3606         struct net_device *dev = (struct net_device *) data;
3607         struct fe_priv *np = netdev_priv(dev);
3608         u8 __iomem *base = get_hwbase(dev);
3609
3610         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3611                 np->events = readl(base + NvRegIrqStatus);
3612                 writel(np->events, base + NvRegIrqStatus);
3613         } else {
3614                 np->events = readl(base + NvRegMSIXIrqStatus);
3615                 writel(np->events, base + NvRegMSIXIrqStatus);
3616         }
3617         if (!(np->events & np->irqmask))
3618                 return IRQ_NONE;
3619
3620         nv_msi_workaround(np);
3621
3622         if (napi_schedule_prep(&np->napi)) {
3623                 /*
3624                  * Disable further irq's (msix not enabled with napi)
3625                  */
3626                 writel(0, base + NvRegIrqMask);
3627                 __napi_schedule(&np->napi);
3628         }
3629
3630         return IRQ_HANDLED;
3631 }
3632
3633 /* All _optimized functions are used to help increase performance
3634  * (reduce CPU and increase throughput). They use descripter version 3,
3635  * compiler directives, and reduce memory accesses.
3636  */
3637 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3638 {
3639         struct net_device *dev = (struct net_device *) data;
3640         struct fe_priv *np = netdev_priv(dev);
3641         u8 __iomem *base = get_hwbase(dev);
3642
3643         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3644                 np->events = readl(base + NvRegIrqStatus);
3645                 writel(np->events, base + NvRegIrqStatus);
3646         } else {
3647                 np->events = readl(base + NvRegMSIXIrqStatus);
3648                 writel(np->events, base + NvRegMSIXIrqStatus);
3649         }
3650         if (!(np->events & np->irqmask))
3651                 return IRQ_NONE;
3652
3653         nv_msi_workaround(np);
3654
3655         if (napi_schedule_prep(&np->napi)) {
3656                 /*
3657                  * Disable further irq's (msix not enabled with napi)
3658                  */
3659                 writel(0, base + NvRegIrqMask);
3660                 __napi_schedule(&np->napi);
3661         }
3662
3663         return IRQ_HANDLED;
3664 }
3665
3666 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3667 {
3668         struct net_device *dev = (struct net_device *) data;
3669         struct fe_priv *np = netdev_priv(dev);
3670         u8 __iomem *base = get_hwbase(dev);
3671         u32 events;
3672         int i;
3673         unsigned long flags;
3674
3675         for (i = 0;; i++) {
3676                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3677                 writel(events, base + NvRegMSIXIrqStatus);
3678                 netdev_dbg(dev, "tx irq events: %08x\n", events);
3679                 if (!(events & np->irqmask))
3680                         break;
3681
3682                 spin_lock_irqsave(&np->lock, flags);
3683                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3684                 spin_unlock_irqrestore(&np->lock, flags);
3685
3686                 if (unlikely(i > max_interrupt_work)) {
3687                         spin_lock_irqsave(&np->lock, flags);
3688                         /* disable interrupts on the nic */
3689                         writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3690                         pci_push(base);
3691
3692                         if (!np->in_shutdown) {
3693                                 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3694                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3695                         }
3696                         spin_unlock_irqrestore(&np->lock, flags);
3697                         netdev_dbg(dev, "%s: too many iterations (%d)\n",
3698                                    __func__, i);
3699                         break;
3700                 }
3701
3702         }
3703
3704         return IRQ_RETVAL(i);
3705 }
3706
3707 static int nv_napi_poll(struct napi_struct *napi, int budget)
3708 {
3709         struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3710         struct net_device *dev = np->dev;
3711         u8 __iomem *base = get_hwbase(dev);
3712         unsigned long flags;
3713         int retcode;
3714         int rx_count, tx_work = 0, rx_work = 0;
3715
3716         do {
3717                 if (!nv_optimized(np)) {
3718                         spin_lock_irqsave(&np->lock, flags);
3719                         tx_work += nv_tx_done(dev, np->tx_ring_size);
3720                         spin_unlock_irqrestore(&np->lock, flags);
3721
3722                         rx_count = nv_rx_process(dev, budget - rx_work);
3723                         retcode = nv_alloc_rx(dev);
3724                 } else {
3725                         spin_lock_irqsave(&np->lock, flags);
3726                         tx_work += nv_tx_done_optimized(dev, np->tx_ring_size);
3727                         spin_unlock_irqrestore(&np->lock, flags);
3728
3729                         rx_count = nv_rx_process_optimized(dev,
3730                             budget - rx_work);
3731                         retcode = nv_alloc_rx_optimized(dev);
3732                 }
3733         } while (retcode == 0 &&
3734                  rx_count > 0 && (rx_work += rx_count) < budget);
3735
3736         if (retcode) {
3737                 spin_lock_irqsave(&np->lock, flags);
3738                 if (!np->in_shutdown)
3739                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3740                 spin_unlock_irqrestore(&np->lock, flags);
3741         }
3742
3743         nv_change_interrupt_mode(dev, tx_work + rx_work);
3744
3745         if (unlikely(np->events & NVREG_IRQ_LINK)) {
3746                 spin_lock_irqsave(&np->lock, flags);
3747                 nv_link_irq(dev);
3748                 spin_unlock_irqrestore(&np->lock, flags);
3749         }
3750         if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3751                 spin_lock_irqsave(&np->lock, flags);
3752                 nv_linkchange(dev);
3753                 spin_unlock_irqrestore(&np->lock, flags);
3754                 np->link_timeout = jiffies + LINK_TIMEOUT;
3755         }
3756         if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3757                 spin_lock_irqsave(&np->lock, flags);
3758                 if (!np->in_shutdown) {
3759                         np->nic_poll_irq = np->irqmask;
3760                         np->recover_error = 1;
3761                         mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3762                 }
3763                 spin_unlock_irqrestore(&np->lock, flags);
3764                 napi_complete(napi);
3765                 return rx_work;
3766         }
3767
3768         if (rx_work < budget) {
3769                 /* re-enable interrupts
3770                    (msix not enabled in napi) */
3771                 napi_complete_done(napi, rx_work);
3772
3773                 writel(np->irqmask, base + NvRegIrqMask);
3774         }
3775         return rx_work;
3776 }
3777
3778 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3779 {
3780         struct net_device *dev = (struct net_device *) data;
3781         struct fe_priv *np = netdev_priv(dev);
3782         u8 __iomem *base = get_hwbase(dev);
3783         u32 events;
3784         int i;
3785         unsigned long flags;
3786
3787         for (i = 0;; i++) {
3788                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3789                 writel(events, base + NvRegMSIXIrqStatus);
3790                 netdev_dbg(dev, "rx irq events: %08x\n", events);
3791                 if (!(events & np->irqmask))
3792                         break;
3793
3794                 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3795                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3796                                 spin_lock_irqsave(&np->lock, flags);
3797                                 if (!np->in_shutdown)
3798                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3799                                 spin_unlock_irqrestore(&np->lock, flags);
3800                         }
3801                 }
3802
3803                 if (unlikely(i > max_interrupt_work)) {
3804                         spin_lock_irqsave(&np->lock, flags);
3805                         /* disable interrupts on the nic */
3806                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3807                         pci_push(base);
3808
3809                         if (!np->in_shutdown) {
3810                                 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3811                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3812                         }
3813                         spin_unlock_irqrestore(&np->lock, flags);
3814                         netdev_dbg(dev, "%s: too many iterations (%d)\n",
3815                                    __func__, i);
3816                         break;
3817                 }
3818         }
3819
3820         return IRQ_RETVAL(i);
3821 }
3822
3823 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3824 {
3825         struct net_device *dev = (struct net_device *) data;
3826         struct fe_priv *np = netdev_priv(dev);
3827         u8 __iomem *base = get_hwbase(dev);
3828         u32 events;
3829         int i;
3830         unsigned long flags;
3831
3832         for (i = 0;; i++) {
3833                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3834                 writel(events, base + NvRegMSIXIrqStatus);
3835                 netdev_dbg(dev, "irq events: %08x\n", events);
3836                 if (!(events & np->irqmask))
3837                         break;
3838
3839                 /* check tx in case we reached max loop limit in tx isr */
3840                 spin_lock_irqsave(&np->lock, flags);
3841                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3842                 spin_unlock_irqrestore(&np->lock, flags);
3843
3844                 if (events & NVREG_IRQ_LINK) {
3845                         spin_lock_irqsave(&np->lock, flags);
3846                         nv_link_irq(dev);
3847                         spin_unlock_irqrestore(&np->lock, flags);
3848                 }
3849                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3850                         spin_lock_irqsave(&np->lock, flags);
3851                         nv_linkchange(dev);
3852                         spin_unlock_irqrestore(&np->lock, flags);
3853                         np->link_timeout = jiffies + LINK_TIMEOUT;
3854                 }
3855                 if (events & NVREG_IRQ_RECOVER_ERROR) {
3856                         spin_lock_irqsave(&np->lock, flags);
3857                         /* disable interrupts on the nic */
3858                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3859                         pci_push(base);
3860
3861                         if (!np->in_shutdown) {
3862                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3863                                 np->recover_error = 1;
3864                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3865                         }
3866                         spin_unlock_irqrestore(&np->lock, flags);
3867                         break;
3868                 }
3869                 if (unlikely(i > max_interrupt_work)) {
3870                         spin_lock_irqsave(&np->lock, flags);
3871                         /* disable interrupts on the nic */
3872                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3873                         pci_push(base);
3874
3875                         if (!np->in_shutdown) {
3876                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3877                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3878                         }
3879                         spin_unlock_irqrestore(&np->lock, flags);
3880                         netdev_dbg(dev, "%s: too many iterations (%d)\n",
3881                                    __func__, i);
3882                         break;
3883                 }
3884
3885         }
3886
3887         return IRQ_RETVAL(i);
3888 }
3889
3890 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3891 {
3892         struct net_device *dev = (struct net_device *) data;
3893         struct fe_priv *np = netdev_priv(dev);
3894         u8 __iomem *base = get_hwbase(dev);
3895         u32 events;
3896
3897         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3898                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3899                 writel(events & NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3900         } else {
3901                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3902                 writel(events & NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3903         }
3904         pci_push(base);
3905         if (!(events & NVREG_IRQ_TIMER))
3906                 return IRQ_RETVAL(0);
3907
3908         nv_msi_workaround(np);
3909
3910         spin_lock(&np->lock);
3911         np->intr_test = 1;
3912         spin_unlock(&np->lock);
3913
3914         return IRQ_RETVAL(1);
3915 }
3916
3917 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3918 {
3919         u8 __iomem *base = get_hwbase(dev);
3920         int i;
3921         u32 msixmap = 0;
3922
3923         /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3924          * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3925          * the remaining 8 interrupts.
3926          */
3927         for (i = 0; i < 8; i++) {
3928                 if ((irqmask >> i) & 0x1)
3929                         msixmap |= vector << (i << 2);
3930         }
3931         writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3932
3933         msixmap = 0;
3934         for (i = 0; i < 8; i++) {
3935                 if ((irqmask >> (i + 8)) & 0x1)
3936                         msixmap |= vector << (i << 2);
3937         }
3938         writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3939 }
3940
3941 static int nv_request_irq(struct net_device *dev, int intr_test)
3942 {
3943         struct fe_priv *np = get_nvpriv(dev);
3944         u8 __iomem *base = get_hwbase(dev);
3945         int ret;
3946         int i;
3947         irqreturn_t (*handler)(int foo, void *data);
3948
3949         if (intr_test) {
3950                 handler = nv_nic_irq_test;
3951         } else {
3952                 if (nv_optimized(np))
3953                         handler = nv_nic_irq_optimized;
3954                 else
3955                         handler = nv_nic_irq;
3956         }
3957
3958         if (np->msi_flags & NV_MSI_X_CAPABLE) {
3959                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
3960                         np->msi_x_entry[i].entry = i;
3961                 ret = pci_enable_msix_range(np->pci_dev,
3962                                             np->msi_x_entry,
3963                                             np->msi_flags & NV_MSI_X_VECTORS_MASK,
3964                                             np->msi_flags & NV_MSI_X_VECTORS_MASK);
3965                 if (ret > 0) {
3966                         np->msi_flags |= NV_MSI_X_ENABLED;
3967                         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3968                                 /* Request irq for rx handling */
3969                                 sprintf(np->name_rx, "%s-rx", dev->name);
3970                                 ret = request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
3971                                                   nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev);
3972                                 if (ret) {
3973                                         netdev_info(dev,
3974                                                     "request_irq failed for rx %d\n",
3975                                                     ret);
3976                                         pci_disable_msix(np->pci_dev);
3977                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3978                                         goto out_err;
3979                                 }
3980                                 /* Request irq for tx handling */
3981                                 sprintf(np->name_tx, "%s-tx", dev->name);
3982                                 ret = request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
3983                                                   nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev);
3984                                 if (ret) {
3985                                         netdev_info(dev,
3986                                                     "request_irq failed for tx %d\n",
3987                                                     ret);
3988                                         pci_disable_msix(np->pci_dev);
3989                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3990                                         goto out_free_rx;
3991                                 }
3992                                 /* Request irq for link and timer handling */
3993                                 sprintf(np->name_other, "%s-other", dev->name);
3994                                 ret = request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
3995                                                   nv_nic_irq_other, IRQF_SHARED, np->name_other, dev);
3996                                 if (ret) {
3997                                         netdev_info(dev,
3998                                                     "request_irq failed for link %d\n",
3999                                                     ret);
4000                                         pci_disable_msix(np->pci_dev);
4001                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
4002                                         goto out_free_tx;
4003                                 }
4004                                 /* map interrupts to their respective vector */
4005                                 writel(0, base + NvRegMSIXMap0);
4006                                 writel(0, base + NvRegMSIXMap1);
4007                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
4008                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
4009                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
4010                         } else {
4011                                 /* Request irq for all interrupts */
4012                                 ret = request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector,
4013                                                   handler, IRQF_SHARED, dev->name, dev);
4014                                 if (ret) {
4015                                         netdev_info(dev,
4016                                                     "request_irq failed %d\n",
4017                                                     ret);
4018                                         pci_disable_msix(np->pci_dev);
4019                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
4020                                         goto out_err;
4021                                 }
4022
4023                                 /* map interrupts to vector 0 */
4024                                 writel(0, base + NvRegMSIXMap0);
4025                                 writel(0, base + NvRegMSIXMap1);
4026                         }
4027                         netdev_info(dev, "MSI-X enabled\n");
4028                         return 0;
4029                 }
4030         }
4031         if (np->msi_flags & NV_MSI_CAPABLE) {
4032                 ret = pci_enable_msi(np->pci_dev);
4033                 if (ret == 0) {
4034                         np->msi_flags |= NV_MSI_ENABLED;
4035                         ret = request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev);
4036                         if (ret) {
4037                                 netdev_info(dev, "request_irq failed %d\n",
4038                                             ret);
4039                                 pci_disable_msi(np->pci_dev);
4040                                 np->msi_flags &= ~NV_MSI_ENABLED;
4041                                 goto out_err;
4042                         }
4043
4044                         /* map interrupts to vector 0 */
4045                         writel(0, base + NvRegMSIMap0);
4046                         writel(0, base + NvRegMSIMap1);
4047                         /* enable msi vector 0 */
4048                         writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
4049                         netdev_info(dev, "MSI enabled\n");
4050                         return 0;
4051                 }
4052         }
4053
4054         if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
4055                 goto out_err;
4056
4057         return 0;
4058 out_free_tx:
4059         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
4060 out_free_rx:
4061         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
4062 out_err:
4063         return 1;
4064 }
4065
4066 static void nv_free_irq(struct net_device *dev)
4067 {
4068         struct fe_priv *np = get_nvpriv(dev);
4069         int i;
4070
4071         if (np->msi_flags & NV_MSI_X_ENABLED) {
4072                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
4073                         free_irq(np->msi_x_entry[i].vector, dev);
4074                 pci_disable_msix(np->pci_dev);
4075                 np->msi_flags &= ~NV_MSI_X_ENABLED;
4076         } else {
4077                 free_irq(np->pci_dev->irq, dev);
4078                 if (np->msi_flags & NV_MSI_ENABLED) {
4079                         pci_disable_msi(np->pci_dev);
4080                         np->msi_flags &= ~NV_MSI_ENABLED;
4081                 }
4082         }
4083 }
4084
4085 static void nv_do_nic_poll(struct timer_list *t)
4086 {
4087         struct fe_priv *np = from_timer(np, t, nic_poll);
4088         struct net_device *dev = np->dev;
4089         u8 __iomem *base = get_hwbase(dev);
4090         u32 mask = 0;
4091         unsigned long flags;
4092         unsigned int irq = 0;
4093
4094         /*
4095          * First disable irq(s) and then
4096          * reenable interrupts on the nic, we have to do this before calling
4097          * nv_nic_irq because that may decide to do otherwise
4098          */
4099
4100         if (!using_multi_irqs(dev)) {
4101                 if (np->msi_flags & NV_MSI_X_ENABLED)
4102                         irq = np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector;
4103                 else
4104                         irq = np->pci_dev->irq;
4105                 mask = np->irqmask;
4106         } else {
4107                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4108                         irq = np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector;
4109                         mask |= NVREG_IRQ_RX_ALL;
4110                 }
4111                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4112                         irq = np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector;
4113                         mask |= NVREG_IRQ_TX_ALL;
4114                 }
4115                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4116                         irq = np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector;
4117                         mask |= NVREG_IRQ_OTHER;
4118                 }
4119         }
4120
4121         disable_irq_nosync_lockdep_irqsave(irq, &flags);
4122         synchronize_irq(irq);
4123
4124         if (np->recover_error) {
4125                 np->recover_error = 0;
4126                 netdev_info(dev, "MAC in recoverable error state\n");
4127                 if (netif_running(dev)) {
4128                         netif_tx_lock_bh(dev);
4129                         netif_addr_lock(dev);
4130                         spin_lock(&np->lock);
4131                         /* stop engines */
4132                         nv_stop_rxtx(dev);
4133                         if (np->driver_data & DEV_HAS_POWER_CNTRL)
4134                                 nv_mac_reset(dev);
4135                         nv_txrx_reset(dev);
4136                         /* drain rx queue */
4137                         nv_drain_rxtx(dev);
4138                         /* reinit driver view of the rx queue */
4139                         set_bufsize(dev);
4140                         if (nv_init_ring(dev)) {
4141                                 if (!np->in_shutdown)
4142                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4143                         }
4144                         /* reinit nic view of the rx queue */
4145                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4146                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4147                         writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4148                                 base + NvRegRingSizes);
4149                         pci_push(base);
4150                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4151                         pci_push(base);
4152                         /* clear interrupts */
4153                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4154                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4155                         else
4156                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4157
4158                         /* restart rx engine */
4159                         nv_start_rxtx(dev);
4160                         spin_unlock(&np->lock);
4161                         netif_addr_unlock(dev);
4162                         netif_tx_unlock_bh(dev);
4163                 }
4164         }
4165
4166         writel(mask, base + NvRegIrqMask);
4167         pci_push(base);
4168
4169         if (!using_multi_irqs(dev)) {
4170                 np->nic_poll_irq = 0;
4171                 if (nv_optimized(np))
4172                         nv_nic_irq_optimized(0, dev);
4173                 else
4174                         nv_nic_irq(0, dev);
4175         } else {
4176                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4177                         np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL;
4178                         nv_nic_irq_rx(0, dev);
4179                 }
4180                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4181                         np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL;
4182                         nv_nic_irq_tx(0, dev);
4183                 }
4184                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4185                         np->nic_poll_irq &= ~NVREG_IRQ_OTHER;
4186                         nv_nic_irq_other(0, dev);
4187                 }
4188         }
4189
4190         enable_irq_lockdep_irqrestore(irq, &flags);
4191 }
4192
4193 #ifdef CONFIG_NET_POLL_CONTROLLER
4194 static void nv_poll_controller(struct net_device *dev)
4195 {
4196         struct fe_priv *np = netdev_priv(dev);
4197
4198         nv_do_nic_poll(&np->nic_poll);
4199 }
4200 #endif
4201
4202 static void nv_do_stats_poll(struct timer_list *t)
4203         __acquires(&netdev_priv(dev)->hwstats_lock)
4204         __releases(&netdev_priv(dev)->hwstats_lock)
4205 {
4206         struct fe_priv *np = from_timer(np, t, stats_poll);
4207         struct net_device *dev = np->dev;
4208
4209         /* If lock is currently taken, the stats are being refreshed
4210          * and hence fresh enough */
4211         if (spin_trylock(&np->hwstats_lock)) {
4212                 nv_update_stats(dev);
4213                 spin_unlock(&np->hwstats_lock);
4214         }
4215
4216         if (!np->in_shutdown)
4217                 mod_timer(&np->stats_poll,
4218                         round_jiffies(jiffies + STATS_INTERVAL));
4219 }
4220
4221 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4222 {
4223         struct fe_priv *np = netdev_priv(dev);
4224         strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
4225         strlcpy(info->version, FORCEDETH_VERSION, sizeof(info->version));
4226         strlcpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info));
4227 }
4228
4229 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4230 {
4231         struct fe_priv *np = netdev_priv(dev);
4232         wolinfo->supported = WAKE_MAGIC;
4233
4234         spin_lock_irq(&np->lock);
4235         if (np->wolenabled)
4236                 wolinfo->wolopts = WAKE_MAGIC;
4237         spin_unlock_irq(&np->lock);
4238 }
4239
4240 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4241 {
4242         struct fe_priv *np = netdev_priv(dev);
4243         u8 __iomem *base = get_hwbase(dev);
4244         u32 flags = 0;
4245
4246         if (wolinfo->wolopts == 0) {
4247                 np->wolenabled = 0;
4248         } else if (wolinfo->wolopts & WAKE_MAGIC) {
4249                 np->wolenabled = 1;
4250                 flags = NVREG_WAKEUPFLAGS_ENABLE;
4251         }
4252         if (netif_running(dev)) {
4253                 spin_lock_irq(&np->lock);
4254                 writel(flags, base + NvRegWakeUpFlags);
4255                 spin_unlock_irq(&np->lock);
4256         }
4257         device_set_wakeup_enable(&np->pci_dev->dev, np->wolenabled);
4258         return 0;
4259 }
4260
4261 static int nv_get_link_ksettings(struct net_device *dev,
4262                                  struct ethtool_link_ksettings *cmd)
4263 {
4264         struct fe_priv *np = netdev_priv(dev);
4265         u32 speed, supported, advertising;
4266         int adv;
4267
4268         spin_lock_irq(&np->lock);
4269         cmd->base.port = PORT_MII;
4270         if (!netif_running(dev)) {
4271                 /* We do not track link speed / duplex setting if the
4272                  * interface is disabled. Force a link check */
4273                 if (nv_update_linkspeed(dev)) {
4274                         netif_carrier_on(dev);
4275                 } else {
4276                         netif_carrier_off(dev);
4277                 }
4278         }
4279
4280         if (netif_carrier_ok(dev)) {
4281                 switch (np->linkspeed & (NVREG_LINKSPEED_MASK)) {
4282                 case NVREG_LINKSPEED_10:
4283                         speed = SPEED_10;
4284                         break;
4285                 case NVREG_LINKSPEED_100:
4286                         speed = SPEED_100;
4287                         break;
4288                 case NVREG_LINKSPEED_1000:
4289                         speed = SPEED_1000;
4290                         break;
4291                 default:
4292                         speed = -1;
4293                         break;
4294                 }
4295                 cmd->base.duplex = DUPLEX_HALF;
4296                 if (np->duplex)
4297                         cmd->base.duplex = DUPLEX_FULL;
4298         } else {
4299                 speed = SPEED_UNKNOWN;
4300                 cmd->base.duplex = DUPLEX_UNKNOWN;
4301         }
4302         cmd->base.speed = speed;
4303         cmd->base.autoneg = np->autoneg;
4304
4305         advertising = ADVERTISED_MII;
4306         if (np->autoneg) {
4307                 advertising |= ADVERTISED_Autoneg;
4308                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4309                 if (adv & ADVERTISE_10HALF)
4310                         advertising |= ADVERTISED_10baseT_Half;
4311                 if (adv & ADVERTISE_10FULL)
4312                         advertising |= ADVERTISED_10baseT_Full;
4313                 if (adv & ADVERTISE_100HALF)
4314                         advertising |= ADVERTISED_100baseT_Half;
4315                 if (adv & ADVERTISE_100FULL)
4316                         advertising |= ADVERTISED_100baseT_Full;
4317                 if (np->gigabit == PHY_GIGABIT) {
4318                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4319                         if (adv & ADVERTISE_1000FULL)
4320                                 advertising |= ADVERTISED_1000baseT_Full;
4321                 }
4322         }
4323         supported = (SUPPORTED_Autoneg |
4324                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4325                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4326                 SUPPORTED_MII);
4327         if (np->gigabit == PHY_GIGABIT)
4328                 supported |= SUPPORTED_1000baseT_Full;
4329
4330         cmd->base.phy_address = np->phyaddr;
4331
4332         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
4333                                                 supported);
4334         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
4335                                                 advertising);
4336
4337         /* ignore maxtxpkt, maxrxpkt for now */
4338         spin_unlock_irq(&np->lock);
4339         return 0;
4340 }
4341
4342 static int nv_set_link_ksettings(struct net_device *dev,
4343                                  const struct ethtool_link_ksettings *cmd)
4344 {
4345         struct fe_priv *np = netdev_priv(dev);
4346         u32 speed = cmd->base.speed;
4347         u32 advertising;
4348
4349         ethtool_convert_link_mode_to_legacy_u32(&advertising,
4350                                                 cmd->link_modes.advertising);
4351
4352         if (cmd->base.port != PORT_MII)
4353                 return -EINVAL;
4354         if (cmd->base.phy_address != np->phyaddr) {
4355                 /* TODO: support switching between multiple phys. Should be
4356                  * trivial, but not enabled due to lack of test hardware. */
4357                 return -EINVAL;
4358         }
4359         if (cmd->base.autoneg == AUTONEG_ENABLE) {
4360                 u32 mask;
4361
4362                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4363                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4364                 if (np->gigabit == PHY_GIGABIT)
4365                         mask |= ADVERTISED_1000baseT_Full;
4366
4367                 if ((advertising & mask) == 0)
4368                         return -EINVAL;
4369
4370         } else if (cmd->base.autoneg == AUTONEG_DISABLE) {
4371                 /* Note: autonegotiation disable, speed 1000 intentionally
4372                  * forbidden - no one should need that. */
4373
4374                 if (speed != SPEED_10 && speed != SPEED_100)
4375                         return -EINVAL;
4376                 if (cmd->base.duplex != DUPLEX_HALF &&
4377                     cmd->base.duplex != DUPLEX_FULL)
4378                         return -EINVAL;
4379         } else {
4380                 return -EINVAL;
4381         }
4382
4383         netif_carrier_off(dev);
4384         if (netif_running(dev)) {
4385                 unsigned long flags;
4386
4387                 nv_disable_irq(dev);
4388                 netif_tx_lock_bh(dev);
4389                 netif_addr_lock(dev);
4390                 /* with plain spinlock lockdep complains */
4391                 spin_lock_irqsave(&np->lock, flags);
4392                 /* stop engines */
4393                 /* FIXME:
4394                  * this can take some time, and interrupts are disabled
4395                  * due to spin_lock_irqsave, but let's hope no daemon
4396                  * is going to change the settings very often...
4397                  * Worst case:
4398                  * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4399                  * + some minor delays, which is up to a second approximately
4400                  */
4401                 nv_stop_rxtx(dev);
4402                 spin_unlock_irqrestore(&np->lock, flags);
4403                 netif_addr_unlock(dev);
4404                 netif_tx_unlock_bh(dev);
4405         }
4406
4407         if (cmd->base.autoneg == AUTONEG_ENABLE) {
4408                 int adv, bmcr;
4409
4410                 np->autoneg = 1;
4411
4412                 /* advertise only what has been requested */
4413                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4414                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4415                 if (advertising & ADVERTISED_10baseT_Half)
4416                         adv |= ADVERTISE_10HALF;
4417                 if (advertising & ADVERTISED_10baseT_Full)
4418                         adv |= ADVERTISE_10FULL;
4419                 if (advertising & ADVERTISED_100baseT_Half)
4420                         adv |= ADVERTISE_100HALF;
4421                 if (advertising & ADVERTISED_100baseT_Full)
4422                         adv |= ADVERTISE_100FULL;
4423                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)  /* for rx we set both advertisements but disable tx pause */
4424                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4425                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4426                         adv |=  ADVERTISE_PAUSE_ASYM;
4427                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4428
4429                 if (np->gigabit == PHY_GIGABIT) {
4430                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4431                         adv &= ~ADVERTISE_1000FULL;
4432                         if (advertising & ADVERTISED_1000baseT_Full)
4433                                 adv |= ADVERTISE_1000FULL;
4434                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4435                 }
4436
4437                 if (netif_running(dev))
4438                         netdev_info(dev, "link down\n");
4439                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4440                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4441                         bmcr |= BMCR_ANENABLE;
4442                         /* reset the phy in order for settings to stick,
4443                          * and cause autoneg to start */
4444                         if (phy_reset(dev, bmcr)) {
4445                                 netdev_info(dev, "phy reset failed\n");
4446                                 return -EINVAL;
4447                         }
4448                 } else {
4449                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4450                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4451                 }
4452         } else {
4453                 int adv, bmcr;
4454
4455                 np->autoneg = 0;
4456
4457                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4458                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4459                 if (speed == SPEED_10 && cmd->base.duplex == DUPLEX_HALF)
4460                         adv |= ADVERTISE_10HALF;
4461                 if (speed == SPEED_10 && cmd->base.duplex == DUPLEX_FULL)
4462                         adv |= ADVERTISE_10FULL;
4463                 if (speed == SPEED_100 && cmd->base.duplex == DUPLEX_HALF)
4464                         adv |= ADVERTISE_100HALF;
4465                 if (speed == SPEED_100 && cmd->base.duplex == DUPLEX_FULL)
4466                         adv |= ADVERTISE_100FULL;
4467                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4468                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisements but disable tx pause */
4469                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4470                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4471                 }
4472                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4473                         adv |=  ADVERTISE_PAUSE_ASYM;
4474                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4475                 }
4476                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4477                 np->fixed_mode = adv;
4478
4479                 if (np->gigabit == PHY_GIGABIT) {
4480                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4481                         adv &= ~ADVERTISE_1000FULL;
4482                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4483                 }
4484
4485                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4486                 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4487                 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
4488                         bmcr |= BMCR_FULLDPLX;
4489                 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
4490                         bmcr |= BMCR_SPEED100;
4491                 if (np->phy_oui == PHY_OUI_MARVELL) {
4492                         /* reset the phy in order for forced mode settings to stick */
4493                         if (phy_reset(dev, bmcr)) {
4494                                 netdev_info(dev, "phy reset failed\n");
4495                                 return -EINVAL;
4496                         }
4497                 } else {
4498                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4499                         if (netif_running(dev)) {
4500                                 /* Wait a bit and then reconfigure the nic. */
4501                                 udelay(10);
4502                                 nv_linkchange(dev);
4503                         }
4504                 }
4505         }
4506
4507         if (netif_running(dev)) {
4508                 nv_start_rxtx(dev);
4509                 nv_enable_irq(dev);
4510         }
4511
4512         return 0;
4513 }
4514
4515 #define FORCEDETH_REGS_VER      1
4516
4517 static int nv_get_regs_len(struct net_device *dev)
4518 {
4519         struct fe_priv *np = netdev_priv(dev);
4520         return np->register_size;
4521 }
4522
4523 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4524 {
4525         struct fe_priv *np = netdev_priv(dev);
4526         u8 __iomem *base = get_hwbase(dev);
4527         u32 *rbuf = buf;
4528         int i;
4529
4530         regs->version = FORCEDETH_REGS_VER;
4531         spin_lock_irq(&np->lock);
4532         for (i = 0; i < np->register_size/sizeof(u32); i++)
4533                 rbuf[i] = readl(base + i*sizeof(u32));
4534         spin_unlock_irq(&np->lock);
4535 }
4536
4537 static int nv_nway_reset(struct net_device *dev)
4538 {
4539         struct fe_priv *np = netdev_priv(dev);
4540         int ret;
4541
4542         if (np->autoneg) {
4543                 int bmcr;
4544
4545                 netif_carrier_off(dev);
4546                 if (netif_running(dev)) {
4547                         nv_disable_irq(dev);
4548                         netif_tx_lock_bh(dev);
4549                         netif_addr_lock(dev);
4550                         spin_lock(&np->lock);
4551                         /* stop engines */
4552                         nv_stop_rxtx(dev);
4553                         spin_unlock(&np->lock);
4554                         netif_addr_unlock(dev);
4555                         netif_tx_unlock_bh(dev);
4556                         netdev_info(dev, "link down\n");
4557                 }
4558
4559                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4560                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4561                         bmcr |= BMCR_ANENABLE;
4562                         /* reset the phy in order for settings to stick*/
4563                         if (phy_reset(dev, bmcr)) {
4564                                 netdev_info(dev, "phy reset failed\n");
4565                                 return -EINVAL;
4566                         }
4567                 } else {
4568                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4569                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4570                 }
4571
4572                 if (netif_running(dev)) {
4573                         nv_start_rxtx(dev);
4574                         nv_enable_irq(dev);
4575                 }
4576                 ret = 0;
4577         } else {
4578                 ret = -EINVAL;
4579         }
4580
4581         return ret;
4582 }
4583
4584 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4585 {
4586         struct fe_priv *np = netdev_priv(dev);
4587
4588         ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4589         ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4590
4591         ring->rx_pending = np->rx_ring_size;
4592         ring->tx_pending = np->tx_ring_size;
4593 }
4594
4595 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4596 {
4597         struct fe_priv *np = netdev_priv(dev);
4598         u8 __iomem *base = get_hwbase(dev);
4599         u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4600         dma_addr_t ring_addr;
4601
4602         if (ring->rx_pending < RX_RING_MIN ||
4603             ring->tx_pending < TX_RING_MIN ||
4604             ring->rx_mini_pending != 0 ||
4605             ring->rx_jumbo_pending != 0 ||
4606             (np->desc_ver == DESC_VER_1 &&
4607              (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4608               ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4609             (np->desc_ver != DESC_VER_1 &&
4610              (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4611               ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4612                 return -EINVAL;
4613         }
4614
4615         /* allocate new rings */
4616         if (!nv_optimized(np)) {
4617                 rxtx_ring = dma_alloc_coherent(&np->pci_dev->dev,
4618                                                sizeof(struct ring_desc) *
4619                                                (ring->rx_pending +
4620                                                ring->tx_pending),
4621                                                &ring_addr, GFP_ATOMIC);
4622         } else {
4623                 rxtx_ring = dma_alloc_coherent(&np->pci_dev->dev,
4624                                                sizeof(struct ring_desc_ex) *
4625                                                (ring->rx_pending +
4626                                                ring->tx_pending),
4627                                                &ring_addr, GFP_ATOMIC);
4628         }
4629         rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4630         tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4631         if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4632                 /* fall back to old rings */
4633                 if (!nv_optimized(np)) {
4634                         if (rxtx_ring)
4635                                 dma_free_coherent(&np->pci_dev->dev,
4636                                                   sizeof(struct ring_desc) *
4637                                                   (ring->rx_pending +
4638                                                   ring->tx_pending),
4639                                                   rxtx_ring, ring_addr);
4640                 } else {
4641                         if (rxtx_ring)
4642                                 dma_free_coherent(&np->pci_dev->dev,
4643                                                   sizeof(struct ring_desc_ex) *
4644                                                   (ring->rx_pending +
4645                                                   ring->tx_pending),
4646                                                   rxtx_ring, ring_addr);
4647                 }
4648
4649                 kfree(rx_skbuff);
4650                 kfree(tx_skbuff);
4651                 goto exit;
4652         }
4653
4654         if (netif_running(dev)) {
4655                 nv_disable_irq(dev);
4656                 nv_napi_disable(dev);
4657                 netif_tx_lock_bh(dev);
4658                 netif_addr_lock(dev);
4659                 spin_lock(&np->lock);
4660                 /* stop engines */
4661                 nv_stop_rxtx(dev);
4662                 nv_txrx_reset(dev);
4663                 /* drain queues */
4664                 nv_drain_rxtx(dev);
4665                 /* delete queues */
4666                 free_rings(dev);
4667         }
4668
4669         /* set new values */
4670         np->rx_ring_size = ring->rx_pending;
4671         np->tx_ring_size = ring->tx_pending;
4672
4673         if (!nv_optimized(np)) {
4674                 np->rx_ring.orig = (struct ring_desc *)rxtx_ring;
4675                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4676         } else {
4677                 np->rx_ring.ex = (struct ring_desc_ex *)rxtx_ring;
4678                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4679         }
4680         np->rx_skb = (struct nv_skb_map *)rx_skbuff;
4681         np->tx_skb = (struct nv_skb_map *)tx_skbuff;
4682         np->ring_addr = ring_addr;
4683
4684         memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4685         memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4686
4687         if (netif_running(dev)) {
4688                 /* reinit driver view of the queues */
4689                 set_bufsize(dev);
4690                 if (nv_init_ring(dev)) {
4691                         if (!np->in_shutdown)
4692                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4693                 }
4694
4695                 /* reinit nic view of the queues */
4696                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4697                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4698                 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4699                         base + NvRegRingSizes);
4700                 pci_push(base);
4701                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4702                 pci_push(base);
4703
4704                 /* restart engines */
4705                 nv_start_rxtx(dev);
4706                 spin_unlock(&np->lock);
4707                 netif_addr_unlock(dev);
4708                 netif_tx_unlock_bh(dev);
4709                 nv_napi_enable(dev);
4710                 nv_enable_irq(dev);
4711         }
4712         return 0;
4713 exit:
4714         return -ENOMEM;
4715 }
4716
4717 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4718 {
4719         struct fe_priv *np = netdev_priv(dev);
4720
4721         pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4722         pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4723         pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4724 }
4725
4726 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4727 {
4728         struct fe_priv *np = netdev_priv(dev);
4729         int adv, bmcr;
4730
4731         if ((!np->autoneg && np->duplex == 0) ||
4732             (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4733                 netdev_info(dev, "can not set pause settings when forced link is in half duplex\n");
4734                 return -EINVAL;
4735         }
4736         if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4737                 netdev_info(dev, "hardware does not support tx pause frames\n");
4738                 return -EINVAL;
4739         }
4740
4741         netif_carrier_off(dev);
4742         if (netif_running(dev)) {
4743                 nv_disable_irq(dev);
4744                 netif_tx_lock_bh(dev);
4745                 netif_addr_lock(dev);
4746                 spin_lock(&np->lock);
4747                 /* stop engines */
4748                 nv_stop_rxtx(dev);
4749                 spin_unlock(&np->lock);
4750                 netif_addr_unlock(dev);
4751                 netif_tx_unlock_bh(dev);
4752         }
4753
4754         np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4755         if (pause->rx_pause)
4756                 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4757         if (pause->tx_pause)
4758                 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4759
4760         if (np->autoneg && pause->autoneg) {
4761                 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4762
4763                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4764                 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4765                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pause */
4766                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4767                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4768                         adv |=  ADVERTISE_PAUSE_ASYM;
4769                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4770
4771                 if (netif_running(dev))
4772                         netdev_info(dev, "link down\n");
4773                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4774                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4775                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4776         } else {
4777                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4778                 if (pause->rx_pause)
4779                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4780                 if (pause->tx_pause)
4781                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4782
4783                 if (!netif_running(dev))
4784                         nv_update_linkspeed(dev);
4785                 else
4786                         nv_update_pause(dev, np->pause_flags);
4787         }
4788
4789         if (netif_running(dev)) {
4790                 nv_start_rxtx(dev);
4791                 nv_enable_irq(dev);
4792         }
4793         return 0;
4794 }
4795
4796 static int nv_set_loopback(struct net_device *dev, netdev_features_t features)
4797 {
4798         struct fe_priv *np = netdev_priv(dev);
4799         unsigned long flags;
4800         u32 miicontrol;
4801         int err, retval = 0;
4802
4803         spin_lock_irqsave(&np->lock, flags);
4804         miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4805         if (features & NETIF_F_LOOPBACK) {
4806                 if (miicontrol & BMCR_LOOPBACK) {
4807                         spin_unlock_irqrestore(&np->lock, flags);
4808                         netdev_info(dev, "Loopback already enabled\n");
4809                         return 0;
4810                 }
4811                 nv_disable_irq(dev);
4812                 /* Turn on loopback mode */
4813                 miicontrol |= BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
4814                 err = mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol);
4815                 if (err) {
4816                         retval = PHY_ERROR;
4817                         spin_unlock_irqrestore(&np->lock, flags);
4818                         phy_init(dev);
4819                 } else {
4820                         if (netif_running(dev)) {
4821                                 /* Force 1000 Mbps full-duplex */
4822                                 nv_force_linkspeed(dev, NVREG_LINKSPEED_1000,
4823                                                                          1);
4824                                 /* Force link up */
4825                                 netif_carrier_on(dev);
4826                         }
4827                         spin_unlock_irqrestore(&np->lock, flags);
4828                         netdev_info(dev,
4829                                 "Internal PHY loopback mode enabled.\n");
4830                 }
4831         } else {
4832                 if (!(miicontrol & BMCR_LOOPBACK)) {
4833                         spin_unlock_irqrestore(&np->lock, flags);
4834                         netdev_info(dev, "Loopback already disabled\n");
4835                         return 0;
4836                 }
4837                 nv_disable_irq(dev);
4838                 /* Turn off loopback */
4839                 spin_unlock_irqrestore(&np->lock, flags);
4840                 netdev_info(dev, "Internal PHY loopback mode disabled.\n");
4841                 phy_init(dev);
4842         }
4843         msleep(500);
4844         spin_lock_irqsave(&np->lock, flags);
4845         nv_enable_irq(dev);
4846         spin_unlock_irqrestore(&np->lock, flags);
4847
4848         return retval;
4849 }
4850
4851 static netdev_features_t nv_fix_features(struct net_device *dev,
4852         netdev_features_t features)
4853 {
4854         /* vlan is dependent on rx checksum offload */
4855         if (features & (NETIF_F_HW_VLAN_CTAG_TX|NETIF_F_HW_VLAN_CTAG_RX))
4856                 features |= NETIF_F_RXCSUM;
4857
4858         return features;
4859 }
4860
4861 static void nv_vlan_mode(struct net_device *dev, netdev_features_t features)
4862 {
4863         struct fe_priv *np = get_nvpriv(dev);
4864
4865         spin_lock_irq(&np->lock);
4866
4867         if (features & NETIF_F_HW_VLAN_CTAG_RX)
4868                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP;
4869         else
4870                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
4871
4872         if (features & NETIF_F_HW_VLAN_CTAG_TX)
4873                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANINS;
4874         else
4875                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
4876
4877         writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4878
4879         spin_unlock_irq(&np->lock);
4880 }
4881
4882 static int nv_set_features(struct net_device *dev, netdev_features_t features)
4883 {
4884         struct fe_priv *np = netdev_priv(dev);
4885         u8 __iomem *base = get_hwbase(dev);
4886         netdev_features_t changed = dev->features ^ features;
4887         int retval;
4888
4889         if ((changed & NETIF_F_LOOPBACK) && netif_running(dev)) {
4890                 retval = nv_set_loopback(dev, features);
4891                 if (retval != 0)
4892                         return retval;
4893         }
4894
4895         if (changed & NETIF_F_RXCSUM) {
4896                 spin_lock_irq(&np->lock);
4897
4898                 if (features & NETIF_F_RXCSUM)
4899                         np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4900                 else
4901                         np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4902
4903                 if (netif_running(dev))
4904                         writel(np->txrxctl_bits, base + NvRegTxRxControl);
4905
4906                 spin_unlock_irq(&np->lock);
4907         }
4908
4909         if (changed & (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX))
4910                 nv_vlan_mode(dev, features);
4911
4912         return 0;
4913 }
4914
4915 static int nv_get_sset_count(struct net_device *dev, int sset)
4916 {
4917         struct fe_priv *np = netdev_priv(dev);
4918
4919         switch (sset) {
4920         case ETH_SS_TEST:
4921                 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4922                         return NV_TEST_COUNT_EXTENDED;
4923                 else
4924                         return NV_TEST_COUNT_BASE;
4925         case ETH_SS_STATS:
4926                 if (np->driver_data & DEV_HAS_STATISTICS_V3)
4927                         return NV_DEV_STATISTICS_V3_COUNT;
4928                 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4929                         return NV_DEV_STATISTICS_V2_COUNT;
4930                 else if (np->driver_data & DEV_HAS_STATISTICS_V1)
4931                         return NV_DEV_STATISTICS_V1_COUNT;
4932                 else
4933                         return 0;
4934         default:
4935                 return -EOPNOTSUPP;
4936         }
4937 }
4938
4939 static void nv_get_ethtool_stats(struct net_device *dev,
4940                                  struct ethtool_stats *estats, u64 *buffer)
4941         __acquires(&netdev_priv(dev)->hwstats_lock)
4942         __releases(&netdev_priv(dev)->hwstats_lock)
4943 {
4944         struct fe_priv *np = netdev_priv(dev);
4945
4946         spin_lock_bh(&np->hwstats_lock);
4947         nv_update_stats(dev);
4948         memcpy(buffer, &np->estats,
4949                nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
4950         spin_unlock_bh(&np->hwstats_lock);
4951 }
4952
4953 static int nv_link_test(struct net_device *dev)
4954 {
4955         struct fe_priv *np = netdev_priv(dev);
4956         int mii_status;
4957
4958         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4959         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4960
4961         /* check phy link status */
4962         if (!(mii_status & BMSR_LSTATUS))
4963                 return 0;
4964         else
4965                 return 1;
4966 }
4967
4968 static int nv_register_test(struct net_device *dev)
4969 {
4970         u8 __iomem *base = get_hwbase(dev);
4971         int i = 0;
4972         u32 orig_read, new_read;
4973
4974         do {
4975                 orig_read = readl(base + nv_registers_test[i].reg);
4976
4977                 /* xor with mask to toggle bits */
4978                 orig_read ^= nv_registers_test[i].mask;
4979
4980                 writel(orig_read, base + nv_registers_test[i].reg);
4981
4982                 new_read = readl(base + nv_registers_test[i].reg);
4983
4984                 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4985                         return 0;
4986
4987                 /* restore original value */
4988                 orig_read ^= nv_registers_test[i].mask;
4989                 writel(orig_read, base + nv_registers_test[i].reg);
4990
4991         } while (nv_registers_test[++i].reg != 0);
4992
4993         return 1;
4994 }
4995
4996 static int nv_interrupt_test(struct net_device *dev)
4997 {
4998         struct fe_priv *np = netdev_priv(dev);
4999         u8 __iomem *base = get_hwbase(dev);
5000         int ret = 1;
5001         int testcnt;
5002         u32 save_msi_flags, save_poll_interval = 0;
5003
5004         if (netif_running(dev)) {
5005                 /* free current irq */
5006                 nv_free_irq(dev);
5007                 save_poll_interval = readl(base+NvRegPollingInterval);
5008         }
5009
5010         /* flag to test interrupt handler */
5011         np->intr_test = 0;
5012
5013         /* setup test irq */
5014         save_msi_flags = np->msi_flags;
5015         np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
5016         np->msi_flags |= 0x001; /* setup 1 vector */
5017         if (nv_request_irq(dev, 1))
5018                 return 0;
5019
5020         /* setup timer interrupt */
5021         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5022         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5023
5024         nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
5025
5026         /* wait for at least one interrupt */
5027         msleep(100);
5028
5029         spin_lock_irq(&np->lock);
5030
5031         /* flag should be set within ISR */
5032         testcnt = np->intr_test;
5033         if (!testcnt)
5034                 ret = 2;
5035
5036         nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
5037         if (!(np->msi_flags & NV_MSI_X_ENABLED))
5038                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5039         else
5040                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
5041
5042         spin_unlock_irq(&np->lock);
5043
5044         nv_free_irq(dev);
5045
5046         np->msi_flags = save_msi_flags;
5047
5048         if (netif_running(dev)) {
5049                 writel(save_poll_interval, base + NvRegPollingInterval);
5050                 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5051                 /* restore original irq */
5052                 if (nv_request_irq(dev, 0))
5053                         return 0;
5054         }
5055
5056         return ret;
5057 }
5058
5059 static int nv_loopback_test(struct net_device *dev)
5060 {
5061         struct fe_priv *np = netdev_priv(dev);
5062         u8 __iomem *base = get_hwbase(dev);
5063         struct sk_buff *tx_skb, *rx_skb;
5064         dma_addr_t test_dma_addr;
5065         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
5066         u32 flags;
5067         int len, i, pkt_len;
5068         u8 *pkt_data;
5069         u32 filter_flags = 0;
5070         u32 misc1_flags = 0;
5071         int ret = 1;
5072
5073         if (netif_running(dev)) {
5074                 nv_disable_irq(dev);
5075                 filter_flags = readl(base + NvRegPacketFilterFlags);
5076                 misc1_flags = readl(base + NvRegMisc1);
5077         } else {
5078                 nv_txrx_reset(dev);
5079         }
5080
5081         /* reinit driver view of the rx queue */
5082         set_bufsize(dev);
5083         nv_init_ring(dev);
5084
5085         /* setup hardware for loopback */
5086         writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
5087         writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
5088
5089         /* reinit nic view of the rx queue */
5090         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5091         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5092         writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5093                 base + NvRegRingSizes);
5094         pci_push(base);
5095
5096         /* restart rx engine */
5097         nv_start_rxtx(dev);
5098
5099         /* setup packet for tx */
5100         pkt_len = ETH_DATA_LEN;
5101         tx_skb = netdev_alloc_skb(dev, pkt_len);
5102         if (!tx_skb) {
5103                 ret = 0;
5104                 goto out;
5105         }
5106         test_dma_addr = dma_map_single(&np->pci_dev->dev, tx_skb->data,
5107                                        skb_tailroom(tx_skb),
5108                                        DMA_FROM_DEVICE);
5109         if (unlikely(dma_mapping_error(&np->pci_dev->dev,
5110                                        test_dma_addr))) {
5111                 dev_kfree_skb_any(tx_skb);
5112                 goto out;
5113         }
5114         pkt_data = skb_put(tx_skb, pkt_len);
5115         for (i = 0; i < pkt_len; i++)
5116                 pkt_data[i] = (u8)(i & 0xff);
5117
5118         if (!nv_optimized(np)) {
5119                 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
5120                 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
5121         } else {
5122                 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
5123                 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
5124                 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
5125         }
5126         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5127         pci_push(get_hwbase(dev));
5128
5129         msleep(500);
5130
5131         /* check for rx of the packet */
5132         if (!nv_optimized(np)) {
5133                 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
5134                 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
5135
5136         } else {
5137                 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
5138                 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
5139         }
5140
5141         if (flags & NV_RX_AVAIL) {
5142                 ret = 0;
5143         } else if (np->desc_ver == DESC_VER_1) {
5144                 if (flags & NV_RX_ERROR)
5145                         ret = 0;
5146         } else {
5147                 if (flags & NV_RX2_ERROR)
5148                         ret = 0;
5149         }
5150
5151         if (ret) {
5152                 if (len != pkt_len) {
5153                         ret = 0;
5154                 } else {
5155                         rx_skb = np->rx_skb[0].skb;
5156                         for (i = 0; i < pkt_len; i++) {
5157                                 if (rx_skb->data[i] != (u8)(i & 0xff)) {
5158                                         ret = 0;
5159                                         break;
5160                                 }
5161                         }
5162                 }
5163         }
5164
5165         dma_unmap_single(&np->pci_dev->dev, test_dma_addr,
5166                          (skb_end_pointer(tx_skb) - tx_skb->data),
5167                          DMA_TO_DEVICE);
5168         dev_kfree_skb_any(tx_skb);
5169  out:
5170         /* stop engines */
5171         nv_stop_rxtx(dev);
5172         nv_txrx_reset(dev);
5173         /* drain rx queue */
5174         nv_drain_rxtx(dev);
5175
5176         if (netif_running(dev)) {
5177                 writel(misc1_flags, base + NvRegMisc1);
5178                 writel(filter_flags, base + NvRegPacketFilterFlags);
5179                 nv_enable_irq(dev);
5180         }
5181
5182         return ret;
5183 }
5184
5185 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
5186 {
5187         struct fe_priv *np = netdev_priv(dev);
5188         u8 __iomem *base = get_hwbase(dev);
5189         int result, count;
5190
5191         count = nv_get_sset_count(dev, ETH_SS_TEST);
5192         memset(buffer, 0, count * sizeof(u64));
5193
5194         if (!nv_link_test(dev)) {
5195                 test->flags |= ETH_TEST_FL_FAILED;
5196                 buffer[0] = 1;
5197         }
5198
5199         if (test->flags & ETH_TEST_FL_OFFLINE) {
5200                 if (netif_running(dev)) {
5201                         netif_stop_queue(dev);
5202                         nv_napi_disable(dev);
5203                         netif_tx_lock_bh(dev);
5204                         netif_addr_lock(dev);
5205                         spin_lock_irq(&np->lock);
5206                         nv_disable_hw_interrupts(dev, np->irqmask);
5207                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
5208                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5209                         else
5210                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
5211                         /* stop engines */
5212                         nv_stop_rxtx(dev);
5213                         nv_txrx_reset(dev);
5214                         /* drain rx queue */
5215                         nv_drain_rxtx(dev);
5216                         spin_unlock_irq(&np->lock);
5217                         netif_addr_unlock(dev);
5218                         netif_tx_unlock_bh(dev);
5219                 }
5220
5221                 if (!nv_register_test(dev)) {
5222                         test->flags |= ETH_TEST_FL_FAILED;
5223                         buffer[1] = 1;
5224                 }
5225
5226                 result = nv_interrupt_test(dev);
5227                 if (result != 1) {
5228                         test->flags |= ETH_TEST_FL_FAILED;
5229                         buffer[2] = 1;
5230                 }
5231                 if (result == 0) {
5232                         /* bail out */
5233                         return;
5234                 }
5235
5236                 if (count > NV_TEST_COUNT_BASE && !nv_loopback_test(dev)) {
5237                         test->flags |= ETH_TEST_FL_FAILED;
5238                         buffer[3] = 1;
5239                 }
5240
5241                 if (netif_running(dev)) {
5242                         /* reinit driver view of the rx queue */
5243                         set_bufsize(dev);
5244                         if (nv_init_ring(dev)) {
5245                                 if (!np->in_shutdown)
5246                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5247                         }
5248                         /* reinit nic view of the rx queue */
5249                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5250                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5251                         writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5252                                 base + NvRegRingSizes);
5253                         pci_push(base);
5254                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5255                         pci_push(base);
5256                         /* restart rx engine */
5257                         nv_start_rxtx(dev);
5258                         netif_start_queue(dev);
5259                         nv_napi_enable(dev);
5260                         nv_enable_hw_interrupts(dev, np->irqmask);
5261                 }
5262         }
5263 }
5264
5265 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
5266 {
5267         switch (stringset) {
5268         case ETH_SS_STATS:
5269                 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
5270                 break;
5271         case ETH_SS_TEST:
5272                 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
5273                 break;
5274         }
5275 }
5276
5277 static const struct ethtool_ops ops = {
5278         .get_drvinfo = nv_get_drvinfo,
5279         .get_link = ethtool_op_get_link,
5280         .get_wol = nv_get_wol,
5281         .set_wol = nv_set_wol,
5282         .get_regs_len = nv_get_regs_len,
5283         .get_regs = nv_get_regs,
5284         .nway_reset = nv_nway_reset,
5285         .get_ringparam = nv_get_ringparam,
5286         .set_ringparam = nv_set_ringparam,
5287         .get_pauseparam = nv_get_pauseparam,
5288         .set_pauseparam = nv_set_pauseparam,
5289         .get_strings = nv_get_strings,
5290         .get_ethtool_stats = nv_get_ethtool_stats,
5291         .get_sset_count = nv_get_sset_count,
5292         .self_test = nv_self_test,
5293         .get_ts_info = ethtool_op_get_ts_info,
5294         .get_link_ksettings = nv_get_link_ksettings,
5295         .set_link_ksettings = nv_set_link_ksettings,
5296 };
5297
5298 /* The mgmt unit and driver use a semaphore to access the phy during init */
5299 static int nv_mgmt_acquire_sema(struct net_device *dev)
5300 {
5301         struct fe_priv *np = netdev_priv(dev);
5302         u8 __iomem *base = get_hwbase(dev);
5303         int i;
5304         u32 tx_ctrl, mgmt_sema;
5305
5306         for (i = 0; i < 10; i++) {
5307                 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
5308                 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
5309                         break;
5310                 msleep(500);
5311         }
5312
5313         if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
5314                 return 0;
5315
5316         for (i = 0; i < 2; i++) {
5317                 tx_ctrl = readl(base + NvRegTransmitterControl);
5318                 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
5319                 writel(tx_ctrl, base + NvRegTransmitterControl);
5320
5321                 /* verify that semaphore was acquired */
5322                 tx_ctrl = readl(base + NvRegTransmitterControl);
5323                 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
5324                     ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
5325                         np->mgmt_sema = 1;
5326                         return 1;
5327                 } else
5328                         udelay(50);
5329         }
5330
5331         return 0;
5332 }
5333
5334 static void nv_mgmt_release_sema(struct net_device *dev)
5335 {
5336         struct fe_priv *np = netdev_priv(dev);
5337         u8 __iomem *base = get_hwbase(dev);
5338         u32 tx_ctrl;
5339
5340         if (np->driver_data & DEV_HAS_MGMT_UNIT) {
5341                 if (np->mgmt_sema) {
5342                         tx_ctrl = readl(base + NvRegTransmitterControl);
5343                         tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
5344                         writel(tx_ctrl, base + NvRegTransmitterControl);
5345                 }
5346         }
5347 }
5348
5349
5350 static int nv_mgmt_get_version(struct net_device *dev)
5351 {
5352         struct fe_priv *np = netdev_priv(dev);
5353         u8 __iomem *base = get_hwbase(dev);
5354         u32 data_ready = readl(base + NvRegTransmitterControl);
5355         u32 data_ready2 = 0;
5356         unsigned long start;
5357         int ready = 0;
5358
5359         writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
5360         writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
5361         start = jiffies;
5362         while (time_before(jiffies, start + 5*HZ)) {
5363                 data_ready2 = readl(base + NvRegTransmitterControl);
5364                 if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) {
5365                         ready = 1;
5366                         break;
5367                 }
5368                 schedule_timeout_uninterruptible(1);
5369         }
5370
5371         if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR))
5372                 return 0;
5373
5374         np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;
5375
5376         return 1;
5377 }
5378
5379 static int nv_open(struct net_device *dev)
5380 {
5381         struct fe_priv *np = netdev_priv(dev);
5382         u8 __iomem *base = get_hwbase(dev);
5383         int ret = 1;
5384         int oom, i;
5385         u32 low;
5386
5387         /* power up phy */
5388         mii_rw(dev, np->phyaddr, MII_BMCR,
5389                mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
5390
5391         nv_txrx_gate(dev, false);
5392         /* erase previous misconfiguration */
5393         if (np->driver_data & DEV_HAS_POWER_CNTRL)
5394                 nv_mac_reset(dev);
5395         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5396         writel(0, base + NvRegMulticastAddrB);
5397         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5398         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5399         writel(0, base + NvRegPacketFilterFlags);
5400
5401         writel(0, base + NvRegTransmitterControl);
5402         writel(0, base + NvRegReceiverControl);
5403
5404         writel(0, base + NvRegAdapterControl);
5405
5406         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5407                 writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
5408
5409         /* initialize descriptor rings */
5410         set_bufsize(dev);
5411         oom = nv_init_ring(dev);
5412
5413         writel(0, base + NvRegLinkSpeed);
5414         writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5415         nv_txrx_reset(dev);
5416         writel(0, base + NvRegUnknownSetupReg6);
5417
5418         np->in_shutdown = 0;
5419
5420         /* give hw rings */
5421         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5422         writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5423                 base + NvRegRingSizes);
5424
5425         writel(np->linkspeed, base + NvRegLinkSpeed);
5426         if (np->desc_ver == DESC_VER_1)
5427                 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5428         else
5429                 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
5430         writel(np->txrxctl_bits, base + NvRegTxRxControl);
5431         writel(np->vlanctl_bits, base + NvRegVlanControl);
5432         pci_push(base);
5433         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
5434         if (reg_delay(dev, NvRegUnknownSetupReg5,
5435                       NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5436                       NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX))
5437                 netdev_info(dev,
5438                             "%s: SetupReg5, Bit 31 remained off\n", __func__);
5439
5440         writel(0, base + NvRegMIIMask);
5441         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5442         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5443
5444         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5445         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5446         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
5447         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5448
5449         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
5450
5451         get_random_bytes(&low, sizeof(low));
5452         low &= NVREG_SLOTTIME_MASK;
5453         if (np->desc_ver == DESC_VER_1) {
5454                 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5455         } else {
5456                 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5457                         /* setup legacy backoff */
5458                         writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5459                 } else {
5460                         writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5461                         nv_gear_backoff_reseed(dev);
5462                 }
5463         }
5464         writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5465         writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
5466         if (poll_interval == -1) {
5467                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5468                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5469                 else
5470                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5471         } else
5472                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5473         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5474         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5475                         base + NvRegAdapterControl);
5476         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
5477         writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
5478         if (np->wolenabled)
5479                 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5480
5481         i = readl(base + NvRegPowerState);
5482         if ((i & NVREG_POWERSTATE_POWEREDUP) == 0)
5483                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5484
5485         pci_push(base);
5486         udelay(10);
5487         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5488
5489         nv_disable_hw_interrupts(dev, np->irqmask);
5490         pci_push(base);
5491         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5492         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5493         pci_push(base);
5494
5495         if (nv_request_irq(dev, 0))
5496                 goto out_drain;
5497
5498         /* ask for interrupts */
5499         nv_enable_hw_interrupts(dev, np->irqmask);
5500
5501         spin_lock_irq(&np->lock);
5502         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5503         writel(0, base + NvRegMulticastAddrB);
5504         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5505         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5506         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5507         /* One manual link speed update: Interrupts are enabled, future link
5508          * speed changes cause interrupts and are handled by nv_link_irq().
5509          */
5510         {
5511                 u32 miistat;
5512                 miistat = readl(base + NvRegMIIStatus);
5513                 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5514         }
5515         /* set linkspeed to invalid value, thus force nv_update_linkspeed
5516          * to init hw */
5517         np->linkspeed = 0;
5518         ret = nv_update_linkspeed(dev);
5519         nv_start_rxtx(dev);
5520         netif_start_queue(dev);
5521         nv_napi_enable(dev);
5522
5523         if (ret) {
5524                 netif_carrier_on(dev);
5525         } else {
5526                 netdev_info(dev, "no link during initialization\n");
5527                 netif_carrier_off(dev);
5528         }
5529         if (oom)
5530                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5531
5532         /* start statistics timer */
5533         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5534                 mod_timer(&np->stats_poll,
5535                         round_jiffies(jiffies + STATS_INTERVAL));
5536
5537         spin_unlock_irq(&np->lock);
5538
5539         /* If the loopback feature was set while the device was down, make sure
5540          * that it's set correctly now.
5541          */
5542         if (dev->features & NETIF_F_LOOPBACK)
5543                 nv_set_loopback(dev, dev->features);
5544
5545         return 0;
5546 out_drain:
5547         nv_drain_rxtx(dev);
5548         return ret;
5549 }
5550
5551 static int nv_close(struct net_device *dev)
5552 {
5553         struct fe_priv *np = netdev_priv(dev);
5554         u8 __iomem *base;
5555
5556         spin_lock_irq(&np->lock);
5557         np->in_shutdown = 1;
5558         spin_unlock_irq(&np->lock);
5559         nv_napi_disable(dev);
5560         synchronize_irq(np->pci_dev->irq);
5561
5562         del_timer_sync(&np->oom_kick);
5563         del_timer_sync(&np->nic_poll);
5564         del_timer_sync(&np->stats_poll);
5565
5566         netif_stop_queue(dev);
5567         spin_lock_irq(&np->lock);
5568         nv_update_pause(dev, 0); /* otherwise stop_tx bricks NIC */
5569         nv_stop_rxtx(dev);
5570         nv_txrx_reset(dev);
5571
5572         /* disable interrupts on the nic or we will lock up */
5573         base = get_hwbase(dev);
5574         nv_disable_hw_interrupts(dev, np->irqmask);
5575         pci_push(base);
5576
5577         spin_unlock_irq(&np->lock);
5578
5579         nv_free_irq(dev);
5580
5581         nv_drain_rxtx(dev);
5582
5583         if (np->wolenabled || !phy_power_down) {
5584                 nv_txrx_gate(dev, false);
5585                 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5586                 nv_start_rx(dev);
5587         } else {
5588                 /* power down phy */
5589                 mii_rw(dev, np->phyaddr, MII_BMCR,
5590                        mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
5591                 nv_txrx_gate(dev, true);
5592         }
5593
5594         /* FIXME: power down nic */
5595
5596         return 0;
5597 }
5598
5599 static const struct net_device_ops nv_netdev_ops = {
5600         .ndo_open               = nv_open,
5601         .ndo_stop               = nv_close,
5602         .ndo_get_stats64        = nv_get_stats64,
5603         .ndo_start_xmit         = nv_start_xmit,
5604         .ndo_tx_timeout         = nv_tx_timeout,
5605         .ndo_change_mtu         = nv_change_mtu,
5606         .ndo_fix_features       = nv_fix_features,
5607         .ndo_set_features       = nv_set_features,
5608         .ndo_validate_addr      = eth_validate_addr,
5609         .ndo_set_mac_address    = nv_set_mac_address,
5610         .ndo_set_rx_mode        = nv_set_multicast,
5611 #ifdef CONFIG_NET_POLL_CONTROLLER
5612         .ndo_poll_controller    = nv_poll_controller,
5613 #endif
5614 };
5615
5616 static const struct net_device_ops nv_netdev_ops_optimized = {
5617         .ndo_open               = nv_open,
5618         .ndo_stop               = nv_close,
5619         .ndo_get_stats64        = nv_get_stats64,
5620         .ndo_start_xmit         = nv_start_xmit_optimized,
5621         .ndo_tx_timeout         = nv_tx_timeout,
5622         .ndo_change_mtu         = nv_change_mtu,
5623         .ndo_fix_features       = nv_fix_features,
5624         .ndo_set_features       = nv_set_features,
5625         .ndo_validate_addr      = eth_validate_addr,
5626         .ndo_set_mac_address    = nv_set_mac_address,
5627         .ndo_set_rx_mode        = nv_set_multicast,
5628 #ifdef CONFIG_NET_POLL_CONTROLLER
5629         .ndo_poll_controller    = nv_poll_controller,
5630 #endif
5631 };
5632
5633 static int nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5634 {
5635         struct net_device *dev;
5636         struct fe_priv *np;
5637         unsigned long addr;
5638         u8 __iomem *base;
5639         int err, i;
5640         u32 powerstate, txreg;
5641         u32 phystate_orig = 0, phystate;
5642         int phyinitialized = 0;
5643         static int printed_version;
5644
5645         if (!printed_version++)
5646                 pr_info("Reverse Engineered nForce ethernet driver. Version %s.\n",
5647                         FORCEDETH_VERSION);
5648
5649         dev = alloc_etherdev(sizeof(struct fe_priv));
5650         err = -ENOMEM;
5651         if (!dev)
5652                 goto out;
5653
5654         np = netdev_priv(dev);
5655         np->dev = dev;
5656         np->pci_dev = pci_dev;
5657         spin_lock_init(&np->lock);
5658         spin_lock_init(&np->hwstats_lock);
5659         SET_NETDEV_DEV(dev, &pci_dev->dev);
5660         u64_stats_init(&np->swstats_rx_syncp);
5661         u64_stats_init(&np->swstats_tx_syncp);
5662
5663         timer_setup(&np->oom_kick, nv_do_rx_refill, 0);
5664         timer_setup(&np->nic_poll, nv_do_nic_poll, 0);
5665         timer_setup(&np->stats_poll, nv_do_stats_poll, TIMER_DEFERRABLE);
5666
5667         err = pci_enable_device(pci_dev);
5668         if (err)
5669                 goto out_free;
5670
5671         pci_set_master(pci_dev);
5672
5673         err = pci_request_regions(pci_dev, DRV_NAME);
5674         if (err < 0)
5675                 goto out_disable;
5676
5677         if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5678                 np->register_size = NV_PCI_REGSZ_VER3;
5679         else if (id->driver_data & DEV_HAS_STATISTICS_V1)
5680                 np->register_size = NV_PCI_REGSZ_VER2;
5681         else
5682                 np->register_size = NV_PCI_REGSZ_VER1;
5683
5684         err = -EINVAL;
5685         addr = 0;
5686         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5687                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
5688                                 pci_resource_len(pci_dev, i) >= np->register_size) {
5689                         addr = pci_resource_start(pci_dev, i);
5690                         break;
5691                 }
5692         }
5693         if (i == DEVICE_COUNT_RESOURCE) {
5694                 dev_info(&pci_dev->dev, "Couldn't find register window\n");
5695                 goto out_relreg;
5696         }
5697
5698         /* copy of driver data */
5699         np->driver_data = id->driver_data;
5700         /* copy of device id */
5701         np->device_id = id->device;
5702
5703         /* handle different descriptor versions */
5704         if (id->driver_data & DEV_HAS_HIGH_DMA) {
5705                 /* packet format 3: supports 40-bit addressing */
5706                 np->desc_ver = DESC_VER_3;
5707                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
5708                 if (dma_64bit) {
5709                         if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39)))
5710                                 dev_info(&pci_dev->dev,
5711                                          "64-bit DMA failed, using 32-bit addressing\n");
5712                         else
5713                                 dev->features |= NETIF_F_HIGHDMA;
5714                         if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) {
5715                                 dev_info(&pci_dev->dev,
5716                                          "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5717                         }
5718                 }
5719         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5720                 /* packet format 2: supports jumbo frames */
5721                 np->desc_ver = DESC_VER_2;
5722                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
5723         } else {
5724                 /* original packet format */
5725                 np->desc_ver = DESC_VER_1;
5726                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
5727         }
5728
5729         np->pkt_limit = NV_PKTLIMIT_1;
5730         if (id->driver_data & DEV_HAS_LARGEDESC)
5731                 np->pkt_limit = NV_PKTLIMIT_2;
5732
5733         if (id->driver_data & DEV_HAS_CHECKSUM) {
5734                 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
5735                 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG |
5736                         NETIF_F_TSO | NETIF_F_RXCSUM;
5737         }
5738
5739         np->vlanctl_bits = 0;
5740         if (id->driver_data & DEV_HAS_VLAN) {
5741                 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5742                 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX |
5743                                     NETIF_F_HW_VLAN_CTAG_TX;
5744         }
5745
5746         dev->features |= dev->hw_features;
5747
5748         /* Add loopback capability to the device. */
5749         dev->hw_features |= NETIF_F_LOOPBACK;
5750
5751         /* MTU range: 64 - 1500 or 9100 */
5752         dev->min_mtu = ETH_ZLEN + ETH_FCS_LEN;
5753         dev->max_mtu = np->pkt_limit;
5754
5755         np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
5756         if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5757             (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5758             (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
5759                 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
5760         }
5761
5762         err = -ENOMEM;
5763         np->base = ioremap(addr, np->register_size);
5764         if (!np->base)
5765                 goto out_relreg;
5766
5767         np->rx_ring_size = RX_RING_DEFAULT;
5768         np->tx_ring_size = TX_RING_DEFAULT;
5769
5770         if (!nv_optimized(np)) {
5771                 np->rx_ring.orig = dma_alloc_coherent(&pci_dev->dev,
5772                                                       sizeof(struct ring_desc) *
5773                                                       (np->rx_ring_size +
5774                                                       np->tx_ring_size),
5775                                                       &np->ring_addr,
5776                                                       GFP_ATOMIC);
5777                 if (!np->rx_ring.orig)
5778                         goto out_unmap;
5779                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
5780         } else {
5781                 np->rx_ring.ex = dma_alloc_coherent(&pci_dev->dev,
5782                                                     sizeof(struct ring_desc_ex) *
5783                                                     (np->rx_ring_size +
5784                                                     np->tx_ring_size),
5785                                                     &np->ring_addr, GFP_ATOMIC);
5786                 if (!np->rx_ring.ex)
5787                         goto out_unmap;
5788                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
5789         }
5790         np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5791         np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5792         if (!np->rx_skb || !np->tx_skb)
5793                 goto out_freering;
5794
5795         if (!nv_optimized(np))
5796                 dev->netdev_ops = &nv_netdev_ops;
5797         else
5798                 dev->netdev_ops = &nv_netdev_ops_optimized;
5799
5800         netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
5801         dev->ethtool_ops = &ops;
5802         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5803
5804         pci_set_drvdata(pci_dev, dev);
5805
5806         /* read the mac address */
5807         base = get_hwbase(dev);
5808         np->orig_mac[0] = readl(base + NvRegMacAddrA);
5809         np->orig_mac[1] = readl(base + NvRegMacAddrB);
5810
5811         /* check the workaround bit for correct mac address order */
5812         txreg = readl(base + NvRegTransmitPoll);
5813         if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
5814                 /* mac address is already in correct order */
5815                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5816                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5817                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5818                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5819                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5820                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5821         } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5822                 /* mac address is already in correct order */
5823                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5824                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5825                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5826                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5827                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5828                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5829                 /*
5830                  * Set orig mac address back to the reversed version.
5831                  * This flag will be cleared during low power transition.
5832                  * Therefore, we should always put back the reversed address.
5833                  */
5834                 np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
5835                         (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
5836                 np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
5837         } else {
5838                 /* need to reverse mac address to correct order */
5839                 dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
5840                 dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
5841                 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5842                 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5843                 dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
5844                 dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
5845                 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5846                 dev_dbg(&pci_dev->dev,
5847                         "%s: set workaround bit for reversed mac addr\n",
5848                         __func__);
5849         }
5850
5851         if (!is_valid_ether_addr(dev->dev_addr)) {
5852                 /*
5853                  * Bad mac address. At least one bios sets the mac address
5854                  * to 01:23:45:67:89:ab
5855                  */
5856                 dev_err(&pci_dev->dev,
5857                         "Invalid MAC address detected: %pM - Please complain to your hardware vendor.\n",
5858                         dev->dev_addr);
5859                 eth_hw_addr_random(dev);
5860                 dev_err(&pci_dev->dev,
5861                         "Using random MAC address: %pM\n", dev->dev_addr);
5862         }
5863
5864         /* set mac address */
5865         nv_copy_mac_to_hw(dev);
5866
5867         /* disable WOL */
5868         writel(0, base + NvRegWakeUpFlags);
5869         np->wolenabled = 0;
5870         device_set_wakeup_enable(&pci_dev->dev, false);
5871
5872         if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5873
5874                 /* take phy and nic out of low power mode */
5875                 powerstate = readl(base + NvRegPowerState2);
5876                 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5877                 if ((id->driver_data & DEV_NEED_LOW_POWER_FIX) &&
5878                     pci_dev->revision >= 0xA3)
5879                         powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5880                 writel(powerstate, base + NvRegPowerState2);
5881         }
5882
5883         if (np->desc_ver == DESC_VER_1)
5884                 np->tx_flags = NV_TX_VALID;
5885         else
5886                 np->tx_flags = NV_TX2_VALID;
5887
5888         np->msi_flags = 0;
5889         if ((id->driver_data & DEV_HAS_MSI) && msi)
5890                 np->msi_flags |= NV_MSI_CAPABLE;
5891
5892         if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5893                 /* msix has had reported issues when modifying irqmask
5894                    as in the case of napi, therefore, disable for now
5895                 */
5896 #if 0
5897                 np->msi_flags |= NV_MSI_X_CAPABLE;
5898 #endif
5899         }
5900
5901         if (optimization_mode == NV_OPTIMIZATION_MODE_CPU) {
5902                 np->irqmask = NVREG_IRQMASK_CPU;
5903                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5904                         np->msi_flags |= 0x0001;
5905         } else if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC &&
5906                    !(id->driver_data & DEV_NEED_TIMERIRQ)) {
5907                 /* start off in throughput mode */
5908                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5909                 /* remove support for msix mode */
5910                 np->msi_flags &= ~NV_MSI_X_CAPABLE;
5911         } else {
5912                 optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
5913                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5914                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5915                         np->msi_flags |= 0x0003;
5916         }
5917
5918         if (id->driver_data & DEV_NEED_TIMERIRQ)
5919                 np->irqmask |= NVREG_IRQ_TIMER;
5920         if (id->driver_data & DEV_NEED_LINKTIMER) {
5921                 np->need_linktimer = 1;
5922                 np->link_timeout = jiffies + LINK_TIMEOUT;
5923         } else {
5924                 np->need_linktimer = 0;
5925         }
5926
5927         /* Limit the number of tx's outstanding for hw bug */
5928         if (id->driver_data & DEV_NEED_TX_LIMIT) {
5929                 np->tx_limit = 1;
5930                 if (((id->driver_data & DEV_NEED_TX_LIMIT2) == DEV_NEED_TX_LIMIT2) &&
5931                     pci_dev->revision >= 0xA2)
5932                         np->tx_limit = 0;
5933         }
5934
5935         /* clear phy state and temporarily halt phy interrupts */
5936         writel(0, base + NvRegMIIMask);
5937         phystate = readl(base + NvRegAdapterControl);
5938         if (phystate & NVREG_ADAPTCTL_RUNNING) {
5939                 phystate_orig = 1;
5940                 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5941                 writel(phystate, base + NvRegAdapterControl);
5942         }
5943         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5944
5945         if (id->driver_data & DEV_HAS_MGMT_UNIT) {
5946                 /* management unit running on the mac? */
5947                 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) &&
5948                     (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) &&
5949                     nv_mgmt_acquire_sema(dev) &&
5950                     nv_mgmt_get_version(dev)) {
5951                         np->mac_in_use = 1;
5952                         if (np->mgmt_version > 0)
5953                                 np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE;
5954                         /* management unit setup the phy already? */
5955                         if (np->mac_in_use &&
5956                             ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5957                              NVREG_XMITCTL_SYNC_PHY_INIT)) {
5958                                 /* phy is inited by mgmt unit */
5959                                 phyinitialized = 1;
5960                         } else {
5961                                 /* we need to init the phy */
5962                         }
5963                 }
5964         }
5965
5966         /* find a suitable phy */
5967         for (i = 1; i <= 32; i++) {
5968                 int id1, id2;
5969                 int phyaddr = i & 0x1F;
5970
5971                 spin_lock_irq(&np->lock);
5972                 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5973                 spin_unlock_irq(&np->lock);
5974                 if (id1 < 0 || id1 == 0xffff)
5975                         continue;
5976                 spin_lock_irq(&np->lock);
5977                 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5978                 spin_unlock_irq(&np->lock);
5979                 if (id2 < 0 || id2 == 0xffff)
5980                         continue;
5981
5982                 np->phy_model = id2 & PHYID2_MODEL_MASK;
5983                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5984                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5985                 np->phyaddr = phyaddr;
5986                 np->phy_oui = id1 | id2;
5987
5988                 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5989                 if (np->phy_oui == PHY_OUI_REALTEK2)
5990                         np->phy_oui = PHY_OUI_REALTEK;
5991                 /* Setup phy revision for Realtek */
5992                 if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211)
5993                         np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
5994
5995                 break;
5996         }
5997         if (i == 33) {
5998                 dev_info(&pci_dev->dev, "open: Could not find a valid PHY\n");
5999                 goto out_error;
6000         }
6001
6002         if (!phyinitialized) {
6003                 /* reset it */
6004                 phy_init(dev);
6005         } else {
6006                 /* see if it is a gigabit phy */
6007                 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
6008                 if (mii_status & PHY_GIGABIT)
6009                         np->gigabit = PHY_GIGABIT;
6010         }
6011
6012         /* set default link speed settings */
6013         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
6014         np->duplex = 0;
6015         np->autoneg = 1;
6016
6017         err = register_netdev(dev);
6018         if (err) {
6019                 dev_info(&pci_dev->dev, "unable to register netdev: %d\n", err);
6020                 goto out_error;
6021         }
6022
6023         netif_carrier_off(dev);
6024
6025         /* Some NICs freeze when TX pause is enabled while NIC is
6026          * down, and this stays across warm reboots. The sequence
6027          * below should be enough to recover from that state.
6028          */
6029         nv_update_pause(dev, 0);
6030         nv_start_tx(dev);
6031         nv_stop_tx(dev);
6032
6033         if (id->driver_data & DEV_HAS_VLAN)
6034                 nv_vlan_mode(dev, dev->features);
6035
6036         dev_info(&pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, addr %pM\n",
6037                  dev->name, np->phy_oui, np->phyaddr, dev->dev_addr);
6038
6039         dev_info(&pci_dev->dev, "%s%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
6040                  dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
6041                  dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ?
6042                         "csum " : "",
6043                  dev->features & (NETIF_F_HW_VLAN_CTAG_RX |
6044                                   NETIF_F_HW_VLAN_CTAG_TX) ?
6045                         "vlan " : "",
6046                  dev->features & (NETIF_F_LOOPBACK) ?
6047                         "loopback " : "",
6048                  id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
6049                  id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
6050                  id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
6051                  np->gigabit == PHY_GIGABIT ? "gbit " : "",
6052                  np->need_linktimer ? "lnktim " : "",
6053                  np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
6054                  np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
6055                  np->desc_ver);
6056
6057         return 0;
6058
6059 out_error:
6060         if (phystate_orig)
6061                 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
6062 out_freering:
6063         free_rings(dev);
6064 out_unmap:
6065         iounmap(get_hwbase(dev));
6066 out_relreg:
6067         pci_release_regions(pci_dev);
6068 out_disable:
6069         pci_disable_device(pci_dev);
6070 out_free:
6071         free_netdev(dev);
6072 out:
6073         return err;
6074 }
6075
6076 static void nv_restore_phy(struct net_device *dev)
6077 {
6078         struct fe_priv *np = netdev_priv(dev);
6079         u16 phy_reserved, mii_control;
6080
6081         if (np->phy_oui == PHY_OUI_REALTEK &&
6082             np->phy_model == PHY_MODEL_REALTEK_8201 &&
6083             phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
6084                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
6085                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
6086                 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
6087                 phy_reserved |= PHY_REALTEK_INIT8;
6088                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
6089                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
6090
6091                 /* restart auto negotiation */
6092                 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
6093                 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
6094                 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);
6095         }
6096 }
6097
6098 static void nv_restore_mac_addr(struct pci_dev *pci_dev)
6099 {
6100         struct net_device *dev = pci_get_drvdata(pci_dev);
6101         struct fe_priv *np = netdev_priv(dev);
6102         u8 __iomem *base = get_hwbase(dev);
6103
6104         /* special op: write back the misordered MAC address - otherwise
6105          * the next nv_probe would see a wrong address.
6106          */
6107         writel(np->orig_mac[0], base + NvRegMacAddrA);
6108         writel(np->orig_mac[1], base + NvRegMacAddrB);
6109         writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
6110                base + NvRegTransmitPoll);
6111 }
6112
6113 static void nv_remove(struct pci_dev *pci_dev)
6114 {
6115         struct net_device *dev = pci_get_drvdata(pci_dev);
6116
6117         unregister_netdev(dev);
6118
6119         nv_restore_mac_addr(pci_dev);
6120
6121         /* restore any phy related changes */
6122         nv_restore_phy(dev);
6123
6124         nv_mgmt_release_sema(dev);
6125
6126         /* free all structures */
6127         free_rings(dev);
6128         iounmap(get_hwbase(dev));
6129         pci_release_regions(pci_dev);
6130         pci_disable_device(pci_dev);
6131         free_netdev(dev);
6132 }
6133
6134 #ifdef CONFIG_PM_SLEEP
6135 static int nv_suspend(struct device *device)
6136 {
6137         struct pci_dev *pdev = to_pci_dev(device);
6138         struct net_device *dev = pci_get_drvdata(pdev);
6139         struct fe_priv *np = netdev_priv(dev);
6140         u8 __iomem *base = get_hwbase(dev);
6141         int i;
6142
6143         if (netif_running(dev)) {
6144                 /* Gross. */
6145                 nv_close(dev);
6146         }
6147         netif_device_detach(dev);
6148
6149         /* save non-pci configuration space */
6150         for (i = 0; i <= np->register_size/sizeof(u32); i++)
6151                 np->saved_config_space[i] = readl(base + i*sizeof(u32));
6152
6153         return 0;
6154 }
6155
6156 static int nv_resume(struct device *device)
6157 {
6158         struct pci_dev *pdev = to_pci_dev(device);
6159         struct net_device *dev = pci_get_drvdata(pdev);
6160         struct fe_priv *np = netdev_priv(dev);
6161         u8 __iomem *base = get_hwbase(dev);
6162         int i, rc = 0;
6163
6164         /* restore non-pci configuration space */
6165         for (i = 0; i <= np->register_size/sizeof(u32); i++)
6166                 writel(np->saved_config_space[i], base+i*sizeof(u32));
6167
6168         if (np->driver_data & DEV_NEED_MSI_FIX)
6169                 pci_write_config_dword(pdev, NV_MSI_PRIV_OFFSET, NV_MSI_PRIV_VALUE);
6170
6171         /* restore phy state, including autoneg */
6172         phy_init(dev);
6173
6174         netif_device_attach(dev);
6175         if (netif_running(dev)) {
6176                 rc = nv_open(dev);
6177                 nv_set_multicast(dev);
6178         }
6179         return rc;
6180 }
6181
6182 static SIMPLE_DEV_PM_OPS(nv_pm_ops, nv_suspend, nv_resume);
6183 #define NV_PM_OPS (&nv_pm_ops)
6184
6185 #else
6186 #define NV_PM_OPS NULL
6187 #endif /* CONFIG_PM_SLEEP */
6188
6189 #ifdef CONFIG_PM
6190 static void nv_shutdown(struct pci_dev *pdev)
6191 {
6192         struct net_device *dev = pci_get_drvdata(pdev);
6193         struct fe_priv *np = netdev_priv(dev);
6194
6195         if (netif_running(dev))
6196                 nv_close(dev);
6197
6198         /*
6199          * Restore the MAC so a kernel started by kexec won't get confused.
6200          * If we really go for poweroff, we must not restore the MAC,
6201          * otherwise the MAC for WOL will be reversed at least on some boards.
6202          */
6203         if (system_state != SYSTEM_POWER_OFF)
6204                 nv_restore_mac_addr(pdev);
6205
6206         pci_disable_device(pdev);
6207         /*
6208          * Apparently it is not possible to reinitialise from D3 hot,
6209          * only put the device into D3 if we really go for poweroff.
6210          */
6211         if (system_state == SYSTEM_POWER_OFF) {
6212                 pci_wake_from_d3(pdev, np->wolenabled);
6213                 pci_set_power_state(pdev, PCI_D3hot);
6214         }
6215 }
6216 #else
6217 #define nv_shutdown NULL
6218 #endif /* CONFIG_PM */
6219
6220 static const struct pci_device_id pci_tbl[] = {
6221         {       /* nForce Ethernet Controller */
6222                 PCI_DEVICE(0x10DE, 0x01C3),
6223                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6224         },
6225         {       /* nForce2 Ethernet Controller */
6226                 PCI_DEVICE(0x10DE, 0x0066),
6227                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6228         },
6229         {       /* nForce3 Ethernet Controller */
6230                 PCI_DEVICE(0x10DE, 0x00D6),
6231                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6232         },
6233         {       /* nForce3 Ethernet Controller */
6234                 PCI_DEVICE(0x10DE, 0x0086),
6235                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6236         },
6237         {       /* nForce3 Ethernet Controller */
6238                 PCI_DEVICE(0x10DE, 0x008C),
6239                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6240         },
6241         {       /* nForce3 Ethernet Controller */
6242                 PCI_DEVICE(0x10DE, 0x00E6),
6243                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6244         },
6245         {       /* nForce3 Ethernet Controller */
6246                 PCI_DEVICE(0x10DE, 0x00DF),
6247                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6248         },
6249         {       /* CK804 Ethernet Controller */
6250                 PCI_DEVICE(0x10DE, 0x0056),
6251                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6252         },
6253         {       /* CK804 Ethernet Controller */
6254                 PCI_DEVICE(0x10DE, 0x0057),
6255                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6256         },
6257         {       /* MCP04 Ethernet Controller */
6258                 PCI_DEVICE(0x10DE, 0x0037),
6259                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6260         },
6261         {       /* MCP04 Ethernet Controller */
6262                 PCI_DEVICE(0x10DE, 0x0038),
6263                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6264         },
6265         {       /* MCP51 Ethernet Controller */
6266                 PCI_DEVICE(0x10DE, 0x0268),
6267                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
6268         },
6269         {       /* MCP51 Ethernet Controller */
6270                 PCI_DEVICE(0x10DE, 0x0269),
6271                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
6272         },
6273         {       /* MCP55 Ethernet Controller */
6274                 PCI_DEVICE(0x10DE, 0x0372),
6275                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
6276         },
6277         {       /* MCP55 Ethernet Controller */
6278                 PCI_DEVICE(0x10DE, 0x0373),
6279                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
6280         },
6281         {       /* MCP61 Ethernet Controller */
6282                 PCI_DEVICE(0x10DE, 0x03E5),
6283                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6284         },
6285         {       /* MCP61 Ethernet Controller */
6286                 PCI_DEVICE(0x10DE, 0x03E6),
6287                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6288         },
6289         {       /* MCP61 Ethernet Controller */
6290                 PCI_DEVICE(0x10DE, 0x03EE),
6291                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6292         },
6293         {       /* MCP61 Ethernet Controller */
6294                 PCI_DEVICE(0x10DE, 0x03EF),
6295                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6296         },
6297         {       /* MCP65 Ethernet Controller */
6298                 PCI_DEVICE(0x10DE, 0x0450),
6299                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6300         },
6301         {       /* MCP65 Ethernet Controller */
6302                 PCI_DEVICE(0x10DE, 0x0451),
6303                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6304         },
6305         {       /* MCP65 Ethernet Controller */
6306                 PCI_DEVICE(0x10DE, 0x0452),
6307                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6308         },
6309         {       /* MCP65 Ethernet Controller */
6310                 PCI_DEVICE(0x10DE, 0x0453),
6311                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6312         },
6313         {       /* MCP67 Ethernet Controller */
6314                 PCI_DEVICE(0x10DE, 0x054C),
6315                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6316         },
6317         {       /* MCP67 Ethernet Controller */
6318                 PCI_DEVICE(0x10DE, 0x054D),
6319                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6320         },
6321         {       /* MCP67 Ethernet Controller */
6322                 PCI_DEVICE(0x10DE, 0x054E),
6323                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6324         },
6325         {       /* MCP67 Ethernet Controller */
6326                 PCI_DEVICE(0x10DE, 0x054F),
6327                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6328         },
6329         {       /* MCP73 Ethernet Controller */
6330                 PCI_DEVICE(0x10DE, 0x07DC),
6331                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6332         },
6333         {       /* MCP73 Ethernet Controller */
6334                 PCI_DEVICE(0x10DE, 0x07DD),
6335                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6336         },
6337         {       /* MCP73 Ethernet Controller */
6338                 PCI_DEVICE(0x10DE, 0x07DE),
6339                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6340         },
6341         {       /* MCP73 Ethernet Controller */
6342                 PCI_DEVICE(0x10DE, 0x07DF),
6343                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6344         },
6345         {       /* MCP77 Ethernet Controller */
6346                 PCI_DEVICE(0x10DE, 0x0760),
6347                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6348         },
6349         {       /* MCP77 Ethernet Controller */
6350                 PCI_DEVICE(0x10DE, 0x0761),
6351                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6352         },
6353         {       /* MCP77 Ethernet Controller */
6354                 PCI_DEVICE(0x10DE, 0x0762),
6355                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6356         },
6357         {       /* MCP77 Ethernet Controller */
6358                 PCI_DEVICE(0x10DE, 0x0763),
6359                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6360         },
6361         {       /* MCP79 Ethernet Controller */
6362                 PCI_DEVICE(0x10DE, 0x0AB0),
6363                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6364         },
6365         {       /* MCP79 Ethernet Controller */
6366                 PCI_DEVICE(0x10DE, 0x0AB1),
6367                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6368         },
6369         {       /* MCP79 Ethernet Controller */
6370                 PCI_DEVICE(0x10DE, 0x0AB2),
6371                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6372         },
6373         {       /* MCP79 Ethernet Controller */
6374                 PCI_DEVICE(0x10DE, 0x0AB3),
6375                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6376         },
6377         {       /* MCP89 Ethernet Controller */
6378                 PCI_DEVICE(0x10DE, 0x0D7D),
6379                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX,
6380         },
6381         {0,},
6382 };
6383
6384 static struct pci_driver forcedeth_pci_driver = {
6385         .name           = DRV_NAME,
6386         .id_table       = pci_tbl,
6387         .probe          = nv_probe,
6388         .remove         = nv_remove,
6389         .shutdown       = nv_shutdown,
6390         .driver.pm      = NV_PM_OPS,
6391 };
6392
6393 module_param(max_interrupt_work, int, 0);
6394 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
6395 module_param(optimization_mode, int, 0);
6396 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer. In dynamic mode (2), the mode toggles between throughput and CPU mode based on network load.");
6397 module_param(poll_interval, int, 0);
6398 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
6399 module_param(msi, int, 0);
6400 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
6401 module_param(msix, int, 0);
6402 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
6403 module_param(dma_64bit, int, 0);
6404 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
6405 module_param(phy_cross, int, 0);
6406 MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
6407 module_param(phy_power_down, int, 0);
6408 MODULE_PARM_DESC(phy_power_down, "Power down phy and disable link when interface is down (1), or leave phy powered up (0).");
6409 module_param(debug_tx_timeout, bool, 0);
6410 MODULE_PARM_DESC(debug_tx_timeout,
6411                  "Dump tx related registers and ring when tx_timeout happens");
6412
6413 module_pci_driver(forcedeth_pci_driver);
6414 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6415 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6416 MODULE_LICENSE("GPL");
6417 MODULE_DEVICE_TABLE(pci, pci_tbl);