1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Microsemi Ocelot Switch driver
5 * Copyright (c) 2017 Microsemi Corporation
7 #include <linux/etherdevice.h>
8 #include <linux/ethtool.h>
9 #include <linux/if_bridge.h>
10 #include <linux/if_ether.h>
11 #include <linux/if_vlan.h>
12 #include <linux/interrupt.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/netdevice.h>
16 #include <linux/phy.h>
17 #include <linux/ptp_clock_kernel.h>
18 #include <linux/skbuff.h>
19 #include <linux/iopoll.h>
21 #include <net/netevent.h>
22 #include <net/rtnetlink.h>
23 #include <net/switchdev.h>
27 #include "ocelot_ace.h"
29 #define TABLE_UPDATE_SLEEP_US 10
30 #define TABLE_UPDATE_TIMEOUT_US 100000
32 /* MAC table entry types.
33 * ENTRYTYPE_NORMAL is subject to aging.
34 * ENTRYTYPE_LOCKED is not subject to aging.
35 * ENTRYTYPE_MACv4 is not subject to aging. For IPv4 multicast.
36 * ENTRYTYPE_MACv6 is not subject to aging. For IPv6 multicast.
38 enum macaccess_entry_type {
45 struct ocelot_mact_entry {
48 enum macaccess_entry_type type;
51 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot)
53 return ocelot_read(ocelot, ANA_TABLES_MACACCESS);
56 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot)
60 return readx_poll_timeout(ocelot_mact_read_macaccess,
62 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) ==
64 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US);
67 static void ocelot_mact_select(struct ocelot *ocelot,
68 const unsigned char mac[ETH_ALEN],
71 u32 macl = 0, mach = 0;
73 /* Set the MAC address to handle and the vlan associated in a format
74 * understood by the hardware.
84 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA);
85 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA);
89 static int ocelot_mact_learn(struct ocelot *ocelot, int port,
90 const unsigned char mac[ETH_ALEN],
92 enum macaccess_entry_type type)
94 ocelot_mact_select(ocelot, mac, vid);
96 /* Issue a write command */
97 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID |
98 ANA_TABLES_MACACCESS_DEST_IDX(port) |
99 ANA_TABLES_MACACCESS_ENTRYTYPE(type) |
100 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN),
101 ANA_TABLES_MACACCESS);
103 return ocelot_mact_wait_for_completion(ocelot);
106 static int ocelot_mact_forget(struct ocelot *ocelot,
107 const unsigned char mac[ETH_ALEN],
110 ocelot_mact_select(ocelot, mac, vid);
112 /* Issue a forget command */
114 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET),
115 ANA_TABLES_MACACCESS);
117 return ocelot_mact_wait_for_completion(ocelot);
120 static void ocelot_mact_init(struct ocelot *ocelot)
122 /* Configure the learning mode entries attributes:
123 * - Do not copy the frame to the CPU extraction queues.
124 * - Use the vlan and mac_cpoy for dmac lookup.
126 ocelot_rmw(ocelot, 0,
127 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS
128 | ANA_AGENCTRL_LEARN_FWD_KILL
129 | ANA_AGENCTRL_LEARN_IGNORE_VLAN,
132 /* Clear the MAC table */
133 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS);
136 static void ocelot_vcap_enable(struct ocelot *ocelot, int port)
138 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA |
139 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa),
140 ANA_PORT_VCAP_S2_CFG, port);
143 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot)
145 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS);
148 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot)
152 return readx_poll_timeout(ocelot_vlant_read_vlanaccess,
155 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) ==
156 ANA_TABLES_VLANACCESS_CMD_IDLE,
157 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US);
160 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask)
162 /* Select the VID to configure */
163 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid),
164 ANA_TABLES_VLANTIDX);
165 /* Set the vlan port members mask and issue a write command */
166 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) |
167 ANA_TABLES_VLANACCESS_CMD_WRITE,
168 ANA_TABLES_VLANACCESS);
170 return ocelot_vlant_wait_for_completion(ocelot);
173 static void ocelot_vlan_mode(struct ocelot *ocelot, int port,
174 netdev_features_t features)
179 val = ocelot_read(ocelot, ANA_VLANMASK);
180 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
184 ocelot_write(ocelot, val, ANA_VLANMASK);
187 static void ocelot_port_vlan_filtering(struct ocelot *ocelot, int port,
190 struct ocelot_port *ocelot_port = ocelot->ports[port];
194 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
195 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1);
198 ocelot_rmw_gix(ocelot, val,
199 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
200 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M,
201 ANA_PORT_VLAN_CFG, port);
203 if (vlan_aware && !ocelot_port->vid)
204 /* If port is vlan-aware and tagged, drop untagged and priority
207 val = ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA |
208 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA |
209 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA;
212 ocelot_rmw_gix(ocelot, val,
213 ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA |
214 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA |
215 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA,
216 ANA_PORT_DROP_CFG, port);
219 if (ocelot_port->vid)
220 /* Tag all frames except when VID == DEFAULT_VLAN */
221 val |= REW_TAG_CFG_TAG_CFG(1);
224 val |= REW_TAG_CFG_TAG_CFG(3);
226 /* Port tagging disabled. */
227 val = REW_TAG_CFG_TAG_CFG(0);
229 ocelot_rmw_gix(ocelot, val,
230 REW_TAG_CFG_TAG_CFG_M,
234 static int ocelot_port_set_native_vlan(struct ocelot *ocelot, int port,
237 struct ocelot_port *ocelot_port = ocelot->ports[port];
239 if (ocelot_port->vid != vid) {
240 /* Always permit deleting the native VLAN (vid = 0) */
241 if (ocelot_port->vid && vid) {
243 "Port already has a native VLAN: %d\n",
247 ocelot_port->vid = vid;
250 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_VID(vid),
251 REW_PORT_VLAN_CFG_PORT_VID_M,
252 REW_PORT_VLAN_CFG, port);
257 /* Default vlan to clasify for untagged frames (may be zero) */
258 static void ocelot_port_set_pvid(struct ocelot *ocelot, int port, u16 pvid)
260 struct ocelot_port *ocelot_port = ocelot->ports[port];
262 ocelot_rmw_gix(ocelot,
263 ANA_PORT_VLAN_CFG_VLAN_VID(pvid),
264 ANA_PORT_VLAN_CFG_VLAN_VID_M,
265 ANA_PORT_VLAN_CFG, port);
267 ocelot_port->pvid = pvid;
270 static int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
275 /* Make the port a member of the VLAN */
276 ocelot->vlan_mask[vid] |= BIT(port);
277 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]);
281 /* Default ingress vlan classification */
283 ocelot_port_set_pvid(ocelot, port, vid);
285 /* Untagged egress vlan clasification */
287 ret = ocelot_port_set_native_vlan(ocelot, port, vid);
295 static int ocelot_vlan_vid_add(struct net_device *dev, u16 vid, bool pvid,
298 struct ocelot_port_private *priv = netdev_priv(dev);
299 struct ocelot_port *ocelot_port = &priv->port;
300 struct ocelot *ocelot = ocelot_port->ocelot;
301 int port = priv->chip_port;
304 ret = ocelot_vlan_add(ocelot, port, vid, pvid, untagged);
308 /* Add the port MAC address to with the right VLAN information */
309 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, vid,
315 static int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid)
317 struct ocelot_port *ocelot_port = ocelot->ports[port];
320 /* Stop the port from being a member of the vlan */
321 ocelot->vlan_mask[vid] &= ~BIT(port);
322 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]);
327 if (ocelot_port->pvid == vid)
328 ocelot_port_set_pvid(ocelot, port, 0);
331 if (ocelot_port->vid == vid)
332 ocelot_port_set_native_vlan(ocelot, port, 0);
337 static int ocelot_vlan_vid_del(struct net_device *dev, u16 vid)
339 struct ocelot_port_private *priv = netdev_priv(dev);
340 struct ocelot *ocelot = priv->port.ocelot;
341 int port = priv->chip_port;
344 /* 8021q removes VID 0 on module unload for all interfaces
345 * with VLAN filtering feature. We need to keep it to receive
351 ret = ocelot_vlan_del(ocelot, port, vid);
355 /* Del the port MAC address to with the right VLAN information */
356 ocelot_mact_forget(ocelot, dev->dev_addr, vid);
361 static void ocelot_vlan_init(struct ocelot *ocelot)
365 /* Clear VLAN table, by default all ports are members of all VLANs */
366 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT,
367 ANA_TABLES_VLANACCESS);
368 ocelot_vlant_wait_for_completion(ocelot);
370 /* Configure the port VLAN memberships */
371 for (vid = 1; vid < VLAN_N_VID; vid++) {
372 ocelot->vlan_mask[vid] = 0;
373 ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]);
376 /* Because VLAN filtering is enabled, we need VID 0 to get untagged
377 * traffic. It is added automatically if 8021q module is loaded, but
378 * we can't rely on it since module may be not loaded.
380 ocelot->vlan_mask[0] = GENMASK(ocelot->num_phys_ports - 1, 0);
381 ocelot_vlant_set_mask(ocelot, 0, ocelot->vlan_mask[0]);
383 /* Set vlan ingress filter mask to all ports but the CPU port by
386 ocelot_write(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0),
389 for (port = 0; port < ocelot->num_phys_ports; port++) {
390 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port);
391 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port);
396 * Bit 8: Unit; 0:1, 1:16
397 * Bit 7-0: Value to be multiplied with unit
399 static u16 ocelot_wm_enc(u16 value)
402 return BIT(8) | (value / 16);
407 static void ocelot_adjust_link(struct ocelot *ocelot, int port,
408 struct phy_device *phydev)
410 struct ocelot_port *ocelot_port = ocelot->ports[port];
411 int speed, atop_wm, mode = 0;
413 switch (phydev->speed) {
415 speed = OCELOT_SPEED_10;
418 speed = OCELOT_SPEED_100;
421 speed = OCELOT_SPEED_1000;
422 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
425 speed = OCELOT_SPEED_2500;
426 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
429 dev_err(ocelot->dev, "Unsupported PHY speed on port %d: %d\n",
430 port, phydev->speed);
434 phy_print_status(phydev);
439 /* Only full duplex supported for now */
440 ocelot_port_writel(ocelot_port, DEV_MAC_MODE_CFG_FDX_ENA |
441 mode, DEV_MAC_MODE_CFG);
444 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0
445 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5
447 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5),
450 /* Load seed (0) and set MAC HDX late collision */
451 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) |
452 DEV_MAC_HDX_CFG_SEED_LOAD,
455 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67),
458 /* Disable HDX fast control */
459 ocelot_port_writel(ocelot_port, DEV_PORT_MISC_HDX_FAST_DIS,
462 /* SGMII only for now */
463 ocelot_port_writel(ocelot_port, PCS1G_MODE_CFG_SGMII_MODE_ENA,
465 ocelot_port_writel(ocelot_port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG);
468 ocelot_port_writel(ocelot_port, PCS1G_CFG_PCS_ENA, PCS1G_CFG);
470 /* No aneg on SGMII */
471 ocelot_port_writel(ocelot_port, 0, PCS1G_ANEG_CFG);
474 ocelot_port_writel(ocelot_port, 0, PCS1G_LB_CFG);
476 /* Set Max Length and maximum tags allowed */
477 ocelot_port_writel(ocelot_port, VLAN_ETH_FRAME_LEN,
479 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) |
480 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA |
481 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA,
484 /* Enable MAC module */
485 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA |
486 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG);
488 /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of
490 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(speed),
493 /* Set SMAC of Pause frame (00:00:00:00:00:00) */
494 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG);
495 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG);
498 ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed),
499 ANA_PFC_PFC_CFG, port);
501 /* Set Pause WM hysteresis
502 * 152 = 6 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ
503 * 101 = 4 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ
505 ocelot_write_rix(ocelot, SYS_PAUSE_CFG_PAUSE_ENA |
506 SYS_PAUSE_CFG_PAUSE_STOP(101) |
507 SYS_PAUSE_CFG_PAUSE_START(152), SYS_PAUSE_CFG, port);
509 /* Core: Enable port for frame transfer */
510 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE |
511 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) |
512 QSYS_SWITCH_PORT_MODE_PORT_ENA,
513 QSYS_SWITCH_PORT_MODE, port);
516 ocelot_write_rix(ocelot, SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) |
517 SYS_MAC_FC_CFG_RX_FC_ENA | SYS_MAC_FC_CFG_TX_FC_ENA |
518 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA |
519 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) |
520 SYS_MAC_FC_CFG_FC_LINK_SPEED(speed),
521 SYS_MAC_FC_CFG, port);
522 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port);
524 /* Tail dropping watermark */
525 atop_wm = (ocelot->shared_queue_sz - 9 * VLAN_ETH_FRAME_LEN) / OCELOT_BUFFER_CELL_SZ;
526 ocelot_write_rix(ocelot, ocelot_wm_enc(9 * VLAN_ETH_FRAME_LEN),
528 ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG);
531 static void ocelot_port_adjust_link(struct net_device *dev)
533 struct ocelot_port_private *priv = netdev_priv(dev);
534 struct ocelot *ocelot = priv->port.ocelot;
535 int port = priv->chip_port;
537 ocelot_adjust_link(ocelot, port, dev->phydev);
540 static void ocelot_port_enable(struct ocelot *ocelot, int port,
541 struct phy_device *phy)
543 /* Enable receiving frames on the port, and activate auto-learning of
546 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO |
547 ANA_PORT_PORT_CFG_RECV_ENA |
548 ANA_PORT_PORT_CFG_PORTID_VAL(port),
549 ANA_PORT_PORT_CFG, port);
552 static int ocelot_port_open(struct net_device *dev)
554 struct ocelot_port_private *priv = netdev_priv(dev);
555 struct ocelot *ocelot = priv->port.ocelot;
556 int port = priv->chip_port;
560 err = phy_set_mode_ext(priv->serdes, PHY_MODE_ETHERNET,
563 netdev_err(dev, "Could not set mode of SerDes\n");
568 err = phy_connect_direct(dev, priv->phy, &ocelot_port_adjust_link,
571 netdev_err(dev, "Could not attach to PHY\n");
575 dev->phydev = priv->phy;
577 phy_attached_info(priv->phy);
578 phy_start(priv->phy);
580 ocelot_port_enable(ocelot, port, priv->phy);
585 static void ocelot_port_disable(struct ocelot *ocelot, int port)
587 struct ocelot_port *ocelot_port = ocelot->ports[port];
589 ocelot_port_writel(ocelot_port, 0, DEV_MAC_ENA_CFG);
590 ocelot_rmw_rix(ocelot, 0, QSYS_SWITCH_PORT_MODE_PORT_ENA,
591 QSYS_SWITCH_PORT_MODE, port);
594 static int ocelot_port_stop(struct net_device *dev)
596 struct ocelot_port_private *priv = netdev_priv(dev);
597 struct ocelot *ocelot = priv->port.ocelot;
598 int port = priv->chip_port;
600 phy_disconnect(priv->phy);
604 ocelot_port_disable(ocelot, port);
609 /* Generate the IFH for frame injection
611 * The IFH is a 128bit-value
612 * bit 127: bypass the analyzer processing
613 * bit 56-67: destination mask
614 * bit 28-29: pop_cnt: 3 disables all rewriting of the frame
615 * bit 20-27: cpu extraction queue mask
616 * bit 16: tag type 0: C-tag, 1: S-tag
619 static int ocelot_gen_ifh(u32 *ifh, struct frame_info *info)
621 ifh[0] = IFH_INJ_BYPASS | ((0x1ff & info->rew_op) << 21);
622 ifh[1] = (0xf00 & info->port) >> 8;
623 ifh[2] = (0xff & info->port) << 24;
624 ifh[3] = (info->tag_type << 16) | info->vid;
629 static int ocelot_port_xmit(struct sk_buff *skb, struct net_device *dev)
631 struct ocelot_port_private *priv = netdev_priv(dev);
632 struct skb_shared_info *shinfo = skb_shinfo(skb);
633 struct ocelot_port *ocelot_port = &priv->port;
634 struct ocelot *ocelot = ocelot_port->ocelot;
635 struct frame_info info = {};
636 u8 grp = 0; /* Send everything on CPU group 0 */
637 unsigned int i, count, last;
638 int port = priv->chip_port;
639 u32 val, ifh[IFH_LEN];
641 val = ocelot_read(ocelot, QS_INJ_STATUS);
642 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp))) ||
643 (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp))))
644 return NETDEV_TX_BUSY;
646 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
647 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp);
649 info.port = BIT(port);
650 info.tag_type = IFH_TAG_TYPE_C;
651 info.vid = skb_vlan_tag_get(skb);
653 /* Check if timestamping is needed */
654 if (ocelot->ptp && shinfo->tx_flags & SKBTX_HW_TSTAMP) {
655 info.rew_op = ocelot_port->ptp_cmd;
656 if (ocelot_port->ptp_cmd == IFH_REW_OP_TWO_STEP_PTP)
657 info.rew_op |= (ocelot_port->ts_id % 4) << 3;
660 ocelot_gen_ifh(ifh, &info);
662 for (i = 0; i < IFH_LEN; i++)
663 ocelot_write_rix(ocelot, (__force u32)cpu_to_be32(ifh[i]),
666 count = (skb->len + 3) / 4;
668 for (i = 0; i < count; i++) {
669 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp);
673 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) {
674 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
678 /* Indicate EOF and valid bytes in last word */
679 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
680 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) |
685 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
686 skb_tx_timestamp(skb);
688 dev->stats.tx_packets++;
689 dev->stats.tx_bytes += skb->len;
691 if (ocelot->ptp && shinfo->tx_flags & SKBTX_HW_TSTAMP &&
692 ocelot_port->ptp_cmd == IFH_REW_OP_TWO_STEP_PTP) {
693 struct ocelot_skb *oskb =
694 kzalloc(sizeof(struct ocelot_skb), GFP_ATOMIC);
699 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
702 oskb->id = ocelot_port->ts_id % 4;
703 ocelot_port->ts_id++;
705 list_add_tail(&oskb->head, &ocelot_port->skbs);
711 dev_kfree_skb_any(skb);
715 void ocelot_get_hwtimestamp(struct ocelot *ocelot, struct timespec64 *ts)
720 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags);
722 /* Read current PTP time to get seconds */
723 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN);
725 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM);
726 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE);
727 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN);
728 ts->tv_sec = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN);
730 /* Read packet HW timestamp from FIFO */
731 val = ocelot_read(ocelot, SYS_PTP_TXSTAMP);
732 ts->tv_nsec = SYS_PTP_TXSTAMP_PTP_TXSTAMP(val);
734 /* Sec has incremented since the ts was registered */
735 if ((ts->tv_sec & 0x1) != !!(val & SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC))
738 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags);
740 EXPORT_SYMBOL(ocelot_get_hwtimestamp);
742 static int ocelot_mc_unsync(struct net_device *dev, const unsigned char *addr)
744 struct ocelot_port_private *priv = netdev_priv(dev);
745 struct ocelot_port *ocelot_port = &priv->port;
746 struct ocelot *ocelot = ocelot_port->ocelot;
748 return ocelot_mact_forget(ocelot, addr, ocelot_port->pvid);
751 static int ocelot_mc_sync(struct net_device *dev, const unsigned char *addr)
753 struct ocelot_port_private *priv = netdev_priv(dev);
754 struct ocelot_port *ocelot_port = &priv->port;
755 struct ocelot *ocelot = ocelot_port->ocelot;
757 return ocelot_mact_learn(ocelot, PGID_CPU, addr, ocelot_port->pvid,
761 static void ocelot_set_rx_mode(struct net_device *dev)
763 struct ocelot_port_private *priv = netdev_priv(dev);
764 struct ocelot *ocelot = priv->port.ocelot;
768 /* This doesn't handle promiscuous mode because the bridge core is
769 * setting IFF_PROMISC on all slave interfaces and all frames would be
770 * forwarded to the CPU port.
772 val = GENMASK(ocelot->num_phys_ports - 1, 0);
773 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++)
774 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i);
776 __dev_mc_sync(dev, ocelot_mc_sync, ocelot_mc_unsync);
779 static int ocelot_port_get_phys_port_name(struct net_device *dev,
780 char *buf, size_t len)
782 struct ocelot_port_private *priv = netdev_priv(dev);
783 int port = priv->chip_port;
786 ret = snprintf(buf, len, "p%d", port);
793 static int ocelot_port_set_mac_address(struct net_device *dev, void *p)
795 struct ocelot_port_private *priv = netdev_priv(dev);
796 struct ocelot_port *ocelot_port = &priv->port;
797 struct ocelot *ocelot = ocelot_port->ocelot;
798 const struct sockaddr *addr = p;
800 /* Learn the new net device MAC address in the mac table. */
801 ocelot_mact_learn(ocelot, PGID_CPU, addr->sa_data, ocelot_port->pvid,
803 /* Then forget the previous one. */
804 ocelot_mact_forget(ocelot, dev->dev_addr, ocelot_port->pvid);
806 ether_addr_copy(dev->dev_addr, addr->sa_data);
810 static void ocelot_get_stats64(struct net_device *dev,
811 struct rtnl_link_stats64 *stats)
813 struct ocelot_port_private *priv = netdev_priv(dev);
814 struct ocelot *ocelot = priv->port.ocelot;
815 int port = priv->chip_port;
817 /* Configure the port to read the stats from */
818 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port),
822 stats->rx_bytes = ocelot_read(ocelot, SYS_COUNT_RX_OCTETS);
823 stats->rx_packets = ocelot_read(ocelot, SYS_COUNT_RX_SHORTS) +
824 ocelot_read(ocelot, SYS_COUNT_RX_FRAGMENTS) +
825 ocelot_read(ocelot, SYS_COUNT_RX_JABBERS) +
826 ocelot_read(ocelot, SYS_COUNT_RX_LONGS) +
827 ocelot_read(ocelot, SYS_COUNT_RX_64) +
828 ocelot_read(ocelot, SYS_COUNT_RX_65_127) +
829 ocelot_read(ocelot, SYS_COUNT_RX_128_255) +
830 ocelot_read(ocelot, SYS_COUNT_RX_256_1023) +
831 ocelot_read(ocelot, SYS_COUNT_RX_1024_1526) +
832 ocelot_read(ocelot, SYS_COUNT_RX_1527_MAX);
833 stats->multicast = ocelot_read(ocelot, SYS_COUNT_RX_MULTICAST);
834 stats->rx_dropped = dev->stats.rx_dropped;
837 stats->tx_bytes = ocelot_read(ocelot, SYS_COUNT_TX_OCTETS);
838 stats->tx_packets = ocelot_read(ocelot, SYS_COUNT_TX_64) +
839 ocelot_read(ocelot, SYS_COUNT_TX_65_127) +
840 ocelot_read(ocelot, SYS_COUNT_TX_128_511) +
841 ocelot_read(ocelot, SYS_COUNT_TX_512_1023) +
842 ocelot_read(ocelot, SYS_COUNT_TX_1024_1526) +
843 ocelot_read(ocelot, SYS_COUNT_TX_1527_MAX);
844 stats->tx_dropped = ocelot_read(ocelot, SYS_COUNT_TX_DROPS) +
845 ocelot_read(ocelot, SYS_COUNT_TX_AGING);
846 stats->collisions = ocelot_read(ocelot, SYS_COUNT_TX_COLLISION);
849 static int ocelot_fdb_add(struct ocelot *ocelot, int port,
850 const unsigned char *addr, u16 vid,
853 struct ocelot_port *ocelot_port = ocelot->ports[port];
857 /* If the bridge is not VLAN aware and no VID was
858 * provided, set it to pvid to ensure the MAC entry
859 * matches incoming untagged packets
861 vid = ocelot_port->pvid;
863 /* If the bridge is VLAN aware a VID must be provided as
864 * otherwise the learnt entry wouldn't match any frame.
869 return ocelot_mact_learn(ocelot, port, addr, vid, ENTRYTYPE_LOCKED);
872 static int ocelot_port_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
873 struct net_device *dev,
874 const unsigned char *addr,
876 struct netlink_ext_ack *extack)
878 struct ocelot_port_private *priv = netdev_priv(dev);
879 struct ocelot *ocelot = priv->port.ocelot;
880 int port = priv->chip_port;
882 return ocelot_fdb_add(ocelot, port, addr, vid, priv->vlan_aware);
885 static int ocelot_fdb_del(struct ocelot *ocelot, int port,
886 const unsigned char *addr, u16 vid)
888 return ocelot_mact_forget(ocelot, addr, vid);
891 static int ocelot_port_fdb_del(struct ndmsg *ndm, struct nlattr *tb[],
892 struct net_device *dev,
893 const unsigned char *addr, u16 vid)
895 struct ocelot_port_private *priv = netdev_priv(dev);
896 struct ocelot *ocelot = priv->port.ocelot;
897 int port = priv->chip_port;
899 return ocelot_fdb_del(ocelot, port, addr, vid);
902 struct ocelot_dump_ctx {
903 struct net_device *dev;
905 struct netlink_callback *cb;
909 static int ocelot_port_fdb_do_dump(const unsigned char *addr, u16 vid,
910 bool is_static, void *data)
912 struct ocelot_dump_ctx *dump = data;
913 u32 portid = NETLINK_CB(dump->cb->skb).portid;
914 u32 seq = dump->cb->nlh->nlmsg_seq;
915 struct nlmsghdr *nlh;
918 if (dump->idx < dump->cb->args[2])
921 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH,
922 sizeof(*ndm), NLM_F_MULTI);
926 ndm = nlmsg_data(nlh);
927 ndm->ndm_family = AF_BRIDGE;
930 ndm->ndm_flags = NTF_SELF;
932 ndm->ndm_ifindex = dump->dev->ifindex;
933 ndm->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
935 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, addr))
936 goto nla_put_failure;
938 if (vid && nla_put_u16(dump->skb, NDA_VLAN, vid))
939 goto nla_put_failure;
941 nlmsg_end(dump->skb, nlh);
948 nlmsg_cancel(dump->skb, nlh);
952 static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col,
953 struct ocelot_mact_entry *entry)
955 u32 val, dst, macl, mach;
958 /* Set row and column to read from */
959 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row);
960 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col);
962 /* Issue a read command */
964 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ),
965 ANA_TABLES_MACACCESS);
967 if (ocelot_mact_wait_for_completion(ocelot))
970 /* Read the entry flags */
971 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS);
972 if (!(val & ANA_TABLES_MACACCESS_VALID))
975 /* If the entry read has another port configured as its destination,
978 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3;
982 /* Get the entry's MAC address and VLAN id */
983 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA);
984 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA);
986 mac[0] = (mach >> 8) & 0xff;
987 mac[1] = (mach >> 0) & 0xff;
988 mac[2] = (macl >> 24) & 0xff;
989 mac[3] = (macl >> 16) & 0xff;
990 mac[4] = (macl >> 8) & 0xff;
991 mac[5] = (macl >> 0) & 0xff;
993 entry->vid = (mach >> 16) & 0xfff;
994 ether_addr_copy(entry->mac, mac);
999 static int ocelot_fdb_dump(struct ocelot *ocelot, int port,
1000 dsa_fdb_dump_cb_t *cb, void *data)
1004 /* Loop through all the mac tables entries. There are 1024 rows of 4
1007 for (i = 0; i < 1024; i++) {
1008 for (j = 0; j < 4; j++) {
1009 struct ocelot_mact_entry entry;
1013 ret = ocelot_mact_read(ocelot, port, i, j, &entry);
1014 /* If the entry is invalid (wrong port, invalid...),
1022 is_static = (entry.type == ENTRYTYPE_LOCKED);
1024 ret = cb(entry.mac, entry.vid, is_static, data);
1033 static int ocelot_port_fdb_dump(struct sk_buff *skb,
1034 struct netlink_callback *cb,
1035 struct net_device *dev,
1036 struct net_device *filter_dev, int *idx)
1038 struct ocelot_port_private *priv = netdev_priv(dev);
1039 struct ocelot *ocelot = priv->port.ocelot;
1040 struct ocelot_dump_ctx dump = {
1046 int port = priv->chip_port;
1049 ret = ocelot_fdb_dump(ocelot, port, ocelot_port_fdb_do_dump, &dump);
1056 static int ocelot_vlan_rx_add_vid(struct net_device *dev, __be16 proto,
1059 return ocelot_vlan_vid_add(dev, vid, false, false);
1062 static int ocelot_vlan_rx_kill_vid(struct net_device *dev, __be16 proto,
1065 return ocelot_vlan_vid_del(dev, vid);
1068 static int ocelot_set_features(struct net_device *dev,
1069 netdev_features_t features)
1071 netdev_features_t changed = dev->features ^ features;
1072 struct ocelot_port_private *priv = netdev_priv(dev);
1073 struct ocelot *ocelot = priv->port.ocelot;
1074 int port = priv->chip_port;
1076 if ((dev->features & NETIF_F_HW_TC) > (features & NETIF_F_HW_TC) &&
1077 priv->tc.offload_cnt) {
1079 "Cannot disable HW TC offload while offloads active\n");
1083 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER)
1084 ocelot_vlan_mode(ocelot, port, features);
1089 static int ocelot_get_port_parent_id(struct net_device *dev,
1090 struct netdev_phys_item_id *ppid)
1092 struct ocelot_port_private *priv = netdev_priv(dev);
1093 struct ocelot *ocelot = priv->port.ocelot;
1095 ppid->id_len = sizeof(ocelot->base_mac);
1096 memcpy(&ppid->id, &ocelot->base_mac, ppid->id_len);
1101 static int ocelot_hwstamp_get(struct ocelot *ocelot, int port,
1104 return copy_to_user(ifr->ifr_data, &ocelot->hwtstamp_config,
1105 sizeof(ocelot->hwtstamp_config)) ? -EFAULT : 0;
1108 static int ocelot_hwstamp_set(struct ocelot *ocelot, int port,
1111 struct ocelot_port *ocelot_port = ocelot->ports[port];
1112 struct hwtstamp_config cfg;
1114 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1117 /* reserved for future extensions */
1121 /* Tx type sanity check */
1122 switch (cfg.tx_type) {
1123 case HWTSTAMP_TX_ON:
1124 ocelot_port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP;
1126 case HWTSTAMP_TX_ONESTEP_SYNC:
1127 /* IFH_REW_OP_ONE_STEP_PTP updates the correctional field, we
1128 * need to update the origin time.
1130 ocelot_port->ptp_cmd = IFH_REW_OP_ORIGIN_PTP;
1132 case HWTSTAMP_TX_OFF:
1133 ocelot_port->ptp_cmd = 0;
1139 mutex_lock(&ocelot->ptp_lock);
1141 switch (cfg.rx_filter) {
1142 case HWTSTAMP_FILTER_NONE:
1144 case HWTSTAMP_FILTER_ALL:
1145 case HWTSTAMP_FILTER_SOME:
1146 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1147 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1148 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1149 case HWTSTAMP_FILTER_NTP_ALL:
1150 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1151 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1152 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1153 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1154 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1155 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1156 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1157 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1158 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1159 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1162 mutex_unlock(&ocelot->ptp_lock);
1166 /* Commit back the result & save it */
1167 memcpy(&ocelot->hwtstamp_config, &cfg, sizeof(cfg));
1168 mutex_unlock(&ocelot->ptp_lock);
1170 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1173 static int ocelot_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1175 struct ocelot_port_private *priv = netdev_priv(dev);
1176 struct ocelot *ocelot = priv->port.ocelot;
1177 int port = priv->chip_port;
1179 /* The function is only used for PTP operations for now */
1185 return ocelot_hwstamp_set(ocelot, port, ifr);
1187 return ocelot_hwstamp_get(ocelot, port, ifr);
1193 static const struct net_device_ops ocelot_port_netdev_ops = {
1194 .ndo_open = ocelot_port_open,
1195 .ndo_stop = ocelot_port_stop,
1196 .ndo_start_xmit = ocelot_port_xmit,
1197 .ndo_set_rx_mode = ocelot_set_rx_mode,
1198 .ndo_get_phys_port_name = ocelot_port_get_phys_port_name,
1199 .ndo_set_mac_address = ocelot_port_set_mac_address,
1200 .ndo_get_stats64 = ocelot_get_stats64,
1201 .ndo_fdb_add = ocelot_port_fdb_add,
1202 .ndo_fdb_del = ocelot_port_fdb_del,
1203 .ndo_fdb_dump = ocelot_port_fdb_dump,
1204 .ndo_vlan_rx_add_vid = ocelot_vlan_rx_add_vid,
1205 .ndo_vlan_rx_kill_vid = ocelot_vlan_rx_kill_vid,
1206 .ndo_set_features = ocelot_set_features,
1207 .ndo_get_port_parent_id = ocelot_get_port_parent_id,
1208 .ndo_setup_tc = ocelot_setup_tc,
1209 .ndo_do_ioctl = ocelot_ioctl,
1212 static void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset,
1217 if (sset != ETH_SS_STATS)
1220 for (i = 0; i < ocelot->num_stats; i++)
1221 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name,
1225 static void ocelot_port_get_strings(struct net_device *netdev, u32 sset,
1228 struct ocelot_port_private *priv = netdev_priv(netdev);
1229 struct ocelot *ocelot = priv->port.ocelot;
1230 int port = priv->chip_port;
1232 ocelot_get_strings(ocelot, port, sset, data);
1235 static void ocelot_update_stats(struct ocelot *ocelot)
1239 mutex_lock(&ocelot->stats_lock);
1241 for (i = 0; i < ocelot->num_phys_ports; i++) {
1242 /* Configure the port to read the stats from */
1243 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG);
1245 for (j = 0; j < ocelot->num_stats; j++) {
1247 unsigned int idx = i * ocelot->num_stats + j;
1249 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS,
1250 ocelot->stats_layout[j].offset);
1252 if (val < (ocelot->stats[idx] & U32_MAX))
1253 ocelot->stats[idx] += (u64)1 << 32;
1255 ocelot->stats[idx] = (ocelot->stats[idx] &
1256 ~(u64)U32_MAX) + val;
1260 mutex_unlock(&ocelot->stats_lock);
1263 static void ocelot_check_stats_work(struct work_struct *work)
1265 struct delayed_work *del_work = to_delayed_work(work);
1266 struct ocelot *ocelot = container_of(del_work, struct ocelot,
1269 ocelot_update_stats(ocelot);
1271 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work,
1272 OCELOT_STATS_CHECK_DELAY);
1275 static void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data)
1279 /* check and update now */
1280 ocelot_update_stats(ocelot);
1282 /* Copy all counters */
1283 for (i = 0; i < ocelot->num_stats; i++)
1284 *data++ = ocelot->stats[port * ocelot->num_stats + i];
1287 static void ocelot_port_get_ethtool_stats(struct net_device *dev,
1288 struct ethtool_stats *stats,
1291 struct ocelot_port_private *priv = netdev_priv(dev);
1292 struct ocelot *ocelot = priv->port.ocelot;
1293 int port = priv->chip_port;
1295 ocelot_get_ethtool_stats(ocelot, port, data);
1298 static int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset)
1300 if (sset != ETH_SS_STATS)
1303 return ocelot->num_stats;
1306 static int ocelot_port_get_sset_count(struct net_device *dev, int sset)
1308 struct ocelot_port_private *priv = netdev_priv(dev);
1309 struct ocelot *ocelot = priv->port.ocelot;
1310 int port = priv->chip_port;
1312 return ocelot_get_sset_count(ocelot, port, sset);
1315 static int ocelot_get_ts_info(struct ocelot *ocelot, int port,
1316 struct ethtool_ts_info *info)
1318 info->phc_index = ocelot->ptp_clock ?
1319 ptp_clock_index(ocelot->ptp_clock) : -1;
1320 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE |
1321 SOF_TIMESTAMPING_RX_SOFTWARE |
1322 SOF_TIMESTAMPING_SOFTWARE |
1323 SOF_TIMESTAMPING_TX_HARDWARE |
1324 SOF_TIMESTAMPING_RX_HARDWARE |
1325 SOF_TIMESTAMPING_RAW_HARDWARE;
1326 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) |
1327 BIT(HWTSTAMP_TX_ONESTEP_SYNC);
1328 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL);
1333 static int ocelot_port_get_ts_info(struct net_device *dev,
1334 struct ethtool_ts_info *info)
1336 struct ocelot_port_private *priv = netdev_priv(dev);
1337 struct ocelot *ocelot = priv->port.ocelot;
1338 int port = priv->chip_port;
1341 return ethtool_op_get_ts_info(dev, info);
1343 return ocelot_get_ts_info(ocelot, port, info);
1346 static const struct ethtool_ops ocelot_ethtool_ops = {
1347 .get_strings = ocelot_port_get_strings,
1348 .get_ethtool_stats = ocelot_port_get_ethtool_stats,
1349 .get_sset_count = ocelot_port_get_sset_count,
1350 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1351 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1352 .get_ts_info = ocelot_port_get_ts_info,
1355 static void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port,
1361 if (!(BIT(port) & ocelot->bridge_mask))
1364 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, port);
1367 case BR_STATE_FORWARDING:
1368 ocelot->bridge_fwd_mask |= BIT(port);
1370 case BR_STATE_LEARNING:
1371 port_cfg |= ANA_PORT_PORT_CFG_LEARN_ENA;
1375 port_cfg &= ~ANA_PORT_PORT_CFG_LEARN_ENA;
1376 ocelot->bridge_fwd_mask &= ~BIT(port);
1380 ocelot_write_gix(ocelot, port_cfg, ANA_PORT_PORT_CFG, port);
1382 /* Apply FWD mask. The loop is needed to add/remove the current port as
1383 * a source for the other ports.
1385 for (p = 0; p < ocelot->num_phys_ports; p++) {
1386 if (ocelot->bridge_fwd_mask & BIT(p)) {
1387 unsigned long mask = ocelot->bridge_fwd_mask & ~BIT(p);
1389 for (i = 0; i < ocelot->num_phys_ports; i++) {
1390 unsigned long bond_mask = ocelot->lags[i];
1395 if (bond_mask & BIT(p)) {
1401 ocelot_write_rix(ocelot,
1402 BIT(ocelot->num_phys_ports) | mask,
1403 ANA_PGID_PGID, PGID_SRC + p);
1405 /* Only the CPU port, this is compatible with link
1408 ocelot_write_rix(ocelot,
1409 BIT(ocelot->num_phys_ports),
1410 ANA_PGID_PGID, PGID_SRC + p);
1415 static void ocelot_port_attr_stp_state_set(struct ocelot *ocelot, int port,
1416 struct switchdev_trans *trans,
1419 if (switchdev_trans_ph_prepare(trans))
1422 ocelot_bridge_stp_state_set(ocelot, port, state);
1425 static void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs)
1427 ocelot_write(ocelot, ANA_AUTOAGE_AGE_PERIOD(msecs / 2),
1431 static void ocelot_port_attr_ageing_set(struct ocelot *ocelot, int port,
1432 unsigned long ageing_clock_t)
1434 unsigned long ageing_jiffies = clock_t_to_jiffies(ageing_clock_t);
1435 u32 ageing_time = jiffies_to_msecs(ageing_jiffies) / 1000;
1437 ocelot_set_ageing_time(ocelot, ageing_time);
1440 static void ocelot_port_attr_mc_set(struct ocelot *ocelot, int port, bool mc)
1442 u32 cpu_fwd_mcast = ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA |
1443 ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA |
1444 ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA;
1448 val = cpu_fwd_mcast;
1450 ocelot_rmw_gix(ocelot, val, cpu_fwd_mcast,
1451 ANA_PORT_CPU_FWD_CFG, port);
1454 static int ocelot_port_attr_set(struct net_device *dev,
1455 const struct switchdev_attr *attr,
1456 struct switchdev_trans *trans)
1458 struct ocelot_port_private *priv = netdev_priv(dev);
1459 struct ocelot *ocelot = priv->port.ocelot;
1460 int port = priv->chip_port;
1464 case SWITCHDEV_ATTR_ID_PORT_STP_STATE:
1465 ocelot_port_attr_stp_state_set(ocelot, port, trans,
1468 case SWITCHDEV_ATTR_ID_BRIDGE_AGEING_TIME:
1469 ocelot_port_attr_ageing_set(ocelot, port, attr->u.ageing_time);
1471 case SWITCHDEV_ATTR_ID_BRIDGE_VLAN_FILTERING:
1472 priv->vlan_aware = attr->u.vlan_filtering;
1473 ocelot_port_vlan_filtering(ocelot, port, priv->vlan_aware);
1475 case SWITCHDEV_ATTR_ID_BRIDGE_MC_DISABLED:
1476 ocelot_port_attr_mc_set(ocelot, port, !attr->u.mc_disabled);
1486 static int ocelot_port_obj_add_vlan(struct net_device *dev,
1487 const struct switchdev_obj_port_vlan *vlan,
1488 struct switchdev_trans *trans)
1493 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
1494 ret = ocelot_vlan_vid_add(dev, vid,
1495 vlan->flags & BRIDGE_VLAN_INFO_PVID,
1496 vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED);
1504 static int ocelot_port_vlan_del_vlan(struct net_device *dev,
1505 const struct switchdev_obj_port_vlan *vlan)
1510 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
1511 ret = ocelot_vlan_vid_del(dev, vid);
1520 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot,
1521 const unsigned char *addr,
1524 struct ocelot_multicast *mc;
1526 list_for_each_entry(mc, &ocelot->multicast, list) {
1527 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid)
1534 static int ocelot_port_obj_add_mdb(struct net_device *dev,
1535 const struct switchdev_obj_port_mdb *mdb,
1536 struct switchdev_trans *trans)
1538 struct ocelot_port_private *priv = netdev_priv(dev);
1539 struct ocelot_port *ocelot_port = &priv->port;
1540 struct ocelot *ocelot = ocelot_port->ocelot;
1541 unsigned char addr[ETH_ALEN];
1542 struct ocelot_multicast *mc;
1543 int port = priv->chip_port;
1548 vid = ocelot_port->pvid;
1550 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
1552 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL);
1556 memcpy(mc->addr, mdb->addr, ETH_ALEN);
1559 list_add_tail(&mc->list, &ocelot->multicast);
1563 memcpy(addr, mc->addr, ETH_ALEN);
1567 addr[2] = mc->ports << 0;
1568 addr[1] = mc->ports << 8;
1569 ocelot_mact_forget(ocelot, addr, vid);
1572 mc->ports |= BIT(port);
1573 addr[2] = mc->ports << 0;
1574 addr[1] = mc->ports << 8;
1576 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4);
1579 static int ocelot_port_obj_del_mdb(struct net_device *dev,
1580 const struct switchdev_obj_port_mdb *mdb)
1582 struct ocelot_port_private *priv = netdev_priv(dev);
1583 struct ocelot_port *ocelot_port = &priv->port;
1584 struct ocelot *ocelot = ocelot_port->ocelot;
1585 unsigned char addr[ETH_ALEN];
1586 struct ocelot_multicast *mc;
1587 int port = priv->chip_port;
1591 vid = ocelot_port->pvid;
1593 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
1597 memcpy(addr, mc->addr, ETH_ALEN);
1598 addr[2] = mc->ports << 0;
1599 addr[1] = mc->ports << 8;
1601 ocelot_mact_forget(ocelot, addr, vid);
1603 mc->ports &= ~BIT(port);
1605 list_del(&mc->list);
1606 devm_kfree(ocelot->dev, mc);
1610 addr[2] = mc->ports << 0;
1611 addr[1] = mc->ports << 8;
1613 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4);
1616 static int ocelot_port_obj_add(struct net_device *dev,
1617 const struct switchdev_obj *obj,
1618 struct switchdev_trans *trans,
1619 struct netlink_ext_ack *extack)
1624 case SWITCHDEV_OBJ_ID_PORT_VLAN:
1625 ret = ocelot_port_obj_add_vlan(dev,
1626 SWITCHDEV_OBJ_PORT_VLAN(obj),
1629 case SWITCHDEV_OBJ_ID_PORT_MDB:
1630 ret = ocelot_port_obj_add_mdb(dev, SWITCHDEV_OBJ_PORT_MDB(obj),
1640 static int ocelot_port_obj_del(struct net_device *dev,
1641 const struct switchdev_obj *obj)
1646 case SWITCHDEV_OBJ_ID_PORT_VLAN:
1647 ret = ocelot_port_vlan_del_vlan(dev,
1648 SWITCHDEV_OBJ_PORT_VLAN(obj));
1650 case SWITCHDEV_OBJ_ID_PORT_MDB:
1651 ret = ocelot_port_obj_del_mdb(dev, SWITCHDEV_OBJ_PORT_MDB(obj));
1660 static int ocelot_port_bridge_join(struct ocelot *ocelot, int port,
1661 struct net_device *bridge)
1663 if (!ocelot->bridge_mask) {
1664 ocelot->hw_bridge_dev = bridge;
1666 if (ocelot->hw_bridge_dev != bridge)
1667 /* This is adding the port to a second bridge, this is
1672 ocelot->bridge_mask |= BIT(port);
1677 static int ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
1678 struct net_device *bridge)
1680 ocelot->bridge_mask &= ~BIT(port);
1682 if (!ocelot->bridge_mask)
1683 ocelot->hw_bridge_dev = NULL;
1685 ocelot_port_vlan_filtering(ocelot, port, 0);
1686 ocelot_port_set_pvid(ocelot, port, 0);
1687 return ocelot_port_set_native_vlan(ocelot, port, 0);
1690 static void ocelot_set_aggr_pgids(struct ocelot *ocelot)
1694 /* Reset destination and aggregation PGIDS */
1695 for (port = 0; port < ocelot->num_phys_ports; port++)
1696 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
1698 for (i = PGID_AGGR; i < PGID_SRC; i++)
1699 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0),
1702 /* Now, set PGIDs for each LAG */
1703 for (lag = 0; lag < ocelot->num_phys_ports; lag++) {
1704 unsigned long bond_mask;
1708 bond_mask = ocelot->lags[lag];
1712 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) {
1714 ocelot_write_rix(ocelot, bond_mask,
1715 ANA_PGID_PGID, port);
1716 aggr_idx[aggr_count] = port;
1720 for (i = PGID_AGGR; i < PGID_SRC; i++) {
1723 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i);
1725 ac |= BIT(aggr_idx[i % aggr_count]);
1726 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i);
1731 static void ocelot_setup_lag(struct ocelot *ocelot, int lag)
1733 unsigned long bond_mask = ocelot->lags[lag];
1736 for_each_set_bit(p, &bond_mask, ocelot->num_phys_ports) {
1737 u32 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, p);
1739 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M;
1741 /* Use lag port as logical port for port i */
1742 ocelot_write_gix(ocelot, port_cfg |
1743 ANA_PORT_PORT_CFG_PORTID_VAL(lag),
1744 ANA_PORT_PORT_CFG, p);
1748 static int ocelot_port_lag_join(struct ocelot *ocelot, int port,
1749 struct net_device *bond)
1751 struct net_device *ndev;
1756 for_each_netdev_in_bond_rcu(bond, ndev) {
1757 struct ocelot_port_private *priv = netdev_priv(ndev);
1759 bond_mask |= BIT(priv->chip_port);
1763 lp = __ffs(bond_mask);
1765 /* If the new port is the lowest one, use it as the logical port from
1770 ocelot->lags[port] = bond_mask;
1771 bond_mask &= ~BIT(port);
1773 lp = __ffs(bond_mask);
1774 ocelot->lags[lp] = 0;
1778 ocelot->lags[lp] |= BIT(port);
1781 ocelot_setup_lag(ocelot, lag);
1782 ocelot_set_aggr_pgids(ocelot);
1787 static void ocelot_port_lag_leave(struct ocelot *ocelot, int port,
1788 struct net_device *bond)
1793 /* Remove port from any lag */
1794 for (i = 0; i < ocelot->num_phys_ports; i++)
1795 ocelot->lags[i] &= ~BIT(port);
1797 /* if it was the logical port of the lag, move the lag config to the
1800 if (ocelot->lags[port]) {
1801 int n = __ffs(ocelot->lags[port]);
1803 ocelot->lags[n] = ocelot->lags[port];
1804 ocelot->lags[port] = 0;
1806 ocelot_setup_lag(ocelot, n);
1809 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, port);
1810 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M;
1811 ocelot_write_gix(ocelot, port_cfg | ANA_PORT_PORT_CFG_PORTID_VAL(port),
1812 ANA_PORT_PORT_CFG, port);
1814 ocelot_set_aggr_pgids(ocelot);
1817 /* Checks if the net_device instance given to us originate from our driver. */
1818 static bool ocelot_netdevice_dev_check(const struct net_device *dev)
1820 return dev->netdev_ops == &ocelot_port_netdev_ops;
1823 static int ocelot_netdevice_port_event(struct net_device *dev,
1824 unsigned long event,
1825 struct netdev_notifier_changeupper_info *info)
1827 struct ocelot_port_private *priv = netdev_priv(dev);
1828 struct ocelot_port *ocelot_port = &priv->port;
1829 struct ocelot *ocelot = ocelot_port->ocelot;
1830 int port = priv->chip_port;
1834 case NETDEV_CHANGEUPPER:
1835 if (netif_is_bridge_master(info->upper_dev)) {
1836 if (info->linking) {
1837 err = ocelot_port_bridge_join(ocelot, port,
1840 err = ocelot_port_bridge_leave(ocelot, port,
1842 priv->vlan_aware = false;
1845 if (netif_is_lag_master(info->upper_dev)) {
1847 err = ocelot_port_lag_join(ocelot, port,
1850 ocelot_port_lag_leave(ocelot, port,
1861 static int ocelot_netdevice_event(struct notifier_block *unused,
1862 unsigned long event, void *ptr)
1864 struct netdev_notifier_changeupper_info *info = ptr;
1865 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
1868 if (!ocelot_netdevice_dev_check(dev))
1871 if (event == NETDEV_PRECHANGEUPPER &&
1872 netif_is_lag_master(info->upper_dev)) {
1873 struct netdev_lag_upper_info *lag_upper_info = info->upper_info;
1874 struct netlink_ext_ack *extack;
1876 if (lag_upper_info &&
1877 lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
1878 extack = netdev_notifier_info_to_extack(&info->info);
1879 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type");
1886 if (netif_is_lag_master(dev)) {
1887 struct net_device *slave;
1888 struct list_head *iter;
1890 netdev_for_each_lower_dev(dev, slave, iter) {
1891 ret = ocelot_netdevice_port_event(slave, event, info);
1896 ret = ocelot_netdevice_port_event(dev, event, info);
1900 return notifier_from_errno(ret);
1903 struct notifier_block ocelot_netdevice_nb __read_mostly = {
1904 .notifier_call = ocelot_netdevice_event,
1906 EXPORT_SYMBOL(ocelot_netdevice_nb);
1908 static int ocelot_switchdev_event(struct notifier_block *unused,
1909 unsigned long event, void *ptr)
1911 struct net_device *dev = switchdev_notifier_info_to_dev(ptr);
1915 case SWITCHDEV_PORT_ATTR_SET:
1916 err = switchdev_handle_port_attr_set(dev, ptr,
1917 ocelot_netdevice_dev_check,
1918 ocelot_port_attr_set);
1919 return notifier_from_errno(err);
1925 struct notifier_block ocelot_switchdev_nb __read_mostly = {
1926 .notifier_call = ocelot_switchdev_event,
1928 EXPORT_SYMBOL(ocelot_switchdev_nb);
1930 static int ocelot_switchdev_blocking_event(struct notifier_block *unused,
1931 unsigned long event, void *ptr)
1933 struct net_device *dev = switchdev_notifier_info_to_dev(ptr);
1937 /* Blocking events. */
1938 case SWITCHDEV_PORT_OBJ_ADD:
1939 err = switchdev_handle_port_obj_add(dev, ptr,
1940 ocelot_netdevice_dev_check,
1941 ocelot_port_obj_add);
1942 return notifier_from_errno(err);
1943 case SWITCHDEV_PORT_OBJ_DEL:
1944 err = switchdev_handle_port_obj_del(dev, ptr,
1945 ocelot_netdevice_dev_check,
1946 ocelot_port_obj_del);
1947 return notifier_from_errno(err);
1948 case SWITCHDEV_PORT_ATTR_SET:
1949 err = switchdev_handle_port_attr_set(dev, ptr,
1950 ocelot_netdevice_dev_check,
1951 ocelot_port_attr_set);
1952 return notifier_from_errno(err);
1958 struct notifier_block ocelot_switchdev_blocking_nb __read_mostly = {
1959 .notifier_call = ocelot_switchdev_blocking_event,
1961 EXPORT_SYMBOL(ocelot_switchdev_blocking_nb);
1963 int ocelot_ptp_gettime64(struct ptp_clock_info *ptp, struct timespec64 *ts)
1965 struct ocelot *ocelot = container_of(ptp, struct ocelot, ptp_info);
1966 unsigned long flags;
1971 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags);
1973 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN);
1974 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM);
1975 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE);
1976 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN);
1978 s = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_MSB, TOD_ACC_PIN) & 0xffff;
1980 s += ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN);
1981 ns = ocelot_read_rix(ocelot, PTP_PIN_TOD_NSEC, TOD_ACC_PIN);
1983 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags);
1985 /* Deal with negative values */
1986 if (ns >= 0x3ffffff0 && ns <= 0x3fffffff) {
1992 set_normalized_timespec64(ts, s, ns);
1995 EXPORT_SYMBOL(ocelot_ptp_gettime64);
1997 static int ocelot_ptp_settime64(struct ptp_clock_info *ptp,
1998 const struct timespec64 *ts)
2000 struct ocelot *ocelot = container_of(ptp, struct ocelot, ptp_info);
2001 unsigned long flags;
2004 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags);
2006 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN);
2007 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM);
2008 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_IDLE);
2010 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN);
2012 ocelot_write_rix(ocelot, lower_32_bits(ts->tv_sec), PTP_PIN_TOD_SEC_LSB,
2014 ocelot_write_rix(ocelot, upper_32_bits(ts->tv_sec), PTP_PIN_TOD_SEC_MSB,
2016 ocelot_write_rix(ocelot, ts->tv_nsec, PTP_PIN_TOD_NSEC, TOD_ACC_PIN);
2018 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN);
2019 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM);
2020 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_LOAD);
2022 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN);
2024 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags);
2028 static int ocelot_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
2030 if (delta > -(NSEC_PER_SEC / 2) && delta < (NSEC_PER_SEC / 2)) {
2031 struct ocelot *ocelot = container_of(ptp, struct ocelot, ptp_info);
2032 unsigned long flags;
2035 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags);
2037 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN);
2038 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM);
2039 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_IDLE);
2041 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN);
2043 ocelot_write_rix(ocelot, 0, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN);
2044 ocelot_write_rix(ocelot, 0, PTP_PIN_TOD_SEC_MSB, TOD_ACC_PIN);
2045 ocelot_write_rix(ocelot, delta, PTP_PIN_TOD_NSEC, TOD_ACC_PIN);
2047 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN);
2048 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM);
2049 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_DELTA);
2051 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN);
2053 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags);
2055 /* Fall back using ocelot_ptp_settime64 which is not exact. */
2056 struct timespec64 ts;
2059 ocelot_ptp_gettime64(ptp, &ts);
2061 now = ktime_to_ns(timespec64_to_ktime(ts));
2062 ts = ns_to_timespec64(now + delta);
2064 ocelot_ptp_settime64(ptp, &ts);
2069 static int ocelot_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
2071 struct ocelot *ocelot = container_of(ptp, struct ocelot, ptp_info);
2072 u32 unit = 0, direction = 0;
2073 unsigned long flags;
2076 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags);
2081 if (scaled_ppm < 0) {
2082 direction = PTP_CFG_CLK_ADJ_CFG_DIR;
2083 scaled_ppm = -scaled_ppm;
2086 adj = PSEC_PER_SEC << 16;
2087 do_div(adj, scaled_ppm);
2090 /* If the adjustment value is too large, use ns instead */
2091 if (adj >= (1L << 30)) {
2092 unit = PTP_CFG_CLK_ADJ_FREQ_NS;
2097 if (adj >= (1L << 30))
2100 ocelot_write(ocelot, unit | adj, PTP_CLK_CFG_ADJ_FREQ);
2101 ocelot_write(ocelot, PTP_CFG_CLK_ADJ_CFG_ENA | direction,
2102 PTP_CLK_CFG_ADJ_CFG);
2104 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags);
2108 ocelot_write(ocelot, 0, PTP_CLK_CFG_ADJ_CFG);
2110 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags);
2114 static struct ptp_clock_info ocelot_ptp_clock_info = {
2115 .owner = THIS_MODULE,
2116 .name = "ocelot ptp",
2117 .max_adj = 0x7fffffff,
2123 .gettime64 = ocelot_ptp_gettime64,
2124 .settime64 = ocelot_ptp_settime64,
2125 .adjtime = ocelot_ptp_adjtime,
2126 .adjfine = ocelot_ptp_adjfine,
2129 static int ocelot_init_timestamp(struct ocelot *ocelot)
2131 ocelot->ptp_info = ocelot_ptp_clock_info;
2132 ocelot->ptp_clock = ptp_clock_register(&ocelot->ptp_info, ocelot->dev);
2133 if (IS_ERR(ocelot->ptp_clock))
2134 return PTR_ERR(ocelot->ptp_clock);
2135 /* Check if PHC support is missing at the configuration level */
2136 if (!ocelot->ptp_clock)
2139 ocelot_write(ocelot, SYS_PTP_CFG_PTP_STAMP_WID(30), SYS_PTP_CFG);
2140 ocelot_write(ocelot, 0xffffffff, ANA_TABLES_PTP_ID_LOW);
2141 ocelot_write(ocelot, 0xffffffff, ANA_TABLES_PTP_ID_HIGH);
2143 ocelot_write(ocelot, PTP_CFG_MISC_PTP_EN, PTP_CFG_MISC);
2145 /* There is no device reconfiguration, PTP Rx stamping is always
2148 ocelot->hwtstamp_config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
2153 static void ocelot_init_port(struct ocelot *ocelot, int port)
2155 struct ocelot_port *ocelot_port = ocelot->ports[port];
2157 INIT_LIST_HEAD(&ocelot_port->skbs);
2159 /* Basic L2 initialization */
2161 /* Drop frames with multicast source address */
2162 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
2163 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
2164 ANA_PORT_DROP_CFG, port);
2166 /* Set default VLAN and tag type to 8021Q. */
2167 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q),
2168 REW_PORT_VLAN_CFG_PORT_TPID_M,
2169 REW_PORT_VLAN_CFG, port);
2171 /* Enable vcap lookups */
2172 ocelot_vcap_enable(ocelot, port);
2175 int ocelot_probe_port(struct ocelot *ocelot, u8 port,
2177 struct phy_device *phy)
2179 struct ocelot_port_private *priv;
2180 struct ocelot_port *ocelot_port;
2181 struct net_device *dev;
2184 dev = alloc_etherdev(sizeof(struct ocelot_port_private));
2187 SET_NETDEV_DEV(dev, ocelot->dev);
2188 priv = netdev_priv(dev);
2191 priv->chip_port = port;
2192 ocelot_port = &priv->port;
2193 ocelot_port->ocelot = ocelot;
2194 ocelot_port->regs = regs;
2195 ocelot->ports[port] = ocelot_port;
2197 dev->netdev_ops = &ocelot_port_netdev_ops;
2198 dev->ethtool_ops = &ocelot_ethtool_ops;
2200 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_RXFCS |
2202 dev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
2204 memcpy(dev->dev_addr, ocelot->base_mac, ETH_ALEN);
2205 dev->dev_addr[ETH_ALEN - 1] += port;
2206 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, ocelot_port->pvid,
2209 ocelot_init_port(ocelot, port);
2211 err = register_netdev(dev);
2213 dev_err(ocelot->dev, "register_netdev failed\n");
2219 EXPORT_SYMBOL(ocelot_probe_port);
2221 void ocelot_set_cpu_port(struct ocelot *ocelot, int cpu,
2222 enum ocelot_tag_prefix injection,
2223 enum ocelot_tag_prefix extraction)
2225 /* Configure and enable the CPU port. */
2226 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu);
2227 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU);
2228 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA |
2229 ANA_PORT_PORT_CFG_PORTID_VAL(cpu),
2230 ANA_PORT_PORT_CFG, cpu);
2232 /* If the CPU port is a physical port, set up the port in Node
2233 * Processor Interface (NPI) mode. This is the mode through which
2234 * frames can be injected from and extracted to an external CPU.
2235 * Only one port can be an NPI at the same time.
2237 if (cpu < ocelot->num_phys_ports) {
2238 ocelot_write(ocelot, QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M |
2239 QSYS_EXT_CPU_CFG_EXT_CPU_PORT(cpu),
2243 /* CPU port Injection/Extraction configuration */
2244 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE |
2245 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) |
2246 QSYS_SWITCH_PORT_MODE_PORT_ENA,
2247 QSYS_SWITCH_PORT_MODE, cpu);
2248 ocelot_write_rix(ocelot, SYS_PORT_MODE_INCL_XTR_HDR(extraction) |
2249 SYS_PORT_MODE_INCL_INJ_HDR(injection),
2250 SYS_PORT_MODE, cpu);
2252 /* Configure the CPU port to be VLAN aware */
2253 ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) |
2254 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
2255 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1),
2256 ANA_PORT_VLAN_CFG, cpu);
2260 EXPORT_SYMBOL(ocelot_set_cpu_port);
2262 int ocelot_init(struct ocelot *ocelot)
2264 char queue_name[32];
2268 ocelot->lags = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports,
2269 sizeof(u32), GFP_KERNEL);
2273 ocelot->stats = devm_kcalloc(ocelot->dev,
2274 ocelot->num_phys_ports * ocelot->num_stats,
2275 sizeof(u64), GFP_KERNEL);
2279 mutex_init(&ocelot->stats_lock);
2280 mutex_init(&ocelot->ptp_lock);
2281 spin_lock_init(&ocelot->ptp_clock_lock);
2282 snprintf(queue_name, sizeof(queue_name), "%s-stats",
2283 dev_name(ocelot->dev));
2284 ocelot->stats_queue = create_singlethread_workqueue(queue_name);
2285 if (!ocelot->stats_queue)
2288 INIT_LIST_HEAD(&ocelot->multicast);
2289 ocelot_mact_init(ocelot);
2290 ocelot_vlan_init(ocelot);
2291 ocelot_ace_init(ocelot);
2293 for (port = 0; port < ocelot->num_phys_ports; port++) {
2294 /* Clear all counters (5 groups) */
2295 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) |
2296 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f),
2300 /* Only use S-Tag */
2301 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG);
2303 /* Aggregation mode */
2304 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA |
2305 ANA_AGGR_CFG_AC_DMAC_ENA |
2306 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA |
2307 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, ANA_AGGR_CFG);
2309 /* Set MAC age time to default value. The entry is aged after
2312 ocelot_write(ocelot,
2313 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ),
2316 /* Disable learning for frames discarded by VLAN ingress filtering */
2317 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1);
2319 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */
2320 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA |
2321 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING);
2323 /* Setup flooding PGIDs */
2324 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) |
2325 ANA_FLOODING_FLD_BROADCAST(PGID_MC) |
2326 ANA_FLOODING_FLD_UNICAST(PGID_UC),
2328 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) |
2329 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) |
2330 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) |
2331 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC),
2334 for (port = 0; port < ocelot->num_phys_ports; port++) {
2335 /* Transmit the frame to the local port. */
2336 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
2337 /* Do not forward BPDU frames to the front ports. */
2338 ocelot_write_gix(ocelot,
2339 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff),
2340 ANA_PORT_CPU_FWD_BPDU_CFG,
2342 /* Ensure bridging is disabled */
2343 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port);
2346 /* Allow broadcast MAC frames. */
2347 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++) {
2348 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0));
2350 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i);
2352 ocelot_write_rix(ocelot,
2353 ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)),
2354 ANA_PGID_PGID, PGID_MC);
2355 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4);
2356 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6);
2358 /* Allow manual injection via DEVCPU_QS registers, and byte swap these
2359 * registers endianness.
2361 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP |
2362 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0);
2363 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP |
2364 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0);
2365 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) |
2366 ANA_CPUQ_CFG_CPUQ_LRN(2) |
2367 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) |
2368 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) |
2369 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) |
2370 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) |
2371 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) |
2372 ANA_CPUQ_CFG_CPUQ_IGMP(6) |
2373 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG);
2374 for (i = 0; i < 16; i++)
2375 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) |
2376 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6),
2377 ANA_CPUQ_8021_CFG, i);
2379 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats_work);
2380 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work,
2381 OCELOT_STATS_CHECK_DELAY);
2384 ret = ocelot_init_timestamp(ocelot);
2386 dev_err(ocelot->dev,
2387 "Timestamp initialization failed\n");
2394 EXPORT_SYMBOL(ocelot_init);
2396 void ocelot_deinit(struct ocelot *ocelot)
2398 struct list_head *pos, *tmp;
2399 struct ocelot_port *port;
2400 struct ocelot_skb *entry;
2403 cancel_delayed_work(&ocelot->stats_work);
2404 destroy_workqueue(ocelot->stats_queue);
2405 mutex_destroy(&ocelot->stats_lock);
2406 ocelot_ace_deinit();
2408 for (i = 0; i < ocelot->num_phys_ports; i++) {
2409 port = ocelot->ports[i];
2411 list_for_each_safe(pos, tmp, &port->skbs) {
2412 entry = list_entry(pos, struct ocelot_skb, head);
2415 dev_kfree_skb_any(entry->skb);
2420 EXPORT_SYMBOL(ocelot_deinit);
2422 MODULE_LICENSE("Dual MIT/GPL");