drivers/net/ethernet/mellanox/mlxsw/switchx2.c

   1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
   2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
   3
   4 #include <linux/kernel.h>
   5 #include <linux/module.h>
   6 #include <linux/types.h>
   7 #include <linux/pci.h>
   8 #include <linux/netdevice.h>
   9 #include <linux/etherdevice.h>
  10 #include <linux/slab.h>
  11 #include <linux/device.h>
  12 #include <linux/skbuff.h>
  13 #include <linux/if_vlan.h>
  14
  15 #include "pci.h"
  16 #include "core.h"
  17 #include "reg.h"
  18 #include "port.h"
  19 #include "trap.h"
  20 #include "txheader.h"
  21 #include "ib.h"
  22
  23 static const char mlxsw_sx_driver_name[] = "mlxsw_switchx2";
  24 static const char mlxsw_sx_driver_version[] = "1.0";
  25
  26 struct mlxsw_sx_port;
  27
  28 struct mlxsw_sx {
  29         struct mlxsw_sx_port **ports;
  30         struct mlxsw_core *core;
  31         const struct mlxsw_bus_info *bus_info;
  32         u8 hw_id[ETH_ALEN];
  33 };
  34
  35 struct mlxsw_sx_port_pcpu_stats {
  36         u64                     rx_packets;
  37         u64                     rx_bytes;
  38         u64                     tx_packets;
  39         u64                     tx_bytes;
  40         struct u64_stats_sync   syncp;
  41         u32                     tx_dropped;
  42 };
  43
  44 struct mlxsw_sx_port {
  45         struct net_device *dev;
  46         struct mlxsw_sx_port_pcpu_stats __percpu *pcpu_stats;
  47         struct mlxsw_sx *mlxsw_sx;
  48         u8 local_port;
  49         struct {
  50                 u8 module;
  51         } mapping;
  52 };
  53
  54 /* tx_hdr_version
  55  * Tx header version.
  56  * Must be set to 0.
  57  */
  58 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
  59
  60 /* tx_hdr_ctl
  61  * Packet control type.
  62  * 0 - Ethernet control (e.g. EMADs, LACP)
  63  * 1 - Ethernet data
  64  */
  65 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
  66
  67 /* tx_hdr_proto
  68  * Packet protocol type. Must be set to 1 (Ethernet).
  69  */
  70 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
  71
  72 /* tx_hdr_etclass
  73  * Egress TClass to be used on the egress device on the egress port.
  74  * The MSB is specified in the 'ctclass3' field.
  75  * Range is 0-15, where 15 is the highest priority.
  76  */
  77 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 18, 3);
  78
  79 /* tx_hdr_swid
  80  * Switch partition ID.
  81  */
  82 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
  83
  84 /* tx_hdr_port_mid
  85  * Destination local port for unicast packets.
  86  * Destination multicast ID for multicast packets.
  87  *
  88  * Control packets are directed to a specific egress port, while data
  89  * packets are transmitted through the CPU port (0) into the switch partition,
  90  * where forwarding rules are applied.
  91  */
  92 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
  93
  94 /* tx_hdr_ctclass3
  95  * See field 'etclass'.
  96  */
  97 MLXSW_ITEM32(tx, hdr, ctclass3, 0x04, 14, 1);
  98
  99 /* tx_hdr_rdq
 100  * RDQ for control packets sent to remote CPU.
 101  * Must be set to 0x1F for EMADs, otherwise 0.
 102  */
 103 MLXSW_ITEM32(tx, hdr, rdq, 0x04, 9, 5);
 104
 105 /* tx_hdr_cpu_sig
 106  * Signature control for packets going to CPU. Must be set to 0.
 107  */
 108 MLXSW_ITEM32(tx, hdr, cpu_sig, 0x04, 0, 9);
 109
 110 /* tx_hdr_sig
 111  * Stacking protocl signature. Must be set to 0xE0E0.
 112  */
 113 MLXSW_ITEM32(tx, hdr, sig, 0x0C, 16, 16);
 114
 115 /* tx_hdr_stclass
 116  * Stacking TClass.
 117  */
 118 MLXSW_ITEM32(tx, hdr, stclass, 0x0C, 13, 3);
 119
 120 /* tx_hdr_emad
 121  * EMAD bit. Must be set for EMADs.
 122  */
 123 MLXSW_ITEM32(tx, hdr, emad, 0x0C, 5, 1);
 124
 125 /* tx_hdr_type
 126  * 0 - Data packets
 127  * 6 - Control packets
 128  */
 129 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
 130
 131 static void mlxsw_sx_txhdr_construct(struct sk_buff *skb,
 132                                      const struct mlxsw_tx_info *tx_info)
 133 {
 134         char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
 135         bool is_emad = tx_info->is_emad;
 136
 137         memset(txhdr, 0, MLXSW_TXHDR_LEN);
 138
 139         /* We currently set default values for the egress tclass (QoS). */
 140         mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_0);
 141         mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
 142         mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
 143         mlxsw_tx_hdr_etclass_set(txhdr, is_emad ? MLXSW_TXHDR_ETCLASS_6 :
 144                                                   MLXSW_TXHDR_ETCLASS_5);
 145         mlxsw_tx_hdr_swid_set(txhdr, 0);
 146         mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
 147         mlxsw_tx_hdr_ctclass3_set(txhdr, MLXSW_TXHDR_CTCLASS3);
 148         mlxsw_tx_hdr_rdq_set(txhdr, is_emad ? MLXSW_TXHDR_RDQ_EMAD :
 149                                               MLXSW_TXHDR_RDQ_OTHER);
 150         mlxsw_tx_hdr_cpu_sig_set(txhdr, MLXSW_TXHDR_CPU_SIG);
 151         mlxsw_tx_hdr_sig_set(txhdr, MLXSW_TXHDR_SIG);
 152         mlxsw_tx_hdr_stclass_set(txhdr, MLXSW_TXHDR_STCLASS_NONE);
 153         mlxsw_tx_hdr_emad_set(txhdr, is_emad ? MLXSW_TXHDR_EMAD :
 154                                                MLXSW_TXHDR_NOT_EMAD);
 155         mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
 156 }
 157
 158 static int mlxsw_sx_port_admin_status_set(struct mlxsw_sx_port *mlxsw_sx_port,
 159                                           bool is_up)
 160 {
 161         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 162         char paos_pl[MLXSW_REG_PAOS_LEN];
 163
 164         mlxsw_reg_paos_pack(paos_pl, mlxsw_sx_port->local_port,
 165                             is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
 166                             MLXSW_PORT_ADMIN_STATUS_DOWN);
 167         return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(paos), paos_pl);
 168 }
 169
 170 static int mlxsw_sx_port_oper_status_get(struct mlxsw_sx_port *mlxsw_sx_port,
 171                                          bool *p_is_up)
 172 {
 173         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 174         char paos_pl[MLXSW_REG_PAOS_LEN];
 175         u8 oper_status;
 176         int err;
 177
 178         mlxsw_reg_paos_pack(paos_pl, mlxsw_sx_port->local_port, 0);
 179         err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(paos), paos_pl);
 180         if (err)
 181                 return err;
 182         oper_status = mlxsw_reg_paos_oper_status_get(paos_pl);
 183         *p_is_up = oper_status == MLXSW_PORT_ADMIN_STATUS_UP ? true : false;
 184         return 0;
 185 }
 186
 187 static int __mlxsw_sx_port_mtu_set(struct mlxsw_sx_port *mlxsw_sx_port,
 188                                    u16 mtu)
 189 {
 190         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 191         char pmtu_pl[MLXSW_REG_PMTU_LEN];
 192         int max_mtu;
 193         int err;
 194
 195         mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sx_port->local_port, 0);
 196         err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(pmtu), pmtu_pl);
 197         if (err)
 198                 return err;
 199         max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
 200
 201         if (mtu > max_mtu)
 202                 return -EINVAL;
 203
 204         mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sx_port->local_port, mtu);
 205         return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(pmtu), pmtu_pl);
 206 }
 207
 208 static int mlxsw_sx_port_mtu_eth_set(struct mlxsw_sx_port *mlxsw_sx_port,
 209                                      u16 mtu)
 210 {
 211         mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
 212         return __mlxsw_sx_port_mtu_set(mlxsw_sx_port, mtu);
 213 }
 214
 215 static int mlxsw_sx_port_mtu_ib_set(struct mlxsw_sx_port *mlxsw_sx_port,
 216                                     u16 mtu)
 217 {
 218         return __mlxsw_sx_port_mtu_set(mlxsw_sx_port, mtu);
 219 }
 220
 221 static int mlxsw_sx_port_ib_port_set(struct mlxsw_sx_port *mlxsw_sx_port,
 222                                      u8 ib_port)
 223 {
 224         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 225         char plib_pl[MLXSW_REG_PLIB_LEN] = {0};
 226         int err;
 227
 228         mlxsw_reg_plib_local_port_set(plib_pl, mlxsw_sx_port->local_port);
 229         mlxsw_reg_plib_ib_port_set(plib_pl, ib_port);
 230         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(plib), plib_pl);
 231         return err;
 232 }
 233
 234 static int mlxsw_sx_port_swid_set(struct mlxsw_sx_port *mlxsw_sx_port, u8 swid)
 235 {
 236         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 237         char pspa_pl[MLXSW_REG_PSPA_LEN];
 238
 239         mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sx_port->local_port);
 240         return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(pspa), pspa_pl);
 241 }
 242
 243 static int
 244 mlxsw_sx_port_system_port_mapping_set(struct mlxsw_sx_port *mlxsw_sx_port)
 245 {
 246         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 247         char sspr_pl[MLXSW_REG_SSPR_LEN];
 248
 249         mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sx_port->local_port);
 250         return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sspr), sspr_pl);
 251 }
 252
 253 static int mlxsw_sx_port_module_info_get(struct mlxsw_sx *mlxsw_sx,
 254                                          u8 local_port, u8 *p_module,
 255                                          u8 *p_width)
 256 {
 257         char pmlp_pl[MLXSW_REG_PMLP_LEN];
 258         int err;
 259
 260         mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
 261         err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(pmlp), pmlp_pl);
 262         if (err)
 263                 return err;
 264         *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
 265         *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
 266         return 0;
 267 }
 268
 269 static int mlxsw_sx_port_open(struct net_device *dev)
 270 {
 271         struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
 272         int err;
 273
 274         err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, true);
 275         if (err)
 276                 return err;
 277         netif_start_queue(dev);
 278         return 0;
 279 }
 280
 281 static int mlxsw_sx_port_stop(struct net_device *dev)
 282 {
 283         struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
 284
 285         netif_stop_queue(dev);
 286         return mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
 287 }
 288
 289 static netdev_tx_t mlxsw_sx_port_xmit(struct sk_buff *skb,
 290                                       struct net_device *dev)
 291 {
 292         struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
 293         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 294         struct mlxsw_sx_port_pcpu_stats *pcpu_stats;
 295         const struct mlxsw_tx_info tx_info = {
 296                 .local_port = mlxsw_sx_port->local_port,
 297                 .is_emad = false,
 298         };
 299         u64 len;
 300         int err;
 301
 302         if (mlxsw_core_skb_transmit_busy(mlxsw_sx->core, &tx_info))
 303                 return NETDEV_TX_BUSY;
 304
 305         if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
 306                 struct sk_buff *skb_orig = skb;
 307
 308                 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
 309                 if (!skb) {
 310                         this_cpu_inc(mlxsw_sx_port->pcpu_stats->tx_dropped);
 311                         dev_kfree_skb_any(skb_orig);
 312                         return NETDEV_TX_OK;
 313                 }
 314                 dev_consume_skb_any(skb_orig);
 315         }
 316         mlxsw_sx_txhdr_construct(skb, &tx_info);
 317         /* TX header is consumed by HW on the way so we shouldn't count its
 318          * bytes as being sent.
 319          */
 320         len = skb->len - MLXSW_TXHDR_LEN;
 321         /* Due to a race we might fail here because of a full queue. In that
 322          * unlikely case we simply drop the packet.
 323          */
 324         err = mlxsw_core_skb_transmit(mlxsw_sx->core, skb, &tx_info);
 325
 326         if (!err) {
 327                 pcpu_stats = this_cpu_ptr(mlxsw_sx_port->pcpu_stats);
 328                 u64_stats_update_begin(&pcpu_stats->syncp);
 329                 pcpu_stats->tx_packets++;
 330                 pcpu_stats->tx_bytes += len;
 331                 u64_stats_update_end(&pcpu_stats->syncp);
 332         } else {
 333                 this_cpu_inc(mlxsw_sx_port->pcpu_stats->tx_dropped);
 334                 dev_kfree_skb_any(skb);
 335         }
 336         return NETDEV_TX_OK;
 337 }
 338
 339 static int mlxsw_sx_port_change_mtu(struct net_device *dev, int mtu)
 340 {
 341         struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
 342         int err;
 343
 344         err = mlxsw_sx_port_mtu_eth_set(mlxsw_sx_port, mtu);
 345         if (err)
 346                 return err;
 347         dev->mtu = mtu;
 348         return 0;
 349 }
 350
 351 static void
 352 mlxsw_sx_port_get_stats64(struct net_device *dev,
 353                           struct rtnl_link_stats64 *stats)
 354 {
 355         struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
 356         struct mlxsw_sx_port_pcpu_stats *p;
 357         u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
 358         u32 tx_dropped = 0;
 359         unsigned int start;
 360         int i;
 361
 362         for_each_possible_cpu(i) {
 363                 p = per_cpu_ptr(mlxsw_sx_port->pcpu_stats, i);
 364                 do {
 365                         start = u64_stats_fetch_begin_irq(&p->syncp);
 366                         rx_packets      = p->rx_packets;
 367                         rx_bytes        = p->rx_bytes;
 368                         tx_packets      = p->tx_packets;
 369                         tx_bytes        = p->tx_bytes;
 370                 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
 371
 372                 stats->rx_packets       += rx_packets;
 373                 stats->rx_bytes         += rx_bytes;
 374                 stats->tx_packets       += tx_packets;
 375                 stats->tx_bytes         += tx_bytes;
 376                 /* tx_dropped is u32, updated without syncp protection. */
 377                 tx_dropped      += p->tx_dropped;
 378         }
 379         stats->tx_dropped       = tx_dropped;
 380 }
 381
 382 static int mlxsw_sx_port_get_phys_port_name(struct net_device *dev, char *name,
 383                                             size_t len)
 384 {
 385         struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
 386
 387         return mlxsw_core_port_get_phys_port_name(mlxsw_sx_port->mlxsw_sx->core,
 388                                                   mlxsw_sx_port->local_port,
 389                                                   name, len);
 390 }
 391
 392 static int mlxsw_sx_port_get_port_parent_id(struct net_device *dev,
 393                                             struct netdev_phys_item_id *ppid)
 394 {
 395         struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
 396         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 397
 398         ppid->id_len = sizeof(mlxsw_sx->hw_id);
 399         memcpy(&ppid->id, &mlxsw_sx->hw_id, ppid->id_len);
 400
 401         return 0;
 402 }
 403
 404 static const struct net_device_ops mlxsw_sx_port_netdev_ops = {
 405         .ndo_open               = mlxsw_sx_port_open,
 406         .ndo_stop               = mlxsw_sx_port_stop,
 407         .ndo_start_xmit         = mlxsw_sx_port_xmit,
 408         .ndo_change_mtu         = mlxsw_sx_port_change_mtu,
 409         .ndo_get_stats64        = mlxsw_sx_port_get_stats64,
 410         .ndo_get_phys_port_name = mlxsw_sx_port_get_phys_port_name,
 411         .ndo_get_port_parent_id = mlxsw_sx_port_get_port_parent_id,
 412 };
 413
 414 static void mlxsw_sx_port_get_drvinfo(struct net_device *dev,
 415                                       struct ethtool_drvinfo *drvinfo)
 416 {
 417         struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
 418         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 419
 420         strlcpy(drvinfo->driver, mlxsw_sx_driver_name, sizeof(drvinfo->driver));
 421         strlcpy(drvinfo->version, mlxsw_sx_driver_version,
 422                 sizeof(drvinfo->version));
 423         snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
 424                  "%d.%d.%d",
 425                  mlxsw_sx->bus_info->fw_rev.major,
 426                  mlxsw_sx->bus_info->fw_rev.minor,
 427                  mlxsw_sx->bus_info->fw_rev.subminor);
 428         strlcpy(drvinfo->bus_info, mlxsw_sx->bus_info->device_name,
 429                 sizeof(drvinfo->bus_info));
 430 }
 431
 432 struct mlxsw_sx_port_hw_stats {
 433         char str[ETH_GSTRING_LEN];
 434         u64 (*getter)(const char *payload);
 435 };
 436
 437 static const struct mlxsw_sx_port_hw_stats mlxsw_sx_port_hw_stats[] = {
 438         {
 439                 .str = "a_frames_transmitted_ok",
 440                 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
 441         },
 442         {
 443                 .str = "a_frames_received_ok",
 444                 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
 445         },
 446         {
 447                 .str = "a_frame_check_sequence_errors",
 448                 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
 449         },
 450         {
 451                 .str = "a_alignment_errors",
 452                 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
 453         },
 454         {
 455                 .str = "a_octets_transmitted_ok",
 456                 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
 457         },
 458         {
 459                 .str = "a_octets_received_ok",
 460                 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
 461         },
 462         {
 463                 .str = "a_multicast_frames_xmitted_ok",
 464                 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
 465         },
 466         {
 467                 .str = "a_broadcast_frames_xmitted_ok",
 468                 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
 469         },
 470         {
 471                 .str = "a_multicast_frames_received_ok",
 472                 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
 473         },
 474         {
 475                 .str = "a_broadcast_frames_received_ok",
 476                 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
 477         },
 478         {
 479                 .str = "a_in_range_length_errors",
 480                 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
 481         },
 482         {
 483                 .str = "a_out_of_range_length_field",
 484                 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
 485         },
 486         {
 487                 .str = "a_frame_too_long_errors",
 488                 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
 489         },
 490         {
 491                 .str = "a_symbol_error_during_carrier",
 492                 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
 493         },
 494         {
 495                 .str = "a_mac_control_frames_transmitted",
 496                 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
 497         },
 498         {
 499                 .str = "a_mac_control_frames_received",
 500                 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
 501         },
 502         {
 503                 .str = "a_unsupported_opcodes_received",
 504                 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
 505         },
 506         {
 507                 .str = "a_pause_mac_ctrl_frames_received",
 508                 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
 509         },
 510         {
 511                 .str = "a_pause_mac_ctrl_frames_xmitted",
 512                 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
 513         },
 514 };
 515
 516 #define MLXSW_SX_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sx_port_hw_stats)
 517
 518 static void mlxsw_sx_port_get_strings(struct net_device *dev,
 519                                       u32 stringset, u8 *data)
 520 {
 521         u8 *p = data;
 522         int i;
 523
 524         switch (stringset) {
 525         case ETH_SS_STATS:
 526                 for (i = 0; i < MLXSW_SX_PORT_HW_STATS_LEN; i++) {
 527                         memcpy(p, mlxsw_sx_port_hw_stats[i].str,
 528                                ETH_GSTRING_LEN);
 529                         p += ETH_GSTRING_LEN;
 530                 }
 531                 break;
 532         }
 533 }
 534
 535 static void mlxsw_sx_port_get_stats(struct net_device *dev,
 536                                     struct ethtool_stats *stats, u64 *data)
 537 {
 538         struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
 539         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 540         char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
 541         int i;
 542         int err;
 543
 544         mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sx_port->local_port,
 545                              MLXSW_REG_PPCNT_IEEE_8023_CNT, 0);
 546         err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ppcnt), ppcnt_pl);
 547         for (i = 0; i < MLXSW_SX_PORT_HW_STATS_LEN; i++)
 548                 data[i] = !err ? mlxsw_sx_port_hw_stats[i].getter(ppcnt_pl) : 0;
 549 }
 550
 551 static int mlxsw_sx_port_get_sset_count(struct net_device *dev, int sset)
 552 {
 553         switch (sset) {
 554         case ETH_SS_STATS:
 555                 return MLXSW_SX_PORT_HW_STATS_LEN;
 556         default:
 557                 return -EOPNOTSUPP;
 558         }
 559 }
 560
 561 struct mlxsw_sx_port_link_mode {
 562         u32 mask;
 563         u32 supported;
 564         u32 advertised;
 565         u32 speed;
 566 };
 567
 568 static const struct mlxsw_sx_port_link_mode mlxsw_sx_port_link_mode[] = {
 569         {
 570                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
 571                 .supported      = SUPPORTED_100baseT_Full,
 572                 .advertised     = ADVERTISED_100baseT_Full,
 573                 .speed          = 100,
 574         },
 575         {
 576                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX,
 577                 .speed          = 100,
 578         },
 579         {
 580                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
 581                                   MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
 582                 .supported      = SUPPORTED_1000baseKX_Full,
 583                 .advertised     = ADVERTISED_1000baseKX_Full,
 584                 .speed          = 1000,
 585         },
 586         {
 587                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
 588                 .supported      = SUPPORTED_10000baseT_Full,
 589                 .advertised     = ADVERTISED_10000baseT_Full,
 590                 .speed          = 10000,
 591         },
 592         {
 593                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
 594                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
 595                 .supported      = SUPPORTED_10000baseKX4_Full,
 596                 .advertised     = ADVERTISED_10000baseKX4_Full,
 597                 .speed          = 10000,
 598         },
 599         {
 600                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
 601                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
 602                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
 603                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
 604                 .supported      = SUPPORTED_10000baseKR_Full,
 605                 .advertised     = ADVERTISED_10000baseKR_Full,
 606                 .speed          = 10000,
 607         },
 608         {
 609                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
 610                 .supported      = SUPPORTED_20000baseKR2_Full,
 611                 .advertised     = ADVERTISED_20000baseKR2_Full,
 612                 .speed          = 20000,
 613         },
 614         {
 615                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
 616                 .supported      = SUPPORTED_40000baseCR4_Full,
 617                 .advertised     = ADVERTISED_40000baseCR4_Full,
 618                 .speed          = 40000,
 619         },
 620         {
 621                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
 622                 .supported      = SUPPORTED_40000baseKR4_Full,
 623                 .advertised     = ADVERTISED_40000baseKR4_Full,
 624                 .speed          = 40000,
 625         },
 626         {
 627                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
 628                 .supported      = SUPPORTED_40000baseSR4_Full,
 629                 .advertised     = ADVERTISED_40000baseSR4_Full,
 630                 .speed          = 40000,
 631         },
 632         {
 633                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
 634                 .supported      = SUPPORTED_40000baseLR4_Full,
 635                 .advertised     = ADVERTISED_40000baseLR4_Full,
 636                 .speed          = 40000,
 637         },
 638         {
 639                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR |
 640                                   MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR |
 641                                   MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
 642                 .speed          = 25000,
 643         },
 644         {
 645                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 |
 646                                   MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 |
 647                                   MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
 648                 .speed          = 50000,
 649         },
 650         {
 651                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
 652                 .supported      = SUPPORTED_56000baseKR4_Full,
 653                 .advertised     = ADVERTISED_56000baseKR4_Full,
 654                 .speed          = 56000,
 655         },
 656         {
 657                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 |
 658                                   MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
 659                                   MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
 660                                   MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
 661                 .speed          = 100000,
 662         },
 663 };
 664
 665 #define MLXSW_SX_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sx_port_link_mode)
 666 #define MLXSW_SX_PORT_BASE_SPEED 10000 /* Mb/s */
 667
 668 static u32 mlxsw_sx_from_ptys_supported_port(u32 ptys_eth_proto)
 669 {
 670         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
 671                               MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
 672                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
 673                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
 674                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
 675                               MLXSW_REG_PTYS_ETH_SPEED_SGMII))
 676                 return SUPPORTED_FIBRE;
 677
 678         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
 679                               MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
 680                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
 681                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
 682                               MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
 683                 return SUPPORTED_Backplane;
 684         return 0;
 685 }
 686
 687 static u32 mlxsw_sx_from_ptys_supported_link(u32 ptys_eth_proto)
 688 {
 689         u32 modes = 0;
 690         int i;
 691
 692         for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
 693                 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask)
 694                         modes |= mlxsw_sx_port_link_mode[i].supported;
 695         }
 696         return modes;
 697 }
 698
 699 static u32 mlxsw_sx_from_ptys_advert_link(u32 ptys_eth_proto)
 700 {
 701         u32 modes = 0;
 702         int i;
 703
 704         for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
 705                 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask)
 706                         modes |= mlxsw_sx_port_link_mode[i].advertised;
 707         }
 708         return modes;
 709 }
 710
 711 static void mlxsw_sx_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
 712                                             struct ethtool_link_ksettings *cmd)
 713 {
 714         u32 speed = SPEED_UNKNOWN;
 715         u8 duplex = DUPLEX_UNKNOWN;
 716         int i;
 717
 718         if (!carrier_ok)
 719                 goto out;
 720
 721         for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
 722                 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask) {
 723                         speed = mlxsw_sx_port_link_mode[i].speed;
 724                         duplex = DUPLEX_FULL;
 725                         break;
 726                 }
 727         }
 728 out:
 729         cmd->base.speed = speed;
 730         cmd->base.duplex = duplex;
 731 }
 732
 733 static u8 mlxsw_sx_port_connector_port(u32 ptys_eth_proto)
 734 {
 735         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
 736                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
 737                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
 738                               MLXSW_REG_PTYS_ETH_SPEED_SGMII))
 739                 return PORT_FIBRE;
 740
 741         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
 742                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
 743                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
 744                 return PORT_DA;
 745
 746         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
 747                               MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
 748                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
 749                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
 750                 return PORT_NONE;
 751
 752         return PORT_OTHER;
 753 }
 754
 755 static int
 756 mlxsw_sx_port_get_link_ksettings(struct net_device *dev,
 757                                  struct ethtool_link_ksettings *cmd)
 758 {
 759         struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
 760         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 761         char ptys_pl[MLXSW_REG_PTYS_LEN];
 762         u32 eth_proto_cap;
 763         u32 eth_proto_admin;
 764         u32 eth_proto_oper;
 765         u32 supported, advertising, lp_advertising;
 766         int err;
 767
 768         mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sx_port->local_port, 0, false);
 769         err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
 770         if (err) {
 771                 netdev_err(dev, "Failed to get proto");
 772                 return err;
 773         }
 774         mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap,
 775                                   &eth_proto_admin, &eth_proto_oper);
 776
 777         supported = mlxsw_sx_from_ptys_supported_port(eth_proto_cap) |
 778                          mlxsw_sx_from_ptys_supported_link(eth_proto_cap) |
 779                          SUPPORTED_Pause | SUPPORTED_Asym_Pause;
 780         advertising = mlxsw_sx_from_ptys_advert_link(eth_proto_admin);
 781         mlxsw_sx_from_ptys_speed_duplex(netif_carrier_ok(dev),
 782                                         eth_proto_oper, cmd);
 783
 784         eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
 785         cmd->base.port = mlxsw_sx_port_connector_port(eth_proto_oper);
 786         lp_advertising = mlxsw_sx_from_ptys_advert_link(eth_proto_oper);
 787
 788         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
 789                                                 supported);
 790         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
 791                                                 advertising);
 792         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising,
 793                                                 lp_advertising);
 794
 795         return 0;
 796 }
 797
 798 static u32 mlxsw_sx_to_ptys_advert_link(u32 advertising)
 799 {
 800         u32 ptys_proto = 0;
 801         int i;
 802
 803         for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
 804                 if (advertising & mlxsw_sx_port_link_mode[i].advertised)
 805                         ptys_proto |= mlxsw_sx_port_link_mode[i].mask;
 806         }
 807         return ptys_proto;
 808 }
 809
 810 static u32 mlxsw_sx_to_ptys_speed(u32 speed)
 811 {
 812         u32 ptys_proto = 0;
 813         int i;
 814
 815         for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
 816                 if (speed == mlxsw_sx_port_link_mode[i].speed)
 817                         ptys_proto |= mlxsw_sx_port_link_mode[i].mask;
 818         }
 819         return ptys_proto;
 820 }
 821
 822 static u32 mlxsw_sx_to_ptys_upper_speed(u32 upper_speed)
 823 {
 824         u32 ptys_proto = 0;
 825         int i;
 826
 827         for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
 828                 if (mlxsw_sx_port_link_mode[i].speed <= upper_speed)
 829                         ptys_proto |= mlxsw_sx_port_link_mode[i].mask;
 830         }
 831         return ptys_proto;
 832 }
 833
 834 static int
 835 mlxsw_sx_port_set_link_ksettings(struct net_device *dev,
 836                                  const struct ethtool_link_ksettings *cmd)
 837 {
 838         struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
 839         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 840         char ptys_pl[MLXSW_REG_PTYS_LEN];
 841         u32 speed;
 842         u32 eth_proto_new;
 843         u32 eth_proto_cap;
 844         u32 eth_proto_admin;
 845         u32 advertising;
 846         bool is_up;
 847         int err;
 848
 849         speed = cmd->base.speed;
 850
 851         ethtool_convert_link_mode_to_legacy_u32(&advertising,
 852                                                 cmd->link_modes.advertising);
 853
 854         eth_proto_new = cmd->base.autoneg == AUTONEG_ENABLE ?
 855                 mlxsw_sx_to_ptys_advert_link(advertising) :
 856                 mlxsw_sx_to_ptys_speed(speed);
 857
 858         mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sx_port->local_port, 0, false);
 859         err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
 860         if (err) {
 861                 netdev_err(dev, "Failed to get proto");
 862                 return err;
 863         }
 864         mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin,
 865                                   NULL);
 866
 867         eth_proto_new = eth_proto_new & eth_proto_cap;
 868         if (!eth_proto_new) {
 869                 netdev_err(dev, "Not supported proto admin requested");
 870                 return -EINVAL;
 871         }
 872         if (eth_proto_new == eth_proto_admin)
 873                 return 0;
 874
 875         mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sx_port->local_port,
 876                                 eth_proto_new, true);
 877         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
 878         if (err) {
 879                 netdev_err(dev, "Failed to set proto admin");
 880                 return err;
 881         }
 882
 883         err = mlxsw_sx_port_oper_status_get(mlxsw_sx_port, &is_up);
 884         if (err) {
 885                 netdev_err(dev, "Failed to get oper status");
 886                 return err;
 887         }
 888         if (!is_up)
 889                 return 0;
 890
 891         err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
 892         if (err) {
 893                 netdev_err(dev, "Failed to set admin status");
 894                 return err;
 895         }
 896
 897         err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, true);
 898         if (err) {
 899                 netdev_err(dev, "Failed to set admin status");
 900                 return err;
 901         }
 902
 903         return 0;
 904 }
 905
 906 static const struct ethtool_ops mlxsw_sx_port_ethtool_ops = {
 907         .get_drvinfo            = mlxsw_sx_port_get_drvinfo,
 908         .get_link               = ethtool_op_get_link,
 909         .get_strings            = mlxsw_sx_port_get_strings,
 910         .get_ethtool_stats      = mlxsw_sx_port_get_stats,
 911         .get_sset_count         = mlxsw_sx_port_get_sset_count,
 912         .get_link_ksettings     = mlxsw_sx_port_get_link_ksettings,
 913         .set_link_ksettings     = mlxsw_sx_port_set_link_ksettings,
 914 };
 915
 916 static int mlxsw_sx_hw_id_get(struct mlxsw_sx *mlxsw_sx)
 917 {
 918         char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
 919         int err;
 920
 921         err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(spad), spad_pl);
 922         if (err)
 923                 return err;
 924         mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sx->hw_id);
 925         return 0;
 926 }
 927
 928 static int mlxsw_sx_port_dev_addr_get(struct mlxsw_sx_port *mlxsw_sx_port)
 929 {
 930         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 931         struct net_device *dev = mlxsw_sx_port->dev;
 932         char ppad_pl[MLXSW_REG_PPAD_LEN];
 933         int err;
 934
 935         mlxsw_reg_ppad_pack(ppad_pl, false, 0);
 936         err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ppad), ppad_pl);
 937         if (err)
 938                 return err;
 939         mlxsw_reg_ppad_mac_memcpy_from(ppad_pl, dev->dev_addr);
 940         /* The last byte value in base mac address is guaranteed
 941          * to be such it does not overflow when adding local_port
 942          * value.
 943          */
 944         dev->dev_addr[ETH_ALEN - 1] += mlxsw_sx_port->local_port;
 945         return 0;
 946 }
 947
 948 static int mlxsw_sx_port_stp_state_set(struct mlxsw_sx_port *mlxsw_sx_port,
 949                                        u16 vid, enum mlxsw_reg_spms_state state)
 950 {
 951         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 952         char *spms_pl;
 953         int err;
 954
 955         spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
 956         if (!spms_pl)
 957                 return -ENOMEM;
 958         mlxsw_reg_spms_pack(spms_pl, mlxsw_sx_port->local_port);
 959         mlxsw_reg_spms_vid_pack(spms_pl, vid, state);
 960         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(spms), spms_pl);
 961         kfree(spms_pl);
 962         return err;
 963 }
 964
 965 static int mlxsw_sx_port_ib_speed_set(struct mlxsw_sx_port *mlxsw_sx_port,
 966                                       u16 speed, u16 width)
 967 {
 968         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 969         char ptys_pl[MLXSW_REG_PTYS_LEN];
 970
 971         mlxsw_reg_ptys_ib_pack(ptys_pl, mlxsw_sx_port->local_port, speed,
 972                                width);
 973         return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
 974 }
 975
 976 static int
 977 mlxsw_sx_port_speed_by_width_set(struct mlxsw_sx_port *mlxsw_sx_port, u8 width)
 978 {
 979         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 980         u32 upper_speed = MLXSW_SX_PORT_BASE_SPEED * width;
 981         char ptys_pl[MLXSW_REG_PTYS_LEN];
 982         u32 eth_proto_admin;
 983
 984         eth_proto_admin = mlxsw_sx_to_ptys_upper_speed(upper_speed);
 985         mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sx_port->local_port,
 986                                 eth_proto_admin, true);
 987         return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
 988 }
 989
 990 static int
 991 mlxsw_sx_port_mac_learning_mode_set(struct mlxsw_sx_port *mlxsw_sx_port,
 992                                     enum mlxsw_reg_spmlr_learn_mode mode)
 993 {
 994         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 995         char spmlr_pl[MLXSW_REG_SPMLR_LEN];
 996
 997         mlxsw_reg_spmlr_pack(spmlr_pl, mlxsw_sx_port->local_port, mode);
 998         return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(spmlr), spmlr_pl);
 999 }
1000
1001 static int __mlxsw_sx_port_eth_create(struct mlxsw_sx *mlxsw_sx, u8 local_port,
1002                                       u8 module, u8 width)
1003 {
1004         struct mlxsw_sx_port *mlxsw_sx_port;
1005         struct net_device *dev;
1006         int err;
1007
1008         dev = alloc_etherdev(sizeof(struct mlxsw_sx_port));
1009         if (!dev)
1010                 return -ENOMEM;
1011         SET_NETDEV_DEV(dev, mlxsw_sx->bus_info->dev);
1012         mlxsw_sx_port = netdev_priv(dev);
1013         mlxsw_sx_port->dev = dev;
1014         mlxsw_sx_port->mlxsw_sx = mlxsw_sx;
1015         mlxsw_sx_port->local_port = local_port;
1016         mlxsw_sx_port->mapping.module = module;
1017
1018         mlxsw_sx_port->pcpu_stats =
1019                 netdev_alloc_pcpu_stats(struct mlxsw_sx_port_pcpu_stats);
1020         if (!mlxsw_sx_port->pcpu_stats) {
1021                 err = -ENOMEM;
1022                 goto err_alloc_stats;
1023         }
1024
1025         dev->netdev_ops = &mlxsw_sx_port_netdev_ops;
1026         dev->ethtool_ops = &mlxsw_sx_port_ethtool_ops;
1027
1028         err = mlxsw_sx_port_dev_addr_get(mlxsw_sx_port);
1029         if (err) {
1030                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Unable to get port mac address\n",
1031                         mlxsw_sx_port->local_port);
1032                 goto err_dev_addr_get;
1033         }
1034
1035         netif_carrier_off(dev);
1036
1037         dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
1038                          NETIF_F_VLAN_CHALLENGED;
1039
1040         dev->min_mtu = 0;
1041         dev->max_mtu = ETH_MAX_MTU;
1042
1043         /* Each packet needs to have a Tx header (metadata) on top all other
1044          * headers.
1045          */
1046         dev->needed_headroom = MLXSW_TXHDR_LEN;
1047
1048         err = mlxsw_sx_port_system_port_mapping_set(mlxsw_sx_port);
1049         if (err) {
1050                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set system port mapping\n",
1051                         mlxsw_sx_port->local_port);
1052                 goto err_port_system_port_mapping_set;
1053         }
1054
1055         err = mlxsw_sx_port_swid_set(mlxsw_sx_port, 0);
1056         if (err) {
1057                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set SWID\n",
1058                         mlxsw_sx_port->local_port);
1059                 goto err_port_swid_set;
1060         }
1061
1062         err = mlxsw_sx_port_speed_by_width_set(mlxsw_sx_port, width);
1063         if (err) {
1064                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set speed\n",
1065                         mlxsw_sx_port->local_port);
1066                 goto err_port_speed_set;
1067         }
1068
1069         err = mlxsw_sx_port_mtu_eth_set(mlxsw_sx_port, ETH_DATA_LEN);
1070         if (err) {
1071                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set MTU\n",
1072                         mlxsw_sx_port->local_port);
1073                 goto err_port_mtu_set;
1074         }
1075
1076         err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
1077         if (err)
1078                 goto err_port_admin_status_set;
1079
1080         err = mlxsw_sx_port_stp_state_set(mlxsw_sx_port,
1081                                           MLXSW_PORT_DEFAULT_VID,
1082                                           MLXSW_REG_SPMS_STATE_FORWARDING);
1083         if (err) {
1084                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set STP state\n",
1085                         mlxsw_sx_port->local_port);
1086                 goto err_port_stp_state_set;
1087         }
1088
1089         err = mlxsw_sx_port_mac_learning_mode_set(mlxsw_sx_port,
1090                                                   MLXSW_REG_SPMLR_LEARN_MODE_DISABLE);
1091         if (err) {
1092                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set MAC learning mode\n",
1093                         mlxsw_sx_port->local_port);
1094                 goto err_port_mac_learning_mode_set;
1095         }
1096
1097         err = register_netdev(dev);
1098         if (err) {
1099                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to register netdev\n",
1100                         mlxsw_sx_port->local_port);
1101                 goto err_register_netdev;
1102         }
1103
1104         mlxsw_core_port_eth_set(mlxsw_sx->core, mlxsw_sx_port->local_port,
1105                                 mlxsw_sx_port, dev, module + 1, false, 0);
1106         mlxsw_sx->ports[local_port] = mlxsw_sx_port;
1107         return 0;
1108
1109 err_register_netdev:
1110 err_port_mac_learning_mode_set:
1111 err_port_stp_state_set:
1112 err_port_admin_status_set:
1113 err_port_mtu_set:
1114 err_port_speed_set:
1115         mlxsw_sx_port_swid_set(mlxsw_sx_port, MLXSW_PORT_SWID_DISABLED_PORT);
1116 err_port_swid_set:
1117 err_port_system_port_mapping_set:
1118 err_dev_addr_get:
1119         free_percpu(mlxsw_sx_port->pcpu_stats);
1120 err_alloc_stats:
1121         free_netdev(dev);
1122         return err;
1123 }
1124
1125 static int mlxsw_sx_port_eth_create(struct mlxsw_sx *mlxsw_sx, u8 local_port,
1126                                     u8 module, u8 width)
1127 {
1128         int err;
1129
1130         err = mlxsw_core_port_init(mlxsw_sx->core, local_port);
1131         if (err) {
1132                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to init core port\n",
1133                         local_port);
1134                 return err;
1135         }
1136         err = __mlxsw_sx_port_eth_create(mlxsw_sx, local_port, module, width);
1137         if (err)
1138                 goto err_port_create;
1139
1140         return 0;
1141
1142 err_port_create:
1143         mlxsw_core_port_fini(mlxsw_sx->core, local_port);
1144         return err;
1145 }
1146
1147 static void __mlxsw_sx_port_eth_remove(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1148 {
1149         struct mlxsw_sx_port *mlxsw_sx_port = mlxsw_sx->ports[local_port];
1150
1151         mlxsw_core_port_clear(mlxsw_sx->core, local_port, mlxsw_sx);
1152         unregister_netdev(mlxsw_sx_port->dev); /* This calls ndo_stop */
1153         mlxsw_sx->ports[local_port] = NULL;
1154         mlxsw_sx_port_swid_set(mlxsw_sx_port, MLXSW_PORT_SWID_DISABLED_PORT);
1155         free_percpu(mlxsw_sx_port->pcpu_stats);
1156         free_netdev(mlxsw_sx_port->dev);
1157 }
1158
1159 static bool mlxsw_sx_port_created(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1160 {
1161         return mlxsw_sx->ports[local_port] != NULL;
1162 }
1163
1164 static int __mlxsw_sx_port_ib_create(struct mlxsw_sx *mlxsw_sx, u8 local_port,
1165                                      u8 module, u8 width)
1166 {
1167         struct mlxsw_sx_port *mlxsw_sx_port;
1168         int err;
1169
1170         mlxsw_sx_port = kzalloc(sizeof(*mlxsw_sx_port), GFP_KERNEL);
1171         if (!mlxsw_sx_port)
1172                 return -ENOMEM;
1173         mlxsw_sx_port->mlxsw_sx = mlxsw_sx;
1174         mlxsw_sx_port->local_port = local_port;
1175         mlxsw_sx_port->mapping.module = module;
1176
1177         err = mlxsw_sx_port_system_port_mapping_set(mlxsw_sx_port);
1178         if (err) {
1179                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set system port mapping\n",
1180                         mlxsw_sx_port->local_port);
1181                 goto err_port_system_port_mapping_set;
1182         }
1183
1184         /* Adding port to Infiniband swid (1) */
1185         err = mlxsw_sx_port_swid_set(mlxsw_sx_port, 1);
1186         if (err) {
1187                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set SWID\n",
1188                         mlxsw_sx_port->local_port);
1189                 goto err_port_swid_set;
1190         }
1191
1192         /* Expose the IB port number as it's front panel name */
1193         err = mlxsw_sx_port_ib_port_set(mlxsw_sx_port, module + 1);
1194         if (err) {
1195                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set IB port\n",
1196                         mlxsw_sx_port->local_port);
1197                 goto err_port_ib_set;
1198         }
1199
1200         /* Supports all speeds from SDR to FDR (bitmask) and support bus width
1201          * of 1x, 2x and 4x (3 bits bitmask)
1202          */
1203         err = mlxsw_sx_port_ib_speed_set(mlxsw_sx_port,
1204                                          MLXSW_REG_PTYS_IB_SPEED_EDR - 1,
1205                                          BIT(3) - 1);
1206         if (err) {
1207                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set speed\n",
1208                         mlxsw_sx_port->local_port);
1209                 goto err_port_speed_set;
1210         }
1211
1212         /* Change to the maximum MTU the device supports, the SMA will take
1213          * care of the active MTU
1214          */
1215         err = mlxsw_sx_port_mtu_ib_set(mlxsw_sx_port, MLXSW_IB_DEFAULT_MTU);
1216         if (err) {
1217                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set MTU\n",
1218                         mlxsw_sx_port->local_port);
1219                 goto err_port_mtu_set;
1220         }
1221
1222         err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, true);
1223         if (err) {
1224                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to change admin state to UP\n",
1225                         mlxsw_sx_port->local_port);
1226                 goto err_port_admin_set;
1227         }
1228
1229         mlxsw_core_port_ib_set(mlxsw_sx->core, mlxsw_sx_port->local_port,
1230                                mlxsw_sx_port);
1231         mlxsw_sx->ports[local_port] = mlxsw_sx_port;
1232         return 0;
1233
1234 err_port_admin_set:
1235 err_port_mtu_set:
1236 err_port_speed_set:
1237 err_port_ib_set:
1238         mlxsw_sx_port_swid_set(mlxsw_sx_port, MLXSW_PORT_SWID_DISABLED_PORT);
1239 err_port_swid_set:
1240 err_port_system_port_mapping_set:
1241         kfree(mlxsw_sx_port);
1242         return err;
1243 }
1244
1245 static void __mlxsw_sx_port_ib_remove(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1246 {
1247         struct mlxsw_sx_port *mlxsw_sx_port = mlxsw_sx->ports[local_port];
1248
1249         mlxsw_core_port_clear(mlxsw_sx->core, local_port, mlxsw_sx);
1250         mlxsw_sx->ports[local_port] = NULL;
1251         mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
1252         mlxsw_sx_port_swid_set(mlxsw_sx_port, MLXSW_PORT_SWID_DISABLED_PORT);
1253         kfree(mlxsw_sx_port);
1254 }
1255
1256 static void __mlxsw_sx_port_remove(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1257 {
1258         enum devlink_port_type port_type =
1259                 mlxsw_core_port_type_get(mlxsw_sx->core, local_port);
1260
1261         if (port_type == DEVLINK_PORT_TYPE_ETH)
1262                 __mlxsw_sx_port_eth_remove(mlxsw_sx, local_port);
1263         else if (port_type == DEVLINK_PORT_TYPE_IB)
1264                 __mlxsw_sx_port_ib_remove(mlxsw_sx, local_port);
1265 }
1266
1267 static void mlxsw_sx_port_remove(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1268 {
1269         __mlxsw_sx_port_remove(mlxsw_sx, local_port);
1270         mlxsw_core_port_fini(mlxsw_sx->core, local_port);
1271 }
1272
1273 static void mlxsw_sx_ports_remove(struct mlxsw_sx *mlxsw_sx)
1274 {
1275         int i;
1276
1277         for (i = 1; i < mlxsw_core_max_ports(mlxsw_sx->core); i++)
1278                 if (mlxsw_sx_port_created(mlxsw_sx, i))
1279                         mlxsw_sx_port_remove(mlxsw_sx, i);
1280         kfree(mlxsw_sx->ports);
1281 }
1282
1283 static int mlxsw_sx_ports_create(struct mlxsw_sx *mlxsw_sx)
1284 {
1285         unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sx->core);
1286         size_t alloc_size;
1287         u8 module, width;
1288         int i;
1289         int err;
1290
1291         alloc_size = sizeof(struct mlxsw_sx_port *) * max_ports;
1292         mlxsw_sx->ports = kzalloc(alloc_size, GFP_KERNEL);
1293         if (!mlxsw_sx->ports)
1294                 return -ENOMEM;
1295
1296         for (i = 1; i < max_ports; i++) {
1297                 err = mlxsw_sx_port_module_info_get(mlxsw_sx, i, &module,
1298                                                     &width);
1299                 if (err)
1300                         goto err_port_module_info_get;
1301                 if (!width)
1302                         continue;
1303                 err = mlxsw_sx_port_eth_create(mlxsw_sx, i, module, width);
1304                 if (err)
1305                         goto err_port_create;
1306         }
1307         return 0;
1308
1309 err_port_create:
1310 err_port_module_info_get:
1311         for (i--; i >= 1; i--)
1312                 if (mlxsw_sx_port_created(mlxsw_sx, i))
1313                         mlxsw_sx_port_remove(mlxsw_sx, i);
1314         kfree(mlxsw_sx->ports);
1315         return err;
1316 }
1317
1318 static void mlxsw_sx_pude_eth_event_func(struct mlxsw_sx_port *mlxsw_sx_port,
1319                                          enum mlxsw_reg_pude_oper_status status)
1320 {
1321         if (status == MLXSW_PORT_OPER_STATUS_UP) {
1322                 netdev_info(mlxsw_sx_port->dev, "link up\n");
1323                 netif_carrier_on(mlxsw_sx_port->dev);
1324         } else {
1325                 netdev_info(mlxsw_sx_port->dev, "link down\n");
1326                 netif_carrier_off(mlxsw_sx_port->dev);
1327         }
1328 }
1329
1330 static void mlxsw_sx_pude_ib_event_func(struct mlxsw_sx_port *mlxsw_sx_port,
1331                                         enum mlxsw_reg_pude_oper_status status)
1332 {
1333         if (status == MLXSW_PORT_OPER_STATUS_UP)
1334                 pr_info("ib link for port %d - up\n",
1335                         mlxsw_sx_port->mapping.module + 1);
1336         else
1337                 pr_info("ib link for port %d - down\n",
1338                         mlxsw_sx_port->mapping.module + 1);
1339 }
1340
1341 static void mlxsw_sx_pude_event_func(const struct mlxsw_reg_info *reg,
1342                                      char *pude_pl, void *priv)
1343 {
1344         struct mlxsw_sx *mlxsw_sx = priv;
1345         struct mlxsw_sx_port *mlxsw_sx_port;
1346         enum mlxsw_reg_pude_oper_status status;
1347         enum devlink_port_type port_type;
1348         u8 local_port;
1349
1350         local_port = mlxsw_reg_pude_local_port_get(pude_pl);
1351         mlxsw_sx_port = mlxsw_sx->ports[local_port];
1352         if (!mlxsw_sx_port) {
1353                 dev_warn(mlxsw_sx->bus_info->dev, "Port %d: Link event received for non-existent port\n",
1354                          local_port);
1355                 return;
1356         }
1357
1358         status = mlxsw_reg_pude_oper_status_get(pude_pl);
1359         port_type = mlxsw_core_port_type_get(mlxsw_sx->core, local_port);
1360         if (port_type == DEVLINK_PORT_TYPE_ETH)
1361                 mlxsw_sx_pude_eth_event_func(mlxsw_sx_port, status);
1362         else if (port_type == DEVLINK_PORT_TYPE_IB)
1363                 mlxsw_sx_pude_ib_event_func(mlxsw_sx_port, status);
1364 }
1365
1366 static void mlxsw_sx_rx_listener_func(struct sk_buff *skb, u8 local_port,
1367                                       void *priv)
1368 {
1369         struct mlxsw_sx *mlxsw_sx = priv;
1370         struct mlxsw_sx_port *mlxsw_sx_port = mlxsw_sx->ports[local_port];
1371         struct mlxsw_sx_port_pcpu_stats *pcpu_stats;
1372
1373         if (unlikely(!mlxsw_sx_port)) {
1374                 dev_warn_ratelimited(mlxsw_sx->bus_info->dev, "Port %d: skb received for non-existent port\n",
1375                                      local_port);
1376                 return;
1377         }
1378
1379         skb->dev = mlxsw_sx_port->dev;
1380
1381         pcpu_stats = this_cpu_ptr(mlxsw_sx_port->pcpu_stats);
1382         u64_stats_update_begin(&pcpu_stats->syncp);
1383         pcpu_stats->rx_packets++;
1384         pcpu_stats->rx_bytes += skb->len;
1385         u64_stats_update_end(&pcpu_stats->syncp);
1386
1387         skb->protocol = eth_type_trans(skb, skb->dev);
1388         netif_receive_skb(skb);
1389 }
1390
1391 static int mlxsw_sx_port_type_set(struct mlxsw_core *mlxsw_core, u8 local_port,
1392                                   enum devlink_port_type new_type)
1393 {
1394         struct mlxsw_sx *mlxsw_sx = mlxsw_core_driver_priv(mlxsw_core);
1395         u8 module, width;
1396         int err;
1397
1398         if (new_type == DEVLINK_PORT_TYPE_AUTO)
1399                 return -EOPNOTSUPP;
1400
1401         __mlxsw_sx_port_remove(mlxsw_sx, local_port);
1402         err = mlxsw_sx_port_module_info_get(mlxsw_sx, local_port, &module,
1403                                             &width);
1404         if (err)
1405                 goto err_port_module_info_get;
1406
1407         if (new_type == DEVLINK_PORT_TYPE_ETH)
1408                 err = __mlxsw_sx_port_eth_create(mlxsw_sx, local_port, module,
1409                                                  width);
1410         else if (new_type == DEVLINK_PORT_TYPE_IB)
1411                 err = __mlxsw_sx_port_ib_create(mlxsw_sx, local_port, module,
1412                                                 width);
1413
1414 err_port_module_info_get:
1415         return err;
1416 }
1417
1418 #define MLXSW_SX_RXL(_trap_id) \
1419         MLXSW_RXL(mlxsw_sx_rx_listener_func, _trap_id, TRAP_TO_CPU,     \
1420                   false, SX2_RX, FORWARD)
1421
1422 static const struct mlxsw_listener mlxsw_sx_listener[] = {
1423         MLXSW_EVENTL(mlxsw_sx_pude_event_func, PUDE, EMAD),
1424         MLXSW_SX_RXL(FDB_MC),
1425         MLXSW_SX_RXL(STP),
1426         MLXSW_SX_RXL(LACP),
1427         MLXSW_SX_RXL(EAPOL),
1428         MLXSW_SX_RXL(LLDP),
1429         MLXSW_SX_RXL(MMRP),
1430         MLXSW_SX_RXL(MVRP),
1431         MLXSW_SX_RXL(RPVST),
1432         MLXSW_SX_RXL(DHCP),
1433         MLXSW_SX_RXL(IGMP_QUERY),
1434         MLXSW_SX_RXL(IGMP_V1_REPORT),
1435         MLXSW_SX_RXL(IGMP_V2_REPORT),
1436         MLXSW_SX_RXL(IGMP_V2_LEAVE),
1437         MLXSW_SX_RXL(IGMP_V3_REPORT),
1438 };
1439
1440 static int mlxsw_sx_traps_init(struct mlxsw_sx *mlxsw_sx)
1441 {
1442         char htgt_pl[MLXSW_REG_HTGT_LEN];
1443         int i;
1444         int err;
1445
1446         mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX,
1447                             MLXSW_REG_HTGT_INVALID_POLICER,
1448                             MLXSW_REG_HTGT_DEFAULT_PRIORITY,
1449                             MLXSW_REG_HTGT_DEFAULT_TC);
1450         mlxsw_reg_htgt_local_path_rdq_set(htgt_pl,
1451                                           MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX);
1452
1453         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(htgt), htgt_pl);
1454         if (err)
1455                 return err;
1456
1457         mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL,
1458                             MLXSW_REG_HTGT_INVALID_POLICER,
1459                             MLXSW_REG_HTGT_DEFAULT_PRIORITY,
1460                             MLXSW_REG_HTGT_DEFAULT_TC);
1461         mlxsw_reg_htgt_local_path_rdq_set(htgt_pl,
1462                                         MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL);
1463
1464         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(htgt), htgt_pl);
1465         if (err)
1466                 return err;
1467
1468         for (i = 0; i < ARRAY_SIZE(mlxsw_sx_listener); i++) {
1469                 err = mlxsw_core_trap_register(mlxsw_sx->core,
1470                                                &mlxsw_sx_listener[i],
1471                                                mlxsw_sx);
1472                 if (err)
1473                         goto err_listener_register;
1474
1475         }
1476         return 0;
1477
1478 err_listener_register:
1479         for (i--; i >= 0; i--) {
1480                 mlxsw_core_trap_unregister(mlxsw_sx->core,
1481                                            &mlxsw_sx_listener[i],
1482                                            mlxsw_sx);
1483         }
1484         return err;
1485 }
1486
1487 static void mlxsw_sx_traps_fini(struct mlxsw_sx *mlxsw_sx)
1488 {
1489         int i;
1490
1491         for (i = 0; i < ARRAY_SIZE(mlxsw_sx_listener); i++) {
1492                 mlxsw_core_trap_unregister(mlxsw_sx->core,
1493                                            &mlxsw_sx_listener[i],
1494                                            mlxsw_sx);
1495         }
1496 }
1497
1498 static int mlxsw_sx_flood_init(struct mlxsw_sx *mlxsw_sx)
1499 {
1500         char sfgc_pl[MLXSW_REG_SFGC_LEN];
1501         char sgcr_pl[MLXSW_REG_SGCR_LEN];
1502         char *sftr_pl;
1503         int err;
1504
1505         /* Configure a flooding table, which includes only CPU port. */
1506         sftr_pl = kmalloc(MLXSW_REG_SFTR_LEN, GFP_KERNEL);
1507         if (!sftr_pl)
1508                 return -ENOMEM;
1509         mlxsw_reg_sftr_pack(sftr_pl, 0, 0, MLXSW_REG_SFGC_TABLE_TYPE_SINGLE, 0,
1510                             MLXSW_PORT_CPU_PORT, true);
1511         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sftr), sftr_pl);
1512         kfree(sftr_pl);
1513         if (err)
1514                 return err;
1515
1516         /* Flood different packet types using the flooding table. */
1517         mlxsw_reg_sfgc_pack(sfgc_pl,
1518                             MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
1519                             MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1520                             MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1521                             0);
1522         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1523         if (err)
1524                 return err;
1525
1526         mlxsw_reg_sfgc_pack(sfgc_pl,
1527                             MLXSW_REG_SFGC_TYPE_BROADCAST,
1528                             MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1529                             MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1530                             0);
1531         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1532         if (err)
1533                 return err;
1534
1535         mlxsw_reg_sfgc_pack(sfgc_pl,
1536                             MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
1537                             MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1538                             MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1539                             0);
1540         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1541         if (err)
1542                 return err;
1543
1544         mlxsw_reg_sfgc_pack(sfgc_pl,
1545                             MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
1546                             MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1547                             MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1548                             0);
1549         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1550         if (err)
1551                 return err;
1552
1553         mlxsw_reg_sfgc_pack(sfgc_pl,
1554                             MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
1555                             MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1556                             MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1557                             0);
1558         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1559         if (err)
1560                 return err;
1561
1562         mlxsw_reg_sgcr_pack(sgcr_pl, true);
1563         return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sgcr), sgcr_pl);
1564 }
1565
1566 static int mlxsw_sx_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
1567 {
1568         char htgt_pl[MLXSW_REG_HTGT_LEN];
1569
1570         mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
1571                             MLXSW_REG_HTGT_INVALID_POLICER,
1572                             MLXSW_REG_HTGT_DEFAULT_PRIORITY,
1573                             MLXSW_REG_HTGT_DEFAULT_TC);
1574         mlxsw_reg_htgt_swid_set(htgt_pl, MLXSW_PORT_SWID_ALL_SWIDS);
1575         mlxsw_reg_htgt_local_path_rdq_set(htgt_pl,
1576                                         MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD);
1577         return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
1578 }
1579
1580 static int mlxsw_sx_init(struct mlxsw_core *mlxsw_core,
1581                          const struct mlxsw_bus_info *mlxsw_bus_info)
1582 {
1583         struct mlxsw_sx *mlxsw_sx = mlxsw_core_driver_priv(mlxsw_core);
1584         int err;
1585
1586         mlxsw_sx->core = mlxsw_core;
1587         mlxsw_sx->bus_info = mlxsw_bus_info;
1588
1589         err = mlxsw_sx_hw_id_get(mlxsw_sx);
1590         if (err) {
1591                 dev_err(mlxsw_sx->bus_info->dev, "Failed to get switch HW ID\n");
1592                 return err;
1593         }
1594
1595         err = mlxsw_sx_ports_create(mlxsw_sx);
1596         if (err) {
1597                 dev_err(mlxsw_sx->bus_info->dev, "Failed to create ports\n");
1598                 return err;
1599         }
1600
1601         err = mlxsw_sx_traps_init(mlxsw_sx);
1602         if (err) {
1603                 dev_err(mlxsw_sx->bus_info->dev, "Failed to set traps\n");
1604                 goto err_listener_register;
1605         }
1606
1607         err = mlxsw_sx_flood_init(mlxsw_sx);
1608         if (err) {
1609                 dev_err(mlxsw_sx->bus_info->dev, "Failed to initialize flood tables\n");
1610                 goto err_flood_init;
1611         }
1612
1613         return 0;
1614
1615 err_flood_init:
1616         mlxsw_sx_traps_fini(mlxsw_sx);
1617 err_listener_register:
1618         mlxsw_sx_ports_remove(mlxsw_sx);
1619         return err;
1620 }
1621
1622 static void mlxsw_sx_fini(struct mlxsw_core *mlxsw_core)
1623 {
1624         struct mlxsw_sx *mlxsw_sx = mlxsw_core_driver_priv(mlxsw_core);
1625
1626         mlxsw_sx_traps_fini(mlxsw_sx);
1627         mlxsw_sx_ports_remove(mlxsw_sx);
1628 }
1629
1630 static const struct mlxsw_config_profile mlxsw_sx_config_profile = {
1631         .used_max_vepa_channels         = 1,
1632         .max_vepa_channels              = 0,
1633         .used_max_mid                   = 1,
1634         .max_mid                        = 7000,
1635         .used_max_pgt                   = 1,
1636         .max_pgt                        = 0,
1637         .used_max_system_port           = 1,
1638         .max_system_port                = 48000,
1639         .used_max_vlan_groups           = 1,
1640         .max_vlan_groups                = 127,
1641         .used_max_regions               = 1,
1642         .max_regions                    = 400,
1643         .used_flood_tables              = 1,
1644         .max_flood_tables               = 2,
1645         .max_vid_flood_tables           = 1,
1646         .used_flood_mode                = 1,
1647         .flood_mode                     = 3,
1648         .used_max_ib_mc                 = 1,
1649         .max_ib_mc                      = 6,
1650         .used_max_pkey                  = 1,
1651         .max_pkey                       = 0,
1652         .swid_config                    = {
1653                 {
1654                         .used_type      = 1,
1655                         .type           = MLXSW_PORT_SWID_TYPE_ETH,
1656                 },
1657                 {
1658                         .used_type      = 1,
1659                         .type           = MLXSW_PORT_SWID_TYPE_IB,
1660                 }
1661         },
1662 };
1663
1664 static struct mlxsw_driver mlxsw_sx_driver = {
1665         .kind                   = mlxsw_sx_driver_name,
1666         .priv_size              = sizeof(struct mlxsw_sx),
1667         .init                   = mlxsw_sx_init,
1668         .fini                   = mlxsw_sx_fini,
1669         .basic_trap_groups_set  = mlxsw_sx_basic_trap_groups_set,
1670         .txhdr_construct        = mlxsw_sx_txhdr_construct,
1671         .txhdr_len              = MLXSW_TXHDR_LEN,
1672         .profile                = &mlxsw_sx_config_profile,
1673         .port_type_set          = mlxsw_sx_port_type_set,
1674 };
1675
1676 static const struct pci_device_id mlxsw_sx_pci_id_table[] = {
1677         {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SWITCHX2), 0},
1678         {0, },
1679 };
1680
1681 static struct pci_driver mlxsw_sx_pci_driver = {
1682         .name = mlxsw_sx_driver_name,
1683         .id_table = mlxsw_sx_pci_id_table,
1684 };
1685
1686 static int __init mlxsw_sx_module_init(void)
1687 {
1688         int err;
1689
1690         err = mlxsw_core_driver_register(&mlxsw_sx_driver);
1691         if (err)
1692                 return err;
1693
1694         err = mlxsw_pci_driver_register(&mlxsw_sx_pci_driver);
1695         if (err)
1696                 goto err_pci_driver_register;
1697
1698         return 0;
1699
1700 err_pci_driver_register:
1701         mlxsw_core_driver_unregister(&mlxsw_sx_driver);
1702         return err;
1703 }
1704
1705 static void __exit mlxsw_sx_module_exit(void)
1706 {
1707         mlxsw_pci_driver_unregister(&mlxsw_sx_pci_driver);
1708         mlxsw_core_driver_unregister(&mlxsw_sx_driver);
1709 }
1710
1711 module_init(mlxsw_sx_module_init);
1712 module_exit(mlxsw_sx_module_exit);
1713
1714 MODULE_LICENSE("Dual BSD/GPL");
1715 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
1716 MODULE_DESCRIPTION("Mellanox SwitchX-2 driver");
1717 MODULE_DEVICE_TABLE(pci, mlxsw_sx_pci_id_table);