1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/types.h>
8 #include <linux/netdevice.h>
9 #include <linux/etherdevice.h>
10 #include <linux/ethtool.h>
11 #include <linux/slab.h>
12 #include <linux/device.h>
13 #include <linux/skbuff.h>
14 #include <linux/if_vlan.h>
15 #include <linux/if_bridge.h>
16 #include <linux/workqueue.h>
17 #include <linux/jiffies.h>
18 #include <linux/bitops.h>
19 #include <linux/list.h>
20 #include <linux/notifier.h>
21 #include <linux/dcbnl.h>
22 #include <linux/inetdevice.h>
23 #include <linux/netlink.h>
24 #include <linux/random.h>
25 #include <net/switchdev.h>
26 #include <net/pkt_cls.h>
27 #include <net/tc_act/tc_mirred.h>
28 #include <net/netevent.h>
29 #include <net/tc_act/tc_sample.h>
30 #include <net/addrconf.h>
39 #include "spectrum_cnt.h"
40 #include "spectrum_dpipe.h"
41 #include "spectrum_acl_flex_actions.h"
42 #include "spectrum_span.h"
43 #include "../mlxfw/mlxfw.h"
45 #define MLXSW_SP_FWREV_MINOR_TO_BRANCH(minor) ((minor) / 100)
47 #define MLXSW_SP1_FWREV_MAJOR 13
48 #define MLXSW_SP1_FWREV_MINOR 1703
49 #define MLXSW_SP1_FWREV_SUBMINOR 4
50 #define MLXSW_SP1_FWREV_CAN_RESET_MINOR 1702
52 static const struct mlxsw_fw_rev mlxsw_sp1_fw_rev = {
53 .major = MLXSW_SP1_FWREV_MAJOR,
54 .minor = MLXSW_SP1_FWREV_MINOR,
55 .subminor = MLXSW_SP1_FWREV_SUBMINOR,
56 .can_reset_minor = MLXSW_SP1_FWREV_CAN_RESET_MINOR,
59 #define MLXSW_SP1_FW_FILENAME \
60 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_SP1_FWREV_MAJOR) \
61 "." __stringify(MLXSW_SP1_FWREV_MINOR) \
62 "." __stringify(MLXSW_SP1_FWREV_SUBMINOR) ".mfa2"
64 static const char mlxsw_sp1_driver_name[] = "mlxsw_spectrum";
65 static const char mlxsw_sp2_driver_name[] = "mlxsw_spectrum2";
66 static const char mlxsw_sp_driver_version[] = "1.0";
72 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
75 * Packet control type.
76 * 0 - Ethernet control (e.g. EMADs, LACP)
79 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
82 * Packet protocol type. Must be set to 1 (Ethernet).
84 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
86 /* tx_hdr_rx_is_router
87 * Packet is sent from the router. Valid for data packets only.
89 MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
92 * Indicates if the 'fid' field is valid and should be used for
93 * forwarding lookup. Valid for data packets only.
95 MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
98 * Switch partition ID. Must be set to 0.
100 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
102 /* tx_hdr_control_tclass
103 * Indicates if the packet should use the control TClass and not one
104 * of the data TClasses.
106 MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
109 * Egress TClass to be used on the egress device on the egress port.
111 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
114 * Destination local port for unicast packets.
115 * Destination multicast ID for multicast packets.
117 * Control packets are directed to a specific egress port, while data
118 * packets are transmitted through the CPU port (0) into the switch partition,
119 * where forwarding rules are applied.
121 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
124 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
125 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
126 * Valid for data packets only.
128 MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
132 * 6 - Control packets
134 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
136 struct mlxsw_sp_mlxfw_dev {
137 struct mlxfw_dev mlxfw_dev;
138 struct mlxsw_sp *mlxsw_sp;
141 static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev,
142 u16 component_index, u32 *p_max_size,
143 u8 *p_align_bits, u16 *p_max_write_size)
145 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
146 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
147 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
148 char mcqi_pl[MLXSW_REG_MCQI_LEN];
151 mlxsw_reg_mcqi_pack(mcqi_pl, component_index);
152 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl);
155 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits,
158 *p_align_bits = max_t(u8, *p_align_bits, 2);
159 *p_max_write_size = min_t(u16, *p_max_write_size,
160 MLXSW_REG_MCDA_MAX_DATA_LEN);
164 static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
166 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
167 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
168 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
169 char mcc_pl[MLXSW_REG_MCC_LEN];
173 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0);
174 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
178 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state);
179 if (control_state != MLXFW_FSM_STATE_IDLE)
182 mlxsw_reg_mcc_pack(mcc_pl,
183 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
185 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
188 static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev,
189 u32 fwhandle, u16 component_index,
192 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
193 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
194 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
195 char mcc_pl[MLXSW_REG_MCC_LEN];
197 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
198 component_index, fwhandle, component_size);
199 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
202 static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev,
203 u32 fwhandle, u8 *data, u16 size,
206 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
207 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
208 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
209 char mcda_pl[MLXSW_REG_MCDA_LEN];
211 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data);
212 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl);
215 static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev,
216 u32 fwhandle, u16 component_index)
218 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
219 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
220 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
221 char mcc_pl[MLXSW_REG_MCC_LEN];
223 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
224 component_index, fwhandle, 0);
225 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
228 static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
230 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
231 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
232 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
233 char mcc_pl[MLXSW_REG_MCC_LEN];
235 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0,
237 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
240 static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
241 enum mlxfw_fsm_state *fsm_state,
242 enum mlxfw_fsm_state_err *fsm_state_err)
244 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
245 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
246 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
247 char mcc_pl[MLXSW_REG_MCC_LEN];
252 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0);
253 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
257 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state);
258 *fsm_state = control_state;
259 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
260 MLXFW_FSM_STATE_ERR_MAX);
264 static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
266 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
267 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
268 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
269 char mcc_pl[MLXSW_REG_MCC_LEN];
271 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0,
273 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
276 static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
278 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
279 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
280 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
281 char mcc_pl[MLXSW_REG_MCC_LEN];
283 mlxsw_reg_mcc_pack(mcc_pl,
284 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
286 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
289 static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = {
290 .component_query = mlxsw_sp_component_query,
291 .fsm_lock = mlxsw_sp_fsm_lock,
292 .fsm_component_update = mlxsw_sp_fsm_component_update,
293 .fsm_block_download = mlxsw_sp_fsm_block_download,
294 .fsm_component_verify = mlxsw_sp_fsm_component_verify,
295 .fsm_activate = mlxsw_sp_fsm_activate,
296 .fsm_query_state = mlxsw_sp_fsm_query_state,
297 .fsm_cancel = mlxsw_sp_fsm_cancel,
298 .fsm_release = mlxsw_sp_fsm_release
301 static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp,
302 const struct firmware *firmware)
304 struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = {
306 .ops = &mlxsw_sp_mlxfw_dev_ops,
307 .psid = mlxsw_sp->bus_info->psid,
308 .psid_size = strlen(mlxsw_sp->bus_info->psid),
313 return mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev, firmware);
316 static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp)
318 const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev;
319 const struct mlxsw_fw_rev *req_rev = mlxsw_sp->req_rev;
320 const char *fw_filename = mlxsw_sp->fw_filename;
321 const struct firmware *firmware;
324 /* Don't check if driver does not require it */
325 if (!req_rev || !fw_filename)
328 /* Validate driver & FW are compatible */
329 if (rev->major != req_rev->major) {
330 WARN(1, "Mismatch in major FW version [%d:%d] is never expected; Please contact support\n",
331 rev->major, req_rev->major);
334 if (MLXSW_SP_FWREV_MINOR_TO_BRANCH(rev->minor) ==
335 MLXSW_SP_FWREV_MINOR_TO_BRANCH(req_rev->minor) &&
336 (rev->minor > req_rev->minor ||
337 (rev->minor == req_rev->minor &&
338 rev->subminor >= req_rev->subminor)))
341 dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d is incompatible with the driver\n",
342 rev->major, rev->minor, rev->subminor);
343 dev_info(mlxsw_sp->bus_info->dev, "Flashing firmware using file %s\n",
346 err = request_firmware_direct(&firmware, fw_filename,
347 mlxsw_sp->bus_info->dev);
349 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n",
354 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
355 release_firmware(firmware);
357 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n");
359 /* On FW flash success, tell the caller FW reset is needed
360 * if current FW supports it.
362 if (rev->minor >= req_rev->can_reset_minor)
363 return err ? err : -EAGAIN;
368 int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
369 unsigned int counter_index, u64 *packets,
372 char mgpc_pl[MLXSW_REG_MGPC_LEN];
375 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
376 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
377 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
381 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
383 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
387 static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
388 unsigned int counter_index)
390 char mgpc_pl[MLXSW_REG_MGPC_LEN];
392 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
393 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
394 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
397 int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
398 unsigned int *p_counter_index)
402 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
406 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
408 goto err_counter_clear;
412 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
417 void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
418 unsigned int counter_index)
420 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
424 static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
425 const struct mlxsw_tx_info *tx_info)
427 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
429 memset(txhdr, 0, MLXSW_TXHDR_LEN);
431 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
432 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
433 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
434 mlxsw_tx_hdr_swid_set(txhdr, 0);
435 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
436 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
437 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
440 enum mlxsw_reg_spms_state mlxsw_sp_stp_spms_state(u8 state)
443 case BR_STATE_FORWARDING:
444 return MLXSW_REG_SPMS_STATE_FORWARDING;
445 case BR_STATE_LEARNING:
446 return MLXSW_REG_SPMS_STATE_LEARNING;
447 case BR_STATE_LISTENING: /* fall-through */
448 case BR_STATE_DISABLED: /* fall-through */
449 case BR_STATE_BLOCKING:
450 return MLXSW_REG_SPMS_STATE_DISCARDING;
456 int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
459 enum mlxsw_reg_spms_state spms_state = mlxsw_sp_stp_spms_state(state);
460 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
464 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
467 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
468 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
470 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
475 static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
477 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
480 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
483 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
487 static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
488 bool enable, u32 rate)
490 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
491 char mpsc_pl[MLXSW_REG_MPSC_LEN];
493 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
494 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
497 static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
500 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
501 char paos_pl[MLXSW_REG_PAOS_LEN];
503 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
504 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
505 MLXSW_PORT_ADMIN_STATUS_DOWN);
506 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
509 static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
512 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
513 char ppad_pl[MLXSW_REG_PPAD_LEN];
515 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
516 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
517 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
520 static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
522 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
523 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
525 ether_addr_copy(addr, mlxsw_sp->base_mac);
526 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
527 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
530 static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
532 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
533 char pmtu_pl[MLXSW_REG_PMTU_LEN];
537 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
538 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
539 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
542 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
547 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
548 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
551 static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
553 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
554 char pspa_pl[MLXSW_REG_PSPA_LEN];
556 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port);
557 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
560 int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
562 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
563 char svpe_pl[MLXSW_REG_SVPE_LEN];
565 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
566 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
569 int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
572 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
576 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
579 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
581 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
586 static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
589 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
590 char spvid_pl[MLXSW_REG_SPVID_LEN];
592 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
593 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
596 static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
599 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
600 char spaft_pl[MLXSW_REG_SPAFT_LEN];
602 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
603 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
606 int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
611 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
615 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
618 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
620 goto err_port_allow_untagged_set;
623 mlxsw_sp_port->pvid = vid;
626 err_port_allow_untagged_set:
627 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
632 mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
634 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
635 char sspr_pl[MLXSW_REG_SSPR_LEN];
637 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
638 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
641 static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
642 u8 local_port, u8 *p_module,
643 u8 *p_width, u8 *p_lane)
645 char pmlp_pl[MLXSW_REG_PMLP_LEN];
648 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
649 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
652 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
653 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
654 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
658 static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port,
659 u8 module, u8 width, u8 lane)
661 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
662 char pmlp_pl[MLXSW_REG_PMLP_LEN];
665 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
666 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
667 for (i = 0; i < width; i++) {
668 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
669 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
672 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
675 static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port)
677 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
678 char pmlp_pl[MLXSW_REG_PMLP_LEN];
680 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
681 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
682 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
685 static int mlxsw_sp_port_open(struct net_device *dev)
687 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
690 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
693 netif_start_queue(dev);
697 static int mlxsw_sp_port_stop(struct net_device *dev)
699 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
701 netif_stop_queue(dev);
702 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
705 static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
706 struct net_device *dev)
708 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
709 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
710 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
711 const struct mlxsw_tx_info tx_info = {
712 .local_port = mlxsw_sp_port->local_port,
718 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
719 return NETDEV_TX_BUSY;
721 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
722 struct sk_buff *skb_orig = skb;
724 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
726 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
727 dev_kfree_skb_any(skb_orig);
730 dev_consume_skb_any(skb_orig);
733 if (eth_skb_pad(skb)) {
734 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
738 mlxsw_sp_txhdr_construct(skb, &tx_info);
739 /* TX header is consumed by HW on the way so we shouldn't count its
740 * bytes as being sent.
742 len = skb->len - MLXSW_TXHDR_LEN;
744 /* Due to a race we might fail here because of a full queue. In that
745 * unlikely case we simply drop the packet.
747 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
750 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
751 u64_stats_update_begin(&pcpu_stats->syncp);
752 pcpu_stats->tx_packets++;
753 pcpu_stats->tx_bytes += len;
754 u64_stats_update_end(&pcpu_stats->syncp);
756 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
757 dev_kfree_skb_any(skb);
762 static void mlxsw_sp_set_rx_mode(struct net_device *dev)
766 static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
768 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
769 struct sockaddr *addr = p;
772 if (!is_valid_ether_addr(addr->sa_data))
773 return -EADDRNOTAVAIL;
775 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
778 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
782 static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
785 return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
788 #define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
790 static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
793 delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
795 return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
799 /* Maximum delay buffer needed in case of PAUSE frames, in bytes.
800 * Assumes 100m cable and maximum MTU.
802 #define MLXSW_SP_PAUSE_DELAY 58752
804 static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
805 u16 delay, bool pfc, bool pause)
808 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
810 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
815 static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
819 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
821 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
825 int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
826 u8 *prio_tc, bool pause_en,
827 struct ieee_pfc *my_pfc)
829 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
830 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
831 u16 delay = !!my_pfc ? my_pfc->delay : 0;
832 char pbmc_pl[MLXSW_REG_PBMC_LEN];
835 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
836 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
840 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
841 bool configure = false;
846 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
847 if (prio_tc[j] == i) {
848 pfc = pfc_en & BIT(j);
857 lossy = !(pfc || pause_en);
858 thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
859 delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc,
861 mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy);
864 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
867 static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
868 int mtu, bool pause_en)
870 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
871 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
872 struct ieee_pfc *my_pfc;
875 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
876 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
878 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
882 static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
884 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
885 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
888 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
891 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
893 goto err_span_port_mtu_update;
894 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
896 goto err_port_mtu_set;
901 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
902 err_span_port_mtu_update:
903 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
908 mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
909 struct rtnl_link_stats64 *stats)
911 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
912 struct mlxsw_sp_port_pcpu_stats *p;
913 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
918 for_each_possible_cpu(i) {
919 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
921 start = u64_stats_fetch_begin_irq(&p->syncp);
922 rx_packets = p->rx_packets;
923 rx_bytes = p->rx_bytes;
924 tx_packets = p->tx_packets;
925 tx_bytes = p->tx_bytes;
926 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
928 stats->rx_packets += rx_packets;
929 stats->rx_bytes += rx_bytes;
930 stats->tx_packets += tx_packets;
931 stats->tx_bytes += tx_bytes;
932 /* tx_dropped is u32, updated without syncp protection. */
933 tx_dropped += p->tx_dropped;
935 stats->tx_dropped = tx_dropped;
939 static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
942 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
949 static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
953 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
954 return mlxsw_sp_port_get_sw_stats64(dev, sp);
960 static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
961 int prio, char *ppcnt_pl)
963 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
964 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
966 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
967 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
970 static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
971 struct rtnl_link_stats64 *stats)
973 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
976 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
982 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
984 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
986 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
988 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
990 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
992 stats->rx_crc_errors =
993 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
994 stats->rx_frame_errors =
995 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
997 stats->rx_length_errors = (
998 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
999 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
1000 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
1002 stats->rx_errors = (stats->rx_crc_errors +
1003 stats->rx_frame_errors + stats->rx_length_errors);
1010 mlxsw_sp_port_get_hw_xstats(struct net_device *dev,
1011 struct mlxsw_sp_port_xstats *xstats)
1013 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1016 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0,
1019 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl);
1021 for (i = 0; i < TC_MAX_QUEUE; i++) {
1022 err = mlxsw_sp_port_get_stats_raw(dev,
1023 MLXSW_REG_PPCNT_TC_CONG_TC,
1026 xstats->wred_drop[i] =
1027 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl);
1029 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT,
1034 xstats->backlog[i] =
1035 mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl);
1036 xstats->tail_drop[i] =
1037 mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl);
1040 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1041 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_PRIO_CNT,
1046 xstats->tx_packets[i] = mlxsw_reg_ppcnt_tx_frames_get(ppcnt_pl);
1047 xstats->tx_bytes[i] = mlxsw_reg_ppcnt_tx_octets_get(ppcnt_pl);
1051 static void update_stats_cache(struct work_struct *work)
1053 struct mlxsw_sp_port *mlxsw_sp_port =
1054 container_of(work, struct mlxsw_sp_port,
1055 periodic_hw_stats.update_dw.work);
1057 if (!netif_carrier_ok(mlxsw_sp_port->dev))
1060 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
1061 &mlxsw_sp_port->periodic_hw_stats.stats);
1062 mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev,
1063 &mlxsw_sp_port->periodic_hw_stats.xstats);
1066 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw,
1067 MLXSW_HW_STATS_UPDATE_TIME);
1070 /* Return the stats from a cache that is updated periodically,
1071 * as this function might get called in an atomic context.
1074 mlxsw_sp_port_get_stats64(struct net_device *dev,
1075 struct rtnl_link_stats64 *stats)
1077 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1079 memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats));
1082 static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
1083 u16 vid_begin, u16 vid_end,
1084 bool is_member, bool untagged)
1086 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1090 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1094 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1095 vid_end, is_member, untagged);
1096 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1101 int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1102 u16 vid_end, bool is_member, bool untagged)
1107 for (vid = vid_begin; vid <= vid_end;
1108 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1109 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1112 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1113 is_member, untagged);
1121 static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port)
1123 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
1125 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
1126 &mlxsw_sp_port->vlans_list, list)
1127 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
1130 static struct mlxsw_sp_port_vlan *
1131 mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1133 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1134 bool untagged = vid == 1;
1137 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
1139 return ERR_PTR(err);
1141 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
1142 if (!mlxsw_sp_port_vlan) {
1144 goto err_port_vlan_alloc;
1147 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
1148 mlxsw_sp_port_vlan->ref_count = 1;
1149 mlxsw_sp_port_vlan->vid = vid;
1150 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
1152 return mlxsw_sp_port_vlan;
1154 err_port_vlan_alloc:
1155 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1156 return ERR_PTR(err);
1160 mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1162 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
1163 u16 vid = mlxsw_sp_port_vlan->vid;
1165 list_del(&mlxsw_sp_port_vlan->list);
1166 kfree(mlxsw_sp_port_vlan);
1167 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1170 struct mlxsw_sp_port_vlan *
1171 mlxsw_sp_port_vlan_get(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1173 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1175 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1176 if (mlxsw_sp_port_vlan) {
1177 mlxsw_sp_port_vlan->ref_count++;
1178 return mlxsw_sp_port_vlan;
1181 return mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid);
1184 void mlxsw_sp_port_vlan_put(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1186 struct mlxsw_sp_fid *fid = mlxsw_sp_port_vlan->fid;
1188 if (--mlxsw_sp_port_vlan->ref_count != 0)
1191 if (mlxsw_sp_port_vlan->bridge_port)
1192 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
1194 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
1196 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
1199 static int mlxsw_sp_port_add_vid(struct net_device *dev,
1200 __be16 __always_unused proto, u16 vid)
1202 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1204 /* VLAN 0 is added to HW filter when device goes up, but it is
1205 * reserved in our case, so simply return.
1210 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_get(mlxsw_sp_port, vid));
1213 static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1214 __be16 __always_unused proto, u16 vid)
1216 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1217 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1219 /* VLAN 0 is removed from HW filter when device goes down, but
1220 * it is reserved in our case, so simply return.
1225 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1226 if (!mlxsw_sp_port_vlan)
1228 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
1233 static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
1236 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1238 return mlxsw_core_port_get_phys_port_name(mlxsw_sp_port->mlxsw_sp->core,
1239 mlxsw_sp_port->local_port,
1243 static struct mlxsw_sp_port_mall_tc_entry *
1244 mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1245 unsigned long cookie) {
1246 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1248 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1249 if (mall_tc_entry->cookie == cookie)
1250 return mall_tc_entry;
1256 mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1257 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
1258 const struct tc_action *a,
1261 enum mlxsw_sp_span_type span_type;
1262 struct net_device *to_dev;
1264 to_dev = tcf_mirred_dev(a);
1266 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1270 mirror->ingress = ingress;
1271 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1272 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_dev, span_type,
1273 true, &mirror->span_id);
1277 mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1278 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1280 enum mlxsw_sp_span_type span_type;
1282 span_type = mirror->ingress ?
1283 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1284 mlxsw_sp_span_mirror_del(mlxsw_sp_port, mirror->span_id,
1289 mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1290 struct tc_cls_matchall_offload *cls,
1291 const struct tc_action *a,
1296 if (!mlxsw_sp_port->sample)
1298 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1299 netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1302 if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) {
1303 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1307 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1308 tcf_sample_psample_group(a));
1309 mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a);
1310 mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a);
1311 mlxsw_sp_port->sample->rate = tcf_sample_rate(a);
1313 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a));
1315 goto err_port_sample_set;
1318 err_port_sample_set:
1319 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1324 mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1326 if (!mlxsw_sp_port->sample)
1329 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1330 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1333 static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1334 struct tc_cls_matchall_offload *f,
1337 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1338 __be16 protocol = f->common.protocol;
1339 const struct tc_action *a;
1343 if (!tcf_exts_has_one_action(f->exts)) {
1344 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
1348 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1351 mall_tc_entry->cookie = f->cookie;
1353 a = tcf_exts_first_action(f->exts);
1355 if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) {
1356 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1358 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1359 mirror = &mall_tc_entry->mirror;
1360 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1361 mirror, a, ingress);
1362 } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) {
1363 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
1364 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, f,
1371 goto err_add_action;
1373 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
1377 kfree(mall_tc_entry);
1381 static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1382 struct tc_cls_matchall_offload *f)
1384 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1386 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
1388 if (!mall_tc_entry) {
1389 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1392 list_del(&mall_tc_entry->list);
1394 switch (mall_tc_entry->type) {
1395 case MLXSW_SP_PORT_MALL_MIRROR:
1396 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1397 &mall_tc_entry->mirror);
1399 case MLXSW_SP_PORT_MALL_SAMPLE:
1400 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1406 kfree(mall_tc_entry);
1409 static int mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1410 struct tc_cls_matchall_offload *f,
1413 switch (f->command) {
1414 case TC_CLSMATCHALL_REPLACE:
1415 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port, f,
1417 case TC_CLSMATCHALL_DESTROY:
1418 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port, f);
1426 mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_acl_block *acl_block,
1427 struct tc_cls_flower_offload *f)
1429 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_acl_block_mlxsw_sp(acl_block);
1431 switch (f->command) {
1432 case TC_CLSFLOWER_REPLACE:
1433 return mlxsw_sp_flower_replace(mlxsw_sp, acl_block, f);
1434 case TC_CLSFLOWER_DESTROY:
1435 mlxsw_sp_flower_destroy(mlxsw_sp, acl_block, f);
1437 case TC_CLSFLOWER_STATS:
1438 return mlxsw_sp_flower_stats(mlxsw_sp, acl_block, f);
1439 case TC_CLSFLOWER_TMPLT_CREATE:
1440 return mlxsw_sp_flower_tmplt_create(mlxsw_sp, acl_block, f);
1441 case TC_CLSFLOWER_TMPLT_DESTROY:
1442 mlxsw_sp_flower_tmplt_destroy(mlxsw_sp, acl_block, f);
1449 static int mlxsw_sp_setup_tc_block_cb_matchall(enum tc_setup_type type,
1451 void *cb_priv, bool ingress)
1453 struct mlxsw_sp_port *mlxsw_sp_port = cb_priv;
1456 case TC_SETUP_CLSMATCHALL:
1457 if (!tc_cls_can_offload_and_chain0(mlxsw_sp_port->dev,
1461 return mlxsw_sp_setup_tc_cls_matchall(mlxsw_sp_port, type_data,
1463 case TC_SETUP_CLSFLOWER:
1470 static int mlxsw_sp_setup_tc_block_cb_matchall_ig(enum tc_setup_type type,
1474 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1478 static int mlxsw_sp_setup_tc_block_cb_matchall_eg(enum tc_setup_type type,
1482 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1486 static int mlxsw_sp_setup_tc_block_cb_flower(enum tc_setup_type type,
1487 void *type_data, void *cb_priv)
1489 struct mlxsw_sp_acl_block *acl_block = cb_priv;
1492 case TC_SETUP_CLSMATCHALL:
1494 case TC_SETUP_CLSFLOWER:
1495 if (mlxsw_sp_acl_block_disabled(acl_block))
1498 return mlxsw_sp_setup_tc_cls_flower(acl_block, type_data);
1505 mlxsw_sp_setup_tc_block_flower_bind(struct mlxsw_sp_port *mlxsw_sp_port,
1506 struct tcf_block *block, bool ingress,
1507 struct netlink_ext_ack *extack)
1509 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1510 struct mlxsw_sp_acl_block *acl_block;
1511 struct tcf_block_cb *block_cb;
1514 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower,
1517 acl_block = mlxsw_sp_acl_block_create(mlxsw_sp, block->net);
1520 block_cb = __tcf_block_cb_register(block,
1521 mlxsw_sp_setup_tc_block_cb_flower,
1522 mlxsw_sp, acl_block, extack);
1523 if (IS_ERR(block_cb)) {
1524 err = PTR_ERR(block_cb);
1525 goto err_cb_register;
1528 acl_block = tcf_block_cb_priv(block_cb);
1530 tcf_block_cb_incref(block_cb);
1531 err = mlxsw_sp_acl_block_bind(mlxsw_sp, acl_block,
1532 mlxsw_sp_port, ingress);
1534 goto err_block_bind;
1537 mlxsw_sp_port->ing_acl_block = acl_block;
1539 mlxsw_sp_port->eg_acl_block = acl_block;
1544 if (!tcf_block_cb_decref(block_cb)) {
1545 __tcf_block_cb_unregister(block, block_cb);
1547 mlxsw_sp_acl_block_destroy(acl_block);
1553 mlxsw_sp_setup_tc_block_flower_unbind(struct mlxsw_sp_port *mlxsw_sp_port,
1554 struct tcf_block *block, bool ingress)
1556 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1557 struct mlxsw_sp_acl_block *acl_block;
1558 struct tcf_block_cb *block_cb;
1561 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower,
1567 mlxsw_sp_port->ing_acl_block = NULL;
1569 mlxsw_sp_port->eg_acl_block = NULL;
1571 acl_block = tcf_block_cb_priv(block_cb);
1572 err = mlxsw_sp_acl_block_unbind(mlxsw_sp, acl_block,
1573 mlxsw_sp_port, ingress);
1574 if (!err && !tcf_block_cb_decref(block_cb)) {
1575 __tcf_block_cb_unregister(block, block_cb);
1576 mlxsw_sp_acl_block_destroy(acl_block);
1580 static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port,
1581 struct tc_block_offload *f)
1587 if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) {
1588 cb = mlxsw_sp_setup_tc_block_cb_matchall_ig;
1590 } else if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_EGRESS) {
1591 cb = mlxsw_sp_setup_tc_block_cb_matchall_eg;
1597 switch (f->command) {
1599 err = tcf_block_cb_register(f->block, cb, mlxsw_sp_port,
1600 mlxsw_sp_port, f->extack);
1603 err = mlxsw_sp_setup_tc_block_flower_bind(mlxsw_sp_port,
1607 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1611 case TC_BLOCK_UNBIND:
1612 mlxsw_sp_setup_tc_block_flower_unbind(mlxsw_sp_port,
1614 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1621 static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type,
1624 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1627 case TC_SETUP_BLOCK:
1628 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data);
1629 case TC_SETUP_QDISC_RED:
1630 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data);
1631 case TC_SETUP_QDISC_PRIO:
1632 return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data);
1639 static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable)
1641 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1644 if (mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->ing_acl_block) ||
1645 mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->eg_acl_block) ||
1646 !list_empty(&mlxsw_sp_port->mall_tc_list)) {
1647 netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n");
1650 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->ing_acl_block);
1651 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->eg_acl_block);
1653 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->ing_acl_block);
1654 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->eg_acl_block);
1659 typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable);
1661 static int mlxsw_sp_handle_feature(struct net_device *dev,
1662 netdev_features_t wanted_features,
1663 netdev_features_t feature,
1664 mlxsw_sp_feature_handler feature_handler)
1666 netdev_features_t changes = wanted_features ^ dev->features;
1667 bool enable = !!(wanted_features & feature);
1670 if (!(changes & feature))
1673 err = feature_handler(dev, enable);
1675 netdev_err(dev, "%s feature %pNF failed, err %d\n",
1676 enable ? "Enable" : "Disable", &feature, err);
1681 dev->features |= feature;
1683 dev->features &= ~feature;
1687 static int mlxsw_sp_set_features(struct net_device *dev,
1688 netdev_features_t features)
1690 return mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC,
1691 mlxsw_sp_feature_hw_tc);
1694 static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1695 .ndo_open = mlxsw_sp_port_open,
1696 .ndo_stop = mlxsw_sp_port_stop,
1697 .ndo_start_xmit = mlxsw_sp_port_xmit,
1698 .ndo_setup_tc = mlxsw_sp_setup_tc,
1699 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
1700 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
1701 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
1702 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
1703 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
1704 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
1705 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
1706 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
1707 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
1708 .ndo_set_features = mlxsw_sp_set_features,
1711 static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1712 struct ethtool_drvinfo *drvinfo)
1714 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1715 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1717 strlcpy(drvinfo->driver, mlxsw_sp->bus_info->device_kind,
1718 sizeof(drvinfo->driver));
1719 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1720 sizeof(drvinfo->version));
1721 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1723 mlxsw_sp->bus_info->fw_rev.major,
1724 mlxsw_sp->bus_info->fw_rev.minor,
1725 mlxsw_sp->bus_info->fw_rev.subminor);
1726 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1727 sizeof(drvinfo->bus_info));
1730 static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1731 struct ethtool_pauseparam *pause)
1733 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1735 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1736 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1739 static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1740 struct ethtool_pauseparam *pause)
1742 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1744 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1745 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1746 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1748 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1752 static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1753 struct ethtool_pauseparam *pause)
1755 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1756 bool pause_en = pause->tx_pause || pause->rx_pause;
1759 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1760 netdev_err(dev, "PFC already enabled on port\n");
1764 if (pause->autoneg) {
1765 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1769 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1771 netdev_err(dev, "Failed to configure port's headroom\n");
1775 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1777 netdev_err(dev, "Failed to set PAUSE parameters\n");
1778 goto err_port_pause_configure;
1781 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1782 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1786 err_port_pause_configure:
1787 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1788 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1792 struct mlxsw_sp_port_hw_stats {
1793 char str[ETH_GSTRING_LEN];
1794 u64 (*getter)(const char *payload);
1798 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
1800 .str = "a_frames_transmitted_ok",
1801 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1804 .str = "a_frames_received_ok",
1805 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1808 .str = "a_frame_check_sequence_errors",
1809 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1812 .str = "a_alignment_errors",
1813 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1816 .str = "a_octets_transmitted_ok",
1817 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1820 .str = "a_octets_received_ok",
1821 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1824 .str = "a_multicast_frames_xmitted_ok",
1825 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1828 .str = "a_broadcast_frames_xmitted_ok",
1829 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1832 .str = "a_multicast_frames_received_ok",
1833 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1836 .str = "a_broadcast_frames_received_ok",
1837 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1840 .str = "a_in_range_length_errors",
1841 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1844 .str = "a_out_of_range_length_field",
1845 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1848 .str = "a_frame_too_long_errors",
1849 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1852 .str = "a_symbol_error_during_carrier",
1853 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1856 .str = "a_mac_control_frames_transmitted",
1857 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1860 .str = "a_mac_control_frames_received",
1861 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1864 .str = "a_unsupported_opcodes_received",
1865 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1868 .str = "a_pause_mac_ctrl_frames_received",
1869 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1872 .str = "a_pause_mac_ctrl_frames_xmitted",
1873 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1877 #define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
1879 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_rfc_2819_stats[] = {
1881 .str = "ether_pkts64octets",
1882 .getter = mlxsw_reg_ppcnt_ether_stats_pkts64octets_get,
1885 .str = "ether_pkts65to127octets",
1886 .getter = mlxsw_reg_ppcnt_ether_stats_pkts65to127octets_get,
1889 .str = "ether_pkts128to255octets",
1890 .getter = mlxsw_reg_ppcnt_ether_stats_pkts128to255octets_get,
1893 .str = "ether_pkts256to511octets",
1894 .getter = mlxsw_reg_ppcnt_ether_stats_pkts256to511octets_get,
1897 .str = "ether_pkts512to1023octets",
1898 .getter = mlxsw_reg_ppcnt_ether_stats_pkts512to1023octets_get,
1901 .str = "ether_pkts1024to1518octets",
1902 .getter = mlxsw_reg_ppcnt_ether_stats_pkts1024to1518octets_get,
1905 .str = "ether_pkts1519to2047octets",
1906 .getter = mlxsw_reg_ppcnt_ether_stats_pkts1519to2047octets_get,
1909 .str = "ether_pkts2048to4095octets",
1910 .getter = mlxsw_reg_ppcnt_ether_stats_pkts2048to4095octets_get,
1913 .str = "ether_pkts4096to8191octets",
1914 .getter = mlxsw_reg_ppcnt_ether_stats_pkts4096to8191octets_get,
1917 .str = "ether_pkts8192to10239octets",
1918 .getter = mlxsw_reg_ppcnt_ether_stats_pkts8192to10239octets_get,
1922 #define MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN \
1923 ARRAY_SIZE(mlxsw_sp_port_hw_rfc_2819_stats)
1925 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
1927 .str = "rx_octets_prio",
1928 .getter = mlxsw_reg_ppcnt_rx_octets_get,
1931 .str = "rx_frames_prio",
1932 .getter = mlxsw_reg_ppcnt_rx_frames_get,
1935 .str = "tx_octets_prio",
1936 .getter = mlxsw_reg_ppcnt_tx_octets_get,
1939 .str = "tx_frames_prio",
1940 .getter = mlxsw_reg_ppcnt_tx_frames_get,
1943 .str = "rx_pause_prio",
1944 .getter = mlxsw_reg_ppcnt_rx_pause_get,
1947 .str = "rx_pause_duration_prio",
1948 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
1951 .str = "tx_pause_prio",
1952 .getter = mlxsw_reg_ppcnt_tx_pause_get,
1955 .str = "tx_pause_duration_prio",
1956 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
1960 #define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
1962 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
1964 .str = "tc_transmit_queue_tc",
1965 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
1966 .cells_bytes = true,
1969 .str = "tc_no_buffer_discard_uc_tc",
1970 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
1974 #define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
1976 #define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
1977 MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN + \
1978 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN * \
1979 IEEE_8021QAZ_MAX_TCS) + \
1980 (MLXSW_SP_PORT_HW_TC_STATS_LEN * \
1983 static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
1987 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
1988 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1989 mlxsw_sp_port_hw_prio_stats[i].str, prio);
1990 *p += ETH_GSTRING_LEN;
1994 static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
1998 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
1999 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
2000 mlxsw_sp_port_hw_tc_stats[i].str, tc);
2001 *p += ETH_GSTRING_LEN;
2005 static void mlxsw_sp_port_get_strings(struct net_device *dev,
2006 u32 stringset, u8 *data)
2011 switch (stringset) {
2013 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
2014 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
2016 p += ETH_GSTRING_LEN;
2018 for (i = 0; i < MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN; i++) {
2019 memcpy(p, mlxsw_sp_port_hw_rfc_2819_stats[i].str,
2021 p += ETH_GSTRING_LEN;
2024 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2025 mlxsw_sp_port_get_prio_strings(&p, i);
2027 for (i = 0; i < TC_MAX_QUEUE; i++)
2028 mlxsw_sp_port_get_tc_strings(&p, i);
2034 static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
2035 enum ethtool_phys_id_state state)
2037 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2038 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2039 char mlcr_pl[MLXSW_REG_MLCR_LEN];
2043 case ETHTOOL_ID_ACTIVE:
2046 case ETHTOOL_ID_INACTIVE:
2053 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
2054 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
2058 mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
2059 int *p_len, enum mlxsw_reg_ppcnt_grp grp)
2062 case MLXSW_REG_PPCNT_IEEE_8023_CNT:
2063 *p_hw_stats = mlxsw_sp_port_hw_stats;
2064 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
2066 case MLXSW_REG_PPCNT_RFC_2819_CNT:
2067 *p_hw_stats = mlxsw_sp_port_hw_rfc_2819_stats;
2068 *p_len = MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN;
2070 case MLXSW_REG_PPCNT_PRIO_CNT:
2071 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
2072 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2074 case MLXSW_REG_PPCNT_TC_CNT:
2075 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
2076 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
2085 static void __mlxsw_sp_port_get_stats(struct net_device *dev,
2086 enum mlxsw_reg_ppcnt_grp grp, int prio,
2087 u64 *data, int data_index)
2089 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2090 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2091 struct mlxsw_sp_port_hw_stats *hw_stats;
2092 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
2096 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
2099 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
2100 for (i = 0; i < len; i++) {
2101 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
2102 if (!hw_stats[i].cells_bytes)
2104 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
2105 data[data_index + i]);
2109 static void mlxsw_sp_port_get_stats(struct net_device *dev,
2110 struct ethtool_stats *stats, u64 *data)
2112 int i, data_index = 0;
2114 /* IEEE 802.3 Counters */
2115 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
2117 data_index = MLXSW_SP_PORT_HW_STATS_LEN;
2119 /* RFC 2819 Counters */
2120 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_RFC_2819_CNT, 0,
2122 data_index += MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN;
2124 /* Per-Priority Counters */
2125 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2126 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
2128 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2131 /* Per-TC Counters */
2132 for (i = 0; i < TC_MAX_QUEUE; i++) {
2133 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
2135 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
2139 static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
2143 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
2149 struct mlxsw_sp_port_link_mode {
2150 enum ethtool_link_mode_bit_indices mask_ethtool;
2155 static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
2157 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
2158 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2162 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
2163 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
2164 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2165 .speed = SPEED_1000,
2168 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
2169 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2170 .speed = SPEED_10000,
2173 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
2174 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
2175 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2176 .speed = SPEED_10000,
2179 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2180 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2181 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2182 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
2183 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2184 .speed = SPEED_10000,
2187 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
2188 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
2189 .speed = SPEED_20000,
2192 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
2193 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2194 .speed = SPEED_40000,
2197 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
2198 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2199 .speed = SPEED_40000,
2202 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
2203 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2204 .speed = SPEED_40000,
2207 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
2208 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2209 .speed = SPEED_40000,
2212 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
2213 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2214 .speed = SPEED_25000,
2217 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
2218 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2219 .speed = SPEED_25000,
2222 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2223 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2224 .speed = SPEED_25000,
2227 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2228 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2229 .speed = SPEED_25000,
2232 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
2233 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2234 .speed = SPEED_50000,
2237 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
2238 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2239 .speed = SPEED_50000,
2242 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
2243 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2244 .speed = SPEED_50000,
2247 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2248 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
2249 .speed = SPEED_56000,
2252 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2253 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
2254 .speed = SPEED_56000,
2257 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2258 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
2259 .speed = SPEED_56000,
2262 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2263 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
2264 .speed = SPEED_56000,
2267 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
2268 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2269 .speed = SPEED_100000,
2272 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
2273 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2274 .speed = SPEED_100000,
2277 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
2278 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2279 .speed = SPEED_100000,
2282 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
2283 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2284 .speed = SPEED_100000,
2288 #define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
2291 mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
2292 struct ethtool_link_ksettings *cmd)
2294 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2295 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2296 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2297 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2298 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2299 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2300 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
2302 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2303 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2304 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2305 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
2306 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
2307 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
2310 static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
2314 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2315 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
2316 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2321 static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
2322 struct ethtool_link_ksettings *cmd)
2324 u32 speed = SPEED_UNKNOWN;
2325 u8 duplex = DUPLEX_UNKNOWN;
2331 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2332 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
2333 speed = mlxsw_sp_port_link_mode[i].speed;
2334 duplex = DUPLEX_FULL;
2339 cmd->base.speed = speed;
2340 cmd->base.duplex = duplex;
2343 static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
2345 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2346 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2347 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2348 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2351 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2352 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2353 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
2356 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2357 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2358 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2359 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
2366 mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
2371 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2372 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2373 cmd->link_modes.advertising))
2374 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2379 static u32 mlxsw_sp_to_ptys_speed(u32 speed)
2384 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2385 if (speed == mlxsw_sp_port_link_mode[i].speed)
2386 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2391 static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
2396 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2397 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
2398 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2403 static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
2404 struct ethtool_link_ksettings *cmd)
2406 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
2407 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
2408 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
2410 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
2411 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
2414 static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
2415 struct ethtool_link_ksettings *cmd)
2420 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
2421 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
2425 mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
2426 struct ethtool_link_ksettings *cmd)
2428 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
2431 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
2432 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
2435 static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
2436 struct ethtool_link_ksettings *cmd)
2438 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
2439 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2440 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2441 char ptys_pl[MLXSW_REG_PTYS_LEN];
2446 autoneg = mlxsw_sp_port->link.autoneg;
2447 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0, false);
2448 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2451 mlxsw_reg_ptys_eth_unpack(ptys_pl, ð_proto_cap, ð_proto_admin,
2454 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
2456 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
2458 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
2459 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
2460 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
2462 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2463 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
2464 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
2471 mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
2472 const struct ethtool_link_ksettings *cmd)
2474 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2475 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2476 char ptys_pl[MLXSW_REG_PTYS_LEN];
2477 u32 eth_proto_cap, eth_proto_new;
2481 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0, false);
2482 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2485 mlxsw_reg_ptys_eth_unpack(ptys_pl, ð_proto_cap, NULL, NULL);
2487 autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
2488 eth_proto_new = autoneg ?
2489 mlxsw_sp_to_ptys_advert_link(cmd) :
2490 mlxsw_sp_to_ptys_speed(cmd->base.speed);
2492 eth_proto_new = eth_proto_new & eth_proto_cap;
2493 if (!eth_proto_new) {
2494 netdev_err(dev, "No supported speed requested\n");
2498 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2499 eth_proto_new, autoneg);
2500 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2504 if (!netif_running(dev))
2507 mlxsw_sp_port->link.autoneg = autoneg;
2509 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2510 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
2515 static int mlxsw_sp_flash_device(struct net_device *dev,
2516 struct ethtool_flash *flash)
2518 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2519 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2520 const struct firmware *firmware;
2523 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
2529 err = request_firmware_direct(&firmware, flash->data, &dev->dev);
2532 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
2533 release_firmware(firmware);
2540 #define MLXSW_SP_I2C_ADDR_LOW 0x50
2541 #define MLXSW_SP_I2C_ADDR_HIGH 0x51
2542 #define MLXSW_SP_EEPROM_PAGE_LENGTH 256
2544 static int mlxsw_sp_query_module_eeprom(struct mlxsw_sp_port *mlxsw_sp_port,
2545 u16 offset, u16 size, void *data,
2546 unsigned int *p_read_size)
2548 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2549 char eeprom_tmp[MLXSW_SP_REG_MCIA_EEPROM_SIZE];
2550 char mcia_pl[MLXSW_REG_MCIA_LEN];
2555 size = min_t(u16, size, MLXSW_SP_REG_MCIA_EEPROM_SIZE);
2557 if (offset < MLXSW_SP_EEPROM_PAGE_LENGTH &&
2558 offset + size > MLXSW_SP_EEPROM_PAGE_LENGTH)
2559 /* Cross pages read, read until offset 256 in low page */
2560 size = MLXSW_SP_EEPROM_PAGE_LENGTH - offset;
2562 i2c_addr = MLXSW_SP_I2C_ADDR_LOW;
2563 if (offset >= MLXSW_SP_EEPROM_PAGE_LENGTH) {
2564 i2c_addr = MLXSW_SP_I2C_ADDR_HIGH;
2565 offset -= MLXSW_SP_EEPROM_PAGE_LENGTH;
2568 mlxsw_reg_mcia_pack(mcia_pl, mlxsw_sp_port->mapping.module,
2569 0, 0, offset, size, i2c_addr);
2571 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcia), mcia_pl);
2575 status = mlxsw_reg_mcia_status_get(mcia_pl);
2579 mlxsw_reg_mcia_eeprom_memcpy_from(mcia_pl, eeprom_tmp);
2580 memcpy(data, eeprom_tmp, size);
2581 *p_read_size = size;
2586 enum mlxsw_sp_eeprom_module_info_rev_id {
2587 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00,
2588 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01,
2589 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03,
2592 enum mlxsw_sp_eeprom_module_info_id {
2593 MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP = 0x03,
2594 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP = 0x0C,
2595 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D,
2596 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11,
2599 enum mlxsw_sp_eeprom_module_info {
2600 MLXSW_SP_EEPROM_MODULE_INFO_ID,
2601 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID,
2602 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2605 static int mlxsw_sp_get_module_info(struct net_device *netdev,
2606 struct ethtool_modinfo *modinfo)
2608 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2609 u8 module_info[MLXSW_SP_EEPROM_MODULE_INFO_SIZE];
2610 u8 module_rev_id, module_id;
2611 unsigned int read_size;
2614 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, 0,
2615 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2616 module_info, &read_size);
2620 if (read_size < MLXSW_SP_EEPROM_MODULE_INFO_SIZE)
2623 module_rev_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_REV_ID];
2624 module_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_ID];
2626 switch (module_id) {
2627 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP:
2628 modinfo->type = ETH_MODULE_SFF_8436;
2629 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2631 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS:
2632 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28:
2633 if (module_id == MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 ||
2634 module_rev_id >= MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636) {
2635 modinfo->type = ETH_MODULE_SFF_8636;
2636 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
2638 modinfo->type = ETH_MODULE_SFF_8436;
2639 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2642 case MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP:
2643 modinfo->type = ETH_MODULE_SFF_8472;
2644 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2653 static int mlxsw_sp_get_module_eeprom(struct net_device *netdev,
2654 struct ethtool_eeprom *ee,
2657 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2658 int offset = ee->offset;
2659 unsigned int read_size;
2666 memset(data, 0, ee->len);
2668 while (i < ee->len) {
2669 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, offset,
2670 ee->len - i, data + i,
2673 netdev_err(mlxsw_sp_port->dev, "Eeprom query failed\n");
2678 offset += read_size;
2684 static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
2685 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
2686 .get_link = ethtool_op_get_link,
2687 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
2688 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
2689 .get_strings = mlxsw_sp_port_get_strings,
2690 .set_phys_id = mlxsw_sp_port_set_phys_id,
2691 .get_ethtool_stats = mlxsw_sp_port_get_stats,
2692 .get_sset_count = mlxsw_sp_port_get_sset_count,
2693 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
2694 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
2695 .flash_device = mlxsw_sp_flash_device,
2696 .get_module_info = mlxsw_sp_get_module_info,
2697 .get_module_eeprom = mlxsw_sp_get_module_eeprom,
2701 mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
2703 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2704 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
2705 char ptys_pl[MLXSW_REG_PTYS_LEN];
2706 u32 eth_proto_admin;
2708 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
2709 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2710 eth_proto_admin, mlxsw_sp_port->link.autoneg);
2711 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2714 int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
2715 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
2716 bool dwrr, u8 dwrr_weight)
2718 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2719 char qeec_pl[MLXSW_REG_QEEC_LEN];
2721 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2723 mlxsw_reg_qeec_de_set(qeec_pl, true);
2724 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
2725 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
2726 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2729 int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
2730 enum mlxsw_reg_qeec_hr hr, u8 index,
2731 u8 next_index, u32 maxrate)
2733 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2734 char qeec_pl[MLXSW_REG_QEEC_LEN];
2736 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2738 mlxsw_reg_qeec_mase_set(qeec_pl, true);
2739 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
2740 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2743 int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
2744 u8 switch_prio, u8 tclass)
2746 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2747 char qtct_pl[MLXSW_REG_QTCT_LEN];
2749 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
2751 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
2754 static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
2758 /* Setup the elements hierarcy, so that each TC is linked to
2759 * one subgroup, which are all member in the same group.
2761 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2762 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
2766 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2767 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2768 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
2773 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2774 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2775 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
2780 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2781 MLXSW_REG_QEEC_HIERARCY_TC,
2788 /* Make sure the max shaper is disabled in all hierarchies that
2791 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2792 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
2793 MLXSW_REG_QEEC_MAS_DIS);
2796 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2797 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2798 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
2800 MLXSW_REG_QEEC_MAS_DIS);
2804 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2805 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2806 MLXSW_REG_QEEC_HIERARCY_TC,
2808 MLXSW_REG_QEEC_MAS_DIS);
2812 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2813 MLXSW_REG_QEEC_HIERARCY_TC,
2815 MLXSW_REG_QEEC_MAS_DIS);
2820 /* Map all priorities to traffic class 0. */
2821 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2822 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
2830 static int mlxsw_sp_port_tc_mc_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
2833 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2834 char qtctm_pl[MLXSW_REG_QTCTM_LEN];
2836 mlxsw_reg_qtctm_pack(qtctm_pl, mlxsw_sp_port->local_port, enable);
2837 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtctm), qtctm_pl);
2840 static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2841 bool split, u8 module, u8 width, u8 lane)
2843 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
2844 struct mlxsw_sp_port *mlxsw_sp_port;
2845 struct net_device *dev;
2848 err = mlxsw_core_port_init(mlxsw_sp->core, local_port);
2850 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
2855 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
2858 goto err_alloc_etherdev;
2860 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
2861 mlxsw_sp_port = netdev_priv(dev);
2862 mlxsw_sp_port->dev = dev;
2863 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
2864 mlxsw_sp_port->local_port = local_port;
2865 mlxsw_sp_port->pvid = 1;
2866 mlxsw_sp_port->split = split;
2867 mlxsw_sp_port->mapping.module = module;
2868 mlxsw_sp_port->mapping.width = width;
2869 mlxsw_sp_port->mapping.lane = lane;
2870 mlxsw_sp_port->link.autoneg = 1;
2871 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
2872 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
2874 mlxsw_sp_port->pcpu_stats =
2875 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
2876 if (!mlxsw_sp_port->pcpu_stats) {
2878 goto err_alloc_stats;
2881 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
2883 if (!mlxsw_sp_port->sample) {
2885 goto err_alloc_sample;
2888 INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw,
2889 &update_stats_cache);
2891 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
2892 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
2894 err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane);
2896 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
2897 mlxsw_sp_port->local_port);
2898 goto err_port_module_map;
2901 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
2903 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
2904 mlxsw_sp_port->local_port);
2905 goto err_port_swid_set;
2908 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
2910 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
2911 mlxsw_sp_port->local_port);
2912 goto err_dev_addr_init;
2915 netif_carrier_off(dev);
2917 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
2918 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
2919 dev->hw_features |= NETIF_F_HW_TC;
2922 dev->max_mtu = ETH_MAX_MTU;
2924 /* Each packet needs to have a Tx header (metadata) on top all other
2927 dev->needed_headroom = MLXSW_TXHDR_LEN;
2929 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
2931 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
2932 mlxsw_sp_port->local_port);
2933 goto err_port_system_port_mapping_set;
2936 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
2938 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
2939 mlxsw_sp_port->local_port);
2940 goto err_port_speed_by_width_set;
2943 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
2945 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
2946 mlxsw_sp_port->local_port);
2947 goto err_port_mtu_set;
2950 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2952 goto err_port_admin_status_set;
2954 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
2956 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
2957 mlxsw_sp_port->local_port);
2958 goto err_port_buffers_init;
2961 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
2963 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
2964 mlxsw_sp_port->local_port);
2965 goto err_port_ets_init;
2968 err = mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, true);
2970 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC MC mode\n",
2971 mlxsw_sp_port->local_port);
2972 goto err_port_tc_mc_mode;
2975 /* ETS and buffers must be initialized before DCB. */
2976 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
2978 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
2979 mlxsw_sp_port->local_port);
2980 goto err_port_dcb_init;
2983 err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
2985 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
2986 mlxsw_sp_port->local_port);
2987 goto err_port_fids_init;
2990 err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port);
2992 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n",
2993 mlxsw_sp_port->local_port);
2994 goto err_port_qdiscs_init;
2997 err = mlxsw_sp_port_nve_init(mlxsw_sp_port);
2999 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize NVE\n",
3000 mlxsw_sp_port->local_port);
3001 goto err_port_nve_init;
3004 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
3005 if (IS_ERR(mlxsw_sp_port_vlan)) {
3006 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
3007 mlxsw_sp_port->local_port);
3008 err = PTR_ERR(mlxsw_sp_port_vlan);
3009 goto err_port_vlan_get;
3012 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
3013 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
3014 err = register_netdev(dev);
3016 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
3017 mlxsw_sp_port->local_port);
3018 goto err_register_netdev;
3021 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
3022 mlxsw_sp_port, dev, module + 1,
3023 mlxsw_sp_port->split, lane / width);
3024 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0);
3027 err_register_netdev:
3028 mlxsw_sp->ports[local_port] = NULL;
3029 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
3030 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
3032 mlxsw_sp_port_nve_fini(mlxsw_sp_port);
3034 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
3035 err_port_qdiscs_init:
3036 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
3038 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
3040 mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false);
3041 err_port_tc_mc_mode:
3043 err_port_buffers_init:
3044 err_port_admin_status_set:
3046 err_port_speed_by_width_set:
3047 err_port_system_port_mapping_set:
3049 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
3051 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
3052 err_port_module_map:
3053 kfree(mlxsw_sp_port->sample);
3055 free_percpu(mlxsw_sp_port->pcpu_stats);
3059 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3063 static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
3065 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3067 cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw);
3068 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
3069 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
3070 mlxsw_sp->ports[local_port] = NULL;
3071 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
3072 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
3073 mlxsw_sp_port_nve_fini(mlxsw_sp_port);
3074 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
3075 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
3076 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
3077 mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false);
3078 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
3079 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
3080 kfree(mlxsw_sp_port->sample);
3081 free_percpu(mlxsw_sp_port->pcpu_stats);
3082 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
3083 free_netdev(mlxsw_sp_port->dev);
3084 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3087 static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
3089 return mlxsw_sp->ports[local_port] != NULL;
3092 static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
3096 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
3097 if (mlxsw_sp_port_created(mlxsw_sp, i))
3098 mlxsw_sp_port_remove(mlxsw_sp, i);
3099 kfree(mlxsw_sp->port_to_module);
3100 kfree(mlxsw_sp->ports);
3103 static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
3105 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
3106 u8 module, width, lane;
3111 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
3112 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
3113 if (!mlxsw_sp->ports)
3116 mlxsw_sp->port_to_module = kmalloc_array(max_ports, sizeof(int),
3118 if (!mlxsw_sp->port_to_module) {
3120 goto err_port_to_module_alloc;
3123 for (i = 1; i < max_ports; i++) {
3124 /* Mark as invalid */
3125 mlxsw_sp->port_to_module[i] = -1;
3127 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
3130 goto err_port_module_info_get;
3133 mlxsw_sp->port_to_module[i] = module;
3134 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
3135 module, width, lane);
3137 goto err_port_create;
3142 err_port_module_info_get:
3143 for (i--; i >= 1; i--)
3144 if (mlxsw_sp_port_created(mlxsw_sp, i))
3145 mlxsw_sp_port_remove(mlxsw_sp, i);
3146 kfree(mlxsw_sp->port_to_module);
3147 err_port_to_module_alloc:
3148 kfree(mlxsw_sp->ports);
3152 static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
3154 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
3156 return local_port - offset;
3159 static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
3160 u8 module, unsigned int count)
3162 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
3165 for (i = 0; i < count; i++) {
3166 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
3167 module, width, i * width);
3169 goto err_port_create;
3175 for (i--; i >= 0; i--)
3176 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3177 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
3181 static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
3182 u8 base_port, unsigned int count)
3184 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
3187 /* Split by four means we need to re-create two ports, otherwise
3192 for (i = 0; i < count; i++) {
3193 local_port = base_port + i * 2;
3194 if (mlxsw_sp->port_to_module[local_port] < 0)
3196 module = mlxsw_sp->port_to_module[local_port];
3198 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
3203 static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
3205 struct netlink_ext_ack *extack)
3207 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3208 struct mlxsw_sp_port *mlxsw_sp_port;
3209 u8 module, cur_width, base_port;
3213 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3214 if (!mlxsw_sp_port) {
3215 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3217 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
3221 module = mlxsw_sp_port->mapping.module;
3222 cur_width = mlxsw_sp_port->mapping.width;
3224 if (count != 2 && count != 4) {
3225 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
3226 NL_SET_ERR_MSG_MOD(extack, "Port can only be split into 2 or 4 ports");
3230 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
3231 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
3232 NL_SET_ERR_MSG_MOD(extack, "Port cannot be split further");
3236 /* Make sure we have enough slave (even) ports for the split. */
3238 base_port = local_port;
3239 if (mlxsw_sp->ports[base_port + 1]) {
3240 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3241 NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration");
3245 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3246 if (mlxsw_sp->ports[base_port + 1] ||
3247 mlxsw_sp->ports[base_port + 3]) {
3248 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3249 NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration");
3254 for (i = 0; i < count; i++)
3255 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3256 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
3258 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
3260 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
3261 goto err_port_split_create;
3266 err_port_split_create:
3267 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
3271 static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port,
3272 struct netlink_ext_ack *extack)
3274 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3275 struct mlxsw_sp_port *mlxsw_sp_port;
3276 u8 cur_width, base_port;
3280 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3281 if (!mlxsw_sp_port) {
3282 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3284 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
3288 if (!mlxsw_sp_port->split) {
3289 netdev_err(mlxsw_sp_port->dev, "Port was not split\n");
3290 NL_SET_ERR_MSG_MOD(extack, "Port was not split");
3294 cur_width = mlxsw_sp_port->mapping.width;
3295 count = cur_width == 1 ? 4 : 2;
3297 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3299 /* Determine which ports to remove. */
3300 if (count == 2 && local_port >= base_port + 2)
3301 base_port = base_port + 2;
3303 for (i = 0; i < count; i++)
3304 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3305 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
3307 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
3312 static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
3313 char *pude_pl, void *priv)
3315 struct mlxsw_sp *mlxsw_sp = priv;
3316 struct mlxsw_sp_port *mlxsw_sp_port;
3317 enum mlxsw_reg_pude_oper_status status;
3320 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
3321 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3325 status = mlxsw_reg_pude_oper_status_get(pude_pl);
3326 if (status == MLXSW_PORT_OPER_STATUS_UP) {
3327 netdev_info(mlxsw_sp_port->dev, "link up\n");
3328 netif_carrier_on(mlxsw_sp_port->dev);
3330 netdev_info(mlxsw_sp_port->dev, "link down\n");
3331 netif_carrier_off(mlxsw_sp_port->dev);
3335 static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
3336 u8 local_port, void *priv)
3338 struct mlxsw_sp *mlxsw_sp = priv;
3339 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3340 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
3342 if (unlikely(!mlxsw_sp_port)) {
3343 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
3348 skb->dev = mlxsw_sp_port->dev;
3350 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
3351 u64_stats_update_begin(&pcpu_stats->syncp);
3352 pcpu_stats->rx_packets++;
3353 pcpu_stats->rx_bytes += skb->len;
3354 u64_stats_update_end(&pcpu_stats->syncp);
3356 skb->protocol = eth_type_trans(skb, skb->dev);
3357 netif_receive_skb(skb);
3360 static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
3363 skb->offload_fwd_mark = 1;
3364 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
3367 static void mlxsw_sp_rx_listener_mr_mark_func(struct sk_buff *skb,
3368 u8 local_port, void *priv)
3370 skb->offload_mr_fwd_mark = 1;
3371 skb->offload_fwd_mark = 1;
3372 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
3375 static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
3378 struct mlxsw_sp *mlxsw_sp = priv;
3379 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3380 struct psample_group *psample_group;
3383 if (unlikely(!mlxsw_sp_port)) {
3384 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
3388 if (unlikely(!mlxsw_sp_port->sample)) {
3389 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
3394 size = mlxsw_sp_port->sample->truncate ?
3395 mlxsw_sp_port->sample->trunc_size : skb->len;
3398 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
3401 psample_sample_packet(psample_group, skb, size,
3402 mlxsw_sp_port->dev->ifindex, 0,
3403 mlxsw_sp_port->sample->rate);
3410 #define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
3411 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
3412 _is_ctrl, SP_##_trap_group, DISCARD)
3414 #define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
3415 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
3416 _is_ctrl, SP_##_trap_group, DISCARD)
3418 #define MLXSW_SP_RXL_MR_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
3419 MLXSW_RXL(mlxsw_sp_rx_listener_mr_mark_func, _trap_id, _action, \
3420 _is_ctrl, SP_##_trap_group, DISCARD)
3422 #define MLXSW_SP_EVENTL(_func, _trap_id) \
3423 MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
3425 static const struct mlxsw_listener mlxsw_sp_listener[] = {
3427 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
3429 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
3430 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
3431 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true),
3432 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
3433 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
3434 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
3435 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
3436 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
3437 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
3438 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
3439 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
3440 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),
3441 MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU, IPV6_MLD,
3443 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3445 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_DONE, TRAP_TO_CPU, IPV6_MLD,
3447 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV2_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3450 MLXSW_SP_RXL_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3451 MLXSW_SP_RXL_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3452 MLXSW_SP_RXL_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3453 MLXSW_SP_RXL_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
3454 MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP,
3456 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, false),
3457 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false),
3458 MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, ROUTER_EXP, false),
3459 MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, ROUTER_EXP,
3461 MLXSW_SP_RXL_MARK(IPV4_OSPF, TRAP_TO_CPU, OSPF, false),
3462 MLXSW_SP_RXL_MARK(IPV6_OSPF, TRAP_TO_CPU, OSPF, false),
3463 MLXSW_SP_RXL_MARK(IPV6_DHCP, TRAP_TO_CPU, DHCP, false),
3464 MLXSW_SP_RXL_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
3465 MLXSW_SP_RXL_MARK(IPV4_BGP, TRAP_TO_CPU, BGP, false),
3466 MLXSW_SP_RXL_MARK(IPV6_BGP, TRAP_TO_CPU, BGP, false),
3467 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3469 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3471 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3473 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3475 MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6_ND, false),
3476 MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP,
3478 MLXSW_SP_RXL_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, HOST_MISS, false),
3479 MLXSW_SP_RXL_MARK(HOST_MISS_IPV6, TRAP_TO_CPU, HOST_MISS, false),
3480 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, ROUTER_EXP, false),
3481 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, ROUTER_EXP, false),
3482 MLXSW_SP_RXL_MARK(IPIP_DECAP_ERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3483 MLXSW_SP_RXL_MARK(DECAP_ECN0, TRAP_TO_CPU, ROUTER_EXP, false),
3484 MLXSW_SP_RXL_MARK(IPV4_VRRP, TRAP_TO_CPU, ROUTER_EXP, false),
3485 MLXSW_SP_RXL_MARK(IPV6_VRRP, TRAP_TO_CPU, ROUTER_EXP, false),
3486 /* PKT Sample trap */
3487 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
3488 false, SP_IP2ME, DISCARD),
3490 MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false),
3491 /* Multicast Router Traps */
3492 MLXSW_SP_RXL_MARK(IPV4_PIM, TRAP_TO_CPU, PIM, false),
3493 MLXSW_SP_RXL_MARK(IPV6_PIM, TRAP_TO_CPU, PIM, false),
3494 MLXSW_SP_RXL_MARK(RPF, TRAP_TO_CPU, RPF, false),
3495 MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false),
3496 MLXSW_SP_RXL_MR_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false),
3498 MLXSW_SP_RXL_MARK(NVE_ENCAP_ARP, TRAP_TO_CPU, ARP, false),
3501 static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
3503 char qpcr_pl[MLXSW_REG_QPCR_LEN];
3504 enum mlxsw_reg_qpcr_ir_units ir_units;
3505 int max_cpu_policers;
3511 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
3514 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
3516 ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
3517 for (i = 0; i < max_cpu_policers; i++) {
3520 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3521 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3522 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3523 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
3524 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
3525 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
3529 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3530 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
3534 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
3535 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3536 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3537 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
3538 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3539 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
3540 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
3541 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
3545 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3554 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
3556 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
3564 static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
3566 char htgt_pl[MLXSW_REG_HTGT_LEN];
3567 enum mlxsw_reg_htgt_trap_group i;
3568 int max_cpu_policers;
3569 int max_trap_groups;
3574 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
3577 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
3578 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
3580 for (i = 0; i < max_trap_groups; i++) {
3583 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3584 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3585 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3586 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
3587 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
3591 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
3592 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3596 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3597 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3598 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
3602 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3603 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
3604 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
3608 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
3609 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3610 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
3611 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
3615 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
3616 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
3617 tc = MLXSW_REG_HTGT_DEFAULT_TC;
3618 policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
3624 if (max_cpu_policers <= policer_id &&
3625 policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
3628 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
3629 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3637 static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
3642 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
3646 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
3650 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
3651 err = mlxsw_core_trap_register(mlxsw_sp->core,
3652 &mlxsw_sp_listener[i],
3655 goto err_listener_register;
3660 err_listener_register:
3661 for (i--; i >= 0; i--) {
3662 mlxsw_core_trap_unregister(mlxsw_sp->core,
3663 &mlxsw_sp_listener[i],
3669 static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
3673 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
3674 mlxsw_core_trap_unregister(mlxsw_sp->core,
3675 &mlxsw_sp_listener[i],
3680 static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
3682 char slcr_pl[MLXSW_REG_SLCR_LEN];
3686 get_random_bytes(&seed, sizeof(seed));
3687 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
3688 MLXSW_REG_SLCR_LAG_HASH_DMAC |
3689 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
3690 MLXSW_REG_SLCR_LAG_HASH_VLANID |
3691 MLXSW_REG_SLCR_LAG_HASH_SIP |
3692 MLXSW_REG_SLCR_LAG_HASH_DIP |
3693 MLXSW_REG_SLCR_LAG_HASH_SPORT |
3694 MLXSW_REG_SLCR_LAG_HASH_DPORT |
3695 MLXSW_REG_SLCR_LAG_HASH_IPPROTO, seed);
3696 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
3700 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
3701 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
3704 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
3705 sizeof(struct mlxsw_sp_upper),
3707 if (!mlxsw_sp->lags)
3713 static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
3715 kfree(mlxsw_sp->lags);
3718 static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
3720 char htgt_pl[MLXSW_REG_HTGT_LEN];
3722 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3723 MLXSW_REG_HTGT_INVALID_POLICER,
3724 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
3725 MLXSW_REG_HTGT_DEFAULT_TC);
3726 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3729 static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
3730 unsigned long event, void *ptr);
3732 static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
3733 const struct mlxsw_bus_info *mlxsw_bus_info)
3735 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3738 mlxsw_sp->core = mlxsw_core;
3739 mlxsw_sp->bus_info = mlxsw_bus_info;
3741 err = mlxsw_sp_fw_rev_validate(mlxsw_sp);
3745 err = mlxsw_sp_base_mac_get(mlxsw_sp);
3747 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
3751 err = mlxsw_sp_kvdl_init(mlxsw_sp);
3753 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n");
3757 err = mlxsw_sp_fids_init(mlxsw_sp);
3759 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
3763 err = mlxsw_sp_traps_init(mlxsw_sp);
3765 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
3766 goto err_traps_init;
3769 err = mlxsw_sp_buffers_init(mlxsw_sp);
3771 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
3772 goto err_buffers_init;
3775 err = mlxsw_sp_lag_init(mlxsw_sp);
3777 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
3781 /* Initialize SPAN before router and switchdev, so that those components
3782 * can call mlxsw_sp_span_respin().
3784 err = mlxsw_sp_span_init(mlxsw_sp);
3786 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
3790 err = mlxsw_sp_switchdev_init(mlxsw_sp);
3792 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
3793 goto err_switchdev_init;
3796 err = mlxsw_sp_counter_pool_init(mlxsw_sp);
3798 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
3799 goto err_counter_pool_init;
3802 err = mlxsw_sp_afa_init(mlxsw_sp);
3804 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n");
3808 err = mlxsw_sp_nve_init(mlxsw_sp);
3810 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize NVE\n");
3814 err = mlxsw_sp_router_init(mlxsw_sp);
3816 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
3817 goto err_router_init;
3820 /* Initialize netdevice notifier after router and SPAN is initialized,
3821 * so that the event handler can use router structures and call SPAN
3824 mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event;
3825 err = register_netdevice_notifier(&mlxsw_sp->netdevice_nb);
3827 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n");
3828 goto err_netdev_notifier;
3831 err = mlxsw_sp_acl_init(mlxsw_sp);
3833 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
3837 err = mlxsw_sp_dpipe_init(mlxsw_sp);
3839 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
3840 goto err_dpipe_init;
3843 err = mlxsw_sp_ports_create(mlxsw_sp);
3845 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
3846 goto err_ports_create;
3852 mlxsw_sp_dpipe_fini(mlxsw_sp);
3854 mlxsw_sp_acl_fini(mlxsw_sp);
3856 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
3857 err_netdev_notifier:
3858 mlxsw_sp_router_fini(mlxsw_sp);
3860 mlxsw_sp_nve_fini(mlxsw_sp);
3862 mlxsw_sp_afa_fini(mlxsw_sp);
3864 mlxsw_sp_counter_pool_fini(mlxsw_sp);
3865 err_counter_pool_init:
3866 mlxsw_sp_switchdev_fini(mlxsw_sp);
3868 mlxsw_sp_span_fini(mlxsw_sp);
3870 mlxsw_sp_lag_fini(mlxsw_sp);
3872 mlxsw_sp_buffers_fini(mlxsw_sp);
3874 mlxsw_sp_traps_fini(mlxsw_sp);
3876 mlxsw_sp_fids_fini(mlxsw_sp);
3878 mlxsw_sp_kvdl_fini(mlxsw_sp);
3882 static int mlxsw_sp1_init(struct mlxsw_core *mlxsw_core,
3883 const struct mlxsw_bus_info *mlxsw_bus_info)
3885 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3887 mlxsw_sp->req_rev = &mlxsw_sp1_fw_rev;
3888 mlxsw_sp->fw_filename = MLXSW_SP1_FW_FILENAME;
3889 mlxsw_sp->kvdl_ops = &mlxsw_sp1_kvdl_ops;
3890 mlxsw_sp->afa_ops = &mlxsw_sp1_act_afa_ops;
3891 mlxsw_sp->afk_ops = &mlxsw_sp1_afk_ops;
3892 mlxsw_sp->mr_tcam_ops = &mlxsw_sp1_mr_tcam_ops;
3893 mlxsw_sp->acl_tcam_ops = &mlxsw_sp1_acl_tcam_ops;
3894 mlxsw_sp->nve_ops_arr = mlxsw_sp1_nve_ops_arr;
3896 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info);
3899 static int mlxsw_sp2_init(struct mlxsw_core *mlxsw_core,
3900 const struct mlxsw_bus_info *mlxsw_bus_info)
3902 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3904 mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops;
3905 mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops;
3906 mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops;
3907 mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops;
3908 mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops;
3909 mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr;
3911 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info);
3914 static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
3916 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3918 mlxsw_sp_ports_remove(mlxsw_sp);
3919 mlxsw_sp_dpipe_fini(mlxsw_sp);
3920 mlxsw_sp_acl_fini(mlxsw_sp);
3921 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
3922 mlxsw_sp_router_fini(mlxsw_sp);
3923 mlxsw_sp_nve_fini(mlxsw_sp);
3924 mlxsw_sp_afa_fini(mlxsw_sp);
3925 mlxsw_sp_counter_pool_fini(mlxsw_sp);
3926 mlxsw_sp_switchdev_fini(mlxsw_sp);
3927 mlxsw_sp_span_fini(mlxsw_sp);
3928 mlxsw_sp_lag_fini(mlxsw_sp);
3929 mlxsw_sp_buffers_fini(mlxsw_sp);
3930 mlxsw_sp_traps_fini(mlxsw_sp);
3931 mlxsw_sp_fids_fini(mlxsw_sp);
3932 mlxsw_sp_kvdl_fini(mlxsw_sp);
3935 static const struct mlxsw_config_profile mlxsw_sp1_config_profile = {
3937 .max_mid = MLXSW_SP_MID_MAX,
3938 .used_flood_tables = 1,
3939 .used_flood_mode = 1,
3941 .max_fid_offset_flood_tables = 3,
3942 .fid_offset_flood_table_size = VLAN_N_VID - 1,
3943 .max_fid_flood_tables = 3,
3944 .fid_flood_table_size = MLXSW_SP_FID_8021D_MAX,
3945 .used_max_ib_mc = 1,
3949 .used_kvd_sizes = 1,
3950 .kvd_hash_single_parts = 59,
3951 .kvd_hash_double_parts = 41,
3952 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
3956 .type = MLXSW_PORT_SWID_TYPE_ETH,
3961 static const struct mlxsw_config_profile mlxsw_sp2_config_profile = {
3963 .max_mid = MLXSW_SP_MID_MAX,
3964 .used_flood_tables = 1,
3965 .used_flood_mode = 1,
3967 .max_fid_offset_flood_tables = 3,
3968 .fid_offset_flood_table_size = VLAN_N_VID - 1,
3969 .max_fid_flood_tables = 3,
3970 .fid_flood_table_size = MLXSW_SP_FID_8021D_MAX,
3971 .used_max_ib_mc = 1,
3978 .type = MLXSW_PORT_SWID_TYPE_ETH,
3984 mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core,
3985 struct devlink_resource_size_params *kvd_size_params,
3986 struct devlink_resource_size_params *linear_size_params,
3987 struct devlink_resource_size_params *hash_double_size_params,
3988 struct devlink_resource_size_params *hash_single_size_params)
3990 u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
3991 KVD_SINGLE_MIN_SIZE);
3992 u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
3993 KVD_DOUBLE_MIN_SIZE);
3994 u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
3995 u32 linear_size_min = 0;
3997 devlink_resource_size_params_init(kvd_size_params, kvd_size, kvd_size,
3998 MLXSW_SP_KVD_GRANULARITY,
3999 DEVLINK_RESOURCE_UNIT_ENTRY);
4000 devlink_resource_size_params_init(linear_size_params, linear_size_min,
4001 kvd_size - single_size_min -
4003 MLXSW_SP_KVD_GRANULARITY,
4004 DEVLINK_RESOURCE_UNIT_ENTRY);
4005 devlink_resource_size_params_init(hash_double_size_params,
4007 kvd_size - single_size_min -
4009 MLXSW_SP_KVD_GRANULARITY,
4010 DEVLINK_RESOURCE_UNIT_ENTRY);
4011 devlink_resource_size_params_init(hash_single_size_params,
4013 kvd_size - double_size_min -
4015 MLXSW_SP_KVD_GRANULARITY,
4016 DEVLINK_RESOURCE_UNIT_ENTRY);
4019 static int mlxsw_sp1_resources_kvd_register(struct mlxsw_core *mlxsw_core)
4021 struct devlink *devlink = priv_to_devlink(mlxsw_core);
4022 struct devlink_resource_size_params hash_single_size_params;
4023 struct devlink_resource_size_params hash_double_size_params;
4024 struct devlink_resource_size_params linear_size_params;
4025 struct devlink_resource_size_params kvd_size_params;
4026 u32 kvd_size, single_size, double_size, linear_size;
4027 const struct mlxsw_config_profile *profile;
4030 profile = &mlxsw_sp1_config_profile;
4031 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
4034 mlxsw_sp_resource_size_params_prepare(mlxsw_core, &kvd_size_params,
4035 &linear_size_params,
4036 &hash_double_size_params,
4037 &hash_single_size_params);
4039 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
4040 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
4041 kvd_size, MLXSW_SP_RESOURCE_KVD,
4042 DEVLINK_RESOURCE_ID_PARENT_TOP,
4047 linear_size = profile->kvd_linear_size;
4048 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR,
4050 MLXSW_SP_RESOURCE_KVD_LINEAR,
4051 MLXSW_SP_RESOURCE_KVD,
4052 &linear_size_params);
4056 err = mlxsw_sp1_kvdl_resources_register(mlxsw_core);
4060 double_size = kvd_size - linear_size;
4061 double_size *= profile->kvd_hash_double_parts;
4062 double_size /= profile->kvd_hash_double_parts +
4063 profile->kvd_hash_single_parts;
4064 double_size = rounddown(double_size, MLXSW_SP_KVD_GRANULARITY);
4065 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE,
4067 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
4068 MLXSW_SP_RESOURCE_KVD,
4069 &hash_double_size_params);
4073 single_size = kvd_size - double_size - linear_size;
4074 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE,
4076 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
4077 MLXSW_SP_RESOURCE_KVD,
4078 &hash_single_size_params);
4085 static int mlxsw_sp1_resources_register(struct mlxsw_core *mlxsw_core)
4087 return mlxsw_sp1_resources_kvd_register(mlxsw_core);
4090 static int mlxsw_sp2_resources_register(struct mlxsw_core *mlxsw_core)
4095 static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core,
4096 const struct mlxsw_config_profile *profile,
4097 u64 *p_single_size, u64 *p_double_size,
4100 struct devlink *devlink = priv_to_devlink(mlxsw_core);
4104 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
4105 !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE))
4108 /* The hash part is what left of the kvd without the
4109 * linear part. It is split to the single size and
4110 * double size by the parts ratio from the profile.
4111 * Both sizes must be a multiplications of the
4112 * granularity from the profile. In case the user
4113 * provided the sizes they are obtained via devlink.
4115 err = devlink_resource_size_get(devlink,
4116 MLXSW_SP_RESOURCE_KVD_LINEAR,
4119 *p_linear_size = profile->kvd_linear_size;
4121 err = devlink_resource_size_get(devlink,
4122 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
4125 double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
4127 double_size *= profile->kvd_hash_double_parts;
4128 double_size /= profile->kvd_hash_double_parts +
4129 profile->kvd_hash_single_parts;
4130 *p_double_size = rounddown(double_size,
4131 MLXSW_SP_KVD_GRANULARITY);
4134 err = devlink_resource_size_get(devlink,
4135 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
4138 *p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
4139 *p_double_size - *p_linear_size;
4141 /* Check results are legal. */
4142 if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
4143 *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
4144 MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size)
4150 static struct mlxsw_driver mlxsw_sp1_driver = {
4151 .kind = mlxsw_sp1_driver_name,
4152 .priv_size = sizeof(struct mlxsw_sp),
4153 .init = mlxsw_sp1_init,
4154 .fini = mlxsw_sp_fini,
4155 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
4156 .port_split = mlxsw_sp_port_split,
4157 .port_unsplit = mlxsw_sp_port_unsplit,
4158 .sb_pool_get = mlxsw_sp_sb_pool_get,
4159 .sb_pool_set = mlxsw_sp_sb_pool_set,
4160 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
4161 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
4162 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
4163 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
4164 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
4165 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
4166 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
4167 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
4168 .txhdr_construct = mlxsw_sp_txhdr_construct,
4169 .resources_register = mlxsw_sp1_resources_register,
4170 .kvd_sizes_get = mlxsw_sp_kvd_sizes_get,
4171 .txhdr_len = MLXSW_TXHDR_LEN,
4172 .profile = &mlxsw_sp1_config_profile,
4173 .res_query_enabled = true,
4176 static struct mlxsw_driver mlxsw_sp2_driver = {
4177 .kind = mlxsw_sp2_driver_name,
4178 .priv_size = sizeof(struct mlxsw_sp),
4179 .init = mlxsw_sp2_init,
4180 .fini = mlxsw_sp_fini,
4181 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
4182 .port_split = mlxsw_sp_port_split,
4183 .port_unsplit = mlxsw_sp_port_unsplit,
4184 .sb_pool_get = mlxsw_sp_sb_pool_get,
4185 .sb_pool_set = mlxsw_sp_sb_pool_set,
4186 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
4187 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
4188 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
4189 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
4190 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
4191 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
4192 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
4193 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
4194 .txhdr_construct = mlxsw_sp_txhdr_construct,
4195 .resources_register = mlxsw_sp2_resources_register,
4196 .txhdr_len = MLXSW_TXHDR_LEN,
4197 .profile = &mlxsw_sp2_config_profile,
4198 .res_query_enabled = true,
4201 bool mlxsw_sp_port_dev_check(const struct net_device *dev)
4203 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
4206 static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
4208 struct mlxsw_sp_port **p_mlxsw_sp_port = data;
4211 if (mlxsw_sp_port_dev_check(lower_dev)) {
4212 *p_mlxsw_sp_port = netdev_priv(lower_dev);
4219 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
4221 struct mlxsw_sp_port *mlxsw_sp_port;
4223 if (mlxsw_sp_port_dev_check(dev))
4224 return netdev_priv(dev);
4226 mlxsw_sp_port = NULL;
4227 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
4229 return mlxsw_sp_port;
4232 struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
4234 struct mlxsw_sp_port *mlxsw_sp_port;
4236 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
4237 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
4240 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
4242 struct mlxsw_sp_port *mlxsw_sp_port;
4244 if (mlxsw_sp_port_dev_check(dev))
4245 return netdev_priv(dev);
4247 mlxsw_sp_port = NULL;
4248 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
4251 return mlxsw_sp_port;
4254 struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
4256 struct mlxsw_sp_port *mlxsw_sp_port;
4259 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
4261 dev_hold(mlxsw_sp_port->dev);
4263 return mlxsw_sp_port;
4266 void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
4268 dev_put(mlxsw_sp_port->dev);
4271 static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
4273 char sldr_pl[MLXSW_REG_SLDR_LEN];
4275 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
4276 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4279 static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
4281 char sldr_pl[MLXSW_REG_SLDR_LEN];
4283 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
4284 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4287 static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4288 u16 lag_id, u8 port_index)
4290 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4291 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4293 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
4294 lag_id, port_index);
4295 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4298 static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4301 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4302 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4304 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
4306 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4309 static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
4312 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4313 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4315 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
4317 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4320 static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
4323 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4324 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4326 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
4328 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4331 static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4332 struct net_device *lag_dev,
4335 struct mlxsw_sp_upper *lag;
4336 int free_lag_id = -1;
4340 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
4341 for (i = 0; i < max_lag; i++) {
4342 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
4343 if (lag->ref_count) {
4344 if (lag->dev == lag_dev) {
4348 } else if (free_lag_id < 0) {
4352 if (free_lag_id < 0)
4354 *p_lag_id = free_lag_id;
4359 mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
4360 struct net_device *lag_dev,
4361 struct netdev_lag_upper_info *lag_upper_info,
4362 struct netlink_ext_ack *extack)
4366 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) {
4367 NL_SET_ERR_MSG_MOD(extack, "Exceeded number of supported LAG devices");
4370 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
4371 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type");
4377 static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4378 u16 lag_id, u8 *p_port_index)
4380 u64 max_lag_members;
4383 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
4385 for (i = 0; i < max_lag_members; i++) {
4386 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
4394 static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
4395 struct net_device *lag_dev)
4397 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4398 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
4399 struct mlxsw_sp_upper *lag;
4404 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
4407 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4408 if (!lag->ref_count) {
4409 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
4415 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
4418 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
4420 goto err_col_port_add;
4421 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
4423 goto err_col_port_enable;
4425 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
4426 mlxsw_sp_port->local_port);
4427 mlxsw_sp_port->lag_id = lag_id;
4428 mlxsw_sp_port->lagged = 1;
4431 /* Port is no longer usable as a router interface */
4432 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, 1);
4433 if (mlxsw_sp_port_vlan->fid)
4434 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
4438 err_col_port_enable:
4439 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
4441 if (!lag->ref_count)
4442 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
4446 static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
4447 struct net_device *lag_dev)
4449 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4450 u16 lag_id = mlxsw_sp_port->lag_id;
4451 struct mlxsw_sp_upper *lag;
4453 if (!mlxsw_sp_port->lagged)
4455 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4456 WARN_ON(lag->ref_count == 0);
4458 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
4459 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
4461 /* Any VLANs configured on the port are no longer valid */
4462 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
4464 if (lag->ref_count == 1)
4465 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
4467 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4468 mlxsw_sp_port->local_port);
4469 mlxsw_sp_port->lagged = 0;
4472 mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
4473 /* Make sure untagged frames are allowed to ingress */
4474 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
4477 static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4480 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4481 char sldr_pl[MLXSW_REG_SLDR_LEN];
4483 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
4484 mlxsw_sp_port->local_port);
4485 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4488 static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4491 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4492 char sldr_pl[MLXSW_REG_SLDR_LEN];
4494 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
4495 mlxsw_sp_port->local_port);
4496 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4499 static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
4500 bool lag_tx_enabled)
4503 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
4504 mlxsw_sp_port->lag_id);
4506 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
4507 mlxsw_sp_port->lag_id);
4510 static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
4511 struct netdev_lag_lower_state_info *info)
4513 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
4516 static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
4519 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4520 enum mlxsw_reg_spms_state spms_state;
4525 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
4526 MLXSW_REG_SPMS_STATE_DISCARDING;
4528 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
4531 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
4533 for (vid = 0; vid < VLAN_N_VID; vid++)
4534 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
4536 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
4541 static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
4546 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
4549 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
4551 goto err_port_stp_set;
4552 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4555 goto err_port_vlan_set;
4557 for (; vid <= VLAN_N_VID - 1; vid++) {
4558 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4561 goto err_vid_learning_set;
4566 err_vid_learning_set:
4567 for (vid--; vid >= 1; vid--)
4568 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true);
4570 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
4572 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
4576 static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4580 for (vid = VLAN_N_VID - 1; vid >= 1; vid--)
4581 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4584 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4586 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
4587 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
4590 static bool mlxsw_sp_bridge_has_multiple_vxlans(struct net_device *br_dev)
4592 unsigned int num_vxlans = 0;
4593 struct net_device *dev;
4594 struct list_head *iter;
4596 netdev_for_each_lower_dev(br_dev, dev, iter) {
4597 if (netif_is_vxlan(dev))
4601 return num_vxlans > 1;
4604 static bool mlxsw_sp_bridge_vxlan_is_valid(struct net_device *br_dev,
4605 struct netlink_ext_ack *extack)
4607 if (br_multicast_enabled(br_dev)) {
4608 NL_SET_ERR_MSG_MOD(extack, "Multicast can not be enabled on a bridge with a VxLAN device");
4612 if (br_vlan_enabled(br_dev)) {
4613 NL_SET_ERR_MSG_MOD(extack, "VLAN filtering can not be enabled on a bridge with a VxLAN device");
4617 if (mlxsw_sp_bridge_has_multiple_vxlans(br_dev)) {
4618 NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices are not supported in a VLAN-unaware bridge");
4625 static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
4626 struct net_device *dev,
4627 unsigned long event, void *ptr)
4629 struct netdev_notifier_changeupper_info *info;
4630 struct mlxsw_sp_port *mlxsw_sp_port;
4631 struct netlink_ext_ack *extack;
4632 struct net_device *upper_dev;
4633 struct mlxsw_sp *mlxsw_sp;
4636 mlxsw_sp_port = netdev_priv(dev);
4637 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4639 extack = netdev_notifier_info_to_extack(&info->info);
4642 case NETDEV_PRECHANGEUPPER:
4643 upper_dev = info->upper_dev;
4644 if (!is_vlan_dev(upper_dev) &&
4645 !netif_is_lag_master(upper_dev) &&
4646 !netif_is_bridge_master(upper_dev) &&
4647 !netif_is_ovs_master(upper_dev) &&
4648 !netif_is_macvlan(upper_dev)) {
4649 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
4654 if (netif_is_bridge_master(upper_dev) &&
4655 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) &&
4656 mlxsw_sp_bridge_has_vxlan(upper_dev) &&
4657 !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
4659 if (netdev_has_any_upper_dev(upper_dev) &&
4660 (!netif_is_bridge_master(upper_dev) ||
4661 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4663 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
4666 if (netif_is_lag_master(upper_dev) &&
4667 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
4668 info->upper_info, extack))
4670 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) {
4671 NL_SET_ERR_MSG_MOD(extack, "Master device is a LAG master and this device has a VLAN");
4674 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
4675 !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) {
4676 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on a LAG port");
4679 if (netif_is_macvlan(upper_dev) &&
4680 !mlxsw_sp_rif_find_by_dev(mlxsw_sp, lower_dev)) {
4681 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
4684 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) {
4685 NL_SET_ERR_MSG_MOD(extack, "Master device is an OVS master and this device has a VLAN");
4688 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) {
4689 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on an OVS port");
4692 if (is_vlan_dev(upper_dev) &&
4693 vlan_dev_vlan_id(upper_dev) == 1) {
4694 NL_SET_ERR_MSG_MOD(extack, "Creating a VLAN device with VID 1 is unsupported: VLAN 1 carries untagged traffic");
4698 case NETDEV_CHANGEUPPER:
4699 upper_dev = info->upper_dev;
4700 if (netif_is_bridge_master(upper_dev)) {
4702 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4707 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4710 } else if (netif_is_lag_master(upper_dev)) {
4712 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
4715 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
4717 } else if (netif_is_ovs_master(upper_dev)) {
4719 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
4721 mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
4722 } else if (netif_is_macvlan(upper_dev)) {
4724 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
4732 static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
4733 unsigned long event, void *ptr)
4735 struct netdev_notifier_changelowerstate_info *info;
4736 struct mlxsw_sp_port *mlxsw_sp_port;
4739 mlxsw_sp_port = netdev_priv(dev);
4743 case NETDEV_CHANGELOWERSTATE:
4744 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
4745 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
4746 info->lower_state_info);
4748 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
4756 static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
4757 struct net_device *port_dev,
4758 unsigned long event, void *ptr)
4761 case NETDEV_PRECHANGEUPPER:
4762 case NETDEV_CHANGEUPPER:
4763 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
4765 case NETDEV_CHANGELOWERSTATE:
4766 return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
4773 static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
4774 unsigned long event, void *ptr)
4776 struct net_device *dev;
4777 struct list_head *iter;
4780 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4781 if (mlxsw_sp_port_dev_check(dev)) {
4782 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
4792 static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
4793 struct net_device *dev,
4794 unsigned long event, void *ptr,
4797 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
4798 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4799 struct netdev_notifier_changeupper_info *info = ptr;
4800 struct netlink_ext_ack *extack;
4801 struct net_device *upper_dev;
4804 extack = netdev_notifier_info_to_extack(&info->info);
4807 case NETDEV_PRECHANGEUPPER:
4808 upper_dev = info->upper_dev;
4809 if (!netif_is_bridge_master(upper_dev) &&
4810 !netif_is_macvlan(upper_dev)) {
4811 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
4816 if (netif_is_bridge_master(upper_dev) &&
4817 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) &&
4818 mlxsw_sp_bridge_has_vxlan(upper_dev) &&
4819 !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
4821 if (netdev_has_any_upper_dev(upper_dev) &&
4822 (!netif_is_bridge_master(upper_dev) ||
4823 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4825 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
4828 if (netif_is_macvlan(upper_dev) &&
4829 !mlxsw_sp_rif_find_by_dev(mlxsw_sp, vlan_dev)) {
4830 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
4834 case NETDEV_CHANGEUPPER:
4835 upper_dev = info->upper_dev;
4836 if (netif_is_bridge_master(upper_dev)) {
4838 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4843 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4846 } else if (netif_is_macvlan(upper_dev)) {
4848 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
4859 static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
4860 struct net_device *lag_dev,
4861 unsigned long event,
4864 struct net_device *dev;
4865 struct list_head *iter;
4868 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4869 if (mlxsw_sp_port_dev_check(dev)) {
4870 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
4881 static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
4882 unsigned long event, void *ptr)
4884 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
4885 u16 vid = vlan_dev_vlan_id(vlan_dev);
4887 if (mlxsw_sp_port_dev_check(real_dev))
4888 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
4890 else if (netif_is_lag_master(real_dev))
4891 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
4898 static int mlxsw_sp_netdevice_bridge_event(struct net_device *br_dev,
4899 unsigned long event, void *ptr)
4901 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(br_dev);
4902 struct netdev_notifier_changeupper_info *info = ptr;
4903 struct netlink_ext_ack *extack;
4904 struct net_device *upper_dev;
4909 extack = netdev_notifier_info_to_extack(&info->info);
4912 case NETDEV_PRECHANGEUPPER:
4913 upper_dev = info->upper_dev;
4914 if (!is_vlan_dev(upper_dev) && !netif_is_macvlan(upper_dev)) {
4915 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
4920 if (netif_is_macvlan(upper_dev) &&
4921 !mlxsw_sp_rif_find_by_dev(mlxsw_sp, br_dev)) {
4922 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
4926 case NETDEV_CHANGEUPPER:
4927 upper_dev = info->upper_dev;
4930 if (is_vlan_dev(upper_dev))
4931 mlxsw_sp_rif_destroy_by_dev(mlxsw_sp, upper_dev);
4932 if (netif_is_macvlan(upper_dev))
4933 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
4940 static int mlxsw_sp_netdevice_macvlan_event(struct net_device *macvlan_dev,
4941 unsigned long event, void *ptr)
4943 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(macvlan_dev);
4944 struct netdev_notifier_changeupper_info *info = ptr;
4945 struct netlink_ext_ack *extack;
4947 if (!mlxsw_sp || event != NETDEV_PRECHANGEUPPER)
4950 extack = netdev_notifier_info_to_extack(&info->info);
4952 /* VRF enslavement is handled in mlxsw_sp_netdevice_vrf_event() */
4953 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
4958 static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
4960 struct netdev_notifier_changeupper_info *info = ptr;
4962 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
4964 return netif_is_l3_master(info->upper_dev);
4967 static int mlxsw_sp_netdevice_vxlan_event(struct mlxsw_sp *mlxsw_sp,
4968 struct net_device *dev,
4969 unsigned long event, void *ptr)
4971 struct netdev_notifier_changeupper_info *cu_info;
4972 struct netdev_notifier_info *info = ptr;
4973 struct netlink_ext_ack *extack;
4974 struct net_device *upper_dev;
4976 extack = netdev_notifier_info_to_extack(info);
4979 case NETDEV_CHANGEUPPER:
4980 cu_info = container_of(info,
4981 struct netdev_notifier_changeupper_info,
4983 upper_dev = cu_info->upper_dev;
4984 if (!netif_is_bridge_master(upper_dev))
4986 if (!mlxsw_sp_lower_get(upper_dev))
4988 if (!mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
4990 if (cu_info->linking) {
4991 if (!netif_running(dev))
4993 return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev,
4996 mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, upper_dev, dev);
5000 upper_dev = netdev_master_upper_dev_get(dev);
5003 if (!netif_is_bridge_master(upper_dev))
5005 if (!mlxsw_sp_lower_get(upper_dev))
5007 return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev, dev,
5010 upper_dev = netdev_master_upper_dev_get(dev);
5013 if (!netif_is_bridge_master(upper_dev))
5015 if (!mlxsw_sp_lower_get(upper_dev))
5017 mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, upper_dev, dev);
5024 static int mlxsw_sp_netdevice_event(struct notifier_block *nb,
5025 unsigned long event, void *ptr)
5027 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
5028 struct mlxsw_sp_span_entry *span_entry;
5029 struct mlxsw_sp *mlxsw_sp;
5032 mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb);
5033 if (event == NETDEV_UNREGISTER) {
5034 span_entry = mlxsw_sp_span_entry_find_by_port(mlxsw_sp, dev);
5036 mlxsw_sp_span_entry_invalidate(mlxsw_sp, span_entry);
5038 mlxsw_sp_span_respin(mlxsw_sp);
5040 if (netif_is_vxlan(dev))
5041 err = mlxsw_sp_netdevice_vxlan_event(mlxsw_sp, dev, event, ptr);
5042 if (mlxsw_sp_netdev_is_ipip_ol(mlxsw_sp, dev))
5043 err = mlxsw_sp_netdevice_ipip_ol_event(mlxsw_sp, dev,
5045 else if (mlxsw_sp_netdev_is_ipip_ul(mlxsw_sp, dev))
5046 err = mlxsw_sp_netdevice_ipip_ul_event(mlxsw_sp, dev,
5048 else if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
5049 err = mlxsw_sp_netdevice_router_port_event(dev);
5050 else if (mlxsw_sp_is_vrf_event(event, ptr))
5051 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
5052 else if (mlxsw_sp_port_dev_check(dev))
5053 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr);
5054 else if (netif_is_lag_master(dev))
5055 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
5056 else if (is_vlan_dev(dev))
5057 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
5058 else if (netif_is_bridge_master(dev))
5059 err = mlxsw_sp_netdevice_bridge_event(dev, event, ptr);
5060 else if (netif_is_macvlan(dev))
5061 err = mlxsw_sp_netdevice_macvlan_event(dev, event, ptr);
5063 return notifier_from_errno(err);
5066 static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = {
5067 .notifier_call = mlxsw_sp_inetaddr_valid_event,
5070 static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = {
5071 .notifier_call = mlxsw_sp_inetaddr_event,
5074 static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = {
5075 .notifier_call = mlxsw_sp_inet6addr_valid_event,
5078 static struct notifier_block mlxsw_sp_inet6addr_nb __read_mostly = {
5079 .notifier_call = mlxsw_sp_inet6addr_event,
5082 static const struct pci_device_id mlxsw_sp1_pci_id_table[] = {
5083 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
5087 static struct pci_driver mlxsw_sp1_pci_driver = {
5088 .name = mlxsw_sp1_driver_name,
5089 .id_table = mlxsw_sp1_pci_id_table,
5092 static const struct pci_device_id mlxsw_sp2_pci_id_table[] = {
5093 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM2), 0},
5097 static struct pci_driver mlxsw_sp2_pci_driver = {
5098 .name = mlxsw_sp2_driver_name,
5099 .id_table = mlxsw_sp2_pci_id_table,
5102 static int __init mlxsw_sp_module_init(void)
5106 register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
5107 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
5108 register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
5109 register_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
5111 err = mlxsw_core_driver_register(&mlxsw_sp1_driver);
5113 goto err_sp1_core_driver_register;
5115 err = mlxsw_core_driver_register(&mlxsw_sp2_driver);
5117 goto err_sp2_core_driver_register;
5119 err = mlxsw_pci_driver_register(&mlxsw_sp1_pci_driver);
5121 goto err_sp1_pci_driver_register;
5123 err = mlxsw_pci_driver_register(&mlxsw_sp2_pci_driver);
5125 goto err_sp2_pci_driver_register;
5129 err_sp2_pci_driver_register:
5130 mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver);
5131 err_sp1_pci_driver_register:
5132 mlxsw_core_driver_unregister(&mlxsw_sp2_driver);
5133 err_sp2_core_driver_register:
5134 mlxsw_core_driver_unregister(&mlxsw_sp1_driver);
5135 err_sp1_core_driver_register:
5136 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
5137 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
5138 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
5139 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
5143 static void __exit mlxsw_sp_module_exit(void)
5145 mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver);
5146 mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver);
5147 mlxsw_core_driver_unregister(&mlxsw_sp2_driver);
5148 mlxsw_core_driver_unregister(&mlxsw_sp1_driver);
5149 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
5150 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
5151 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
5152 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
5155 module_init(mlxsw_sp_module_init);
5156 module_exit(mlxsw_sp_module_exit);
5158 MODULE_LICENSE("Dual BSD/GPL");
5159 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
5160 MODULE_DESCRIPTION("Mellanox Spectrum driver");
5161 MODULE_DEVICE_TABLE(pci, mlxsw_sp1_pci_id_table);
5162 MODULE_DEVICE_TABLE(pci, mlxsw_sp2_pci_id_table);
5163 MODULE_FIRMWARE(MLXSW_SP1_FW_FILENAME);