drivers/net/ethernet/mellanox/mlxsw/spectrum.c

   1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
   2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
   3
   4 #include <linux/kernel.h>
   5 #include <linux/module.h>
   6 #include <linux/types.h>
   7 #include <linux/pci.h>
   8 #include <linux/netdevice.h>
   9 #include <linux/etherdevice.h>
  10 #include <linux/ethtool.h>
  11 #include <linux/slab.h>
  12 #include <linux/device.h>
  13 #include <linux/skbuff.h>
  14 #include <linux/if_vlan.h>
  15 #include <linux/if_bridge.h>
  16 #include <linux/workqueue.h>
  17 #include <linux/jiffies.h>
  18 #include <linux/bitops.h>
  19 #include <linux/list.h>
  20 #include <linux/notifier.h>
  21 #include <linux/dcbnl.h>
  22 #include <linux/inetdevice.h>
  23 #include <linux/netlink.h>
  24 #include <linux/random.h>
  25 #include <net/switchdev.h>
  26 #include <net/pkt_cls.h>
  27 #include <net/tc_act/tc_mirred.h>
  28 #include <net/netevent.h>
  29 #include <net/tc_act/tc_sample.h>
  30 #include <net/addrconf.h>
  31
  32 #include "spectrum.h"
  33 #include "pci.h"
  34 #include "core.h"
  35 #include "reg.h"
  36 #include "port.h"
  37 #include "trap.h"
  38 #include "txheader.h"
  39 #include "spectrum_cnt.h"
  40 #include "spectrum_dpipe.h"
  41 #include "spectrum_acl_flex_actions.h"
  42 #include "spectrum_span.h"
  43 #include "../mlxfw/mlxfw.h"
  44
  45 #define MLXSW_SP_FWREV_MINOR_TO_BRANCH(minor) ((minor) / 100)
  46
  47 #define MLXSW_SP1_FWREV_MAJOR 13
  48 #define MLXSW_SP1_FWREV_MINOR 1703
  49 #define MLXSW_SP1_FWREV_SUBMINOR 4
  50 #define MLXSW_SP1_FWREV_CAN_RESET_MINOR 1702
  51
  52 static const struct mlxsw_fw_rev mlxsw_sp1_fw_rev = {
  53         .major = MLXSW_SP1_FWREV_MAJOR,
  54         .minor = MLXSW_SP1_FWREV_MINOR,
  55         .subminor = MLXSW_SP1_FWREV_SUBMINOR,
  56         .can_reset_minor = MLXSW_SP1_FWREV_CAN_RESET_MINOR,
  57 };
  58
  59 #define MLXSW_SP1_FW_FILENAME \
  60         "mellanox/mlxsw_spectrum-" __stringify(MLXSW_SP1_FWREV_MAJOR) \
  61         "." __stringify(MLXSW_SP1_FWREV_MINOR) \
  62         "." __stringify(MLXSW_SP1_FWREV_SUBMINOR) ".mfa2"
  63
  64 static const char mlxsw_sp1_driver_name[] = "mlxsw_spectrum";
  65 static const char mlxsw_sp2_driver_name[] = "mlxsw_spectrum2";
  66 static const char mlxsw_sp_driver_version[] = "1.0";
  67
  68 /* tx_hdr_version
  69  * Tx header version.
  70  * Must be set to 1.
  71  */
  72 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
  73
  74 /* tx_hdr_ctl
  75  * Packet control type.
  76  * 0 - Ethernet control (e.g. EMADs, LACP)
  77  * 1 - Ethernet data
  78  */
  79 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
  80
  81 /* tx_hdr_proto
  82  * Packet protocol type. Must be set to 1 (Ethernet).
  83  */
  84 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
  85
  86 /* tx_hdr_rx_is_router
  87  * Packet is sent from the router. Valid for data packets only.
  88  */
  89 MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
  90
  91 /* tx_hdr_fid_valid
  92  * Indicates if the 'fid' field is valid and should be used for
  93  * forwarding lookup. Valid for data packets only.
  94  */
  95 MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
  96
  97 /* tx_hdr_swid
  98  * Switch partition ID. Must be set to 0.
  99  */
 100 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
 101
 102 /* tx_hdr_control_tclass
 103  * Indicates if the packet should use the control TClass and not one
 104  * of the data TClasses.
 105  */
 106 MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
 107
 108 /* tx_hdr_etclass
 109  * Egress TClass to be used on the egress device on the egress port.
 110  */
 111 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
 112
 113 /* tx_hdr_port_mid
 114  * Destination local port for unicast packets.
 115  * Destination multicast ID for multicast packets.
 116  *
 117  * Control packets are directed to a specific egress port, while data
 118  * packets are transmitted through the CPU port (0) into the switch partition,
 119  * where forwarding rules are applied.
 120  */
 121 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
 122
 123 /* tx_hdr_fid
 124  * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
 125  * set, otherwise calculated based on the packet's VID using VID to FID mapping.
 126  * Valid for data packets only.
 127  */
 128 MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
 129
 130 /* tx_hdr_type
 131  * 0 - Data packets
 132  * 6 - Control packets
 133  */
 134 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
 135
 136 struct mlxsw_sp_mlxfw_dev {
 137         struct mlxfw_dev mlxfw_dev;
 138         struct mlxsw_sp *mlxsw_sp;
 139 };
 140
 141 static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev,
 142                                     u16 component_index, u32 *p_max_size,
 143                                     u8 *p_align_bits, u16 *p_max_write_size)
 144 {
 145         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 146                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 147         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 148         char mcqi_pl[MLXSW_REG_MCQI_LEN];
 149         int err;
 150
 151         mlxsw_reg_mcqi_pack(mcqi_pl, component_index);
 152         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl);
 153         if (err)
 154                 return err;
 155         mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits,
 156                               p_max_write_size);
 157
 158         *p_align_bits = max_t(u8, *p_align_bits, 2);
 159         *p_max_write_size = min_t(u16, *p_max_write_size,
 160                                   MLXSW_REG_MCDA_MAX_DATA_LEN);
 161         return 0;
 162 }
 163
 164 static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
 165 {
 166         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 167                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 168         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 169         char mcc_pl[MLXSW_REG_MCC_LEN];
 170         u8 control_state;
 171         int err;
 172
 173         mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0);
 174         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
 175         if (err)
 176                 return err;
 177
 178         mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state);
 179         if (control_state != MLXFW_FSM_STATE_IDLE)
 180                 return -EBUSY;
 181
 182         mlxsw_reg_mcc_pack(mcc_pl,
 183                            MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
 184                            0, *fwhandle, 0);
 185         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
 186 }
 187
 188 static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev,
 189                                          u32 fwhandle, u16 component_index,
 190                                          u32 component_size)
 191 {
 192         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 193                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 194         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 195         char mcc_pl[MLXSW_REG_MCC_LEN];
 196
 197         mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
 198                            component_index, fwhandle, component_size);
 199         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
 200 }
 201
 202 static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev,
 203                                        u32 fwhandle, u8 *data, u16 size,
 204                                        u32 offset)
 205 {
 206         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 207                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 208         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 209         char mcda_pl[MLXSW_REG_MCDA_LEN];
 210
 211         mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data);
 212         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl);
 213 }
 214
 215 static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev,
 216                                          u32 fwhandle, u16 component_index)
 217 {
 218         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 219                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 220         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 221         char mcc_pl[MLXSW_REG_MCC_LEN];
 222
 223         mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
 224                            component_index, fwhandle, 0);
 225         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
 226 }
 227
 228 static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
 229 {
 230         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 231                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 232         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 233         char mcc_pl[MLXSW_REG_MCC_LEN];
 234
 235         mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0,
 236                            fwhandle, 0);
 237         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
 238 }
 239
 240 static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
 241                                     enum mlxfw_fsm_state *fsm_state,
 242                                     enum mlxfw_fsm_state_err *fsm_state_err)
 243 {
 244         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 245                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 246         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 247         char mcc_pl[MLXSW_REG_MCC_LEN];
 248         u8 control_state;
 249         u8 error_code;
 250         int err;
 251
 252         mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0);
 253         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
 254         if (err)
 255                 return err;
 256
 257         mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state);
 258         *fsm_state = control_state;
 259         *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
 260                                MLXFW_FSM_STATE_ERR_MAX);
 261         return 0;
 262 }
 263
 264 static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
 265 {
 266         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 267                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 268         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 269         char mcc_pl[MLXSW_REG_MCC_LEN];
 270
 271         mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0,
 272                            fwhandle, 0);
 273         mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
 274 }
 275
 276 static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
 277 {
 278         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 279                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 280         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 281         char mcc_pl[MLXSW_REG_MCC_LEN];
 282
 283         mlxsw_reg_mcc_pack(mcc_pl,
 284                            MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
 285                            fwhandle, 0);
 286         mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
 287 }
 288
 289 static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = {
 290         .component_query        = mlxsw_sp_component_query,
 291         .fsm_lock               = mlxsw_sp_fsm_lock,
 292         .fsm_component_update   = mlxsw_sp_fsm_component_update,
 293         .fsm_block_download     = mlxsw_sp_fsm_block_download,
 294         .fsm_component_verify   = mlxsw_sp_fsm_component_verify,
 295         .fsm_activate           = mlxsw_sp_fsm_activate,
 296         .fsm_query_state        = mlxsw_sp_fsm_query_state,
 297         .fsm_cancel             = mlxsw_sp_fsm_cancel,
 298         .fsm_release            = mlxsw_sp_fsm_release
 299 };
 300
 301 static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp,
 302                                    const struct firmware *firmware)
 303 {
 304         struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = {
 305                 .mlxfw_dev = {
 306                         .ops = &mlxsw_sp_mlxfw_dev_ops,
 307                         .psid = mlxsw_sp->bus_info->psid,
 308                         .psid_size = strlen(mlxsw_sp->bus_info->psid),
 309                 },
 310                 .mlxsw_sp = mlxsw_sp
 311         };
 312
 313         return mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev, firmware);
 314 }
 315
 316 static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp)
 317 {
 318         const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev;
 319         const struct mlxsw_fw_rev *req_rev = mlxsw_sp->req_rev;
 320         const char *fw_filename = mlxsw_sp->fw_filename;
 321         const struct firmware *firmware;
 322         int err;
 323
 324         /* Don't check if driver does not require it */
 325         if (!req_rev || !fw_filename)
 326                 return 0;
 327
 328         /* Validate driver & FW are compatible */
 329         if (rev->major != req_rev->major) {
 330                 WARN(1, "Mismatch in major FW version [%d:%d] is never expected; Please contact support\n",
 331                      rev->major, req_rev->major);
 332                 return -EINVAL;
 333         }
 334         if (MLXSW_SP_FWREV_MINOR_TO_BRANCH(rev->minor) ==
 335             MLXSW_SP_FWREV_MINOR_TO_BRANCH(req_rev->minor) &&
 336             (rev->minor > req_rev->minor ||
 337              (rev->minor == req_rev->minor &&
 338               rev->subminor >= req_rev->subminor)))
 339                 return 0;
 340
 341         dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d is incompatible with the driver\n",
 342                  rev->major, rev->minor, rev->subminor);
 343         dev_info(mlxsw_sp->bus_info->dev, "Flashing firmware using file %s\n",
 344                  fw_filename);
 345
 346         err = request_firmware_direct(&firmware, fw_filename,
 347                                       mlxsw_sp->bus_info->dev);
 348         if (err) {
 349                 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n",
 350                         fw_filename);
 351                 return err;
 352         }
 353
 354         err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
 355         release_firmware(firmware);
 356         if (err)
 357                 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n");
 358
 359         /* On FW flash success, tell the caller FW reset is needed
 360          * if current FW supports it.
 361          */
 362         if (rev->minor >= req_rev->can_reset_minor)
 363                 return err ? err : -EAGAIN;
 364         else
 365                 return 0;
 366 }
 367
 368 int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
 369                               unsigned int counter_index, u64 *packets,
 370                               u64 *bytes)
 371 {
 372         char mgpc_pl[MLXSW_REG_MGPC_LEN];
 373         int err;
 374
 375         mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
 376                             MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
 377         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
 378         if (err)
 379                 return err;
 380         if (packets)
 381                 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
 382         if (bytes)
 383                 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
 384         return 0;
 385 }
 386
 387 static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
 388                                        unsigned int counter_index)
 389 {
 390         char mgpc_pl[MLXSW_REG_MGPC_LEN];
 391
 392         mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
 393                             MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
 394         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
 395 }
 396
 397 int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
 398                                 unsigned int *p_counter_index)
 399 {
 400         int err;
 401
 402         err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
 403                                      p_counter_index);
 404         if (err)
 405                 return err;
 406         err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
 407         if (err)
 408                 goto err_counter_clear;
 409         return 0;
 410
 411 err_counter_clear:
 412         mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
 413                               *p_counter_index);
 414         return err;
 415 }
 416
 417 void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
 418                                 unsigned int counter_index)
 419 {
 420          mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
 421                                counter_index);
 422 }
 423
 424 static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
 425                                      const struct mlxsw_tx_info *tx_info)
 426 {
 427         char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
 428
 429         memset(txhdr, 0, MLXSW_TXHDR_LEN);
 430
 431         mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
 432         mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
 433         mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
 434         mlxsw_tx_hdr_swid_set(txhdr, 0);
 435         mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
 436         mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
 437         mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
 438 }
 439
 440 enum mlxsw_reg_spms_state mlxsw_sp_stp_spms_state(u8 state)
 441 {
 442         switch (state) {
 443         case BR_STATE_FORWARDING:
 444                 return MLXSW_REG_SPMS_STATE_FORWARDING;
 445         case BR_STATE_LEARNING:
 446                 return MLXSW_REG_SPMS_STATE_LEARNING;
 447         case BR_STATE_LISTENING: /* fall-through */
 448         case BR_STATE_DISABLED: /* fall-through */
 449         case BR_STATE_BLOCKING:
 450                 return MLXSW_REG_SPMS_STATE_DISCARDING;
 451         default:
 452                 BUG();
 453         }
 454 }
 455
 456 int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
 457                               u8 state)
 458 {
 459         enum mlxsw_reg_spms_state spms_state = mlxsw_sp_stp_spms_state(state);
 460         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 461         char *spms_pl;
 462         int err;
 463
 464         spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
 465         if (!spms_pl)
 466                 return -ENOMEM;
 467         mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
 468         mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
 469
 470         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
 471         kfree(spms_pl);
 472         return err;
 473 }
 474
 475 static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
 476 {
 477         char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
 478         int err;
 479
 480         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
 481         if (err)
 482                 return err;
 483         mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
 484         return 0;
 485 }
 486
 487 static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
 488                                     bool enable, u32 rate)
 489 {
 490         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 491         char mpsc_pl[MLXSW_REG_MPSC_LEN];
 492
 493         mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
 494         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
 495 }
 496
 497 static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
 498                                           bool is_up)
 499 {
 500         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 501         char paos_pl[MLXSW_REG_PAOS_LEN];
 502
 503         mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
 504                             is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
 505                             MLXSW_PORT_ADMIN_STATUS_DOWN);
 506         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
 507 }
 508
 509 static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
 510                                       unsigned char *addr)
 511 {
 512         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 513         char ppad_pl[MLXSW_REG_PPAD_LEN];
 514
 515         mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
 516         mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
 517         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
 518 }
 519
 520 static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
 521 {
 522         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 523         unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
 524
 525         ether_addr_copy(addr, mlxsw_sp->base_mac);
 526         addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
 527         return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
 528 }
 529
 530 static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
 531 {
 532         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 533         char pmtu_pl[MLXSW_REG_PMTU_LEN];
 534         int max_mtu;
 535         int err;
 536
 537         mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
 538         mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
 539         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
 540         if (err)
 541                 return err;
 542         max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
 543
 544         if (mtu > max_mtu)
 545                 return -EINVAL;
 546
 547         mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
 548         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
 549 }
 550
 551 static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
 552 {
 553         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 554         char pspa_pl[MLXSW_REG_PSPA_LEN];
 555
 556         mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port);
 557         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
 558 }
 559
 560 int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
 561 {
 562         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 563         char svpe_pl[MLXSW_REG_SVPE_LEN];
 564
 565         mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
 566         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
 567 }
 568
 569 int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
 570                                    bool learn_enable)
 571 {
 572         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 573         char *spvmlr_pl;
 574         int err;
 575
 576         spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
 577         if (!spvmlr_pl)
 578                 return -ENOMEM;
 579         mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
 580                               learn_enable);
 581         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
 582         kfree(spvmlr_pl);
 583         return err;
 584 }
 585
 586 static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
 587                                     u16 vid)
 588 {
 589         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 590         char spvid_pl[MLXSW_REG_SPVID_LEN];
 591
 592         mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
 593         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
 594 }
 595
 596 static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
 597                                             bool allow)
 598 {
 599         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 600         char spaft_pl[MLXSW_REG_SPAFT_LEN];
 601
 602         mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
 603         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
 604 }
 605
 606 int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
 607 {
 608         int err;
 609
 610         if (!vid) {
 611                 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
 612                 if (err)
 613                         return err;
 614         } else {
 615                 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
 616                 if (err)
 617                         return err;
 618                 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
 619                 if (err)
 620                         goto err_port_allow_untagged_set;
 621         }
 622
 623         mlxsw_sp_port->pvid = vid;
 624         return 0;
 625
 626 err_port_allow_untagged_set:
 627         __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
 628         return err;
 629 }
 630
 631 static int
 632 mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
 633 {
 634         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 635         char sspr_pl[MLXSW_REG_SSPR_LEN];
 636
 637         mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
 638         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
 639 }
 640
 641 static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
 642                                          u8 local_port, u8 *p_module,
 643                                          u8 *p_width, u8 *p_lane)
 644 {
 645         char pmlp_pl[MLXSW_REG_PMLP_LEN];
 646         int err;
 647
 648         mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
 649         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
 650         if (err)
 651                 return err;
 652         *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
 653         *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
 654         *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
 655         return 0;
 656 }
 657
 658 static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port,
 659                                     u8 module, u8 width, u8 lane)
 660 {
 661         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 662         char pmlp_pl[MLXSW_REG_PMLP_LEN];
 663         int i;
 664
 665         mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
 666         mlxsw_reg_pmlp_width_set(pmlp_pl, width);
 667         for (i = 0; i < width; i++) {
 668                 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
 669                 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i);  /* Rx & Tx */
 670         }
 671
 672         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
 673 }
 674
 675 static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port)
 676 {
 677         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 678         char pmlp_pl[MLXSW_REG_PMLP_LEN];
 679
 680         mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
 681         mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
 682         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
 683 }
 684
 685 static int mlxsw_sp_port_open(struct net_device *dev)
 686 {
 687         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 688         int err;
 689
 690         err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
 691         if (err)
 692                 return err;
 693         netif_start_queue(dev);
 694         return 0;
 695 }
 696
 697 static int mlxsw_sp_port_stop(struct net_device *dev)
 698 {
 699         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 700
 701         netif_stop_queue(dev);
 702         return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
 703 }
 704
 705 static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
 706                                       struct net_device *dev)
 707 {
 708         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 709         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 710         struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
 711         const struct mlxsw_tx_info tx_info = {
 712                 .local_port = mlxsw_sp_port->local_port,
 713                 .is_emad = false,
 714         };
 715         u64 len;
 716         int err;
 717
 718         if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
 719                 return NETDEV_TX_BUSY;
 720
 721         if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
 722                 struct sk_buff *skb_orig = skb;
 723
 724                 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
 725                 if (!skb) {
 726                         this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
 727                         dev_kfree_skb_any(skb_orig);
 728                         return NETDEV_TX_OK;
 729                 }
 730                 dev_consume_skb_any(skb_orig);
 731         }
 732
 733         if (eth_skb_pad(skb)) {
 734                 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
 735                 return NETDEV_TX_OK;
 736         }
 737
 738         mlxsw_sp_txhdr_construct(skb, &tx_info);
 739         /* TX header is consumed by HW on the way so we shouldn't count its
 740          * bytes as being sent.
 741          */
 742         len = skb->len - MLXSW_TXHDR_LEN;
 743
 744         /* Due to a race we might fail here because of a full queue. In that
 745          * unlikely case we simply drop the packet.
 746          */
 747         err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
 748
 749         if (!err) {
 750                 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
 751                 u64_stats_update_begin(&pcpu_stats->syncp);
 752                 pcpu_stats->tx_packets++;
 753                 pcpu_stats->tx_bytes += len;
 754                 u64_stats_update_end(&pcpu_stats->syncp);
 755         } else {
 756                 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
 757                 dev_kfree_skb_any(skb);
 758         }
 759         return NETDEV_TX_OK;
 760 }
 761
 762 static void mlxsw_sp_set_rx_mode(struct net_device *dev)
 763 {
 764 }
 765
 766 static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
 767 {
 768         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 769         struct sockaddr *addr = p;
 770         int err;
 771
 772         if (!is_valid_ether_addr(addr->sa_data))
 773                 return -EADDRNOTAVAIL;
 774
 775         err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
 776         if (err)
 777                 return err;
 778         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
 779         return 0;
 780 }
 781
 782 static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
 783                                          int mtu)
 784 {
 785         return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
 786 }
 787
 788 #define MLXSW_SP_CELL_FACTOR 2  /* 2 * cell_size / (IPG + cell_size + 1) */
 789
 790 static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
 791                                   u16 delay)
 792 {
 793         delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
 794                                                             BITS_PER_BYTE));
 795         return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
 796                                                                    mtu);
 797 }
 798
 799 /* Maximum delay buffer needed in case of PAUSE frames, in bytes.
 800  * Assumes 100m cable and maximum MTU.
 801  */
 802 #define MLXSW_SP_PAUSE_DELAY 58752
 803
 804 static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
 805                                      u16 delay, bool pfc, bool pause)
 806 {
 807         if (pfc)
 808                 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
 809         else if (pause)
 810                 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
 811         else
 812                 return 0;
 813 }
 814
 815 static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
 816                                  bool lossy)
 817 {
 818         if (lossy)
 819                 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
 820         else
 821                 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
 822                                                     thres);
 823 }
 824
 825 int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
 826                                  u8 *prio_tc, bool pause_en,
 827                                  struct ieee_pfc *my_pfc)
 828 {
 829         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 830         u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
 831         u16 delay = !!my_pfc ? my_pfc->delay : 0;
 832         char pbmc_pl[MLXSW_REG_PBMC_LEN];
 833         int i, j, err;
 834
 835         mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
 836         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
 837         if (err)
 838                 return err;
 839
 840         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
 841                 bool configure = false;
 842                 bool pfc = false;
 843                 bool lossy;
 844                 u16 thres;
 845
 846                 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
 847                         if (prio_tc[j] == i) {
 848                                 pfc = pfc_en & BIT(j);
 849                                 configure = true;
 850                                 break;
 851                         }
 852                 }
 853
 854                 if (!configure)
 855                         continue;
 856
 857                 lossy = !(pfc || pause_en);
 858                 thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
 859                 delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc,
 860                                                   pause_en);
 861                 mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy);
 862         }
 863
 864         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
 865 }
 866
 867 static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
 868                                       int mtu, bool pause_en)
 869 {
 870         u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
 871         bool dcb_en = !!mlxsw_sp_port->dcb.ets;
 872         struct ieee_pfc *my_pfc;
 873         u8 *prio_tc;
 874
 875         prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
 876         my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
 877
 878         return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
 879                                             pause_en, my_pfc);
 880 }
 881
 882 static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
 883 {
 884         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 885         bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
 886         int err;
 887
 888         err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
 889         if (err)
 890                 return err;
 891         err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
 892         if (err)
 893                 goto err_span_port_mtu_update;
 894         err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
 895         if (err)
 896                 goto err_port_mtu_set;
 897         dev->mtu = mtu;
 898         return 0;
 899
 900 err_port_mtu_set:
 901         mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
 902 err_span_port_mtu_update:
 903         mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
 904         return err;
 905 }
 906
 907 static int
 908 mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
 909                              struct rtnl_link_stats64 *stats)
 910 {
 911         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 912         struct mlxsw_sp_port_pcpu_stats *p;
 913         u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
 914         u32 tx_dropped = 0;
 915         unsigned int start;
 916         int i;
 917
 918         for_each_possible_cpu(i) {
 919                 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
 920                 do {
 921                         start = u64_stats_fetch_begin_irq(&p->syncp);
 922                         rx_packets      = p->rx_packets;
 923                         rx_bytes        = p->rx_bytes;
 924                         tx_packets      = p->tx_packets;
 925                         tx_bytes        = p->tx_bytes;
 926                 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
 927
 928                 stats->rx_packets       += rx_packets;
 929                 stats->rx_bytes         += rx_bytes;
 930                 stats->tx_packets       += tx_packets;
 931                 stats->tx_bytes         += tx_bytes;
 932                 /* tx_dropped is u32, updated without syncp protection. */
 933                 tx_dropped      += p->tx_dropped;
 934         }
 935         stats->tx_dropped       = tx_dropped;
 936         return 0;
 937 }
 938
 939 static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
 940 {
 941         switch (attr_id) {
 942         case IFLA_OFFLOAD_XSTATS_CPU_HIT:
 943                 return true;
 944         }
 945
 946         return false;
 947 }
 948
 949 static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
 950                                            void *sp)
 951 {
 952         switch (attr_id) {
 953         case IFLA_OFFLOAD_XSTATS_CPU_HIT:
 954                 return mlxsw_sp_port_get_sw_stats64(dev, sp);
 955         }
 956
 957         return -EINVAL;
 958 }
 959
 960 static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
 961                                        int prio, char *ppcnt_pl)
 962 {
 963         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 964         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 965
 966         mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
 967         return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
 968 }
 969
 970 static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
 971                                       struct rtnl_link_stats64 *stats)
 972 {
 973         char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
 974         int err;
 975
 976         err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
 977                                           0, ppcnt_pl);
 978         if (err)
 979                 goto out;
 980
 981         stats->tx_packets =
 982                 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
 983         stats->rx_packets =
 984                 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
 985         stats->tx_bytes =
 986                 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
 987         stats->rx_bytes =
 988                 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
 989         stats->multicast =
 990                 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
 991
 992         stats->rx_crc_errors =
 993                 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
 994         stats->rx_frame_errors =
 995                 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
 996
 997         stats->rx_length_errors = (
 998                 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
 999                 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
1000                 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
1001
1002         stats->rx_errors = (stats->rx_crc_errors +
1003                 stats->rx_frame_errors + stats->rx_length_errors);
1004
1005 out:
1006         return err;
1007 }
1008
1009 static void
1010 mlxsw_sp_port_get_hw_xstats(struct net_device *dev,
1011                             struct mlxsw_sp_port_xstats *xstats)
1012 {
1013         char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1014         int err, i;
1015
1016         err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0,
1017                                           ppcnt_pl);
1018         if (!err)
1019                 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl);
1020
1021         for (i = 0; i < TC_MAX_QUEUE; i++) {
1022                 err = mlxsw_sp_port_get_stats_raw(dev,
1023                                                   MLXSW_REG_PPCNT_TC_CONG_TC,
1024                                                   i, ppcnt_pl);
1025                 if (!err)
1026                         xstats->wred_drop[i] =
1027                                 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl);
1028
1029                 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT,
1030                                                   i, ppcnt_pl);
1031                 if (err)
1032                         continue;
1033
1034                 xstats->backlog[i] =
1035                         mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl);
1036                 xstats->tail_drop[i] =
1037                         mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl);
1038         }
1039
1040         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1041                 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_PRIO_CNT,
1042                                                   i, ppcnt_pl);
1043                 if (err)
1044                         continue;
1045
1046                 xstats->tx_packets[i] = mlxsw_reg_ppcnt_tx_frames_get(ppcnt_pl);
1047                 xstats->tx_bytes[i] = mlxsw_reg_ppcnt_tx_octets_get(ppcnt_pl);
1048         }
1049 }
1050
1051 static void update_stats_cache(struct work_struct *work)
1052 {
1053         struct mlxsw_sp_port *mlxsw_sp_port =
1054                 container_of(work, struct mlxsw_sp_port,
1055                              periodic_hw_stats.update_dw.work);
1056
1057         if (!netif_carrier_ok(mlxsw_sp_port->dev))
1058                 goto out;
1059
1060         mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
1061                                    &mlxsw_sp_port->periodic_hw_stats.stats);
1062         mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev,
1063                                     &mlxsw_sp_port->periodic_hw_stats.xstats);
1064
1065 out:
1066         mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw,
1067                                MLXSW_HW_STATS_UPDATE_TIME);
1068 }
1069
1070 /* Return the stats from a cache that is updated periodically,
1071  * as this function might get called in an atomic context.
1072  */
1073 static void
1074 mlxsw_sp_port_get_stats64(struct net_device *dev,
1075                           struct rtnl_link_stats64 *stats)
1076 {
1077         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1078
1079         memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats));
1080 }
1081
1082 static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
1083                                     u16 vid_begin, u16 vid_end,
1084                                     bool is_member, bool untagged)
1085 {
1086         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1087         char *spvm_pl;
1088         int err;
1089
1090         spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1091         if (!spvm_pl)
1092                 return -ENOMEM;
1093
1094         mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1095                             vid_end, is_member, untagged);
1096         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1097         kfree(spvm_pl);
1098         return err;
1099 }
1100
1101 int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1102                            u16 vid_end, bool is_member, bool untagged)
1103 {
1104         u16 vid, vid_e;
1105         int err;
1106
1107         for (vid = vid_begin; vid <= vid_end;
1108              vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1109                 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1110                             vid_end);
1111
1112                 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1113                                                is_member, untagged);
1114                 if (err)
1115                         return err;
1116         }
1117
1118         return 0;
1119 }
1120
1121 static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port)
1122 {
1123         struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
1124
1125         list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
1126                                  &mlxsw_sp_port->vlans_list, list)
1127                 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
1128 }
1129
1130 static struct mlxsw_sp_port_vlan *
1131 mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1132 {
1133         struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1134         bool untagged = vid == 1;
1135         int err;
1136
1137         err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
1138         if (err)
1139                 return ERR_PTR(err);
1140
1141         mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
1142         if (!mlxsw_sp_port_vlan) {
1143                 err = -ENOMEM;
1144                 goto err_port_vlan_alloc;
1145         }
1146
1147         mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
1148         mlxsw_sp_port_vlan->ref_count = 1;
1149         mlxsw_sp_port_vlan->vid = vid;
1150         list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
1151
1152         return mlxsw_sp_port_vlan;
1153
1154 err_port_vlan_alloc:
1155         mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1156         return ERR_PTR(err);
1157 }
1158
1159 static void
1160 mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1161 {
1162         struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
1163         u16 vid = mlxsw_sp_port_vlan->vid;
1164
1165         list_del(&mlxsw_sp_port_vlan->list);
1166         kfree(mlxsw_sp_port_vlan);
1167         mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1168 }
1169
1170 struct mlxsw_sp_port_vlan *
1171 mlxsw_sp_port_vlan_get(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1172 {
1173         struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1174
1175         mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1176         if (mlxsw_sp_port_vlan) {
1177                 mlxsw_sp_port_vlan->ref_count++;
1178                 return mlxsw_sp_port_vlan;
1179         }
1180
1181         return mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid);
1182 }
1183
1184 void mlxsw_sp_port_vlan_put(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1185 {
1186         struct mlxsw_sp_fid *fid = mlxsw_sp_port_vlan->fid;
1187
1188         if (--mlxsw_sp_port_vlan->ref_count != 0)
1189                 return;
1190
1191         if (mlxsw_sp_port_vlan->bridge_port)
1192                 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
1193         else if (fid)
1194                 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
1195
1196         mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
1197 }
1198
1199 static int mlxsw_sp_port_add_vid(struct net_device *dev,
1200                                  __be16 __always_unused proto, u16 vid)
1201 {
1202         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1203
1204         /* VLAN 0 is added to HW filter when device goes up, but it is
1205          * reserved in our case, so simply return.
1206          */
1207         if (!vid)
1208                 return 0;
1209
1210         return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_get(mlxsw_sp_port, vid));
1211 }
1212
1213 static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1214                                   __be16 __always_unused proto, u16 vid)
1215 {
1216         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1217         struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1218
1219         /* VLAN 0 is removed from HW filter when device goes down, but
1220          * it is reserved in our case, so simply return.
1221          */
1222         if (!vid)
1223                 return 0;
1224
1225         mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1226         if (!mlxsw_sp_port_vlan)
1227                 return 0;
1228         mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
1229
1230         return 0;
1231 }
1232
1233 static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
1234                                             size_t len)
1235 {
1236         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1237
1238         return mlxsw_core_port_get_phys_port_name(mlxsw_sp_port->mlxsw_sp->core,
1239                                                   mlxsw_sp_port->local_port,
1240                                                   name, len);
1241 }
1242
1243 static struct mlxsw_sp_port_mall_tc_entry *
1244 mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1245                                  unsigned long cookie) {
1246         struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1247
1248         list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1249                 if (mall_tc_entry->cookie == cookie)
1250                         return mall_tc_entry;
1251
1252         return NULL;
1253 }
1254
1255 static int
1256 mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1257                                       struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
1258                                       const struct tc_action *a,
1259                                       bool ingress)
1260 {
1261         enum mlxsw_sp_span_type span_type;
1262         struct net_device *to_dev;
1263
1264         to_dev = tcf_mirred_dev(a);
1265         if (!to_dev) {
1266                 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1267                 return -EINVAL;
1268         }
1269
1270         mirror->ingress = ingress;
1271         span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1272         return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_dev, span_type,
1273                                         true, &mirror->span_id);
1274 }
1275
1276 static void
1277 mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1278                                       struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1279 {
1280         enum mlxsw_sp_span_type span_type;
1281
1282         span_type = mirror->ingress ?
1283                         MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1284         mlxsw_sp_span_mirror_del(mlxsw_sp_port, mirror->span_id,
1285                                  span_type, true);
1286 }
1287
1288 static int
1289 mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1290                                       struct tc_cls_matchall_offload *cls,
1291                                       const struct tc_action *a,
1292                                       bool ingress)
1293 {
1294         int err;
1295
1296         if (!mlxsw_sp_port->sample)
1297                 return -EOPNOTSUPP;
1298         if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1299                 netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1300                 return -EEXIST;
1301         }
1302         if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) {
1303                 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1304                 return -EOPNOTSUPP;
1305         }
1306
1307         rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1308                            tcf_sample_psample_group(a));
1309         mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a);
1310         mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a);
1311         mlxsw_sp_port->sample->rate = tcf_sample_rate(a);
1312
1313         err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a));
1314         if (err)
1315                 goto err_port_sample_set;
1316         return 0;
1317
1318 err_port_sample_set:
1319         RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1320         return err;
1321 }
1322
1323 static void
1324 mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1325 {
1326         if (!mlxsw_sp_port->sample)
1327                 return;
1328
1329         mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1330         RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1331 }
1332
1333 static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1334                                           struct tc_cls_matchall_offload *f,
1335                                           bool ingress)
1336 {
1337         struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1338         __be16 protocol = f->common.protocol;
1339         const struct tc_action *a;
1340         LIST_HEAD(actions);
1341         int err;
1342
1343         if (!tcf_exts_has_one_action(f->exts)) {
1344                 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
1345                 return -EOPNOTSUPP;
1346         }
1347
1348         mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1349         if (!mall_tc_entry)
1350                 return -ENOMEM;
1351         mall_tc_entry->cookie = f->cookie;
1352
1353         a = tcf_exts_first_action(f->exts);
1354
1355         if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) {
1356                 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1357
1358                 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1359                 mirror = &mall_tc_entry->mirror;
1360                 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1361                                                             mirror, a, ingress);
1362         } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) {
1363                 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
1364                 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, f,
1365                                                             a, ingress);
1366         } else {
1367                 err = -EOPNOTSUPP;
1368         }
1369
1370         if (err)
1371                 goto err_add_action;
1372
1373         list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
1374         return 0;
1375
1376 err_add_action:
1377         kfree(mall_tc_entry);
1378         return err;
1379 }
1380
1381 static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1382                                            struct tc_cls_matchall_offload *f)
1383 {
1384         struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1385
1386         mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
1387                                                          f->cookie);
1388         if (!mall_tc_entry) {
1389                 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1390                 return;
1391         }
1392         list_del(&mall_tc_entry->list);
1393
1394         switch (mall_tc_entry->type) {
1395         case MLXSW_SP_PORT_MALL_MIRROR:
1396                 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1397                                                       &mall_tc_entry->mirror);
1398                 break;
1399         case MLXSW_SP_PORT_MALL_SAMPLE:
1400                 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1401                 break;
1402         default:
1403                 WARN_ON(1);
1404         }
1405
1406         kfree(mall_tc_entry);
1407 }
1408
1409 static int mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1410                                           struct tc_cls_matchall_offload *f,
1411                                           bool ingress)
1412 {
1413         switch (f->command) {
1414         case TC_CLSMATCHALL_REPLACE:
1415                 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port, f,
1416                                                       ingress);
1417         case TC_CLSMATCHALL_DESTROY:
1418                 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port, f);
1419                 return 0;
1420         default:
1421                 return -EOPNOTSUPP;
1422         }
1423 }
1424
1425 static int
1426 mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_acl_block *acl_block,
1427                              struct tc_cls_flower_offload *f)
1428 {
1429         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_acl_block_mlxsw_sp(acl_block);
1430
1431         switch (f->command) {
1432         case TC_CLSFLOWER_REPLACE:
1433                 return mlxsw_sp_flower_replace(mlxsw_sp, acl_block, f);
1434         case TC_CLSFLOWER_DESTROY:
1435                 mlxsw_sp_flower_destroy(mlxsw_sp, acl_block, f);
1436                 return 0;
1437         case TC_CLSFLOWER_STATS:
1438                 return mlxsw_sp_flower_stats(mlxsw_sp, acl_block, f);
1439         case TC_CLSFLOWER_TMPLT_CREATE:
1440                 return mlxsw_sp_flower_tmplt_create(mlxsw_sp, acl_block, f);
1441         case TC_CLSFLOWER_TMPLT_DESTROY:
1442                 mlxsw_sp_flower_tmplt_destroy(mlxsw_sp, acl_block, f);
1443                 return 0;
1444         default:
1445                 return -EOPNOTSUPP;
1446         }
1447 }
1448
1449 static int mlxsw_sp_setup_tc_block_cb_matchall(enum tc_setup_type type,
1450                                                void *type_data,
1451                                                void *cb_priv, bool ingress)
1452 {
1453         struct mlxsw_sp_port *mlxsw_sp_port = cb_priv;
1454
1455         switch (type) {
1456         case TC_SETUP_CLSMATCHALL:
1457                 if (!tc_cls_can_offload_and_chain0(mlxsw_sp_port->dev,
1458                                                    type_data))
1459                         return -EOPNOTSUPP;
1460
1461                 return mlxsw_sp_setup_tc_cls_matchall(mlxsw_sp_port, type_data,
1462                                                       ingress);
1463         case TC_SETUP_CLSFLOWER:
1464                 return 0;
1465         default:
1466                 return -EOPNOTSUPP;
1467         }
1468 }
1469
1470 static int mlxsw_sp_setup_tc_block_cb_matchall_ig(enum tc_setup_type type,
1471                                                   void *type_data,
1472                                                   void *cb_priv)
1473 {
1474         return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1475                                                    cb_priv, true);
1476 }
1477
1478 static int mlxsw_sp_setup_tc_block_cb_matchall_eg(enum tc_setup_type type,
1479                                                   void *type_data,
1480                                                   void *cb_priv)
1481 {
1482         return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1483                                                    cb_priv, false);
1484 }
1485
1486 static int mlxsw_sp_setup_tc_block_cb_flower(enum tc_setup_type type,
1487                                              void *type_data, void *cb_priv)
1488 {
1489         struct mlxsw_sp_acl_block *acl_block = cb_priv;
1490
1491         switch (type) {
1492         case TC_SETUP_CLSMATCHALL:
1493                 return 0;
1494         case TC_SETUP_CLSFLOWER:
1495                 if (mlxsw_sp_acl_block_disabled(acl_block))
1496                         return -EOPNOTSUPP;
1497
1498                 return mlxsw_sp_setup_tc_cls_flower(acl_block, type_data);
1499         default:
1500                 return -EOPNOTSUPP;
1501         }
1502 }
1503
1504 static int
1505 mlxsw_sp_setup_tc_block_flower_bind(struct mlxsw_sp_port *mlxsw_sp_port,
1506                                     struct tcf_block *block, bool ingress,
1507                                     struct netlink_ext_ack *extack)
1508 {
1509         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1510         struct mlxsw_sp_acl_block *acl_block;
1511         struct tcf_block_cb *block_cb;
1512         int err;
1513
1514         block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower,
1515                                        mlxsw_sp);
1516         if (!block_cb) {
1517                 acl_block = mlxsw_sp_acl_block_create(mlxsw_sp, block->net);
1518                 if (!acl_block)
1519                         return -ENOMEM;
1520                 block_cb = __tcf_block_cb_register(block,
1521                                                    mlxsw_sp_setup_tc_block_cb_flower,
1522                                                    mlxsw_sp, acl_block, extack);
1523                 if (IS_ERR(block_cb)) {
1524                         err = PTR_ERR(block_cb);
1525                         goto err_cb_register;
1526                 }
1527         } else {
1528                 acl_block = tcf_block_cb_priv(block_cb);
1529         }
1530         tcf_block_cb_incref(block_cb);
1531         err = mlxsw_sp_acl_block_bind(mlxsw_sp, acl_block,
1532                                       mlxsw_sp_port, ingress);
1533         if (err)
1534                 goto err_block_bind;
1535
1536         if (ingress)
1537                 mlxsw_sp_port->ing_acl_block = acl_block;
1538         else
1539                 mlxsw_sp_port->eg_acl_block = acl_block;
1540
1541         return 0;
1542
1543 err_block_bind:
1544         if (!tcf_block_cb_decref(block_cb)) {
1545                 __tcf_block_cb_unregister(block, block_cb);
1546 err_cb_register:
1547                 mlxsw_sp_acl_block_destroy(acl_block);
1548         }
1549         return err;
1550 }
1551
1552 static void
1553 mlxsw_sp_setup_tc_block_flower_unbind(struct mlxsw_sp_port *mlxsw_sp_port,
1554                                       struct tcf_block *block, bool ingress)
1555 {
1556         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1557         struct mlxsw_sp_acl_block *acl_block;
1558         struct tcf_block_cb *block_cb;
1559         int err;
1560
1561         block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower,
1562                                        mlxsw_sp);
1563         if (!block_cb)
1564                 return;
1565
1566         if (ingress)
1567                 mlxsw_sp_port->ing_acl_block = NULL;
1568         else
1569                 mlxsw_sp_port->eg_acl_block = NULL;
1570
1571         acl_block = tcf_block_cb_priv(block_cb);
1572         err = mlxsw_sp_acl_block_unbind(mlxsw_sp, acl_block,
1573                                         mlxsw_sp_port, ingress);
1574         if (!err && !tcf_block_cb_decref(block_cb)) {
1575                 __tcf_block_cb_unregister(block, block_cb);
1576                 mlxsw_sp_acl_block_destroy(acl_block);
1577         }
1578 }
1579
1580 static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port,
1581                                    struct tc_block_offload *f)
1582 {
1583         tc_setup_cb_t *cb;
1584         bool ingress;
1585         int err;
1586
1587         if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) {
1588                 cb = mlxsw_sp_setup_tc_block_cb_matchall_ig;
1589                 ingress = true;
1590         } else if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_EGRESS) {
1591                 cb = mlxsw_sp_setup_tc_block_cb_matchall_eg;
1592                 ingress = false;
1593         } else {
1594                 return -EOPNOTSUPP;
1595         }
1596
1597         switch (f->command) {
1598         case TC_BLOCK_BIND:
1599                 err = tcf_block_cb_register(f->block, cb, mlxsw_sp_port,
1600                                             mlxsw_sp_port, f->extack);
1601                 if (err)
1602                         return err;
1603                 err = mlxsw_sp_setup_tc_block_flower_bind(mlxsw_sp_port,
1604                                                           f->block, ingress,
1605                                                           f->extack);
1606                 if (err) {
1607                         tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1608                         return err;
1609                 }
1610                 return 0;
1611         case TC_BLOCK_UNBIND:
1612                 mlxsw_sp_setup_tc_block_flower_unbind(mlxsw_sp_port,
1613                                                       f->block, ingress);
1614                 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1615                 return 0;
1616         default:
1617                 return -EOPNOTSUPP;
1618         }
1619 }
1620
1621 static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type,
1622                              void *type_data)
1623 {
1624         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1625
1626         switch (type) {
1627         case TC_SETUP_BLOCK:
1628                 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data);
1629         case TC_SETUP_QDISC_RED:
1630                 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data);
1631         case TC_SETUP_QDISC_PRIO:
1632                 return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data);
1633         default:
1634                 return -EOPNOTSUPP;
1635         }
1636 }
1637
1638
1639 static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable)
1640 {
1641         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1642
1643         if (!enable) {
1644                 if (mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->ing_acl_block) ||
1645                     mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->eg_acl_block) ||
1646                     !list_empty(&mlxsw_sp_port->mall_tc_list)) {
1647                         netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n");
1648                         return -EINVAL;
1649                 }
1650                 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->ing_acl_block);
1651                 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->eg_acl_block);
1652         } else {
1653                 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->ing_acl_block);
1654                 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->eg_acl_block);
1655         }
1656         return 0;
1657 }
1658
1659 typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable);
1660
1661 static int mlxsw_sp_handle_feature(struct net_device *dev,
1662                                    netdev_features_t wanted_features,
1663                                    netdev_features_t feature,
1664                                    mlxsw_sp_feature_handler feature_handler)
1665 {
1666         netdev_features_t changes = wanted_features ^ dev->features;
1667         bool enable = !!(wanted_features & feature);
1668         int err;
1669
1670         if (!(changes & feature))
1671                 return 0;
1672
1673         err = feature_handler(dev, enable);
1674         if (err) {
1675                 netdev_err(dev, "%s feature %pNF failed, err %d\n",
1676                            enable ? "Enable" : "Disable", &feature, err);
1677                 return err;
1678         }
1679
1680         if (enable)
1681                 dev->features |= feature;
1682         else
1683                 dev->features &= ~feature;
1684
1685         return 0;
1686 }
1687 static int mlxsw_sp_set_features(struct net_device *dev,
1688                                  netdev_features_t features)
1689 {
1690         return mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC,
1691                                        mlxsw_sp_feature_hw_tc);
1692 }
1693
1694 static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1695         .ndo_open               = mlxsw_sp_port_open,
1696         .ndo_stop               = mlxsw_sp_port_stop,
1697         .ndo_start_xmit         = mlxsw_sp_port_xmit,
1698         .ndo_setup_tc           = mlxsw_sp_setup_tc,
1699         .ndo_set_rx_mode        = mlxsw_sp_set_rx_mode,
1700         .ndo_set_mac_address    = mlxsw_sp_port_set_mac_address,
1701         .ndo_change_mtu         = mlxsw_sp_port_change_mtu,
1702         .ndo_get_stats64        = mlxsw_sp_port_get_stats64,
1703         .ndo_has_offload_stats  = mlxsw_sp_port_has_offload_stats,
1704         .ndo_get_offload_stats  = mlxsw_sp_port_get_offload_stats,
1705         .ndo_vlan_rx_add_vid    = mlxsw_sp_port_add_vid,
1706         .ndo_vlan_rx_kill_vid   = mlxsw_sp_port_kill_vid,
1707         .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
1708         .ndo_set_features       = mlxsw_sp_set_features,
1709 };
1710
1711 static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1712                                       struct ethtool_drvinfo *drvinfo)
1713 {
1714         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1715         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1716
1717         strlcpy(drvinfo->driver, mlxsw_sp->bus_info->device_kind,
1718                 sizeof(drvinfo->driver));
1719         strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1720                 sizeof(drvinfo->version));
1721         snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1722                  "%d.%d.%d",
1723                  mlxsw_sp->bus_info->fw_rev.major,
1724                  mlxsw_sp->bus_info->fw_rev.minor,
1725                  mlxsw_sp->bus_info->fw_rev.subminor);
1726         strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1727                 sizeof(drvinfo->bus_info));
1728 }
1729
1730 static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1731                                          struct ethtool_pauseparam *pause)
1732 {
1733         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1734
1735         pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1736         pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1737 }
1738
1739 static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1740                                    struct ethtool_pauseparam *pause)
1741 {
1742         char pfcc_pl[MLXSW_REG_PFCC_LEN];
1743
1744         mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1745         mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1746         mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1747
1748         return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1749                                pfcc_pl);
1750 }
1751
1752 static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1753                                         struct ethtool_pauseparam *pause)
1754 {
1755         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1756         bool pause_en = pause->tx_pause || pause->rx_pause;
1757         int err;
1758
1759         if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1760                 netdev_err(dev, "PFC already enabled on port\n");
1761                 return -EINVAL;
1762         }
1763
1764         if (pause->autoneg) {
1765                 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1766                 return -EINVAL;
1767         }
1768
1769         err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1770         if (err) {
1771                 netdev_err(dev, "Failed to configure port's headroom\n");
1772                 return err;
1773         }
1774
1775         err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1776         if (err) {
1777                 netdev_err(dev, "Failed to set PAUSE parameters\n");
1778                 goto err_port_pause_configure;
1779         }
1780
1781         mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1782         mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1783
1784         return 0;
1785
1786 err_port_pause_configure:
1787         pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1788         mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1789         return err;
1790 }
1791
1792 struct mlxsw_sp_port_hw_stats {
1793         char str[ETH_GSTRING_LEN];
1794         u64 (*getter)(const char *payload);
1795         bool cells_bytes;
1796 };
1797
1798 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
1799         {
1800                 .str = "a_frames_transmitted_ok",
1801                 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1802         },
1803         {
1804                 .str = "a_frames_received_ok",
1805                 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1806         },
1807         {
1808                 .str = "a_frame_check_sequence_errors",
1809                 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1810         },
1811         {
1812                 .str = "a_alignment_errors",
1813                 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1814         },
1815         {
1816                 .str = "a_octets_transmitted_ok",
1817                 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1818         },
1819         {
1820                 .str = "a_octets_received_ok",
1821                 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1822         },
1823         {
1824                 .str = "a_multicast_frames_xmitted_ok",
1825                 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1826         },
1827         {
1828                 .str = "a_broadcast_frames_xmitted_ok",
1829                 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1830         },
1831         {
1832                 .str = "a_multicast_frames_received_ok",
1833                 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1834         },
1835         {
1836                 .str = "a_broadcast_frames_received_ok",
1837                 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1838         },
1839         {
1840                 .str = "a_in_range_length_errors",
1841                 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1842         },
1843         {
1844                 .str = "a_out_of_range_length_field",
1845                 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1846         },
1847         {
1848                 .str = "a_frame_too_long_errors",
1849                 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1850         },
1851         {
1852                 .str = "a_symbol_error_during_carrier",
1853                 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1854         },
1855         {
1856                 .str = "a_mac_control_frames_transmitted",
1857                 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1858         },
1859         {
1860                 .str = "a_mac_control_frames_received",
1861                 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1862         },
1863         {
1864                 .str = "a_unsupported_opcodes_received",
1865                 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1866         },
1867         {
1868                 .str = "a_pause_mac_ctrl_frames_received",
1869                 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1870         },
1871         {
1872                 .str = "a_pause_mac_ctrl_frames_xmitted",
1873                 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1874         },
1875 };
1876
1877 #define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
1878
1879 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_rfc_2819_stats[] = {
1880         {
1881                 .str = "ether_pkts64octets",
1882                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts64octets_get,
1883         },
1884         {
1885                 .str = "ether_pkts65to127octets",
1886                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts65to127octets_get,
1887         },
1888         {
1889                 .str = "ether_pkts128to255octets",
1890                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts128to255octets_get,
1891         },
1892         {
1893                 .str = "ether_pkts256to511octets",
1894                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts256to511octets_get,
1895         },
1896         {
1897                 .str = "ether_pkts512to1023octets",
1898                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts512to1023octets_get,
1899         },
1900         {
1901                 .str = "ether_pkts1024to1518octets",
1902                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts1024to1518octets_get,
1903         },
1904         {
1905                 .str = "ether_pkts1519to2047octets",
1906                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts1519to2047octets_get,
1907         },
1908         {
1909                 .str = "ether_pkts2048to4095octets",
1910                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts2048to4095octets_get,
1911         },
1912         {
1913                 .str = "ether_pkts4096to8191octets",
1914                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts4096to8191octets_get,
1915         },
1916         {
1917                 .str = "ether_pkts8192to10239octets",
1918                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts8192to10239octets_get,
1919         },
1920 };
1921
1922 #define MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN \
1923         ARRAY_SIZE(mlxsw_sp_port_hw_rfc_2819_stats)
1924
1925 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
1926         {
1927                 .str = "rx_octets_prio",
1928                 .getter = mlxsw_reg_ppcnt_rx_octets_get,
1929         },
1930         {
1931                 .str = "rx_frames_prio",
1932                 .getter = mlxsw_reg_ppcnt_rx_frames_get,
1933         },
1934         {
1935                 .str = "tx_octets_prio",
1936                 .getter = mlxsw_reg_ppcnt_tx_octets_get,
1937         },
1938         {
1939                 .str = "tx_frames_prio",
1940                 .getter = mlxsw_reg_ppcnt_tx_frames_get,
1941         },
1942         {
1943                 .str = "rx_pause_prio",
1944                 .getter = mlxsw_reg_ppcnt_rx_pause_get,
1945         },
1946         {
1947                 .str = "rx_pause_duration_prio",
1948                 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
1949         },
1950         {
1951                 .str = "tx_pause_prio",
1952                 .getter = mlxsw_reg_ppcnt_tx_pause_get,
1953         },
1954         {
1955                 .str = "tx_pause_duration_prio",
1956                 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
1957         },
1958 };
1959
1960 #define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
1961
1962 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
1963         {
1964                 .str = "tc_transmit_queue_tc",
1965                 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
1966                 .cells_bytes = true,
1967         },
1968         {
1969                 .str = "tc_no_buffer_discard_uc_tc",
1970                 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
1971         },
1972 };
1973
1974 #define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
1975
1976 #define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
1977                                          MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN + \
1978                                          (MLXSW_SP_PORT_HW_PRIO_STATS_LEN * \
1979                                           IEEE_8021QAZ_MAX_TCS) + \
1980                                          (MLXSW_SP_PORT_HW_TC_STATS_LEN * \
1981                                           TC_MAX_QUEUE))
1982
1983 static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
1984 {
1985         int i;
1986
1987         for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
1988                 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1989                          mlxsw_sp_port_hw_prio_stats[i].str, prio);
1990                 *p += ETH_GSTRING_LEN;
1991         }
1992 }
1993
1994 static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
1995 {
1996         int i;
1997
1998         for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
1999                 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
2000                          mlxsw_sp_port_hw_tc_stats[i].str, tc);
2001                 *p += ETH_GSTRING_LEN;
2002         }
2003 }
2004
2005 static void mlxsw_sp_port_get_strings(struct net_device *dev,
2006                                       u32 stringset, u8 *data)
2007 {
2008         u8 *p = data;
2009         int i;
2010
2011         switch (stringset) {
2012         case ETH_SS_STATS:
2013                 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
2014                         memcpy(p, mlxsw_sp_port_hw_stats[i].str,
2015                                ETH_GSTRING_LEN);
2016                         p += ETH_GSTRING_LEN;
2017                 }
2018                 for (i = 0; i < MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN; i++) {
2019                         memcpy(p, mlxsw_sp_port_hw_rfc_2819_stats[i].str,
2020                                ETH_GSTRING_LEN);
2021                         p += ETH_GSTRING_LEN;
2022                 }
2023
2024                 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2025                         mlxsw_sp_port_get_prio_strings(&p, i);
2026
2027                 for (i = 0; i < TC_MAX_QUEUE; i++)
2028                         mlxsw_sp_port_get_tc_strings(&p, i);
2029
2030                 break;
2031         }
2032 }
2033
2034 static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
2035                                      enum ethtool_phys_id_state state)
2036 {
2037         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2038         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2039         char mlcr_pl[MLXSW_REG_MLCR_LEN];
2040         bool active;
2041
2042         switch (state) {
2043         case ETHTOOL_ID_ACTIVE:
2044                 active = true;
2045                 break;
2046         case ETHTOOL_ID_INACTIVE:
2047                 active = false;
2048                 break;
2049         default:
2050                 return -EOPNOTSUPP;
2051         }
2052
2053         mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
2054         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
2055 }
2056
2057 static int
2058 mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
2059                                int *p_len, enum mlxsw_reg_ppcnt_grp grp)
2060 {
2061         switch (grp) {
2062         case MLXSW_REG_PPCNT_IEEE_8023_CNT:
2063                 *p_hw_stats = mlxsw_sp_port_hw_stats;
2064                 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
2065                 break;
2066         case MLXSW_REG_PPCNT_RFC_2819_CNT:
2067                 *p_hw_stats = mlxsw_sp_port_hw_rfc_2819_stats;
2068                 *p_len = MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN;
2069                 break;
2070         case MLXSW_REG_PPCNT_PRIO_CNT:
2071                 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
2072                 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2073                 break;
2074         case MLXSW_REG_PPCNT_TC_CNT:
2075                 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
2076                 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
2077                 break;
2078         default:
2079                 WARN_ON(1);
2080                 return -EOPNOTSUPP;
2081         }
2082         return 0;
2083 }
2084
2085 static void __mlxsw_sp_port_get_stats(struct net_device *dev,
2086                                       enum mlxsw_reg_ppcnt_grp grp, int prio,
2087                                       u64 *data, int data_index)
2088 {
2089         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2090         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2091         struct mlxsw_sp_port_hw_stats *hw_stats;
2092         char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
2093         int i, len;
2094         int err;
2095
2096         err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
2097         if (err)
2098                 return;
2099         mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
2100         for (i = 0; i < len; i++) {
2101                 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
2102                 if (!hw_stats[i].cells_bytes)
2103                         continue;
2104                 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
2105                                                             data[data_index + i]);
2106         }
2107 }
2108
2109 static void mlxsw_sp_port_get_stats(struct net_device *dev,
2110                                     struct ethtool_stats *stats, u64 *data)
2111 {
2112         int i, data_index = 0;
2113
2114         /* IEEE 802.3 Counters */
2115         __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
2116                                   data, data_index);
2117         data_index = MLXSW_SP_PORT_HW_STATS_LEN;
2118
2119         /* RFC 2819 Counters */
2120         __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_RFC_2819_CNT, 0,
2121                                   data, data_index);
2122         data_index += MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN;
2123
2124         /* Per-Priority Counters */
2125         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2126                 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
2127                                           data, data_index);
2128                 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2129         }
2130
2131         /* Per-TC Counters */
2132         for (i = 0; i < TC_MAX_QUEUE; i++) {
2133                 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
2134                                           data, data_index);
2135                 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
2136         }
2137 }
2138
2139 static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
2140 {
2141         switch (sset) {
2142         case ETH_SS_STATS:
2143                 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
2144         default:
2145                 return -EOPNOTSUPP;
2146         }
2147 }
2148
2149 struct mlxsw_sp_port_link_mode {
2150         enum ethtool_link_mode_bit_indices mask_ethtool;
2151         u32 mask;
2152         u32 speed;
2153 };
2154
2155 static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
2156         {
2157                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
2158                 .mask_ethtool   = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2159                 .speed          = SPEED_100,
2160         },
2161         {
2162                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
2163                                   MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
2164                 .mask_ethtool   = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2165                 .speed          = SPEED_1000,
2166         },
2167         {
2168                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
2169                 .mask_ethtool   = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2170                 .speed          = SPEED_10000,
2171         },
2172         {
2173                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
2174                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
2175                 .mask_ethtool   = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2176                 .speed          = SPEED_10000,
2177         },
2178         {
2179                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2180                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2181                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2182                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
2183                 .mask_ethtool   = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2184                 .speed          = SPEED_10000,
2185         },
2186         {
2187                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
2188                 .mask_ethtool   = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
2189                 .speed          = SPEED_20000,
2190         },
2191         {
2192                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
2193                 .mask_ethtool   = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2194                 .speed          = SPEED_40000,
2195         },
2196         {
2197                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
2198                 .mask_ethtool   = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2199                 .speed          = SPEED_40000,
2200         },
2201         {
2202                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
2203                 .mask_ethtool   = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2204                 .speed          = SPEED_40000,
2205         },
2206         {
2207                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
2208                 .mask_ethtool   = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2209                 .speed          = SPEED_40000,
2210         },
2211         {
2212                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
2213                 .mask_ethtool   = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2214                 .speed          = SPEED_25000,
2215         },
2216         {
2217                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
2218                 .mask_ethtool   = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2219                 .speed          = SPEED_25000,
2220         },
2221         {
2222                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2223                 .mask_ethtool   = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2224                 .speed          = SPEED_25000,
2225         },
2226         {
2227                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2228                 .mask_ethtool   = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2229                 .speed          = SPEED_25000,
2230         },
2231         {
2232                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
2233                 .mask_ethtool   = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2234                 .speed          = SPEED_50000,
2235         },
2236         {
2237                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
2238                 .mask_ethtool   = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2239                 .speed          = SPEED_50000,
2240         },
2241         {
2242                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
2243                 .mask_ethtool   = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2244                 .speed          = SPEED_50000,
2245         },
2246         {
2247                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2248                 .mask_ethtool   = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
2249                 .speed          = SPEED_56000,
2250         },
2251         {
2252                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2253                 .mask_ethtool   = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
2254                 .speed          = SPEED_56000,
2255         },
2256         {
2257                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2258                 .mask_ethtool   = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
2259                 .speed          = SPEED_56000,
2260         },
2261         {
2262                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2263                 .mask_ethtool   = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
2264                 .speed          = SPEED_56000,
2265         },
2266         {
2267                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
2268                 .mask_ethtool   = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2269                 .speed          = SPEED_100000,
2270         },
2271         {
2272                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
2273                 .mask_ethtool   = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2274                 .speed          = SPEED_100000,
2275         },
2276         {
2277                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
2278                 .mask_ethtool   = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2279                 .speed          = SPEED_100000,
2280         },
2281         {
2282                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
2283                 .mask_ethtool   = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2284                 .speed          = SPEED_100000,
2285         },
2286 };
2287
2288 #define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
2289
2290 static void
2291 mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
2292                                   struct ethtool_link_ksettings *cmd)
2293 {
2294         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2295                               MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2296                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2297                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2298                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2299                               MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2300                 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
2301
2302         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2303                               MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2304                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2305                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
2306                               MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
2307                 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
2308 }
2309
2310 static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
2311 {
2312         int i;
2313
2314         for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2315                 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
2316                         __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2317                                   mode);
2318         }
2319 }
2320
2321 static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
2322                                             struct ethtool_link_ksettings *cmd)
2323 {
2324         u32 speed = SPEED_UNKNOWN;
2325         u8 duplex = DUPLEX_UNKNOWN;
2326         int i;
2327
2328         if (!carrier_ok)
2329                 goto out;
2330
2331         for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2332                 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
2333                         speed = mlxsw_sp_port_link_mode[i].speed;
2334                         duplex = DUPLEX_FULL;
2335                         break;
2336                 }
2337         }
2338 out:
2339         cmd->base.speed = speed;
2340         cmd->base.duplex = duplex;
2341 }
2342
2343 static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
2344 {
2345         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2346                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2347                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2348                               MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2349                 return PORT_FIBRE;
2350
2351         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2352                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2353                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
2354                 return PORT_DA;
2355
2356         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2357                               MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2358                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2359                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
2360                 return PORT_NONE;
2361
2362         return PORT_OTHER;
2363 }
2364
2365 static u32
2366 mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
2367 {
2368         u32 ptys_proto = 0;
2369         int i;
2370
2371         for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2372                 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2373                              cmd->link_modes.advertising))
2374                         ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2375         }
2376         return ptys_proto;
2377 }
2378
2379 static u32 mlxsw_sp_to_ptys_speed(u32 speed)
2380 {
2381         u32 ptys_proto = 0;
2382         int i;
2383
2384         for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2385                 if (speed == mlxsw_sp_port_link_mode[i].speed)
2386                         ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2387         }
2388         return ptys_proto;
2389 }
2390
2391 static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
2392 {
2393         u32 ptys_proto = 0;
2394         int i;
2395
2396         for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2397                 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
2398                         ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2399         }
2400         return ptys_proto;
2401 }
2402
2403 static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
2404                                              struct ethtool_link_ksettings *cmd)
2405 {
2406         ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
2407         ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
2408         ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
2409
2410         mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
2411         mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
2412 }
2413
2414 static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
2415                                              struct ethtool_link_ksettings *cmd)
2416 {
2417         if (!autoneg)
2418                 return;
2419
2420         ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
2421         mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
2422 }
2423
2424 static void
2425 mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
2426                                     struct ethtool_link_ksettings *cmd)
2427 {
2428         if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
2429                 return;
2430
2431         ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
2432         mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
2433 }
2434
2435 static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
2436                                             struct ethtool_link_ksettings *cmd)
2437 {
2438         u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
2439         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2440         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2441         char ptys_pl[MLXSW_REG_PTYS_LEN];
2442         u8 autoneg_status;
2443         bool autoneg;
2444         int err;
2445
2446         autoneg = mlxsw_sp_port->link.autoneg;
2447         mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0, false);
2448         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2449         if (err)
2450                 return err;
2451         mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin,
2452                                   &eth_proto_oper);
2453
2454         mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
2455
2456         mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
2457
2458         eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
2459         autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
2460         mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
2461
2462         cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2463         cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
2464         mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
2465                                         cmd);
2466
2467         return 0;
2468 }
2469
2470 static int
2471 mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
2472                                  const struct ethtool_link_ksettings *cmd)
2473 {
2474         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2475         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2476         char ptys_pl[MLXSW_REG_PTYS_LEN];
2477         u32 eth_proto_cap, eth_proto_new;
2478         bool autoneg;
2479         int err;
2480
2481         mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0, false);
2482         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2483         if (err)
2484                 return err;
2485         mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
2486
2487         autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
2488         eth_proto_new = autoneg ?
2489                 mlxsw_sp_to_ptys_advert_link(cmd) :
2490                 mlxsw_sp_to_ptys_speed(cmd->base.speed);
2491
2492         eth_proto_new = eth_proto_new & eth_proto_cap;
2493         if (!eth_proto_new) {
2494                 netdev_err(dev, "No supported speed requested\n");
2495                 return -EINVAL;
2496         }
2497
2498         mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2499                                 eth_proto_new, autoneg);
2500         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2501         if (err)
2502                 return err;
2503
2504         if (!netif_running(dev))
2505                 return 0;
2506
2507         mlxsw_sp_port->link.autoneg = autoneg;
2508
2509         mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2510         mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
2511
2512         return 0;
2513 }
2514
2515 static int mlxsw_sp_flash_device(struct net_device *dev,
2516                                  struct ethtool_flash *flash)
2517 {
2518         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2519         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2520         const struct firmware *firmware;
2521         int err;
2522
2523         if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
2524                 return -EOPNOTSUPP;
2525
2526         dev_hold(dev);
2527         rtnl_unlock();
2528
2529         err = request_firmware_direct(&firmware, flash->data, &dev->dev);
2530         if (err)
2531                 goto out;
2532         err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
2533         release_firmware(firmware);
2534 out:
2535         rtnl_lock();
2536         dev_put(dev);
2537         return err;
2538 }
2539
2540 #define MLXSW_SP_I2C_ADDR_LOW 0x50
2541 #define MLXSW_SP_I2C_ADDR_HIGH 0x51
2542 #define MLXSW_SP_EEPROM_PAGE_LENGTH 256
2543
2544 static int mlxsw_sp_query_module_eeprom(struct mlxsw_sp_port *mlxsw_sp_port,
2545                                         u16 offset, u16 size, void *data,
2546                                         unsigned int *p_read_size)
2547 {
2548         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2549         char eeprom_tmp[MLXSW_SP_REG_MCIA_EEPROM_SIZE];
2550         char mcia_pl[MLXSW_REG_MCIA_LEN];
2551         u16 i2c_addr;
2552         int status;
2553         int err;
2554
2555         size = min_t(u16, size, MLXSW_SP_REG_MCIA_EEPROM_SIZE);
2556
2557         if (offset < MLXSW_SP_EEPROM_PAGE_LENGTH &&
2558             offset + size > MLXSW_SP_EEPROM_PAGE_LENGTH)
2559                 /* Cross pages read, read until offset 256 in low page */
2560                 size = MLXSW_SP_EEPROM_PAGE_LENGTH - offset;
2561
2562         i2c_addr = MLXSW_SP_I2C_ADDR_LOW;
2563         if (offset >= MLXSW_SP_EEPROM_PAGE_LENGTH) {
2564                 i2c_addr = MLXSW_SP_I2C_ADDR_HIGH;
2565                 offset -= MLXSW_SP_EEPROM_PAGE_LENGTH;
2566         }
2567
2568         mlxsw_reg_mcia_pack(mcia_pl, mlxsw_sp_port->mapping.module,
2569                             0, 0, offset, size, i2c_addr);
2570
2571         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcia), mcia_pl);
2572         if (err)
2573                 return err;
2574
2575         status = mlxsw_reg_mcia_status_get(mcia_pl);
2576         if (status)
2577                 return -EIO;
2578
2579         mlxsw_reg_mcia_eeprom_memcpy_from(mcia_pl, eeprom_tmp);
2580         memcpy(data, eeprom_tmp, size);
2581         *p_read_size = size;
2582
2583         return 0;
2584 }
2585
2586 enum mlxsw_sp_eeprom_module_info_rev_id {
2587         MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_UNSPC      = 0x00,
2588         MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8436       = 0x01,
2589         MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636       = 0x03,
2590 };
2591
2592 enum mlxsw_sp_eeprom_module_info_id {
2593         MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP              = 0x03,
2594         MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP             = 0x0C,
2595         MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS        = 0x0D,
2596         MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28           = 0x11,
2597 };
2598
2599 enum mlxsw_sp_eeprom_module_info {
2600         MLXSW_SP_EEPROM_MODULE_INFO_ID,
2601         MLXSW_SP_EEPROM_MODULE_INFO_REV_ID,
2602         MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2603 };
2604
2605 static int mlxsw_sp_get_module_info(struct net_device *netdev,
2606                                     struct ethtool_modinfo *modinfo)
2607 {
2608         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2609         u8 module_info[MLXSW_SP_EEPROM_MODULE_INFO_SIZE];
2610         u8 module_rev_id, module_id;
2611         unsigned int read_size;
2612         int err;
2613
2614         err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, 0,
2615                                            MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2616                                            module_info, &read_size);
2617         if (err)
2618                 return err;
2619
2620         if (read_size < MLXSW_SP_EEPROM_MODULE_INFO_SIZE)
2621                 return -EIO;
2622
2623         module_rev_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_REV_ID];
2624         module_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_ID];
2625
2626         switch (module_id) {
2627         case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP:
2628                 modinfo->type       = ETH_MODULE_SFF_8436;
2629                 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2630                 break;
2631         case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS:
2632         case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28:
2633                 if (module_id  == MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 ||
2634                     module_rev_id >= MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636) {
2635                         modinfo->type       = ETH_MODULE_SFF_8636;
2636                         modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
2637                 } else {
2638                         modinfo->type       = ETH_MODULE_SFF_8436;
2639                         modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2640                 }
2641                 break;
2642         case MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP:
2643                 modinfo->type       = ETH_MODULE_SFF_8472;
2644                 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2645                 break;
2646         default:
2647                 return -EINVAL;
2648         }
2649
2650         return 0;
2651 }
2652
2653 static int mlxsw_sp_get_module_eeprom(struct net_device *netdev,
2654                                       struct ethtool_eeprom *ee,
2655                                       u8 *data)
2656 {
2657         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2658         int offset = ee->offset;
2659         unsigned int read_size;
2660         int i = 0;
2661         int err;
2662
2663         if (!ee->len)
2664                 return -EINVAL;
2665
2666         memset(data, 0, ee->len);
2667
2668         while (i < ee->len) {
2669                 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, offset,
2670                                                    ee->len - i, data + i,
2671                                                    &read_size);
2672                 if (err) {
2673                         netdev_err(mlxsw_sp_port->dev, "Eeprom query failed\n");
2674                         return err;
2675                 }
2676
2677                 i += read_size;
2678                 offset += read_size;
2679         }
2680
2681         return 0;
2682 }
2683
2684 static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
2685         .get_drvinfo            = mlxsw_sp_port_get_drvinfo,
2686         .get_link               = ethtool_op_get_link,
2687         .get_pauseparam         = mlxsw_sp_port_get_pauseparam,
2688         .set_pauseparam         = mlxsw_sp_port_set_pauseparam,
2689         .get_strings            = mlxsw_sp_port_get_strings,
2690         .set_phys_id            = mlxsw_sp_port_set_phys_id,
2691         .get_ethtool_stats      = mlxsw_sp_port_get_stats,
2692         .get_sset_count         = mlxsw_sp_port_get_sset_count,
2693         .get_link_ksettings     = mlxsw_sp_port_get_link_ksettings,
2694         .set_link_ksettings     = mlxsw_sp_port_set_link_ksettings,
2695         .flash_device           = mlxsw_sp_flash_device,
2696         .get_module_info        = mlxsw_sp_get_module_info,
2697         .get_module_eeprom      = mlxsw_sp_get_module_eeprom,
2698 };
2699
2700 static int
2701 mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
2702 {
2703         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2704         u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
2705         char ptys_pl[MLXSW_REG_PTYS_LEN];
2706         u32 eth_proto_admin;
2707
2708         eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
2709         mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2710                                 eth_proto_admin, mlxsw_sp_port->link.autoneg);
2711         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2712 }
2713
2714 int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
2715                           enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
2716                           bool dwrr, u8 dwrr_weight)
2717 {
2718         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2719         char qeec_pl[MLXSW_REG_QEEC_LEN];
2720
2721         mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2722                             next_index);
2723         mlxsw_reg_qeec_de_set(qeec_pl, true);
2724         mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
2725         mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
2726         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2727 }
2728
2729 int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
2730                                   enum mlxsw_reg_qeec_hr hr, u8 index,
2731                                   u8 next_index, u32 maxrate)
2732 {
2733         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2734         char qeec_pl[MLXSW_REG_QEEC_LEN];
2735
2736         mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2737                             next_index);
2738         mlxsw_reg_qeec_mase_set(qeec_pl, true);
2739         mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
2740         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2741 }
2742
2743 static int mlxsw_sp_port_min_bw_set(struct mlxsw_sp_port *mlxsw_sp_port,
2744                                     enum mlxsw_reg_qeec_hr hr, u8 index,
2745                                     u8 next_index, u32 minrate)
2746 {
2747         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2748         char qeec_pl[MLXSW_REG_QEEC_LEN];
2749
2750         mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2751                             next_index);
2752         mlxsw_reg_qeec_mise_set(qeec_pl, true);
2753         mlxsw_reg_qeec_min_shaper_rate_set(qeec_pl, minrate);
2754
2755         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2756 }
2757
2758 int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
2759                               u8 switch_prio, u8 tclass)
2760 {
2761         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2762         char qtct_pl[MLXSW_REG_QTCT_LEN];
2763
2764         mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
2765                             tclass);
2766         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
2767 }
2768
2769 static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
2770 {
2771         int err, i;
2772
2773         /* Setup the elements hierarcy, so that each TC is linked to
2774          * one subgroup, which are all member in the same group.
2775          */
2776         err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2777                                     MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
2778                                     0);
2779         if (err)
2780                 return err;
2781         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2782                 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2783                                             MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
2784                                             0, false, 0);
2785                 if (err)
2786                         return err;
2787         }
2788         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2789                 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2790                                             MLXSW_REG_QEEC_HIERARCY_TC, i, i,
2791                                             false, 0);
2792                 if (err)
2793                         return err;
2794
2795                 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2796                                             MLXSW_REG_QEEC_HIERARCY_TC,
2797                                             i + 8, i,
2798                                             false, 0);
2799                 if (err)
2800                         return err;
2801         }
2802
2803         /* Make sure the max shaper is disabled in all hierarchies that
2804          * support it.
2805          */
2806         err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2807                                             MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
2808                                             MLXSW_REG_QEEC_MAS_DIS);
2809         if (err)
2810                 return err;
2811         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2812                 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2813                                                     MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
2814                                                     i, 0,
2815                                                     MLXSW_REG_QEEC_MAS_DIS);
2816                 if (err)
2817                         return err;
2818         }
2819         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2820                 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2821                                                     MLXSW_REG_QEEC_HIERARCY_TC,
2822                                                     i, i,
2823                                                     MLXSW_REG_QEEC_MAS_DIS);
2824                 if (err)
2825                         return err;
2826
2827                 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2828                                                     MLXSW_REG_QEEC_HIERARCY_TC,
2829                                                     i + 8, i,
2830                                                     MLXSW_REG_QEEC_MAS_DIS);
2831                 if (err)
2832                         return err;
2833         }
2834
2835         /* Configure the min shaper for multicast TCs. */
2836         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2837                 err = mlxsw_sp_port_min_bw_set(mlxsw_sp_port,
2838                                                MLXSW_REG_QEEC_HIERARCY_TC,
2839                                                i + 8, i,
2840                                                MLXSW_REG_QEEC_MIS_MIN);
2841                 if (err)
2842                         return err;
2843         }
2844
2845         /* Map all priorities to traffic class 0. */
2846         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2847                 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
2848                 if (err)
2849                         return err;
2850         }
2851
2852         return 0;
2853 }
2854
2855 static int mlxsw_sp_port_tc_mc_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
2856                                         bool enable)
2857 {
2858         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2859         char qtctm_pl[MLXSW_REG_QTCTM_LEN];
2860
2861         mlxsw_reg_qtctm_pack(qtctm_pl, mlxsw_sp_port->local_port, enable);
2862         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtctm), qtctm_pl);
2863 }
2864
2865 static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2866                                 bool split, u8 module, u8 width, u8 lane)
2867 {
2868         struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
2869         struct mlxsw_sp_port *mlxsw_sp_port;
2870         struct net_device *dev;
2871         int err;
2872
2873         err = mlxsw_core_port_init(mlxsw_sp->core, local_port);
2874         if (err) {
2875                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
2876                         local_port);
2877                 return err;
2878         }
2879
2880         dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
2881         if (!dev) {
2882                 err = -ENOMEM;
2883                 goto err_alloc_etherdev;
2884         }
2885         SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
2886         mlxsw_sp_port = netdev_priv(dev);
2887         mlxsw_sp_port->dev = dev;
2888         mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
2889         mlxsw_sp_port->local_port = local_port;
2890         mlxsw_sp_port->pvid = 1;
2891         mlxsw_sp_port->split = split;
2892         mlxsw_sp_port->mapping.module = module;
2893         mlxsw_sp_port->mapping.width = width;
2894         mlxsw_sp_port->mapping.lane = lane;
2895         mlxsw_sp_port->link.autoneg = 1;
2896         INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
2897         INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
2898
2899         mlxsw_sp_port->pcpu_stats =
2900                 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
2901         if (!mlxsw_sp_port->pcpu_stats) {
2902                 err = -ENOMEM;
2903                 goto err_alloc_stats;
2904         }
2905
2906         mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
2907                                         GFP_KERNEL);
2908         if (!mlxsw_sp_port->sample) {
2909                 err = -ENOMEM;
2910                 goto err_alloc_sample;
2911         }
2912
2913         INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw,
2914                           &update_stats_cache);
2915
2916         dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
2917         dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
2918
2919         err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane);
2920         if (err) {
2921                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
2922                         mlxsw_sp_port->local_port);
2923                 goto err_port_module_map;
2924         }
2925
2926         err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
2927         if (err) {
2928                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
2929                         mlxsw_sp_port->local_port);
2930                 goto err_port_swid_set;
2931         }
2932
2933         err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
2934         if (err) {
2935                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
2936                         mlxsw_sp_port->local_port);
2937                 goto err_dev_addr_init;
2938         }
2939
2940         netif_carrier_off(dev);
2941
2942         dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
2943                          NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
2944         dev->hw_features |= NETIF_F_HW_TC;
2945
2946         dev->min_mtu = 0;
2947         dev->max_mtu = ETH_MAX_MTU;
2948
2949         /* Each packet needs to have a Tx header (metadata) on top all other
2950          * headers.
2951          */
2952         dev->needed_headroom = MLXSW_TXHDR_LEN;
2953
2954         err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
2955         if (err) {
2956                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
2957                         mlxsw_sp_port->local_port);
2958                 goto err_port_system_port_mapping_set;
2959         }
2960
2961         err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
2962         if (err) {
2963                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
2964                         mlxsw_sp_port->local_port);
2965                 goto err_port_speed_by_width_set;
2966         }
2967
2968         err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
2969         if (err) {
2970                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
2971                         mlxsw_sp_port->local_port);
2972                 goto err_port_mtu_set;
2973         }
2974
2975         err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2976         if (err)
2977                 goto err_port_admin_status_set;
2978
2979         err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
2980         if (err) {
2981                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
2982                         mlxsw_sp_port->local_port);
2983                 goto err_port_buffers_init;
2984         }
2985
2986         err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
2987         if (err) {
2988                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
2989                         mlxsw_sp_port->local_port);
2990                 goto err_port_ets_init;
2991         }
2992
2993         err = mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, true);
2994         if (err) {
2995                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC MC mode\n",
2996                         mlxsw_sp_port->local_port);
2997                 goto err_port_tc_mc_mode;
2998         }
2999
3000         /* ETS and buffers must be initialized before DCB. */
3001         err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
3002         if (err) {
3003                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
3004                         mlxsw_sp_port->local_port);
3005                 goto err_port_dcb_init;
3006         }
3007
3008         err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
3009         if (err) {
3010                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
3011                         mlxsw_sp_port->local_port);
3012                 goto err_port_fids_init;
3013         }
3014
3015         err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port);
3016         if (err) {
3017                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n",
3018                         mlxsw_sp_port->local_port);
3019                 goto err_port_qdiscs_init;
3020         }
3021
3022         err = mlxsw_sp_port_nve_init(mlxsw_sp_port);
3023         if (err) {
3024                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize NVE\n",
3025                         mlxsw_sp_port->local_port);
3026                 goto err_port_nve_init;
3027         }
3028
3029         mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
3030         if (IS_ERR(mlxsw_sp_port_vlan)) {
3031                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
3032                         mlxsw_sp_port->local_port);
3033                 err = PTR_ERR(mlxsw_sp_port_vlan);
3034                 goto err_port_vlan_get;
3035         }
3036
3037         mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
3038         mlxsw_sp->ports[local_port] = mlxsw_sp_port;
3039         err = register_netdev(dev);
3040         if (err) {
3041                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
3042                         mlxsw_sp_port->local_port);
3043                 goto err_register_netdev;
3044         }
3045
3046         mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
3047                                 mlxsw_sp_port, dev, module + 1,
3048                                 mlxsw_sp_port->split, lane / width);
3049         mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0);
3050         return 0;
3051
3052 err_register_netdev:
3053         mlxsw_sp->ports[local_port] = NULL;
3054         mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
3055         mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
3056 err_port_vlan_get:
3057         mlxsw_sp_port_nve_fini(mlxsw_sp_port);
3058 err_port_nve_init:
3059         mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
3060 err_port_qdiscs_init:
3061         mlxsw_sp_port_fids_fini(mlxsw_sp_port);
3062 err_port_fids_init:
3063         mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
3064 err_port_dcb_init:
3065         mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false);
3066 err_port_tc_mc_mode:
3067 err_port_ets_init:
3068 err_port_buffers_init:
3069 err_port_admin_status_set:
3070 err_port_mtu_set:
3071 err_port_speed_by_width_set:
3072 err_port_system_port_mapping_set:
3073 err_dev_addr_init:
3074         mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
3075 err_port_swid_set:
3076         mlxsw_sp_port_module_unmap(mlxsw_sp_port);
3077 err_port_module_map:
3078         kfree(mlxsw_sp_port->sample);
3079 err_alloc_sample:
3080         free_percpu(mlxsw_sp_port->pcpu_stats);
3081 err_alloc_stats:
3082         free_netdev(dev);
3083 err_alloc_etherdev:
3084         mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3085         return err;
3086 }
3087
3088 static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
3089 {
3090         struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3091
3092         cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw);
3093         mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
3094         unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
3095         mlxsw_sp->ports[local_port] = NULL;
3096         mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
3097         mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
3098         mlxsw_sp_port_nve_fini(mlxsw_sp_port);
3099         mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
3100         mlxsw_sp_port_fids_fini(mlxsw_sp_port);
3101         mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
3102         mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false);
3103         mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
3104         mlxsw_sp_port_module_unmap(mlxsw_sp_port);
3105         kfree(mlxsw_sp_port->sample);
3106         free_percpu(mlxsw_sp_port->pcpu_stats);
3107         WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
3108         free_netdev(mlxsw_sp_port->dev);
3109         mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3110 }
3111
3112 static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
3113 {
3114         return mlxsw_sp->ports[local_port] != NULL;
3115 }
3116
3117 static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
3118 {
3119         int i;
3120
3121         for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
3122                 if (mlxsw_sp_port_created(mlxsw_sp, i))
3123                         mlxsw_sp_port_remove(mlxsw_sp, i);
3124         kfree(mlxsw_sp->port_to_module);
3125         kfree(mlxsw_sp->ports);
3126 }
3127
3128 static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
3129 {
3130         unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
3131         u8 module, width, lane;
3132         size_t alloc_size;
3133         int i;
3134         int err;
3135
3136         alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
3137         mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
3138         if (!mlxsw_sp->ports)
3139                 return -ENOMEM;
3140
3141         mlxsw_sp->port_to_module = kmalloc_array(max_ports, sizeof(int),
3142                                                  GFP_KERNEL);
3143         if (!mlxsw_sp->port_to_module) {
3144                 err = -ENOMEM;
3145                 goto err_port_to_module_alloc;
3146         }
3147
3148         for (i = 1; i < max_ports; i++) {
3149                 /* Mark as invalid */
3150                 mlxsw_sp->port_to_module[i] = -1;
3151
3152                 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
3153                                                     &width, &lane);
3154                 if (err)
3155                         goto err_port_module_info_get;
3156                 if (!width)
3157                         continue;
3158                 mlxsw_sp->port_to_module[i] = module;
3159                 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
3160                                            module, width, lane);
3161                 if (err)
3162                         goto err_port_create;
3163         }
3164         return 0;
3165
3166 err_port_create:
3167 err_port_module_info_get:
3168         for (i--; i >= 1; i--)
3169                 if (mlxsw_sp_port_created(mlxsw_sp, i))
3170                         mlxsw_sp_port_remove(mlxsw_sp, i);
3171         kfree(mlxsw_sp->port_to_module);
3172 err_port_to_module_alloc:
3173         kfree(mlxsw_sp->ports);
3174         return err;
3175 }
3176
3177 static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
3178 {
3179         u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
3180
3181         return local_port - offset;
3182 }
3183
3184 static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
3185                                       u8 module, unsigned int count)
3186 {
3187         u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
3188         int err, i;
3189
3190         for (i = 0; i < count; i++) {
3191                 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
3192                                            module, width, i * width);
3193                 if (err)
3194                         goto err_port_create;
3195         }
3196
3197         return 0;
3198
3199 err_port_create:
3200         for (i--; i >= 0; i--)
3201                 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3202                         mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
3203         return err;
3204 }
3205
3206 static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
3207                                          u8 base_port, unsigned int count)
3208 {
3209         u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
3210         int i;
3211
3212         /* Split by four means we need to re-create two ports, otherwise
3213          * only one.
3214          */
3215         count = count / 2;
3216
3217         for (i = 0; i < count; i++) {
3218                 local_port = base_port + i * 2;
3219                 if (mlxsw_sp->port_to_module[local_port] < 0)
3220                         continue;
3221                 module = mlxsw_sp->port_to_module[local_port];
3222
3223                 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
3224                                      width, 0);
3225         }
3226 }
3227
3228 static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
3229                                unsigned int count,
3230                                struct netlink_ext_ack *extack)
3231 {
3232         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3233         struct mlxsw_sp_port *mlxsw_sp_port;
3234         u8 module, cur_width, base_port;
3235         int i;
3236         int err;
3237
3238         mlxsw_sp_port = mlxsw_sp->ports[local_port];
3239         if (!mlxsw_sp_port) {
3240                 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3241                         local_port);
3242                 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
3243                 return -EINVAL;
3244         }
3245
3246         module = mlxsw_sp_port->mapping.module;
3247         cur_width = mlxsw_sp_port->mapping.width;
3248
3249         if (count != 2 && count != 4) {
3250                 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
3251                 NL_SET_ERR_MSG_MOD(extack, "Port can only be split into 2 or 4 ports");
3252                 return -EINVAL;
3253         }
3254
3255         if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
3256                 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
3257                 NL_SET_ERR_MSG_MOD(extack, "Port cannot be split further");
3258                 return -EINVAL;
3259         }
3260
3261         /* Make sure we have enough slave (even) ports for the split. */
3262         if (count == 2) {
3263                 base_port = local_port;
3264                 if (mlxsw_sp->ports[base_port + 1]) {
3265                         netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3266                         NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration");
3267                         return -EINVAL;
3268                 }
3269         } else {
3270                 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3271                 if (mlxsw_sp->ports[base_port + 1] ||
3272                     mlxsw_sp->ports[base_port + 3]) {
3273                         netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3274                         NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration");
3275                         return -EINVAL;
3276                 }
3277         }
3278
3279         for (i = 0; i < count; i++)
3280                 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3281                         mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
3282
3283         err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
3284         if (err) {
3285                 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
3286                 goto err_port_split_create;
3287         }
3288
3289         return 0;
3290
3291 err_port_split_create:
3292         mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
3293         return err;
3294 }
3295
3296 static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port,
3297                                  struct netlink_ext_ack *extack)
3298 {
3299         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3300         struct mlxsw_sp_port *mlxsw_sp_port;
3301         u8 cur_width, base_port;
3302         unsigned int count;
3303         int i;
3304
3305         mlxsw_sp_port = mlxsw_sp->ports[local_port];
3306         if (!mlxsw_sp_port) {
3307                 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3308                         local_port);
3309                 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
3310                 return -EINVAL;
3311         }
3312
3313         if (!mlxsw_sp_port->split) {
3314                 netdev_err(mlxsw_sp_port->dev, "Port was not split\n");
3315                 NL_SET_ERR_MSG_MOD(extack, "Port was not split");
3316                 return -EINVAL;
3317         }
3318
3319         cur_width = mlxsw_sp_port->mapping.width;
3320         count = cur_width == 1 ? 4 : 2;
3321
3322         base_port = mlxsw_sp_cluster_base_port_get(local_port);
3323
3324         /* Determine which ports to remove. */
3325         if (count == 2 && local_port >= base_port + 2)
3326                 base_port = base_port + 2;
3327
3328         for (i = 0; i < count; i++)
3329                 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3330                         mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
3331
3332         mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
3333
3334         return 0;
3335 }
3336
3337 static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
3338                                      char *pude_pl, void *priv)
3339 {
3340         struct mlxsw_sp *mlxsw_sp = priv;
3341         struct mlxsw_sp_port *mlxsw_sp_port;
3342         enum mlxsw_reg_pude_oper_status status;
3343         u8 local_port;
3344
3345         local_port = mlxsw_reg_pude_local_port_get(pude_pl);
3346         mlxsw_sp_port = mlxsw_sp->ports[local_port];
3347         if (!mlxsw_sp_port)
3348                 return;
3349
3350         status = mlxsw_reg_pude_oper_status_get(pude_pl);
3351         if (status == MLXSW_PORT_OPER_STATUS_UP) {
3352                 netdev_info(mlxsw_sp_port->dev, "link up\n");
3353                 netif_carrier_on(mlxsw_sp_port->dev);
3354         } else {
3355                 netdev_info(mlxsw_sp_port->dev, "link down\n");
3356                 netif_carrier_off(mlxsw_sp_port->dev);
3357         }
3358 }
3359
3360 static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
3361                                               u8 local_port, void *priv)
3362 {
3363         struct mlxsw_sp *mlxsw_sp = priv;
3364         struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3365         struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
3366
3367         if (unlikely(!mlxsw_sp_port)) {
3368                 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
3369                                      local_port);
3370                 return;
3371         }
3372
3373         skb->dev = mlxsw_sp_port->dev;
3374
3375         pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
3376         u64_stats_update_begin(&pcpu_stats->syncp);
3377         pcpu_stats->rx_packets++;
3378         pcpu_stats->rx_bytes += skb->len;
3379         u64_stats_update_end(&pcpu_stats->syncp);
3380
3381         skb->protocol = eth_type_trans(skb, skb->dev);
3382         netif_receive_skb(skb);
3383 }
3384
3385 static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
3386                                            void *priv)
3387 {
3388         skb->offload_fwd_mark = 1;
3389         return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
3390 }
3391
3392 static void mlxsw_sp_rx_listener_mr_mark_func(struct sk_buff *skb,
3393                                               u8 local_port, void *priv)
3394 {
3395         skb->offload_mr_fwd_mark = 1;
3396         skb->offload_fwd_mark = 1;
3397         return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
3398 }
3399
3400 static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
3401                                              void *priv)
3402 {
3403         struct mlxsw_sp *mlxsw_sp = priv;
3404         struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3405         struct psample_group *psample_group;
3406         u32 size;
3407
3408         if (unlikely(!mlxsw_sp_port)) {
3409                 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
3410                                      local_port);
3411                 goto out;
3412         }
3413         if (unlikely(!mlxsw_sp_port->sample)) {
3414                 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
3415                                      local_port);
3416                 goto out;
3417         }
3418
3419         size = mlxsw_sp_port->sample->truncate ?
3420                   mlxsw_sp_port->sample->trunc_size : skb->len;
3421
3422         rcu_read_lock();
3423         psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
3424         if (!psample_group)
3425                 goto out_unlock;
3426         psample_sample_packet(psample_group, skb, size,
3427                               mlxsw_sp_port->dev->ifindex, 0,
3428                               mlxsw_sp_port->sample->rate);
3429 out_unlock:
3430         rcu_read_unlock();
3431 out:
3432         consume_skb(skb);
3433 }
3434
3435 #define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl)  \
3436         MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
3437                   _is_ctrl, SP_##_trap_group, DISCARD)
3438
3439 #define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl)     \
3440         MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action,    \
3441                 _is_ctrl, SP_##_trap_group, DISCARD)
3442
3443 #define MLXSW_SP_RXL_MR_MARK(_trap_id, _action, _trap_group, _is_ctrl)  \
3444         MLXSW_RXL(mlxsw_sp_rx_listener_mr_mark_func, _trap_id, _action, \
3445                 _is_ctrl, SP_##_trap_group, DISCARD)
3446
3447 #define MLXSW_SP_EVENTL(_func, _trap_id)                \
3448         MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
3449
3450 static const struct mlxsw_listener mlxsw_sp_listener[] = {
3451         /* Events */
3452         MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
3453         /* L2 traps */
3454         MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
3455         MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
3456         MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true),
3457         MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
3458         MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
3459         MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
3460         MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
3461         MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
3462         MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
3463         MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
3464         MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
3465         MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),
3466         MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU, IPV6_MLD,
3467                           false),
3468         MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3469                              false),
3470         MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_DONE, TRAP_TO_CPU, IPV6_MLD,
3471                              false),
3472         MLXSW_SP_RXL_NO_MARK(IPV6_MLDV2_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3473                              false),
3474         /* L3 traps */
3475         MLXSW_SP_RXL_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3476         MLXSW_SP_RXL_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3477         MLXSW_SP_RXL_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3478         MLXSW_SP_RXL_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
3479         MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP,
3480                           false),
3481         MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, false),
3482         MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false),
3483         MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, ROUTER_EXP, false),
3484         MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, ROUTER_EXP,
3485                           false),
3486         MLXSW_SP_RXL_MARK(IPV4_OSPF, TRAP_TO_CPU, OSPF, false),
3487         MLXSW_SP_RXL_MARK(IPV6_OSPF, TRAP_TO_CPU, OSPF, false),
3488         MLXSW_SP_RXL_MARK(IPV6_DHCP, TRAP_TO_CPU, DHCP, false),
3489         MLXSW_SP_RXL_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
3490         MLXSW_SP_RXL_MARK(IPV4_BGP, TRAP_TO_CPU, BGP, false),
3491         MLXSW_SP_RXL_MARK(IPV6_BGP, TRAP_TO_CPU, BGP, false),
3492         MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3493                           false),
3494         MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3495                           false),
3496         MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3497                           false),
3498         MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3499                           false),
3500         MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6_ND, false),
3501         MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP,
3502                           false),
3503         MLXSW_SP_RXL_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, HOST_MISS, false),
3504         MLXSW_SP_RXL_MARK(HOST_MISS_IPV6, TRAP_TO_CPU, HOST_MISS, false),
3505         MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, ROUTER_EXP, false),
3506         MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, ROUTER_EXP, false),
3507         MLXSW_SP_RXL_MARK(IPIP_DECAP_ERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3508         MLXSW_SP_RXL_MARK(DECAP_ECN0, TRAP_TO_CPU, ROUTER_EXP, false),
3509         MLXSW_SP_RXL_MARK(IPV4_VRRP, TRAP_TO_CPU, ROUTER_EXP, false),
3510         MLXSW_SP_RXL_MARK(IPV6_VRRP, TRAP_TO_CPU, ROUTER_EXP, false),
3511         /* PKT Sample trap */
3512         MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
3513                   false, SP_IP2ME, DISCARD),
3514         /* ACL trap */
3515         MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false),
3516         /* Multicast Router Traps */
3517         MLXSW_SP_RXL_MARK(IPV4_PIM, TRAP_TO_CPU, PIM, false),
3518         MLXSW_SP_RXL_MARK(IPV6_PIM, TRAP_TO_CPU, PIM, false),
3519         MLXSW_SP_RXL_MARK(RPF, TRAP_TO_CPU, RPF, false),
3520         MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false),
3521         MLXSW_SP_RXL_MR_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false),
3522         /* NVE traps */
3523         MLXSW_SP_RXL_MARK(NVE_ENCAP_ARP, TRAP_TO_CPU, ARP, false),
3524 };
3525
3526 static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
3527 {
3528         char qpcr_pl[MLXSW_REG_QPCR_LEN];
3529         enum mlxsw_reg_qpcr_ir_units ir_units;
3530         int max_cpu_policers;
3531         bool is_bytes;
3532         u8 burst_size;
3533         u32 rate;
3534         int i, err;
3535
3536         if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
3537                 return -EIO;
3538
3539         max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
3540
3541         ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
3542         for (i = 0; i < max_cpu_policers; i++) {
3543                 is_bytes = false;
3544                 switch (i) {
3545                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3546                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3547                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3548                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
3549                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
3550                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
3551                         rate = 128;
3552                         burst_size = 7;
3553                         break;
3554                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3555                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
3556                         rate = 16 * 1024;
3557                         burst_size = 10;
3558                         break;
3559                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
3560                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3561                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3562                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
3563                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3564                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
3565                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
3566                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
3567                         rate = 1024;
3568                         burst_size = 7;
3569                         break;
3570                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3571                         is_bytes = true;
3572                         rate = 4 * 1024;
3573                         burst_size = 4;
3574                         break;
3575                 default:
3576                         continue;
3577                 }
3578
3579                 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
3580                                     burst_size);
3581                 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
3582                 if (err)
3583                         return err;
3584         }
3585
3586         return 0;
3587 }
3588
3589 static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
3590 {
3591         char htgt_pl[MLXSW_REG_HTGT_LEN];
3592         enum mlxsw_reg_htgt_trap_group i;
3593         int max_cpu_policers;
3594         int max_trap_groups;
3595         u8 priority, tc;
3596         u16 policer_id;
3597         int err;
3598
3599         if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
3600                 return -EIO;
3601
3602         max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
3603         max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
3604
3605         for (i = 0; i < max_trap_groups; i++) {
3606                 policer_id = i;
3607                 switch (i) {
3608                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3609                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3610                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3611                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
3612                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
3613                         priority = 5;
3614                         tc = 5;
3615                         break;
3616                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
3617                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3618                         priority = 4;
3619                         tc = 4;
3620                         break;
3621                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3622                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3623                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
3624                         priority = 3;
3625                         tc = 3;
3626                         break;
3627                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3628                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
3629                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
3630                         priority = 2;
3631                         tc = 2;
3632                         break;
3633                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
3634                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3635                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
3636                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
3637                         priority = 1;
3638                         tc = 1;
3639                         break;
3640                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
3641                         priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
3642                         tc = MLXSW_REG_HTGT_DEFAULT_TC;
3643                         policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
3644                         break;
3645                 default:
3646                         continue;
3647                 }
3648
3649                 if (max_cpu_policers <= policer_id &&
3650                     policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
3651                         return -EIO;
3652
3653                 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
3654                 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3655                 if (err)
3656                         return err;
3657         }
3658
3659         return 0;
3660 }
3661
3662 static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
3663 {
3664         int i;
3665         int err;
3666
3667         err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
3668         if (err)
3669                 return err;
3670
3671         err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
3672         if (err)
3673                 return err;
3674
3675         for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
3676                 err = mlxsw_core_trap_register(mlxsw_sp->core,
3677                                                &mlxsw_sp_listener[i],
3678                                                mlxsw_sp);
3679                 if (err)
3680                         goto err_listener_register;
3681
3682         }
3683         return 0;
3684
3685 err_listener_register:
3686         for (i--; i >= 0; i--) {
3687                 mlxsw_core_trap_unregister(mlxsw_sp->core,
3688                                            &mlxsw_sp_listener[i],
3689                                            mlxsw_sp);
3690         }
3691         return err;
3692 }
3693
3694 static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
3695 {
3696         int i;
3697
3698         for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
3699                 mlxsw_core_trap_unregister(mlxsw_sp->core,
3700                                            &mlxsw_sp_listener[i],
3701                                            mlxsw_sp);
3702         }
3703 }
3704
3705 static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
3706 {
3707         char slcr_pl[MLXSW_REG_SLCR_LEN];
3708         u32 seed;
3709         int err;
3710
3711         get_random_bytes(&seed, sizeof(seed));
3712         mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
3713                                      MLXSW_REG_SLCR_LAG_HASH_DMAC |
3714                                      MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
3715                                      MLXSW_REG_SLCR_LAG_HASH_VLANID |
3716                                      MLXSW_REG_SLCR_LAG_HASH_SIP |
3717                                      MLXSW_REG_SLCR_LAG_HASH_DIP |
3718                                      MLXSW_REG_SLCR_LAG_HASH_SPORT |
3719                                      MLXSW_REG_SLCR_LAG_HASH_DPORT |
3720                                      MLXSW_REG_SLCR_LAG_HASH_IPPROTO, seed);
3721         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
3722         if (err)
3723                 return err;
3724
3725         if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
3726             !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
3727                 return -EIO;
3728
3729         mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
3730                                  sizeof(struct mlxsw_sp_upper),
3731                                  GFP_KERNEL);
3732         if (!mlxsw_sp->lags)
3733                 return -ENOMEM;
3734
3735         return 0;
3736 }
3737
3738 static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
3739 {
3740         kfree(mlxsw_sp->lags);
3741 }
3742
3743 static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
3744 {
3745         char htgt_pl[MLXSW_REG_HTGT_LEN];
3746
3747         mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3748                             MLXSW_REG_HTGT_INVALID_POLICER,
3749                             MLXSW_REG_HTGT_DEFAULT_PRIORITY,
3750                             MLXSW_REG_HTGT_DEFAULT_TC);
3751         return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3752 }
3753
3754 static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
3755                                     unsigned long event, void *ptr);
3756
3757 static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
3758                          const struct mlxsw_bus_info *mlxsw_bus_info)
3759 {
3760         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3761         int err;
3762
3763         mlxsw_sp->core = mlxsw_core;
3764         mlxsw_sp->bus_info = mlxsw_bus_info;
3765
3766         err = mlxsw_sp_fw_rev_validate(mlxsw_sp);
3767         if (err)
3768                 return err;
3769
3770         err = mlxsw_sp_base_mac_get(mlxsw_sp);
3771         if (err) {
3772                 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
3773                 return err;
3774         }
3775
3776         err = mlxsw_sp_kvdl_init(mlxsw_sp);
3777         if (err) {
3778                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n");
3779                 return err;
3780         }
3781
3782         err = mlxsw_sp_fids_init(mlxsw_sp);
3783         if (err) {
3784                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
3785                 goto err_fids_init;
3786         }
3787
3788         err = mlxsw_sp_traps_init(mlxsw_sp);
3789         if (err) {
3790                 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
3791                 goto err_traps_init;
3792         }
3793
3794         err = mlxsw_sp_buffers_init(mlxsw_sp);
3795         if (err) {
3796                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
3797                 goto err_buffers_init;
3798         }
3799
3800         err = mlxsw_sp_lag_init(mlxsw_sp);
3801         if (err) {
3802                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
3803                 goto err_lag_init;
3804         }
3805
3806         /* Initialize SPAN before router and switchdev, so that those components
3807          * can call mlxsw_sp_span_respin().
3808          */
3809         err = mlxsw_sp_span_init(mlxsw_sp);
3810         if (err) {
3811                 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
3812                 goto err_span_init;
3813         }
3814
3815         err = mlxsw_sp_switchdev_init(mlxsw_sp);
3816         if (err) {
3817                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
3818                 goto err_switchdev_init;
3819         }
3820
3821         err = mlxsw_sp_counter_pool_init(mlxsw_sp);
3822         if (err) {
3823                 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
3824                 goto err_counter_pool_init;
3825         }
3826
3827         err = mlxsw_sp_afa_init(mlxsw_sp);
3828         if (err) {
3829                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n");
3830                 goto err_afa_init;
3831         }
3832
3833         err = mlxsw_sp_nve_init(mlxsw_sp);
3834         if (err) {
3835                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize NVE\n");
3836                 goto err_nve_init;
3837         }
3838
3839         err = mlxsw_sp_router_init(mlxsw_sp);
3840         if (err) {
3841                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
3842                 goto err_router_init;
3843         }
3844
3845         /* Initialize netdevice notifier after router and SPAN is initialized,
3846          * so that the event handler can use router structures and call SPAN
3847          * respin.
3848          */
3849         mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event;
3850         err = register_netdevice_notifier(&mlxsw_sp->netdevice_nb);
3851         if (err) {
3852                 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n");
3853                 goto err_netdev_notifier;
3854         }
3855
3856         err = mlxsw_sp_acl_init(mlxsw_sp);
3857         if (err) {
3858                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
3859                 goto err_acl_init;
3860         }
3861
3862         err = mlxsw_sp_dpipe_init(mlxsw_sp);
3863         if (err) {
3864                 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
3865                 goto err_dpipe_init;
3866         }
3867
3868         err = mlxsw_sp_ports_create(mlxsw_sp);
3869         if (err) {
3870                 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
3871                 goto err_ports_create;
3872         }
3873
3874         return 0;
3875
3876 err_ports_create:
3877         mlxsw_sp_dpipe_fini(mlxsw_sp);
3878 err_dpipe_init:
3879         mlxsw_sp_acl_fini(mlxsw_sp);
3880 err_acl_init:
3881         unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
3882 err_netdev_notifier:
3883         mlxsw_sp_router_fini(mlxsw_sp);
3884 err_router_init:
3885         mlxsw_sp_nve_fini(mlxsw_sp);
3886 err_nve_init:
3887         mlxsw_sp_afa_fini(mlxsw_sp);
3888 err_afa_init:
3889         mlxsw_sp_counter_pool_fini(mlxsw_sp);
3890 err_counter_pool_init:
3891         mlxsw_sp_switchdev_fini(mlxsw_sp);
3892 err_switchdev_init:
3893         mlxsw_sp_span_fini(mlxsw_sp);
3894 err_span_init:
3895         mlxsw_sp_lag_fini(mlxsw_sp);
3896 err_lag_init:
3897         mlxsw_sp_buffers_fini(mlxsw_sp);
3898 err_buffers_init:
3899         mlxsw_sp_traps_fini(mlxsw_sp);
3900 err_traps_init:
3901         mlxsw_sp_fids_fini(mlxsw_sp);
3902 err_fids_init:
3903         mlxsw_sp_kvdl_fini(mlxsw_sp);
3904         return err;
3905 }
3906
3907 static int mlxsw_sp1_init(struct mlxsw_core *mlxsw_core,
3908                           const struct mlxsw_bus_info *mlxsw_bus_info)
3909 {
3910         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3911
3912         mlxsw_sp->req_rev = &mlxsw_sp1_fw_rev;
3913         mlxsw_sp->fw_filename = MLXSW_SP1_FW_FILENAME;
3914         mlxsw_sp->kvdl_ops = &mlxsw_sp1_kvdl_ops;
3915         mlxsw_sp->afa_ops = &mlxsw_sp1_act_afa_ops;
3916         mlxsw_sp->afk_ops = &mlxsw_sp1_afk_ops;
3917         mlxsw_sp->mr_tcam_ops = &mlxsw_sp1_mr_tcam_ops;
3918         mlxsw_sp->acl_tcam_ops = &mlxsw_sp1_acl_tcam_ops;
3919         mlxsw_sp->nve_ops_arr = mlxsw_sp1_nve_ops_arr;
3920
3921         return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info);
3922 }
3923
3924 static int mlxsw_sp2_init(struct mlxsw_core *mlxsw_core,
3925                           const struct mlxsw_bus_info *mlxsw_bus_info)
3926 {
3927         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3928
3929         mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops;
3930         mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops;
3931         mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops;
3932         mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops;
3933         mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops;
3934         mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr;
3935
3936         return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info);
3937 }
3938
3939 static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
3940 {
3941         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3942
3943         mlxsw_sp_ports_remove(mlxsw_sp);
3944         mlxsw_sp_dpipe_fini(mlxsw_sp);
3945         mlxsw_sp_acl_fini(mlxsw_sp);
3946         unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
3947         mlxsw_sp_router_fini(mlxsw_sp);
3948         mlxsw_sp_nve_fini(mlxsw_sp);
3949         mlxsw_sp_afa_fini(mlxsw_sp);
3950         mlxsw_sp_counter_pool_fini(mlxsw_sp);
3951         mlxsw_sp_switchdev_fini(mlxsw_sp);
3952         mlxsw_sp_span_fini(mlxsw_sp);
3953         mlxsw_sp_lag_fini(mlxsw_sp);
3954         mlxsw_sp_buffers_fini(mlxsw_sp);
3955         mlxsw_sp_traps_fini(mlxsw_sp);
3956         mlxsw_sp_fids_fini(mlxsw_sp);
3957         mlxsw_sp_kvdl_fini(mlxsw_sp);
3958 }
3959
3960 static const struct mlxsw_config_profile mlxsw_sp1_config_profile = {
3961         .used_max_mid                   = 1,
3962         .max_mid                        = MLXSW_SP_MID_MAX,
3963         .used_flood_tables              = 1,
3964         .used_flood_mode                = 1,
3965         .flood_mode                     = 3,
3966         .max_fid_offset_flood_tables    = 3,
3967         .fid_offset_flood_table_size    = VLAN_N_VID - 1,
3968         .max_fid_flood_tables           = 3,
3969         .fid_flood_table_size           = MLXSW_SP_FID_8021D_MAX,
3970         .used_max_ib_mc                 = 1,
3971         .max_ib_mc                      = 0,
3972         .used_max_pkey                  = 1,
3973         .max_pkey                       = 0,
3974         .used_kvd_sizes                 = 1,
3975         .kvd_hash_single_parts          = 59,
3976         .kvd_hash_double_parts          = 41,
3977         .kvd_linear_size                = MLXSW_SP_KVD_LINEAR_SIZE,
3978         .swid_config                    = {
3979                 {
3980                         .used_type      = 1,
3981                         .type           = MLXSW_PORT_SWID_TYPE_ETH,
3982                 }
3983         },
3984 };
3985
3986 static const struct mlxsw_config_profile mlxsw_sp2_config_profile = {
3987         .used_max_mid                   = 1,
3988         .max_mid                        = MLXSW_SP_MID_MAX,
3989         .used_flood_tables              = 1,
3990         .used_flood_mode                = 1,
3991         .flood_mode                     = 3,
3992         .max_fid_offset_flood_tables    = 3,
3993         .fid_offset_flood_table_size    = VLAN_N_VID - 1,
3994         .max_fid_flood_tables           = 3,
3995         .fid_flood_table_size           = MLXSW_SP_FID_8021D_MAX,
3996         .used_max_ib_mc                 = 1,
3997         .max_ib_mc                      = 0,
3998         .used_max_pkey                  = 1,
3999         .max_pkey                       = 0,
4000         .swid_config                    = {
4001                 {
4002                         .used_type      = 1,
4003                         .type           = MLXSW_PORT_SWID_TYPE_ETH,
4004                 }
4005         },
4006 };
4007
4008 static void
4009 mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core,
4010                                       struct devlink_resource_size_params *kvd_size_params,
4011                                       struct devlink_resource_size_params *linear_size_params,
4012                                       struct devlink_resource_size_params *hash_double_size_params,
4013                                       struct devlink_resource_size_params *hash_single_size_params)
4014 {
4015         u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
4016                                                  KVD_SINGLE_MIN_SIZE);
4017         u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
4018                                                  KVD_DOUBLE_MIN_SIZE);
4019         u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
4020         u32 linear_size_min = 0;
4021
4022         devlink_resource_size_params_init(kvd_size_params, kvd_size, kvd_size,
4023                                           MLXSW_SP_KVD_GRANULARITY,
4024                                           DEVLINK_RESOURCE_UNIT_ENTRY);
4025         devlink_resource_size_params_init(linear_size_params, linear_size_min,
4026                                           kvd_size - single_size_min -
4027                                           double_size_min,
4028                                           MLXSW_SP_KVD_GRANULARITY,
4029                                           DEVLINK_RESOURCE_UNIT_ENTRY);
4030         devlink_resource_size_params_init(hash_double_size_params,
4031                                           double_size_min,
4032                                           kvd_size - single_size_min -
4033                                           linear_size_min,
4034                                           MLXSW_SP_KVD_GRANULARITY,
4035                                           DEVLINK_RESOURCE_UNIT_ENTRY);
4036         devlink_resource_size_params_init(hash_single_size_params,
4037                                           single_size_min,
4038                                           kvd_size - double_size_min -
4039                                           linear_size_min,
4040                                           MLXSW_SP_KVD_GRANULARITY,
4041                                           DEVLINK_RESOURCE_UNIT_ENTRY);
4042 }
4043
4044 static int mlxsw_sp1_resources_kvd_register(struct mlxsw_core *mlxsw_core)
4045 {
4046         struct devlink *devlink = priv_to_devlink(mlxsw_core);
4047         struct devlink_resource_size_params hash_single_size_params;
4048         struct devlink_resource_size_params hash_double_size_params;
4049         struct devlink_resource_size_params linear_size_params;
4050         struct devlink_resource_size_params kvd_size_params;
4051         u32 kvd_size, single_size, double_size, linear_size;
4052         const struct mlxsw_config_profile *profile;
4053         int err;
4054
4055         profile = &mlxsw_sp1_config_profile;
4056         if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
4057                 return -EIO;
4058
4059         mlxsw_sp_resource_size_params_prepare(mlxsw_core, &kvd_size_params,
4060                                               &linear_size_params,
4061                                               &hash_double_size_params,
4062                                               &hash_single_size_params);
4063
4064         kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
4065         err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
4066                                         kvd_size, MLXSW_SP_RESOURCE_KVD,
4067                                         DEVLINK_RESOURCE_ID_PARENT_TOP,
4068                                         &kvd_size_params);
4069         if (err)
4070                 return err;
4071
4072         linear_size = profile->kvd_linear_size;
4073         err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR,
4074                                         linear_size,
4075                                         MLXSW_SP_RESOURCE_KVD_LINEAR,
4076                                         MLXSW_SP_RESOURCE_KVD,
4077                                         &linear_size_params);
4078         if (err)
4079                 return err;
4080
4081         err = mlxsw_sp1_kvdl_resources_register(mlxsw_core);
4082         if  (err)
4083                 return err;
4084
4085         double_size = kvd_size - linear_size;
4086         double_size *= profile->kvd_hash_double_parts;
4087         double_size /= profile->kvd_hash_double_parts +
4088                        profile->kvd_hash_single_parts;
4089         double_size = rounddown(double_size, MLXSW_SP_KVD_GRANULARITY);
4090         err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE,
4091                                         double_size,
4092                                         MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
4093                                         MLXSW_SP_RESOURCE_KVD,
4094                                         &hash_double_size_params);
4095         if (err)
4096                 return err;
4097
4098         single_size = kvd_size - double_size - linear_size;
4099         err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE,
4100                                         single_size,
4101                                         MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
4102                                         MLXSW_SP_RESOURCE_KVD,
4103                                         &hash_single_size_params);
4104         if (err)
4105                 return err;
4106
4107         return 0;
4108 }
4109
4110 static int mlxsw_sp1_resources_register(struct mlxsw_core *mlxsw_core)
4111 {
4112         return mlxsw_sp1_resources_kvd_register(mlxsw_core);
4113 }
4114
4115 static int mlxsw_sp2_resources_register(struct mlxsw_core *mlxsw_core)
4116 {
4117         return 0;
4118 }
4119
4120 static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core,
4121                                   const struct mlxsw_config_profile *profile,
4122                                   u64 *p_single_size, u64 *p_double_size,
4123                                   u64 *p_linear_size)
4124 {
4125         struct devlink *devlink = priv_to_devlink(mlxsw_core);
4126         u32 double_size;
4127         int err;
4128
4129         if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
4130             !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE))
4131                 return -EIO;
4132
4133         /* The hash part is what left of the kvd without the
4134          * linear part. It is split to the single size and
4135          * double size by the parts ratio from the profile.
4136          * Both sizes must be a multiplications of the
4137          * granularity from the profile. In case the user
4138          * provided the sizes they are obtained via devlink.
4139          */
4140         err = devlink_resource_size_get(devlink,
4141                                         MLXSW_SP_RESOURCE_KVD_LINEAR,
4142                                         p_linear_size);
4143         if (err)
4144                 *p_linear_size = profile->kvd_linear_size;
4145
4146         err = devlink_resource_size_get(devlink,
4147                                         MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
4148                                         p_double_size);
4149         if (err) {
4150                 double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
4151                               *p_linear_size;
4152                 double_size *= profile->kvd_hash_double_parts;
4153                 double_size /= profile->kvd_hash_double_parts +
4154                                profile->kvd_hash_single_parts;
4155                 *p_double_size = rounddown(double_size,
4156                                            MLXSW_SP_KVD_GRANULARITY);
4157         }
4158
4159         err = devlink_resource_size_get(devlink,
4160                                         MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
4161                                         p_single_size);
4162         if (err)
4163                 *p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
4164                                  *p_double_size - *p_linear_size;
4165
4166         /* Check results are legal. */
4167         if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
4168             *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
4169             MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size)
4170                 return -EIO;
4171
4172         return 0;
4173 }
4174
4175 static struct mlxsw_driver mlxsw_sp1_driver = {
4176         .kind                           = mlxsw_sp1_driver_name,
4177         .priv_size                      = sizeof(struct mlxsw_sp),
4178         .init                           = mlxsw_sp1_init,
4179         .fini                           = mlxsw_sp_fini,
4180         .basic_trap_groups_set          = mlxsw_sp_basic_trap_groups_set,
4181         .port_split                     = mlxsw_sp_port_split,
4182         .port_unsplit                   = mlxsw_sp_port_unsplit,
4183         .sb_pool_get                    = mlxsw_sp_sb_pool_get,
4184         .sb_pool_set                    = mlxsw_sp_sb_pool_set,
4185         .sb_port_pool_get               = mlxsw_sp_sb_port_pool_get,
4186         .sb_port_pool_set               = mlxsw_sp_sb_port_pool_set,
4187         .sb_tc_pool_bind_get            = mlxsw_sp_sb_tc_pool_bind_get,
4188         .sb_tc_pool_bind_set            = mlxsw_sp_sb_tc_pool_bind_set,
4189         .sb_occ_snapshot                = mlxsw_sp_sb_occ_snapshot,
4190         .sb_occ_max_clear               = mlxsw_sp_sb_occ_max_clear,
4191         .sb_occ_port_pool_get           = mlxsw_sp_sb_occ_port_pool_get,
4192         .sb_occ_tc_port_bind_get        = mlxsw_sp_sb_occ_tc_port_bind_get,
4193         .txhdr_construct                = mlxsw_sp_txhdr_construct,
4194         .resources_register             = mlxsw_sp1_resources_register,
4195         .kvd_sizes_get                  = mlxsw_sp_kvd_sizes_get,
4196         .txhdr_len                      = MLXSW_TXHDR_LEN,
4197         .profile                        = &mlxsw_sp1_config_profile,
4198         .res_query_enabled              = true,
4199 };
4200
4201 static struct mlxsw_driver mlxsw_sp2_driver = {
4202         .kind                           = mlxsw_sp2_driver_name,
4203         .priv_size                      = sizeof(struct mlxsw_sp),
4204         .init                           = mlxsw_sp2_init,
4205         .fini                           = mlxsw_sp_fini,
4206         .basic_trap_groups_set          = mlxsw_sp_basic_trap_groups_set,
4207         .port_split                     = mlxsw_sp_port_split,
4208         .port_unsplit                   = mlxsw_sp_port_unsplit,
4209         .sb_pool_get                    = mlxsw_sp_sb_pool_get,
4210         .sb_pool_set                    = mlxsw_sp_sb_pool_set,
4211         .sb_port_pool_get               = mlxsw_sp_sb_port_pool_get,
4212         .sb_port_pool_set               = mlxsw_sp_sb_port_pool_set,
4213         .sb_tc_pool_bind_get            = mlxsw_sp_sb_tc_pool_bind_get,
4214         .sb_tc_pool_bind_set            = mlxsw_sp_sb_tc_pool_bind_set,
4215         .sb_occ_snapshot                = mlxsw_sp_sb_occ_snapshot,
4216         .sb_occ_max_clear               = mlxsw_sp_sb_occ_max_clear,
4217         .sb_occ_port_pool_get           = mlxsw_sp_sb_occ_port_pool_get,
4218         .sb_occ_tc_port_bind_get        = mlxsw_sp_sb_occ_tc_port_bind_get,
4219         .txhdr_construct                = mlxsw_sp_txhdr_construct,
4220         .resources_register             = mlxsw_sp2_resources_register,
4221         .txhdr_len                      = MLXSW_TXHDR_LEN,
4222         .profile                        = &mlxsw_sp2_config_profile,
4223         .res_query_enabled              = true,
4224 };
4225
4226 bool mlxsw_sp_port_dev_check(const struct net_device *dev)
4227 {
4228         return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
4229 }
4230
4231 static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
4232 {
4233         struct mlxsw_sp_port **p_mlxsw_sp_port = data;
4234         int ret = 0;
4235
4236         if (mlxsw_sp_port_dev_check(lower_dev)) {
4237                 *p_mlxsw_sp_port = netdev_priv(lower_dev);
4238                 ret = 1;
4239         }
4240
4241         return ret;
4242 }
4243
4244 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
4245 {
4246         struct mlxsw_sp_port *mlxsw_sp_port;
4247
4248         if (mlxsw_sp_port_dev_check(dev))
4249                 return netdev_priv(dev);
4250
4251         mlxsw_sp_port = NULL;
4252         netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
4253
4254         return mlxsw_sp_port;
4255 }
4256
4257 struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
4258 {
4259         struct mlxsw_sp_port *mlxsw_sp_port;
4260
4261         mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
4262         return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
4263 }
4264
4265 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
4266 {
4267         struct mlxsw_sp_port *mlxsw_sp_port;
4268
4269         if (mlxsw_sp_port_dev_check(dev))
4270                 return netdev_priv(dev);
4271
4272         mlxsw_sp_port = NULL;
4273         netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
4274                                       &mlxsw_sp_port);
4275
4276         return mlxsw_sp_port;
4277 }
4278
4279 struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
4280 {
4281         struct mlxsw_sp_port *mlxsw_sp_port;
4282
4283         rcu_read_lock();
4284         mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
4285         if (mlxsw_sp_port)
4286                 dev_hold(mlxsw_sp_port->dev);
4287         rcu_read_unlock();
4288         return mlxsw_sp_port;
4289 }
4290
4291 void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
4292 {
4293         dev_put(mlxsw_sp_port->dev);
4294 }
4295
4296 static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
4297 {
4298         char sldr_pl[MLXSW_REG_SLDR_LEN];
4299
4300         mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
4301         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4302 }
4303
4304 static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
4305 {
4306         char sldr_pl[MLXSW_REG_SLDR_LEN];
4307
4308         mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
4309         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4310 }
4311
4312 static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4313                                      u16 lag_id, u8 port_index)
4314 {
4315         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4316         char slcor_pl[MLXSW_REG_SLCOR_LEN];
4317
4318         mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
4319                                       lag_id, port_index);
4320         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4321 }
4322
4323 static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4324                                         u16 lag_id)
4325 {
4326         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4327         char slcor_pl[MLXSW_REG_SLCOR_LEN];
4328
4329         mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
4330                                          lag_id);
4331         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4332 }
4333
4334 static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
4335                                         u16 lag_id)
4336 {
4337         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4338         char slcor_pl[MLXSW_REG_SLCOR_LEN];
4339
4340         mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
4341                                         lag_id);
4342         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4343 }
4344
4345 static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
4346                                          u16 lag_id)
4347 {
4348         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4349         char slcor_pl[MLXSW_REG_SLCOR_LEN];
4350
4351         mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
4352                                          lag_id);
4353         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4354 }
4355
4356 static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4357                                   struct net_device *lag_dev,
4358                                   u16 *p_lag_id)
4359 {
4360         struct mlxsw_sp_upper *lag;
4361         int free_lag_id = -1;
4362         u64 max_lag;
4363         int i;
4364
4365         max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
4366         for (i = 0; i < max_lag; i++) {
4367                 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
4368                 if (lag->ref_count) {
4369                         if (lag->dev == lag_dev) {
4370                                 *p_lag_id = i;
4371                                 return 0;
4372                         }
4373                 } else if (free_lag_id < 0) {
4374                         free_lag_id = i;
4375                 }
4376         }
4377         if (free_lag_id < 0)
4378                 return -EBUSY;
4379         *p_lag_id = free_lag_id;
4380         return 0;
4381 }
4382
4383 static bool
4384 mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
4385                           struct net_device *lag_dev,
4386                           struct netdev_lag_upper_info *lag_upper_info,
4387                           struct netlink_ext_ack *extack)
4388 {
4389         u16 lag_id;
4390
4391         if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) {
4392                 NL_SET_ERR_MSG_MOD(extack, "Exceeded number of supported LAG devices");
4393                 return false;
4394         }
4395         if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
4396                 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type");
4397                 return false;
4398         }
4399         return true;
4400 }
4401
4402 static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4403                                        u16 lag_id, u8 *p_port_index)
4404 {
4405         u64 max_lag_members;
4406         int i;
4407
4408         max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
4409                                              MAX_LAG_MEMBERS);
4410         for (i = 0; i < max_lag_members; i++) {
4411                 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
4412                         *p_port_index = i;
4413                         return 0;
4414                 }
4415         }
4416         return -EBUSY;
4417 }
4418
4419 static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
4420                                   struct net_device *lag_dev)
4421 {
4422         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4423         struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
4424         struct mlxsw_sp_upper *lag;
4425         u16 lag_id;
4426         u8 port_index;
4427         int err;
4428
4429         err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
4430         if (err)
4431                 return err;
4432         lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4433         if (!lag->ref_count) {
4434                 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
4435                 if (err)
4436                         return err;
4437                 lag->dev = lag_dev;
4438         }
4439
4440         err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
4441         if (err)
4442                 return err;
4443         err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
4444         if (err)
4445                 goto err_col_port_add;
4446         err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
4447         if (err)
4448                 goto err_col_port_enable;
4449
4450         mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
4451                                    mlxsw_sp_port->local_port);
4452         mlxsw_sp_port->lag_id = lag_id;
4453         mlxsw_sp_port->lagged = 1;
4454         lag->ref_count++;
4455
4456         /* Port is no longer usable as a router interface */
4457         mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, 1);
4458         if (mlxsw_sp_port_vlan->fid)
4459                 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
4460
4461         return 0;
4462
4463 err_col_port_enable:
4464         mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
4465 err_col_port_add:
4466         if (!lag->ref_count)
4467                 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
4468         return err;
4469 }
4470
4471 static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
4472                                     struct net_device *lag_dev)
4473 {
4474         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4475         u16 lag_id = mlxsw_sp_port->lag_id;
4476         struct mlxsw_sp_upper *lag;
4477
4478         if (!mlxsw_sp_port->lagged)
4479                 return;
4480         lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4481         WARN_ON(lag->ref_count == 0);
4482
4483         mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
4484         mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
4485
4486         /* Any VLANs configured on the port are no longer valid */
4487         mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
4488
4489         if (lag->ref_count == 1)
4490                 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
4491
4492         mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4493                                      mlxsw_sp_port->local_port);
4494         mlxsw_sp_port->lagged = 0;
4495         lag->ref_count--;
4496
4497         mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
4498         /* Make sure untagged frames are allowed to ingress */
4499         mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
4500 }
4501
4502 static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4503                                       u16 lag_id)
4504 {
4505         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4506         char sldr_pl[MLXSW_REG_SLDR_LEN];
4507
4508         mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
4509                                          mlxsw_sp_port->local_port);
4510         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4511 }
4512
4513 static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4514                                          u16 lag_id)
4515 {
4516         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4517         char sldr_pl[MLXSW_REG_SLDR_LEN];
4518
4519         mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
4520                                             mlxsw_sp_port->local_port);
4521         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4522 }
4523
4524 static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
4525                                        bool lag_tx_enabled)
4526 {
4527         if (lag_tx_enabled)
4528                 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
4529                                                   mlxsw_sp_port->lag_id);
4530         else
4531                 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
4532                                                      mlxsw_sp_port->lag_id);
4533 }
4534
4535 static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
4536                                      struct netdev_lag_lower_state_info *info)
4537 {
4538         return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
4539 }
4540
4541 static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
4542                                  bool enable)
4543 {
4544         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4545         enum mlxsw_reg_spms_state spms_state;
4546         char *spms_pl;
4547         u16 vid;
4548         int err;
4549
4550         spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
4551                               MLXSW_REG_SPMS_STATE_DISCARDING;
4552
4553         spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
4554         if (!spms_pl)
4555                 return -ENOMEM;
4556         mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
4557
4558         for (vid = 0; vid < VLAN_N_VID; vid++)
4559                 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
4560
4561         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
4562         kfree(spms_pl);
4563         return err;
4564 }
4565
4566 static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
4567 {
4568         u16 vid = 1;
4569         int err;
4570
4571         err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
4572         if (err)
4573                 return err;
4574         err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
4575         if (err)
4576                 goto err_port_stp_set;
4577         err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4578                                      true, false);
4579         if (err)
4580                 goto err_port_vlan_set;
4581
4582         for (; vid <= VLAN_N_VID - 1; vid++) {
4583                 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4584                                                      vid, false);
4585                 if (err)
4586                         goto err_vid_learning_set;
4587         }
4588
4589         return 0;
4590
4591 err_vid_learning_set:
4592         for (vid--; vid >= 1; vid--)
4593                 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true);
4594 err_port_vlan_set:
4595         mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
4596 err_port_stp_set:
4597         mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
4598         return err;
4599 }
4600
4601 static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4602 {
4603         u16 vid;
4604
4605         for (vid = VLAN_N_VID - 1; vid >= 1; vid--)
4606                 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4607                                                vid, true);
4608
4609         mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4610                                false, false);
4611         mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
4612         mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
4613 }
4614
4615 static bool mlxsw_sp_bridge_has_multiple_vxlans(struct net_device *br_dev)
4616 {
4617         unsigned int num_vxlans = 0;
4618         struct net_device *dev;
4619         struct list_head *iter;
4620
4621         netdev_for_each_lower_dev(br_dev, dev, iter) {
4622                 if (netif_is_vxlan(dev))
4623                         num_vxlans++;
4624         }
4625
4626         return num_vxlans > 1;
4627 }
4628
4629 static bool mlxsw_sp_bridge_vxlan_is_valid(struct net_device *br_dev,
4630                                            struct netlink_ext_ack *extack)
4631 {
4632         if (br_multicast_enabled(br_dev)) {
4633                 NL_SET_ERR_MSG_MOD(extack, "Multicast can not be enabled on a bridge with a VxLAN device");
4634                 return false;
4635         }
4636
4637         if (br_vlan_enabled(br_dev)) {
4638                 NL_SET_ERR_MSG_MOD(extack, "VLAN filtering can not be enabled on a bridge with a VxLAN device");
4639                 return false;
4640         }
4641
4642         if (mlxsw_sp_bridge_has_multiple_vxlans(br_dev)) {
4643                 NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices are not supported in a VLAN-unaware bridge");
4644                 return false;
4645         }
4646
4647         return true;
4648 }
4649
4650 static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
4651                                                struct net_device *dev,
4652                                                unsigned long event, void *ptr)
4653 {
4654         struct netdev_notifier_changeupper_info *info;
4655         struct mlxsw_sp_port *mlxsw_sp_port;
4656         struct netlink_ext_ack *extack;
4657         struct net_device *upper_dev;
4658         struct mlxsw_sp *mlxsw_sp;
4659         int err = 0;
4660
4661         mlxsw_sp_port = netdev_priv(dev);
4662         mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4663         info = ptr;
4664         extack = netdev_notifier_info_to_extack(&info->info);
4665
4666         switch (event) {
4667         case NETDEV_PRECHANGEUPPER:
4668                 upper_dev = info->upper_dev;
4669                 if (!is_vlan_dev(upper_dev) &&
4670                     !netif_is_lag_master(upper_dev) &&
4671                     !netif_is_bridge_master(upper_dev) &&
4672                     !netif_is_ovs_master(upper_dev) &&
4673                     !netif_is_macvlan(upper_dev)) {
4674                         NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
4675                         return -EINVAL;
4676                 }
4677                 if (!info->linking)
4678                         break;
4679                 if (netif_is_bridge_master(upper_dev) &&
4680                     !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) &&
4681                     mlxsw_sp_bridge_has_vxlan(upper_dev) &&
4682                     !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
4683                         return -EOPNOTSUPP;
4684                 if (netdev_has_any_upper_dev(upper_dev) &&
4685                     (!netif_is_bridge_master(upper_dev) ||
4686                      !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4687                                                           upper_dev))) {
4688                         NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
4689                         return -EINVAL;
4690                 }
4691                 if (netif_is_lag_master(upper_dev) &&
4692                     !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
4693                                                info->upper_info, extack))
4694                         return -EINVAL;
4695                 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) {
4696                         NL_SET_ERR_MSG_MOD(extack, "Master device is a LAG master and this device has a VLAN");
4697                         return -EINVAL;
4698                 }
4699                 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
4700                     !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) {
4701                         NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on a LAG port");
4702                         return -EINVAL;
4703                 }
4704                 if (netif_is_macvlan(upper_dev) &&
4705                     !mlxsw_sp_rif_find_by_dev(mlxsw_sp, lower_dev)) {
4706                         NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
4707                         return -EOPNOTSUPP;
4708                 }
4709                 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) {
4710                         NL_SET_ERR_MSG_MOD(extack, "Master device is an OVS master and this device has a VLAN");
4711                         return -EINVAL;
4712                 }
4713                 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) {
4714                         NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on an OVS port");
4715                         return -EINVAL;
4716                 }
4717                 if (is_vlan_dev(upper_dev) &&
4718                     vlan_dev_vlan_id(upper_dev) == 1) {
4719                         NL_SET_ERR_MSG_MOD(extack, "Creating a VLAN device with VID 1 is unsupported: VLAN 1 carries untagged traffic");
4720                         return -EINVAL;
4721                 }
4722                 break;
4723         case NETDEV_CHANGEUPPER:
4724                 upper_dev = info->upper_dev;
4725                 if (netif_is_bridge_master(upper_dev)) {
4726                         if (info->linking)
4727                                 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4728                                                                 lower_dev,
4729                                                                 upper_dev,
4730                                                                 extack);
4731                         else
4732                                 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4733                                                            lower_dev,
4734                                                            upper_dev);
4735                 } else if (netif_is_lag_master(upper_dev)) {
4736                         if (info->linking)
4737                                 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
4738                                                              upper_dev);
4739                         else
4740                                 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
4741                                                         upper_dev);
4742                 } else if (netif_is_ovs_master(upper_dev)) {
4743                         if (info->linking)
4744                                 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
4745                         else
4746                                 mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
4747                 } else if (netif_is_macvlan(upper_dev)) {
4748                         if (!info->linking)
4749                                 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
4750                 }
4751                 break;
4752         }
4753
4754         return err;
4755 }
4756
4757 static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
4758                                                unsigned long event, void *ptr)
4759 {
4760         struct netdev_notifier_changelowerstate_info *info;
4761         struct mlxsw_sp_port *mlxsw_sp_port;
4762         int err;
4763
4764         mlxsw_sp_port = netdev_priv(dev);
4765         info = ptr;
4766
4767         switch (event) {
4768         case NETDEV_CHANGELOWERSTATE:
4769                 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
4770                         err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
4771                                                         info->lower_state_info);
4772                         if (err)
4773                                 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
4774                 }
4775                 break;
4776         }
4777
4778         return 0;
4779 }
4780
4781 static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
4782                                          struct net_device *port_dev,
4783                                          unsigned long event, void *ptr)
4784 {
4785         switch (event) {
4786         case NETDEV_PRECHANGEUPPER:
4787         case NETDEV_CHANGEUPPER:
4788                 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
4789                                                            event, ptr);
4790         case NETDEV_CHANGELOWERSTATE:
4791                 return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
4792                                                            ptr);
4793         }
4794
4795         return 0;
4796 }
4797
4798 static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
4799                                         unsigned long event, void *ptr)
4800 {
4801         struct net_device *dev;
4802         struct list_head *iter;
4803         int ret;
4804
4805         netdev_for_each_lower_dev(lag_dev, dev, iter) {
4806                 if (mlxsw_sp_port_dev_check(dev)) {
4807                         ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
4808                                                             ptr);
4809                         if (ret)
4810                                 return ret;
4811                 }
4812         }
4813
4814         return 0;
4815 }
4816
4817 static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
4818                                               struct net_device *dev,
4819                                               unsigned long event, void *ptr,
4820                                               u16 vid)
4821 {
4822         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
4823         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4824         struct netdev_notifier_changeupper_info *info = ptr;
4825         struct netlink_ext_ack *extack;
4826         struct net_device *upper_dev;
4827         int err = 0;
4828
4829         extack = netdev_notifier_info_to_extack(&info->info);
4830
4831         switch (event) {
4832         case NETDEV_PRECHANGEUPPER:
4833                 upper_dev = info->upper_dev;
4834                 if (!netif_is_bridge_master(upper_dev) &&
4835                     !netif_is_macvlan(upper_dev)) {
4836                         NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
4837                         return -EINVAL;
4838                 }
4839                 if (!info->linking)
4840                         break;
4841                 if (netif_is_bridge_master(upper_dev) &&
4842                     !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) &&
4843                     mlxsw_sp_bridge_has_vxlan(upper_dev) &&
4844                     !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
4845                         return -EOPNOTSUPP;
4846                 if (netdev_has_any_upper_dev(upper_dev) &&
4847                     (!netif_is_bridge_master(upper_dev) ||
4848                      !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4849                                                           upper_dev))) {
4850                         NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
4851                         return -EINVAL;
4852                 }
4853                 if (netif_is_macvlan(upper_dev) &&
4854                     !mlxsw_sp_rif_find_by_dev(mlxsw_sp, vlan_dev)) {
4855                         NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
4856                         return -EOPNOTSUPP;
4857                 }
4858                 break;
4859         case NETDEV_CHANGEUPPER:
4860                 upper_dev = info->upper_dev;
4861                 if (netif_is_bridge_master(upper_dev)) {
4862                         if (info->linking)
4863                                 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4864                                                                 vlan_dev,
4865                                                                 upper_dev,
4866                                                                 extack);
4867                         else
4868                                 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4869                                                            vlan_dev,
4870                                                            upper_dev);
4871                 } else if (netif_is_macvlan(upper_dev)) {
4872                         if (!info->linking)
4873                                 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
4874                 } else {
4875                         err = -EINVAL;
4876                         WARN_ON(1);
4877                 }
4878                 break;
4879         }
4880
4881         return err;
4882 }
4883
4884 static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
4885                                                   struct net_device *lag_dev,
4886                                                   unsigned long event,
4887                                                   void *ptr, u16 vid)
4888 {
4889         struct net_device *dev;
4890         struct list_head *iter;
4891         int ret;
4892
4893         netdev_for_each_lower_dev(lag_dev, dev, iter) {
4894                 if (mlxsw_sp_port_dev_check(dev)) {
4895                         ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
4896                                                                  event, ptr,
4897                                                                  vid);
4898                         if (ret)
4899                                 return ret;
4900                 }
4901         }
4902
4903         return 0;
4904 }
4905
4906 static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
4907                                          unsigned long event, void *ptr)
4908 {
4909         struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
4910         u16 vid = vlan_dev_vlan_id(vlan_dev);
4911
4912         if (mlxsw_sp_port_dev_check(real_dev))
4913                 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
4914                                                           event, ptr, vid);
4915         else if (netif_is_lag_master(real_dev))
4916                 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
4917                                                               real_dev, event,
4918                                                               ptr, vid);
4919
4920         return 0;
4921 }
4922
4923 static int mlxsw_sp_netdevice_bridge_event(struct net_device *br_dev,
4924                                            unsigned long event, void *ptr)
4925 {
4926         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(br_dev);
4927         struct netdev_notifier_changeupper_info *info = ptr;
4928         struct netlink_ext_ack *extack;
4929         struct net_device *upper_dev;
4930
4931         if (!mlxsw_sp)
4932                 return 0;
4933
4934         extack = netdev_notifier_info_to_extack(&info->info);
4935
4936         switch (event) {
4937         case NETDEV_PRECHANGEUPPER:
4938                 upper_dev = info->upper_dev;
4939                 if (!is_vlan_dev(upper_dev) && !netif_is_macvlan(upper_dev)) {
4940                         NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
4941                         return -EOPNOTSUPP;
4942                 }
4943                 if (!info->linking)
4944                         break;
4945                 if (netif_is_macvlan(upper_dev) &&
4946                     !mlxsw_sp_rif_find_by_dev(mlxsw_sp, br_dev)) {
4947                         NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
4948                         return -EOPNOTSUPP;
4949                 }
4950                 break;
4951         case NETDEV_CHANGEUPPER:
4952                 upper_dev = info->upper_dev;
4953                 if (info->linking)
4954                         break;
4955                 if (is_vlan_dev(upper_dev))
4956                         mlxsw_sp_rif_destroy_by_dev(mlxsw_sp, upper_dev);
4957                 if (netif_is_macvlan(upper_dev))
4958                         mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
4959                 break;
4960         }
4961
4962         return 0;
4963 }
4964
4965 static int mlxsw_sp_netdevice_macvlan_event(struct net_device *macvlan_dev,
4966                                             unsigned long event, void *ptr)
4967 {
4968         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(macvlan_dev);
4969         struct netdev_notifier_changeupper_info *info = ptr;
4970         struct netlink_ext_ack *extack;
4971
4972         if (!mlxsw_sp || event != NETDEV_PRECHANGEUPPER)
4973                 return 0;
4974
4975         extack = netdev_notifier_info_to_extack(&info->info);
4976
4977         /* VRF enslavement is handled in mlxsw_sp_netdevice_vrf_event() */
4978         NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
4979
4980         return -EOPNOTSUPP;
4981 }
4982
4983 static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
4984 {
4985         struct netdev_notifier_changeupper_info *info = ptr;
4986
4987         if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
4988                 return false;
4989         return netif_is_l3_master(info->upper_dev);
4990 }
4991
4992 static int mlxsw_sp_netdevice_vxlan_event(struct mlxsw_sp *mlxsw_sp,
4993                                           struct net_device *dev,
4994                                           unsigned long event, void *ptr)
4995 {
4996         struct netdev_notifier_changeupper_info *cu_info;
4997         struct netdev_notifier_info *info = ptr;
4998         struct netlink_ext_ack *extack;
4999         struct net_device *upper_dev;
5000
5001         extack = netdev_notifier_info_to_extack(info);
5002
5003         switch (event) {
5004         case NETDEV_CHANGEUPPER:
5005                 cu_info = container_of(info,
5006                                        struct netdev_notifier_changeupper_info,
5007                                        info);
5008                 upper_dev = cu_info->upper_dev;
5009                 if (!netif_is_bridge_master(upper_dev))
5010                         return 0;
5011                 if (!mlxsw_sp_lower_get(upper_dev))
5012                         return 0;
5013                 if (!mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
5014                         return -EOPNOTSUPP;
5015                 if (cu_info->linking) {
5016                         if (!netif_running(dev))
5017                                 return 0;
5018                         return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev,
5019                                                           dev, extack);
5020                 } else {
5021                         mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, upper_dev, dev);
5022                 }
5023                 break;
5024         case NETDEV_PRE_UP:
5025                 upper_dev = netdev_master_upper_dev_get(dev);
5026                 if (!upper_dev)
5027                         return 0;
5028                 if (!netif_is_bridge_master(upper_dev))
5029                         return 0;
5030                 if (!mlxsw_sp_lower_get(upper_dev))
5031                         return 0;
5032                 return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev, dev,
5033                                                   extack);
5034         case NETDEV_DOWN:
5035                 upper_dev = netdev_master_upper_dev_get(dev);
5036                 if (!upper_dev)
5037                         return 0;
5038                 if (!netif_is_bridge_master(upper_dev))
5039                         return 0;
5040                 if (!mlxsw_sp_lower_get(upper_dev))
5041                         return 0;
5042                 mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, upper_dev, dev);
5043                 break;
5044         }
5045
5046         return 0;
5047 }
5048
5049 static int mlxsw_sp_netdevice_event(struct notifier_block *nb,
5050                                     unsigned long event, void *ptr)
5051 {
5052         struct net_device *dev = netdev_notifier_info_to_dev(ptr);
5053         struct mlxsw_sp_span_entry *span_entry;
5054         struct mlxsw_sp *mlxsw_sp;
5055         int err = 0;
5056
5057         mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb);
5058         if (event == NETDEV_UNREGISTER) {
5059                 span_entry = mlxsw_sp_span_entry_find_by_port(mlxsw_sp, dev);
5060                 if (span_entry)
5061                         mlxsw_sp_span_entry_invalidate(mlxsw_sp, span_entry);
5062         }
5063         mlxsw_sp_span_respin(mlxsw_sp);
5064
5065         if (netif_is_vxlan(dev))
5066                 err = mlxsw_sp_netdevice_vxlan_event(mlxsw_sp, dev, event, ptr);
5067         if (mlxsw_sp_netdev_is_ipip_ol(mlxsw_sp, dev))
5068                 err = mlxsw_sp_netdevice_ipip_ol_event(mlxsw_sp, dev,
5069                                                        event, ptr);
5070         else if (mlxsw_sp_netdev_is_ipip_ul(mlxsw_sp, dev))
5071                 err = mlxsw_sp_netdevice_ipip_ul_event(mlxsw_sp, dev,
5072                                                        event, ptr);
5073         else if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
5074                 err = mlxsw_sp_netdevice_router_port_event(dev);
5075         else if (mlxsw_sp_is_vrf_event(event, ptr))
5076                 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
5077         else if (mlxsw_sp_port_dev_check(dev))
5078                 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr);
5079         else if (netif_is_lag_master(dev))
5080                 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
5081         else if (is_vlan_dev(dev))
5082                 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
5083         else if (netif_is_bridge_master(dev))
5084                 err = mlxsw_sp_netdevice_bridge_event(dev, event, ptr);
5085         else if (netif_is_macvlan(dev))
5086                 err = mlxsw_sp_netdevice_macvlan_event(dev, event, ptr);
5087
5088         return notifier_from_errno(err);
5089 }
5090
5091 static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = {
5092         .notifier_call = mlxsw_sp_inetaddr_valid_event,
5093 };
5094
5095 static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = {
5096         .notifier_call = mlxsw_sp_inetaddr_event,
5097 };
5098
5099 static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = {
5100         .notifier_call = mlxsw_sp_inet6addr_valid_event,
5101 };
5102
5103 static struct notifier_block mlxsw_sp_inet6addr_nb __read_mostly = {
5104         .notifier_call = mlxsw_sp_inet6addr_event,
5105 };
5106
5107 static const struct pci_device_id mlxsw_sp1_pci_id_table[] = {
5108         {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
5109         {0, },
5110 };
5111
5112 static struct pci_driver mlxsw_sp1_pci_driver = {
5113         .name = mlxsw_sp1_driver_name,
5114         .id_table = mlxsw_sp1_pci_id_table,
5115 };
5116
5117 static const struct pci_device_id mlxsw_sp2_pci_id_table[] = {
5118         {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM2), 0},
5119         {0, },
5120 };
5121
5122 static struct pci_driver mlxsw_sp2_pci_driver = {
5123         .name = mlxsw_sp2_driver_name,
5124         .id_table = mlxsw_sp2_pci_id_table,
5125 };
5126
5127 static int __init mlxsw_sp_module_init(void)
5128 {
5129         int err;
5130
5131         register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
5132         register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
5133         register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
5134         register_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
5135
5136         err = mlxsw_core_driver_register(&mlxsw_sp1_driver);
5137         if (err)
5138                 goto err_sp1_core_driver_register;
5139
5140         err = mlxsw_core_driver_register(&mlxsw_sp2_driver);
5141         if (err)
5142                 goto err_sp2_core_driver_register;
5143
5144         err = mlxsw_pci_driver_register(&mlxsw_sp1_pci_driver);
5145         if (err)
5146                 goto err_sp1_pci_driver_register;
5147
5148         err = mlxsw_pci_driver_register(&mlxsw_sp2_pci_driver);
5149         if (err)
5150                 goto err_sp2_pci_driver_register;
5151
5152         return 0;
5153
5154 err_sp2_pci_driver_register:
5155         mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver);
5156 err_sp1_pci_driver_register:
5157         mlxsw_core_driver_unregister(&mlxsw_sp2_driver);
5158 err_sp2_core_driver_register:
5159         mlxsw_core_driver_unregister(&mlxsw_sp1_driver);
5160 err_sp1_core_driver_register:
5161         unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
5162         unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
5163         unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
5164         unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
5165         return err;
5166 }
5167
5168 static void __exit mlxsw_sp_module_exit(void)
5169 {
5170         mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver);
5171         mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver);
5172         mlxsw_core_driver_unregister(&mlxsw_sp2_driver);
5173         mlxsw_core_driver_unregister(&mlxsw_sp1_driver);
5174         unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
5175         unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
5176         unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
5177         unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
5178 }
5179
5180 module_init(mlxsw_sp_module_init);
5181 module_exit(mlxsw_sp_module_exit);
5182
5183 MODULE_LICENSE("Dual BSD/GPL");
5184 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
5185 MODULE_DESCRIPTION("Mellanox Spectrum driver");
5186 MODULE_DEVICE_TABLE(pci, mlxsw_sp1_pci_id_table);
5187 MODULE_DEVICE_TABLE(pci, mlxsw_sp2_pci_id_table);
5188 MODULE_FIRMWARE(MLXSW_SP1_FW_FILENAME);