a2df12b79f8e915702323f9258972260135c094c
[sfrench/cifs-2.6.git] / drivers / net / ethernet / mellanox / mlxsw / spectrum.c
1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
3
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/types.h>
7 #include <linux/pci.h>
8 #include <linux/netdevice.h>
9 #include <linux/etherdevice.h>
10 #include <linux/ethtool.h>
11 #include <linux/slab.h>
12 #include <linux/device.h>
13 #include <linux/skbuff.h>
14 #include <linux/if_vlan.h>
15 #include <linux/if_bridge.h>
16 #include <linux/workqueue.h>
17 #include <linux/jiffies.h>
18 #include <linux/bitops.h>
19 #include <linux/list.h>
20 #include <linux/notifier.h>
21 #include <linux/dcbnl.h>
22 #include <linux/inetdevice.h>
23 #include <linux/netlink.h>
24 #include <linux/random.h>
25 #include <net/switchdev.h>
26 #include <net/pkt_cls.h>
27 #include <net/tc_act/tc_mirred.h>
28 #include <net/netevent.h>
29 #include <net/tc_act/tc_sample.h>
30 #include <net/addrconf.h>
31
32 #include "spectrum.h"
33 #include "pci.h"
34 #include "core.h"
35 #include "reg.h"
36 #include "port.h"
37 #include "trap.h"
38 #include "txheader.h"
39 #include "spectrum_cnt.h"
40 #include "spectrum_dpipe.h"
41 #include "spectrum_acl_flex_actions.h"
42 #include "spectrum_span.h"
43 #include "../mlxfw/mlxfw.h"
44
45 #define MLXSW_SP_FWREV_MINOR_TO_BRANCH(minor) ((minor) / 100)
46
47 #define MLXSW_SP1_FWREV_MAJOR 13
48 #define MLXSW_SP1_FWREV_MINOR 1703
49 #define MLXSW_SP1_FWREV_SUBMINOR 4
50 #define MLXSW_SP1_FWREV_CAN_RESET_MINOR 1702
51
52 static const struct mlxsw_fw_rev mlxsw_sp1_fw_rev = {
53         .major = MLXSW_SP1_FWREV_MAJOR,
54         .minor = MLXSW_SP1_FWREV_MINOR,
55         .subminor = MLXSW_SP1_FWREV_SUBMINOR,
56         .can_reset_minor = MLXSW_SP1_FWREV_CAN_RESET_MINOR,
57 };
58
59 #define MLXSW_SP1_FW_FILENAME \
60         "mellanox/mlxsw_spectrum-" __stringify(MLXSW_SP1_FWREV_MAJOR) \
61         "." __stringify(MLXSW_SP1_FWREV_MINOR) \
62         "." __stringify(MLXSW_SP1_FWREV_SUBMINOR) ".mfa2"
63
64 static const char mlxsw_sp1_driver_name[] = "mlxsw_spectrum";
65 static const char mlxsw_sp2_driver_name[] = "mlxsw_spectrum2";
66 static const char mlxsw_sp_driver_version[] = "1.0";
67
68 /* tx_hdr_version
69  * Tx header version.
70  * Must be set to 1.
71  */
72 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
73
74 /* tx_hdr_ctl
75  * Packet control type.
76  * 0 - Ethernet control (e.g. EMADs, LACP)
77  * 1 - Ethernet data
78  */
79 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
80
81 /* tx_hdr_proto
82  * Packet protocol type. Must be set to 1 (Ethernet).
83  */
84 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
85
86 /* tx_hdr_rx_is_router
87  * Packet is sent from the router. Valid for data packets only.
88  */
89 MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
90
91 /* tx_hdr_fid_valid
92  * Indicates if the 'fid' field is valid and should be used for
93  * forwarding lookup. Valid for data packets only.
94  */
95 MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
96
97 /* tx_hdr_swid
98  * Switch partition ID. Must be set to 0.
99  */
100 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
101
102 /* tx_hdr_control_tclass
103  * Indicates if the packet should use the control TClass and not one
104  * of the data TClasses.
105  */
106 MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
107
108 /* tx_hdr_etclass
109  * Egress TClass to be used on the egress device on the egress port.
110  */
111 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
112
113 /* tx_hdr_port_mid
114  * Destination local port for unicast packets.
115  * Destination multicast ID for multicast packets.
116  *
117  * Control packets are directed to a specific egress port, while data
118  * packets are transmitted through the CPU port (0) into the switch partition,
119  * where forwarding rules are applied.
120  */
121 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
122
123 /* tx_hdr_fid
124  * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
125  * set, otherwise calculated based on the packet's VID using VID to FID mapping.
126  * Valid for data packets only.
127  */
128 MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
129
130 /* tx_hdr_type
131  * 0 - Data packets
132  * 6 - Control packets
133  */
134 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
135
136 struct mlxsw_sp_mlxfw_dev {
137         struct mlxfw_dev mlxfw_dev;
138         struct mlxsw_sp *mlxsw_sp;
139 };
140
141 static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev,
142                                     u16 component_index, u32 *p_max_size,
143                                     u8 *p_align_bits, u16 *p_max_write_size)
144 {
145         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
146                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
147         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
148         char mcqi_pl[MLXSW_REG_MCQI_LEN];
149         int err;
150
151         mlxsw_reg_mcqi_pack(mcqi_pl, component_index);
152         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl);
153         if (err)
154                 return err;
155         mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits,
156                               p_max_write_size);
157
158         *p_align_bits = max_t(u8, *p_align_bits, 2);
159         *p_max_write_size = min_t(u16, *p_max_write_size,
160                                   MLXSW_REG_MCDA_MAX_DATA_LEN);
161         return 0;
162 }
163
164 static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
165 {
166         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
167                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
168         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
169         char mcc_pl[MLXSW_REG_MCC_LEN];
170         u8 control_state;
171         int err;
172
173         mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0);
174         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
175         if (err)
176                 return err;
177
178         mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state);
179         if (control_state != MLXFW_FSM_STATE_IDLE)
180                 return -EBUSY;
181
182         mlxsw_reg_mcc_pack(mcc_pl,
183                            MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
184                            0, *fwhandle, 0);
185         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
186 }
187
188 static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev,
189                                          u32 fwhandle, u16 component_index,
190                                          u32 component_size)
191 {
192         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
193                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
194         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
195         char mcc_pl[MLXSW_REG_MCC_LEN];
196
197         mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
198                            component_index, fwhandle, component_size);
199         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
200 }
201
202 static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev,
203                                        u32 fwhandle, u8 *data, u16 size,
204                                        u32 offset)
205 {
206         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
207                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
208         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
209         char mcda_pl[MLXSW_REG_MCDA_LEN];
210
211         mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data);
212         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl);
213 }
214
215 static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev,
216                                          u32 fwhandle, u16 component_index)
217 {
218         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
219                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
220         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
221         char mcc_pl[MLXSW_REG_MCC_LEN];
222
223         mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
224                            component_index, fwhandle, 0);
225         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
226 }
227
228 static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
229 {
230         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
231                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
232         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
233         char mcc_pl[MLXSW_REG_MCC_LEN];
234
235         mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0,
236                            fwhandle, 0);
237         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
238 }
239
240 static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
241                                     enum mlxfw_fsm_state *fsm_state,
242                                     enum mlxfw_fsm_state_err *fsm_state_err)
243 {
244         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
245                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
246         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
247         char mcc_pl[MLXSW_REG_MCC_LEN];
248         u8 control_state;
249         u8 error_code;
250         int err;
251
252         mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0);
253         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
254         if (err)
255                 return err;
256
257         mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state);
258         *fsm_state = control_state;
259         *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
260                                MLXFW_FSM_STATE_ERR_MAX);
261         return 0;
262 }
263
264 static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
265 {
266         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
267                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
268         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
269         char mcc_pl[MLXSW_REG_MCC_LEN];
270
271         mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0,
272                            fwhandle, 0);
273         mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
274 }
275
276 static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
277 {
278         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
279                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
280         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
281         char mcc_pl[MLXSW_REG_MCC_LEN];
282
283         mlxsw_reg_mcc_pack(mcc_pl,
284                            MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
285                            fwhandle, 0);
286         mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
287 }
288
289 static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = {
290         .component_query        = mlxsw_sp_component_query,
291         .fsm_lock               = mlxsw_sp_fsm_lock,
292         .fsm_component_update   = mlxsw_sp_fsm_component_update,
293         .fsm_block_download     = mlxsw_sp_fsm_block_download,
294         .fsm_component_verify   = mlxsw_sp_fsm_component_verify,
295         .fsm_activate           = mlxsw_sp_fsm_activate,
296         .fsm_query_state        = mlxsw_sp_fsm_query_state,
297         .fsm_cancel             = mlxsw_sp_fsm_cancel,
298         .fsm_release            = mlxsw_sp_fsm_release
299 };
300
301 static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp,
302                                    const struct firmware *firmware)
303 {
304         struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = {
305                 .mlxfw_dev = {
306                         .ops = &mlxsw_sp_mlxfw_dev_ops,
307                         .psid = mlxsw_sp->bus_info->psid,
308                         .psid_size = strlen(mlxsw_sp->bus_info->psid),
309                 },
310                 .mlxsw_sp = mlxsw_sp
311         };
312
313         return mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev, firmware);
314 }
315
316 static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp)
317 {
318         const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev;
319         const struct mlxsw_fw_rev *req_rev = mlxsw_sp->req_rev;
320         const char *fw_filename = mlxsw_sp->fw_filename;
321         const struct firmware *firmware;
322         int err;
323
324         /* Don't check if driver does not require it */
325         if (!req_rev || !fw_filename)
326                 return 0;
327
328         /* Validate driver & FW are compatible */
329         if (rev->major != req_rev->major) {
330                 WARN(1, "Mismatch in major FW version [%d:%d] is never expected; Please contact support\n",
331                      rev->major, req_rev->major);
332                 return -EINVAL;
333         }
334         if (MLXSW_SP_FWREV_MINOR_TO_BRANCH(rev->minor) ==
335             MLXSW_SP_FWREV_MINOR_TO_BRANCH(req_rev->minor) &&
336             (rev->minor > req_rev->minor ||
337              (rev->minor == req_rev->minor &&
338               rev->subminor >= req_rev->subminor)))
339                 return 0;
340
341         dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d is incompatible with the driver\n",
342                  rev->major, rev->minor, rev->subminor);
343         dev_info(mlxsw_sp->bus_info->dev, "Flashing firmware using file %s\n",
344                  fw_filename);
345
346         err = request_firmware_direct(&firmware, fw_filename,
347                                       mlxsw_sp->bus_info->dev);
348         if (err) {
349                 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n",
350                         fw_filename);
351                 return err;
352         }
353
354         err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
355         release_firmware(firmware);
356         if (err)
357                 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n");
358
359         /* On FW flash success, tell the caller FW reset is needed
360          * if current FW supports it.
361          */
362         if (rev->minor >= req_rev->can_reset_minor)
363                 return err ? err : -EAGAIN;
364         else
365                 return 0;
366 }
367
368 int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
369                               unsigned int counter_index, u64 *packets,
370                               u64 *bytes)
371 {
372         char mgpc_pl[MLXSW_REG_MGPC_LEN];
373         int err;
374
375         mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
376                             MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
377         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
378         if (err)
379                 return err;
380         if (packets)
381                 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
382         if (bytes)
383                 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
384         return 0;
385 }
386
387 static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
388                                        unsigned int counter_index)
389 {
390         char mgpc_pl[MLXSW_REG_MGPC_LEN];
391
392         mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
393                             MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
394         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
395 }
396
397 int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
398                                 unsigned int *p_counter_index)
399 {
400         int err;
401
402         err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
403                                      p_counter_index);
404         if (err)
405                 return err;
406         err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
407         if (err)
408                 goto err_counter_clear;
409         return 0;
410
411 err_counter_clear:
412         mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
413                               *p_counter_index);
414         return err;
415 }
416
417 void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
418                                 unsigned int counter_index)
419 {
420          mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
421                                counter_index);
422 }
423
424 static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
425                                      const struct mlxsw_tx_info *tx_info)
426 {
427         char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
428
429         memset(txhdr, 0, MLXSW_TXHDR_LEN);
430
431         mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
432         mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
433         mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
434         mlxsw_tx_hdr_swid_set(txhdr, 0);
435         mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
436         mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
437         mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
438 }
439
440 enum mlxsw_reg_spms_state mlxsw_sp_stp_spms_state(u8 state)
441 {
442         switch (state) {
443         case BR_STATE_FORWARDING:
444                 return MLXSW_REG_SPMS_STATE_FORWARDING;
445         case BR_STATE_LEARNING:
446                 return MLXSW_REG_SPMS_STATE_LEARNING;
447         case BR_STATE_LISTENING: /* fall-through */
448         case BR_STATE_DISABLED: /* fall-through */
449         case BR_STATE_BLOCKING:
450                 return MLXSW_REG_SPMS_STATE_DISCARDING;
451         default:
452                 BUG();
453         }
454 }
455
456 int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
457                               u8 state)
458 {
459         enum mlxsw_reg_spms_state spms_state = mlxsw_sp_stp_spms_state(state);
460         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
461         char *spms_pl;
462         int err;
463
464         spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
465         if (!spms_pl)
466                 return -ENOMEM;
467         mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
468         mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
469
470         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
471         kfree(spms_pl);
472         return err;
473 }
474
475 static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
476 {
477         char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
478         int err;
479
480         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
481         if (err)
482                 return err;
483         mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
484         return 0;
485 }
486
487 static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
488                                     bool enable, u32 rate)
489 {
490         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
491         char mpsc_pl[MLXSW_REG_MPSC_LEN];
492
493         mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
494         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
495 }
496
497 static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
498                                           bool is_up)
499 {
500         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
501         char paos_pl[MLXSW_REG_PAOS_LEN];
502
503         mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
504                             is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
505                             MLXSW_PORT_ADMIN_STATUS_DOWN);
506         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
507 }
508
509 static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
510                                       unsigned char *addr)
511 {
512         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
513         char ppad_pl[MLXSW_REG_PPAD_LEN];
514
515         mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
516         mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
517         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
518 }
519
520 static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
521 {
522         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
523         unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
524
525         ether_addr_copy(addr, mlxsw_sp->base_mac);
526         addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
527         return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
528 }
529
530 static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
531 {
532         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
533         char pmtu_pl[MLXSW_REG_PMTU_LEN];
534         int max_mtu;
535         int err;
536
537         mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
538         mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
539         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
540         if (err)
541                 return err;
542         max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
543
544         if (mtu > max_mtu)
545                 return -EINVAL;
546
547         mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
548         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
549 }
550
551 static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
552 {
553         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
554         char pspa_pl[MLXSW_REG_PSPA_LEN];
555
556         mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port);
557         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
558 }
559
560 int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
561 {
562         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
563         char svpe_pl[MLXSW_REG_SVPE_LEN];
564
565         mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
566         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
567 }
568
569 int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
570                                    bool learn_enable)
571 {
572         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
573         char *spvmlr_pl;
574         int err;
575
576         spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
577         if (!spvmlr_pl)
578                 return -ENOMEM;
579         mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
580                               learn_enable);
581         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
582         kfree(spvmlr_pl);
583         return err;
584 }
585
586 static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
587                                     u16 vid)
588 {
589         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
590         char spvid_pl[MLXSW_REG_SPVID_LEN];
591
592         mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
593         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
594 }
595
596 static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
597                                             bool allow)
598 {
599         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
600         char spaft_pl[MLXSW_REG_SPAFT_LEN];
601
602         mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
603         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
604 }
605
606 int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
607 {
608         int err;
609
610         if (!vid) {
611                 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
612                 if (err)
613                         return err;
614         } else {
615                 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
616                 if (err)
617                         return err;
618                 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
619                 if (err)
620                         goto err_port_allow_untagged_set;
621         }
622
623         mlxsw_sp_port->pvid = vid;
624         return 0;
625
626 err_port_allow_untagged_set:
627         __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
628         return err;
629 }
630
631 static int
632 mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
633 {
634         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
635         char sspr_pl[MLXSW_REG_SSPR_LEN];
636
637         mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
638         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
639 }
640
641 static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
642                                          u8 local_port, u8 *p_module,
643                                          u8 *p_width, u8 *p_lane)
644 {
645         char pmlp_pl[MLXSW_REG_PMLP_LEN];
646         int err;
647
648         mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
649         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
650         if (err)
651                 return err;
652         *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
653         *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
654         *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
655         return 0;
656 }
657
658 static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port,
659                                     u8 module, u8 width, u8 lane)
660 {
661         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
662         char pmlp_pl[MLXSW_REG_PMLP_LEN];
663         int i;
664
665         mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
666         mlxsw_reg_pmlp_width_set(pmlp_pl, width);
667         for (i = 0; i < width; i++) {
668                 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
669                 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i);  /* Rx & Tx */
670         }
671
672         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
673 }
674
675 static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port)
676 {
677         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
678         char pmlp_pl[MLXSW_REG_PMLP_LEN];
679
680         mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
681         mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
682         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
683 }
684
685 static int mlxsw_sp_port_open(struct net_device *dev)
686 {
687         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
688         int err;
689
690         err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
691         if (err)
692                 return err;
693         netif_start_queue(dev);
694         return 0;
695 }
696
697 static int mlxsw_sp_port_stop(struct net_device *dev)
698 {
699         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
700
701         netif_stop_queue(dev);
702         return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
703 }
704
705 static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
706                                       struct net_device *dev)
707 {
708         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
709         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
710         struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
711         const struct mlxsw_tx_info tx_info = {
712                 .local_port = mlxsw_sp_port->local_port,
713                 .is_emad = false,
714         };
715         u64 len;
716         int err;
717
718         if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
719                 return NETDEV_TX_BUSY;
720
721         if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
722                 struct sk_buff *skb_orig = skb;
723
724                 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
725                 if (!skb) {
726                         this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
727                         dev_kfree_skb_any(skb_orig);
728                         return NETDEV_TX_OK;
729                 }
730                 dev_consume_skb_any(skb_orig);
731         }
732
733         if (eth_skb_pad(skb)) {
734                 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
735                 return NETDEV_TX_OK;
736         }
737
738         mlxsw_sp_txhdr_construct(skb, &tx_info);
739         /* TX header is consumed by HW on the way so we shouldn't count its
740          * bytes as being sent.
741          */
742         len = skb->len - MLXSW_TXHDR_LEN;
743
744         /* Due to a race we might fail here because of a full queue. In that
745          * unlikely case we simply drop the packet.
746          */
747         err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
748
749         if (!err) {
750                 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
751                 u64_stats_update_begin(&pcpu_stats->syncp);
752                 pcpu_stats->tx_packets++;
753                 pcpu_stats->tx_bytes += len;
754                 u64_stats_update_end(&pcpu_stats->syncp);
755         } else {
756                 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
757                 dev_kfree_skb_any(skb);
758         }
759         return NETDEV_TX_OK;
760 }
761
762 static void mlxsw_sp_set_rx_mode(struct net_device *dev)
763 {
764 }
765
766 static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
767 {
768         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
769         struct sockaddr *addr = p;
770         int err;
771
772         if (!is_valid_ether_addr(addr->sa_data))
773                 return -EADDRNOTAVAIL;
774
775         err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
776         if (err)
777                 return err;
778         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
779         return 0;
780 }
781
782 static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
783                                          int mtu)
784 {
785         return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
786 }
787
788 #define MLXSW_SP_CELL_FACTOR 2  /* 2 * cell_size / (IPG + cell_size + 1) */
789
790 static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
791                                   u16 delay)
792 {
793         delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
794                                                             BITS_PER_BYTE));
795         return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
796                                                                    mtu);
797 }
798
799 /* Maximum delay buffer needed in case of PAUSE frames, in bytes.
800  * Assumes 100m cable and maximum MTU.
801  */
802 #define MLXSW_SP_PAUSE_DELAY 58752
803
804 static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
805                                      u16 delay, bool pfc, bool pause)
806 {
807         if (pfc)
808                 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
809         else if (pause)
810                 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
811         else
812                 return 0;
813 }
814
815 static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
816                                  bool lossy)
817 {
818         if (lossy)
819                 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
820         else
821                 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
822                                                     thres);
823 }
824
825 int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
826                                  u8 *prio_tc, bool pause_en,
827                                  struct ieee_pfc *my_pfc)
828 {
829         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
830         u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
831         u16 delay = !!my_pfc ? my_pfc->delay : 0;
832         char pbmc_pl[MLXSW_REG_PBMC_LEN];
833         int i, j, err;
834
835         mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
836         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
837         if (err)
838                 return err;
839
840         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
841                 bool configure = false;
842                 bool pfc = false;
843                 bool lossy;
844                 u16 thres;
845
846                 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
847                         if (prio_tc[j] == i) {
848                                 pfc = pfc_en & BIT(j);
849                                 configure = true;
850                                 break;
851                         }
852                 }
853
854                 if (!configure)
855                         continue;
856
857                 lossy = !(pfc || pause_en);
858                 thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
859                 delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc,
860                                                   pause_en);
861                 mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy);
862         }
863
864         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
865 }
866
867 static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
868                                       int mtu, bool pause_en)
869 {
870         u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
871         bool dcb_en = !!mlxsw_sp_port->dcb.ets;
872         struct ieee_pfc *my_pfc;
873         u8 *prio_tc;
874
875         prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
876         my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
877
878         return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
879                                             pause_en, my_pfc);
880 }
881
882 static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
883 {
884         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
885         bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
886         int err;
887
888         err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
889         if (err)
890                 return err;
891         err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
892         if (err)
893                 goto err_span_port_mtu_update;
894         err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
895         if (err)
896                 goto err_port_mtu_set;
897         dev->mtu = mtu;
898         return 0;
899
900 err_port_mtu_set:
901         mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
902 err_span_port_mtu_update:
903         mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
904         return err;
905 }
906
907 static int
908 mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
909                              struct rtnl_link_stats64 *stats)
910 {
911         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
912         struct mlxsw_sp_port_pcpu_stats *p;
913         u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
914         u32 tx_dropped = 0;
915         unsigned int start;
916         int i;
917
918         for_each_possible_cpu(i) {
919                 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
920                 do {
921                         start = u64_stats_fetch_begin_irq(&p->syncp);
922                         rx_packets      = p->rx_packets;
923                         rx_bytes        = p->rx_bytes;
924                         tx_packets      = p->tx_packets;
925                         tx_bytes        = p->tx_bytes;
926                 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
927
928                 stats->rx_packets       += rx_packets;
929                 stats->rx_bytes         += rx_bytes;
930                 stats->tx_packets       += tx_packets;
931                 stats->tx_bytes         += tx_bytes;
932                 /* tx_dropped is u32, updated without syncp protection. */
933                 tx_dropped      += p->tx_dropped;
934         }
935         stats->tx_dropped       = tx_dropped;
936         return 0;
937 }
938
939 static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
940 {
941         switch (attr_id) {
942         case IFLA_OFFLOAD_XSTATS_CPU_HIT:
943                 return true;
944         }
945
946         return false;
947 }
948
949 static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
950                                            void *sp)
951 {
952         switch (attr_id) {
953         case IFLA_OFFLOAD_XSTATS_CPU_HIT:
954                 return mlxsw_sp_port_get_sw_stats64(dev, sp);
955         }
956
957         return -EINVAL;
958 }
959
960 static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
961                                        int prio, char *ppcnt_pl)
962 {
963         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
964         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
965
966         mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
967         return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
968 }
969
970 static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
971                                       struct rtnl_link_stats64 *stats)
972 {
973         char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
974         int err;
975
976         err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
977                                           0, ppcnt_pl);
978         if (err)
979                 goto out;
980
981         stats->tx_packets =
982                 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
983         stats->rx_packets =
984                 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
985         stats->tx_bytes =
986                 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
987         stats->rx_bytes =
988                 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
989         stats->multicast =
990                 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
991
992         stats->rx_crc_errors =
993                 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
994         stats->rx_frame_errors =
995                 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
996
997         stats->rx_length_errors = (
998                 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
999                 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
1000                 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
1001
1002         stats->rx_errors = (stats->rx_crc_errors +
1003                 stats->rx_frame_errors + stats->rx_length_errors);
1004
1005 out:
1006         return err;
1007 }
1008
1009 static void
1010 mlxsw_sp_port_get_hw_xstats(struct net_device *dev,
1011                             struct mlxsw_sp_port_xstats *xstats)
1012 {
1013         char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1014         int err, i;
1015
1016         err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0,
1017                                           ppcnt_pl);
1018         if (!err)
1019                 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl);
1020
1021         for (i = 0; i < TC_MAX_QUEUE; i++) {
1022                 err = mlxsw_sp_port_get_stats_raw(dev,
1023                                                   MLXSW_REG_PPCNT_TC_CONG_TC,
1024                                                   i, ppcnt_pl);
1025                 if (!err)
1026                         xstats->wred_drop[i] =
1027                                 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl);
1028
1029                 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT,
1030                                                   i, ppcnt_pl);
1031                 if (err)
1032                         continue;
1033
1034                 xstats->backlog[i] =
1035                         mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl);
1036                 xstats->tail_drop[i] =
1037                         mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl);
1038         }
1039
1040         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1041                 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_PRIO_CNT,
1042                                                   i, ppcnt_pl);
1043                 if (err)
1044                         continue;
1045
1046                 xstats->tx_packets[i] = mlxsw_reg_ppcnt_tx_frames_get(ppcnt_pl);
1047                 xstats->tx_bytes[i] = mlxsw_reg_ppcnt_tx_octets_get(ppcnt_pl);
1048         }
1049 }
1050
1051 static void update_stats_cache(struct work_struct *work)
1052 {
1053         struct mlxsw_sp_port *mlxsw_sp_port =
1054                 container_of(work, struct mlxsw_sp_port,
1055                              periodic_hw_stats.update_dw.work);
1056
1057         if (!netif_carrier_ok(mlxsw_sp_port->dev))
1058                 goto out;
1059
1060         mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
1061                                    &mlxsw_sp_port->periodic_hw_stats.stats);
1062         mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev,
1063                                     &mlxsw_sp_port->periodic_hw_stats.xstats);
1064
1065 out:
1066         mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw,
1067                                MLXSW_HW_STATS_UPDATE_TIME);
1068 }
1069
1070 /* Return the stats from a cache that is updated periodically,
1071  * as this function might get called in an atomic context.
1072  */
1073 static void
1074 mlxsw_sp_port_get_stats64(struct net_device *dev,
1075                           struct rtnl_link_stats64 *stats)
1076 {
1077         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1078
1079         memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats));
1080 }
1081
1082 static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
1083                                     u16 vid_begin, u16 vid_end,
1084                                     bool is_member, bool untagged)
1085 {
1086         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1087         char *spvm_pl;
1088         int err;
1089
1090         spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1091         if (!spvm_pl)
1092                 return -ENOMEM;
1093
1094         mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1095                             vid_end, is_member, untagged);
1096         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1097         kfree(spvm_pl);
1098         return err;
1099 }
1100
1101 int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1102                            u16 vid_end, bool is_member, bool untagged)
1103 {
1104         u16 vid, vid_e;
1105         int err;
1106
1107         for (vid = vid_begin; vid <= vid_end;
1108              vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1109                 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1110                             vid_end);
1111
1112                 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1113                                                is_member, untagged);
1114                 if (err)
1115                         return err;
1116         }
1117
1118         return 0;
1119 }
1120
1121 static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port)
1122 {
1123         struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
1124
1125         list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
1126                                  &mlxsw_sp_port->vlans_list, list)
1127                 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
1128 }
1129
1130 static struct mlxsw_sp_port_vlan *
1131 mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1132 {
1133         struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1134         bool untagged = vid == 1;
1135         int err;
1136
1137         err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
1138         if (err)
1139                 return ERR_PTR(err);
1140
1141         mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
1142         if (!mlxsw_sp_port_vlan) {
1143                 err = -ENOMEM;
1144                 goto err_port_vlan_alloc;
1145         }
1146
1147         mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
1148         mlxsw_sp_port_vlan->ref_count = 1;
1149         mlxsw_sp_port_vlan->vid = vid;
1150         list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
1151
1152         return mlxsw_sp_port_vlan;
1153
1154 err_port_vlan_alloc:
1155         mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1156         return ERR_PTR(err);
1157 }
1158
1159 static void
1160 mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1161 {
1162         struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
1163         u16 vid = mlxsw_sp_port_vlan->vid;
1164
1165         list_del(&mlxsw_sp_port_vlan->list);
1166         kfree(mlxsw_sp_port_vlan);
1167         mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1168 }
1169
1170 struct mlxsw_sp_port_vlan *
1171 mlxsw_sp_port_vlan_get(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1172 {
1173         struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1174
1175         mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1176         if (mlxsw_sp_port_vlan) {
1177                 mlxsw_sp_port_vlan->ref_count++;
1178                 return mlxsw_sp_port_vlan;
1179         }
1180
1181         return mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid);
1182 }
1183
1184 void mlxsw_sp_port_vlan_put(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1185 {
1186         struct mlxsw_sp_fid *fid = mlxsw_sp_port_vlan->fid;
1187
1188         if (--mlxsw_sp_port_vlan->ref_count != 0)
1189                 return;
1190
1191         if (mlxsw_sp_port_vlan->bridge_port)
1192                 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
1193         else if (fid)
1194                 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
1195
1196         mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
1197 }
1198
1199 static int mlxsw_sp_port_add_vid(struct net_device *dev,
1200                                  __be16 __always_unused proto, u16 vid)
1201 {
1202         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1203
1204         /* VLAN 0 is added to HW filter when device goes up, but it is
1205          * reserved in our case, so simply return.
1206          */
1207         if (!vid)
1208                 return 0;
1209
1210         return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_get(mlxsw_sp_port, vid));
1211 }
1212
1213 static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1214                                   __be16 __always_unused proto, u16 vid)
1215 {
1216         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1217         struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1218
1219         /* VLAN 0 is removed from HW filter when device goes down, but
1220          * it is reserved in our case, so simply return.
1221          */
1222         if (!vid)
1223                 return 0;
1224
1225         mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1226         if (!mlxsw_sp_port_vlan)
1227                 return 0;
1228         mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
1229
1230         return 0;
1231 }
1232
1233 static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
1234                                             size_t len)
1235 {
1236         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1237
1238         return mlxsw_core_port_get_phys_port_name(mlxsw_sp_port->mlxsw_sp->core,
1239                                                   mlxsw_sp_port->local_port,
1240                                                   name, len);
1241 }
1242
1243 static struct mlxsw_sp_port_mall_tc_entry *
1244 mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1245                                  unsigned long cookie) {
1246         struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1247
1248         list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1249                 if (mall_tc_entry->cookie == cookie)
1250                         return mall_tc_entry;
1251
1252         return NULL;
1253 }
1254
1255 static int
1256 mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1257                                       struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
1258                                       const struct tc_action *a,
1259                                       bool ingress)
1260 {
1261         enum mlxsw_sp_span_type span_type;
1262         struct net_device *to_dev;
1263
1264         to_dev = tcf_mirred_dev(a);
1265         if (!to_dev) {
1266                 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1267                 return -EINVAL;
1268         }
1269
1270         mirror->ingress = ingress;
1271         span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1272         return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_dev, span_type,
1273                                         true, &mirror->span_id);
1274 }
1275
1276 static void
1277 mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1278                                       struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1279 {
1280         enum mlxsw_sp_span_type span_type;
1281
1282         span_type = mirror->ingress ?
1283                         MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1284         mlxsw_sp_span_mirror_del(mlxsw_sp_port, mirror->span_id,
1285                                  span_type, true);
1286 }
1287
1288 static int
1289 mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1290                                       struct tc_cls_matchall_offload *cls,
1291                                       const struct tc_action *a,
1292                                       bool ingress)
1293 {
1294         int err;
1295
1296         if (!mlxsw_sp_port->sample)
1297                 return -EOPNOTSUPP;
1298         if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1299                 netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1300                 return -EEXIST;
1301         }
1302         if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) {
1303                 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1304                 return -EOPNOTSUPP;
1305         }
1306
1307         rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1308                            tcf_sample_psample_group(a));
1309         mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a);
1310         mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a);
1311         mlxsw_sp_port->sample->rate = tcf_sample_rate(a);
1312
1313         err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a));
1314         if (err)
1315                 goto err_port_sample_set;
1316         return 0;
1317
1318 err_port_sample_set:
1319         RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1320         return err;
1321 }
1322
1323 static void
1324 mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1325 {
1326         if (!mlxsw_sp_port->sample)
1327                 return;
1328
1329         mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1330         RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1331 }
1332
1333 static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1334                                           struct tc_cls_matchall_offload *f,
1335                                           bool ingress)
1336 {
1337         struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1338         __be16 protocol = f->common.protocol;
1339         const struct tc_action *a;
1340         LIST_HEAD(actions);
1341         int err;
1342
1343         if (!tcf_exts_has_one_action(f->exts)) {
1344                 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
1345                 return -EOPNOTSUPP;
1346         }
1347
1348         mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1349         if (!mall_tc_entry)
1350                 return -ENOMEM;
1351         mall_tc_entry->cookie = f->cookie;
1352
1353         a = tcf_exts_first_action(f->exts);
1354
1355         if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) {
1356                 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1357
1358                 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1359                 mirror = &mall_tc_entry->mirror;
1360                 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1361                                                             mirror, a, ingress);
1362         } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) {
1363                 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
1364                 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, f,
1365                                                             a, ingress);
1366         } else {
1367                 err = -EOPNOTSUPP;
1368         }
1369
1370         if (err)
1371                 goto err_add_action;
1372
1373         list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
1374         return 0;
1375
1376 err_add_action:
1377         kfree(mall_tc_entry);
1378         return err;
1379 }
1380
1381 static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1382                                            struct tc_cls_matchall_offload *f)
1383 {
1384         struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1385
1386         mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
1387                                                          f->cookie);
1388         if (!mall_tc_entry) {
1389                 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1390                 return;
1391         }
1392         list_del(&mall_tc_entry->list);
1393
1394         switch (mall_tc_entry->type) {
1395         case MLXSW_SP_PORT_MALL_MIRROR:
1396                 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1397                                                       &mall_tc_entry->mirror);
1398                 break;
1399         case MLXSW_SP_PORT_MALL_SAMPLE:
1400                 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1401                 break;
1402         default:
1403                 WARN_ON(1);
1404         }
1405
1406         kfree(mall_tc_entry);
1407 }
1408
1409 static int mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1410                                           struct tc_cls_matchall_offload *f,
1411                                           bool ingress)
1412 {
1413         switch (f->command) {
1414         case TC_CLSMATCHALL_REPLACE:
1415                 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port, f,
1416                                                       ingress);
1417         case TC_CLSMATCHALL_DESTROY:
1418                 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port, f);
1419                 return 0;
1420         default:
1421                 return -EOPNOTSUPP;
1422         }
1423 }
1424
1425 static int
1426 mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_acl_block *acl_block,
1427                              struct tc_cls_flower_offload *f)
1428 {
1429         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_acl_block_mlxsw_sp(acl_block);
1430
1431         switch (f->command) {
1432         case TC_CLSFLOWER_REPLACE:
1433                 return mlxsw_sp_flower_replace(mlxsw_sp, acl_block, f);
1434         case TC_CLSFLOWER_DESTROY:
1435                 mlxsw_sp_flower_destroy(mlxsw_sp, acl_block, f);
1436                 return 0;
1437         case TC_CLSFLOWER_STATS:
1438                 return mlxsw_sp_flower_stats(mlxsw_sp, acl_block, f);
1439         case TC_CLSFLOWER_TMPLT_CREATE:
1440                 return mlxsw_sp_flower_tmplt_create(mlxsw_sp, acl_block, f);
1441         case TC_CLSFLOWER_TMPLT_DESTROY:
1442                 mlxsw_sp_flower_tmplt_destroy(mlxsw_sp, acl_block, f);
1443                 return 0;
1444         default:
1445                 return -EOPNOTSUPP;
1446         }
1447 }
1448
1449 static int mlxsw_sp_setup_tc_block_cb_matchall(enum tc_setup_type type,
1450                                                void *type_data,
1451                                                void *cb_priv, bool ingress)
1452 {
1453         struct mlxsw_sp_port *mlxsw_sp_port = cb_priv;
1454
1455         switch (type) {
1456         case TC_SETUP_CLSMATCHALL:
1457                 if (!tc_cls_can_offload_and_chain0(mlxsw_sp_port->dev,
1458                                                    type_data))
1459                         return -EOPNOTSUPP;
1460
1461                 return mlxsw_sp_setup_tc_cls_matchall(mlxsw_sp_port, type_data,
1462                                                       ingress);
1463         case TC_SETUP_CLSFLOWER:
1464                 return 0;
1465         default:
1466                 return -EOPNOTSUPP;
1467         }
1468 }
1469
1470 static int mlxsw_sp_setup_tc_block_cb_matchall_ig(enum tc_setup_type type,
1471                                                   void *type_data,
1472                                                   void *cb_priv)
1473 {
1474         return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1475                                                    cb_priv, true);
1476 }
1477
1478 static int mlxsw_sp_setup_tc_block_cb_matchall_eg(enum tc_setup_type type,
1479                                                   void *type_data,
1480                                                   void *cb_priv)
1481 {
1482         return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1483                                                    cb_priv, false);
1484 }
1485
1486 static int mlxsw_sp_setup_tc_block_cb_flower(enum tc_setup_type type,
1487                                              void *type_data, void *cb_priv)
1488 {
1489         struct mlxsw_sp_acl_block *acl_block = cb_priv;
1490
1491         switch (type) {
1492         case TC_SETUP_CLSMATCHALL:
1493                 return 0;
1494         case TC_SETUP_CLSFLOWER:
1495                 if (mlxsw_sp_acl_block_disabled(acl_block))
1496                         return -EOPNOTSUPP;
1497
1498                 return mlxsw_sp_setup_tc_cls_flower(acl_block, type_data);
1499         default:
1500                 return -EOPNOTSUPP;
1501         }
1502 }
1503
1504 static int
1505 mlxsw_sp_setup_tc_block_flower_bind(struct mlxsw_sp_port *mlxsw_sp_port,
1506                                     struct tcf_block *block, bool ingress,
1507                                     struct netlink_ext_ack *extack)
1508 {
1509         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1510         struct mlxsw_sp_acl_block *acl_block;
1511         struct tcf_block_cb *block_cb;
1512         int err;
1513
1514         block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower,
1515                                        mlxsw_sp);
1516         if (!block_cb) {
1517                 acl_block = mlxsw_sp_acl_block_create(mlxsw_sp, block->net);
1518                 if (!acl_block)
1519                         return -ENOMEM;
1520                 block_cb = __tcf_block_cb_register(block,
1521                                                    mlxsw_sp_setup_tc_block_cb_flower,
1522                                                    mlxsw_sp, acl_block, extack);
1523                 if (IS_ERR(block_cb)) {
1524                         err = PTR_ERR(block_cb);
1525                         goto err_cb_register;
1526                 }
1527         } else {
1528                 acl_block = tcf_block_cb_priv(block_cb);
1529         }
1530         tcf_block_cb_incref(block_cb);
1531         err = mlxsw_sp_acl_block_bind(mlxsw_sp, acl_block,
1532                                       mlxsw_sp_port, ingress);
1533         if (err)
1534                 goto err_block_bind;
1535
1536         if (ingress)
1537                 mlxsw_sp_port->ing_acl_block = acl_block;
1538         else
1539                 mlxsw_sp_port->eg_acl_block = acl_block;
1540
1541         return 0;
1542
1543 err_block_bind:
1544         if (!tcf_block_cb_decref(block_cb)) {
1545                 __tcf_block_cb_unregister(block, block_cb);
1546 err_cb_register:
1547                 mlxsw_sp_acl_block_destroy(acl_block);
1548         }
1549         return err;
1550 }
1551
1552 static void
1553 mlxsw_sp_setup_tc_block_flower_unbind(struct mlxsw_sp_port *mlxsw_sp_port,
1554                                       struct tcf_block *block, bool ingress)
1555 {
1556         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1557         struct mlxsw_sp_acl_block *acl_block;
1558         struct tcf_block_cb *block_cb;
1559         int err;
1560
1561         block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower,
1562                                        mlxsw_sp);
1563         if (!block_cb)
1564                 return;
1565
1566         if (ingress)
1567                 mlxsw_sp_port->ing_acl_block = NULL;
1568         else
1569                 mlxsw_sp_port->eg_acl_block = NULL;
1570
1571         acl_block = tcf_block_cb_priv(block_cb);
1572         err = mlxsw_sp_acl_block_unbind(mlxsw_sp, acl_block,
1573                                         mlxsw_sp_port, ingress);
1574         if (!err && !tcf_block_cb_decref(block_cb)) {
1575                 __tcf_block_cb_unregister(block, block_cb);
1576                 mlxsw_sp_acl_block_destroy(acl_block);
1577         }
1578 }
1579
1580 static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port,
1581                                    struct tc_block_offload *f)
1582 {
1583         tc_setup_cb_t *cb;
1584         bool ingress;
1585         int err;
1586
1587         if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) {
1588                 cb = mlxsw_sp_setup_tc_block_cb_matchall_ig;
1589                 ingress = true;
1590         } else if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_EGRESS) {
1591                 cb = mlxsw_sp_setup_tc_block_cb_matchall_eg;
1592                 ingress = false;
1593         } else {
1594                 return -EOPNOTSUPP;
1595         }
1596
1597         switch (f->command) {
1598         case TC_BLOCK_BIND:
1599                 err = tcf_block_cb_register(f->block, cb, mlxsw_sp_port,
1600                                             mlxsw_sp_port, f->extack);
1601                 if (err)
1602                         return err;
1603                 err = mlxsw_sp_setup_tc_block_flower_bind(mlxsw_sp_port,
1604                                                           f->block, ingress,
1605                                                           f->extack);
1606                 if (err) {
1607                         tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1608                         return err;
1609                 }
1610                 return 0;
1611         case TC_BLOCK_UNBIND:
1612                 mlxsw_sp_setup_tc_block_flower_unbind(mlxsw_sp_port,
1613                                                       f->block, ingress);
1614                 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1615                 return 0;
1616         default:
1617                 return -EOPNOTSUPP;
1618         }
1619 }
1620
1621 static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type,
1622                              void *type_data)
1623 {
1624         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1625
1626         switch (type) {
1627         case TC_SETUP_BLOCK:
1628                 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data);
1629         case TC_SETUP_QDISC_RED:
1630                 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data);
1631         case TC_SETUP_QDISC_PRIO:
1632                 return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data);
1633         default:
1634                 return -EOPNOTSUPP;
1635         }
1636 }
1637
1638
1639 static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable)
1640 {
1641         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1642
1643         if (!enable) {
1644                 if (mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->ing_acl_block) ||
1645                     mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->eg_acl_block) ||
1646                     !list_empty(&mlxsw_sp_port->mall_tc_list)) {
1647                         netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n");
1648                         return -EINVAL;
1649                 }
1650                 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->ing_acl_block);
1651                 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->eg_acl_block);
1652         } else {
1653                 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->ing_acl_block);
1654                 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->eg_acl_block);
1655         }
1656         return 0;
1657 }
1658
1659 typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable);
1660
1661 static int mlxsw_sp_handle_feature(struct net_device *dev,
1662                                    netdev_features_t wanted_features,
1663                                    netdev_features_t feature,
1664                                    mlxsw_sp_feature_handler feature_handler)
1665 {
1666         netdev_features_t changes = wanted_features ^ dev->features;
1667         bool enable = !!(wanted_features & feature);
1668         int err;
1669
1670         if (!(changes & feature))
1671                 return 0;
1672
1673         err = feature_handler(dev, enable);
1674         if (err) {
1675                 netdev_err(dev, "%s feature %pNF failed, err %d\n",
1676                            enable ? "Enable" : "Disable", &feature, err);
1677                 return err;
1678         }
1679
1680         if (enable)
1681                 dev->features |= feature;
1682         else
1683                 dev->features &= ~feature;
1684
1685         return 0;
1686 }
1687 static int mlxsw_sp_set_features(struct net_device *dev,
1688                                  netdev_features_t features)
1689 {
1690         return mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC,
1691                                        mlxsw_sp_feature_hw_tc);
1692 }
1693
1694 static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1695         .ndo_open               = mlxsw_sp_port_open,
1696         .ndo_stop               = mlxsw_sp_port_stop,
1697         .ndo_start_xmit         = mlxsw_sp_port_xmit,
1698         .ndo_setup_tc           = mlxsw_sp_setup_tc,
1699         .ndo_set_rx_mode        = mlxsw_sp_set_rx_mode,
1700         .ndo_set_mac_address    = mlxsw_sp_port_set_mac_address,
1701         .ndo_change_mtu         = mlxsw_sp_port_change_mtu,
1702         .ndo_get_stats64        = mlxsw_sp_port_get_stats64,
1703         .ndo_has_offload_stats  = mlxsw_sp_port_has_offload_stats,
1704         .ndo_get_offload_stats  = mlxsw_sp_port_get_offload_stats,
1705         .ndo_vlan_rx_add_vid    = mlxsw_sp_port_add_vid,
1706         .ndo_vlan_rx_kill_vid   = mlxsw_sp_port_kill_vid,
1707         .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
1708         .ndo_set_features       = mlxsw_sp_set_features,
1709 };
1710
1711 static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1712                                       struct ethtool_drvinfo *drvinfo)
1713 {
1714         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1715         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1716
1717         strlcpy(drvinfo->driver, mlxsw_sp->bus_info->device_kind,
1718                 sizeof(drvinfo->driver));
1719         strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1720                 sizeof(drvinfo->version));
1721         snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1722                  "%d.%d.%d",
1723                  mlxsw_sp->bus_info->fw_rev.major,
1724                  mlxsw_sp->bus_info->fw_rev.minor,
1725                  mlxsw_sp->bus_info->fw_rev.subminor);
1726         strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1727                 sizeof(drvinfo->bus_info));
1728 }
1729
1730 static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1731                                          struct ethtool_pauseparam *pause)
1732 {
1733         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1734
1735         pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1736         pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1737 }
1738
1739 static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1740                                    struct ethtool_pauseparam *pause)
1741 {
1742         char pfcc_pl[MLXSW_REG_PFCC_LEN];
1743
1744         mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1745         mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1746         mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1747
1748         return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1749                                pfcc_pl);
1750 }
1751
1752 static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1753                                         struct ethtool_pauseparam *pause)
1754 {
1755         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1756         bool pause_en = pause->tx_pause || pause->rx_pause;
1757         int err;
1758
1759         if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1760                 netdev_err(dev, "PFC already enabled on port\n");
1761                 return -EINVAL;
1762         }
1763
1764         if (pause->autoneg) {
1765                 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1766                 return -EINVAL;
1767         }
1768
1769         err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1770         if (err) {
1771                 netdev_err(dev, "Failed to configure port's headroom\n");
1772                 return err;
1773         }
1774
1775         err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1776         if (err) {
1777                 netdev_err(dev, "Failed to set PAUSE parameters\n");
1778                 goto err_port_pause_configure;
1779         }
1780
1781         mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1782         mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1783
1784         return 0;
1785
1786 err_port_pause_configure:
1787         pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1788         mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1789         return err;
1790 }
1791
1792 struct mlxsw_sp_port_hw_stats {
1793         char str[ETH_GSTRING_LEN];
1794         u64 (*getter)(const char *payload);
1795         bool cells_bytes;
1796 };
1797
1798 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
1799         {
1800                 .str = "a_frames_transmitted_ok",
1801                 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1802         },
1803         {
1804                 .str = "a_frames_received_ok",
1805                 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1806         },
1807         {
1808                 .str = "a_frame_check_sequence_errors",
1809                 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1810         },
1811         {
1812                 .str = "a_alignment_errors",
1813                 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1814         },
1815         {
1816                 .str = "a_octets_transmitted_ok",
1817                 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1818         },
1819         {
1820                 .str = "a_octets_received_ok",
1821                 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1822         },
1823         {
1824                 .str = "a_multicast_frames_xmitted_ok",
1825                 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1826         },
1827         {
1828                 .str = "a_broadcast_frames_xmitted_ok",
1829                 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1830         },
1831         {
1832                 .str = "a_multicast_frames_received_ok",
1833                 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1834         },
1835         {
1836                 .str = "a_broadcast_frames_received_ok",
1837                 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1838         },
1839         {
1840                 .str = "a_in_range_length_errors",
1841                 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1842         },
1843         {
1844                 .str = "a_out_of_range_length_field",
1845                 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1846         },
1847         {
1848                 .str = "a_frame_too_long_errors",
1849                 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1850         },
1851         {
1852                 .str = "a_symbol_error_during_carrier",
1853                 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1854         },
1855         {
1856                 .str = "a_mac_control_frames_transmitted",
1857                 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1858         },
1859         {
1860                 .str = "a_mac_control_frames_received",
1861                 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1862         },
1863         {
1864                 .str = "a_unsupported_opcodes_received",
1865                 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1866         },
1867         {
1868                 .str = "a_pause_mac_ctrl_frames_received",
1869                 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1870         },
1871         {
1872                 .str = "a_pause_mac_ctrl_frames_xmitted",
1873                 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1874         },
1875 };
1876
1877 #define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
1878
1879 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_rfc_2819_stats[] = {
1880         {
1881                 .str = "ether_pkts64octets",
1882                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts64octets_get,
1883         },
1884         {
1885                 .str = "ether_pkts65to127octets",
1886                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts65to127octets_get,
1887         },
1888         {
1889                 .str = "ether_pkts128to255octets",
1890                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts128to255octets_get,
1891         },
1892         {
1893                 .str = "ether_pkts256to511octets",
1894                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts256to511octets_get,
1895         },
1896         {
1897                 .str = "ether_pkts512to1023octets",
1898                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts512to1023octets_get,
1899         },
1900         {
1901                 .str = "ether_pkts1024to1518octets",
1902                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts1024to1518octets_get,
1903         },
1904         {
1905                 .str = "ether_pkts1519to2047octets",
1906                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts1519to2047octets_get,
1907         },
1908         {
1909                 .str = "ether_pkts2048to4095octets",
1910                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts2048to4095octets_get,
1911         },
1912         {
1913                 .str = "ether_pkts4096to8191octets",
1914                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts4096to8191octets_get,
1915         },
1916         {
1917                 .str = "ether_pkts8192to10239octets",
1918                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts8192to10239octets_get,
1919         },
1920 };
1921
1922 #define MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN \
1923         ARRAY_SIZE(mlxsw_sp_port_hw_rfc_2819_stats)
1924
1925 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
1926         {
1927                 .str = "rx_octets_prio",
1928                 .getter = mlxsw_reg_ppcnt_rx_octets_get,
1929         },
1930         {
1931                 .str = "rx_frames_prio",
1932                 .getter = mlxsw_reg_ppcnt_rx_frames_get,
1933         },
1934         {
1935                 .str = "tx_octets_prio",
1936                 .getter = mlxsw_reg_ppcnt_tx_octets_get,
1937         },
1938         {
1939                 .str = "tx_frames_prio",
1940                 .getter = mlxsw_reg_ppcnt_tx_frames_get,
1941         },
1942         {
1943                 .str = "rx_pause_prio",
1944                 .getter = mlxsw_reg_ppcnt_rx_pause_get,
1945         },
1946         {
1947                 .str = "rx_pause_duration_prio",
1948                 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
1949         },
1950         {
1951                 .str = "tx_pause_prio",
1952                 .getter = mlxsw_reg_ppcnt_tx_pause_get,
1953         },
1954         {
1955                 .str = "tx_pause_duration_prio",
1956                 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
1957         },
1958 };
1959
1960 #define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
1961
1962 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
1963         {
1964                 .str = "tc_transmit_queue_tc",
1965                 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
1966                 .cells_bytes = true,
1967         },
1968         {
1969                 .str = "tc_no_buffer_discard_uc_tc",
1970                 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
1971         },
1972 };
1973
1974 #define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
1975
1976 #define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
1977                                          MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN + \
1978                                          (MLXSW_SP_PORT_HW_PRIO_STATS_LEN * \
1979                                           IEEE_8021QAZ_MAX_TCS) + \
1980                                          (MLXSW_SP_PORT_HW_TC_STATS_LEN * \
1981                                           TC_MAX_QUEUE))
1982
1983 static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
1984 {
1985         int i;
1986
1987         for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
1988                 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1989                          mlxsw_sp_port_hw_prio_stats[i].str, prio);
1990                 *p += ETH_GSTRING_LEN;
1991         }
1992 }
1993
1994 static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
1995 {
1996         int i;
1997
1998         for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
1999                 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
2000                          mlxsw_sp_port_hw_tc_stats[i].str, tc);
2001                 *p += ETH_GSTRING_LEN;
2002         }
2003 }
2004
2005 static void mlxsw_sp_port_get_strings(struct net_device *dev,
2006                                       u32 stringset, u8 *data)
2007 {
2008         u8 *p = data;
2009         int i;
2010
2011         switch (stringset) {
2012         case ETH_SS_STATS:
2013                 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
2014                         memcpy(p, mlxsw_sp_port_hw_stats[i].str,
2015                                ETH_GSTRING_LEN);
2016                         p += ETH_GSTRING_LEN;
2017                 }
2018                 for (i = 0; i < MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN; i++) {
2019                         memcpy(p, mlxsw_sp_port_hw_rfc_2819_stats[i].str,
2020                                ETH_GSTRING_LEN);
2021                         p += ETH_GSTRING_LEN;
2022                 }
2023
2024                 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2025                         mlxsw_sp_port_get_prio_strings(&p, i);
2026
2027                 for (i = 0; i < TC_MAX_QUEUE; i++)
2028                         mlxsw_sp_port_get_tc_strings(&p, i);
2029
2030                 break;
2031         }
2032 }
2033
2034 static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
2035                                      enum ethtool_phys_id_state state)
2036 {
2037         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2038         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2039         char mlcr_pl[MLXSW_REG_MLCR_LEN];
2040         bool active;
2041
2042         switch (state) {
2043         case ETHTOOL_ID_ACTIVE:
2044                 active = true;
2045                 break;
2046         case ETHTOOL_ID_INACTIVE:
2047                 active = false;
2048                 break;
2049         default:
2050                 return -EOPNOTSUPP;
2051         }
2052
2053         mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
2054         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
2055 }
2056
2057 static int
2058 mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
2059                                int *p_len, enum mlxsw_reg_ppcnt_grp grp)
2060 {
2061         switch (grp) {
2062         case MLXSW_REG_PPCNT_IEEE_8023_CNT:
2063                 *p_hw_stats = mlxsw_sp_port_hw_stats;
2064                 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
2065                 break;
2066         case MLXSW_REG_PPCNT_RFC_2819_CNT:
2067                 *p_hw_stats = mlxsw_sp_port_hw_rfc_2819_stats;
2068                 *p_len = MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN;
2069                 break;
2070         case MLXSW_REG_PPCNT_PRIO_CNT:
2071                 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
2072                 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2073                 break;
2074         case MLXSW_REG_PPCNT_TC_CNT:
2075                 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
2076                 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
2077                 break;
2078         default:
2079                 WARN_ON(1);
2080                 return -EOPNOTSUPP;
2081         }
2082         return 0;
2083 }
2084
2085 static void __mlxsw_sp_port_get_stats(struct net_device *dev,
2086                                       enum mlxsw_reg_ppcnt_grp grp, int prio,
2087                                       u64 *data, int data_index)
2088 {
2089         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2090         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2091         struct mlxsw_sp_port_hw_stats *hw_stats;
2092         char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
2093         int i, len;
2094         int err;
2095
2096         err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
2097         if (err)
2098                 return;
2099         mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
2100         for (i = 0; i < len; i++) {
2101                 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
2102                 if (!hw_stats[i].cells_bytes)
2103                         continue;
2104                 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
2105                                                             data[data_index + i]);
2106         }
2107 }
2108
2109 static void mlxsw_sp_port_get_stats(struct net_device *dev,
2110                                     struct ethtool_stats *stats, u64 *data)
2111 {
2112         int i, data_index = 0;
2113
2114         /* IEEE 802.3 Counters */
2115         __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
2116                                   data, data_index);
2117         data_index = MLXSW_SP_PORT_HW_STATS_LEN;
2118
2119         /* RFC 2819 Counters */
2120         __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_RFC_2819_CNT, 0,
2121                                   data, data_index);
2122         data_index += MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN;
2123
2124         /* Per-Priority Counters */
2125         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2126                 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
2127                                           data, data_index);
2128                 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2129         }
2130
2131         /* Per-TC Counters */
2132         for (i = 0; i < TC_MAX_QUEUE; i++) {
2133                 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
2134                                           data, data_index);
2135                 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
2136         }
2137 }
2138
2139 static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
2140 {
2141         switch (sset) {
2142         case ETH_SS_STATS:
2143                 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
2144         default:
2145                 return -EOPNOTSUPP;
2146         }
2147 }
2148
2149 struct mlxsw_sp_port_link_mode {
2150         enum ethtool_link_mode_bit_indices mask_ethtool;
2151         u32 mask;
2152         u32 speed;
2153 };
2154
2155 static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
2156         {
2157                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
2158                 .mask_ethtool   = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2159                 .speed          = SPEED_100,
2160         },
2161         {
2162                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
2163                                   MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
2164                 .mask_ethtool   = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2165                 .speed          = SPEED_1000,
2166         },
2167         {
2168                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
2169                 .mask_ethtool   = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2170                 .speed          = SPEED_10000,
2171         },
2172         {
2173                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
2174                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
2175                 .mask_ethtool   = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2176                 .speed          = SPEED_10000,
2177         },
2178         {
2179                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2180                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2181                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2182                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
2183                 .mask_ethtool   = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2184                 .speed          = SPEED_10000,
2185         },
2186         {
2187                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
2188                 .mask_ethtool   = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
2189                 .speed          = SPEED_20000,
2190         },
2191         {
2192                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
2193                 .mask_ethtool   = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2194                 .speed          = SPEED_40000,
2195         },
2196         {
2197                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
2198                 .mask_ethtool   = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2199                 .speed          = SPEED_40000,
2200         },
2201         {
2202                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
2203                 .mask_ethtool   = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2204                 .speed          = SPEED_40000,
2205         },
2206         {
2207                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
2208                 .mask_ethtool   = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2209                 .speed          = SPEED_40000,
2210         },
2211         {
2212                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
2213                 .mask_ethtool   = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2214                 .speed          = SPEED_25000,
2215         },
2216         {
2217                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
2218                 .mask_ethtool   = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2219                 .speed          = SPEED_25000,
2220         },
2221         {
2222                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2223                 .mask_ethtool   = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2224                 .speed          = SPEED_25000,
2225         },
2226         {
2227                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2228                 .mask_ethtool   = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2229                 .speed          = SPEED_25000,
2230         },
2231         {
2232                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
2233                 .mask_ethtool   = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2234                 .speed          = SPEED_50000,
2235         },
2236         {
2237                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
2238                 .mask_ethtool   = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2239                 .speed          = SPEED_50000,
2240         },
2241         {
2242                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
2243                 .mask_ethtool   = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2244                 .speed          = SPEED_50000,
2245         },
2246         {
2247                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2248                 .mask_ethtool   = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
2249                 .speed          = SPEED_56000,
2250         },
2251         {
2252                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2253                 .mask_ethtool   = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
2254                 .speed          = SPEED_56000,
2255         },
2256         {
2257                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2258                 .mask_ethtool   = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
2259                 .speed          = SPEED_56000,
2260         },
2261         {
2262                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2263                 .mask_ethtool   = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
2264                 .speed          = SPEED_56000,
2265         },
2266         {
2267                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
2268                 .mask_ethtool   = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2269                 .speed          = SPEED_100000,
2270         },
2271         {
2272                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
2273                 .mask_ethtool   = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2274                 .speed          = SPEED_100000,
2275         },
2276         {
2277                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
2278                 .mask_ethtool   = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2279                 .speed          = SPEED_100000,
2280         },
2281         {
2282                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
2283                 .mask_ethtool   = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2284                 .speed          = SPEED_100000,
2285         },
2286 };
2287
2288 #define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
2289
2290 static void
2291 mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
2292                                   struct ethtool_link_ksettings *cmd)
2293 {
2294         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2295                               MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2296                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2297                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2298                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2299                               MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2300                 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
2301
2302         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2303                               MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2304                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2305                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
2306                               MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
2307                 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
2308 }
2309
2310 static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
2311 {
2312         int i;
2313
2314         for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2315                 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
2316                         __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2317                                   mode);
2318         }
2319 }
2320
2321 static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
2322                                             struct ethtool_link_ksettings *cmd)
2323 {
2324         u32 speed = SPEED_UNKNOWN;
2325         u8 duplex = DUPLEX_UNKNOWN;
2326         int i;
2327
2328         if (!carrier_ok)
2329                 goto out;
2330
2331         for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2332                 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
2333                         speed = mlxsw_sp_port_link_mode[i].speed;
2334                         duplex = DUPLEX_FULL;
2335                         break;
2336                 }
2337         }
2338 out:
2339         cmd->base.speed = speed;
2340         cmd->base.duplex = duplex;
2341 }
2342
2343 static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
2344 {
2345         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2346                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2347                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2348                               MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2349                 return PORT_FIBRE;
2350
2351         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2352                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2353                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
2354                 return PORT_DA;
2355
2356         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2357                               MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2358                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2359                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
2360                 return PORT_NONE;
2361
2362         return PORT_OTHER;
2363 }
2364
2365 static u32
2366 mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
2367 {
2368         u32 ptys_proto = 0;
2369         int i;
2370
2371         for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2372                 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2373                              cmd->link_modes.advertising))
2374                         ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2375         }
2376         return ptys_proto;
2377 }
2378
2379 static u32 mlxsw_sp_to_ptys_speed(u32 speed)
2380 {
2381         u32 ptys_proto = 0;
2382         int i;
2383
2384         for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2385                 if (speed == mlxsw_sp_port_link_mode[i].speed)
2386                         ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2387         }
2388         return ptys_proto;
2389 }
2390
2391 static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
2392 {
2393         u32 ptys_proto = 0;
2394         int i;
2395
2396         for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2397                 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
2398                         ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2399         }
2400         return ptys_proto;
2401 }
2402
2403 static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
2404                                              struct ethtool_link_ksettings *cmd)
2405 {
2406         ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
2407         ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
2408         ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
2409
2410         mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
2411         mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
2412 }
2413
2414 static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
2415                                              struct ethtool_link_ksettings *cmd)
2416 {
2417         if (!autoneg)
2418                 return;
2419
2420         ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
2421         mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
2422 }
2423
2424 static void
2425 mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
2426                                     struct ethtool_link_ksettings *cmd)
2427 {
2428         if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
2429                 return;
2430
2431         ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
2432         mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
2433 }
2434
2435 static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
2436                                             struct ethtool_link_ksettings *cmd)
2437 {
2438         u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
2439         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2440         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2441         char ptys_pl[MLXSW_REG_PTYS_LEN];
2442         u8 autoneg_status;
2443         bool autoneg;
2444         int err;
2445
2446         autoneg = mlxsw_sp_port->link.autoneg;
2447         mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0, false);
2448         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2449         if (err)
2450                 return err;
2451         mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin,
2452                                   &eth_proto_oper);
2453
2454         mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
2455
2456         mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
2457
2458         eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
2459         autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
2460         mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
2461
2462         cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2463         cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
2464         mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
2465                                         cmd);
2466
2467         return 0;
2468 }
2469
2470 static int
2471 mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
2472                                  const struct ethtool_link_ksettings *cmd)
2473 {
2474         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2475         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2476         char ptys_pl[MLXSW_REG_PTYS_LEN];
2477         u32 eth_proto_cap, eth_proto_new;
2478         bool autoneg;
2479         int err;
2480
2481         mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0, false);
2482         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2483         if (err)
2484                 return err;
2485         mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
2486
2487         autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
2488         eth_proto_new = autoneg ?
2489                 mlxsw_sp_to_ptys_advert_link(cmd) :
2490                 mlxsw_sp_to_ptys_speed(cmd->base.speed);
2491
2492         eth_proto_new = eth_proto_new & eth_proto_cap;
2493         if (!eth_proto_new) {
2494                 netdev_err(dev, "No supported speed requested\n");
2495                 return -EINVAL;
2496         }
2497
2498         mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2499                                 eth_proto_new, autoneg);
2500         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2501         if (err)
2502                 return err;
2503
2504         if (!netif_running(dev))
2505                 return 0;
2506
2507         mlxsw_sp_port->link.autoneg = autoneg;
2508
2509         mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2510         mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
2511
2512         return 0;
2513 }
2514
2515 static int mlxsw_sp_flash_device(struct net_device *dev,
2516                                  struct ethtool_flash *flash)
2517 {
2518         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2519         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2520         const struct firmware *firmware;
2521         int err;
2522
2523         if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
2524                 return -EOPNOTSUPP;
2525
2526         dev_hold(dev);
2527         rtnl_unlock();
2528
2529         err = request_firmware_direct(&firmware, flash->data, &dev->dev);
2530         if (err)
2531                 goto out;
2532         err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
2533         release_firmware(firmware);
2534 out:
2535         rtnl_lock();
2536         dev_put(dev);
2537         return err;
2538 }
2539
2540 #define MLXSW_SP_I2C_ADDR_LOW 0x50
2541 #define MLXSW_SP_I2C_ADDR_HIGH 0x51
2542 #define MLXSW_SP_EEPROM_PAGE_LENGTH 256
2543
2544 static int mlxsw_sp_query_module_eeprom(struct mlxsw_sp_port *mlxsw_sp_port,
2545                                         u16 offset, u16 size, void *data,
2546                                         unsigned int *p_read_size)
2547 {
2548         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2549         char eeprom_tmp[MLXSW_SP_REG_MCIA_EEPROM_SIZE];
2550         char mcia_pl[MLXSW_REG_MCIA_LEN];
2551         u16 i2c_addr;
2552         int status;
2553         int err;
2554
2555         size = min_t(u16, size, MLXSW_SP_REG_MCIA_EEPROM_SIZE);
2556
2557         if (offset < MLXSW_SP_EEPROM_PAGE_LENGTH &&
2558             offset + size > MLXSW_SP_EEPROM_PAGE_LENGTH)
2559                 /* Cross pages read, read until offset 256 in low page */
2560                 size = MLXSW_SP_EEPROM_PAGE_LENGTH - offset;
2561
2562         i2c_addr = MLXSW_SP_I2C_ADDR_LOW;
2563         if (offset >= MLXSW_SP_EEPROM_PAGE_LENGTH) {
2564                 i2c_addr = MLXSW_SP_I2C_ADDR_HIGH;
2565                 offset -= MLXSW_SP_EEPROM_PAGE_LENGTH;
2566         }
2567
2568         mlxsw_reg_mcia_pack(mcia_pl, mlxsw_sp_port->mapping.module,
2569                             0, 0, offset, size, i2c_addr);
2570
2571         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcia), mcia_pl);
2572         if (err)
2573                 return err;
2574
2575         status = mlxsw_reg_mcia_status_get(mcia_pl);
2576         if (status)
2577                 return -EIO;
2578
2579         mlxsw_reg_mcia_eeprom_memcpy_from(mcia_pl, eeprom_tmp);
2580         memcpy(data, eeprom_tmp, size);
2581         *p_read_size = size;
2582
2583         return 0;
2584 }
2585
2586 enum mlxsw_sp_eeprom_module_info_rev_id {
2587         MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_UNSPC      = 0x00,
2588         MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8436       = 0x01,
2589         MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636       = 0x03,
2590 };
2591
2592 enum mlxsw_sp_eeprom_module_info_id {
2593         MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP              = 0x03,
2594         MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP             = 0x0C,
2595         MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS        = 0x0D,
2596         MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28           = 0x11,
2597 };
2598
2599 enum mlxsw_sp_eeprom_module_info {
2600         MLXSW_SP_EEPROM_MODULE_INFO_ID,
2601         MLXSW_SP_EEPROM_MODULE_INFO_REV_ID,
2602         MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2603 };
2604
2605 static int mlxsw_sp_get_module_info(struct net_device *netdev,
2606                                     struct ethtool_modinfo *modinfo)
2607 {
2608         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2609         u8 module_info[MLXSW_SP_EEPROM_MODULE_INFO_SIZE];
2610         u8 module_rev_id, module_id;
2611         unsigned int read_size;
2612         int err;
2613
2614         err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, 0,
2615                                            MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2616                                            module_info, &read_size);
2617         if (err)
2618                 return err;
2619
2620         if (read_size < MLXSW_SP_EEPROM_MODULE_INFO_SIZE)
2621                 return -EIO;
2622
2623         module_rev_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_REV_ID];
2624         module_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_ID];
2625
2626         switch (module_id) {
2627         case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP:
2628                 modinfo->type       = ETH_MODULE_SFF_8436;
2629                 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2630                 break;
2631         case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS:
2632         case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28:
2633                 if (module_id  == MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 ||
2634                     module_rev_id >= MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636) {
2635                         modinfo->type       = ETH_MODULE_SFF_8636;
2636                         modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
2637                 } else {
2638                         modinfo->type       = ETH_MODULE_SFF_8436;
2639                         modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2640                 }
2641                 break;
2642         case MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP:
2643                 modinfo->type       = ETH_MODULE_SFF_8472;
2644                 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2645                 break;
2646         default:
2647                 return -EINVAL;
2648         }
2649
2650         return 0;
2651 }
2652
2653 static int mlxsw_sp_get_module_eeprom(struct net_device *netdev,
2654                                       struct ethtool_eeprom *ee,
2655                                       u8 *data)
2656 {
2657         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2658         int offset = ee->offset;
2659         unsigned int read_size;
2660         int i = 0;
2661         int err;
2662
2663         if (!ee->len)
2664                 return -EINVAL;
2665
2666         memset(data, 0, ee->len);
2667
2668         while (i < ee->len) {
2669                 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, offset,
2670                                                    ee->len - i, data + i,
2671                                                    &read_size);
2672                 if (err) {
2673                         netdev_err(mlxsw_sp_port->dev, "Eeprom query failed\n");
2674                         return err;
2675                 }
2676
2677                 i += read_size;
2678                 offset += read_size;
2679         }
2680
2681         return 0;
2682 }
2683
2684 static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
2685         .get_drvinfo            = mlxsw_sp_port_get_drvinfo,
2686         .get_link               = ethtool_op_get_link,
2687         .get_pauseparam         = mlxsw_sp_port_get_pauseparam,
2688         .set_pauseparam         = mlxsw_sp_port_set_pauseparam,
2689         .get_strings            = mlxsw_sp_port_get_strings,
2690         .set_phys_id            = mlxsw_sp_port_set_phys_id,
2691         .get_ethtool_stats      = mlxsw_sp_port_get_stats,
2692         .get_sset_count         = mlxsw_sp_port_get_sset_count,
2693         .get_link_ksettings     = mlxsw_sp_port_get_link_ksettings,
2694         .set_link_ksettings     = mlxsw_sp_port_set_link_ksettings,
2695         .flash_device           = mlxsw_sp_flash_device,
2696         .get_module_info        = mlxsw_sp_get_module_info,
2697         .get_module_eeprom      = mlxsw_sp_get_module_eeprom,
2698 };
2699
2700 static int
2701 mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
2702 {
2703         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2704         u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
2705         char ptys_pl[MLXSW_REG_PTYS_LEN];
2706         u32 eth_proto_admin;
2707
2708         eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
2709         mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2710                                 eth_proto_admin, mlxsw_sp_port->link.autoneg);
2711         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2712 }
2713
2714 int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
2715                           enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
2716                           bool dwrr, u8 dwrr_weight)
2717 {
2718         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2719         char qeec_pl[MLXSW_REG_QEEC_LEN];
2720
2721         mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2722                             next_index);
2723         mlxsw_reg_qeec_de_set(qeec_pl, true);
2724         mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
2725         mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
2726         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2727 }
2728
2729 int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
2730                                   enum mlxsw_reg_qeec_hr hr, u8 index,
2731                                   u8 next_index, u32 maxrate)
2732 {
2733         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2734         char qeec_pl[MLXSW_REG_QEEC_LEN];
2735
2736         mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2737                             next_index);
2738         mlxsw_reg_qeec_mase_set(qeec_pl, true);
2739         mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
2740         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2741 }
2742
2743 static int mlxsw_sp_port_min_bw_set(struct mlxsw_sp_port *mlxsw_sp_port,
2744                                     enum mlxsw_reg_qeec_hr hr, u8 index,
2745                                     u8 next_index, u32 minrate)
2746 {
2747         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2748         char qeec_pl[MLXSW_REG_QEEC_LEN];
2749
2750         mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2751                             next_index);
2752         mlxsw_reg_qeec_mise_set(qeec_pl, true);
2753         mlxsw_reg_qeec_min_shaper_rate_set(qeec_pl, minrate);
2754
2755         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2756 }
2757
2758 int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
2759                               u8 switch_prio, u8 tclass)
2760 {
2761         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2762         char qtct_pl[MLXSW_REG_QTCT_LEN];
2763
2764         mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
2765                             tclass);
2766         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
2767 }
2768
2769 static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
2770 {
2771         int err, i;
2772
2773         /* Setup the elements hierarcy, so that each TC is linked to
2774          * one subgroup, which are all member in the same group.
2775          */
2776         err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2777                                     MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
2778                                     0);
2779         if (err)
2780                 return err;
2781         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2782                 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2783                                             MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
2784                                             0, false, 0);
2785                 if (err)
2786                         return err;
2787         }
2788         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2789                 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2790                                             MLXSW_REG_QEEC_HIERARCY_TC, i, i,
2791                                             false, 0);
2792                 if (err)
2793                         return err;
2794
2795                 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2796                                             MLXSW_REG_QEEC_HIERARCY_TC,
2797                                             i + 8, i,
2798                                             false, 0);
2799                 if (err)
2800                         return err;
2801         }
2802
2803         /* Make sure the max shaper is disabled in all hierarchies that
2804          * support it.
2805          */
2806         err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2807                                             MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
2808                                             MLXSW_REG_QEEC_MAS_DIS);
2809         if (err)
2810                 return err;
2811         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2812                 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2813                                                     MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
2814                                                     i, 0,
2815                                                     MLXSW_REG_QEEC_MAS_DIS);
2816                 if (err)
2817                         return err;
2818         }
2819         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2820                 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2821                                                     MLXSW_REG_QEEC_HIERARCY_TC,
2822                                                     i, i,
2823                                                     MLXSW_REG_QEEC_MAS_DIS);
2824                 if (err)
2825                         return err;
2826
2827                 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2828                                                     MLXSW_REG_QEEC_HIERARCY_TC,
2829                                                     i + 8, i,
2830                                                     MLXSW_REG_QEEC_MAS_DIS);
2831                 if (err)
2832                         return err;
2833         }
2834
2835         /* Configure the min shaper for multicast TCs. */
2836         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2837                 err = mlxsw_sp_port_min_bw_set(mlxsw_sp_port,
2838                                                MLXSW_REG_QEEC_HIERARCY_TC,
2839                                                i + 8, i,
2840                                                MLXSW_REG_QEEC_MIS_MIN);
2841                 if (err)
2842                         return err;
2843         }
2844
2845         /* Map all priorities to traffic class 0. */
2846         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2847                 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
2848                 if (err)
2849                         return err;
2850         }
2851
2852         return 0;
2853 }
2854
2855 static int mlxsw_sp_port_tc_mc_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
2856                                         bool enable)
2857 {
2858         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2859         char qtctm_pl[MLXSW_REG_QTCTM_LEN];
2860
2861         mlxsw_reg_qtctm_pack(qtctm_pl, mlxsw_sp_port->local_port, enable);
2862         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtctm), qtctm_pl);
2863 }
2864
2865 static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2866                                 bool split, u8 module, u8 width, u8 lane)
2867 {
2868         struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
2869         struct mlxsw_sp_port *mlxsw_sp_port;
2870         struct net_device *dev;
2871         int err;
2872
2873         err = mlxsw_core_port_init(mlxsw_sp->core, local_port);
2874         if (err) {
2875                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
2876                         local_port);
2877                 return err;
2878         }
2879
2880         dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
2881         if (!dev) {
2882                 err = -ENOMEM;
2883                 goto err_alloc_etherdev;
2884         }
2885         SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
2886         mlxsw_sp_port = netdev_priv(dev);
2887         mlxsw_sp_port->dev = dev;
2888         mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
2889         mlxsw_sp_port->local_port = local_port;
2890         mlxsw_sp_port->pvid = 1;
2891         mlxsw_sp_port->split = split;
2892         mlxsw_sp_port->mapping.module = module;
2893         mlxsw_sp_port->mapping.width = width;
2894         mlxsw_sp_port->mapping.lane = lane;
2895         mlxsw_sp_port->link.autoneg = 1;
2896         INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
2897         INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
2898
2899         mlxsw_sp_port->pcpu_stats =
2900                 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
2901         if (!mlxsw_sp_port->pcpu_stats) {
2902                 err = -ENOMEM;
2903                 goto err_alloc_stats;
2904         }
2905
2906         mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
2907                                         GFP_KERNEL);
2908         if (!mlxsw_sp_port->sample) {
2909                 err = -ENOMEM;
2910                 goto err_alloc_sample;
2911         }
2912
2913         INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw,
2914                           &update_stats_cache);
2915
2916         dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
2917         dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
2918
2919         err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane);
2920         if (err) {
2921                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
2922                         mlxsw_sp_port->local_port);
2923                 goto err_port_module_map;
2924         }
2925
2926         err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
2927         if (err) {
2928                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
2929                         mlxsw_sp_port->local_port);
2930                 goto err_port_swid_set;
2931         }
2932
2933         err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
2934         if (err) {
2935                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
2936                         mlxsw_sp_port->local_port);
2937                 goto err_dev_addr_init;
2938         }
2939
2940         netif_carrier_off(dev);
2941
2942         dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
2943                          NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
2944         dev->hw_features |= NETIF_F_HW_TC;
2945
2946         dev->min_mtu = 0;
2947         dev->max_mtu = ETH_MAX_MTU;
2948
2949         /* Each packet needs to have a Tx header (metadata) on top all other
2950          * headers.
2951          */
2952         dev->needed_headroom = MLXSW_TXHDR_LEN;
2953
2954         err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
2955         if (err) {
2956                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
2957                         mlxsw_sp_port->local_port);
2958                 goto err_port_system_port_mapping_set;
2959         }
2960
2961         err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
2962         if (err) {
2963                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
2964                         mlxsw_sp_port->local_port);
2965                 goto err_port_speed_by_width_set;
2966         }
2967
2968         err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
2969         if (err) {
2970                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
2971                         mlxsw_sp_port->local_port);
2972                 goto err_port_mtu_set;
2973         }
2974
2975         err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2976         if (err)
2977                 goto err_port_admin_status_set;
2978
2979         err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
2980         if (err) {
2981                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
2982                         mlxsw_sp_port->local_port);
2983                 goto err_port_buffers_init;
2984         }
2985
2986         err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
2987         if (err) {
2988                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
2989                         mlxsw_sp_port->local_port);
2990                 goto err_port_ets_init;
2991         }
2992
2993         err = mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, true);
2994         if (err) {
2995                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC MC mode\n",
2996                         mlxsw_sp_port->local_port);
2997                 goto err_port_tc_mc_mode;
2998         }
2999
3000         /* ETS and buffers must be initialized before DCB. */
3001         err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
3002         if (err) {
3003                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
3004                         mlxsw_sp_port->local_port);
3005                 goto err_port_dcb_init;
3006         }
3007
3008         err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
3009         if (err) {
3010                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
3011                         mlxsw_sp_port->local_port);
3012                 goto err_port_fids_init;
3013         }
3014
3015         err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port);
3016         if (err) {
3017                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n",
3018                         mlxsw_sp_port->local_port);
3019                 goto err_port_qdiscs_init;
3020         }
3021
3022         err = mlxsw_sp_port_nve_init(mlxsw_sp_port);
3023         if (err) {
3024                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize NVE\n",
3025                         mlxsw_sp_port->local_port);
3026                 goto err_port_nve_init;
3027         }
3028
3029         mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
3030         if (IS_ERR(mlxsw_sp_port_vlan)) {
3031                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
3032                         mlxsw_sp_port->local_port);
3033                 err = PTR_ERR(mlxsw_sp_port_vlan);
3034                 goto err_port_vlan_get;
3035         }
3036
3037         mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
3038         mlxsw_sp->ports[local_port] = mlxsw_sp_port;
3039         err = register_netdev(dev);
3040         if (err) {
3041                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
3042                         mlxsw_sp_port->local_port);
3043                 goto err_register_netdev;
3044         }
3045
3046         mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
3047                                 mlxsw_sp_port, dev, module + 1,
3048                                 mlxsw_sp_port->split, lane / width);
3049         mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0);
3050         return 0;
3051
3052 err_register_netdev:
3053         mlxsw_sp->ports[local_port] = NULL;
3054         mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
3055         mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
3056 err_port_vlan_get:
3057         mlxsw_sp_port_nve_fini(mlxsw_sp_port);
3058 err_port_nve_init:
3059         mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
3060 err_port_qdiscs_init:
3061         mlxsw_sp_port_fids_fini(mlxsw_sp_port);
3062 err_port_fids_init:
3063         mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
3064 err_port_dcb_init:
3065         mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false);
3066 err_port_tc_mc_mode:
3067 err_port_ets_init:
3068 err_port_buffers_init:
3069 err_port_admin_status_set:
3070 err_port_mtu_set:
3071 err_port_speed_by_width_set:
3072 err_port_system_port_mapping_set:
3073 err_dev_addr_init:
3074         mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
3075 err_port_swid_set:
3076         mlxsw_sp_port_module_unmap(mlxsw_sp_port);
3077 err_port_module_map:
3078         kfree(mlxsw_sp_port->sample);
3079 err_alloc_sample:
3080         free_percpu(mlxsw_sp_port->pcpu_stats);
3081 err_alloc_stats:
3082         free_netdev(dev);
3083 err_alloc_etherdev:
3084         mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3085         return err;
3086 }
3087
3088 static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
3089 {
3090         struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3091
3092         cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw);
3093         mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
3094         unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
3095         mlxsw_sp->ports[local_port] = NULL;
3096         mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
3097         mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
3098         mlxsw_sp_port_nve_fini(mlxsw_sp_port);
3099         mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
3100         mlxsw_sp_port_fids_fini(mlxsw_sp_port);
3101         mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
3102         mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false);
3103         mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
3104         mlxsw_sp_port_module_unmap(mlxsw_sp_port);
3105         kfree(mlxsw_sp_port->sample);
3106         free_percpu(mlxsw_sp_port->pcpu_stats);
3107         WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
3108         free_netdev(mlxsw_sp_port->dev);
3109         mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3110 }
3111
3112 static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
3113 {
3114         return mlxsw_sp->ports[local_port] != NULL;
3115 }
3116
3117 static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
3118 {
3119         int i;
3120
3121         for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
3122                 if (mlxsw_sp_port_created(mlxsw_sp, i))
3123                         mlxsw_sp_port_remove(mlxsw_sp, i);
3124         kfree(mlxsw_sp->port_to_module);
3125         kfree(mlxsw_sp->ports);
3126 }
3127
3128 static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
3129 {
3130         unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
3131         u8 module, width, lane;
3132         size_t alloc_size;
3133         int i;
3134         int err;
3135
3136         alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
3137         mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
3138         if (!mlxsw_sp->ports)
3139                 return -ENOMEM;
3140
3141         mlxsw_sp->port_to_module = kmalloc_array(max_ports, sizeof(int),
3142                                                  GFP_KERNEL);
3143         if (!mlxsw_sp->port_to_module) {
3144                 err = -ENOMEM;
3145                 goto err_port_to_module_alloc;
3146         }
3147
3148         for (i = 1; i < max_ports; i++) {
3149                 /* Mark as invalid */
3150                 mlxsw_sp->port_to_module[i] = -1;
3151
3152                 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
3153                                                     &width, &lane);
3154                 if (err)
3155                         goto err_port_module_info_get;
3156                 if (!width)
3157                         continue;
3158                 mlxsw_sp->port_to_module[i] = module;
3159                 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
3160                                            module, width, lane);
3161                 if (err)
3162                         goto err_port_create;
3163         }
3164         return 0;
3165
3166 err_port_create:
3167 err_port_module_info_get:
3168         for (i--; i >= 1; i--)
3169                 if (mlxsw_sp_port_created(mlxsw_sp, i))
3170                         mlxsw_sp_port_remove(mlxsw_sp, i);
3171         kfree(mlxsw_sp->port_to_module);
3172 err_port_to_module_alloc:
3173         kfree(mlxsw_sp->ports);
3174         return err;
3175 }
3176
3177 static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
3178 {
3179         u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
3180
3181         return local_port - offset;
3182 }
3183
3184 static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
3185                                       u8 module, unsigned int count)
3186 {
3187         u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
3188         int err, i;
3189
3190         for (i = 0; i < count; i++) {
3191                 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
3192                                            module, width, i * width);
3193                 if (err)
3194                         goto err_port_create;
3195         }
3196
3197         return 0;
3198
3199 err_port_create:
3200         for (i--; i >= 0; i--)
3201                 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3202                         mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
3203         return err;
3204 }
3205
3206 static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
3207                                          u8 base_port, unsigned int count)
3208 {
3209         u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
3210         int i;
3211
3212         /* Split by four means we need to re-create two ports, otherwise
3213          * only one.
3214          */
3215         count = count / 2;
3216
3217         for (i = 0; i < count; i++) {
3218                 local_port = base_port + i * 2;
3219                 if (mlxsw_sp->port_to_module[local_port] < 0)
3220                         continue;
3221                 module = mlxsw_sp->port_to_module[local_port];
3222
3223                 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
3224                                      width, 0);
3225         }
3226 }
3227
3228 static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
3229                                unsigned int count,
3230                                struct netlink_ext_ack *extack)
3231 {
3232         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3233         struct mlxsw_sp_port *mlxsw_sp_port;
3234         u8 module, cur_width, base_port;
3235         int i;
3236         int err;
3237
3238         mlxsw_sp_port = mlxsw_sp->ports[local_port];
3239         if (!mlxsw_sp_port) {
3240                 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3241                         local_port);
3242                 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
3243                 return -EINVAL;
3244         }
3245
3246         module = mlxsw_sp_port->mapping.module;
3247         cur_width = mlxsw_sp_port->mapping.width;
3248
3249         if (count != 2 && count != 4) {
3250                 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
3251                 NL_SET_ERR_MSG_MOD(extack, "Port can only be split into 2 or 4 ports");
3252                 return -EINVAL;
3253         }
3254
3255         if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
3256                 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
3257                 NL_SET_ERR_MSG_MOD(extack, "Port cannot be split further");
3258                 return -EINVAL;
3259         }
3260
3261         /* Make sure we have enough slave (even) ports for the split. */
3262         if (count == 2) {
3263                 base_port = local_port;
3264                 if (mlxsw_sp->ports[base_port + 1]) {
3265                         netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3266                         NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration");
3267                         return -EINVAL;
3268                 }
3269         } else {
3270                 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3271                 if (mlxsw_sp->ports[base_port + 1] ||
3272                     mlxsw_sp->ports[base_port + 3]) {
3273                         netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3274                         NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration");
3275                         return -EINVAL;
3276                 }
3277         }
3278
3279         for (i = 0; i < count; i++)
3280                 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3281                         mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
3282
3283         err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
3284         if (err) {
3285                 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
3286                 goto err_port_split_create;
3287         }
3288
3289         return 0;
3290
3291 err_port_split_create:
3292         mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
3293         return err;
3294 }
3295
3296 static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port,
3297                                  struct netlink_ext_ack *extack)
3298 {
3299         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3300         struct mlxsw_sp_port *mlxsw_sp_port;
3301         u8 cur_width, base_port;
3302         unsigned int count;
3303         int i;
3304
3305         mlxsw_sp_port = mlxsw_sp->ports[local_port];
3306         if (!mlxsw_sp_port) {
3307                 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3308                         local_port);
3309                 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
3310                 return -EINVAL;
3311         }
3312
3313         if (!mlxsw_sp_port->split) {
3314                 netdev_err(mlxsw_sp_port->dev, "Port was not split\n");
3315                 NL_SET_ERR_MSG_MOD(extack, "Port was not split");
3316                 return -EINVAL;
3317         }
3318
3319         cur_width = mlxsw_sp_port->mapping.width;
3320         count = cur_width == 1 ? 4 : 2;
3321
3322         base_port = mlxsw_sp_cluster_base_port_get(local_port);
3323
3324         /* Determine which ports to remove. */
3325         if (count == 2 && local_port >= base_port + 2)
3326                 base_port = base_port + 2;
3327
3328         for (i = 0; i < count; i++)
3329                 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3330                         mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
3331
3332         mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
3333
3334         return 0;
3335 }
3336
3337 static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
3338                                      char *pude_pl, void *priv)
3339 {
3340         struct mlxsw_sp *mlxsw_sp = priv;
3341         struct mlxsw_sp_port *mlxsw_sp_port;
3342         enum mlxsw_reg_pude_oper_status status;
3343         u8 local_port;
3344
3345         local_port = mlxsw_reg_pude_local_port_get(pude_pl);
3346         mlxsw_sp_port = mlxsw_sp->ports[local_port];
3347         if (!mlxsw_sp_port)
3348                 return;
3349
3350         status = mlxsw_reg_pude_oper_status_get(pude_pl);
3351         if (status == MLXSW_PORT_OPER_STATUS_UP) {
3352                 netdev_info(mlxsw_sp_port->dev, "link up\n");
3353                 netif_carrier_on(mlxsw_sp_port->dev);
3354         } else {
3355                 netdev_info(mlxsw_sp_port->dev, "link down\n");
3356                 netif_carrier_off(mlxsw_sp_port->dev);
3357         }
3358 }
3359
3360 static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
3361                                               u8 local_port, void *priv)
3362 {
3363         struct mlxsw_sp *mlxsw_sp = priv;
3364         struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3365         struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
3366
3367         if (unlikely(!mlxsw_sp_port)) {
3368                 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
3369                                      local_port);
3370                 return;
3371         }
3372
3373         skb->dev = mlxsw_sp_port->dev;
3374
3375         pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
3376         u64_stats_update_begin(&pcpu_stats->syncp);
3377         pcpu_stats->rx_packets++;
3378         pcpu_stats->rx_bytes += skb->len;
3379         u64_stats_update_end(&pcpu_stats->syncp);
3380
3381         skb->protocol = eth_type_trans(skb, skb->dev);
3382         netif_receive_skb(skb);
3383 }
3384
3385 static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
3386                                            void *priv)
3387 {
3388         skb->offload_fwd_mark = 1;
3389         return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
3390 }
3391
3392 static void mlxsw_sp_rx_listener_mr_mark_func(struct sk_buff *skb,
3393                                               u8 local_port, void *priv)
3394 {
3395         skb->offload_mr_fwd_mark = 1;
3396         skb->offload_fwd_mark = 1;
3397         return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
3398 }
3399
3400 static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
3401                                              void *priv)
3402 {
3403         struct mlxsw_sp *mlxsw_sp = priv;
3404         struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3405         struct psample_group *psample_group;
3406         u32 size;
3407
3408         if (unlikely(!mlxsw_sp_port)) {
3409                 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
3410                                      local_port);
3411                 goto out;
3412         }
3413         if (unlikely(!mlxsw_sp_port->sample)) {
3414                 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
3415                                      local_port);
3416                 goto out;
3417         }
3418
3419         size = mlxsw_sp_port->sample->truncate ?
3420                   mlxsw_sp_port->sample->trunc_size : skb->len;
3421
3422         rcu_read_lock();
3423         psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
3424         if (!psample_group)
3425                 goto out_unlock;
3426         psample_sample_packet(psample_group, skb, size,
3427                               mlxsw_sp_port->dev->ifindex, 0,
3428                               mlxsw_sp_port->sample->rate);
3429 out_unlock:
3430         rcu_read_unlock();
3431 out:
3432         consume_skb(skb);
3433 }
3434
3435 #define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl)  \
3436         MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
3437                   _is_ctrl, SP_##_trap_group, DISCARD)
3438
3439 #define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl)     \
3440         MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action,    \
3441                &nb