drivers/net/ethernet/mellanox/mlxsw/spectrum.c

   1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
   2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
   3
   4 #include <linux/kernel.h>
   5 #include <linux/module.h>
   6 #include <linux/types.h>
   7 #include <linux/pci.h>
   8 #include <linux/netdevice.h>
   9 #include <linux/etherdevice.h>
  10 #include <linux/ethtool.h>
  11 #include <linux/slab.h>
  12 #include <linux/device.h>
  13 #include <linux/skbuff.h>
  14 #include <linux/if_vlan.h>
  15 #include <linux/if_bridge.h>
  16 #include <linux/workqueue.h>
  17 #include <linux/jiffies.h>
  18 #include <linux/bitops.h>
  19 #include <linux/list.h>
  20 #include <linux/notifier.h>
  21 #include <linux/dcbnl.h>
  22 #include <linux/inetdevice.h>
  23 #include <linux/netlink.h>
  24 #include <linux/random.h>
  25 #include <net/switchdev.h>
  26 #include <net/pkt_cls.h>
  27 #include <net/tc_act/tc_mirred.h>
  28 #include <net/netevent.h>
  29 #include <net/tc_act/tc_sample.h>
  30 #include <net/addrconf.h>
  31
  32 #include "spectrum.h"
  33 #include "pci.h"
  34 #include "core.h"
  35 #include "reg.h"
  36 #include "port.h"
  37 #include "trap.h"
  38 #include "txheader.h"
  39 #include "spectrum_cnt.h"
  40 #include "spectrum_dpipe.h"
  41 #include "spectrum_acl_flex_actions.h"
  42 #include "spectrum_span.h"
  43 #include "../mlxfw/mlxfw.h"
  44
  45 #define MLXSW_SP_FWREV_MINOR_TO_BRANCH(minor) ((minor) / 100)
  46
  47 #define MLXSW_SP1_FWREV_MAJOR 13
  48 #define MLXSW_SP1_FWREV_MINOR 1910
  49 #define MLXSW_SP1_FWREV_SUBMINOR 622
  50 #define MLXSW_SP1_FWREV_CAN_RESET_MINOR 1702
  51
  52 static const struct mlxsw_fw_rev mlxsw_sp1_fw_rev = {
  53         .major = MLXSW_SP1_FWREV_MAJOR,
  54         .minor = MLXSW_SP1_FWREV_MINOR,
  55         .subminor = MLXSW_SP1_FWREV_SUBMINOR,
  56         .can_reset_minor = MLXSW_SP1_FWREV_CAN_RESET_MINOR,
  57 };
  58
  59 #define MLXSW_SP1_FW_FILENAME \
  60         "mellanox/mlxsw_spectrum-" __stringify(MLXSW_SP1_FWREV_MAJOR) \
  61         "." __stringify(MLXSW_SP1_FWREV_MINOR) \
  62         "." __stringify(MLXSW_SP1_FWREV_SUBMINOR) ".mfa2"
  63
  64 static const char mlxsw_sp1_driver_name[] = "mlxsw_spectrum";
  65 static const char mlxsw_sp2_driver_name[] = "mlxsw_spectrum2";
  66 static const char mlxsw_sp_driver_version[] = "1.0";
  67
  68 static const unsigned char mlxsw_sp1_mac_mask[ETH_ALEN] = {
  69         0xff, 0xff, 0xff, 0xff, 0xfc, 0x00
  70 };
  71 static const unsigned char mlxsw_sp2_mac_mask[ETH_ALEN] = {
  72         0xff, 0xff, 0xff, 0xff, 0xf0, 0x00
  73 };
  74
  75 /* tx_hdr_version
  76  * Tx header version.
  77  * Must be set to 1.
  78  */
  79 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
  80
  81 /* tx_hdr_ctl
  82  * Packet control type.
  83  * 0 - Ethernet control (e.g. EMADs, LACP)
  84  * 1 - Ethernet data
  85  */
  86 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
  87
  88 /* tx_hdr_proto
  89  * Packet protocol type. Must be set to 1 (Ethernet).
  90  */
  91 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
  92
  93 /* tx_hdr_rx_is_router
  94  * Packet is sent from the router. Valid for data packets only.
  95  */
  96 MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
  97
  98 /* tx_hdr_fid_valid
  99  * Indicates if the 'fid' field is valid and should be used for
 100  * forwarding lookup. Valid for data packets only.
 101  */
 102 MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
 103
 104 /* tx_hdr_swid
 105  * Switch partition ID. Must be set to 0.
 106  */
 107 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
 108
 109 /* tx_hdr_control_tclass
 110  * Indicates if the packet should use the control TClass and not one
 111  * of the data TClasses.
 112  */
 113 MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
 114
 115 /* tx_hdr_etclass
 116  * Egress TClass to be used on the egress device on the egress port.
 117  */
 118 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
 119
 120 /* tx_hdr_port_mid
 121  * Destination local port for unicast packets.
 122  * Destination multicast ID for multicast packets.
 123  *
 124  * Control packets are directed to a specific egress port, while data
 125  * packets are transmitted through the CPU port (0) into the switch partition,
 126  * where forwarding rules are applied.
 127  */
 128 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
 129
 130 /* tx_hdr_fid
 131  * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
 132  * set, otherwise calculated based on the packet's VID using VID to FID mapping.
 133  * Valid for data packets only.
 134  */
 135 MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
 136
 137 /* tx_hdr_type
 138  * 0 - Data packets
 139  * 6 - Control packets
 140  */
 141 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
 142
 143 struct mlxsw_sp_mlxfw_dev {
 144         struct mlxfw_dev mlxfw_dev;
 145         struct mlxsw_sp *mlxsw_sp;
 146 };
 147
 148 static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev,
 149                                     u16 component_index, u32 *p_max_size,
 150                                     u8 *p_align_bits, u16 *p_max_write_size)
 151 {
 152         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 153                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 154         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 155         char mcqi_pl[MLXSW_REG_MCQI_LEN];
 156         int err;
 157
 158         mlxsw_reg_mcqi_pack(mcqi_pl, component_index);
 159         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl);
 160         if (err)
 161                 return err;
 162         mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits,
 163                               p_max_write_size);
 164
 165         *p_align_bits = max_t(u8, *p_align_bits, 2);
 166         *p_max_write_size = min_t(u16, *p_max_write_size,
 167                                   MLXSW_REG_MCDA_MAX_DATA_LEN);
 168         return 0;
 169 }
 170
 171 static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
 172 {
 173         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 174                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 175         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 176         char mcc_pl[MLXSW_REG_MCC_LEN];
 177         u8 control_state;
 178         int err;
 179
 180         mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0);
 181         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
 182         if (err)
 183                 return err;
 184
 185         mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state);
 186         if (control_state != MLXFW_FSM_STATE_IDLE)
 187                 return -EBUSY;
 188
 189         mlxsw_reg_mcc_pack(mcc_pl,
 190                            MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
 191                            0, *fwhandle, 0);
 192         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
 193 }
 194
 195 static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev,
 196                                          u32 fwhandle, u16 component_index,
 197                                          u32 component_size)
 198 {
 199         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 200                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 201         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 202         char mcc_pl[MLXSW_REG_MCC_LEN];
 203
 204         mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
 205                            component_index, fwhandle, component_size);
 206         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
 207 }
 208
 209 static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev,
 210                                        u32 fwhandle, u8 *data, u16 size,
 211                                        u32 offset)
 212 {
 213         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 214                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 215         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 216         char mcda_pl[MLXSW_REG_MCDA_LEN];
 217
 218         mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data);
 219         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl);
 220 }
 221
 222 static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev,
 223                                          u32 fwhandle, u16 component_index)
 224 {
 225         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 226                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 227         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 228         char mcc_pl[MLXSW_REG_MCC_LEN];
 229
 230         mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
 231                            component_index, fwhandle, 0);
 232         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
 233 }
 234
 235 static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
 236 {
 237         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 238                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 239         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 240         char mcc_pl[MLXSW_REG_MCC_LEN];
 241
 242         mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0,
 243                            fwhandle, 0);
 244         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
 245 }
 246
 247 static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
 248                                     enum mlxfw_fsm_state *fsm_state,
 249                                     enum mlxfw_fsm_state_err *fsm_state_err)
 250 {
 251         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 252                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 253         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 254         char mcc_pl[MLXSW_REG_MCC_LEN];
 255         u8 control_state;
 256         u8 error_code;
 257         int err;
 258
 259         mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0);
 260         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
 261         if (err)
 262                 return err;
 263
 264         mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state);
 265         *fsm_state = control_state;
 266         *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
 267                                MLXFW_FSM_STATE_ERR_MAX);
 268         return 0;
 269 }
 270
 271 static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
 272 {
 273         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 274                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 275         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 276         char mcc_pl[MLXSW_REG_MCC_LEN];
 277
 278         mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0,
 279                            fwhandle, 0);
 280         mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
 281 }
 282
 283 static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
 284 {
 285         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 286                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 287         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 288         char mcc_pl[MLXSW_REG_MCC_LEN];
 289
 290         mlxsw_reg_mcc_pack(mcc_pl,
 291                            MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
 292                            fwhandle, 0);
 293         mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
 294 }
 295
 296 static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = {
 297         .component_query        = mlxsw_sp_component_query,
 298         .fsm_lock               = mlxsw_sp_fsm_lock,
 299         .fsm_component_update   = mlxsw_sp_fsm_component_update,
 300         .fsm_block_download     = mlxsw_sp_fsm_block_download,
 301         .fsm_component_verify   = mlxsw_sp_fsm_component_verify,
 302         .fsm_activate           = mlxsw_sp_fsm_activate,
 303         .fsm_query_state        = mlxsw_sp_fsm_query_state,
 304         .fsm_cancel             = mlxsw_sp_fsm_cancel,
 305         .fsm_release            = mlxsw_sp_fsm_release
 306 };
 307
 308 static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp,
 309                                    const struct firmware *firmware)
 310 {
 311         struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = {
 312                 .mlxfw_dev = {
 313                         .ops = &mlxsw_sp_mlxfw_dev_ops,
 314                         .psid = mlxsw_sp->bus_info->psid,
 315                         .psid_size = strlen(mlxsw_sp->bus_info->psid),
 316                 },
 317                 .mlxsw_sp = mlxsw_sp
 318         };
 319         int err;
 320
 321         mlxsw_core_fw_flash_start(mlxsw_sp->core);
 322         err = mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev, firmware);
 323         mlxsw_core_fw_flash_end(mlxsw_sp->core);
 324
 325         return err;
 326 }
 327
 328 static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp)
 329 {
 330         const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev;
 331         const struct mlxsw_fw_rev *req_rev = mlxsw_sp->req_rev;
 332         const char *fw_filename = mlxsw_sp->fw_filename;
 333         union devlink_param_value value;
 334         const struct firmware *firmware;
 335         int err;
 336
 337         /* Don't check if driver does not require it */
 338         if (!req_rev || !fw_filename)
 339                 return 0;
 340
 341         /* Don't check if devlink 'fw_load_policy' param is 'flash' */
 342         err = devlink_param_driverinit_value_get(priv_to_devlink(mlxsw_sp->core),
 343                                                  DEVLINK_PARAM_GENERIC_ID_FW_LOAD_POLICY,
 344                                                  &value);
 345         if (err)
 346                 return err;
 347         if (value.vu8 == DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_FLASH)
 348                 return 0;
 349
 350         /* Validate driver & FW are compatible */
 351         if (rev->major != req_rev->major) {
 352                 WARN(1, "Mismatch in major FW version [%d:%d] is never expected; Please contact support\n",
 353                      rev->major, req_rev->major);
 354                 return -EINVAL;
 355         }
 356         if (MLXSW_SP_FWREV_MINOR_TO_BRANCH(rev->minor) ==
 357             MLXSW_SP_FWREV_MINOR_TO_BRANCH(req_rev->minor) &&
 358             (rev->minor > req_rev->minor ||
 359              (rev->minor == req_rev->minor &&
 360               rev->subminor >= req_rev->subminor)))
 361                 return 0;
 362
 363         dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d is incompatible with the driver\n",
 364                  rev->major, rev->minor, rev->subminor);
 365         dev_info(mlxsw_sp->bus_info->dev, "Flashing firmware using file %s\n",
 366                  fw_filename);
 367
 368         err = request_firmware_direct(&firmware, fw_filename,
 369                                       mlxsw_sp->bus_info->dev);
 370         if (err) {
 371                 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n",
 372                         fw_filename);
 373                 return err;
 374         }
 375
 376         err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
 377         release_firmware(firmware);
 378         if (err)
 379                 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n");
 380
 381         /* On FW flash success, tell the caller FW reset is needed
 382          * if current FW supports it.
 383          */
 384         if (rev->minor >= req_rev->can_reset_minor)
 385                 return err ? err : -EAGAIN;
 386         else
 387                 return 0;
 388 }
 389
 390 int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
 391                               unsigned int counter_index, u64 *packets,
 392                               u64 *bytes)
 393 {
 394         char mgpc_pl[MLXSW_REG_MGPC_LEN];
 395         int err;
 396
 397         mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
 398                             MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
 399         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
 400         if (err)
 401                 return err;
 402         if (packets)
 403                 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
 404         if (bytes)
 405                 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
 406         return 0;
 407 }
 408
 409 static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
 410                                        unsigned int counter_index)
 411 {
 412         char mgpc_pl[MLXSW_REG_MGPC_LEN];
 413
 414         mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
 415                             MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
 416         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
 417 }
 418
 419 int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
 420                                 unsigned int *p_counter_index)
 421 {
 422         int err;
 423
 424         err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
 425                                      p_counter_index);
 426         if (err)
 427                 return err;
 428         err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
 429         if (err)
 430                 goto err_counter_clear;
 431         return 0;
 432
 433 err_counter_clear:
 434         mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
 435                               *p_counter_index);
 436         return err;
 437 }
 438
 439 void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
 440                                 unsigned int counter_index)
 441 {
 442          mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
 443                                counter_index);
 444 }
 445
 446 static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
 447                                      const struct mlxsw_tx_info *tx_info)
 448 {
 449         char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
 450
 451         memset(txhdr, 0, MLXSW_TXHDR_LEN);
 452
 453         mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
 454         mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
 455         mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
 456         mlxsw_tx_hdr_swid_set(txhdr, 0);
 457         mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
 458         mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
 459         mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
 460 }
 461
 462 enum mlxsw_reg_spms_state mlxsw_sp_stp_spms_state(u8 state)
 463 {
 464         switch (state) {
 465         case BR_STATE_FORWARDING:
 466                 return MLXSW_REG_SPMS_STATE_FORWARDING;
 467         case BR_STATE_LEARNING:
 468                 return MLXSW_REG_SPMS_STATE_LEARNING;
 469         case BR_STATE_LISTENING: /* fall-through */
 470         case BR_STATE_DISABLED: /* fall-through */
 471         case BR_STATE_BLOCKING:
 472                 return MLXSW_REG_SPMS_STATE_DISCARDING;
 473         default:
 474                 BUG();
 475         }
 476 }
 477
 478 int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
 479                               u8 state)
 480 {
 481         enum mlxsw_reg_spms_state spms_state = mlxsw_sp_stp_spms_state(state);
 482         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 483         char *spms_pl;
 484         int err;
 485
 486         spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
 487         if (!spms_pl)
 488                 return -ENOMEM;
 489         mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
 490         mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
 491
 492         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
 493         kfree(spms_pl);
 494         return err;
 495 }
 496
 497 static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
 498 {
 499         char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
 500         int err;
 501
 502         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
 503         if (err)
 504                 return err;
 505         mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
 506         return 0;
 507 }
 508
 509 static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
 510                                     bool enable, u32 rate)
 511 {
 512         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 513         char mpsc_pl[MLXSW_REG_MPSC_LEN];
 514
 515         mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
 516         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
 517 }
 518
 519 static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
 520                                           bool is_up)
 521 {
 522         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 523         char paos_pl[MLXSW_REG_PAOS_LEN];
 524
 525         mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
 526                             is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
 527                             MLXSW_PORT_ADMIN_STATUS_DOWN);
 528         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
 529 }
 530
 531 static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
 532                                       unsigned char *addr)
 533 {
 534         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 535         char ppad_pl[MLXSW_REG_PPAD_LEN];
 536
 537         mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
 538         mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
 539         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
 540 }
 541
 542 static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
 543 {
 544         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 545         unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
 546
 547         ether_addr_copy(addr, mlxsw_sp->base_mac);
 548         addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
 549         return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
 550 }
 551
 552 static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
 553 {
 554         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 555         char pmtu_pl[MLXSW_REG_PMTU_LEN];
 556         int max_mtu;
 557         int err;
 558
 559         mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
 560         mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
 561         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
 562         if (err)
 563                 return err;
 564         max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
 565
 566         if (mtu > max_mtu)
 567                 return -EINVAL;
 568
 569         mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
 570         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
 571 }
 572
 573 static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
 574 {
 575         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 576         char pspa_pl[MLXSW_REG_PSPA_LEN];
 577
 578         mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port);
 579         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
 580 }
 581
 582 int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
 583 {
 584         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 585         char svpe_pl[MLXSW_REG_SVPE_LEN];
 586
 587         mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
 588         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
 589 }
 590
 591 int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
 592                                    bool learn_enable)
 593 {
 594         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 595         char *spvmlr_pl;
 596         int err;
 597
 598         spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
 599         if (!spvmlr_pl)
 600                 return -ENOMEM;
 601         mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
 602                               learn_enable);
 603         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
 604         kfree(spvmlr_pl);
 605         return err;
 606 }
 607
 608 static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
 609                                     u16 vid)
 610 {
 611         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 612         char spvid_pl[MLXSW_REG_SPVID_LEN];
 613
 614         mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
 615         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
 616 }
 617
 618 static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
 619                                             bool allow)
 620 {
 621         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 622         char spaft_pl[MLXSW_REG_SPAFT_LEN];
 623
 624         mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
 625         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
 626 }
 627
 628 int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
 629 {
 630         int err;
 631
 632         if (!vid) {
 633                 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
 634                 if (err)
 635                         return err;
 636         } else {
 637                 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
 638                 if (err)
 639                         return err;
 640                 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
 641                 if (err)
 642                         goto err_port_allow_untagged_set;
 643         }
 644
 645         mlxsw_sp_port->pvid = vid;
 646         return 0;
 647
 648 err_port_allow_untagged_set:
 649         __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
 650         return err;
 651 }
 652
 653 static int
 654 mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
 655 {
 656         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 657         char sspr_pl[MLXSW_REG_SSPR_LEN];
 658
 659         mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
 660         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
 661 }
 662
 663 static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
 664                                          u8 local_port, u8 *p_module,
 665                                          u8 *p_width, u8 *p_lane)
 666 {
 667         char pmlp_pl[MLXSW_REG_PMLP_LEN];
 668         int err;
 669
 670         mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
 671         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
 672         if (err)
 673                 return err;
 674         *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
 675         *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
 676         *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
 677         return 0;
 678 }
 679
 680 static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port,
 681                                     u8 module, u8 width, u8 lane)
 682 {
 683         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 684         char pmlp_pl[MLXSW_REG_PMLP_LEN];
 685         int i;
 686
 687         mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
 688         mlxsw_reg_pmlp_width_set(pmlp_pl, width);
 689         for (i = 0; i < width; i++) {
 690                 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
 691                 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i);  /* Rx & Tx */
 692         }
 693
 694         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
 695 }
 696
 697 static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port)
 698 {
 699         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 700         char pmlp_pl[MLXSW_REG_PMLP_LEN];
 701
 702         mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
 703         mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
 704         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
 705 }
 706
 707 static int mlxsw_sp_port_open(struct net_device *dev)
 708 {
 709         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 710         int err;
 711
 712         err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
 713         if (err)
 714                 return err;
 715         netif_start_queue(dev);
 716         return 0;
 717 }
 718
 719 static int mlxsw_sp_port_stop(struct net_device *dev)
 720 {
 721         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 722
 723         netif_stop_queue(dev);
 724         return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
 725 }
 726
 727 static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
 728                                       struct net_device *dev)
 729 {
 730         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 731         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 732         struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
 733         const struct mlxsw_tx_info tx_info = {
 734                 .local_port = mlxsw_sp_port->local_port,
 735                 .is_emad = false,
 736         };
 737         u64 len;
 738         int err;
 739
 740         if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
 741                 return NETDEV_TX_BUSY;
 742
 743         if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
 744                 struct sk_buff *skb_orig = skb;
 745
 746                 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
 747                 if (!skb) {
 748                         this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
 749                         dev_kfree_skb_any(skb_orig);
 750                         return NETDEV_TX_OK;
 751                 }
 752                 dev_consume_skb_any(skb_orig);
 753         }
 754
 755         if (eth_skb_pad(skb)) {
 756                 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
 757                 return NETDEV_TX_OK;
 758         }
 759
 760         mlxsw_sp_txhdr_construct(skb, &tx_info);
 761         /* TX header is consumed by HW on the way so we shouldn't count its
 762          * bytes as being sent.
 763          */
 764         len = skb->len - MLXSW_TXHDR_LEN;
 765
 766         /* Due to a race we might fail here because of a full queue. In that
 767          * unlikely case we simply drop the packet.
 768          */
 769         err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
 770
 771         if (!err) {
 772                 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
 773                 u64_stats_update_begin(&pcpu_stats->syncp);
 774                 pcpu_stats->tx_packets++;
 775                 pcpu_stats->tx_bytes += len;
 776                 u64_stats_update_end(&pcpu_stats->syncp);
 777         } else {
 778                 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
 779                 dev_kfree_skb_any(skb);
 780         }
 781         return NETDEV_TX_OK;
 782 }
 783
 784 static void mlxsw_sp_set_rx_mode(struct net_device *dev)
 785 {
 786 }
 787
 788 static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
 789 {
 790         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 791         struct sockaddr *addr = p;
 792         int err;
 793
 794         if (!is_valid_ether_addr(addr->sa_data))
 795                 return -EADDRNOTAVAIL;
 796
 797         err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
 798         if (err)
 799                 return err;
 800         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
 801         return 0;
 802 }
 803
 804 static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
 805                                          int mtu)
 806 {
 807         return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
 808 }
 809
 810 #define MLXSW_SP_CELL_FACTOR 2  /* 2 * cell_size / (IPG + cell_size + 1) */
 811
 812 static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
 813                                   u16 delay)
 814 {
 815         delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
 816                                                             BITS_PER_BYTE));
 817         return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
 818                                                                    mtu);
 819 }
 820
 821 /* Maximum delay buffer needed in case of PAUSE frames, in bytes.
 822  * Assumes 100m cable and maximum MTU.
 823  */
 824 #define MLXSW_SP_PAUSE_DELAY 58752
 825
 826 static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
 827                                      u16 delay, bool pfc, bool pause)
 828 {
 829         if (pfc)
 830                 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
 831         else if (pause)
 832                 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
 833         else
 834                 return 0;
 835 }
 836
 837 static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
 838                                  bool lossy)
 839 {
 840         if (lossy)
 841                 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
 842         else
 843                 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
 844                                                     thres);
 845 }
 846
 847 int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
 848                                  u8 *prio_tc, bool pause_en,
 849                                  struct ieee_pfc *my_pfc)
 850 {
 851         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 852         u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
 853         u16 delay = !!my_pfc ? my_pfc->delay : 0;
 854         char pbmc_pl[MLXSW_REG_PBMC_LEN];
 855         int i, j, err;
 856
 857         mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
 858         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
 859         if (err)
 860                 return err;
 861
 862         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
 863                 bool configure = false;
 864                 bool pfc = false;
 865                 bool lossy;
 866                 u16 thres;
 867
 868                 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
 869                         if (prio_tc[j] == i) {
 870                                 pfc = pfc_en & BIT(j);
 871                                 configure = true;
 872                                 break;
 873                         }
 874                 }
 875
 876                 if (!configure)
 877                         continue;
 878
 879                 lossy = !(pfc || pause_en);
 880                 thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
 881                 delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc,
 882                                                   pause_en);
 883                 mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy);
 884         }
 885
 886         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
 887 }
 888
 889 static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
 890                                       int mtu, bool pause_en)
 891 {
 892         u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
 893         bool dcb_en = !!mlxsw_sp_port->dcb.ets;
 894         struct ieee_pfc *my_pfc;
 895         u8 *prio_tc;
 896
 897         prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
 898         my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
 899
 900         return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
 901                                             pause_en, my_pfc);
 902 }
 903
 904 static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
 905 {
 906         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 907         bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
 908         int err;
 909
 910         err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
 911         if (err)
 912                 return err;
 913         err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
 914         if (err)
 915                 goto err_span_port_mtu_update;
 916         err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
 917         if (err)
 918                 goto err_port_mtu_set;
 919         dev->mtu = mtu;
 920         return 0;
 921
 922 err_port_mtu_set:
 923         mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
 924 err_span_port_mtu_update:
 925         mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
 926         return err;
 927 }
 928
 929 static int
 930 mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
 931                              struct rtnl_link_stats64 *stats)
 932 {
 933         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 934         struct mlxsw_sp_port_pcpu_stats *p;
 935         u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
 936         u32 tx_dropped = 0;
 937         unsigned int start;
 938         int i;
 939
 940         for_each_possible_cpu(i) {
 941                 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
 942                 do {
 943                         start = u64_stats_fetch_begin_irq(&p->syncp);
 944                         rx_packets      = p->rx_packets;
 945                         rx_bytes        = p->rx_bytes;
 946                         tx_packets      = p->tx_packets;
 947                         tx_bytes        = p->tx_bytes;
 948                 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
 949
 950                 stats->rx_packets       += rx_packets;
 951                 stats->rx_bytes         += rx_bytes;
 952                 stats->tx_packets       += tx_packets;
 953                 stats->tx_bytes         += tx_bytes;
 954                 /* tx_dropped is u32, updated without syncp protection. */
 955                 tx_dropped      += p->tx_dropped;
 956         }
 957         stats->tx_dropped       = tx_dropped;
 958         return 0;
 959 }
 960
 961 static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
 962 {
 963         switch (attr_id) {
 964         case IFLA_OFFLOAD_XSTATS_CPU_HIT:
 965                 return true;
 966         }
 967
 968         return false;
 969 }
 970
 971 static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
 972                                            void *sp)
 973 {
 974         switch (attr_id) {
 975         case IFLA_OFFLOAD_XSTATS_CPU_HIT:
 976                 return mlxsw_sp_port_get_sw_stats64(dev, sp);
 977         }
 978
 979         return -EINVAL;
 980 }
 981
 982 static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
 983                                        int prio, char *ppcnt_pl)
 984 {
 985         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 986         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 987
 988         mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
 989         return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
 990 }
 991
 992 static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
 993                                       struct rtnl_link_stats64 *stats)
 994 {
 995         char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
 996         int err;
 997
 998         err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
 999                                           0, ppcnt_pl);
1000         if (err)
1001                 goto out;
1002
1003         stats->tx_packets =
1004                 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
1005         stats->rx_packets =
1006                 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
1007         stats->tx_bytes =
1008                 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
1009         stats->rx_bytes =
1010                 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
1011         stats->multicast =
1012                 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
1013
1014         stats->rx_crc_errors =
1015                 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
1016         stats->rx_frame_errors =
1017                 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
1018
1019         stats->rx_length_errors = (
1020                 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
1021                 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
1022                 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
1023
1024         stats->rx_errors = (stats->rx_crc_errors +
1025                 stats->rx_frame_errors + stats->rx_length_errors);
1026
1027 out:
1028         return err;
1029 }
1030
1031 static void
1032 mlxsw_sp_port_get_hw_xstats(struct net_device *dev,
1033                             struct mlxsw_sp_port_xstats *xstats)
1034 {
1035         char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1036         int err, i;
1037
1038         err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0,
1039                                           ppcnt_pl);
1040         if (!err)
1041                 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl);
1042
1043         for (i = 0; i < TC_MAX_QUEUE; i++) {
1044                 err = mlxsw_sp_port_get_stats_raw(dev,
1045                                                   MLXSW_REG_PPCNT_TC_CONG_TC,
1046                                                   i, ppcnt_pl);
1047                 if (!err)
1048                         xstats->wred_drop[i] =
1049                                 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl);
1050
1051                 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT,
1052                                                   i, ppcnt_pl);
1053                 if (err)
1054                         continue;
1055
1056                 xstats->backlog[i] =
1057                         mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl);
1058                 xstats->tail_drop[i] =
1059                         mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl);
1060         }
1061
1062         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1063                 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_PRIO_CNT,
1064                                                   i, ppcnt_pl);
1065                 if (err)
1066                         continue;
1067
1068                 xstats->tx_packets[i] = mlxsw_reg_ppcnt_tx_frames_get(ppcnt_pl);
1069                 xstats->tx_bytes[i] = mlxsw_reg_ppcnt_tx_octets_get(ppcnt_pl);
1070         }
1071 }
1072
1073 static void update_stats_cache(struct work_struct *work)
1074 {
1075         struct mlxsw_sp_port *mlxsw_sp_port =
1076                 container_of(work, struct mlxsw_sp_port,
1077                              periodic_hw_stats.update_dw.work);
1078
1079         if (!netif_carrier_ok(mlxsw_sp_port->dev))
1080                 goto out;
1081
1082         mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
1083                                    &mlxsw_sp_port->periodic_hw_stats.stats);
1084         mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev,
1085                                     &mlxsw_sp_port->periodic_hw_stats.xstats);
1086
1087 out:
1088         mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw,
1089                                MLXSW_HW_STATS_UPDATE_TIME);
1090 }
1091
1092 /* Return the stats from a cache that is updated periodically,
1093  * as this function might get called in an atomic context.
1094  */
1095 static void
1096 mlxsw_sp_port_get_stats64(struct net_device *dev,
1097                           struct rtnl_link_stats64 *stats)
1098 {
1099         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1100
1101         memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats));
1102 }
1103
1104 static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
1105                                     u16 vid_begin, u16 vid_end,
1106                                     bool is_member, bool untagged)
1107 {
1108         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1109         char *spvm_pl;
1110         int err;
1111
1112         spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1113         if (!spvm_pl)
1114                 return -ENOMEM;
1115
1116         mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1117                             vid_end, is_member, untagged);
1118         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1119         kfree(spvm_pl);
1120         return err;
1121 }
1122
1123 int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1124                            u16 vid_end, bool is_member, bool untagged)
1125 {
1126         u16 vid, vid_e;
1127         int err;
1128
1129         for (vid = vid_begin; vid <= vid_end;
1130              vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1131                 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1132                             vid_end);
1133
1134                 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1135                                                is_member, untagged);
1136                 if (err)
1137                         return err;
1138         }
1139
1140         return 0;
1141 }
1142
1143 static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port,
1144                                      bool flush_default)
1145 {
1146         struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
1147
1148         list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
1149                                  &mlxsw_sp_port->vlans_list, list) {
1150                 if (!flush_default &&
1151                     mlxsw_sp_port_vlan->vid == MLXSW_SP_DEFAULT_VID)
1152                         continue;
1153                 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
1154         }
1155 }
1156
1157 static void
1158 mlxsw_sp_port_vlan_cleanup(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1159 {
1160         if (mlxsw_sp_port_vlan->bridge_port)
1161                 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
1162         else if (mlxsw_sp_port_vlan->fid)
1163                 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
1164 }
1165
1166 struct mlxsw_sp_port_vlan *
1167 mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1168 {
1169         struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1170         bool untagged = vid == MLXSW_SP_DEFAULT_VID;
1171         int err;
1172
1173         mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1174         if (mlxsw_sp_port_vlan)
1175                 return ERR_PTR(-EEXIST);
1176
1177         err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
1178         if (err)
1179                 return ERR_PTR(err);
1180
1181         mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
1182         if (!mlxsw_sp_port_vlan) {
1183                 err = -ENOMEM;
1184                 goto err_port_vlan_alloc;
1185         }
1186
1187         mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
1188         mlxsw_sp_port_vlan->vid = vid;
1189         list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
1190
1191         return mlxsw_sp_port_vlan;
1192
1193 err_port_vlan_alloc:
1194         mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1195         return ERR_PTR(err);
1196 }
1197
1198 void mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1199 {
1200         struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
1201         u16 vid = mlxsw_sp_port_vlan->vid;
1202
1203         mlxsw_sp_port_vlan_cleanup(mlxsw_sp_port_vlan);
1204         list_del(&mlxsw_sp_port_vlan->list);
1205         kfree(mlxsw_sp_port_vlan);
1206         mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1207 }
1208
1209 static int mlxsw_sp_port_add_vid(struct net_device *dev,
1210                                  __be16 __always_unused proto, u16 vid)
1211 {
1212         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1213
1214         /* VLAN 0 is added to HW filter when device goes up, but it is
1215          * reserved in our case, so simply return.
1216          */
1217         if (!vid)
1218                 return 0;
1219
1220         return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid));
1221 }
1222
1223 static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1224                                   __be16 __always_unused proto, u16 vid)
1225 {
1226         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1227         struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1228
1229         /* VLAN 0 is removed from HW filter when device goes down, but
1230          * it is reserved in our case, so simply return.
1231          */
1232         if (!vid)
1233                 return 0;
1234
1235         mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1236         if (!mlxsw_sp_port_vlan)
1237                 return 0;
1238         mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
1239
1240         return 0;
1241 }
1242
1243 static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
1244                                             size_t len)
1245 {
1246         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1247
1248         return mlxsw_core_port_get_phys_port_name(mlxsw_sp_port->mlxsw_sp->core,
1249                                                   mlxsw_sp_port->local_port,
1250                                                   name, len);
1251 }
1252
1253 static struct mlxsw_sp_port_mall_tc_entry *
1254 mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1255                                  unsigned long cookie) {
1256         struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1257
1258         list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1259                 if (mall_tc_entry->cookie == cookie)
1260                         return mall_tc_entry;
1261
1262         return NULL;
1263 }
1264
1265 static int
1266 mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1267                                       struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
1268                                       const struct tc_action *a,
1269                                       bool ingress)
1270 {
1271         enum mlxsw_sp_span_type span_type;
1272         struct net_device *to_dev;
1273
1274         to_dev = tcf_mirred_dev(a);
1275         if (!to_dev) {
1276                 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1277                 return -EINVAL;
1278         }
1279
1280         mirror->ingress = ingress;
1281         span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1282         return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_dev, span_type,
1283                                         true, &mirror->span_id);
1284 }
1285
1286 static void
1287 mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1288                                       struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1289 {
1290         enum mlxsw_sp_span_type span_type;
1291
1292         span_type = mirror->ingress ?
1293                         MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1294         mlxsw_sp_span_mirror_del(mlxsw_sp_port, mirror->span_id,
1295                                  span_type, true);
1296 }
1297
1298 static int
1299 mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1300                                       struct tc_cls_matchall_offload *cls,
1301                                       const struct tc_action *a,
1302                                       bool ingress)
1303 {
1304         int err;
1305
1306         if (!mlxsw_sp_port->sample)
1307                 return -EOPNOTSUPP;
1308         if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1309                 netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1310                 return -EEXIST;
1311         }
1312         if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) {
1313                 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1314                 return -EOPNOTSUPP;
1315         }
1316
1317         rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1318                            tcf_sample_psample_group(a));
1319         mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a);
1320         mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a);
1321         mlxsw_sp_port->sample->rate = tcf_sample_rate(a);
1322
1323         err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a));
1324         if (err)
1325                 goto err_port_sample_set;
1326         return 0;
1327
1328 err_port_sample_set:
1329         RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1330         return err;
1331 }
1332
1333 static void
1334 mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1335 {
1336         if (!mlxsw_sp_port->sample)
1337                 return;
1338
1339         mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1340         RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1341 }
1342
1343 static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1344                                           struct tc_cls_matchall_offload *f,
1345                                           bool ingress)
1346 {
1347         struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1348         __be16 protocol = f->common.protocol;
1349         const struct tc_action *a;
1350         int err;
1351
1352         if (!tcf_exts_has_one_action(f->exts)) {
1353                 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
1354                 return -EOPNOTSUPP;
1355         }
1356
1357         mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1358         if (!mall_tc_entry)
1359                 return -ENOMEM;
1360         mall_tc_entry->cookie = f->cookie;
1361
1362         a = tcf_exts_first_action(f->exts);
1363
1364         if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) {
1365                 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1366
1367                 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1368                 mirror = &mall_tc_entry->mirror;
1369                 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1370                                                             mirror, a, ingress);
1371         } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) {
1372                 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
1373                 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, f,
1374                                                             a, ingress);
1375         } else {
1376                 err = -EOPNOTSUPP;
1377         }
1378
1379         if (err)
1380                 goto err_add_action;
1381
1382         list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
1383         return 0;
1384
1385 err_add_action:
1386         kfree(mall_tc_entry);
1387         return err;
1388 }
1389
1390 static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1391                                            struct tc_cls_matchall_offload *f)
1392 {
1393         struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1394
1395         mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
1396                                                          f->cookie);
1397         if (!mall_tc_entry) {
1398                 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1399                 return;
1400         }
1401         list_del(&mall_tc_entry->list);
1402
1403         switch (mall_tc_entry->type) {
1404         case MLXSW_SP_PORT_MALL_MIRROR:
1405                 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1406                                                       &mall_tc_entry->mirror);
1407                 break;
1408         case MLXSW_SP_PORT_MALL_SAMPLE:
1409                 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1410                 break;
1411         default:
1412                 WARN_ON(1);
1413         }
1414
1415         kfree(mall_tc_entry);
1416 }
1417
1418 static int mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1419                                           struct tc_cls_matchall_offload *f,
1420                                           bool ingress)
1421 {
1422         switch (f->command) {
1423         case TC_CLSMATCHALL_REPLACE:
1424                 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port, f,
1425                                                       ingress);
1426         case TC_CLSMATCHALL_DESTROY:
1427                 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port, f);
1428                 return 0;
1429         default:
1430                 return -EOPNOTSUPP;
1431         }
1432 }
1433
1434 static int
1435 mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_acl_block *acl_block,
1436                              struct tc_cls_flower_offload *f)
1437 {
1438         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_acl_block_mlxsw_sp(acl_block);
1439
1440         switch (f->command) {
1441         case TC_CLSFLOWER_REPLACE:
1442                 return mlxsw_sp_flower_replace(mlxsw_sp, acl_block, f);
1443         case TC_CLSFLOWER_DESTROY:
1444                 mlxsw_sp_flower_destroy(mlxsw_sp, acl_block, f);
1445                 return 0;
1446         case TC_CLSFLOWER_STATS:
1447                 return mlxsw_sp_flower_stats(mlxsw_sp, acl_block, f);
1448         case TC_CLSFLOWER_TMPLT_CREATE:
1449                 return mlxsw_sp_flower_tmplt_create(mlxsw_sp, acl_block, f);
1450         case TC_CLSFLOWER_TMPLT_DESTROY:
1451                 mlxsw_sp_flower_tmplt_destroy(mlxsw_sp, acl_block, f);
1452                 return 0;
1453         default:
1454                 return -EOPNOTSUPP;
1455         }
1456 }
1457
1458 static int mlxsw_sp_setup_tc_block_cb_matchall(enum tc_setup_type type,
1459                                                void *type_data,
1460                                                void *cb_priv, bool ingress)
1461 {
1462         struct mlxsw_sp_port *mlxsw_sp_port = cb_priv;
1463
1464         switch (type) {
1465         case TC_SETUP_CLSMATCHALL:
1466                 if (!tc_cls_can_offload_and_chain0(mlxsw_sp_port->dev,
1467                                                    type_data))
1468                         return -EOPNOTSUPP;
1469
1470                 return mlxsw_sp_setup_tc_cls_matchall(mlxsw_sp_port, type_data,
1471                                                       ingress);
1472         case TC_SETUP_CLSFLOWER:
1473                 return 0;
1474         default:
1475                 return -EOPNOTSUPP;
1476         }
1477 }
1478
1479 static int mlxsw_sp_setup_tc_block_cb_matchall_ig(enum tc_setup_type type,
1480                                                   void *type_data,
1481                                                   void *cb_priv)
1482 {
1483         return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1484                                                    cb_priv, true);
1485 }
1486
1487 static int mlxsw_sp_setup_tc_block_cb_matchall_eg(enum tc_setup_type type,
1488                                                   void *type_data,
1489                                                   void *cb_priv)
1490 {
1491         return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1492                                                    cb_priv, false);
1493 }
1494
1495 static int mlxsw_sp_setup_tc_block_cb_flower(enum tc_setup_type type,
1496                                              void *type_data, void *cb_priv)
1497 {
1498         struct mlxsw_sp_acl_block *acl_block = cb_priv;
1499
1500         switch (type) {
1501         case TC_SETUP_CLSMATCHALL:
1502                 return 0;
1503         case TC_SETUP_CLSFLOWER:
1504                 if (mlxsw_sp_acl_block_disabled(acl_block))
1505                         return -EOPNOTSUPP;
1506
1507                 return mlxsw_sp_setup_tc_cls_flower(acl_block, type_data);
1508         default:
1509                 return -EOPNOTSUPP;
1510         }
1511 }
1512
1513 static int
1514 mlxsw_sp_setup_tc_block_flower_bind(struct mlxsw_sp_port *mlxsw_sp_port,
1515                                     struct tcf_block *block, bool ingress,
1516                                     struct netlink_ext_ack *extack)
1517 {
1518         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1519         struct mlxsw_sp_acl_block *acl_block;
1520         struct tcf_block_cb *block_cb;
1521         int err;
1522
1523         block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower,
1524                                        mlxsw_sp);
1525         if (!block_cb) {
1526                 acl_block = mlxsw_sp_acl_block_create(mlxsw_sp, block->net);
1527                 if (!acl_block)
1528                         return -ENOMEM;
1529                 block_cb = __tcf_block_cb_register(block,
1530                                                    mlxsw_sp_setup_tc_block_cb_flower,
1531                                                    mlxsw_sp, acl_block, extack);
1532                 if (IS_ERR(block_cb)) {
1533                         err = PTR_ERR(block_cb);
1534                         goto err_cb_register;
1535                 }
1536         } else {
1537                 acl_block = tcf_block_cb_priv(block_cb);
1538         }
1539         tcf_block_cb_incref(block_cb);
1540         err = mlxsw_sp_acl_block_bind(mlxsw_sp, acl_block,
1541                                       mlxsw_sp_port, ingress);
1542         if (err)
1543                 goto err_block_bind;
1544
1545         if (ingress)
1546                 mlxsw_sp_port->ing_acl_block = acl_block;
1547         else
1548                 mlxsw_sp_port->eg_acl_block = acl_block;
1549
1550         return 0;
1551
1552 err_block_bind:
1553         if (!tcf_block_cb_decref(block_cb)) {
1554                 __tcf_block_cb_unregister(block, block_cb);
1555 err_cb_register:
1556                 mlxsw_sp_acl_block_destroy(acl_block);
1557         }
1558         return err;
1559 }
1560
1561 static void
1562 mlxsw_sp_setup_tc_block_flower_unbind(struct mlxsw_sp_port *mlxsw_sp_port,
1563                                       struct tcf_block *block, bool ingress)
1564 {
1565         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1566         struct mlxsw_sp_acl_block *acl_block;
1567         struct tcf_block_cb *block_cb;
1568         int err;
1569
1570         block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower,
1571                                        mlxsw_sp);
1572         if (!block_cb)
1573                 return;
1574
1575         if (ingress)
1576                 mlxsw_sp_port->ing_acl_block = NULL;
1577         else
1578                 mlxsw_sp_port->eg_acl_block = NULL;
1579
1580         acl_block = tcf_block_cb_priv(block_cb);
1581         err = mlxsw_sp_acl_block_unbind(mlxsw_sp, acl_block,
1582                                         mlxsw_sp_port, ingress);
1583         if (!err && !tcf_block_cb_decref(block_cb)) {
1584                 __tcf_block_cb_unregister(block, block_cb);
1585                 mlxsw_sp_acl_block_destroy(acl_block);
1586         }
1587 }
1588
1589 static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port,
1590                                    struct tc_block_offload *f)
1591 {
1592         tc_setup_cb_t *cb;
1593         bool ingress;
1594         int err;
1595
1596         if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) {
1597                 cb = mlxsw_sp_setup_tc_block_cb_matchall_ig;
1598                 ingress = true;
1599         } else if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_EGRESS) {
1600                 cb = mlxsw_sp_setup_tc_block_cb_matchall_eg;
1601                 ingress = false;
1602         } else {
1603                 return -EOPNOTSUPP;
1604         }
1605
1606         switch (f->command) {
1607         case TC_BLOCK_BIND:
1608                 err = tcf_block_cb_register(f->block, cb, mlxsw_sp_port,
1609                                             mlxsw_sp_port, f->extack);
1610                 if (err)
1611                         return err;
1612                 err = mlxsw_sp_setup_tc_block_flower_bind(mlxsw_sp_port,
1613                                                           f->block, ingress,
1614                                                           f->extack);
1615                 if (err) {
1616                         tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1617                         return err;
1618                 }
1619                 return 0;
1620         case TC_BLOCK_UNBIND:
1621                 mlxsw_sp_setup_tc_block_flower_unbind(mlxsw_sp_port,
1622                                                       f->block, ingress);
1623                 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1624                 return 0;
1625         default:
1626                 return -EOPNOTSUPP;
1627         }
1628 }
1629
1630 static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type,
1631                              void *type_data)
1632 {
1633         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1634
1635         switch (type) {
1636         case TC_SETUP_BLOCK:
1637                 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data);
1638         case TC_SETUP_QDISC_RED:
1639                 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data);
1640         case TC_SETUP_QDISC_PRIO:
1641                 return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data);
1642         default:
1643                 return -EOPNOTSUPP;
1644         }
1645 }
1646
1647
1648 static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable)
1649 {
1650         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1651
1652         if (!enable) {
1653                 if (mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->ing_acl_block) ||
1654                     mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->eg_acl_block) ||
1655                     !list_empty(&mlxsw_sp_port->mall_tc_list)) {
1656                         netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n");
1657                         return -EINVAL;
1658                 }
1659                 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->ing_acl_block);
1660                 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->eg_acl_block);
1661         } else {
1662                 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->ing_acl_block);
1663                 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->eg_acl_block);
1664         }
1665         return 0;
1666 }
1667
1668 typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable);
1669
1670 static int mlxsw_sp_handle_feature(struct net_device *dev,
1671                                    netdev_features_t wanted_features,
1672                                    netdev_features_t feature,
1673                                    mlxsw_sp_feature_handler feature_handler)
1674 {
1675         netdev_features_t changes = wanted_features ^ dev->features;
1676         bool enable = !!(wanted_features & feature);
1677         int err;
1678
1679         if (!(changes & feature))
1680                 return 0;
1681
1682         err = feature_handler(dev, enable);
1683         if (err) {
1684                 netdev_err(dev, "%s feature %pNF failed, err %d\n",
1685                            enable ? "Enable" : "Disable", &feature, err);
1686                 return err;
1687         }
1688
1689         if (enable)
1690                 dev->features |= feature;
1691         else
1692                 dev->features &= ~feature;
1693
1694         return 0;
1695 }
1696 static int mlxsw_sp_set_features(struct net_device *dev,
1697                                  netdev_features_t features)
1698 {
1699         return mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC,
1700                                        mlxsw_sp_feature_hw_tc);
1701 }
1702
1703 static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1704         .ndo_open               = mlxsw_sp_port_open,
1705         .ndo_stop               = mlxsw_sp_port_stop,
1706         .ndo_start_xmit         = mlxsw_sp_port_xmit,
1707         .ndo_setup_tc           = mlxsw_sp_setup_tc,
1708         .ndo_set_rx_mode        = mlxsw_sp_set_rx_mode,
1709         .ndo_set_mac_address    = mlxsw_sp_port_set_mac_address,
1710         .ndo_change_mtu         = mlxsw_sp_port_change_mtu,
1711         .ndo_get_stats64        = mlxsw_sp_port_get_stats64,
1712         .ndo_has_offload_stats  = mlxsw_sp_port_has_offload_stats,
1713         .ndo_get_offload_stats  = mlxsw_sp_port_get_offload_stats,
1714         .ndo_vlan_rx_add_vid    = mlxsw_sp_port_add_vid,
1715         .ndo_vlan_rx_kill_vid   = mlxsw_sp_port_kill_vid,
1716         .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
1717         .ndo_set_features       = mlxsw_sp_set_features,
1718 };
1719
1720 static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1721                                       struct ethtool_drvinfo *drvinfo)
1722 {
1723         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1724         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1725
1726         strlcpy(drvinfo->driver, mlxsw_sp->bus_info->device_kind,
1727                 sizeof(drvinfo->driver));
1728         strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1729                 sizeof(drvinfo->version));
1730         snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1731                  "%d.%d.%d",
1732                  mlxsw_sp->bus_info->fw_rev.major,
1733                  mlxsw_sp->bus_info->fw_rev.minor,
1734                  mlxsw_sp->bus_info->fw_rev.subminor);
1735         strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1736                 sizeof(drvinfo->bus_info));
1737 }
1738
1739 static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1740                                          struct ethtool_pauseparam *pause)
1741 {
1742         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1743
1744         pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1745         pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1746 }
1747
1748 static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1749                                    struct ethtool_pauseparam *pause)
1750 {
1751         char pfcc_pl[MLXSW_REG_PFCC_LEN];
1752
1753         mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1754         mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1755         mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1756
1757         return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1758                                pfcc_pl);
1759 }
1760
1761 static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1762                                         struct ethtool_pauseparam *pause)
1763 {
1764         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1765         bool pause_en = pause->tx_pause || pause->rx_pause;
1766         int err;
1767
1768         if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1769                 netdev_err(dev, "PFC already enabled on port\n");
1770                 return -EINVAL;
1771         }
1772
1773         if (pause->autoneg) {
1774                 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1775                 return -EINVAL;
1776         }
1777
1778         err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1779         if (err) {
1780                 netdev_err(dev, "Failed to configure port's headroom\n");
1781                 return err;
1782         }
1783
1784         err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1785         if (err) {
1786                 netdev_err(dev, "Failed to set PAUSE parameters\n");
1787                 goto err_port_pause_configure;
1788         }
1789
1790         mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1791         mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1792
1793         return 0;
1794
1795 err_port_pause_configure:
1796         pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1797         mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1798         return err;
1799 }
1800
1801 struct mlxsw_sp_port_hw_stats {
1802         char str[ETH_GSTRING_LEN];
1803         u64 (*getter)(const char *payload);
1804         bool cells_bytes;
1805 };
1806
1807 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
1808         {
1809                 .str = "a_frames_transmitted_ok",
1810                 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1811         },
1812         {
1813                 .str = "a_frames_received_ok",
1814                 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1815         },
1816         {
1817                 .str = "a_frame_check_sequence_errors",
1818                 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1819         },
1820         {
1821                 .str = "a_alignment_errors",
1822                 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1823         },
1824         {
1825                 .str = "a_octets_transmitted_ok",
1826                 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1827         },
1828         {
1829                 .str = "a_octets_received_ok",
1830                 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1831         },
1832         {
1833                 .str = "a_multicast_frames_xmitted_ok",
1834                 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1835         },
1836         {
1837                 .str = "a_broadcast_frames_xmitted_ok",
1838                 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1839         },
1840         {
1841                 .str = "a_multicast_frames_received_ok",
1842                 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1843         },
1844         {
1845                 .str = "a_broadcast_frames_received_ok",
1846                 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1847         },
1848         {
1849                 .str = "a_in_range_length_errors",
1850                 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1851         },
1852         {
1853                 .str = "a_out_of_range_length_field",
1854                 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1855         },
1856         {
1857                 .str = "a_frame_too_long_errors",
1858                 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1859         },
1860         {
1861                 .str = "a_symbol_error_during_carrier",
1862                 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1863         },
1864         {
1865                 .str = "a_mac_control_frames_transmitted",
1866                 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1867         },
1868         {
1869                 .str = "a_mac_control_frames_received",
1870                 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1871         },
1872         {
1873                 .str = "a_unsupported_opcodes_received",
1874                 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1875         },
1876         {
1877                 .str = "a_pause_mac_ctrl_frames_received",
1878                 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1879         },
1880         {
1881                 .str = "a_pause_mac_ctrl_frames_xmitted",
1882                 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1883         },
1884 };
1885
1886 #define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
1887
1888 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_rfc_2863_stats[] = {
1889         {
1890                 .str = "if_in_discards",
1891                 .getter = mlxsw_reg_ppcnt_if_in_discards_get,
1892         },
1893         {
1894                 .str = "if_out_discards",
1895                 .getter = mlxsw_reg_ppcnt_if_out_discards_get,
1896         },
1897         {
1898                 .str = "if_out_errors",
1899                 .getter = mlxsw_reg_ppcnt_if_out_errors_get,
1900         },
1901 };
1902
1903 #define MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN \
1904         ARRAY_SIZE(mlxsw_sp_port_hw_rfc_2863_stats)
1905
1906 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_rfc_2819_stats[] = {
1907         {
1908                 .str = "ether_stats_undersize_pkts",
1909                 .getter = mlxsw_reg_ppcnt_ether_stats_undersize_pkts_get,
1910         },
1911         {
1912                 .str = "ether_stats_oversize_pkts",
1913                 .getter = mlxsw_reg_ppcnt_ether_stats_oversize_pkts_get,
1914         },
1915         {
1916                 .str = "ether_stats_fragments",
1917                 .getter = mlxsw_reg_ppcnt_ether_stats_fragments_get,
1918         },
1919         {
1920                 .str = "ether_pkts64octets",
1921                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts64octets_get,
1922         },
1923         {
1924                 .str = "ether_pkts65to127octets",
1925                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts65to127octets_get,
1926         },
1927         {
1928                 .str = "ether_pkts128to255octets",
1929                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts128to255octets_get,
1930         },
1931         {
1932                 .str = "ether_pkts256to511octets",
1933                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts256to511octets_get,
1934         },
1935         {
1936                 .str = "ether_pkts512to1023octets",
1937                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts512to1023octets_get,
1938         },
1939         {
1940                 .str = "ether_pkts1024to1518octets",
1941                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts1024to1518octets_get,
1942         },
1943         {
1944                 .str = "ether_pkts1519to2047octets",
1945                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts1519to2047octets_get,
1946         },
1947         {
1948                 .str = "ether_pkts2048to4095octets",
1949                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts2048to4095octets_get,
1950         },
1951         {
1952                 .str = "ether_pkts4096to8191octets",
1953                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts4096to8191octets_get,
1954         },
1955         {
1956                 .str = "ether_pkts8192to10239octets",
1957                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts8192to10239octets_get,
1958         },
1959 };
1960
1961 #define MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN \
1962         ARRAY_SIZE(mlxsw_sp_port_hw_rfc_2819_stats)
1963
1964 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_rfc_3635_stats[] = {
1965         {
1966                 .str = "dot3stats_fcs_errors",
1967                 .getter = mlxsw_reg_ppcnt_dot3stats_fcs_errors_get,
1968         },
1969         {
1970                 .str = "dot3stats_symbol_errors",
1971                 .getter = mlxsw_reg_ppcnt_dot3stats_symbol_errors_get,
1972         },
1973         {
1974                 .str = "dot3control_in_unknown_opcodes",
1975                 .getter = mlxsw_reg_ppcnt_dot3control_in_unknown_opcodes_get,
1976         },
1977         {
1978                 .str = "dot3in_pause_frames",
1979                 .getter = mlxsw_reg_ppcnt_dot3in_pause_frames_get,
1980         },
1981 };
1982
1983 #define MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN \
1984         ARRAY_SIZE(mlxsw_sp_port_hw_rfc_3635_stats)
1985
1986 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_discard_stats[] = {
1987         {
1988                 .str = "discard_ingress_general",
1989                 .getter = mlxsw_reg_ppcnt_ingress_general_get,
1990         },
1991         {
1992                 .str = "discard_ingress_policy_engine",
1993                 .getter = mlxsw_reg_ppcnt_ingress_policy_engine_get,
1994         },
1995         {
1996                 .str = "discard_ingress_vlan_membership",
1997                 .getter = mlxsw_reg_ppcnt_ingress_vlan_membership_get,
1998         },
1999         {
2000                 .str = "discard_ingress_tag_frame_type",
2001                 .getter = mlxsw_reg_ppcnt_ingress_tag_frame_type_get,
2002         },
2003         {
2004                 .str = "discard_egress_vlan_membership",
2005                 .getter = mlxsw_reg_ppcnt_egress_vlan_membership_get,
2006         },
2007         {
2008                 .str = "discard_loopback_filter",
2009                 .getter = mlxsw_reg_ppcnt_loopback_filter_get,
2010         },
2011         {
2012                 .str = "discard_egress_general",
2013                 .getter = mlxsw_reg_ppcnt_egress_general_get,
2014         },
2015         {
2016                 .str = "discard_egress_hoq",
2017                 .getter = mlxsw_reg_ppcnt_egress_hoq_get,
2018         },
2019         {
2020                 .str = "discard_egress_policy_engine",
2021                 .getter = mlxsw_reg_ppcnt_egress_policy_engine_get,
2022         },
2023         {
2024                 .str = "discard_ingress_tx_link_down",
2025                 .getter = mlxsw_reg_ppcnt_ingress_tx_link_down_get,
2026         },
2027         {
2028                 .str = "discard_egress_stp_filter",
2029                 .getter = mlxsw_reg_ppcnt_egress_stp_filter_get,
2030         },
2031         {
2032                 .str = "discard_egress_sll",
2033                 .getter = mlxsw_reg_ppcnt_egress_sll_get,
2034         },
2035 };
2036
2037 #define MLXSW_SP_PORT_HW_DISCARD_STATS_LEN \
2038         ARRAY_SIZE(mlxsw_sp_port_hw_discard_stats)
2039
2040 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
2041         {
2042                 .str = "rx_octets_prio",
2043                 .getter = mlxsw_reg_ppcnt_rx_octets_get,
2044         },
2045         {
2046                 .str = "rx_frames_prio",
2047                 .getter = mlxsw_reg_ppcnt_rx_frames_get,
2048         },
2049         {
2050                 .str = "tx_octets_prio",
2051                 .getter = mlxsw_reg_ppcnt_tx_octets_get,
2052         },
2053         {
2054                 .str = "tx_frames_prio",
2055                 .getter = mlxsw_reg_ppcnt_tx_frames_get,
2056         },
2057         {
2058                 .str = "rx_pause_prio",
2059                 .getter = mlxsw_reg_ppcnt_rx_pause_get,
2060         },
2061         {
2062                 .str = "rx_pause_duration_prio",
2063                 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
2064         },
2065         {
2066                 .str = "tx_pause_prio",
2067                 .getter = mlxsw_reg_ppcnt_tx_pause_get,
2068         },
2069         {
2070                 .str = "tx_pause_duration_prio",
2071                 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
2072         },
2073 };
2074
2075 #define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
2076
2077 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
2078         {
2079                 .str = "tc_transmit_queue_tc",
2080                 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
2081                 .cells_bytes = true,
2082         },
2083         {
2084                 .str = "tc_no_buffer_discard_uc_tc",
2085                 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
2086         },
2087 };
2088
2089 #define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
2090
2091 #define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
2092                                          MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN + \
2093                                          MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN + \
2094                                          MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN + \
2095                                          MLXSW_SP_PORT_HW_DISCARD_STATS_LEN + \
2096                                          (MLXSW_SP_PORT_HW_PRIO_STATS_LEN * \
2097                                           IEEE_8021QAZ_MAX_TCS) + \
2098                                          (MLXSW_SP_PORT_HW_TC_STATS_LEN * \
2099                                           TC_MAX_QUEUE))
2100
2101 static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
2102 {
2103         int i;
2104
2105         for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
2106                 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
2107                          mlxsw_sp_port_hw_prio_stats[i].str, prio);
2108                 *p += ETH_GSTRING_LEN;
2109         }
2110 }
2111
2112 static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
2113 {
2114         int i;
2115
2116         for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
2117                 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
2118                          mlxsw_sp_port_hw_tc_stats[i].str, tc);
2119                 *p += ETH_GSTRING_LEN;
2120         }
2121 }
2122
2123 static void mlxsw_sp_port_get_strings(struct net_device *dev,
2124                                       u32 stringset, u8 *data)
2125 {
2126         u8 *p = data;
2127         int i;
2128
2129         switch (stringset) {
2130         case ETH_SS_STATS:
2131                 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
2132                         memcpy(p, mlxsw_sp_port_hw_stats[i].str,
2133                                ETH_GSTRING_LEN);
2134                         p += ETH_GSTRING_LEN;
2135                 }
2136
2137                 for (i = 0; i < MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN; i++) {
2138                         memcpy(p, mlxsw_sp_port_hw_rfc_2863_stats[i].str,
2139                                ETH_GSTRING_LEN);
2140                         p += ETH_GSTRING_LEN;
2141                 }
2142
2143                 for (i = 0; i < MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN; i++) {
2144                         memcpy(p, mlxsw_sp_port_hw_rfc_2819_stats[i].str,
2145                                ETH_GSTRING_LEN);
2146                         p += ETH_GSTRING_LEN;
2147                 }
2148
2149                 for (i = 0; i < MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN; i++) {
2150                         memcpy(p, mlxsw_sp_port_hw_rfc_3635_stats[i].str,
2151                                ETH_GSTRING_LEN);
2152                         p += ETH_GSTRING_LEN;
2153                 }
2154
2155                 for (i = 0; i < MLXSW_SP_PORT_HW_DISCARD_STATS_LEN; i++) {
2156                         memcpy(p, mlxsw_sp_port_hw_discard_stats[i].str,
2157                                ETH_GSTRING_LEN);
2158                         p += ETH_GSTRING_LEN;
2159                 }
2160
2161                 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2162                         mlxsw_sp_port_get_prio_strings(&p, i);
2163
2164                 for (i = 0; i < TC_MAX_QUEUE; i++)
2165                         mlxsw_sp_port_get_tc_strings(&p, i);
2166
2167                 break;
2168         }
2169 }
2170
2171 static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
2172                                      enum ethtool_phys_id_state state)
2173 {
2174         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2175         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2176         char mlcr_pl[MLXSW_REG_MLCR_LEN];
2177         bool active;
2178
2179         switch (state) {
2180         case ETHTOOL_ID_ACTIVE:
2181                 active = true;
2182                 break;
2183         case ETHTOOL_ID_INACTIVE:
2184                 active = false;
2185                 break;
2186         default:
2187                 return -EOPNOTSUPP;
2188         }
2189
2190         mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
2191         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
2192 }
2193
2194 static int
2195 mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
2196                                int *p_len, enum mlxsw_reg_ppcnt_grp grp)
2197 {
2198         switch (grp) {
2199         case MLXSW_REG_PPCNT_IEEE_8023_CNT:
2200                 *p_hw_stats = mlxsw_sp_port_hw_stats;
2201                 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
2202                 break;
2203         case MLXSW_REG_PPCNT_RFC_2863_CNT:
2204                 *p_hw_stats = mlxsw_sp_port_hw_rfc_2863_stats;
2205                 *p_len = MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN;
2206                 break;
2207         case MLXSW_REG_PPCNT_RFC_2819_CNT:
2208                 *p_hw_stats = mlxsw_sp_port_hw_rfc_2819_stats;
2209                 *p_len = MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN;
2210                 break;
2211         case MLXSW_REG_PPCNT_RFC_3635_CNT:
2212                 *p_hw_stats = mlxsw_sp_port_hw_rfc_3635_stats;
2213                 *p_len = MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN;
2214                 break;
2215         case MLXSW_REG_PPCNT_DISCARD_CNT:
2216                 *p_hw_stats = mlxsw_sp_port_hw_discard_stats;
2217                 *p_len = MLXSW_SP_PORT_HW_DISCARD_STATS_LEN;
2218                 break;
2219         case MLXSW_REG_PPCNT_PRIO_CNT:
2220                 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
2221                 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2222                 break;
2223         case MLXSW_REG_PPCNT_TC_CNT:
2224                 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
2225                 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
2226                 break;
2227         default:
2228                 WARN_ON(1);
2229                 return -EOPNOTSUPP;
2230         }
2231         return 0;
2232 }
2233
2234 static void __mlxsw_sp_port_get_stats(struct net_device *dev,
2235                                       enum mlxsw_reg_ppcnt_grp grp, int prio,
2236                                       u64 *data, int data_index)
2237 {
2238         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2239         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2240         struct mlxsw_sp_port_hw_stats *hw_stats;
2241         char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
2242         int i, len;
2243         int err;
2244
2245         err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
2246         if (err)
2247                 return;
2248         mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
2249         for (i = 0; i < len; i++) {
2250                 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
2251                 if (!hw_stats[i].cells_bytes)
2252                         continue;
2253                 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
2254                                                             data[data_index + i]);
2255         }
2256 }
2257
2258 static void mlxsw_sp_port_get_stats(struct net_device *dev,
2259                                     struct ethtool_stats *stats, u64 *data)
2260 {
2261         int i, data_index = 0;
2262
2263         /* IEEE 802.3 Counters */
2264         __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
2265                                   data, data_index);
2266         data_index = MLXSW_SP_PORT_HW_STATS_LEN;
2267
2268         /* RFC 2863 Counters */
2269         __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_RFC_2863_CNT, 0,
2270                                   data, data_index);
2271         data_index += MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN;
2272
2273         /* RFC 2819 Counters */
2274         __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_RFC_2819_CNT, 0,
2275                                   data, data_index);
2276         data_index += MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN;
2277
2278         /* RFC 3635 Counters */
2279         __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_RFC_3635_CNT, 0,
2280                                   data, data_index);
2281         data_index += MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN;
2282
2283         /* Discard Counters */
2284         __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_DISCARD_CNT, 0,
2285                                   data, data_index);
2286         data_index += MLXSW_SP_PORT_HW_DISCARD_STATS_LEN;
2287
2288         /* Per-Priority Counters */
2289         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2290                 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
2291                                           data, data_index);
2292                 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2293         }
2294
2295         /* Per-TC Counters */
2296         for (i = 0; i < TC_MAX_QUEUE; i++) {
2297                 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
2298                                           data, data_index);
2299                 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
2300         }
2301 }
2302
2303 static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
2304 {
2305         switch (sset) {
2306         case ETH_SS_STATS:
2307                 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
2308         default:
2309                 return -EOPNOTSUPP;
2310         }
2311 }
2312
2313 struct mlxsw_sp_port_link_mode {
2314         enum ethtool_link_mode_bit_indices mask_ethtool;
2315         u32 mask;
2316         u32 speed;
2317 };
2318
2319 static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
2320         {
2321                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
2322                 .mask_ethtool   = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2323                 .speed          = SPEED_100,
2324         },
2325         {
2326                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
2327                                   MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
2328                 .mask_ethtool   = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2329                 .speed          = SPEED_1000,
2330         },
2331         {
2332                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
2333                 .mask_ethtool   = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2334                 .speed          = SPEED_10000,
2335         },
2336         {
2337                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
2338                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
2339                 .mask_ethtool   = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2340                 .speed          = SPEED_10000,
2341         },
2342         {
2343                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2344                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2345                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2346                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
2347                 .mask_ethtool   = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2348                 .speed          = SPEED_10000,
2349         },
2350         {
2351                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
2352                 .mask_ethtool   = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
2353                 .speed          = SPEED_20000,
2354         },
2355         {
2356                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
2357                 .mask_ethtool   = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2358                 .speed          = SPEED_40000,
2359         },
2360         {
2361                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
2362                 .mask_ethtool   = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2363                 .speed          = SPEED_40000,
2364         },
2365         {
2366                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
2367                 .mask_ethtool   = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2368                 .speed          = SPEED_40000,
2369         },
2370         {
2371                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
2372                 .mask_ethtool   = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2373                 .speed          = SPEED_40000,
2374         },
2375         {
2376                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
2377                 .mask_ethtool   = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2378                 .speed          = SPEED_25000,
2379         },
2380         {
2381                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
2382                 .mask_ethtool   = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2383                 .speed          = SPEED_25000,
2384         },
2385         {
2386                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2387                 .mask_ethtool   = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2388                 .speed          = SPEED_25000,
2389         },
2390         {
2391                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2392                 .mask_ethtool   = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2393                 .speed          = SPEED_25000,
2394         },
2395         {
2396                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
2397                 .mask_ethtool   = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2398                 .speed          = SPEED_50000,
2399         },
2400         {
2401                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
2402                 .mask_ethtool   = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2403                 .speed          = SPEED_50000,
2404         },
2405         {
2406                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
2407                 .mask_ethtool   = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2408                 .speed          = SPEED_50000,
2409         },
2410         {
2411                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2412                 .mask_ethtool   = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
2413                 .speed          = SPEED_56000,
2414         },
2415         {
2416                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2417                 .mask_ethtool   = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
2418                 .speed          = SPEED_56000,
2419         },
2420         {
2421                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2422                 .mask_ethtool   = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
2423                 .speed          = SPEED_56000,
2424         },
2425         {
2426                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2427                 .mask_ethtool   = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
2428                 .speed          = SPEED_56000,
2429         },
2430         {
2431                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
2432                 .mask_ethtool   = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2433                 .speed          = SPEED_100000,
2434         },
2435         {
2436                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
2437                 .mask_ethtool   = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2438                 .speed          = SPEED_100000,
2439         },
2440         {
2441                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
2442                 .mask_ethtool   = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2443                 .speed          = SPEED_100000,
2444         },
2445         {
2446                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
2447                 .mask_ethtool   = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2448                 .speed          = SPEED_100000,
2449         },
2450 };
2451
2452 #define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
2453
2454 static void
2455 mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
2456                                   struct ethtool_link_ksettings *cmd)
2457 {
2458         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2459                               MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2460                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2461                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2462                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2463                               MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2464                 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
2465
2466         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2467                               MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2468                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2469                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
2470                               MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
2471                 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
2472 }
2473
2474 static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
2475 {
2476         int i;
2477
2478         for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2479                 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
2480                         __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2481                                   mode);
2482         }
2483 }
2484
2485 static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
2486                                             struct ethtool_link_ksettings *cmd)
2487 {
2488         u32 speed = SPEED_UNKNOWN;
2489         u8 duplex = DUPLEX_UNKNOWN;
2490         int i;
2491
2492         if (!carrier_ok)
2493                 goto out;
2494
2495         for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2496                 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
2497                         speed = mlxsw_sp_port_link_mode[i].speed;
2498                         duplex = DUPLEX_FULL;
2499                         break;
2500                 }
2501         }
2502 out:
2503         cmd->base.speed = speed;
2504         cmd->base.duplex = duplex;
2505 }
2506
2507 static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
2508 {
2509         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2510                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2511                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2512                               MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2513                 return PORT_FIBRE;
2514
2515         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2516                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2517                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
2518                 return PORT_DA;
2519
2520         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2521                               MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2522                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2523                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
2524                 return PORT_NONE;
2525
2526         return PORT_OTHER;
2527 }
2528
2529 static u32
2530 mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
2531 {
2532         u32 ptys_proto = 0;
2533         int i;
2534
2535         for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2536                 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2537                              cmd->link_modes.advertising))
2538                         ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2539         }
2540         return ptys_proto;
2541 }
2542
2543 static u32 mlxsw_sp_to_ptys_speed(u32 speed)
2544 {
2545         u32 ptys_proto = 0;
2546         int i;
2547
2548         for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2549                 if (speed == mlxsw_sp_port_link_mode[i].speed)
2550                         ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2551         }
2552         return ptys_proto;
2553 }
2554
2555 static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
2556 {
2557         u32 ptys_proto = 0;
2558         int i;
2559
2560         for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2561                 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
2562                         ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2563         }
2564         return ptys_proto;
2565 }
2566
2567 static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
2568                                              struct ethtool_link_ksettings *cmd)
2569 {
2570         ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
2571         ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
2572         ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
2573
2574         mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
2575         mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
2576 }
2577
2578 static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
2579                                              struct ethtool_link_ksettings *cmd)
2580 {
2581         if (!autoneg)
2582                 return;
2583
2584         ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
2585         mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
2586 }
2587
2588 static void
2589 mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
2590                                     struct ethtool_link_ksettings *cmd)
2591 {
2592         if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
2593                 return;
2594
2595         ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
2596         mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
2597 }
2598
2599 static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
2600                                             struct ethtool_link_ksettings *cmd)
2601 {
2602         u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
2603         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2604         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2605         char ptys_pl[MLXSW_REG_PTYS_LEN];
2606         u8 autoneg_status;
2607         bool autoneg;
2608         int err;
2609
2610         autoneg = mlxsw_sp_port->link.autoneg;
2611         mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0, false);
2612         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2613         if (err)
2614                 return err;
2615         mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin,
2616                                   &eth_proto_oper);
2617
2618         mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
2619
2620         mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
2621
2622         eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
2623         autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
2624         mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
2625
2626         cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2627         cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
2628         mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
2629                                         cmd);
2630
2631         return 0;
2632 }
2633
2634 static int
2635 mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
2636                                  const struct ethtool_link_ksettings *cmd)
2637 {
2638         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2639         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2640         char ptys_pl[MLXSW_REG_PTYS_LEN];
2641         u32 eth_proto_cap, eth_proto_new;
2642         bool autoneg;
2643         int err;
2644
2645         mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0, false);
2646         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2647         if (err)
2648                 return err;
2649         mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
2650
2651         autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
2652         eth_proto_new = autoneg ?
2653                 mlxsw_sp_to_ptys_advert_link(cmd) :
2654                 mlxsw_sp_to_ptys_speed(cmd->base.speed);
2655
2656         eth_proto_new = eth_proto_new & eth_proto_cap;
2657         if (!eth_proto_new) {
2658                 netdev_err(dev, "No supported speed requested\n");
2659                 return -EINVAL;
2660         }
2661
2662         mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2663                                 eth_proto_new, autoneg);
2664         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2665         if (err)
2666                 return err;
2667
2668         if (!netif_running(dev))
2669                 return 0;
2670
2671         mlxsw_sp_port->link.autoneg = autoneg;
2672
2673         mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2674         mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
2675
2676         return 0;
2677 }
2678
2679 static int mlxsw_sp_flash_device(struct net_device *dev,
2680                                  struct ethtool_flash *flash)
2681 {
2682         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2683         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2684         const struct firmware *firmware;
2685         int err;
2686
2687         if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
2688                 return -EOPNOTSUPP;
2689
2690         dev_hold(dev);
2691         rtnl_unlock();
2692
2693         err = request_firmware_direct(&firmware, flash->data, &dev->dev);
2694         if (err)
2695                 goto out;
2696         err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
2697         release_firmware(firmware);
2698 out:
2699         rtnl_lock();
2700         dev_put(dev);
2701         return err;
2702 }
2703
2704 #define MLXSW_SP_I2C_ADDR_LOW 0x50
2705 #define MLXSW_SP_I2C_ADDR_HIGH 0x51
2706 #define MLXSW_SP_EEPROM_PAGE_LENGTH 256
2707
2708 static int mlxsw_sp_query_module_eeprom(struct mlxsw_sp_port *mlxsw_sp_port,
2709                                         u16 offset, u16 size, void *data,
2710                                         unsigned int *p_read_size)
2711 {
2712         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2713         char eeprom_tmp[MLXSW_SP_REG_MCIA_EEPROM_SIZE];
2714         char mcia_pl[MLXSW_REG_MCIA_LEN];
2715         u16 i2c_addr;
2716         int status;
2717         int err;
2718
2719         size = min_t(u16, size, MLXSW_SP_REG_MCIA_EEPROM_SIZE);
2720
2721         if (offset < MLXSW_SP_EEPROM_PAGE_LENGTH &&
2722             offset + size > MLXSW_SP_EEPROM_PAGE_LENGTH)
2723                 /* Cross pages read, read until offset 256 in low page */
2724                 size = MLXSW_SP_EEPROM_PAGE_LENGTH - offset;
2725
2726         i2c_addr = MLXSW_SP_I2C_ADDR_LOW;
2727         if (offset >= MLXSW_SP_EEPROM_PAGE_LENGTH) {
2728                 i2c_addr = MLXSW_SP_I2C_ADDR_HIGH;
2729                 offset -= MLXSW_SP_EEPROM_PAGE_LENGTH;
2730         }
2731
2732         mlxsw_reg_mcia_pack(mcia_pl, mlxsw_sp_port->mapping.module,
2733                             0, 0, offset, size, i2c_addr);
2734
2735         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcia), mcia_pl);
2736         if (err)
2737                 return err;
2738
2739         status = mlxsw_reg_mcia_status_get(mcia_pl);
2740         if (status)
2741                 return -EIO;
2742
2743         mlxsw_reg_mcia_eeprom_memcpy_from(mcia_pl, eeprom_tmp);
2744         memcpy(data, eeprom_tmp, size);
2745         *p_read_size = size;
2746
2747         return 0;
2748 }
2749
2750 enum mlxsw_sp_eeprom_module_info_rev_id {
2751         MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_UNSPC      = 0x00,
2752         MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8436       = 0x01,
2753         MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636       = 0x03,
2754 };
2755
2756 enum mlxsw_sp_eeprom_module_info_id {
2757         MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP              = 0x03,
2758         MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP             = 0x0C,
2759         MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS        = 0x0D,
2760         MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28           = 0x11,
2761 };
2762
2763 enum mlxsw_sp_eeprom_module_info {
2764         MLXSW_SP_EEPROM_MODULE_INFO_ID,
2765         MLXSW_SP_EEPROM_MODULE_INFO_REV_ID,
2766         MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2767 };
2768
2769 static int mlxsw_sp_get_module_info(struct net_device *netdev,
2770                                     struct ethtool_modinfo *modinfo)
2771 {
2772         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2773         u8 module_info[MLXSW_SP_EEPROM_MODULE_INFO_SIZE];
2774         u8 module_rev_id, module_id;
2775         unsigned int read_size;
2776         int err;
2777
2778         err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, 0,
2779                                            MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2780                                            module_info, &read_size);
2781         if (err)
2782                 return err;
2783
2784         if (read_size < MLXSW_SP_EEPROM_MODULE_INFO_SIZE)
2785                 return -EIO;
2786
2787         module_rev_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_REV_ID];
2788         module_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_ID];
2789
2790         switch (module_id) {
2791         case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP:
2792                 modinfo->type       = ETH_MODULE_SFF_8436;
2793                 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2794                 break;
2795         case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS:
2796         case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28:
2797                 if (module_id  == MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 ||
2798                     module_rev_id >= MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636) {
2799                         modinfo->type       = ETH_MODULE_SFF_8636;
2800                         modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
2801                 } else {
2802                         modinfo->type       = ETH_MODULE_SFF_8436;
2803                         modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2804                 }
2805                 break;
2806         case MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP:
2807                 modinfo->type       = ETH_MODULE_SFF_8472;
2808                 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2809                 break;
2810         default:
2811                 return -EINVAL;
2812         }
2813
2814         return 0;
2815 }
2816
2817 static int mlxsw_sp_get_module_eeprom(struct net_device *netdev,
2818                                       struct ethtool_eeprom *ee,
2819                                       u8 *data)
2820 {
2821         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2822         int offset = ee->offset;
2823         unsigned int read_size;
2824         int i = 0;
2825         int err;
2826
2827         if (!ee->len)
2828                 return -EINVAL;
2829
2830         memset(data, 0, ee->len);
2831
2832         while (i < ee->len) {
2833                 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, offset,
2834                                                    ee->len - i, data + i,
2835                                                    &read_size);
2836                 if (err) {
2837                         netdev_err(mlxsw_sp_port->dev, "Eeprom query failed\n");
2838                         return err;
2839                 }
2840
2841                 i += read_size;
2842                 offset += read_size;
2843         }
2844
2845         return 0;
2846 }
2847
2848 static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
2849         .get_drvinfo            = mlxsw_sp_port_get_drvinfo,
2850         .get_link               = ethtool_op_get_link,
2851         .get_pauseparam         = mlxsw_sp_port_get_pauseparam,
2852         .set_pauseparam         = mlxsw_sp_port_set_pauseparam,
2853         .get_strings            = mlxsw_sp_port_get_strings,
2854         .set_phys_id            = mlxsw_sp_port_set_phys_id,
2855         .get_ethtool_stats      = mlxsw_sp_port_get_stats,
2856         .get_sset_count         = mlxsw_sp_port_get_sset_count,
2857         .get_link_ksettings     = mlxsw_sp_port_get_link_ksettings,
2858         .set_link_ksettings     = mlxsw_sp_port_set_link_ksettings,
2859         .flash_device           = mlxsw_sp_flash_device,
2860         .get_module_info        = mlxsw_sp_get_module_info,
2861         .get_module_eeprom      = mlxsw_sp_get_module_eeprom,
2862 };
2863
2864 static int
2865 mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
2866 {
2867         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2868         u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
2869         char ptys_pl[MLXSW_REG_PTYS_LEN];
2870         u32 eth_proto_admin;
2871
2872         eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
2873         mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2874                                 eth_proto_admin, mlxsw_sp_port->link.autoneg);
2875         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2876 }
2877
2878 int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
2879                           enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
2880                           bool dwrr, u8 dwrr_weight)
2881 {
2882         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2883         char qeec_pl[MLXSW_REG_QEEC_LEN];
2884
2885         mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2886                             next_index);
2887         mlxsw_reg_qeec_de_set(qeec_pl, true);
2888         mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
2889         mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
2890         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2891 }
2892
2893 int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
2894                                   enum mlxsw_reg_qeec_hr hr, u8 index,
2895                                   u8 next_index, u32 maxrate)
2896 {
2897         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2898         char qeec_pl[MLXSW_REG_QEEC_LEN];
2899
2900         mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2901                             next_index);
2902         mlxsw_reg_qeec_mase_set(qeec_pl, true);
2903         mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
2904         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2905 }
2906
2907 static int mlxsw_sp_port_min_bw_set(struct mlxsw_sp_port *mlxsw_sp_port,
2908                                     enum mlxsw_reg_qeec_hr hr, u8 index,
2909                                     u8 next_index, u32 minrate)
2910 {
2911         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2912         char qeec_pl[MLXSW_REG_QEEC_LEN];
2913
2914         mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2915                             next_index);
2916         mlxsw_reg_qeec_mise_set(qeec_pl, true);
2917         mlxsw_reg_qeec_min_shaper_rate_set(qeec_pl, minrate);
2918
2919         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2920 }
2921
2922 int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
2923                               u8 switch_prio, u8 tclass)
2924 {
2925         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2926         char qtct_pl[MLXSW_REG_QTCT_LEN];
2927
2928         mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
2929                             tclass);
2930         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
2931 }
2932
2933 static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
2934 {
2935         int err, i;
2936
2937         /* Setup the elements hierarcy, so that each TC is linked to
2938          * one subgroup, which are all member in the same group.
2939          */
2940         err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2941                                     MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
2942                                     0);
2943         if (err)
2944                 return err;
2945         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2946                 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2947                                             MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
2948                                             0, false, 0);
2949                 if (err)
2950                         return err;
2951         }
2952         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2953                 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2954                                             MLXSW_REG_QEEC_HIERARCY_TC, i, i,
2955                                             false, 0);
2956                 if (err)
2957                         return err;
2958
2959                 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2960                                             MLXSW_REG_QEEC_HIERARCY_TC,
2961                                             i + 8, i,
2962                                             false, 0);
2963                 if (err)
2964                         return err;
2965         }
2966
2967         /* Make sure the max shaper is disabled in all hierarchies that
2968          * support it.
2969          */
2970         err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2971                                             MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
2972                                             MLXSW_REG_QEEC_MAS_DIS);
2973         if (err)
2974                 return err;
2975         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2976                 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2977                                                     MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
2978                                                     i, 0,
2979                                                     MLXSW_REG_QEEC_MAS_DIS);
2980                 if (err)
2981                         return err;
2982         }
2983         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2984                 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2985                                                     MLXSW_REG_QEEC_HIERARCY_TC,
2986                                                     i, i,
2987                                                     MLXSW_REG_QEEC_MAS_DIS);
2988                 if (err)
2989                         return err;
2990
2991                 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2992                                                     MLXSW_REG_QEEC_HIERARCY_TC,
2993                                                     i + 8, i,
2994                                                     MLXSW_REG_QEEC_MAS_DIS);
2995                 if (err)
2996                         return err;
2997         }
2998
2999         /* Configure the min shaper for multicast TCs. */
3000         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3001                 err = mlxsw_sp_port_min_bw_set(mlxsw_sp_port,
3002                                                MLXSW_REG_QEEC_HIERARCY_TC,
3003                                                i + 8, i,
3004                                                MLXSW_REG_QEEC_MIS_MIN);
3005                 if (err)
3006                         return err;
3007         }
3008
3009         /* Map all priorities to traffic class 0. */
3010         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3011                 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
3012                 if (err)
3013                         return err;
3014         }
3015
3016         return 0;
3017 }
3018
3019 static int mlxsw_sp_port_tc_mc_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
3020                                         bool enable)
3021 {
3022         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3023         char qtctm_pl[MLXSW_REG_QTCTM_LEN];
3024
3025         mlxsw_reg_qtctm_pack(qtctm_pl, mlxsw_sp_port->local_port, enable);
3026         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtctm), qtctm_pl);
3027 }
3028
3029 static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
3030                                 bool split, u8 module, u8 width, u8 lane)
3031 {
3032         struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
3033         struct mlxsw_sp_port *mlxsw_sp_port;
3034         struct net_device *dev;
3035         int err;
3036
3037         err = mlxsw_core_port_init(mlxsw_sp->core, local_port);
3038         if (err) {
3039                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
3040                         local_port);
3041                 return err;
3042         }
3043
3044         dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
3045         if (!dev) {
3046                 err = -ENOMEM;
3047                 goto err_alloc_etherdev;
3048         }
3049         SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
3050         mlxsw_sp_port = netdev_priv(dev);
3051         mlxsw_sp_port->dev = dev;
3052         mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
3053         mlxsw_sp_port->local_port = local_port;
3054         mlxsw_sp_port->pvid = MLXSW_SP_DEFAULT_VID;
3055         mlxsw_sp_port->split = split;
3056         mlxsw_sp_port->mapping.module = module;
3057         mlxsw_sp_port->mapping.width = width;
3058         mlxsw_sp_port->mapping.lane = lane;
3059         mlxsw_sp_port->link.autoneg = 1;
3060         INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
3061         INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
3062
3063         mlxsw_sp_port->pcpu_stats =
3064                 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
3065         if (!mlxsw_sp_port->pcpu_stats) {
3066                 err = -ENOMEM;
3067                 goto err_alloc_stats;
3068         }
3069
3070         mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
3071                                         GFP_KERNEL);
3072         if (!mlxsw_sp_port->sample) {
3073                 err = -ENOMEM;
3074                 goto err_alloc_sample;
3075         }
3076
3077         INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw,
3078                           &update_stats_cache);
3079
3080         dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
3081         dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
3082
3083         err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane);
3084         if (err) {
3085                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
3086                         mlxsw_sp_port->local_port);
3087                 goto err_port_module_map;
3088         }
3089
3090         err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
3091         if (err) {
3092                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
3093                         mlxsw_sp_port->local_port);
3094                 goto err_port_swid_set;
3095         }
3096
3097         err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
3098         if (err) {
3099                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
3100                         mlxsw_sp_port->local_port);
3101                 goto err_dev_addr_init;
3102         }
3103
3104         netif_carrier_off(dev);
3105
3106         dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
3107                          NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
3108         dev->hw_features |= NETIF_F_HW_TC;
3109
3110         dev->min_mtu = 0;
3111         dev->max_mtu = ETH_MAX_MTU;
3112
3113         /* Each packet needs to have a Tx header (metadata) on top all other
3114          * headers.
3115          */
3116         dev->needed_headroom = MLXSW_TXHDR_LEN;
3117
3118         err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
3119         if (err) {
3120                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
3121                         mlxsw_sp_port->local_port);
3122                 goto err_port_system_port_mapping_set;
3123         }
3124
3125         err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
3126         if (err) {
3127                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
3128                         mlxsw_sp_port->local_port);
3129                 goto err_port_speed_by_width_set;
3130         }
3131
3132         err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
3133         if (err) {
3134                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
3135                         mlxsw_sp_port->local_port);
3136                 goto err_port_mtu_set;
3137         }
3138
3139         err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
3140         if (err)
3141                 goto err_port_admin_status_set;
3142
3143         err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
3144         if (err) {
3145                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
3146                         mlxsw_sp_port->local_port);
3147                 goto err_port_buffers_init;
3148         }
3149
3150         err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
3151         if (err) {
3152                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
3153                         mlxsw_sp_port->local_port);
3154                 goto err_port_ets_init;
3155         }
3156
3157         err = mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, true);
3158         if (err) {
3159                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC MC mode\n",
3160                         mlxsw_sp_port->local_port);
3161                 goto err_port_tc_mc_mode;
3162         }
3163
3164         /* ETS and buffers must be initialized before DCB. */
3165         err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
3166         if (err) {
3167                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
3168                         mlxsw_sp_port->local_port);
3169                 goto err_port_dcb_init;
3170         }
3171
3172         err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
3173         if (err) {
3174                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
3175                         mlxsw_sp_port->local_port);
3176                 goto err_port_fids_init;
3177         }
3178
3179         err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port);
3180         if (err) {
3181                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n",
3182                         mlxsw_sp_port->local_port);
3183                 goto err_port_qdiscs_init;
3184         }
3185
3186         err = mlxsw_sp_port_nve_init(mlxsw_sp_port);
3187         if (err) {
3188                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize NVE\n",
3189                         mlxsw_sp_port->local_port);
3190                 goto err_port_nve_init;
3191         }
3192
3193         err = mlxsw_sp_port_pvid_set(mlxsw_sp_port, MLXSW_SP_DEFAULT_VID);
3194         if (err) {
3195                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set PVID\n",
3196                         mlxsw_sp_port->local_port);
3197                 goto err_port_pvid_set;
3198         }
3199
3200         mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_create(mlxsw_sp_port,
3201                                                        MLXSW_SP_DEFAULT_VID);
3202         if (IS_ERR(mlxsw_sp_port_vlan)) {
3203                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
3204                         mlxsw_sp_port->local_port);
3205                 err = PTR_ERR(mlxsw_sp_port_vlan);
3206                 goto err_port_vlan_create;
3207         }
3208         mlxsw_sp_port->default_vlan = mlxsw_sp_port_vlan;
3209
3210         mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
3211         mlxsw_sp->ports[local_port] = mlxsw_sp_port;
3212         err = register_netdev(dev);
3213         if (err) {
3214                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
3215                         mlxsw_sp_port->local_port);
3216                 goto err_register_netdev;
3217         }
3218
3219         mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
3220                                 mlxsw_sp_port, dev, module + 1,
3221                                 mlxsw_sp_port->split, lane / width);
3222         mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0);
3223         return 0;
3224
3225 err_register_netdev:
3226         mlxsw_sp->ports[local_port] = NULL;
3227         mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
3228         mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
3229 err_port_vlan_create:
3230 err_port_pvid_set:
3231         mlxsw_sp_port_nve_fini(mlxsw_sp_port);
3232 err_port_nve_init:
3233         mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
3234 err_port_qdiscs_init:
3235         mlxsw_sp_port_fids_fini(mlxsw_sp_port);
3236 err_port_fids_init:
3237         mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
3238 err_port_dcb_init:
3239         mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false);
3240 err_port_tc_mc_mode:
3241 err_port_ets_init:
3242 err_port_buffers_init:
3243 err_port_admin_status_set:
3244 err_port_mtu_set:
3245 err_port_speed_by_width_set:
3246 err_port_system_port_mapping_set:
3247 err_dev_addr_init:
3248         mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
3249 err_port_swid_set:
3250         mlxsw_sp_port_module_unmap(mlxsw_sp_port);
3251 err_port_module_map:
3252         kfree(mlxsw_sp_port->sample);
3253 err_alloc_sample:
3254         free_percpu(mlxsw_sp_port->pcpu_stats);
3255 err_alloc_stats:
3256         free_netdev(dev);
3257 err_alloc_etherdev:
3258         mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3259         return err;
3260 }
3261
3262 static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
3263 {
3264         struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3265
3266         cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw);
3267         mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
3268         unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
3269         mlxsw_sp->ports[local_port] = NULL;
3270         mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
3271         mlxsw_sp_port_vlan_flush(mlxsw_sp_port, true);
3272         mlxsw_sp_port_nve_fini(mlxsw_sp_port);
3273         mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
3274         mlxsw_sp_port_fids_fini(mlxsw_sp_port);
3275         mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
3276         mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false);
3277         mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
3278         mlxsw_sp_port_module_unmap(mlxsw_sp_port);
3279         kfree(mlxsw_sp_port->sample);
3280         free_percpu(mlxsw_sp_port->pcpu_stats);
3281         WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
3282         free_netdev(mlxsw_sp_port->dev);
3283         mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3284 }
3285
3286 static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
3287 {
3288         return mlxsw_sp->ports[local_port] != NULL;
3289 }
3290
3291 static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
3292 {
3293         int i;
3294
3295         for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
3296                 if (mlxsw_sp_port_created(mlxsw_sp, i))
3297                         mlxsw_sp_port_remove(mlxsw_sp, i);
3298         kfree(mlxsw_sp->port_to_module);
3299         kfree(mlxsw_sp->ports);
3300 }
3301
3302 static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
3303 {
3304         unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
3305         u8 module, width, lane;
3306         size_t alloc_size;
3307         int i;
3308         int err;
3309
3310         alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
3311         mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
3312         if (!mlxsw_sp->ports)
3313                 return -ENOMEM;
3314
3315         mlxsw_sp->port_to_module = kmalloc_array(max_ports, sizeof(int),
3316                                                  GFP_KERNEL);
3317         if (!mlxsw_sp->port_to_module) {
3318                 err = -ENOMEM;
3319                 goto err_port_to_module_alloc;
3320         }
3321
3322         for (i = 1; i < max_ports; i++) {
3323                 /* Mark as invalid */
3324                 mlxsw_sp->port_to_module[i] = -1;
3325
3326                 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
3327                                                     &width, &lane);
3328                 if (err)
3329                         goto err_port_module_info_get;
3330                 if (!width)
3331                         continue;
3332                 mlxsw_sp->port_to_module[i] = module;
3333                 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
3334                                            module, width, lane);
3335                 if (err)
3336                         goto err_port_create;
3337         }
3338         return 0;
3339
3340 err_port_create:
3341 err_port_module_info_get:
3342         for (i--; i >= 1; i--)
3343                 if (mlxsw_sp_port_created(mlxsw_sp, i))
3344                         mlxsw_sp_port_remove(mlxsw_sp, i);
3345         kfree(mlxsw_sp->port_to_module);
3346 err_port_to_module_alloc:
3347         kfree(mlxsw_sp->ports);
3348         return err;
3349 }
3350
3351 static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
3352 {
3353         u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
3354
3355         return local_port - offset;
3356 }
3357
3358 static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
3359                                       u8 module, unsigned int count)
3360 {
3361         u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
3362         int err, i;
3363
3364         for (i = 0; i < count; i++) {
3365                 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
3366                                            module, width, i * width);
3367                 if (err)
3368                         goto err_port_create;
3369         }
3370
3371         return 0;
3372
3373 err_port_create:
3374         for (i--; i >= 0; i--)
3375                 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3376                         mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
3377         return err;
3378 }
3379
3380 static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
3381                                          u8 base_port, unsigned int count)
3382 {
3383         u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
3384         int i;
3385
3386         /* Split by four means we need to re-create two ports, otherwise
3387          * only one.
3388          */
3389         count = count / 2;
3390
3391         for (i = 0; i < count; i++) {
3392                 local_port = base_port + i * 2;
3393                 if (mlxsw_sp->port_to_module[local_port] < 0)
3394                         continue;
3395                 module = mlxsw_sp->port_to_module[local_port];
3396
3397                 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
3398                                      width, 0);
3399         }
3400 }
3401
3402 static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
3403                                unsigned int count,
3404                                struct netlink_ext_ack *extack)
3405 {
3406         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3407         struct mlxsw_sp_port *mlxsw_sp_port;
3408         u8 module, cur_width, base_port;
3409         int i;
3410         int err;
3411
3412         mlxsw_sp_port = mlxsw_sp->ports[local_port];
3413         if (!mlxsw_sp_port) {
3414                 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3415                         local_port);
3416                 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
3417                 return -EINVAL;
3418         }
3419
3420         module = mlxsw_sp_port->mapping.module;
3421         cur_width = mlxsw_sp_port->mapping.width;
3422
3423         if (count != 2 && count != 4) {
3424                 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
3425                 NL_SET_ERR_MSG_MOD(extack, "Port can only be split into 2 or 4 ports");
3426                 return -EINVAL;
3427         }
3428
3429         if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
3430                 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
3431                 NL_SET_ERR_MSG_MOD(extack, "Port cannot be split further");
3432                 return -EINVAL;
3433         }
3434
3435         /* Make sure we have enough slave (even) ports for the split. */
3436         if (count == 2) {
3437                 base_port = local_port;
3438                 if (mlxsw_sp->ports[base_port + 1]) {
3439                         netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3440                         NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration");
3441                         return -EINVAL;
3442                 }
3443         } else {
3444                 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3445                 if (mlxsw_sp->ports[base_port + 1] ||
3446                     mlxsw_sp->ports[base_port + 3]) {
3447                         netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3448                         NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration");
3449                         return -EINVAL;
3450                 }
3451         }
3452
3453         for (i = 0; i < count; i++)
3454                 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3455                         mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
3456
3457         err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
3458         if (err) {
3459                 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
3460                 goto err_port_split_create;
3461         }
3462
3463         return 0;
3464
3465 err_port_split_create:
3466         mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
3467         return err;
3468 }
3469
3470 static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port,
3471                                  struct netlink_ext_ack *extack)
3472 {
3473         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3474         struct mlxsw_sp_port *mlxsw_sp_port;
3475         u8 cur_width, base_port;
3476         unsigned int count;
3477         int i;
3478
3479         mlxsw_sp_port = mlxsw_sp->ports[local_port];
3480         if (!mlxsw_sp_port) {
3481                 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3482                         local_port);
3483                 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
3484                 return -EINVAL;
3485         }
3486
3487         if (!mlxsw_sp_port->split) {
3488                 netdev_err(mlxsw_sp_port->dev, "Port was not split\n");
3489                 NL_SET_ERR_MSG_MOD(extack, "Port was not split");
3490                 return -EINVAL;
3491         }
3492
3493         cur_width = mlxsw_sp_port->mapping.width;
3494         count = cur_width == 1 ? 4 : 2;
3495
3496         base_port = mlxsw_sp_cluster_base_port_get(local_port);
3497
3498         /* Determine which ports to remove. */
3499         if (count == 2 && local_port >= base_port + 2)
3500                 base_port = base_port + 2;
3501
3502         for (i = 0; i < count; i++)
3503                 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3504                         mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
3505
3506         mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
3507
3508         return 0;
3509 }
3510
3511 static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
3512                                      char *pude_pl, void *priv)
3513 {
3514         struct mlxsw_sp *mlxsw_sp = priv;
3515         struct mlxsw_sp_port *mlxsw_sp_port;
3516         enum mlxsw_reg_pude_oper_status status;
3517         u8 local_port;
3518
3519         local_port = mlxsw_reg_pude_local_port_get(pude_pl);
3520         mlxsw_sp_port = mlxsw_sp->ports[local_port];
3521         if (!mlxsw_sp_port)
3522                 return;
3523
3524         status = mlxsw_reg_pude_oper_status_get(pude_pl);
3525         if (status == MLXSW_PORT_OPER_STATUS_UP) {
3526                 netdev_info(mlxsw_sp_port->dev, "link up\n");
3527                 netif_carrier_on(mlxsw_sp_port->dev);
3528         } else {
3529                 netdev_info(mlxsw_sp_port->dev, "link down\n");
3530                 netif_carrier_off(mlxsw_sp_port->dev);
3531         }
3532 }
3533
3534 static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
3535                                               u8 local_port, void *priv)
3536 {
3537         struct mlxsw_sp *mlxsw_sp = priv;
3538         struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3539         struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
3540
3541         if (unlikely(!mlxsw_sp_port)) {
3542                 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
3543                                      local_port);
3544                 return;
3545         }
3546
3547         skb->dev = mlxsw_sp_port->dev;
3548
3549         pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
3550         u64_stats_update_begin(&pcpu_stats->syncp);
3551         pcpu_stats->rx_packets++;
3552         pcpu_stats->rx_bytes += skb->len;
3553         u64_stats_update_end(&pcpu_stats->syncp);
3554
3555         skb->protocol = eth_type_trans(skb, skb->dev);
3556         netif_receive_skb(skb);
3557 }
3558
3559 static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
3560                                            void *priv)
3561 {
3562         skb->offload_fwd_mark = 1;
3563         return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
3564 }
3565
3566 static void mlxsw_sp_rx_listener_l3_mark_func(struct sk_buff *skb,
3567                                               u8 local_port, void *priv)
3568 {
3569         skb->offload_l3_fwd_mark = 1;
3570         skb->offload_fwd_mark = 1;
3571         return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
3572 }
3573
3574 static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
3575                                              void *priv)
3576 {
3577         struct mlxsw_sp *mlxsw_sp = priv;
3578         struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3579         struct psample_group *psample_group;
3580         u32 size;
3581
3582         if (unlikely(!mlxsw_sp_port)) {
3583                 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
3584                                      local_port);
3585                 goto out;
3586         }
3587         if (unlikely(!mlxsw_sp_port->sample)) {
3588                 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
3589                                      local_port);
3590                 goto out;
3591         }
3592
3593         size = mlxsw_sp_port->sample->truncate ?
3594                   mlxsw_sp_port->sample->trunc_size : skb->len;
3595
3596         rcu_read_lock();
3597         psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
3598         if (!psample_group)
3599                 goto out_unlock;
3600         psample_sample_packet(psample_group, skb, size,
3601                               mlxsw_sp_port->dev->ifindex, 0,
3602                               mlxsw_sp_port->sample->rate);
3603 out_unlock:
3604         rcu_read_unlock();
3605 out:
3606         consume_skb(skb);
3607 }
3608
3609 #define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl)  \
3610         MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
3611                   _is_ctrl, SP_##_trap_group, DISCARD)
3612
3613 #define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl)     \
3614         MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action,    \
3615                 _is_ctrl, SP_##_trap_group, DISCARD)
3616
3617 #define MLXSW_SP_RXL_L3_MARK(_trap_id, _action, _trap_group, _is_ctrl)  \
3618         MLXSW_RXL(mlxsw_sp_rx_listener_l3_mark_func, _trap_id, _action, \
3619                 _is_ctrl, SP_##_trap_group, DISCARD)
3620
3621 #define MLXSW_SP_EVENTL(_func, _trap_id)                \
3622         MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
3623
3624 static const struct mlxsw_listener mlxsw_sp_listener[] = {
3625         /* Events */
3626         MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
3627         /* L2 traps */
3628         MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
3629         MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
3630         MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true),
3631         MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
3632         MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
3633         MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
3634         MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
3635         MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
3636         MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
3637         MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
3638         MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
3639         MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),
3640         MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU, IPV6_MLD,
3641                           false),
3642         MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3643                              false),
3644         MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_DONE, TRAP_TO_CPU, IPV6_MLD,
3645                              false),
3646         MLXSW_SP_RXL_NO_MARK(IPV6_MLDV2_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3647                              false),
3648         /* L3 traps */
3649         MLXSW_SP_RXL_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3650         MLXSW_SP_RXL_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3651         MLXSW_SP_RXL_L3_MARK(LBERROR, MIRROR_TO_CPU, LBERROR, false),
3652         MLXSW_SP_RXL_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
3653         MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP,
3654                           false),
3655         MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, false),
3656         MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false),
3657         MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, ROUTER_EXP, false),
3658         MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, ROUTER_EXP,
3659                           false),
3660         MLXSW_SP_RXL_MARK(IPV4_OSPF, TRAP_TO_CPU, OSPF, false),
3661         MLXSW_SP_RXL_MARK(IPV6_OSPF, TRAP_TO_CPU, OSPF, false),
3662         MLXSW_SP_RXL_MARK(IPV6_DHCP, TRAP_TO_CPU, DHCP, false),
3663         MLXSW_SP_RXL_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
3664         MLXSW_SP_RXL_MARK(IPV4_BGP, TRAP_TO_CPU, BGP, false),
3665         MLXSW_SP_RXL_MARK(IPV6_BGP, TRAP_TO_CPU, BGP, false),
3666         MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3667                           false),
3668         MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3669                           false),
3670         MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3671                           false),
3672         MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3673                           false),
3674         MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6_ND, false),
3675         MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP,
3676                           false),
3677         MLXSW_SP_RXL_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, HOST_MISS, false),
3678         MLXSW_SP_RXL_MARK(HOST_MISS_IPV6, TRAP_TO_CPU, HOST_MISS, false),
3679         MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, ROUTER_EXP, false),
3680         MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, ROUTER_EXP, false),
3681         MLXSW_SP_RXL_MARK(IPIP_DECAP_ERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3682         MLXSW_SP_RXL_MARK(DECAP_ECN0, TRAP_TO_CPU, ROUTER_EXP, false),
3683         MLXSW_SP_RXL_MARK(IPV4_VRRP, TRAP_TO_CPU, ROUTER_EXP, false),
3684         MLXSW_SP_RXL_MARK(IPV6_VRRP, TRAP_TO_CPU, ROUTER_EXP, false),
3685         /* PKT Sample trap */
3686         MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
3687                   false, SP_IP2ME, DISCARD),
3688         /* ACL trap */
3689         MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false),
3690         /* Multicast Router Traps */
3691         MLXSW_SP_RXL_MARK(IPV4_PIM, TRAP_TO_CPU, PIM, false),
3692         MLXSW_SP_RXL_MARK(IPV6_PIM, TRAP_TO_CPU, PIM, false),
3693         MLXSW_SP_RXL_MARK(RPF, TRAP_TO_CPU, RPF, false),
3694         MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false),
3695         MLXSW_SP_RXL_L3_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false),
3696         /* NVE traps */
3697         MLXSW_SP_RXL_MARK(NVE_ENCAP_ARP, TRAP_TO_CPU, ARP, false),
3698         MLXSW_SP_RXL_NO_MARK(NVE_DECAP_ARP, TRAP_TO_CPU, ARP, false),
3699 };
3700
3701 static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
3702 {
3703         char qpcr_pl[MLXSW_REG_QPCR_LEN];
3704         enum mlxsw_reg_qpcr_ir_units ir_units;
3705         int max_cpu_policers;
3706         bool is_bytes;
3707         u8 burst_size;
3708         u32 rate;
3709         int i, err;
3710
3711         if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
3712                 return -EIO;
3713
3714         max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
3715
3716         ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
3717         for (i = 0; i < max_cpu_policers; i++) {
3718                 is_bytes = false;
3719                 switch (i) {
3720                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3721                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3722                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3723                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
3724                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
3725                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
3726                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR:
3727                         rate = 128;
3728                         burst_size = 7;
3729                         break;
3730                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3731                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
3732                         rate = 16 * 1024;
3733                         burst_size = 10;
3734                         break;
3735                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
3736                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3737                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3738                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
3739                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3740                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
3741                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
3742                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
3743                         rate = 1024;
3744                         burst_size = 7;
3745                         break;
3746                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3747                         rate = 4 * 1024;
3748                         burst_size = 4;
3749                         break;
3750                 default:
3751                         continue;
3752                 }
3753
3754                 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
3755                                     burst_size);
3756                 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
3757                 if (err)
3758                         return err;
3759         }
3760
3761         return 0;
3762 }
3763
3764 static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
3765 {
3766         char htgt_pl[MLXSW_REG_HTGT_LEN];
3767         enum mlxsw_reg_htgt_trap_group i;
3768         int max_cpu_policers;
3769         int max_trap_groups;
3770         u8 priority, tc;
3771         u16 policer_id;
3772         int err;
3773
3774         if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
3775                 return -EIO;
3776
3777         max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
3778         max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
3779
3780         for (i = 0; i < max_trap_groups; i++) {
3781                 policer_id = i;
3782                 switch (i) {
3783                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3784                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3785                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3786                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
3787                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
3788                         priority = 5;
3789                         tc = 5;
3790                         break;
3791                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
3792                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3793                         priority = 4;
3794                         tc = 4;
3795                         break;
3796                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3797                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3798                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
3799                         priority = 3;
3800                         tc = 3;
3801                         break;
3802                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3803                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
3804                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
3805                         priority = 2;
3806                         tc = 2;
3807                         break;
3808                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
3809                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3810                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
3811                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
3812                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR:
3813                         priority = 1;
3814                         tc = 1;
3815                         break;
3816                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
3817                         priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
3818                         tc = MLXSW_REG_HTGT_DEFAULT_TC;
3819                         policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
3820                         break;
3821                 default:
3822                         continue;
3823                 }
3824
3825                 if (max_cpu_policers <= policer_id &&
3826                     policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
3827                         return -EIO;
3828
3829                 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
3830                 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3831                 if (err)
3832                         return err;
3833         }
3834
3835         return 0;
3836 }
3837
3838 static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
3839 {
3840         int i;
3841         int err;
3842
3843         err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
3844         if (err)
3845                 return err;
3846
3847         err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
3848         if (err)
3849                 return err;
3850
3851         for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
3852                 err = mlxsw_core_trap_register(mlxsw_sp->core,
3853                                                &mlxsw_sp_listener[i],
3854                                                mlxsw_sp);
3855                 if (err)
3856                         goto err_listener_register;
3857
3858         }
3859         return 0;
3860
3861 err_listener_register:
3862         for (i--; i >= 0; i--) {
3863                 mlxsw_core_trap_unregister(mlxsw_sp->core,
3864                                            &mlxsw_sp_listener[i],
3865                                            mlxsw_sp);
3866         }
3867         return err;
3868 }
3869
3870 static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
3871 {
3872         int i;
3873
3874         for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
3875                 mlxsw_core_trap_unregister(mlxsw_sp->core,
3876                                            &mlxsw_sp_listener[i],
3877                                            mlxsw_sp);
3878         }
3879 }
3880
3881 static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
3882 {
3883         char slcr_pl[MLXSW_REG_SLCR_LEN];
3884         u32 seed;
3885         int err;
3886
3887         get_random_bytes(&seed, sizeof(seed));
3888         mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
3889                                      MLXSW_REG_SLCR_LAG_HASH_DMAC |
3890                                      MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
3891                                      MLXSW_REG_SLCR_LAG_HASH_VLANID |
3892                                      MLXSW_REG_SLCR_LAG_HASH_SIP |
3893                                      MLXSW_REG_SLCR_LAG_HASH_DIP |
3894                                      MLXSW_REG_SLCR_LAG_HASH_SPORT |
3895                                      MLXSW_REG_SLCR_LAG_HASH_DPORT |
3896                                      MLXSW_REG_SLCR_LAG_HASH_IPPROTO, seed);
3897         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
3898         if (err)
3899                 return err;
3900
3901         if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
3902             !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
3903                 return -EIO;
3904
3905         mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
3906                                  sizeof(struct mlxsw_sp_upper),
3907                                  GFP_KERNEL);
3908         if (!mlxsw_sp->lags)
3909                 return -ENOMEM;
3910
3911         return 0;
3912 }
3913
3914 static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
3915 {
3916         kfree(mlxsw_sp->lags);
3917 }
3918
3919 static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
3920 {
3921         char htgt_pl[MLXSW_REG_HTGT_LEN];
3922
3923         mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3924                             MLXSW_REG_HTGT_INVALID_POLICER,
3925                             MLXSW_REG_HTGT_DEFAULT_PRIORITY,
3926                             MLXSW_REG_HTGT_DEFAULT_TC);
3927         return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3928 }
3929
3930 static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
3931                                     unsigned long event, void *ptr);
3932
3933 static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
3934                          const struct mlxsw_bus_info *mlxsw_bus_info)
3935 {
3936         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3937         int err;
3938
3939         mlxsw_sp->core = mlxsw_core;
3940         mlxsw_sp->bus_info = mlxsw_bus_info;
3941
3942         err = mlxsw_sp_fw_rev_validate(mlxsw_sp);
3943         if (err)
3944                 return err;
3945
3946         err = mlxsw_sp_base_mac_get(mlxsw_sp);
3947         if (err) {
3948                 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
3949                 return err;
3950         }
3951
3952         err = mlxsw_sp_kvdl_init(mlxsw_sp);
3953         if (err) {
3954                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n");
3955                 return err;
3956         }
3957
3958         err = mlxsw_sp_fids_init(mlxsw_sp);
3959         if (err) {
3960                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
3961                 goto err_fids_init;
3962         }
3963
3964         err = mlxsw_sp_traps_init(mlxsw_sp);
3965         if (err) {
3966                 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
3967                 goto err_traps_init;
3968         }
3969
3970         err = mlxsw_sp_buffers_init(mlxsw_sp);
3971         if (err) {
3972                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
3973                 goto err_buffers_init;
3974         }
3975
3976         err = mlxsw_sp_lag_init(mlxsw_sp);
3977         if (err) {
3978                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
3979                 goto err_lag_init;
3980         }
3981
3982         /* Initialize SPAN before router and switchdev, so that those components
3983          * can call mlxsw_sp_span_respin().
3984          */
3985         err = mlxsw_sp_span_init(mlxsw_sp);
3986         if (err) {
3987                 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
3988                 goto err_span_init;
3989         }
3990
3991         err = mlxsw_sp_switchdev_init(mlxsw_sp);
3992         if (err) {
3993                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
3994                 goto err_switchdev_init;
3995         }
3996
3997         err = mlxsw_sp_counter_pool_init(mlxsw_sp);
3998         if (err) {
3999                 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
4000                 goto err_counter_pool_init;
4001         }
4002
4003         err = mlxsw_sp_afa_init(mlxsw_sp);
4004         if (err) {
4005                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n");
4006                 goto err_afa_init;
4007         }
4008
4009         err = mlxsw_sp_nve_init(mlxsw_sp);
4010         if (err) {
4011                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize NVE\n");
4012                 goto err_nve_init;
4013         }
4014
4015         err = mlxsw_sp_acl_init(mlxsw_sp);
4016         if (err) {
4017                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
4018                 goto err_acl_init;
4019         }
4020
4021         err = mlxsw_sp_router_init(mlxsw_sp);
4022         if (err) {
4023                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
4024                 goto err_router_init;
4025         }
4026
4027         /* Initialize netdevice notifier after router and SPAN is initialized,
4028          * so that the event handler can use router structures and call SPAN
4029          * respin.
4030          */
4031         mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event;
4032         err = register_netdevice_notifier(&mlxsw_sp->netdevice_nb);
4033         if (err) {
4034                 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n");
4035                 goto err_netdev_notifier;
4036         }
4037
4038         err = mlxsw_sp_dpipe_init(mlxsw_sp);
4039         if (err) {
4040                 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
4041                 goto err_dpipe_init;
4042         }
4043
4044         err = mlxsw_sp_ports_create(mlxsw_sp);
4045         if (err) {
4046                 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
4047                 goto err_ports_create;
4048         }
4049
4050         return 0;
4051
4052 err_ports_create:
4053         mlxsw_sp_dpipe_fini(mlxsw_sp);
4054 err_dpipe_init:
4055         unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
4056 err_netdev_notifier:
4057         mlxsw_sp_router_fini(mlxsw_sp);
4058 err_router_init:
4059         mlxsw_sp_acl_fini(mlxsw_sp);
4060 err_acl_init:
4061         mlxsw_sp_nve_fini(mlxsw_sp);
4062 err_nve_init:
4063         mlxsw_sp_afa_fini(mlxsw_sp);
4064 err_afa_init:
4065         mlxsw_sp_counter_pool_fini(mlxsw_sp);
4066 err_counter_pool_init:
4067         mlxsw_sp_switchdev_fini(mlxsw_sp);
4068 err_switchdev_init:
4069         mlxsw_sp_span_fini(mlxsw_sp);
4070 err_span_init:
4071         mlxsw_sp_lag_fini(mlxsw_sp);
4072 err_lag_init:
4073         mlxsw_sp_buffers_fini(mlxsw_sp);
4074 err_buffers_init:
4075         mlxsw_sp_traps_fini(mlxsw_sp);
4076 err_traps_init:
4077         mlxsw_sp_fids_fini(mlxsw_sp);
4078 err_fids_init:
4079         mlxsw_sp_kvdl_fini(mlxsw_sp);
4080         return err;
4081 }
4082
4083 static int mlxsw_sp1_init(struct mlxsw_core *mlxsw_core,
4084                           const struct mlxsw_bus_info *mlxsw_bus_info)
4085 {
4086         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
4087
4088         mlxsw_sp->req_rev = &mlxsw_sp1_fw_rev;
4089         mlxsw_sp->fw_filename = MLXSW_SP1_FW_FILENAME;
4090         mlxsw_sp->kvdl_ops = &mlxsw_sp1_kvdl_ops;
4091         mlxsw_sp->afa_ops = &mlxsw_sp1_act_afa_ops;
4092         mlxsw_sp->afk_ops = &mlxsw_sp1_afk_ops;
4093         mlxsw_sp->mr_tcam_ops = &mlxsw_sp1_mr_tcam_ops;
4094         mlxsw_sp->acl_tcam_ops = &mlxsw_sp1_acl_tcam_ops;
4095         mlxsw_sp->nve_ops_arr = mlxsw_sp1_nve_ops_arr;
4096         mlxsw_sp->mac_mask = mlxsw_sp1_mac_mask;
4097
4098         return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info);
4099 }
4100
4101 static int mlxsw_sp2_init(struct mlxsw_core *mlxsw_core,
4102                           const struct mlxsw_bus_info *mlxsw_bus_info)
4103 {
4104         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
4105
4106         mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops;
4107         mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops;
4108         mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops;
4109         mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops;
4110         mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops;
4111         mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr;
4112         mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask;
4113
4114         return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info);
4115 }
4116
4117 static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
4118 {
4119         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
4120
4121         mlxsw_sp_ports_remove(mlxsw_sp);
4122         mlxsw_sp_dpipe_fini(mlxsw_sp);
4123         unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
4124         mlxsw_sp_router_fini(mlxsw_sp);
4125         mlxsw_sp_acl_fini(mlxsw_sp);
4126         mlxsw_sp_nve_fini(mlxsw_sp);
4127         mlxsw_sp_afa_fini(mlxsw_sp);
4128         mlxsw_sp_counter_pool_fini(mlxsw_sp);
4129         mlxsw_sp_switchdev_fini(mlxsw_sp);
4130         mlxsw_sp_span_fini(mlxsw_sp);
4131         mlxsw_sp_lag_fini(mlxsw_sp);
4132         mlxsw_sp_buffers_fini(mlxsw_sp);
4133         mlxsw_sp_traps_fini(mlxsw_sp);
4134         mlxsw_sp_fids_fini(mlxsw_sp);
4135         mlxsw_sp_kvdl_fini(mlxsw_sp);
4136 }
4137
4138 /* Per-FID flood tables are used for both "true" 802.1D FIDs and emulated
4139  * 802.1Q FIDs
4140  */
4141 #define MLXSW_SP_FID_FLOOD_TABLE_SIZE   (MLXSW_SP_FID_8021D_MAX + \
4142                                          VLAN_VID_MASK - 1)
4143
4144 static const struct mlxsw_config_profile mlxsw_sp1_config_profile = {
4145         .used_max_mid                   = 1,
4146         .max_mid                        = MLXSW_SP_MID_MAX,
4147         .used_flood_tables              = 1,
4148         .used_flood_mode                = 1,
4149         .flood_mode                     = 3,
4150         .max_fid_flood_tables           = 3,
4151         .fid_flood_table_size           = MLXSW_SP_FID_FLOOD_TABLE_SIZE,
4152         .used_max_ib_mc                 = 1,
4153         .max_ib_mc                      = 0,
4154         .used_max_pkey                  = 1,
4155         .max_pkey                       = 0,
4156         .used_kvd_sizes                 = 1,
4157         .kvd_hash_single_parts          = 59,
4158         .kvd_hash_double_parts          = 41,
4159         .kvd_linear_size                = MLXSW_SP_KVD_LINEAR_SIZE,
4160         .swid_config                    = {
4161                 {
4162                         .used_type      = 1,
4163                         .type           = MLXSW_PORT_SWID_TYPE_ETH,
4164                 }
4165         },
4166 };
4167
4168 static const struct mlxsw_config_profile mlxsw_sp2_config_profile = {
4169         .used_max_mid                   = 1,
4170         .max_mid                        = MLXSW_SP_MID_MAX,
4171         .used_flood_tables              = 1,
4172         .used_flood_mode                = 1,
4173         .flood_mode                     = 3,
4174         .max_fid_flood_tables           = 3,
4175         .fid_flood_table_size           = MLXSW_SP_FID_FLOOD_TABLE_SIZE,
4176         .used_max_ib_mc                 = 1,
4177         .max_ib_mc                      = 0,
4178         .used_max_pkey                  = 1,
4179         .max_pkey                       = 0,
4180         .swid_config                    = {
4181                 {
4182                         .used_type      = 1,
4183                         .type           = MLXSW_PORT_SWID_TYPE_ETH,
4184                 }
4185         },
4186 };
4187
4188 static void
4189 mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core,
4190                                       struct devlink_resource_size_params *kvd_size_params,
4191                                       struct devlink_resource_size_params *linear_size_params,
4192                                       struct devlink_resource_size_params *hash_double_size_params,
4193                                       struct devlink_resource_size_params *hash_single_size_params)
4194 {
4195         u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
4196                                                  KVD_SINGLE_MIN_SIZE);
4197         u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
4198                                                  KVD_DOUBLE_MIN_SIZE);
4199         u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
4200         u32 linear_size_min = 0;
4201
4202         devlink_resource_size_params_init(kvd_size_params, kvd_size, kvd_size,
4203                                           MLXSW_SP_KVD_GRANULARITY,
4204                                           DEVLINK_RESOURCE_UNIT_ENTRY);
4205         devlink_resource_size_params_init(linear_size_params, linear_size_min,
4206                                           kvd_size - single_size_min -
4207                                           double_size_min,
4208                                           MLXSW_SP_KVD_GRANULARITY,
4209                                           DEVLINK_RESOURCE_UNIT_ENTRY);
4210         devlink_resource_size_params_init(hash_double_size_params,
4211                                           double_size_min,
4212                                           kvd_size - single_size_min -
4213                                           linear_size_min,
4214                                           MLXSW_SP_KVD_GRANULARITY,
4215                                           DEVLINK_RESOURCE_UNIT_ENTRY);
4216         devlink_resource_size_params_init(hash_single_size_params,
4217                                           single_size_min,
4218                                           kvd_size - double_size_min -
4219                                           linear_size_min,
4220                                           MLXSW_SP_KVD_GRANULARITY,
4221                                           DEVLINK_RESOURCE_UNIT_ENTRY);
4222 }
4223
4224 static int mlxsw_sp1_resources_kvd_register(struct mlxsw_core *mlxsw_core)
4225 {
4226         struct devlink *devlink = priv_to_devlink(mlxsw_core);
4227         struct devlink_resource_size_params hash_single_size_params;
4228         struct devlink_resource_size_params hash_double_size_params;
4229         struct devlink_resource_size_params linear_size_params;
4230         struct devlink_resource_size_params kvd_size_params;
4231         u32 kvd_size, single_size, double_size, linear_size;
4232         const struct mlxsw_config_profile *profile;
4233         int err;
4234
4235         profile = &mlxsw_sp1_config_profile;
4236         if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
4237                 return -EIO;
4238
4239         mlxsw_sp_resource_size_params_prepare(mlxsw_core, &kvd_size_params,
4240                                               &linear_size_params,
4241                                               &hash_double_size_params,
4242                                               &hash_single_size_params);
4243
4244         kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
4245         err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
4246                                         kvd_size, MLXSW_SP_RESOURCE_KVD,
4247                                         DEVLINK_RESOURCE_ID_PARENT_TOP,
4248                                         &kvd_size_params);
4249         if (err)
4250                 return err;
4251
4252         linear_size = profile->kvd_linear_size;
4253         err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR,
4254                                         linear_size,
4255                                         MLXSW_SP_RESOURCE_KVD_LINEAR,
4256                                         MLXSW_SP_RESOURCE_KVD,
4257                                         &linear_size_params);
4258         if (err)
4259                 return err;
4260
4261         err = mlxsw_sp1_kvdl_resources_register(mlxsw_core);
4262         if  (err)
4263                 return err;
4264
4265         double_size = kvd_size - linear_size;
4266         double_size *= profile->kvd_hash_double_parts;
4267         double_size /= profile->kvd_hash_double_parts +
4268                        profile->kvd_hash_single_parts;
4269         double_size = rounddown(double_size, MLXSW_SP_KVD_GRANULARITY);
4270         err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE,
4271                                         double_size,
4272                                         MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
4273                                         MLXSW_SP_RESOURCE_KVD,
4274                                         &hash_double_size_params);
4275         if (err)
4276                 return err;
4277
4278         single_size = kvd_size - double_size - linear_size;
4279         err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE,
4280                                         single_size,
4281                                         MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
4282                                         MLXSW_SP_RESOURCE_KVD,
4283                                         &hash_single_size_params);
4284         if (err)
4285                 return err;
4286
4287         return 0;
4288 }
4289
4290 static int mlxsw_sp1_resources_register(struct mlxsw_core *mlxsw_core)
4291 {
4292         return mlxsw_sp1_resources_kvd_register(mlxsw_core);
4293 }
4294
4295 static int mlxsw_sp2_resources_register(struct mlxsw_core *mlxsw_core)
4296 {
4297         return 0;
4298 }
4299
4300 static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core,
4301                                   const struct mlxsw_config_profile *profile,
4302                                   u64 *p_single_size, u64 *p_double_size,
4303                                   u64 *p_linear_size)
4304 {
4305         struct devlink *devlink = priv_to_devlink(mlxsw_core);
4306         u32 double_size;
4307         int err;
4308
4309         if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
4310             !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE))
4311                 return -EIO;
4312
4313         /* The hash part is what left of the kvd without the
4314          * linear part. It is split to the single size and
4315          * double size by the parts ratio from the profile.
4316          * Both sizes must be a multiplications of the
4317          * granularity from the profile. In case the user
4318          * provided the sizes they are obtained via devlink.
4319          */
4320         err = devlink_resource_size_get(devlink,
4321                                         MLXSW_SP_RESOURCE_KVD_LINEAR,
4322                                         p_linear_size);
4323         if (err)
4324                 *p_linear_size = profile->kvd_linear_size;
4325
4326         err = devlink_resource_size_get(devlink,
4327                                         MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
4328                                         p_double_size);
4329         if (err) {
4330                 double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
4331                               *p_linear_size;
4332                 double_size *= profile->kvd_hash_double_parts;
4333                 double_size /= profile->kvd_hash_double_parts +
4334                                profile->kvd_hash_single_parts;
4335                 *p_double_size = rounddown(double_size,
4336                                            MLXSW_SP_KVD_GRANULARITY);
4337         }
4338
4339         err = devlink_resource_size_get(devlink,
4340                                         MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
4341                                         p_single_size);
4342         if (err)
4343                 *p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
4344                                  *p_double_size - *p_linear_size;
4345
4346         /* Check results are legal. */
4347         if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
4348             *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
4349             MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size)
4350                 return -EIO;
4351
4352         return 0;
4353 }
4354
4355 static int
4356 mlxsw_sp_devlink_param_fw_load_policy_validate(struct devlink *devlink, u32 id,
4357                                                union devlink_param_value val,
4358                                                struct netlink_ext_ack *extack)
4359 {
4360         if ((val.vu8 != DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_DRIVER) &&
4361             (val.vu8 != DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_FLASH)) {
4362                 NL_SET_ERR_MSG_MOD(extack, "'fw_load_policy' must be 'driver' or 'flash'");
4363                 return -EINVAL;
4364         }
4365
4366         return 0;
4367 }
4368
4369 static const struct devlink_param mlxsw_sp_devlink_params[] = {
4370         DEVLINK_PARAM_GENERIC(FW_LOAD_POLICY,
4371                               BIT(DEVLINK_PARAM_CMODE_DRIVERINIT),
4372                               NULL, NULL,
4373                               mlxsw_sp_devlink_param_fw_load_policy_validate),
4374 };
4375
4376 static int mlxsw_sp_params_register(struct mlxsw_core *mlxsw_core)
4377 {
4378         struct devlink *devlink = priv_to_devlink(mlxsw_core);
4379         union devlink_param_value value;
4380         int err;
4381
4382         err = devlink_params_register(devlink, mlxsw_sp_devlink_params,
4383                                       ARRAY_SIZE(mlxsw_sp_devlink_params));
4384         if (err)
4385                 return err;
4386
4387         value.vu8 = DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_DRIVER;
4388         devlink_param_driverinit_value_set(devlink,
4389                                            DEVLINK_PARAM_GENERIC_ID_FW_LOAD_POLICY,
4390                                            value);
4391         return 0;
4392 }
4393
4394 static void mlxsw_sp_params_unregister(struct mlxsw_core *mlxsw_core)
4395 {
4396         devlink_params_unregister(priv_to_devlink(mlxsw_core),
4397                                   mlxsw_sp_devlink_params,
4398                                   ARRAY_SIZE(mlxsw_sp_devlink_params));
4399 }
4400
4401 static struct mlxsw_driver mlxsw_sp1_driver = {
4402         .kind                           = mlxsw_sp1_driver_name,
4403         .priv_size                      = sizeof(struct mlxsw_sp),
4404         .init                           = mlxsw_sp1_init,
4405         .fini                           = mlxsw_sp_fini,
4406         .basic_trap_groups_set          = mlxsw_sp_basic_trap_groups_set,
4407         .port_split                     = mlxsw_sp_port_split,
4408         .port_unsplit                   = mlxsw_sp_port_unsplit,
4409         .sb_pool_get                    = mlxsw_sp_sb_pool_get,
4410         .sb_pool_set                    = mlxsw_sp_sb_pool_set,
4411         .sb_port_pool_get               = mlxsw_sp_sb_port_pool_get,
4412         .sb_port_pool_set               = mlxsw_sp_sb_port_pool_set,
4413         .sb_tc_pool_bind_get            = mlxsw_sp_sb_tc_pool_bind_get,
4414         .sb_tc_pool_bind_set            = mlxsw_sp_sb_tc_pool_bind_set,
4415         .sb_occ_snapshot                = mlxsw_sp_sb_occ_snapshot,
4416         .sb_occ_max_clear               = mlxsw_sp_sb_occ_max_clear,
4417         .sb_occ_port_pool_get           = mlxsw_sp_sb_occ_port_pool_get,
4418         .sb_occ_tc_port_bind_get        = mlxsw_sp_sb_occ_tc_port_bind_get,
4419         .txhdr_construct                = mlxsw_sp_txhdr_construct,
4420         .resources_register             = mlxsw_sp1_resources_register,
4421         .kvd_sizes_get                  = mlxsw_sp_kvd_sizes_get,
4422         .params_register                = mlxsw_sp_params_register,
4423         .params_unregister              = mlxsw_sp_params_unregister,
4424         .txhdr_len                      = MLXSW_TXHDR_LEN,
4425         .profile                        = &mlxsw_sp1_config_profile,
4426         .res_query_enabled              = true,
4427 };
4428
4429 static struct mlxsw_driver mlxsw_sp2_driver = {
4430         .kind                           = mlxsw_sp2_driver_name,
4431         .priv_size                      = sizeof(struct mlxsw_sp),
4432         .init                           = mlxsw_sp2_init,
4433         .fini                           = mlxsw_sp_fini,
4434         .basic_trap_groups_set          = mlxsw_sp_basic_trap_groups_set,
4435         .port_split                     = mlxsw_sp_port_split,
4436         .port_unsplit                   = mlxsw_sp_port_unsplit,
4437         .sb_pool_get                    = mlxsw_sp_sb_pool_get,
4438         .sb_pool_set                    = mlxsw_sp_sb_pool_set,
4439         .sb_port_pool_get               = mlxsw_sp_sb_port_pool_get,
4440         .sb_port_pool_set               = mlxsw_sp_sb_port_pool_set,
4441         .sb_tc_pool_bind_get            = mlxsw_sp_sb_tc_pool_bind_get,
4442         .sb_tc_pool_bind_set            = mlxsw_sp_sb_tc_pool_bind_set,
4443         .sb_occ_snapshot                = mlxsw_sp_sb_occ_snapshot,
4444         .sb_occ_max_clear               = mlxsw_sp_sb_occ_max_clear,
4445         .sb_occ_port_pool_get           = mlxsw_sp_sb_occ_port_pool_get,
4446         .sb_occ_tc_port_bind_get        = mlxsw_sp_sb_occ_tc_port_bind_get,
4447         .txhdr_construct                = mlxsw_sp_txhdr_construct,
4448         .resources_register             = mlxsw_sp2_resources_register,
4449         .params_register                = mlxsw_sp_params_register,
4450         .params_unregister              = mlxsw_sp_params_unregister,
4451         .txhdr_len                      = MLXSW_TXHDR_LEN,
4452         .profile                        = &mlxsw_sp2_config_profile,
4453         .res_query_enabled              = true,
4454 };
4455
4456 bool mlxsw_sp_port_dev_check(const struct net_device *dev)
4457 {
4458         return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
4459 }
4460
4461 static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
4462 {
4463         struct mlxsw_sp_port **p_mlxsw_sp_port = data;
4464         int ret = 0;
4465
4466         if (mlxsw_sp_port_dev_check(lower_dev)) {
4467                 *p_mlxsw_sp_port = netdev_priv(lower_dev);
4468                 ret = 1;
4469         }
4470
4471         return ret;
4472 }
4473
4474 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
4475 {
4476         struct mlxsw_sp_port *mlxsw_sp_port;
4477
4478         if (mlxsw_sp_port_dev_check(dev))
4479                 return netdev_priv(dev);
4480
4481         mlxsw_sp_port = NULL;
4482         netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
4483
4484         return mlxsw_sp_port;
4485 }
4486
4487 struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
4488 {
4489         struct mlxsw_sp_port *mlxsw_sp_port;
4490
4491         mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
4492         return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
4493 }
4494
4495 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
4496 {
4497         struct mlxsw_sp_port *mlxsw_sp_port;
4498
4499         if (mlxsw_sp_port_dev_check(dev))
4500                 return netdev_priv(dev);
4501
4502         mlxsw_sp_port = NULL;
4503         netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
4504                                       &mlxsw_sp_port);
4505
4506         return mlxsw_sp_port;
4507 }
4508
4509 struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
4510 {
4511         struct mlxsw_sp_port *mlxsw_sp_port;
4512
4513         rcu_read_lock();
4514         mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
4515         if (mlxsw_sp_port)
4516                 dev_hold(mlxsw_sp_port->dev);
4517         rcu_read_unlock();
4518         return mlxsw_sp_port;
4519 }
4520
4521 void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
4522 {
4523         dev_put(mlxsw_sp_port->dev);
4524 }
4525
4526 static void
4527 mlxsw_sp_port_lag_uppers_cleanup(struct mlxsw_sp_port *mlxsw_sp_port,
4528                                  struct net_device *lag_dev)
4529 {
4530         struct net_device *br_dev = netdev_master_upper_dev_get(lag_dev);
4531         struct net_device *upper_dev;
4532         struct list_head *iter;
4533
4534         if (netif_is_bridge_port(lag_dev))
4535                 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, lag_dev, br_dev);
4536
4537         netdev_for_each_upper_dev_rcu(lag_dev, upper_dev, iter) {
4538                 if (!netif_is_bridge_port(upper_dev))
4539                         continue;
4540                 br_dev = netdev_master_upper_dev_get(upper_dev);
4541                 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev, br_dev);
4542         }
4543 }
4544
4545 static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
4546 {
4547         char sldr_pl[MLXSW_REG_SLDR_LEN];
4548
4549         mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
4550         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4551 }
4552
4553 static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
4554 {
4555         char sldr_pl[MLXSW_REG_SLDR_LEN];
4556
4557         mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
4558         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4559 }
4560
4561 static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4562                                      u16 lag_id, u8 port_index)
4563 {
4564         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4565         char slcor_pl[MLXSW_REG_SLCOR_LEN];
4566
4567         mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
4568                                       lag_id, port_index);
4569         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4570 }
4571
4572 static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4573                                         u16 lag_id)
4574 {
4575         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4576         char slcor_pl[MLXSW_REG_SLCOR_LEN];
4577
4578         mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
4579                                          lag_id);
4580         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4581 }
4582
4583 static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
4584                                         u16 lag_id)
4585 {
4586         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4587         char slcor_pl[MLXSW_REG_SLCOR_LEN];
4588
4589         mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
4590                                         lag_id);
4591         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4592 }
4593
4594 static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
4595                                          u16 lag_id)
4596 {
4597         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4598         char slcor_pl[MLXSW_REG_SLCOR_LEN];
4599
4600         mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
4601                                          lag_id);
4602         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4603 }
4604
4605 static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4606                                   struct net_device *lag_dev,
4607                                   u16 *p_lag_id)
4608 {
4609         struct mlxsw_sp_upper *lag;
4610         int free_lag_id = -1;
4611         u64 max_lag;
4612         int i;
4613
4614         max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
4615         for (i = 0; i < max_lag; i++) {
4616                 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
4617                 if (lag->ref_count) {
4618                         if (lag->dev == lag_dev) {
4619                                 *p_lag_id = i;
4620                                 return 0;
4621                         }
4622                 } else if (free_lag_id < 0) {
4623                         free_lag_id = i;
4624                 }
4625         }
4626         if (free_lag_id < 0)
4627                 return -EBUSY;
4628         *p_lag_id = free_lag_id;
4629         return 0;
4630 }
4631
4632 static bool
4633 mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
4634                           struct net_device *lag_dev,
4635                           struct netdev_lag_upper_info *lag_upper_info,
4636                           struct netlink_ext_ack *extack)
4637 {
4638         u16 lag_id;
4639
4640         if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) {
4641                 NL_SET_ERR_MSG_MOD(extack, "Exceeded number of supported LAG devices");
4642                 return false;
4643         }
4644         if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
4645                 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type");
4646                 return false;
4647         }
4648         return true;
4649 }
4650
4651 static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4652                                        u16 lag_id, u8 *p_port_index)
4653 {
4654         u64 max_lag_members;
4655         int i;
4656
4657         max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
4658                                              MAX_LAG_MEMBERS);
4659         for (i = 0; i < max_lag_members; i++) {
4660                 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
4661                         *p_port_index = i;
4662                         return 0;
4663                 }
4664         }
4665         return -EBUSY;
4666 }
4667
4668 static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
4669                                   struct net_device *lag_dev)
4670 {
4671         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4672         struct mlxsw_sp_upper *lag;
4673         u16 lag_id;
4674         u8 port_index;
4675         int err;
4676
4677         err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
4678         if (err)
4679                 return err;
4680         lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4681         if (!lag->ref_count) {
4682                 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
4683                 if (err)
4684                         return err;
4685                 lag->dev = lag_dev;
4686         }
4687
4688         err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
4689         if (err)
4690                 return err;
4691         err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
4692         if (err)
4693                 goto err_col_port_add;
4694         err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
4695         if (err)
4696                 goto err_col_port_enable;
4697
4698         mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
4699                                    mlxsw_sp_port->local_port);
4700         mlxsw_sp_port->lag_id = lag_id;
4701         mlxsw_sp_port->lagged = 1;
4702         lag->ref_count++;
4703
4704         /* Port is no longer usable as a router interface */
4705         if (mlxsw_sp_port->default_vlan->fid)
4706                 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port->default_vlan);
4707
4708         return 0;
4709
4710 err_col_port_enable:
4711         mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
4712 err_col_port_add:
4713         if (!lag->ref_count)
4714                 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
4715         return err;
4716 }
4717
4718 static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
4719                                     struct net_device *lag_dev)
4720 {
4721         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4722         u16 lag_id = mlxsw_sp_port->lag_id;
4723         struct mlxsw_sp_upper *lag;
4724
4725         if (!mlxsw_sp_port->lagged)
4726                 return;
4727         lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4728         WARN_ON(lag->ref_count == 0);
4729
4730         mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
4731         mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
4732
4733         /* Any VLANs configured on the port are no longer valid */
4734         mlxsw_sp_port_vlan_flush(mlxsw_sp_port, false);
4735         mlxsw_sp_port_vlan_cleanup(mlxsw_sp_port->default_vlan);
4736         /* Make the LAG and its directly linked uppers leave bridges they
4737          * are memeber in
4738          */
4739         mlxsw_sp_port_lag_uppers_cleanup(mlxsw_sp_port, lag_dev);
4740
4741         if (lag->ref_count == 1)
4742                 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
4743
4744         mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4745                                      mlxsw_sp_port->local_port);
4746         mlxsw_sp_port->lagged = 0;
4747         lag->ref_count--;
4748
4749         /* Make sure untagged frames are allowed to ingress */
4750         mlxsw_sp_port_pvid_set(mlxsw_sp_port, MLXSW_SP_DEFAULT_VID);
4751 }
4752
4753 static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4754                                       u16 lag_id)
4755 {
4756         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4757         char sldr_pl[MLXSW_REG_SLDR_LEN];
4758
4759         mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
4760                                          mlxsw_sp_port->local_port);
4761         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4762 }
4763
4764 static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4765                                          u16 lag_id)
4766 {
4767         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4768         char sldr_pl[MLXSW_REG_SLDR_LEN];
4769
4770         mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
4771                                             mlxsw_sp_port->local_port);
4772         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4773 }
4774
4775 static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
4776                                        bool lag_tx_enabled)
4777 {
4778         if (lag_tx_enabled)
4779                 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
4780                                                   mlxsw_sp_port->lag_id);
4781         else
4782                 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
4783                                                      mlxsw_sp_port->lag_id);
4784 }
4785
4786 static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
4787                                      struct netdev_lag_lower_state_info *info)
4788 {
4789         return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
4790 }
4791
4792 static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
4793                                  bool enable)
4794 {
4795         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4796         enum mlxsw_reg_spms_state spms_state;
4797         char *spms_pl;
4798         u16 vid;
4799         int err;
4800
4801         spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
4802                               MLXSW_REG_SPMS_STATE_DISCARDING;
4803
4804         spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
4805         if (!spms_pl)
4806                 return -ENOMEM;
4807         mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
4808
4809         for (vid = 0; vid < VLAN_N_VID; vid++)
4810                 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
4811
4812         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
4813         kfree(spms_pl);
4814         return err;
4815 }
4816
4817 static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
4818 {
4819         u16 vid = 1;
4820         int err;
4821
4822         err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
4823         if (err)
4824                 return err;
4825         err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
4826         if (err)
4827                 goto err_port_stp_set;
4828         err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 1, VLAN_N_VID - 2,
4829                                      true, false);
4830         if (err)
4831                 goto err_port_vlan_set;
4832
4833         for (; vid <= VLAN_N_VID - 1; vid++) {
4834                 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4835                                                      vid, false);
4836                 if (err)
4837                         goto err_vid_learning_set;
4838         }
4839
4840         return 0;
4841
4842 err_vid_learning_set:
4843         for (vid--; vid >= 1; vid--)
4844                 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true);
4845 err_port_vlan_set:
4846         mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
4847 err_port_stp_set:
4848         mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
4849         return err;
4850 }
4851
4852 static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4853 {
4854         u16 vid;
4855
4856         for (vid = VLAN_N_VID - 1; vid >= 1; vid--)
4857                 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4858                                                vid, true);
4859
4860         mlxsw_sp_port_vlan_set(mlxsw_sp_port, 1, VLAN_N_VID - 2,
4861                                false, false);
4862         mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
4863         mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
4864 }
4865
4866 static bool mlxsw_sp_bridge_has_multiple_vxlans(struct net_device *br_dev)
4867 {
4868         unsigned int num_vxlans = 0;
4869         struct net_device *dev;
4870         struct list_head *iter;
4871
4872         netdev_for_each_lower_dev(br_dev, dev, iter) {
4873                 if (netif_is_vxlan(dev))
4874                         num_vxlans++;
4875         }
4876
4877         return num_vxlans > 1;
4878 }
4879
4880 static bool mlxsw_sp_bridge_vxlan_vlan_is_valid(struct net_device *br_dev)
4881 {
4882         DECLARE_BITMAP(vlans, VLAN_N_VID) = {0};
4883         struct net_device *dev;
4884         struct list_head *iter;
4885
4886         netdev_for_each_lower_dev(br_dev, dev, iter) {
4887                 u16 pvid;
4888                 int err;
4889
4890                 if (!netif_is_vxlan(dev))
4891                         continue;
4892
4893                 err = mlxsw_sp_vxlan_mapped_vid(dev, &pvid);
4894                 if (err || !pvid)
4895                         continue;
4896
4897                 if (test_and_set_bit(pvid, vlans))
4898                         return false;
4899         }
4900
4901         return true;
4902 }
4903
4904 static bool mlxsw_sp_bridge_vxlan_is_valid(struct net_device *br_dev,
4905                                            struct netlink_ext_ack *extack)
4906 {
4907         if (br_multicast_enabled(br_dev)) {
4908                 NL_SET_ERR_MSG_MOD(extack, "Multicast can not be enabled on a bridge with a VxLAN device");
4909                 return false;
4910         }
4911
4912         if (!br_vlan_enabled(br_dev) &&
4913             mlxsw_sp_bridge_has_multiple_vxlans(br_dev)) {
4914                 NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices are not supported in a VLAN-unaware bridge");
4915                 return false;
4916         }
4917
4918         if (br_vlan_enabled(br_dev) &&
4919             !mlxsw_sp_bridge_vxlan_vlan_is_valid(br_dev)) {
4920                 NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices cannot have the same VLAN as PVID and egress untagged");
4921                 return false;
4922         }
4923
4924         return true;
4925 }
4926
4927 static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
4928                                                struct net_device *dev,
4929                                                unsigned long event, void *ptr)
4930 {
4931         struct netdev_notifier_changeupper_info *info;
4932         struct mlxsw_sp_port *mlxsw_sp_port;
4933         struct netlink_ext_ack *extack;
4934         struct net_device *upper_dev;
4935         struct mlxsw_sp *mlxsw_sp;
4936         int err = 0;
4937
4938         mlxsw_sp_port = netdev_priv(dev);
4939         mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4940         info = ptr;
4941         extack = netdev_notifier_info_to_extack(&info->info);
4942
4943         switch (event) {
4944         case NETDEV_PRECHANGEUPPER:
4945                 upper_dev = info->upper_dev;
4946                 if (!is_vlan_dev(upper_dev) &&
4947                     !netif_is_lag_master(upper_dev) &&
4948                     !netif_is_bridge_master(upper_dev) &&
4949                     !netif_is_ovs_master(upper_dev) &&
4950                     !netif_is_macvlan(upper_dev)) {
4951                         NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
4952                         return -EINVAL;
4953                 }
4954                 if (!info->linking)
4955                         break;
4956                 if (netif_is_bridge_master(upper_dev) &&
4957                     !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) &&
4958                     mlxsw_sp_bridge_has_vxlan(upper_dev) &&
4959                     !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
4960                         return -EOPNOTSUPP;
4961                 if (netdev_has_any_upper_dev(upper_dev) &&
4962                     (!netif_is_bridge_master(upper_dev) ||
4963                      !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4964                                                           upper_dev))) {
4965                         NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
4966                         return -EINVAL;
4967                 }
4968                 if (netif_is_lag_master(upper_dev) &&
4969                     !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
4970                                                info->upper_info, extack))
4971                         return -EINVAL;
4972                 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) {
4973                         NL_SET_ERR_MSG_MOD(extack, "Master device is a LAG master and this device has a VLAN");
4974                         return -EINVAL;
4975                 }
4976                 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
4977                     !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) {
4978                         NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on a LAG port");
4979                         return -EINVAL;
4980                 }
4981                 if (netif_is_macvlan(upper_dev) &&
4982                     !mlxsw_sp_rif_find_by_dev(mlxsw_sp, lower_dev)) {
4983                         NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
4984                         return -EOPNOTSUPP;
4985                 }
4986                 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) {
4987                         NL_SET_ERR_MSG_MOD(extack, "Master device is an OVS master and this device has a VLAN");
4988                         return -EINVAL;
4989                 }
4990                 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) {
4991                         NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on an OVS port");
4992                         return -EINVAL;
4993                 }
4994                 break;
4995         case NETDEV_CHANGEUPPER:
4996                 upper_dev = info->upper_dev;
4997                 if (netif_is_bridge_master(upper_dev)) {
4998                         if (info->linking)
4999                                 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
5000                                                                 lower_dev,
5001                                                                 upper_dev,
5002                                                                 extack);
5003                         else
5004                                 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
5005                                                            lower_dev,
5006                                                            upper_dev);
5007                 } else if (netif_is_lag_master(upper_dev)) {
5008                         if (info->linking) {
5009                                 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
5010                                                              upper_dev);
5011                         } else {
5012                                 mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port,
5013                                                             false);
5014                                 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
5015                                                         upper_dev);
5016                         }
5017                 } else if (netif_is_ovs_master(upper_dev)) {
5018                         if (info->linking)
5019                                 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
5020                         else
5021                                 mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
5022                 } else if (netif_is_macvlan(upper_dev)) {
5023                         if (!info->linking)
5024                                 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
5025                 } else if (is_vlan_dev(upper_dev)) {
5026                         struct net_device *br_dev;
5027
5028                         if (!netif_is_bridge_port(upper_dev))
5029                                 break;
5030                         if (info->linking)
5031                                 break;
5032                         br_dev = netdev_master_upper_dev_get(upper_dev);
5033                         mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev,
5034                                                    br_dev);
5035                 }
5036                 break;
5037         }
5038
5039         return err;
5040 }
5041
5042 static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
5043                                                unsigned long event, void *ptr)
5044 {
5045         struct netdev_notifier_changelowerstate_info *info;
5046         struct mlxsw_sp_port *mlxsw_sp_port;
5047         int err;
5048
5049         mlxsw_sp_port = netdev_priv(dev);
5050         info = ptr;
5051
5052         switch (event) {
5053         case NETDEV_CHANGELOWERSTATE:
5054                 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
5055                         err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
5056                                                         info->lower_state_info);
5057                         if (err)
5058                                 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
5059                 }
5060                 break;
5061         }
5062
5063         return 0;
5064 }
5065
5066 static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
5067                                          struct net_device *port_dev,
5068                                          unsigned long event, void *ptr)
5069 {
5070         switch (event) {
5071         case NETDEV_PRECHANGEUPPER:
5072         case NETDEV_CHANGEUPPER:
5073                 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
5074                                                            event, ptr);
5075         case NETDEV_CHANGELOWERSTATE:
5076                 return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
5077                                                            ptr);
5078         }
5079
5080         return 0;
5081 }
5082
5083 static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
5084                                         unsigned long event, void *ptr)
5085 {
5086         struct net_device *dev;
5087         struct list_head *iter;
5088         int ret;
5089
5090         netdev_for_each_lower_dev(lag_dev, dev, iter) {
5091                 if (mlxsw_sp_port_dev_check(dev)) {
5092                         ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
5093                                                             ptr);
5094                         if (ret)
5095                                 return ret;
5096                 }
5097         }
5098
5099         return 0;
5100 }
5101
5102 static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
5103                                               struct net_device *dev,
5104                                               unsigned long event, void *ptr,
5105                                               u16 vid)
5106 {
5107         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
5108         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5109         struct netdev_notifier_changeupper_info *info = ptr;
5110         struct netlink_ext_ack *extack;
5111         struct net_device *upper_dev;
5112         int err = 0;
5113
5114         extack = netdev_notifier_info_to_extack(&info->info);
5115
5116         switch (event) {
5117         case NETDEV_PRECHANGEUPPER:
5118                 upper_dev = info->upper_dev;
5119                 if (!netif_is_bridge_master(upper_dev) &&
5120                     !netif_is_macvlan(upper_dev)) {
5121                         NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
5122                         return -EINVAL;
5123                 }
5124                 if (!info->linking)
5125                         break;
5126                 if (netif_is_bridge_master(upper_dev) &&
5127                     !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) &&
5128                     mlxsw_sp_bridge_has_vxlan(upper_dev) &&
5129                     !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
5130                         return -EOPNOTSUPP;
5131                 if (netdev_has_any_upper_dev(upper_dev) &&
5132                     (!netif_is_bridge_master(upper_dev) ||
5133                      !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
5134                                                           upper_dev))) {
5135                         NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
5136                         return -EINVAL;
5137                 }
5138                 if (netif_is_macvlan(upper_dev) &&
5139                     !mlxsw_sp_rif_find_by_dev(mlxsw_sp, vlan_dev)) {
5140                         NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
5141                         return -EOPNOTSUPP;
5142                 }
5143                 break;
5144         case NETDEV_CHANGEUPPER:
5145                 upper_dev = info->upper_dev;
5146                 if (netif_is_bridge_master(upper_dev)) {
5147                         if (info->linking)
5148                                 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
5149                                                                 vlan_dev,
5150                                                                 upper_dev,
5151                                                                 extack);
5152                         else
5153                                 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
5154                                                            vlan_dev,
5155                                                            upper_dev);
5156                 } else if (netif_is_macvlan(upper_dev)) {
5157                         if (!info->linking)
5158                                 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
5159                 } else {
5160                         err = -EINVAL;
5161                         WARN_ON(1);
5162                 }
5163                 break;
5164         }
5165
5166         return err;
5167 }
5168
5169 static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
5170                                                   struct net_device *lag_dev,
5171                                                   unsigned long event,
5172                                                   void *ptr, u16 vid)
5173 {
5174         struct net_device *dev;
5175         struct list_head *iter;
5176         int ret;
5177
5178         netdev_for_each_lower_dev(lag_dev, dev, iter) {
5179                 if (mlxsw_sp_port_dev_check(dev)) {
5180                         ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
5181                                                                  event, ptr,
5182                                                                  vid);
5183                         if (ret)
5184                                 return ret;
5185                 }
5186         }
5187
5188         return 0;
5189 }
5190
5191 static int mlxsw_sp_netdevice_bridge_vlan_event(struct net_device *vlan_dev,
5192                                                 struct net_device *br_dev,
5193                                                 unsigned long event, void *ptr,
5194                                                 u16 vid)
5195 {
5196         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(vlan_dev);
5197         struct netdev_notifier_changeupper_info *info = ptr;
5198         struct netlink_ext_ack *extack;
5199         struct net_device *upper_dev;
5200
5201         if (!mlxsw_sp)
5202                 return 0;
5203
5204         extack = netdev_notifier_info_to_extack(&info->info);
5205
5206         switch (event) {
5207         case NETDEV_PRECHANGEUPPER:
5208                 upper_dev = info->upper_dev;
5209                 if (!netif_is_macvlan(upper_dev)) {
5210                         NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
5211                         return -EOPNOTSUPP;
5212                 }
5213                 if (!info->linking)
5214                         break;
5215                 if (netif_is_macvlan(upper_dev) &&
5216                     !mlxsw_sp_rif_find_by_dev(mlxsw_sp, vlan_dev)) {
5217                         NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
5218                         return -EOPNOTSUPP;
5219                 }
5220                 break;
5221         case NETDEV_CHANGEUPPER:
5222                 upper_dev = info->upper_dev;
5223                 if (info->linking)
5224                         break;
5225                 if (netif_is_macvlan(upper_dev))
5226                         mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
5227                 break;
5228         }
5229
5230         return 0;
5231 }
5232
5233 static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
5234                                          unsigned long event, void *ptr)
5235 {
5236         struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
5237         u16 vid = vlan_dev_vlan_id(vlan_dev);
5238
5239         if (mlxsw_sp_port_dev_check(real_dev))
5240                 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
5241                                                           event, ptr, vid);
5242         else if (netif_is_lag_master(real_dev))
5243                 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
5244                                                               real_dev, event,
5245                                                               ptr, vid);
5246         else if (netif_is_bridge_master(real_dev))
5247                 return mlxsw_sp_netdevice_bridge_vlan_event(vlan_dev, real_dev,
5248                                                             event, ptr, vid);
5249
5250         return 0;
5251 }
5252
5253 static int mlxsw_sp_netdevice_bridge_event(struct net_device *br_dev,
5254                                            unsigned long event, void *ptr)
5255 {
5256         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(br_dev);
5257         struct netdev_notifier_changeupper_info *info = ptr;
5258         struct netlink_ext_ack *extack;
5259         struct net_device *upper_dev;
5260
5261         if (!mlxsw_sp)
5262                 return 0;
5263
5264         extack = netdev_notifier_info_to_extack(&info->info);
5265
5266         switch (event) {
5267         case NETDEV_PRECHANGEUPPER:
5268                 upper_dev = info->upper_dev;
5269                 if (!is_vlan_dev(upper_dev) && !netif_is_macvlan(upper_dev)) {
5270                         NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
5271                         return -EOPNOTSUPP;
5272                 }
5273                 if (!info->linking)
5274                         break;
5275                 if (netif_is_macvlan(upper_dev) &&
5276                     !mlxsw_sp_rif_find_by_dev(mlxsw_sp, br_dev)) {
5277                         NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
5278                         return -EOPNOTSUPP;
5279                 }
5280                 break;
5281         case NETDEV_CHANGEUPPER:
5282                 upper_dev = info->upper_dev;
5283                 if (info->linking)
5284                         break;
5285                 if (is_vlan_dev(upper_dev))
5286                         mlxsw_sp_rif_destroy_by_dev(mlxsw_sp, upper_dev);
5287                 if (netif_is_macvlan(upper_dev))
5288                         mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
5289                 break;
5290         }
5291
5292         return 0;
5293 }
5294
5295 static int mlxsw_sp_netdevice_macvlan_event(struct net_device *macvlan_dev,
5296                                             unsigned long event, void *ptr)
5297 {
5298         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(macvlan_dev);
5299         struct netdev_notifier_changeupper_info *info = ptr;
5300         struct netlink_ext_ack *extack;
5301
5302         if (!mlxsw_sp || event != NETDEV_PRECHANGEUPPER)
5303                 return 0;
5304
5305         extack = netdev_notifier_info_to_extack(&info->info);
5306
5307         /* VRF enslavement is handled in mlxsw_sp_netdevice_vrf_event() */
5308         NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
5309
5310         return -EOPNOTSUPP;
5311 }
5312
5313 static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
5314 {
5315         struct netdev_notifier_changeupper_info *info = ptr;
5316
5317         if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
5318                 return false;
5319         return netif_is_l3_master(info->upper_dev);
5320 }
5321
5322 static int mlxsw_sp_netdevice_vxlan_event(struct mlxsw_sp *mlxsw_sp,
5323                                           struct net_device *dev,
5324                                           unsigned long event, void *ptr)
5325 {
5326         struct netdev_notifier_changeupper_info *cu_info;
5327         struct netdev_notifier_info *info = ptr;
5328         struct netlink_ext_ack *extack;
5329         struct net_device *upper_dev;
5330
5331         extack = netdev_notifier_info_to_extack(info);
5332
5333         switch (event) {
5334         case NETDEV_CHANGEUPPER:
5335                 cu_info = container_of(info,
5336                                        struct netdev_notifier_changeupper_info,
5337                                        info);
5338                 upper_dev = cu_info->upper_dev;
5339                 if (!netif_is_bridge_master(upper_dev))
5340                         return 0;
5341                 if (!mlxsw_sp_lower_get(upper_dev))
5342                         return 0;
5343                 if (!mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
5344                         return -EOPNOTSUPP;
5345                 if (cu_info->linking) {
5346                         if (!netif_running(dev))
5347                                 return 0;
5348                         /* When the bridge is VLAN-aware, the VNI of the VxLAN
5349                          * device needs to be mapped to a VLAN, but at this
5350                          * point no VLANs are configured on the VxLAN device
5351                          */
5352                         if (br_vlan_enabled(upper_dev))
5353                                 return 0;
5354                         return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev,
5355                                                           dev, 0, extack);
5356                 } else {
5357                         /* VLANs were already flushed, which triggered the
5358                          * necessary cleanup
5359                          */
5360                         if (br_vlan_enabled(upper_dev))
5361                                 return 0;
5362                         mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, dev);
5363                 }
5364                 break;
5365         case NETDEV_PRE_UP:
5366                 upper_dev = netdev_master_upper_dev_get(dev);
5367                 if (!upper_dev)
5368                         return 0;
5369                 if (!netif_is_bridge_master(upper_dev))
5370                         return 0;
5371                 if (!mlxsw_sp_lower_get(upper_dev))
5372                         return 0;
5373                 return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev, dev, 0,
5374                                                   extack);
5375         case NETDEV_DOWN:
5376                 upper_dev = netdev_master_upper_dev_get(dev);
5377                 if (!upper_dev)
5378                         return 0;
5379                 if (!netif_is_bridge_master(upper_dev))
5380                         return 0;
5381                 if (!mlxsw_sp_lower_get(upper_dev))
5382                         return 0;
5383                 mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, dev);
5384                 break;
5385         }
5386
5387         return 0;
5388 }
5389
5390 static int mlxsw_sp_netdevice_event(struct notifier_block *nb,
5391                                     unsigned long event, void *ptr)
5392 {
5393         struct net_device *dev = netdev_notifier_info_to_dev(ptr);
5394         struct mlxsw_sp_span_entry *span_entry;
5395         struct mlxsw_sp *mlxsw_sp;
5396         int err = 0;
5397
5398         mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb);
5399         if (event == NETDEV_UNREGISTER) {
5400                 span_entry = mlxsw_sp_span_entry_find_by_port(mlxsw_sp, dev);
5401                 if (span_entry)
5402                         mlxsw_sp_span_entry_invalidate(mlxsw_sp, span_entry);
5403         }
5404         mlxsw_sp_span_respin(mlxsw_sp);
5405
5406         if (netif_is_vxlan(dev))
5407                 err = mlxsw_sp_netdevice_vxlan_event(mlxsw_sp, dev, event, ptr);
5408         if (mlxsw_sp_netdev_is_ipip_ol(mlxsw_sp, dev))
5409                 err = mlxsw_sp_netdevice_ipip_ol_event(mlxsw_sp, dev,
5410                                                        event, ptr);
5411         else if (mlxsw_sp_netdev_is_ipip_ul(mlxsw_sp, dev))
5412                 err = mlxsw_sp_netdevice_ipip_ul_event(mlxsw_sp, dev,
5413                                                        event, ptr);
5414         else if (event == NETDEV_PRE_CHANGEADDR ||
5415                  event == NETDEV_CHANGEADDR ||
5416                  event == NETDEV_CHANGEMTU)
5417                 err = mlxsw_sp_netdevice_router_port_event(dev, event, ptr);
5418         else if (mlxsw_sp_is_vrf_event(event, ptr))
5419                 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
5420         else if (mlxsw_sp_port_dev_check(dev))
5421                 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr);
5422         else if (netif_is_lag_master(dev))
5423                 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
5424         else if (is_vlan_dev(dev))
5425                 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
5426         else if (netif_is_bridge_master(dev))
5427                 err = mlxsw_sp_netdevice_bridge_event(dev, event, ptr);
5428         else if (netif_is_macvlan(dev))
5429                 err = mlxsw_sp_netdevice_macvlan_event(dev, event, ptr);
5430
5431         return notifier_from_errno(err);
5432 }
5433
5434 static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = {
5435         .notifier_call = mlxsw_sp_inetaddr_valid_event,
5436 };
5437
5438 static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = {
5439         .notifier_call = mlxsw_sp_inet6addr_valid_event,
5440 };
5441
5442 static const struct pci_device_id mlxsw_sp1_pci_id_table[] = {
5443         {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
5444         {0, },
5445 };
5446
5447 static struct pci_driver mlxsw_sp1_pci_driver = {
5448         .name = mlxsw_sp1_driver_name,
5449         .id_table = mlxsw_sp1_pci_id_table,
5450 };
5451
5452 static const struct pci_device_id mlxsw_sp2_pci_id_table[] = {
5453         {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM2), 0},
5454         {0, },
5455 };
5456
5457 static struct pci_driver mlxsw_sp2_pci_driver = {
5458         .name = mlxsw_sp2_driver_name,
5459         .id_table = mlxsw_sp2_pci_id_table,
5460 };
5461
5462 static int __init mlxsw_sp_module_init(void)
5463 {
5464         int err;
5465
5466         register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
5467         register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
5468
5469         err = mlxsw_core_driver_register(&mlxsw_sp1_driver);
5470         if (err)
5471                 goto err_sp1_core_driver_register;
5472
5473         err = mlxsw_core_driver_register(&mlxsw_sp2_driver);
5474         if (err)
5475                 goto err_sp2_core_driver_register;
5476
5477         err = mlxsw_pci_driver_register(&mlxsw_sp1_pci_driver);
5478         if (err)
5479                 goto err_sp1_pci_driver_register;
5480
5481         err = mlxsw_pci_driver_register(&mlxsw_sp2_pci_driver);
5482         if (err)
5483                 goto err_sp2_pci_driver_register;
5484
5485         return 0;
5486
5487 err_sp2_pci_driver_register:
5488         mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver);
5489 err_sp1_pci_driver_register:
5490         mlxsw_core_driver_unregister(&mlxsw_sp2_driver);
5491 err_sp2_core_driver_register:
5492         mlxsw_core_driver_unregister(&mlxsw_sp1_driver);
5493 err_sp1_core_driver_register:
5494         unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
5495         unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
5496         return err;
5497 }
5498
5499 static void __exit mlxsw_sp_module_exit(void)
5500 {
5501         mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver);
5502         mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver);
5503         mlxsw_core_driver_unregister(&mlxsw_sp2_driver);
5504         mlxsw_core_driver_unregister(&mlxsw_sp1_driver);
5505         unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
5506         unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
5507 }
5508
5509 module_init(mlxsw_sp_module_init);
5510 module_exit(mlxsw_sp_module_exit);
5511
5512 MODULE_LICENSE("Dual BSD/GPL");
5513 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
5514 MODULE_DESCRIPTION("Mellanox Spectrum driver");
5515 MODULE_DEVICE_TABLE(pci, mlxsw_sp1_pci_id_table);
5516 MODULE_DEVICE_TABLE(pci, mlxsw_sp2_pci_id_table);
5517 MODULE_FIRMWARE(MLXSW_SP1_FW_FILENAME);