1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/device.h>
7 #include <linux/export.h>
9 #include <linux/if_link.h>
10 #include <linux/netdevice.h>
11 #include <linux/completion.h>
12 #include <linux/skbuff.h>
13 #include <linux/etherdevice.h>
14 #include <linux/types.h>
15 #include <linux/string.h>
16 #include <linux/gfp.h>
17 #include <linux/random.h>
18 #include <linux/jiffies.h>
19 #include <linux/mutex.h>
20 #include <linux/rcupdate.h>
21 #include <linux/slab.h>
22 #include <linux/workqueue.h>
23 #include <asm/byteorder.h>
24 #include <net/devlink.h>
25 #include <trace/events/devlink.h>
34 #include "resources.h"
36 static LIST_HEAD(mlxsw_core_driver_list);
37 static DEFINE_SPINLOCK(mlxsw_core_driver_list_lock);
39 static const char mlxsw_core_driver_name[] = "mlxsw_core";
41 static struct workqueue_struct *mlxsw_wq;
42 static struct workqueue_struct *mlxsw_owq;
44 struct mlxsw_core_port {
45 struct devlink_port devlink_port;
46 void *port_driver_priv;
50 void *mlxsw_core_port_driver_priv(struct mlxsw_core_port *mlxsw_core_port)
52 return mlxsw_core_port->port_driver_priv;
54 EXPORT_SYMBOL(mlxsw_core_port_driver_priv);
56 static bool mlxsw_core_port_check(struct mlxsw_core_port *mlxsw_core_port)
58 return mlxsw_core_port->port_driver_priv != NULL;
62 struct mlxsw_driver *driver;
63 const struct mlxsw_bus *bus;
65 const struct mlxsw_bus_info *bus_info;
66 struct workqueue_struct *emad_wq;
67 struct list_head rx_listener_list;
68 struct list_head event_listener_list;
71 struct list_head trans_list;
72 spinlock_t trans_list_lock; /* protects trans_list writes */
76 u8 *mapping; /* lag_id+port_index to local_port mapping */
79 struct mlxsw_hwmon *hwmon;
80 struct mlxsw_thermal *thermal;
81 struct mlxsw_core_port *ports;
82 unsigned int max_ports;
84 unsigned long driver_priv[0];
85 /* driver_priv has to be always the last item */
88 #define MLXSW_PORT_MAX_PORTS_DEFAULT 0x40
90 static int mlxsw_ports_init(struct mlxsw_core *mlxsw_core)
92 /* Switch ports are numbered from 1 to queried value */
93 if (MLXSW_CORE_RES_VALID(mlxsw_core, MAX_SYSTEM_PORT))
94 mlxsw_core->max_ports = MLXSW_CORE_RES_GET(mlxsw_core,
97 mlxsw_core->max_ports = MLXSW_PORT_MAX_PORTS_DEFAULT + 1;
99 mlxsw_core->ports = kcalloc(mlxsw_core->max_ports,
100 sizeof(struct mlxsw_core_port), GFP_KERNEL);
101 if (!mlxsw_core->ports)
107 static void mlxsw_ports_fini(struct mlxsw_core *mlxsw_core)
109 kfree(mlxsw_core->ports);
112 unsigned int mlxsw_core_max_ports(const struct mlxsw_core *mlxsw_core)
114 return mlxsw_core->max_ports;
116 EXPORT_SYMBOL(mlxsw_core_max_ports);
118 void *mlxsw_core_driver_priv(struct mlxsw_core *mlxsw_core)
120 return mlxsw_core->driver_priv;
122 EXPORT_SYMBOL(mlxsw_core_driver_priv);
124 struct mlxsw_rx_listener_item {
125 struct list_head list;
126 struct mlxsw_rx_listener rxl;
130 struct mlxsw_event_listener_item {
131 struct list_head list;
132 struct mlxsw_event_listener el;
141 * Destination MAC in EMAD's Ethernet header.
142 * Must be set to 01:02:c9:00:00:01
144 MLXSW_ITEM_BUF(emad, eth_hdr, dmac, 0x00, 6);
147 * Source MAC in EMAD's Ethernet header.
148 * Must be set to 00:02:c9:01:02:03
150 MLXSW_ITEM_BUF(emad, eth_hdr, smac, 0x06, 6);
152 /* emad_eth_hdr_ethertype
153 * Ethertype in EMAD's Ethernet header.
154 * Must be set to 0x8932
156 MLXSW_ITEM32(emad, eth_hdr, ethertype, 0x0C, 16, 16);
158 /* emad_eth_hdr_mlx_proto
160 * Must be set to 0x0.
162 MLXSW_ITEM32(emad, eth_hdr, mlx_proto, 0x0C, 8, 8);
165 * Mellanox protocol version.
166 * Must be set to 0x0.
168 MLXSW_ITEM32(emad, eth_hdr, ver, 0x0C, 4, 4);
172 * Must be set to 0x1 (operation TLV).
174 MLXSW_ITEM32(emad, op_tlv, type, 0x00, 27, 5);
177 * Length of the operation TLV in u32.
178 * Must be set to 0x4.
180 MLXSW_ITEM32(emad, op_tlv, len, 0x00, 16, 11);
183 * Direct route bit. Setting to 1 indicates the EMAD is a direct route
184 * EMAD. DR TLV must follow.
186 * Note: Currently not supported and must not be set.
188 MLXSW_ITEM32(emad, op_tlv, dr, 0x00, 15, 1);
190 /* emad_op_tlv_status
191 * Returned status in case of EMAD response. Must be set to 0 in case
194 * 0x1 - device is busy. Requester should retry
195 * 0x2 - Mellanox protocol version not supported
197 * 0x4 - register not supported
198 * 0x5 - operation class not supported
199 * 0x6 - EMAD method not supported
200 * 0x7 - bad parameter (e.g. port out of range)
201 * 0x8 - resource not available
202 * 0x9 - message receipt acknowledgment. Requester should retry
203 * 0x70 - internal error
205 MLXSW_ITEM32(emad, op_tlv, status, 0x00, 8, 7);
207 /* emad_op_tlv_register_id
208 * Register ID of register within register TLV.
210 MLXSW_ITEM32(emad, op_tlv, register_id, 0x04, 16, 16);
213 * Response bit. Setting to 1 indicates Response, otherwise request.
215 MLXSW_ITEM32(emad, op_tlv, r, 0x04, 15, 1);
217 /* emad_op_tlv_method
221 * 0x3 - send (currently not supported)
224 MLXSW_ITEM32(emad, op_tlv, method, 0x04, 8, 7);
227 * EMAD operation class. Must be set to 0x1 (REG_ACCESS).
229 MLXSW_ITEM32(emad, op_tlv, class, 0x04, 0, 8);
232 * EMAD transaction ID. Used for pairing request and response EMADs.
234 MLXSW_ITEM64(emad, op_tlv, tid, 0x08, 0, 64);
238 * Must be set to 0x3 (register TLV).
240 MLXSW_ITEM32(emad, reg_tlv, type, 0x00, 27, 5);
243 * Length of the operation TLV in u32.
245 MLXSW_ITEM32(emad, reg_tlv, len, 0x00, 16, 11);
249 * Must be set to 0x0 (end TLV).
251 MLXSW_ITEM32(emad, end_tlv, type, 0x00, 27, 5);
254 * Length of the end TLV in u32.
257 MLXSW_ITEM32(emad, end_tlv, len, 0x00, 16, 11);
259 enum mlxsw_core_reg_access_type {
260 MLXSW_CORE_REG_ACCESS_TYPE_QUERY,
261 MLXSW_CORE_REG_ACCESS_TYPE_WRITE,
264 static inline const char *
265 mlxsw_core_reg_access_type_str(enum mlxsw_core_reg_access_type type)
268 case MLXSW_CORE_REG_ACCESS_TYPE_QUERY:
270 case MLXSW_CORE_REG_ACCESS_TYPE_WRITE:
276 static void mlxsw_emad_pack_end_tlv(char *end_tlv)
278 mlxsw_emad_end_tlv_type_set(end_tlv, MLXSW_EMAD_TLV_TYPE_END);
279 mlxsw_emad_end_tlv_len_set(end_tlv, MLXSW_EMAD_END_TLV_LEN);
282 static void mlxsw_emad_pack_reg_tlv(char *reg_tlv,
283 const struct mlxsw_reg_info *reg,
286 mlxsw_emad_reg_tlv_type_set(reg_tlv, MLXSW_EMAD_TLV_TYPE_REG);
287 mlxsw_emad_reg_tlv_len_set(reg_tlv, reg->len / sizeof(u32) + 1);
288 memcpy(reg_tlv + sizeof(u32), payload, reg->len);
291 static void mlxsw_emad_pack_op_tlv(char *op_tlv,
292 const struct mlxsw_reg_info *reg,
293 enum mlxsw_core_reg_access_type type,
296 mlxsw_emad_op_tlv_type_set(op_tlv, MLXSW_EMAD_TLV_TYPE_OP);
297 mlxsw_emad_op_tlv_len_set(op_tlv, MLXSW_EMAD_OP_TLV_LEN);
298 mlxsw_emad_op_tlv_dr_set(op_tlv, 0);
299 mlxsw_emad_op_tlv_status_set(op_tlv, 0);
300 mlxsw_emad_op_tlv_register_id_set(op_tlv, reg->id);
301 mlxsw_emad_op_tlv_r_set(op_tlv, MLXSW_EMAD_OP_TLV_REQUEST);
302 if (type == MLXSW_CORE_REG_ACCESS_TYPE_QUERY)
303 mlxsw_emad_op_tlv_method_set(op_tlv,
304 MLXSW_EMAD_OP_TLV_METHOD_QUERY);
306 mlxsw_emad_op_tlv_method_set(op_tlv,
307 MLXSW_EMAD_OP_TLV_METHOD_WRITE);
308 mlxsw_emad_op_tlv_class_set(op_tlv,
309 MLXSW_EMAD_OP_TLV_CLASS_REG_ACCESS);
310 mlxsw_emad_op_tlv_tid_set(op_tlv, tid);
313 static int mlxsw_emad_construct_eth_hdr(struct sk_buff *skb)
315 char *eth_hdr = skb_push(skb, MLXSW_EMAD_ETH_HDR_LEN);
317 mlxsw_emad_eth_hdr_dmac_memcpy_to(eth_hdr, MLXSW_EMAD_EH_DMAC);
318 mlxsw_emad_eth_hdr_smac_memcpy_to(eth_hdr, MLXSW_EMAD_EH_SMAC);
319 mlxsw_emad_eth_hdr_ethertype_set(eth_hdr, MLXSW_EMAD_EH_ETHERTYPE);
320 mlxsw_emad_eth_hdr_mlx_proto_set(eth_hdr, MLXSW_EMAD_EH_MLX_PROTO);
321 mlxsw_emad_eth_hdr_ver_set(eth_hdr, MLXSW_EMAD_EH_PROTO_VERSION);
323 skb_reset_mac_header(skb);
328 static void mlxsw_emad_construct(struct sk_buff *skb,
329 const struct mlxsw_reg_info *reg,
331 enum mlxsw_core_reg_access_type type,
336 buf = skb_push(skb, MLXSW_EMAD_END_TLV_LEN * sizeof(u32));
337 mlxsw_emad_pack_end_tlv(buf);
339 buf = skb_push(skb, reg->len + sizeof(u32));
340 mlxsw_emad_pack_reg_tlv(buf, reg, payload);
342 buf = skb_push(skb, MLXSW_EMAD_OP_TLV_LEN * sizeof(u32));
343 mlxsw_emad_pack_op_tlv(buf, reg, type, tid);
345 mlxsw_emad_construct_eth_hdr(skb);
348 static char *mlxsw_emad_op_tlv(const struct sk_buff *skb)
350 return ((char *) (skb->data + MLXSW_EMAD_ETH_HDR_LEN));
353 static char *mlxsw_emad_reg_tlv(const struct sk_buff *skb)
355 return ((char *) (skb->data + MLXSW_EMAD_ETH_HDR_LEN +
356 MLXSW_EMAD_OP_TLV_LEN * sizeof(u32)));
359 static char *mlxsw_emad_reg_payload(const char *op_tlv)
361 return ((char *) (op_tlv + (MLXSW_EMAD_OP_TLV_LEN + 1) * sizeof(u32)));
364 static u64 mlxsw_emad_get_tid(const struct sk_buff *skb)
368 op_tlv = mlxsw_emad_op_tlv(skb);
369 return mlxsw_emad_op_tlv_tid_get(op_tlv);
372 static bool mlxsw_emad_is_resp(const struct sk_buff *skb)
376 op_tlv = mlxsw_emad_op_tlv(skb);
377 return (mlxsw_emad_op_tlv_r_get(op_tlv) == MLXSW_EMAD_OP_TLV_RESPONSE);
380 static int mlxsw_emad_process_status(char *op_tlv,
381 enum mlxsw_emad_op_tlv_status *p_status)
383 *p_status = mlxsw_emad_op_tlv_status_get(op_tlv);
386 case MLXSW_EMAD_OP_TLV_STATUS_SUCCESS:
388 case MLXSW_EMAD_OP_TLV_STATUS_BUSY:
389 case MLXSW_EMAD_OP_TLV_STATUS_MESSAGE_RECEIPT_ACK:
391 case MLXSW_EMAD_OP_TLV_STATUS_VERSION_NOT_SUPPORTED:
392 case MLXSW_EMAD_OP_TLV_STATUS_UNKNOWN_TLV:
393 case MLXSW_EMAD_OP_TLV_STATUS_REGISTER_NOT_SUPPORTED:
394 case MLXSW_EMAD_OP_TLV_STATUS_CLASS_NOT_SUPPORTED:
395 case MLXSW_EMAD_OP_TLV_STATUS_METHOD_NOT_SUPPORTED:
396 case MLXSW_EMAD_OP_TLV_STATUS_BAD_PARAMETER:
397 case MLXSW_EMAD_OP_TLV_STATUS_RESOURCE_NOT_AVAILABLE:
398 case MLXSW_EMAD_OP_TLV_STATUS_INTERNAL_ERROR:
405 mlxsw_emad_process_status_skb(struct sk_buff *skb,
406 enum mlxsw_emad_op_tlv_status *p_status)
408 return mlxsw_emad_process_status(mlxsw_emad_op_tlv(skb), p_status);
411 struct mlxsw_reg_trans {
412 struct list_head list;
413 struct list_head bulk_list;
414 struct mlxsw_core *core;
415 struct sk_buff *tx_skb;
416 struct mlxsw_tx_info tx_info;
417 struct delayed_work timeout_dw;
418 unsigned int retries;
420 struct completion completion;
422 mlxsw_reg_trans_cb_t *cb;
423 unsigned long cb_priv;
424 const struct mlxsw_reg_info *reg;
425 enum mlxsw_core_reg_access_type type;
427 enum mlxsw_emad_op_tlv_status emad_status;
431 #define MLXSW_EMAD_TIMEOUT_MS 200
433 static void mlxsw_emad_trans_timeout_schedule(struct mlxsw_reg_trans *trans)
435 unsigned long timeout = msecs_to_jiffies(MLXSW_EMAD_TIMEOUT_MS);
437 queue_delayed_work(trans->core->emad_wq, &trans->timeout_dw, timeout);
440 static int mlxsw_emad_transmit(struct mlxsw_core *mlxsw_core,
441 struct mlxsw_reg_trans *trans)
446 skb = skb_copy(trans->tx_skb, GFP_KERNEL);
450 trace_devlink_hwmsg(priv_to_devlink(mlxsw_core), false, 0,
451 skb->data + mlxsw_core->driver->txhdr_len,
452 skb->len - mlxsw_core->driver->txhdr_len);
454 atomic_set(&trans->active, 1);
455 err = mlxsw_core_skb_transmit(mlxsw_core, skb, &trans->tx_info);
460 mlxsw_emad_trans_timeout_schedule(trans);
464 static void mlxsw_emad_trans_finish(struct mlxsw_reg_trans *trans, int err)
466 struct mlxsw_core *mlxsw_core = trans->core;
468 dev_kfree_skb(trans->tx_skb);
469 spin_lock_bh(&mlxsw_core->emad.trans_list_lock);
470 list_del_rcu(&trans->list);
471 spin_unlock_bh(&mlxsw_core->emad.trans_list_lock);
473 complete(&trans->completion);
476 static void mlxsw_emad_transmit_retry(struct mlxsw_core *mlxsw_core,
477 struct mlxsw_reg_trans *trans)
481 if (trans->retries < MLXSW_EMAD_MAX_RETRY) {
483 err = mlxsw_emad_transmit(trans->core, trans);
489 mlxsw_emad_trans_finish(trans, err);
492 static void mlxsw_emad_trans_timeout_work(struct work_struct *work)
494 struct mlxsw_reg_trans *trans = container_of(work,
495 struct mlxsw_reg_trans,
498 if (!atomic_dec_and_test(&trans->active))
501 mlxsw_emad_transmit_retry(trans->core, trans);
504 static void mlxsw_emad_process_response(struct mlxsw_core *mlxsw_core,
505 struct mlxsw_reg_trans *trans,
510 if (!atomic_dec_and_test(&trans->active))
513 err = mlxsw_emad_process_status_skb(skb, &trans->emad_status);
514 if (err == -EAGAIN) {
515 mlxsw_emad_transmit_retry(mlxsw_core, trans);
518 char *op_tlv = mlxsw_emad_op_tlv(skb);
521 trans->cb(mlxsw_core,
522 mlxsw_emad_reg_payload(op_tlv),
523 trans->reg->len, trans->cb_priv);
525 mlxsw_emad_trans_finish(trans, err);
529 /* called with rcu read lock held */
530 static void mlxsw_emad_rx_listener_func(struct sk_buff *skb, u8 local_port,
533 struct mlxsw_core *mlxsw_core = priv;
534 struct mlxsw_reg_trans *trans;
536 trace_devlink_hwmsg(priv_to_devlink(mlxsw_core), true, 0,
537 skb->data, skb->len);
539 if (!mlxsw_emad_is_resp(skb))
542 list_for_each_entry_rcu(trans, &mlxsw_core->emad.trans_list, list) {
543 if (mlxsw_emad_get_tid(skb) == trans->tid) {
544 mlxsw_emad_process_response(mlxsw_core, trans, skb);
553 static const struct mlxsw_listener mlxsw_emad_rx_listener =
554 MLXSW_RXL(mlxsw_emad_rx_listener_func, ETHEMAD, TRAP_TO_CPU, false,
557 static int mlxsw_emad_init(struct mlxsw_core *mlxsw_core)
559 struct workqueue_struct *emad_wq;
563 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_TXRX))
566 emad_wq = alloc_workqueue("mlxsw_core_emad", WQ_MEM_RECLAIM, 0);
569 mlxsw_core->emad_wq = emad_wq;
571 /* Set the upper 32 bits of the transaction ID field to a random
572 * number. This allows us to discard EMADs addressed to other
575 get_random_bytes(&tid, 4);
577 atomic64_set(&mlxsw_core->emad.tid, tid);
579 INIT_LIST_HEAD(&mlxsw_core->emad.trans_list);
580 spin_lock_init(&mlxsw_core->emad.trans_list_lock);
582 err = mlxsw_core_trap_register(mlxsw_core, &mlxsw_emad_rx_listener,
587 err = mlxsw_core->driver->basic_trap_groups_set(mlxsw_core);
589 goto err_emad_trap_set;
590 mlxsw_core->emad.use_emad = true;
595 mlxsw_core_trap_unregister(mlxsw_core, &mlxsw_emad_rx_listener,
597 destroy_workqueue(mlxsw_core->emad_wq);
601 static void mlxsw_emad_fini(struct mlxsw_core *mlxsw_core)
604 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_TXRX))
607 mlxsw_core->emad.use_emad = false;
608 mlxsw_core_trap_unregister(mlxsw_core, &mlxsw_emad_rx_listener,
610 destroy_workqueue(mlxsw_core->emad_wq);
613 static struct sk_buff *mlxsw_emad_alloc(const struct mlxsw_core *mlxsw_core,
619 emad_len = (reg_len + sizeof(u32) + MLXSW_EMAD_ETH_HDR_LEN +
620 (MLXSW_EMAD_OP_TLV_LEN + MLXSW_EMAD_END_TLV_LEN) *
621 sizeof(u32) + mlxsw_core->driver->txhdr_len);
622 if (emad_len > MLXSW_EMAD_MAX_FRAME_LEN)
625 skb = netdev_alloc_skb(NULL, emad_len);
628 memset(skb->data, 0, emad_len);
629 skb_reserve(skb, emad_len);
634 static int mlxsw_emad_reg_access(struct mlxsw_core *mlxsw_core,
635 const struct mlxsw_reg_info *reg,
637 enum mlxsw_core_reg_access_type type,
638 struct mlxsw_reg_trans *trans,
639 struct list_head *bulk_list,
640 mlxsw_reg_trans_cb_t *cb,
641 unsigned long cb_priv, u64 tid)
646 dev_dbg(mlxsw_core->bus_info->dev, "EMAD reg access (tid=%llx,reg_id=%x(%s),type=%s)\n",
647 tid, reg->id, mlxsw_reg_id_str(reg->id),
648 mlxsw_core_reg_access_type_str(type));
650 skb = mlxsw_emad_alloc(mlxsw_core, reg->len);
654 list_add_tail(&trans->bulk_list, bulk_list);
655 trans->core = mlxsw_core;
657 trans->tx_info.local_port = MLXSW_PORT_CPU_PORT;
658 trans->tx_info.is_emad = true;
659 INIT_DELAYED_WORK(&trans->timeout_dw, mlxsw_emad_trans_timeout_work);
661 init_completion(&trans->completion);
663 trans->cb_priv = cb_priv;
667 mlxsw_emad_construct(skb, reg, payload, type, trans->tid);
668 mlxsw_core->driver->txhdr_construct(skb, &trans->tx_info);
670 spin_lock_bh(&mlxsw_core->emad.trans_list_lock);
671 list_add_tail_rcu(&trans->list, &mlxsw_core->emad.trans_list);
672 spin_unlock_bh(&mlxsw_core->emad.trans_list_lock);
673 err = mlxsw_emad_transmit(mlxsw_core, trans);
679 spin_lock_bh(&mlxsw_core->emad.trans_list_lock);
680 list_del_rcu(&trans->list);
681 spin_unlock_bh(&mlxsw_core->emad.trans_list_lock);
682 list_del(&trans->bulk_list);
683 dev_kfree_skb(trans->tx_skb);
691 int mlxsw_core_driver_register(struct mlxsw_driver *mlxsw_driver)
693 spin_lock(&mlxsw_core_driver_list_lock);
694 list_add_tail(&mlxsw_driver->list, &mlxsw_core_driver_list);
695 spin_unlock(&mlxsw_core_driver_list_lock);
698 EXPORT_SYMBOL(mlxsw_core_driver_register);
700 void mlxsw_core_driver_unregister(struct mlxsw_driver *mlxsw_driver)
702 spin_lock(&mlxsw_core_driver_list_lock);
703 list_del(&mlxsw_driver->list);
704 spin_unlock(&mlxsw_core_driver_list_lock);
706 EXPORT_SYMBOL(mlxsw_core_driver_unregister);
708 static struct mlxsw_driver *__driver_find(const char *kind)
710 struct mlxsw_driver *mlxsw_driver;
712 list_for_each_entry(mlxsw_driver, &mlxsw_core_driver_list, list) {
713 if (strcmp(mlxsw_driver->kind, kind) == 0)
719 static struct mlxsw_driver *mlxsw_core_driver_get(const char *kind)
721 struct mlxsw_driver *mlxsw_driver;
723 spin_lock(&mlxsw_core_driver_list_lock);
724 mlxsw_driver = __driver_find(kind);
725 spin_unlock(&mlxsw_core_driver_list_lock);
729 static int mlxsw_devlink_port_split(struct devlink *devlink,
730 unsigned int port_index,
732 struct netlink_ext_ack *extack)
734 struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
736 if (port_index >= mlxsw_core->max_ports) {
737 NL_SET_ERR_MSG_MOD(extack, "Port index exceeds maximum number of ports");
740 if (!mlxsw_core->driver->port_split)
742 return mlxsw_core->driver->port_split(mlxsw_core, port_index, count,
746 static int mlxsw_devlink_port_unsplit(struct devlink *devlink,
747 unsigned int port_index,
748 struct netlink_ext_ack *extack)
750 struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
752 if (port_index >= mlxsw_core->max_ports) {
753 NL_SET_ERR_MSG_MOD(extack, "Port index exceeds maximum number of ports");
756 if (!mlxsw_core->driver->port_unsplit)
758 return mlxsw_core->driver->port_unsplit(mlxsw_core, port_index,
763 mlxsw_devlink_sb_pool_get(struct devlink *devlink,
764 unsigned int sb_index, u16 pool_index,
765 struct devlink_sb_pool_info *pool_info)
767 struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
768 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver;
770 if (!mlxsw_driver->sb_pool_get)
772 return mlxsw_driver->sb_pool_get(mlxsw_core, sb_index,
773 pool_index, pool_info);
777 mlxsw_devlink_sb_pool_set(struct devlink *devlink,
778 unsigned int sb_index, u16 pool_index, u32 size,
779 enum devlink_sb_threshold_type threshold_type)
781 struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
782 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver;
784 if (!mlxsw_driver->sb_pool_set)
786 return mlxsw_driver->sb_pool_set(mlxsw_core, sb_index,
787 pool_index, size, threshold_type);
790 static void *__dl_port(struct devlink_port *devlink_port)
792 return container_of(devlink_port, struct mlxsw_core_port, devlink_port);
795 static int mlxsw_devlink_port_type_set(struct devlink_port *devlink_port,
796 enum devlink_port_type port_type)
798 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink);
799 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver;
800 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port);
802 if (!mlxsw_driver->port_type_set)
805 return mlxsw_driver->port_type_set(mlxsw_core,
806 mlxsw_core_port->local_port,
810 static int mlxsw_devlink_sb_port_pool_get(struct devlink_port *devlink_port,
811 unsigned int sb_index, u16 pool_index,
814 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink);
815 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver;
816 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port);
818 if (!mlxsw_driver->sb_port_pool_get ||
819 !mlxsw_core_port_check(mlxsw_core_port))
821 return mlxsw_driver->sb_port_pool_get(mlxsw_core_port, sb_index,
822 pool_index, p_threshold);
825 static int mlxsw_devlink_sb_port_pool_set(struct devlink_port *devlink_port,
826 unsigned int sb_index, u16 pool_index,
829 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink);
830 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver;
831 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port);
833 if (!mlxsw_driver->sb_port_pool_set ||
834 !mlxsw_core_port_check(mlxsw_core_port))
836 return mlxsw_driver->sb_port_pool_set(mlxsw_core_port, sb_index,
837 pool_index, threshold);
841 mlxsw_devlink_sb_tc_pool_bind_get(struct devlink_port *devlink_port,
842 unsigned int sb_index, u16 tc_index,
843 enum devlink_sb_pool_type pool_type,
844 u16 *p_pool_index, u32 *p_threshold)
846 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink);
847 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver;
848 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port);
850 if (!mlxsw_driver->sb_tc_pool_bind_get ||
851 !mlxsw_core_port_check(mlxsw_core_port))
853 return mlxsw_driver->sb_tc_pool_bind_get(mlxsw_core_port, sb_index,
855 p_pool_index, p_threshold);
859 mlxsw_devlink_sb_tc_pool_bind_set(struct devlink_port *devlink_port,
860 unsigned int sb_index, u16 tc_index,
861 enum devlink_sb_pool_type pool_type,
862 u16 pool_index, u32 threshold)
864 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink);
865 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver;
866 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port);
868 if (!mlxsw_driver->sb_tc_pool_bind_set ||
869 !mlxsw_core_port_check(mlxsw_core_port))
871 return mlxsw_driver->sb_tc_pool_bind_set(mlxsw_core_port, sb_index,
873 pool_index, threshold);
876 static int mlxsw_devlink_sb_occ_snapshot(struct devlink *devlink,
877 unsigned int sb_index)
879 struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
880 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver;
882 if (!mlxsw_driver->sb_occ_snapshot)
884 return mlxsw_driver->sb_occ_snapshot(mlxsw_core, sb_index);
887 static int mlxsw_devlink_sb_occ_max_clear(struct devlink *devlink,
888 unsigned int sb_index)
890 struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
891 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver;
893 if (!mlxsw_driver->sb_occ_max_clear)
895 return mlxsw_driver->sb_occ_max_clear(mlxsw_core, sb_index);
899 mlxsw_devlink_sb_occ_port_pool_get(struct devlink_port *devlink_port,
900 unsigned int sb_index, u16 pool_index,
901 u32 *p_cur, u32 *p_max)
903 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink);
904 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver;
905 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port);
907 if (!mlxsw_driver->sb_occ_port_pool_get ||
908 !mlxsw_core_port_check(mlxsw_core_port))
910 return mlxsw_driver->sb_occ_port_pool_get(mlxsw_core_port, sb_index,
911 pool_index, p_cur, p_max);
915 mlxsw_devlink_sb_occ_tc_port_bind_get(struct devlink_port *devlink_port,
916 unsigned int sb_index, u16 tc_index,
917 enum devlink_sb_pool_type pool_type,
918 u32 *p_cur, u32 *p_max)
920 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink);
921 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver;
922 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port);
924 if (!mlxsw_driver->sb_occ_tc_port_bind_get ||
925 !mlxsw_core_port_check(mlxsw_core_port))
927 return mlxsw_driver->sb_occ_tc_port_bind_get(mlxsw_core_port,
929 pool_type, p_cur, p_max);
932 static int mlxsw_devlink_core_bus_device_reload(struct devlink *devlink,
933 struct netlink_ext_ack *extack)
935 struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
938 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_RESET))
941 mlxsw_core_bus_device_unregister(mlxsw_core, true);
942 err = mlxsw_core_bus_device_register(mlxsw_core->bus_info,
944 mlxsw_core->bus_priv, true,
947 mlxsw_core->reload_fail = true;
951 static const struct devlink_ops mlxsw_devlink_ops = {
952 .reload = mlxsw_devlink_core_bus_device_reload,
953 .port_type_set = mlxsw_devlink_port_type_set,
954 .port_split = mlxsw_devlink_port_split,
955 .port_unsplit = mlxsw_devlink_port_unsplit,
956 .sb_pool_get = mlxsw_devlink_sb_pool_get,
957 .sb_pool_set = mlxsw_devlink_sb_pool_set,
958 .sb_port_pool_get = mlxsw_devlink_sb_port_pool_get,
959 .sb_port_pool_set = mlxsw_devlink_sb_port_pool_set,
960 .sb_tc_pool_bind_get = mlxsw_devlink_sb_tc_pool_bind_get,
961 .sb_tc_pool_bind_set = mlxsw_devlink_sb_tc_pool_bind_set,
962 .sb_occ_snapshot = mlxsw_devlink_sb_occ_snapshot,
963 .sb_occ_max_clear = mlxsw_devlink_sb_occ_max_clear,
964 .sb_occ_port_pool_get = mlxsw_devlink_sb_occ_port_pool_get,
965 .sb_occ_tc_port_bind_get = mlxsw_devlink_sb_occ_tc_port_bind_get,
968 int mlxsw_core_bus_device_register(const struct mlxsw_bus_info *mlxsw_bus_info,
969 const struct mlxsw_bus *mlxsw_bus,
970 void *bus_priv, bool reload,
971 struct devlink *devlink)
973 const char *device_kind = mlxsw_bus_info->device_kind;
974 struct mlxsw_core *mlxsw_core;
975 struct mlxsw_driver *mlxsw_driver;
976 struct mlxsw_res *res;
980 mlxsw_driver = mlxsw_core_driver_get(device_kind);
985 alloc_size = sizeof(*mlxsw_core) + mlxsw_driver->priv_size;
986 devlink = devlink_alloc(&mlxsw_devlink_ops, alloc_size);
989 goto err_devlink_alloc;
993 mlxsw_core = devlink_priv(devlink);
994 INIT_LIST_HEAD(&mlxsw_core->rx_listener_list);
995 INIT_LIST_HEAD(&mlxsw_core->event_listener_list);
996 mlxsw_core->driver = mlxsw_driver;
997 mlxsw_core->bus = mlxsw_bus;
998 mlxsw_core->bus_priv = bus_priv;
999 mlxsw_core->bus_info = mlxsw_bus_info;
1001 res = mlxsw_driver->res_query_enabled ? &mlxsw_core->res : NULL;
1002 err = mlxsw_bus->init(bus_priv, mlxsw_core, mlxsw_driver->profile, res);
1006 if (mlxsw_driver->resources_register && !reload) {
1007 err = mlxsw_driver->resources_register(mlxsw_core);
1009 goto err_register_resources;
1012 err = mlxsw_ports_init(mlxsw_core);
1014 goto err_ports_init;
1016 if (MLXSW_CORE_RES_VALID(mlxsw_core, MAX_LAG) &&
1017 MLXSW_CORE_RES_VALID(mlxsw_core, MAX_LAG_MEMBERS)) {
1018 alloc_size = sizeof(u8) *
1019 MLXSW_CORE_RES_GET(mlxsw_core, MAX_LAG) *
1020 MLXSW_CORE_RES_GET(mlxsw_core, MAX_LAG_MEMBERS);
1021 mlxsw_core->lag.mapping = kzalloc(alloc_size, GFP_KERNEL);
1022 if (!mlxsw_core->lag.mapping) {
1024 goto err_alloc_lag_mapping;
1028 err = mlxsw_emad_init(mlxsw_core);
1033 err = devlink_register(devlink, mlxsw_bus_info->dev);
1035 goto err_devlink_register;
1038 err = mlxsw_hwmon_init(mlxsw_core, mlxsw_bus_info, &mlxsw_core->hwmon);
1040 goto err_hwmon_init;
1042 err = mlxsw_thermal_init(mlxsw_core, mlxsw_bus_info,
1043 &mlxsw_core->thermal);
1045 goto err_thermal_init;
1047 if (mlxsw_driver->init) {
1048 err = mlxsw_driver->init(mlxsw_core, mlxsw_bus_info);
1050 goto err_driver_init;
1056 mlxsw_thermal_fini(mlxsw_core->thermal);
1058 mlxsw_hwmon_fini(mlxsw_core->hwmon);
1061 devlink_unregister(devlink);
1062 err_devlink_register:
1063 mlxsw_emad_fini(mlxsw_core);
1065 kfree(mlxsw_core->lag.mapping);
1066 err_alloc_lag_mapping:
1067 mlxsw_ports_fini(mlxsw_core);
1070 devlink_resources_unregister(devlink, NULL);
1071 err_register_resources:
1072 mlxsw_bus->fini(bus_priv);
1075 devlink_free(devlink);
1079 EXPORT_SYMBOL(mlxsw_core_bus_device_register);
1081 void mlxsw_core_bus_device_unregister(struct mlxsw_core *mlxsw_core,
1084 struct devlink *devlink = priv_to_devlink(mlxsw_core);
1086 if (mlxsw_core->reload_fail)
1089 if (mlxsw_core->driver->fini)
1090 mlxsw_core->driver->fini(mlxsw_core);
1091 mlxsw_thermal_fini(mlxsw_core->thermal);
1092 mlxsw_hwmon_fini(mlxsw_core->hwmon);
1094 devlink_unregister(devlink);
1095 mlxsw_emad_fini(mlxsw_core);
1096 kfree(mlxsw_core->lag.mapping);
1097 mlxsw_ports_fini(mlxsw_core);
1099 devlink_resources_unregister(devlink, NULL);
1100 mlxsw_core->bus->fini(mlxsw_core->bus_priv);
1104 devlink_free(devlink);
1106 EXPORT_SYMBOL(mlxsw_core_bus_device_unregister);
1108 bool mlxsw_core_skb_transmit_busy(struct mlxsw_core *mlxsw_core,
1109 const struct mlxsw_tx_info *tx_info)
1111 return mlxsw_core->bus->skb_transmit_busy(mlxsw_core->bus_priv,
1114 EXPORT_SYMBOL(mlxsw_core_skb_transmit_busy);
1116 int mlxsw_core_skb_transmit(struct mlxsw_core *mlxsw_core, struct sk_buff *skb,
1117 const struct mlxsw_tx_info *tx_info)
1119 return mlxsw_core->bus->skb_transmit(mlxsw_core->bus_priv, skb,
1122 EXPORT_SYMBOL(mlxsw_core_skb_transmit);
1124 static bool __is_rx_listener_equal(const struct mlxsw_rx_listener *rxl_a,
1125 const struct mlxsw_rx_listener *rxl_b)
1127 return (rxl_a->func == rxl_b->func &&
1128 rxl_a->local_port == rxl_b->local_port &&
1129 rxl_a->trap_id == rxl_b->trap_id);
1132 static struct mlxsw_rx_listener_item *
1133 __find_rx_listener_item(struct mlxsw_core *mlxsw_core,
1134 const struct mlxsw_rx_listener *rxl,
1137 struct mlxsw_rx_listener_item *rxl_item;
1139 list_for_each_entry(rxl_item, &mlxsw_core->rx_listener_list, list) {
1140 if (__is_rx_listener_equal(&rxl_item->rxl, rxl) &&
1141 rxl_item->priv == priv)
1147 int mlxsw_core_rx_listener_register(struct mlxsw_core *mlxsw_core,
1148 const struct mlxsw_rx_listener *rxl,
1151 struct mlxsw_rx_listener_item *rxl_item;
1153 rxl_item = __find_rx_listener_item(mlxsw_core, rxl, priv);
1156 rxl_item = kmalloc(sizeof(*rxl_item), GFP_KERNEL);
1159 rxl_item->rxl = *rxl;
1160 rxl_item->priv = priv;
1162 list_add_rcu(&rxl_item->list, &mlxsw_core->rx_listener_list);
1165 EXPORT_SYMBOL(mlxsw_core_rx_listener_register);
1167 void mlxsw_core_rx_listener_unregister(struct mlxsw_core *mlxsw_core,
1168 const struct mlxsw_rx_listener *rxl,
1171 struct mlxsw_rx_listener_item *rxl_item;
1173 rxl_item = __find_rx_listener_item(mlxsw_core, rxl, priv);
1176 list_del_rcu(&rxl_item->list);
1180 EXPORT_SYMBOL(mlxsw_core_rx_listener_unregister);
1182 static void mlxsw_core_event_listener_func(struct sk_buff *skb, u8 local_port,
1185 struct mlxsw_event_listener_item *event_listener_item = priv;
1186 struct mlxsw_reg_info reg;
1188 char *op_tlv = mlxsw_emad_op_tlv(skb);
1189 char *reg_tlv = mlxsw_emad_reg_tlv(skb);
1191 reg.id = mlxsw_emad_op_tlv_register_id_get(op_tlv);
1192 reg.len = (mlxsw_emad_reg_tlv_len_get(reg_tlv) - 1) * sizeof(u32);
1193 payload = mlxsw_emad_reg_payload(op_tlv);
1194 event_listener_item->el.func(®, payload, event_listener_item->priv);
1198 static bool __is_event_listener_equal(const struct mlxsw_event_listener *el_a,
1199 const struct mlxsw_event_listener *el_b)
1201 return (el_a->func == el_b->func &&
1202 el_a->trap_id == el_b->trap_id);
1205 static struct mlxsw_event_listener_item *
1206 __find_event_listener_item(struct mlxsw_core *mlxsw_core,
1207 const struct mlxsw_event_listener *el,
1210 struct mlxsw_event_listener_item *el_item;
1212 list_for_each_entry(el_item, &mlxsw_core->event_listener_list, list) {
1213 if (__is_event_listener_equal(&el_item->el, el) &&
1214 el_item->priv == priv)
1220 int mlxsw_core_event_listener_register(struct mlxsw_core *mlxsw_core,
1221 const struct mlxsw_event_listener *el,
1225 struct mlxsw_event_listener_item *el_item;
1226 const struct mlxsw_rx_listener rxl = {
1227 .func = mlxsw_core_event_listener_func,
1228 .local_port = MLXSW_PORT_DONT_CARE,
1229 .trap_id = el->trap_id,
1232 el_item = __find_event_listener_item(mlxsw_core, el, priv);
1235 el_item = kmalloc(sizeof(*el_item), GFP_KERNEL);
1239 el_item->priv = priv;
1241 err = mlxsw_core_rx_listener_register(mlxsw_core, &rxl, el_item);
1243 goto err_rx_listener_register;
1245 /* No reason to save item if we did not manage to register an RX
1248 list_add_rcu(&el_item->list, &mlxsw_core->event_listener_list);
1252 err_rx_listener_register:
1256 EXPORT_SYMBOL(mlxsw_core_event_listener_register);
1258 void mlxsw_core_event_listener_unregister(struct mlxsw_core *mlxsw_core,
1259 const struct mlxsw_event_listener *el,
1262 struct mlxsw_event_listener_item *el_item;
1263 const struct mlxsw_rx_listener rxl = {
1264 .func = mlxsw_core_event_listener_func,
1265 .local_port = MLXSW_PORT_DONT_CARE,
1266 .trap_id = el->trap_id,
1269 el_item = __find_event_listener_item(mlxsw_core, el, priv);
1272 mlxsw_core_rx_listener_unregister(mlxsw_core, &rxl, el_item);
1273 list_del(&el_item->list);
1276 EXPORT_SYMBOL(mlxsw_core_event_listener_unregister);
1278 static int mlxsw_core_listener_register(struct mlxsw_core *mlxsw_core,
1279 const struct mlxsw_listener *listener,
1282 if (listener->is_event)
1283 return mlxsw_core_event_listener_register(mlxsw_core,
1284 &listener->u.event_listener,
1287 return mlxsw_core_rx_listener_register(mlxsw_core,
1288 &listener->u.rx_listener,
1292 static void mlxsw_core_listener_unregister(struct mlxsw_core *mlxsw_core,
1293 const struct mlxsw_listener *listener,
1296 if (listener->is_event)
1297 mlxsw_core_event_listener_unregister(mlxsw_core,
1298 &listener->u.event_listener,
1301 mlxsw_core_rx_listener_unregister(mlxsw_core,
1302 &listener->u.rx_listener,
1306 int mlxsw_core_trap_register(struct mlxsw_core *mlxsw_core,
1307 const struct mlxsw_listener *listener, void *priv)
1309 char hpkt_pl[MLXSW_REG_HPKT_LEN];
1312 err = mlxsw_core_listener_register(mlxsw_core, listener, priv);
1316 mlxsw_reg_hpkt_pack(hpkt_pl, listener->action, listener->trap_id,
1317 listener->trap_group, listener->is_ctrl);
1318 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(hpkt), hpkt_pl);
1325 mlxsw_core_listener_unregister(mlxsw_core, listener, priv);
1328 EXPORT_SYMBOL(mlxsw_core_trap_register);
1330 void mlxsw_core_trap_unregister(struct mlxsw_core *mlxsw_core,
1331 const struct mlxsw_listener *listener,
1334 char hpkt_pl[MLXSW_REG_HPKT_LEN];
1336 if (!listener->is_event) {
1337 mlxsw_reg_hpkt_pack(hpkt_pl, listener->unreg_action,
1338 listener->trap_id, listener->trap_group,
1340 mlxsw_reg_write(mlxsw_core, MLXSW_REG(hpkt), hpkt_pl);
1343 mlxsw_core_listener_unregister(mlxsw_core, listener, priv);
1345 EXPORT_SYMBOL(mlxsw_core_trap_unregister);
1347 static u64 mlxsw_core_tid_get(struct mlxsw_core *mlxsw_core)
1349 return atomic64_inc_return(&mlxsw_core->emad.tid);
1352 static int mlxsw_core_reg_access_emad(struct mlxsw_core *mlxsw_core,
1353 const struct mlxsw_reg_info *reg,
1355 enum mlxsw_core_reg_access_type type,
1356 struct list_head *bulk_list,
1357 mlxsw_reg_trans_cb_t *cb,
1358 unsigned long cb_priv)
1360 u64 tid = mlxsw_core_tid_get(mlxsw_core);
1361 struct mlxsw_reg_trans *trans;
1364 trans = kzalloc(sizeof(*trans), GFP_KERNEL);
1368 err = mlxsw_emad_reg_access(mlxsw_core, reg, payload, type, trans,
1369 bulk_list, cb, cb_priv, tid);
1377 int mlxsw_reg_trans_query(struct mlxsw_core *mlxsw_core,
1378 const struct mlxsw_reg_info *reg, char *payload,
1379 struct list_head *bulk_list,
1380 mlxsw_reg_trans_cb_t *cb, unsigned long cb_priv)
1382 return mlxsw_core_reg_access_emad(mlxsw_core, reg, payload,
1383 MLXSW_CORE_REG_ACCESS_TYPE_QUERY,
1384 bulk_list, cb, cb_priv);
1386 EXPORT_SYMBOL(mlxsw_reg_trans_query);
1388 int mlxsw_reg_trans_write(struct mlxsw_core *mlxsw_core,
1389 const struct mlxsw_reg_info *reg, char *payload,
1390 struct list_head *bulk_list,
1391 mlxsw_reg_trans_cb_t *cb, unsigned long cb_priv)
1393 return mlxsw_core_reg_access_emad(mlxsw_core, reg, payload,
1394 MLXSW_CORE_REG_ACCESS_TYPE_WRITE,
1395 bulk_list, cb, cb_priv);
1397 EXPORT_SYMBOL(mlxsw_reg_trans_write);
1399 static int mlxsw_reg_trans_wait(struct mlxsw_reg_trans *trans)
1401 struct mlxsw_core *mlxsw_core = trans->core;
1404 wait_for_completion(&trans->completion);
1405 cancel_delayed_work_sync(&trans->timeout_dw);
1409 dev_warn(mlxsw_core->bus_info->dev, "EMAD retries (%d/%d) (tid=%llx)\n",
1410 trans->retries, MLXSW_EMAD_MAX_RETRY, trans->tid);
1412 dev_err(mlxsw_core->bus_info->dev, "EMAD reg access failed (tid=%llx,reg_id=%x(%s),type=%s,status=%x(%s))\n",
1413 trans->tid, trans->reg->id,
1414 mlxsw_reg_id_str(trans->reg->id),
1415 mlxsw_core_reg_access_type_str(trans->type),
1417 mlxsw_emad_op_tlv_status_str(trans->emad_status));
1419 list_del(&trans->bulk_list);
1420 kfree_rcu(trans, rcu);
1424 int mlxsw_reg_trans_bulk_wait(struct list_head *bulk_list)
1426 struct mlxsw_reg_trans *trans;
1427 struct mlxsw_reg_trans *tmp;
1431 list_for_each_entry_safe(trans, tmp, bulk_list, bulk_list) {
1432 err = mlxsw_reg_trans_wait(trans);
1433 if (err && sum_err == 0)
1434 sum_err = err; /* first error to be returned */
1438 EXPORT_SYMBOL(mlxsw_reg_trans_bulk_wait);
1440 static int mlxsw_core_reg_access_cmd(struct mlxsw_core *mlxsw_core,
1441 const struct mlxsw_reg_info *reg,
1443 enum mlxsw_core_reg_access_type type)
1445 enum mlxsw_emad_op_tlv_status status;
1448 char *in_mbox, *out_mbox, *tmp;
1450 dev_dbg(mlxsw_core->bus_info->dev, "Reg cmd access (reg_id=%x(%s),type=%s)\n",
1451 reg->id, mlxsw_reg_id_str(reg->id),
1452 mlxsw_core_reg_access_type_str(type));
1454 in_mbox = mlxsw_cmd_mbox_alloc();
1458 out_mbox = mlxsw_cmd_mbox_alloc();
1464 mlxsw_emad_pack_op_tlv(in_mbox, reg, type,
1465 mlxsw_core_tid_get(mlxsw_core));
1466 tmp = in_mbox + MLXSW_EMAD_OP_TLV_LEN * sizeof(u32);
1467 mlxsw_emad_pack_reg_tlv(tmp, reg, payload);
1469 /* There is a special treatment needed for MRSR (reset) register.
1470 * The command interface will return error after the command
1471 * is executed, so tell the lower layer to expect it
1472 * and cope accordingly.
1474 reset_ok = reg->id == MLXSW_REG_MRSR_ID;
1478 err = mlxsw_cmd_access_reg(mlxsw_core, reset_ok, in_mbox, out_mbox);
1480 err = mlxsw_emad_process_status(out_mbox, &status);
1482 if (err == -EAGAIN && n_retry++ < MLXSW_EMAD_MAX_RETRY)
1484 dev_err(mlxsw_core->bus_info->dev, "Reg cmd access status failed (status=%x(%s))\n",
1485 status, mlxsw_emad_op_tlv_status_str(status));
1490 memcpy(payload, mlxsw_emad_reg_payload(out_mbox),
1493 mlxsw_cmd_mbox_free(out_mbox);
1495 mlxsw_cmd_mbox_free(in_mbox);
1497 dev_err(mlxsw_core->bus_info->dev, "Reg cmd access failed (reg_id=%x(%s),type=%s)\n",
1498 reg->id, mlxsw_reg_id_str(reg->id),
1499 mlxsw_core_reg_access_type_str(type));
1503 static void mlxsw_core_reg_access_cb(struct mlxsw_core *mlxsw_core,
1504 char *payload, size_t payload_len,
1505 unsigned long cb_priv)
1507 char *orig_payload = (char *) cb_priv;
1509 memcpy(orig_payload, payload, payload_len);
1512 static int mlxsw_core_reg_access(struct mlxsw_core *mlxsw_core,
1513 const struct mlxsw_reg_info *reg,
1515 enum mlxsw_core_reg_access_type type)
1517 LIST_HEAD(bulk_list);
1520 /* During initialization EMAD interface is not available to us,
1521 * so we default to command interface. We switch to EMAD interface
1522 * after setting the appropriate traps.
1524 if (!mlxsw_core->emad.use_emad)
1525 return mlxsw_core_reg_access_cmd(mlxsw_core, reg,
1528 err = mlxsw_core_reg_access_emad(mlxsw_core, reg,
1529 payload, type, &bulk_list,
1530 mlxsw_core_reg_access_cb,
1531 (unsigned long) payload);
1534 return mlxsw_reg_trans_bulk_wait(&bulk_list);
1537 int mlxsw_reg_query(struct mlxsw_core *mlxsw_core,
1538 const struct mlxsw_reg_info *reg, char *payload)
1540 return mlxsw_core_reg_access(mlxsw_core, reg, payload,
1541 MLXSW_CORE_REG_ACCESS_TYPE_QUERY);
1543 EXPORT_SYMBOL(mlxsw_reg_query);
1545 int mlxsw_reg_write(struct mlxsw_core *mlxsw_core,
1546 const struct mlxsw_reg_info *reg, char *payload)
1548 return mlxsw_core_reg_access(mlxsw_core, reg, payload,
1549 MLXSW_CORE_REG_ACCESS_TYPE_WRITE);
1551 EXPORT_SYMBOL(mlxsw_reg_write);
1553 void mlxsw_core_skb_receive(struct mlxsw_core *mlxsw_core, struct sk_buff *skb,
1554 struct mlxsw_rx_info *rx_info)
1556 struct mlxsw_rx_listener_item *rxl_item;
1557 const struct mlxsw_rx_listener *rxl;
1561 if (rx_info->is_lag) {
1562 dev_dbg_ratelimited(mlxsw_core->bus_info->dev, "%s: lag_id = %d, lag_port_index = 0x%x\n",
1563 __func__, rx_info->u.lag_id,
1565 /* Upper layer does not care if the skb came from LAG or not,
1566 * so just get the local_port for the lag port and push it up.
1568 local_port = mlxsw_core_lag_mapping_get(mlxsw_core,
1570 rx_info->lag_port_index);
1572 local_port = rx_info->u.sys_port;
1575 dev_dbg_ratelimited(mlxsw_core->bus_info->dev, "%s: local_port = %d, trap_id = 0x%x\n",
1576 __func__, local_port, rx_info->trap_id);
1578 if ((rx_info->trap_id >= MLXSW_TRAP_ID_MAX) ||
1579 (local_port >= mlxsw_core->max_ports))
1583 list_for_each_entry_rcu(rxl_item, &mlxsw_core->rx_listener_list, list) {
1584 rxl = &rxl_item->rxl;
1585 if ((rxl->local_port == MLXSW_PORT_DONT_CARE ||
1586 rxl->local_port == local_port) &&
1587 rxl->trap_id == rx_info->trap_id) {
1596 rxl->func(skb, local_port, rxl_item->priv);
1602 EXPORT_SYMBOL(mlxsw_core_skb_receive);
1604 static int mlxsw_core_lag_mapping_index(struct mlxsw_core *mlxsw_core,
1605 u16 lag_id, u8 port_index)
1607 return MLXSW_CORE_RES_GET(mlxsw_core, MAX_LAG_MEMBERS) * lag_id +
1611 void mlxsw_core_lag_mapping_set(struct mlxsw_core *mlxsw_core,
1612 u16 lag_id, u8 port_index, u8 local_port)
1614 int index = mlxsw_core_lag_mapping_index(mlxsw_core,
1615 lag_id, port_index);
1617 mlxsw_core->lag.mapping[index] = local_port;
1619 EXPORT_SYMBOL(mlxsw_core_lag_mapping_set);
1621 u8 mlxsw_core_lag_mapping_get(struct mlxsw_core *mlxsw_core,
1622 u16 lag_id, u8 port_index)
1624 int index = mlxsw_core_lag_mapping_index(mlxsw_core,
1625 lag_id, port_index);
1627 return mlxsw_core->lag.mapping[index];
1629 EXPORT_SYMBOL(mlxsw_core_lag_mapping_get);
1631 void mlxsw_core_lag_mapping_clear(struct mlxsw_core *mlxsw_core,
1632 u16 lag_id, u8 local_port)
1636 for (i = 0; i < MLXSW_CORE_RES_GET(mlxsw_core, MAX_LAG_MEMBERS); i++) {
1637 int index = mlxsw_core_lag_mapping_index(mlxsw_core,
1640 if (mlxsw_core->lag.mapping[index] == local_port)
1641 mlxsw_core->lag.mapping[index] = 0;
1644 EXPORT_SYMBOL(mlxsw_core_lag_mapping_clear);
1646 bool mlxsw_core_res_valid(struct mlxsw_core *mlxsw_core,
1647 enum mlxsw_res_id res_id)
1649 return mlxsw_res_valid(&mlxsw_core->res, res_id);
1651 EXPORT_SYMBOL(mlxsw_core_res_valid);
1653 u64 mlxsw_core_res_get(struct mlxsw_core *mlxsw_core,
1654 enum mlxsw_res_id res_id)
1656 return mlxsw_res_get(&mlxsw_core->res, res_id);
1658 EXPORT_SYMBOL(mlxsw_core_res_get);
1660 int mlxsw_core_port_init(struct mlxsw_core *mlxsw_core, u8 local_port)
1662 struct devlink *devlink = priv_to_devlink(mlxsw_core);
1663 struct mlxsw_core_port *mlxsw_core_port =
1664 &mlxsw_core->ports[local_port];
1665 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port;
1668 mlxsw_core_port->local_port = local_port;
1669 err = devlink_port_register(devlink, devlink_port, local_port);
1671 memset(mlxsw_core_port, 0, sizeof(*mlxsw_core_port));
1674 EXPORT_SYMBOL(mlxsw_core_port_init);
1676 void mlxsw_core_port_fini(struct mlxsw_core *mlxsw_core, u8 local_port)
1678 struct mlxsw_core_port *mlxsw_core_port =
1679 &mlxsw_core->ports[local_port];
1680 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port;
1682 devlink_port_unregister(devlink_port);
1683 memset(mlxsw_core_port, 0, sizeof(*mlxsw_core_port));
1685 EXPORT_SYMBOL(mlxsw_core_port_fini);
1687 void mlxsw_core_port_eth_set(struct mlxsw_core *mlxsw_core, u8 local_port,
1688 void *port_driver_priv, struct net_device *dev,
1689 u32 port_number, bool split,
1690 u32 split_port_subnumber)
1692 struct mlxsw_core_port *mlxsw_core_port =
1693 &mlxsw_core->ports[local_port];
1694 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port;
1696 mlxsw_core_port->port_driver_priv = port_driver_priv;
1697 devlink_port_attrs_set(devlink_port, DEVLINK_PORT_FLAVOUR_PHYSICAL,
1698 port_number, split, split_port_subnumber);
1699 devlink_port_type_eth_set(devlink_port, dev);
1701 EXPORT_SYMBOL(mlxsw_core_port_eth_set);
1703 void mlxsw_core_port_ib_set(struct mlxsw_core *mlxsw_core, u8 local_port,
1704 void *port_driver_priv)
1706 struct mlxsw_core_port *mlxsw_core_port =
1707 &mlxsw_core->ports[local_port];
1708 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port;
1710 mlxsw_core_port->port_driver_priv = port_driver_priv;
1711 devlink_port_type_ib_set(devlink_port, NULL);
1713 EXPORT_SYMBOL(mlxsw_core_port_ib_set);
1715 void mlxsw_core_port_clear(struct mlxsw_core *mlxsw_core, u8 local_port,
1716 void *port_driver_priv)
1718 struct mlxsw_core_port *mlxsw_core_port =
1719 &mlxsw_core->ports[local_port];
1720 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port;
1722 mlxsw_core_port->port_driver_priv = port_driver_priv;
1723 devlink_port_type_clear(devlink_port);
1725 EXPORT_SYMBOL(mlxsw_core_port_clear);
1727 enum devlink_port_type mlxsw_core_port_type_get(struct mlxsw_core *mlxsw_core,
1730 struct mlxsw_core_port *mlxsw_core_port =
1731 &mlxsw_core->ports[local_port];
1732 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port;
1734 return devlink_port->type;
1736 EXPORT_SYMBOL(mlxsw_core_port_type_get);
1738 int mlxsw_core_port_get_phys_port_name(struct mlxsw_core *mlxsw_core,
1739 u8 local_port, char *name, size_t len)
1741 struct mlxsw_core_port *mlxsw_core_port =
1742 &mlxsw_core->ports[local_port];
1743 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port;
1745 return devlink_port_get_phys_port_name(devlink_port, name, len);
1747 EXPORT_SYMBOL(mlxsw_core_port_get_phys_port_name);
1749 static void mlxsw_core_buf_dump_dbg(struct mlxsw_core *mlxsw_core,
1750 const char *buf, size_t size)
1752 __be32 *m = (__be32 *) buf;
1754 int count = size / sizeof(__be32);
1756 for (i = count - 1; i >= 0; i--)
1761 for (i = 0; i < count; i += 4)
1762 dev_dbg(mlxsw_core->bus_info->dev, "%04x - %08x %08x %08x %08x\n",
1763 i * 4, be32_to_cpu(m[i]), be32_to_cpu(m[i + 1]),
1764 be32_to_cpu(m[i + 2]), be32_to_cpu(m[i + 3]));
1767 int mlxsw_cmd_exec(struct mlxsw_core *mlxsw_core, u16 opcode, u8 opcode_mod,
1768 u32 in_mod, bool out_mbox_direct, bool reset_ok,
1769 char *in_mbox, size_t in_mbox_size,
1770 char *out_mbox, size_t out_mbox_size)
1775 BUG_ON(in_mbox_size % sizeof(u32) || out_mbox_size % sizeof(u32));
1776 if (!mlxsw_core->bus->cmd_exec)
1779 dev_dbg(mlxsw_core->bus_info->dev, "Cmd exec (opcode=%x(%s),opcode_mod=%x,in_mod=%x)\n",
1780 opcode, mlxsw_cmd_opcode_str(opcode), opcode_mod, in_mod);
1782 dev_dbg(mlxsw_core->bus_info->dev, "Input mailbox:\n");
1783 mlxsw_core_buf_dump_dbg(mlxsw_core, in_mbox, in_mbox_size);
1786 err = mlxsw_core->bus->cmd_exec(mlxsw_core->bus_priv, opcode,
1787 opcode_mod, in_mod, out_mbox_direct,
1788 in_mbox, in_mbox_size,
1789 out_mbox, out_mbox_size, &status);
1791 if (!err && out_mbox) {
1792 dev_dbg(mlxsw_core->bus_info->dev, "Output mailbox:\n");
1793 mlxsw_core_buf_dump_dbg(mlxsw_core, out_mbox, out_mbox_size);
1796 if (reset_ok && err == -EIO &&
1797 status == MLXSW_CMD_STATUS_RUNNING_RESET) {
1799 } else if (err == -EIO && status != MLXSW_CMD_STATUS_OK) {
1800 dev_err(mlxsw_core->bus_info->dev, "Cmd exec failed (opcode=%x(%s),opcode_mod=%x,in_mod=%x,status=%x(%s))\n",
1801 opcode, mlxsw_cmd_opcode_str(opcode), opcode_mod,
1802 in_mod, status, mlxsw_cmd_status_str(status));
1803 } else if (err == -ETIMEDOUT) {
1804 dev_err(mlxsw_core->bus_info->dev, "Cmd exec timed-out (opcode=%x(%s),opcode_mod=%x,in_mod=%x)\n",
1805 opcode, mlxsw_cmd_opcode_str(opcode), opcode_mod,
1811 EXPORT_SYMBOL(mlxsw_cmd_exec);
1813 int mlxsw_core_schedule_dw(struct delayed_work *dwork, unsigned long delay)
1815 return queue_delayed_work(mlxsw_wq, dwork, delay);
1817 EXPORT_SYMBOL(mlxsw_core_schedule_dw);
1819 bool mlxsw_core_schedule_work(struct work_struct *work)
1821 return queue_work(mlxsw_owq, work);
1823 EXPORT_SYMBOL(mlxsw_core_schedule_work);
1825 void mlxsw_core_flush_owq(void)
1827 flush_workqueue(mlxsw_owq);
1829 EXPORT_SYMBOL(mlxsw_core_flush_owq);
1831 int mlxsw_core_kvd_sizes_get(struct mlxsw_core *mlxsw_core,
1832 const struct mlxsw_config_profile *profile,
1833 u64 *p_single_size, u64 *p_double_size,
1836 struct mlxsw_driver *driver = mlxsw_core->driver;
1838 if (!driver->kvd_sizes_get)
1841 return driver->kvd_sizes_get(mlxsw_core, profile,
1842 p_single_size, p_double_size,
1845 EXPORT_SYMBOL(mlxsw_core_kvd_sizes_get);
1847 static int __init mlxsw_core_module_init(void)
1851 mlxsw_wq = alloc_workqueue(mlxsw_core_driver_name, WQ_MEM_RECLAIM, 0);
1854 mlxsw_owq = alloc_ordered_workqueue("%s_ordered", WQ_MEM_RECLAIM,
1855 mlxsw_core_driver_name);
1858 goto err_alloc_ordered_workqueue;
1862 err_alloc_ordered_workqueue:
1863 destroy_workqueue(mlxsw_wq);
1867 static void __exit mlxsw_core_module_exit(void)
1869 destroy_workqueue(mlxsw_owq);
1870 destroy_workqueue(mlxsw_wq);
1873 module_init(mlxsw_core_module_init);
1874 module_exit(mlxsw_core_module_exit);
1876 MODULE_LICENSE("Dual BSD/GPL");
1877 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
1878 MODULE_DESCRIPTION("Mellanox switch device core driver");