2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/module.h>
34 #include <linux/mlx5/driver.h>
35 #include <linux/mlx5/port.h>
36 #include <linux/mlx5/cmd.h>
37 #include "mlx5_core.h"
39 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
40 int size_in, void *data_out, int size_out,
41 u16 reg_id, int arg, int write)
43 int outlen = MLX5_ST_SZ_BYTES(access_register_out) + size_out;
44 int inlen = MLX5_ST_SZ_BYTES(access_register_in) + size_in;
50 in = kvzalloc(inlen, GFP_KERNEL);
51 out = kvzalloc(outlen, GFP_KERNEL);
55 data = MLX5_ADDR_OF(access_register_in, in, register_data);
56 memcpy(data, data_in, size_in);
58 MLX5_SET(access_register_in, in, opcode, MLX5_CMD_OP_ACCESS_REG);
59 MLX5_SET(access_register_in, in, op_mod, !write);
60 MLX5_SET(access_register_in, in, argument, arg);
61 MLX5_SET(access_register_in, in, register_id, reg_id);
63 err = mlx5_cmd_exec(dev, in, inlen, out, outlen);
67 data = MLX5_ADDR_OF(access_register_out, out, register_data);
68 memcpy(data_out, data, size_out);
75 EXPORT_SYMBOL_GPL(mlx5_core_access_reg);
77 int mlx5_query_pcam_reg(struct mlx5_core_dev *dev, u32 *pcam, u8 feature_group,
80 u32 in[MLX5_ST_SZ_DW(pcam_reg)] = {0};
81 int sz = MLX5_ST_SZ_BYTES(pcam_reg);
83 MLX5_SET(pcam_reg, in, feature_group, feature_group);
84 MLX5_SET(pcam_reg, in, access_reg_group, access_reg_group);
86 return mlx5_core_access_reg(dev, in, sz, pcam, sz, MLX5_REG_PCAM, 0, 0);
89 int mlx5_query_mcam_reg(struct mlx5_core_dev *dev, u32 *mcam, u8 feature_group,
92 u32 in[MLX5_ST_SZ_DW(mcam_reg)] = {0};
93 int sz = MLX5_ST_SZ_BYTES(mcam_reg);
95 MLX5_SET(mcam_reg, in, feature_group, feature_group);
96 MLX5_SET(mcam_reg, in, access_reg_group, access_reg_group);
98 return mlx5_core_access_reg(dev, in, sz, mcam, sz, MLX5_REG_MCAM, 0, 0);
101 struct mlx5_reg_pcap {
111 int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps)
113 struct mlx5_reg_pcap in;
114 struct mlx5_reg_pcap out;
116 memset(&in, 0, sizeof(in));
117 in.caps_127_96 = cpu_to_be32(caps);
118 in.port_num = port_num;
120 return mlx5_core_access_reg(dev, &in, sizeof(in), &out,
121 sizeof(out), MLX5_REG_PCAP, 0, 1);
123 EXPORT_SYMBOL_GPL(mlx5_set_port_caps);
125 int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
126 int ptys_size, int proto_mask, u8 local_port)
128 u32 in[MLX5_ST_SZ_DW(ptys_reg)] = {0};
130 MLX5_SET(ptys_reg, in, local_port, local_port);
131 MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
132 return mlx5_core_access_reg(dev, in, sizeof(in), ptys,
133 ptys_size, MLX5_REG_PTYS, 0, 0);
135 EXPORT_SYMBOL_GPL(mlx5_query_port_ptys);
137 int mlx5_set_port_beacon(struct mlx5_core_dev *dev, u16 beacon_duration)
139 u32 in[MLX5_ST_SZ_DW(mlcr_reg)] = {0};
140 u32 out[MLX5_ST_SZ_DW(mlcr_reg)];
142 MLX5_SET(mlcr_reg, in, local_port, 1);
143 MLX5_SET(mlcr_reg, in, beacon_duration, beacon_duration);
144 return mlx5_core_access_reg(dev, in, sizeof(in), out,
145 sizeof(out), MLX5_REG_MLCR, 0, 1);
148 int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev,
149 u32 *proto_cap, int proto_mask)
151 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
154 err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, 1);
158 if (proto_mask == MLX5_PTYS_EN)
159 *proto_cap = MLX5_GET(ptys_reg, out, eth_proto_capability);
161 *proto_cap = MLX5_GET(ptys_reg, out, ib_proto_capability);
165 EXPORT_SYMBOL_GPL(mlx5_query_port_proto_cap);
167 int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev,
168 u32 *proto_admin, int proto_mask)
170 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
173 err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, 1);
177 if (proto_mask == MLX5_PTYS_EN)
178 *proto_admin = MLX5_GET(ptys_reg, out, eth_proto_admin);
180 *proto_admin = MLX5_GET(ptys_reg, out, ib_proto_admin);
184 EXPORT_SYMBOL_GPL(mlx5_query_port_proto_admin);
186 int mlx5_query_port_link_width_oper(struct mlx5_core_dev *dev,
187 u8 *link_width_oper, u8 local_port)
189 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
192 err = mlx5_query_port_ptys(dev, out, sizeof(out), MLX5_PTYS_IB, local_port);
196 *link_width_oper = MLX5_GET(ptys_reg, out, ib_link_width_oper);
200 EXPORT_SYMBOL_GPL(mlx5_query_port_link_width_oper);
202 int mlx5_query_port_eth_proto_oper(struct mlx5_core_dev *dev,
203 u32 *proto_oper, u8 local_port)
205 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
208 err = mlx5_query_port_ptys(dev, out, sizeof(out), MLX5_PTYS_EN,
213 *proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
217 EXPORT_SYMBOL(mlx5_query_port_eth_proto_oper);
219 int mlx5_query_port_ib_proto_oper(struct mlx5_core_dev *dev,
220 u8 *proto_oper, u8 local_port)
222 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
225 err = mlx5_query_port_ptys(dev, out, sizeof(out), MLX5_PTYS_IB,
230 *proto_oper = MLX5_GET(ptys_reg, out, ib_proto_oper);
234 EXPORT_SYMBOL(mlx5_query_port_ib_proto_oper);
236 int mlx5_set_port_ptys(struct mlx5_core_dev *dev, bool an_disable,
237 u32 proto_admin, int proto_mask)
239 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
240 u32 in[MLX5_ST_SZ_DW(ptys_reg)];
245 mlx5_query_port_autoneg(dev, proto_mask, &an_status,
246 &an_disable_cap, &an_disable_admin);
247 if (!an_disable_cap && an_disable)
250 memset(in, 0, sizeof(in));
252 MLX5_SET(ptys_reg, in, local_port, 1);
253 MLX5_SET(ptys_reg, in, an_disable_admin, an_disable);
254 MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
255 if (proto_mask == MLX5_PTYS_EN)
256 MLX5_SET(ptys_reg, in, eth_proto_admin, proto_admin);
258 MLX5_SET(ptys_reg, in, ib_proto_admin, proto_admin);
260 return mlx5_core_access_reg(dev, in, sizeof(in), out,
261 sizeof(out), MLX5_REG_PTYS, 0, 1);
263 EXPORT_SYMBOL_GPL(mlx5_set_port_ptys);
265 /* This function should be used after setting a port register only */
266 void mlx5_toggle_port_link(struct mlx5_core_dev *dev)
268 enum mlx5_port_status ps;
270 mlx5_query_port_admin_status(dev, &ps);
271 mlx5_set_port_admin_status(dev, MLX5_PORT_DOWN);
272 if (ps == MLX5_PORT_UP)
273 mlx5_set_port_admin_status(dev, MLX5_PORT_UP);
275 EXPORT_SYMBOL_GPL(mlx5_toggle_port_link);
277 int mlx5_set_port_admin_status(struct mlx5_core_dev *dev,
278 enum mlx5_port_status status)
280 u32 in[MLX5_ST_SZ_DW(paos_reg)] = {0};
281 u32 out[MLX5_ST_SZ_DW(paos_reg)];
283 MLX5_SET(paos_reg, in, local_port, 1);
284 MLX5_SET(paos_reg, in, admin_status, status);
285 MLX5_SET(paos_reg, in, ase, 1);
286 return mlx5_core_access_reg(dev, in, sizeof(in), out,
287 sizeof(out), MLX5_REG_PAOS, 0, 1);
289 EXPORT_SYMBOL_GPL(mlx5_set_port_admin_status);
291 int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
292 enum mlx5_port_status *status)
294 u32 in[MLX5_ST_SZ_DW(paos_reg)] = {0};
295 u32 out[MLX5_ST_SZ_DW(paos_reg)];
298 MLX5_SET(paos_reg, in, local_port, 1);
299 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
300 sizeof(out), MLX5_REG_PAOS, 0, 0);
303 *status = MLX5_GET(paos_reg, out, admin_status);
306 EXPORT_SYMBOL_GPL(mlx5_query_port_admin_status);
308 static void mlx5_query_port_mtu(struct mlx5_core_dev *dev, u16 *admin_mtu,
309 u16 *max_mtu, u16 *oper_mtu, u8 port)
311 u32 in[MLX5_ST_SZ_DW(pmtu_reg)] = {0};
312 u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
314 MLX5_SET(pmtu_reg, in, local_port, port);
315 mlx5_core_access_reg(dev, in, sizeof(in), out,
316 sizeof(out), MLX5_REG_PMTU, 0, 0);
319 *max_mtu = MLX5_GET(pmtu_reg, out, max_mtu);
321 *oper_mtu = MLX5_GET(pmtu_reg, out, oper_mtu);
323 *admin_mtu = MLX5_GET(pmtu_reg, out, admin_mtu);
326 int mlx5_set_port_mtu(struct mlx5_core_dev *dev, u16 mtu, u8 port)
328 u32 in[MLX5_ST_SZ_DW(pmtu_reg)] = {0};
329 u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
331 MLX5_SET(pmtu_reg, in, admin_mtu, mtu);
332 MLX5_SET(pmtu_reg, in, local_port, port);
333 return mlx5_core_access_reg(dev, in, sizeof(in), out,
334 sizeof(out), MLX5_REG_PMTU, 0, 1);
336 EXPORT_SYMBOL_GPL(mlx5_set_port_mtu);
338 void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, u16 *max_mtu,
341 mlx5_query_port_mtu(dev, NULL, max_mtu, NULL, port);
343 EXPORT_SYMBOL_GPL(mlx5_query_port_max_mtu);
345 void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, u16 *oper_mtu,
348 mlx5_query_port_mtu(dev, NULL, NULL, oper_mtu, port);
350 EXPORT_SYMBOL_GPL(mlx5_query_port_oper_mtu);
352 static int mlx5_query_module_num(struct mlx5_core_dev *dev, int *module_num)
354 u32 in[MLX5_ST_SZ_DW(pmlp_reg)] = {0};
355 u32 out[MLX5_ST_SZ_DW(pmlp_reg)];
359 MLX5_SET(pmlp_reg, in, local_port, 1);
360 err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
361 MLX5_REG_PMLP, 0, 0);
365 module_mapping = MLX5_GET(pmlp_reg, out, lane0_module_mapping);
366 *module_num = module_mapping & MLX5_EEPROM_IDENTIFIER_BYTE_MASK;
371 int mlx5_query_module_eeprom(struct mlx5_core_dev *dev,
372 u16 offset, u16 size, u8 *data)
374 u32 out[MLX5_ST_SZ_DW(mcia_reg)];
375 u32 in[MLX5_ST_SZ_DW(mcia_reg)];
380 void *ptr = MLX5_ADDR_OF(mcia_reg, out, dword_0);
382 err = mlx5_query_module_num(dev, &module_num);
386 memset(in, 0, sizeof(in));
387 size = min_t(int, size, MLX5_EEPROM_MAX_BYTES);
389 if (offset < MLX5_EEPROM_PAGE_LENGTH &&
390 offset + size > MLX5_EEPROM_PAGE_LENGTH)
391 /* Cross pages read, read until offset 256 in low page */
392 size -= offset + size - MLX5_EEPROM_PAGE_LENGTH;
394 i2c_addr = MLX5_I2C_ADDR_LOW;
395 if (offset >= MLX5_EEPROM_PAGE_LENGTH) {
396 i2c_addr = MLX5_I2C_ADDR_HIGH;
397 offset -= MLX5_EEPROM_PAGE_LENGTH;
400 MLX5_SET(mcia_reg, in, l, 0);
401 MLX5_SET(mcia_reg, in, module, module_num);
402 MLX5_SET(mcia_reg, in, i2c_device_address, i2c_addr);
403 MLX5_SET(mcia_reg, in, page_number, 0);
404 MLX5_SET(mcia_reg, in, device_address, offset);
405 MLX5_SET(mcia_reg, in, size, size);
407 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
408 sizeof(out), MLX5_REG_MCIA, 0, 0);
412 status = MLX5_GET(mcia_reg, out, status);
414 mlx5_core_err(dev, "query_mcia_reg failed: status: 0x%x\n",
419 memcpy(data, ptr, size);
423 EXPORT_SYMBOL_GPL(mlx5_query_module_eeprom);
425 static int mlx5_query_port_pvlc(struct mlx5_core_dev *dev, u32 *pvlc,
426 int pvlc_size, u8 local_port)
428 u32 in[MLX5_ST_SZ_DW(pvlc_reg)] = {0};
430 MLX5_SET(pvlc_reg, in, local_port, local_port);
431 return mlx5_core_access_reg(dev, in, sizeof(in), pvlc,
432 pvlc_size, MLX5_REG_PVLC, 0, 0);
435 int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev,
436 u8 *vl_hw_cap, u8 local_port)
438 u32 out[MLX5_ST_SZ_DW(pvlc_reg)];
441 err = mlx5_query_port_pvlc(dev, out, sizeof(out), local_port);
445 *vl_hw_cap = MLX5_GET(pvlc_reg, out, vl_hw_cap);
449 EXPORT_SYMBOL_GPL(mlx5_query_port_vl_hw_cap);
451 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
452 u8 port_num, void *out, size_t sz)
457 in = kvzalloc(sz, GFP_KERNEL);
463 MLX5_SET(ppcnt_reg, in, local_port, port_num);
465 MLX5_SET(ppcnt_reg, in, grp, MLX5_INFINIBAND_PORT_COUNTERS_GROUP);
466 err = mlx5_core_access_reg(dev, in, sz, out,
467 sz, MLX5_REG_PPCNT, 0, 0);
472 EXPORT_SYMBOL_GPL(mlx5_core_query_ib_ppcnt);
474 int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause)
476 u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
477 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
479 MLX5_SET(pfcc_reg, in, local_port, 1);
480 MLX5_SET(pfcc_reg, in, pptx, tx_pause);
481 MLX5_SET(pfcc_reg, in, pprx, rx_pause);
483 return mlx5_core_access_reg(dev, in, sizeof(in), out,
484 sizeof(out), MLX5_REG_PFCC, 0, 1);
486 EXPORT_SYMBOL_GPL(mlx5_set_port_pause);
488 int mlx5_query_port_pause(struct mlx5_core_dev *dev,
489 u32 *rx_pause, u32 *tx_pause)
491 u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
492 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
495 MLX5_SET(pfcc_reg, in, local_port, 1);
496 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
497 sizeof(out), MLX5_REG_PFCC, 0, 0);
502 *rx_pause = MLX5_GET(pfcc_reg, out, pprx);
505 *tx_pause = MLX5_GET(pfcc_reg, out, pptx);
509 EXPORT_SYMBOL_GPL(mlx5_query_port_pause);
511 int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx)
513 u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
514 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
516 MLX5_SET(pfcc_reg, in, local_port, 1);
517 MLX5_SET(pfcc_reg, in, pfctx, pfc_en_tx);
518 MLX5_SET(pfcc_reg, in, pfcrx, pfc_en_rx);
519 MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_tx);
520 MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_rx);
522 return mlx5_core_access_reg(dev, in, sizeof(in), out,
523 sizeof(out), MLX5_REG_PFCC, 0, 1);
525 EXPORT_SYMBOL_GPL(mlx5_set_port_pfc);
527 int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx, u8 *pfc_en_rx)
529 u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
530 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
533 MLX5_SET(pfcc_reg, in, local_port, 1);
534 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
535 sizeof(out), MLX5_REG_PFCC, 0, 0);
540 *pfc_en_tx = MLX5_GET(pfcc_reg, out, pfctx);
543 *pfc_en_rx = MLX5_GET(pfcc_reg, out, pfcrx);
547 EXPORT_SYMBOL_GPL(mlx5_query_port_pfc);
549 void mlx5_query_port_autoneg(struct mlx5_core_dev *dev, int proto_mask,
551 u8 *an_disable_cap, u8 *an_disable_admin)
553 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
557 *an_disable_admin = 0;
559 if (mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, 1))
562 *an_status = MLX5_GET(ptys_reg, out, an_status);
563 *an_disable_cap = MLX5_GET(ptys_reg, out, an_disable_cap);
564 *an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin);
566 EXPORT_SYMBOL_GPL(mlx5_query_port_autoneg);
568 int mlx5_max_tc(struct mlx5_core_dev *mdev)
570 u8 num_tc = MLX5_CAP_GEN(mdev, max_tc) ? : 8;
575 int mlx5_query_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *out)
577 u32 in[MLX5_ST_SZ_DW(dcbx_param)] = {0};
579 MLX5_SET(dcbx_param, in, port_number, 1);
581 return mlx5_core_access_reg(mdev, in, sizeof(in), out,
582 sizeof(in), MLX5_REG_DCBX_PARAM, 0, 0);
585 int mlx5_set_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *in)
587 u32 out[MLX5_ST_SZ_DW(dcbx_param)];
589 MLX5_SET(dcbx_param, in, port_number, 1);
591 return mlx5_core_access_reg(mdev, in, sizeof(out), out,
592 sizeof(out), MLX5_REG_DCBX_PARAM, 0, 1);
595 int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, u8 *prio_tc)
597 u32 in[MLX5_ST_SZ_DW(qtct_reg)] = {0};
598 u32 out[MLX5_ST_SZ_DW(qtct_reg)];
602 for (i = 0; i < 8; i++) {
603 if (prio_tc[i] > mlx5_max_tc(mdev))
606 MLX5_SET(qtct_reg, in, prio, i);
607 MLX5_SET(qtct_reg, in, tclass, prio_tc[i]);
609 err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
610 sizeof(out), MLX5_REG_QTCT, 0, 1);
617 EXPORT_SYMBOL_GPL(mlx5_set_port_prio_tc);
619 int mlx5_query_port_prio_tc(struct mlx5_core_dev *mdev,
622 u32 in[MLX5_ST_SZ_DW(qtct_reg)];
623 u32 out[MLX5_ST_SZ_DW(qtct_reg)];
626 memset(in, 0, sizeof(in));
627 memset(out, 0, sizeof(out));
629 MLX5_SET(qtct_reg, in, port_number, 1);
630 MLX5_SET(qtct_reg, in, prio, prio);
632 err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
633 sizeof(out), MLX5_REG_QTCT, 0, 0);
635 *tc = MLX5_GET(qtct_reg, out, tclass);
639 EXPORT_SYMBOL_GPL(mlx5_query_port_prio_tc);
641 static int mlx5_set_port_qetcr_reg(struct mlx5_core_dev *mdev, u32 *in,
644 u32 out[MLX5_ST_SZ_DW(qtct_reg)];
646 if (!MLX5_CAP_GEN(mdev, ets))
649 return mlx5_core_access_reg(mdev, in, inlen, out, sizeof(out),
650 MLX5_REG_QETCR, 0, 1);
653 static int mlx5_query_port_qetcr_reg(struct mlx5_core_dev *mdev, u32 *out,
656 u32 in[MLX5_ST_SZ_DW(qtct_reg)];
658 if (!MLX5_CAP_GEN(mdev, ets))
661 memset(in, 0, sizeof(in));
662 return mlx5_core_access_reg(mdev, in, sizeof(in), out, outlen,
663 MLX5_REG_QETCR, 0, 0);
666 int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, u8 *tc_group)
668 u32 in[MLX5_ST_SZ_DW(qetc_reg)] = {0};
671 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
672 MLX5_SET(qetc_reg, in, tc_configuration[i].g, 1);
673 MLX5_SET(qetc_reg, in, tc_configuration[i].group, tc_group[i]);
676 return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
678 EXPORT_SYMBOL_GPL(mlx5_set_port_tc_group);
680 int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *tc_bw)
682 u32 in[MLX5_ST_SZ_DW(qetc_reg)] = {0};
685 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
686 MLX5_SET(qetc_reg, in, tc_configuration[i].b, 1);
687 MLX5_SET(qetc_reg, in, tc_configuration[i].bw_allocation, tc_bw[i]);
690 return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
692 EXPORT_SYMBOL_GPL(mlx5_set_port_tc_bw_alloc);
694 int mlx5_query_port_tc_bw_alloc(struct mlx5_core_dev *mdev,
697 u32 out[MLX5_ST_SZ_DW(qetc_reg)];
701 err = mlx5_query_port_qetcr_reg(mdev, out, sizeof(out));
705 ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, out,
706 tc_configuration[tc]);
708 *bw_pct = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
713 EXPORT_SYMBOL_GPL(mlx5_query_port_tc_bw_alloc);
715 int mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev *mdev,
719 u32 in[MLX5_ST_SZ_DW(qetc_reg)] = {0};
723 MLX5_SET(qetc_reg, in, port_number, 1);
725 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
726 ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, in, tc_configuration[i]);
728 MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, r, 1);
729 MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, max_bw_units,
731 MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, max_bw_value,
735 return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
737 EXPORT_SYMBOL_GPL(mlx5_modify_port_ets_rate_limit);
739 int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev *mdev,
743 u32 out[MLX5_ST_SZ_DW(qetc_reg)];
748 err = mlx5_query_port_qetcr_reg(mdev, out, sizeof(out));
752 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
753 ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, out, tc_configuration[i]);
755 max_bw_value[i] = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
757 max_bw_units[i] = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
763 EXPORT_SYMBOL_GPL(mlx5_query_port_ets_rate_limit);
765 int mlx5_set_port_wol(struct mlx5_core_dev *mdev, u8 wol_mode)
767 u32 in[MLX5_ST_SZ_DW(set_wol_rol_in)] = {0};
768 u32 out[MLX5_ST_SZ_DW(set_wol_rol_out)] = {0};
770 MLX5_SET(set_wol_rol_in, in, opcode, MLX5_CMD_OP_SET_WOL_ROL);
771 MLX5_SET(set_wol_rol_in, in, wol_mode_valid, 1);
772 MLX5_SET(set_wol_rol_in, in, wol_mode, wol_mode);
773 return mlx5_cmd_exec(mdev, in, sizeof(in), out, sizeof(out));
775 EXPORT_SYMBOL_GPL(mlx5_set_port_wol);
777 int mlx5_query_port_wol(struct mlx5_core_dev *mdev, u8 *wol_mode)
779 u32 in[MLX5_ST_SZ_DW(query_wol_rol_in)] = {0};
780 u32 out[MLX5_ST_SZ_DW(query_wol_rol_out)] = {0};
783 MLX5_SET(query_wol_rol_in, in, opcode, MLX5_CMD_OP_QUERY_WOL_ROL);
784 err = mlx5_cmd_exec(mdev, in, sizeof(in), out, sizeof(out));
786 *wol_mode = MLX5_GET(query_wol_rol_out, out, wol_mode);
790 EXPORT_SYMBOL_GPL(mlx5_query_port_wol);
792 static int mlx5_query_ports_check(struct mlx5_core_dev *mdev, u32 *out,
795 u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {0};
797 MLX5_SET(pcmr_reg, in, local_port, 1);
798 return mlx5_core_access_reg(mdev, in, sizeof(in), out,
799 outlen, MLX5_REG_PCMR, 0, 0);
802 static int mlx5_set_ports_check(struct mlx5_core_dev *mdev, u32 *in, int inlen)
804 u32 out[MLX5_ST_SZ_DW(pcmr_reg)];
806 return mlx5_core_access_reg(mdev, in, inlen, out,
807 sizeof(out), MLX5_REG_PCMR, 0, 1);
810 int mlx5_set_port_fcs(struct mlx5_core_dev *mdev, u8 enable)
812 u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {0};
814 MLX5_SET(pcmr_reg, in, local_port, 1);
815 MLX5_SET(pcmr_reg, in, fcs_chk, enable);
816 return mlx5_set_ports_check(mdev, in, sizeof(in));
819 void mlx5_query_port_fcs(struct mlx5_core_dev *mdev, bool *supported,
822 u32 out[MLX5_ST_SZ_DW(pcmr_reg)];
823 /* Default values for FW which do not support MLX5_REG_PCMR */
827 if (!MLX5_CAP_GEN(mdev, ports_check))
830 if (mlx5_query_ports_check(mdev, out, sizeof(out)))
833 *supported = !!(MLX5_GET(pcmr_reg, out, fcs_cap));
834 *enabled = !!(MLX5_GET(pcmr_reg, out, fcs_chk));
837 static const char *mlx5_pme_status[MLX5_MODULE_STATUS_NUM] = {
838 "Cable plugged", /* MLX5_MODULE_STATUS_PLUGGED = 0x1 */
839 "Cable unplugged", /* MLX5_MODULE_STATUS_UNPLUGGED = 0x2 */
840 "Cable error", /* MLX5_MODULE_STATUS_ERROR = 0x3 */
843 static const char *mlx5_pme_error[MLX5_MODULE_EVENT_ERROR_NUM] = {
844 "Power budget exceeded",
845 "Long Range for non MLNX cable",
846 "Bus stuck(I2C or data shorted)",
847 "No EEPROM/retry timeout",
848 "Enforce part number list",
849 "Unknown identifier",
851 "Bad or shorted cable/module",
855 void mlx5_port_module_event(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe)
857 enum port_module_event_status_type module_status;
858 enum port_module_event_error_type error_type;
859 struct mlx5_eqe_port_module *module_event_eqe;
860 struct mlx5_priv *priv = &dev->priv;
863 module_event_eqe = &eqe->data.port_module;
864 module_num = module_event_eqe->module;
865 module_status = module_event_eqe->module_status &
866 PORT_MODULE_EVENT_MODULE_STATUS_MASK;
867 error_type = module_event_eqe->error_type &
868 PORT_MODULE_EVENT_ERROR_TYPE_MASK;
870 if (module_status < MLX5_MODULE_STATUS_ERROR) {
871 priv->pme_stats.status_counters[module_status - 1]++;
872 } else if (module_status == MLX5_MODULE_STATUS_ERROR) {
873 if (error_type >= MLX5_MODULE_EVENT_ERROR_UNKNOWN)
874 /* Unknown error type */
875 error_type = MLX5_MODULE_EVENT_ERROR_UNKNOWN;
876 priv->pme_stats.error_counters[error_type]++;
879 if (!printk_ratelimit())
882 if (module_status < MLX5_MODULE_STATUS_ERROR)
884 "Port module event: module %u, %s\n",
885 module_num, mlx5_pme_status[module_status - 1]);
887 else if (module_status == MLX5_MODULE_STATUS_ERROR)
889 "Port module event[error]: module %u, %s, %s\n",
890 module_num, mlx5_pme_status[module_status - 1],
891 mlx5_pme_error[error_type]);
894 int mlx5_query_mtpps(struct mlx5_core_dev *mdev, u32 *mtpps, u32 mtpps_size)
896 u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0};
898 return mlx5_core_access_reg(mdev, in, sizeof(in), mtpps,
899 mtpps_size, MLX5_REG_MTPPS, 0, 0);
902 int mlx5_set_mtpps(struct mlx5_core_dev *mdev, u32 *mtpps, u32 mtpps_size)
904 u32 out[MLX5_ST_SZ_DW(mtpps_reg)] = {0};
906 return mlx5_core_access_reg(mdev, mtpps, mtpps_size, out,
907 sizeof(out), MLX5_REG_MTPPS, 0, 1);
910 int mlx5_query_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 *arm, u8 *mode)
912 u32 out[MLX5_ST_SZ_DW(mtppse_reg)] = {0};
913 u32 in[MLX5_ST_SZ_DW(mtppse_reg)] = {0};
916 MLX5_SET(mtppse_reg, in, pin, pin);
918 err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
919 sizeof(out), MLX5_REG_MTPPSE, 0, 0);
923 *arm = MLX5_GET(mtppse_reg, in, event_arm);
924 *mode = MLX5_GET(mtppse_reg, in, event_generation_mode);
929 int mlx5_set_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 arm, u8 mode)
931 u32 out[MLX5_ST_SZ_DW(mtppse_reg)] = {0};
932 u32 in[MLX5_ST_SZ_DW(mtppse_reg)] = {0};
934 MLX5_SET(mtppse_reg, in, pin, pin);
935 MLX5_SET(mtppse_reg, in, event_arm, arm);
936 MLX5_SET(mtppse_reg, in, event_generation_mode, mode);
938 return mlx5_core_access_reg(mdev, in, sizeof(in), out,
939 sizeof(out), MLX5_REG_MTPPSE, 0, 1);