drivers/net/ethernet/mellanox/mlx5/core/health.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/kernel.h>
  34 #include <linux/module.h>
  35 #include <linux/random.h>
  36 #include <linux/vmalloc.h>
  37 #include <linux/hardirq.h>
  38 #include <linux/mlx5/driver.h>
  39 #include <linux/mlx5/cmd.h>
  40 #include "mlx5_core.h"
  41
  42 enum {
  43         MLX5_HEALTH_POLL_INTERVAL       = 2 * HZ,
  44         MAX_MISSES                      = 3,
  45 };
  46
  47 enum {
  48         MLX5_HEALTH_SYNDR_FW_ERR                = 0x1,
  49         MLX5_HEALTH_SYNDR_IRISC_ERR             = 0x7,
  50         MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR  = 0x8,
  51         MLX5_HEALTH_SYNDR_CRC_ERR               = 0x9,
  52         MLX5_HEALTH_SYNDR_FETCH_PCI_ERR         = 0xa,
  53         MLX5_HEALTH_SYNDR_HW_FTL_ERR            = 0xb,
  54         MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR  = 0xc,
  55         MLX5_HEALTH_SYNDR_EQ_ERR                = 0xd,
  56         MLX5_HEALTH_SYNDR_EQ_INV                = 0xe,
  57         MLX5_HEALTH_SYNDR_FFSER_ERR             = 0xf,
  58         MLX5_HEALTH_SYNDR_HIGH_TEMP             = 0x10
  59 };
  60
  61 enum {
  62         MLX5_DROP_NEW_HEALTH_WORK,
  63         MLX5_DROP_NEW_RECOVERY_WORK,
  64 };
  65
  66 u8 mlx5_get_nic_state(struct mlx5_core_dev *dev)
  67 {
  68         return (ioread32be(&dev->iseg->cmdq_addr_l_sz) >> 8) & 3;
  69 }
  70
  71 void mlx5_set_nic_state(struct mlx5_core_dev *dev, u8 state)
  72 {
  73         u32 cur_cmdq_addr_l_sz;
  74
  75         cur_cmdq_addr_l_sz = ioread32be(&dev->iseg->cmdq_addr_l_sz);
  76         iowrite32be((cur_cmdq_addr_l_sz & 0xFFFFF000) |
  77                     state << MLX5_NIC_IFC_OFFSET,
  78                     &dev->iseg->cmdq_addr_l_sz);
  79 }
  80
  81 static void trigger_cmd_completions(struct mlx5_core_dev *dev)
  82 {
  83         unsigned long flags;
  84         u64 vector;
  85
  86         /* wait for pending handlers to complete */
  87         synchronize_irq(pci_irq_vector(dev->pdev, MLX5_EQ_VEC_CMD));
  88         spin_lock_irqsave(&dev->cmd.alloc_lock, flags);
  89         vector = ~dev->cmd.bitmask & ((1ul << (1 << dev->cmd.log_sz)) - 1);
  90         if (!vector)
  91                 goto no_trig;
  92
  93         vector |= MLX5_TRIGGERED_CMD_COMP;
  94         spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags);
  95
  96         mlx5_core_dbg(dev, "vector 0x%llx\n", vector);
  97         mlx5_cmd_comp_handler(dev, vector, true);
  98         return;
  99
 100 no_trig:
 101         spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags);
 102 }
 103
 104 static int in_fatal(struct mlx5_core_dev *dev)
 105 {
 106         struct mlx5_core_health *health = &dev->priv.health;
 107         struct health_buffer __iomem *h = health->health;
 108
 109         if (mlx5_get_nic_state(dev) == MLX5_NIC_IFC_DISABLED)
 110                 return 1;
 111
 112         if (ioread32be(&h->fw_ver) == 0xffffffff)
 113                 return 1;
 114
 115         return 0;
 116 }
 117
 118 void mlx5_enter_error_state(struct mlx5_core_dev *dev, bool force)
 119 {
 120         mutex_lock(&dev->intf_state_mutex);
 121         if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR)
 122                 goto unlock;
 123
 124         mlx5_core_err(dev, "start\n");
 125         if (pci_channel_offline(dev->pdev) || in_fatal(dev) || force) {
 126                 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
 127                 trigger_cmd_completions(dev);
 128         }
 129
 130         mlx5_core_event(dev, MLX5_DEV_EVENT_SYS_ERROR, 1);
 131         mlx5_core_err(dev, "end\n");
 132
 133 unlock:
 134         mutex_unlock(&dev->intf_state_mutex);
 135 }
 136
 137 static void mlx5_handle_bad_state(struct mlx5_core_dev *dev)
 138 {
 139         u8 nic_interface = mlx5_get_nic_state(dev);
 140
 141         switch (nic_interface) {
 142         case MLX5_NIC_IFC_FULL:
 143                 mlx5_core_warn(dev, "Expected to see disabled NIC but it is full driver\n");
 144                 break;
 145
 146         case MLX5_NIC_IFC_DISABLED:
 147                 mlx5_core_warn(dev, "starting teardown\n");
 148                 break;
 149
 150         case MLX5_NIC_IFC_NO_DRAM_NIC:
 151                 mlx5_core_warn(dev, "Expected to see disabled NIC but it is no dram nic\n");
 152                 break;
 153         default:
 154                 mlx5_core_warn(dev, "Expected to see disabled NIC but it is has invalid value %d\n",
 155                                nic_interface);
 156         }
 157
 158         mlx5_disable_device(dev);
 159 }
 160
 161 static void health_recover(struct work_struct *work)
 162 {
 163         struct mlx5_core_health *health;
 164         struct delayed_work *dwork;
 165         struct mlx5_core_dev *dev;
 166         struct mlx5_priv *priv;
 167         u8 nic_state;
 168
 169         dwork = container_of(work, struct delayed_work, work);
 170         health = container_of(dwork, struct mlx5_core_health, recover_work);
 171         priv = container_of(health, struct mlx5_priv, health);
 172         dev = container_of(priv, struct mlx5_core_dev, priv);
 173
 174         nic_state = mlx5_get_nic_state(dev);
 175         if (nic_state == MLX5_NIC_IFC_INVALID) {
 176                 dev_err(&dev->pdev->dev, "health recovery flow aborted since the nic state is invalid\n");
 177                 return;
 178         }
 179
 180         dev_err(&dev->pdev->dev, "starting health recovery flow\n");
 181         mlx5_recover_device(dev);
 182 }
 183
 184 /* How much time to wait until health resetting the driver (in msecs) */
 185 #define MLX5_RECOVERY_DELAY_MSECS 60000
 186 static void health_care(struct work_struct *work)
 187 {
 188         unsigned long recover_delay = msecs_to_jiffies(MLX5_RECOVERY_DELAY_MSECS);
 189         struct mlx5_core_health *health;
 190         struct mlx5_core_dev *dev;
 191         struct mlx5_priv *priv;
 192         unsigned long flags;
 193
 194         health = container_of(work, struct mlx5_core_health, work);
 195         priv = container_of(health, struct mlx5_priv, health);
 196         dev = container_of(priv, struct mlx5_core_dev, priv);
 197         mlx5_core_warn(dev, "handling bad device here\n");
 198         mlx5_handle_bad_state(dev);
 199
 200         spin_lock_irqsave(&health->wq_lock, flags);
 201         if (!test_bit(MLX5_DROP_NEW_RECOVERY_WORK, &health->flags))
 202                 schedule_delayed_work(&health->recover_work, recover_delay);
 203         else
 204                 dev_err(&dev->pdev->dev,
 205                         "new health works are not permitted at this stage\n");
 206         spin_unlock_irqrestore(&health->wq_lock, flags);
 207 }
 208
 209 static const char *hsynd_str(u8 synd)
 210 {
 211         switch (synd) {
 212         case MLX5_HEALTH_SYNDR_FW_ERR:
 213                 return "firmware internal error";
 214         case MLX5_HEALTH_SYNDR_IRISC_ERR:
 215                 return "irisc not responding";
 216         case MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR:
 217                 return "unrecoverable hardware error";
 218         case MLX5_HEALTH_SYNDR_CRC_ERR:
 219                 return "firmware CRC error";
 220         case MLX5_HEALTH_SYNDR_FETCH_PCI_ERR:
 221                 return "ICM fetch PCI error";
 222         case MLX5_HEALTH_SYNDR_HW_FTL_ERR:
 223                 return "HW fatal error\n";
 224         case MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR:
 225                 return "async EQ buffer overrun";
 226         case MLX5_HEALTH_SYNDR_EQ_ERR:
 227                 return "EQ error";
 228         case MLX5_HEALTH_SYNDR_EQ_INV:
 229                 return "Invalid EQ referenced";
 230         case MLX5_HEALTH_SYNDR_FFSER_ERR:
 231                 return "FFSER error";
 232         case MLX5_HEALTH_SYNDR_HIGH_TEMP:
 233                 return "High temperature";
 234         default:
 235                 return "unrecognized error";
 236         }
 237 }
 238
 239 static void print_health_info(struct mlx5_core_dev *dev)
 240 {
 241         struct mlx5_core_health *health = &dev->priv.health;
 242         struct health_buffer __iomem *h = health->health;
 243         char fw_str[18];
 244         u32 fw;
 245         int i;
 246
 247         /* If the syndrome is 0, the device is OK and no need to print buffer */
 248         if (!ioread8(&h->synd))
 249                 return;
 250
 251         for (i = 0; i < ARRAY_SIZE(h->assert_var); i++)
 252                 dev_err(&dev->pdev->dev, "assert_var[%d] 0x%08x\n", i, ioread32be(h->assert_var + i));
 253
 254         dev_err(&dev->pdev->dev, "assert_exit_ptr 0x%08x\n", ioread32be(&h->assert_exit_ptr));
 255         dev_err(&dev->pdev->dev, "assert_callra 0x%08x\n", ioread32be(&h->assert_callra));
 256         sprintf(fw_str, "%d.%d.%d", fw_rev_maj(dev), fw_rev_min(dev), fw_rev_sub(dev));
 257         dev_err(&dev->pdev->dev, "fw_ver %s\n", fw_str);
 258         dev_err(&dev->pdev->dev, "hw_id 0x%08x\n", ioread32be(&h->hw_id));
 259         dev_err(&dev->pdev->dev, "irisc_index %d\n", ioread8(&h->irisc_index));
 260         dev_err(&dev->pdev->dev, "synd 0x%x: %s\n", ioread8(&h->synd), hsynd_str(ioread8(&h->synd)));
 261         dev_err(&dev->pdev->dev, "ext_synd 0x%04x\n", ioread16be(&h->ext_synd));
 262         fw = ioread32be(&h->fw_ver);
 263         dev_err(&dev->pdev->dev, "raw fw_ver 0x%08x\n", fw);
 264 }
 265
 266 static unsigned long get_next_poll_jiffies(void)
 267 {
 268         unsigned long next;
 269
 270         get_random_bytes(&next, sizeof(next));
 271         next %= HZ;
 272         next += jiffies + MLX5_HEALTH_POLL_INTERVAL;
 273
 274         return next;
 275 }
 276
 277 void mlx5_trigger_health_work(struct mlx5_core_dev *dev)
 278 {
 279         struct mlx5_core_health *health = &dev->priv.health;
 280         unsigned long flags;
 281
 282         spin_lock_irqsave(&health->wq_lock, flags);
 283         if (!test_bit(MLX5_DROP_NEW_HEALTH_WORK, &health->flags))
 284                 queue_work(health->wq, &health->work);
 285         else
 286                 dev_err(&dev->pdev->dev,
 287                         "new health works are not permitted at this stage\n");
 288         spin_unlock_irqrestore(&health->wq_lock, flags);
 289 }
 290
 291 static void poll_health(struct timer_list *t)
 292 {
 293         struct mlx5_core_dev *dev = from_timer(dev, t, priv.health.timer);
 294         struct mlx5_core_health *health = &dev->priv.health;
 295         u32 count;
 296
 297         if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR)
 298                 goto out;
 299
 300         count = ioread32be(health->health_counter);
 301         if (count == health->prev)
 302                 ++health->miss_counter;
 303         else
 304                 health->miss_counter = 0;
 305
 306         health->prev = count;
 307         if (health->miss_counter == MAX_MISSES) {
 308                 dev_err(&dev->pdev->dev, "device's health compromised - reached miss count\n");
 309                 print_health_info(dev);
 310         }
 311
 312         if (in_fatal(dev) && !health->sick) {
 313                 health->sick = true;
 314                 print_health_info(dev);
 315                 mlx5_trigger_health_work(dev);
 316         }
 317
 318 out:
 319         mod_timer(&health->timer, get_next_poll_jiffies());
 320 }
 321
 322 void mlx5_start_health_poll(struct mlx5_core_dev *dev)
 323 {
 324         struct mlx5_core_health *health = &dev->priv.health;
 325
 326         timer_setup(&health->timer, poll_health, 0);
 327         health->sick = 0;
 328         clear_bit(MLX5_DROP_NEW_HEALTH_WORK, &health->flags);
 329         clear_bit(MLX5_DROP_NEW_RECOVERY_WORK, &health->flags);
 330         health->health = &dev->iseg->health;
 331         health->health_counter = &dev->iseg->health_counter;
 332
 333         health->timer.expires = round_jiffies(jiffies + MLX5_HEALTH_POLL_INTERVAL);
 334         add_timer(&health->timer);
 335 }
 336
 337 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health)
 338 {
 339         struct mlx5_core_health *health = &dev->priv.health;
 340         unsigned long flags;
 341
 342         if (disable_health) {
 343                 spin_lock_irqsave(&health->wq_lock, flags);
 344                 set_bit(MLX5_DROP_NEW_HEALTH_WORK, &health->flags);
 345                 set_bit(MLX5_DROP_NEW_RECOVERY_WORK, &health->flags);
 346                 spin_unlock_irqrestore(&health->wq_lock, flags);
 347         }
 348
 349         del_timer_sync(&health->timer);
 350 }
 351
 352 void mlx5_drain_health_wq(struct mlx5_core_dev *dev)
 353 {
 354         struct mlx5_core_health *health = &dev->priv.health;
 355         unsigned long flags;
 356
 357         spin_lock_irqsave(&health->wq_lock, flags);
 358         set_bit(MLX5_DROP_NEW_HEALTH_WORK, &health->flags);
 359         set_bit(MLX5_DROP_NEW_RECOVERY_WORK, &health->flags);
 360         spin_unlock_irqrestore(&health->wq_lock, flags);
 361         cancel_delayed_work_sync(&health->recover_work);
 362         cancel_work_sync(&health->work);
 363 }
 364
 365 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev)
 366 {
 367         struct mlx5_core_health *health = &dev->priv.health;
 368         unsigned long flags;
 369
 370         spin_lock_irqsave(&health->wq_lock, flags);
 371         set_bit(MLX5_DROP_NEW_RECOVERY_WORK, &health->flags);
 372         spin_unlock_irqrestore(&health->wq_lock, flags);
 373         cancel_delayed_work_sync(&dev->priv.health.recover_work);
 374 }
 375
 376 void mlx5_health_cleanup(struct mlx5_core_dev *dev)
 377 {
 378         struct mlx5_core_health *health = &dev->priv.health;
 379
 380         destroy_workqueue(health->wq);
 381 }
 382
 383 int mlx5_health_init(struct mlx5_core_dev *dev)
 384 {
 385         struct mlx5_core_health *health;
 386         char *name;
 387
 388         health = &dev->priv.health;
 389         name = kmalloc(64, GFP_KERNEL);
 390         if (!name)
 391                 return -ENOMEM;
 392
 393         strcpy(name, "mlx5_health");
 394         strcat(name, dev_name(&dev->pdev->dev));
 395         health->wq = create_singlethread_workqueue(name);
 396         kfree(name);
 397         if (!health->wq)
 398                 return -ENOMEM;
 399         spin_lock_init(&health->wq_lock);
 400         INIT_WORK(&health->work, health_care);
 401         INIT_DELAYED_WORK(&health->recover_work, health_recover);
 402
 403         return 0;
 404 }