2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
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8 * OpenIB.org BSD license below:
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11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
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21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/interrupt.h>
34 #include <linux/module.h>
35 #include <linux/mlx5/driver.h>
36 #include <linux/mlx5/cmd.h>
37 #include "mlx5_core.h"
38 #ifdef CONFIG_MLX5_CORE_EN
43 MLX5_EQE_SIZE = sizeof(struct mlx5_eqe),
44 MLX5_EQE_OWNER_INIT_VAL = 0x1,
48 MLX5_EQ_STATE_ARMED = 0x9,
49 MLX5_EQ_STATE_FIRED = 0xa,
50 MLX5_EQ_STATE_ALWAYS_ARMED = 0xb,
54 MLX5_NUM_SPARE_EQE = 0x80,
55 MLX5_NUM_ASYNC_EQE = 0x100,
56 MLX5_NUM_CMD_EQE = 32,
60 MLX5_EQ_DOORBEL_OFFSET = 0x40,
63 #define MLX5_ASYNC_EVENT_MASK ((1ull << MLX5_EVENT_TYPE_PATH_MIG) | \
64 (1ull << MLX5_EVENT_TYPE_COMM_EST) | \
65 (1ull << MLX5_EVENT_TYPE_SQ_DRAINED) | \
66 (1ull << MLX5_EVENT_TYPE_CQ_ERROR) | \
67 (1ull << MLX5_EVENT_TYPE_WQ_CATAS_ERROR) | \
68 (1ull << MLX5_EVENT_TYPE_PATH_MIG_FAILED) | \
69 (1ull << MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
70 (1ull << MLX5_EVENT_TYPE_WQ_ACCESS_ERROR) | \
71 (1ull << MLX5_EVENT_TYPE_PORT_CHANGE) | \
72 (1ull << MLX5_EVENT_TYPE_SRQ_CATAS_ERROR) | \
73 (1ull << MLX5_EVENT_TYPE_SRQ_LAST_WQE) | \
74 (1ull << MLX5_EVENT_TYPE_SRQ_RQ_LIMIT))
87 static int mlx5_cmd_destroy_eq(struct mlx5_core_dev *dev, u8 eqn)
89 u32 out[MLX5_ST_SZ_DW(destroy_eq_out)] = {0};
90 u32 in[MLX5_ST_SZ_DW(destroy_eq_in)] = {0};
92 MLX5_SET(destroy_eq_in, in, opcode, MLX5_CMD_OP_DESTROY_EQ);
93 MLX5_SET(destroy_eq_in, in, eq_number, eqn);
94 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
97 static struct mlx5_eqe *get_eqe(struct mlx5_eq *eq, u32 entry)
99 return mlx5_buf_offset(&eq->buf, entry * MLX5_EQE_SIZE);
102 static struct mlx5_eqe *next_eqe_sw(struct mlx5_eq *eq)
104 struct mlx5_eqe *eqe = get_eqe(eq, eq->cons_index & (eq->nent - 1));
106 return ((eqe->owner & 1) ^ !!(eq->cons_index & eq->nent)) ? NULL : eqe;
109 static const char *eqe_type_str(u8 type)
112 case MLX5_EVENT_TYPE_COMP:
113 return "MLX5_EVENT_TYPE_COMP";
114 case MLX5_EVENT_TYPE_PATH_MIG:
115 return "MLX5_EVENT_TYPE_PATH_MIG";
116 case MLX5_EVENT_TYPE_COMM_EST:
117 return "MLX5_EVENT_TYPE_COMM_EST";
118 case MLX5_EVENT_TYPE_SQ_DRAINED:
119 return "MLX5_EVENT_TYPE_SQ_DRAINED";
120 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
121 return "MLX5_EVENT_TYPE_SRQ_LAST_WQE";
122 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
123 return "MLX5_EVENT_TYPE_SRQ_RQ_LIMIT";
124 case MLX5_EVENT_TYPE_CQ_ERROR:
125 return "MLX5_EVENT_TYPE_CQ_ERROR";
126 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
127 return "MLX5_EVENT_TYPE_WQ_CATAS_ERROR";
128 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
129 return "MLX5_EVENT_TYPE_PATH_MIG_FAILED";
130 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
131 return "MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR";
132 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
133 return "MLX5_EVENT_TYPE_WQ_ACCESS_ERROR";
134 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
135 return "MLX5_EVENT_TYPE_SRQ_CATAS_ERROR";
136 case MLX5_EVENT_TYPE_INTERNAL_ERROR:
137 return "MLX5_EVENT_TYPE_INTERNAL_ERROR";
138 case MLX5_EVENT_TYPE_PORT_CHANGE:
139 return "MLX5_EVENT_TYPE_PORT_CHANGE";
140 case MLX5_EVENT_TYPE_GPIO_EVENT:
141 return "MLX5_EVENT_TYPE_GPIO_EVENT";
142 case MLX5_EVENT_TYPE_PORT_MODULE_EVENT:
143 return "MLX5_EVENT_TYPE_PORT_MODULE_EVENT";
144 case MLX5_EVENT_TYPE_REMOTE_CONFIG:
145 return "MLX5_EVENT_TYPE_REMOTE_CONFIG";
146 case MLX5_EVENT_TYPE_DB_BF_CONGESTION:
147 return "MLX5_EVENT_TYPE_DB_BF_CONGESTION";
148 case MLX5_EVENT_TYPE_STALL_EVENT:
149 return "MLX5_EVENT_TYPE_STALL_EVENT";
150 case MLX5_EVENT_TYPE_CMD:
151 return "MLX5_EVENT_TYPE_CMD";
152 case MLX5_EVENT_TYPE_PAGE_REQUEST:
153 return "MLX5_EVENT_TYPE_PAGE_REQUEST";
154 case MLX5_EVENT_TYPE_PAGE_FAULT:
155 return "MLX5_EVENT_TYPE_PAGE_FAULT";
157 return "Unrecognized event";
161 static enum mlx5_dev_event port_subtype_event(u8 subtype)
164 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
165 return MLX5_DEV_EVENT_PORT_DOWN;
166 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
167 return MLX5_DEV_EVENT_PORT_UP;
168 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
169 return MLX5_DEV_EVENT_PORT_INITIALIZED;
170 case MLX5_PORT_CHANGE_SUBTYPE_LID:
171 return MLX5_DEV_EVENT_LID_CHANGE;
172 case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
173 return MLX5_DEV_EVENT_PKEY_CHANGE;
174 case MLX5_PORT_CHANGE_SUBTYPE_GUID:
175 return MLX5_DEV_EVENT_GUID_CHANGE;
176 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
177 return MLX5_DEV_EVENT_CLIENT_REREG;
182 static void eq_update_ci(struct mlx5_eq *eq, int arm)
184 __be32 __iomem *addr = eq->doorbell + (arm ? 0 : 2);
185 u32 val = (eq->cons_index & 0xffffff) | (eq->eqn << 24);
186 __raw_writel((__force u32) cpu_to_be32(val), addr);
187 /* We still want ordering, just not swabbing, so add a barrier */
191 static int mlx5_eq_int(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
193 struct mlx5_eqe *eqe;
200 while ((eqe = next_eqe_sw(eq))) {
202 * Make sure we read EQ entry contents after we've
203 * checked the ownership bit.
207 mlx5_core_dbg(eq->dev, "eqn %d, eqe type %s\n",
208 eq->eqn, eqe_type_str(eqe->type));
210 case MLX5_EVENT_TYPE_COMP:
211 cqn = be32_to_cpu(eqe->data.comp.cqn) & 0xffffff;
212 mlx5_cq_completion(dev, cqn);
215 case MLX5_EVENT_TYPE_PATH_MIG:
216 case MLX5_EVENT_TYPE_COMM_EST:
217 case MLX5_EVENT_TYPE_SQ_DRAINED:
218 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
219 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
220 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
221 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
222 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
223 rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
224 rsn |= (eqe->data.qp_srq.type << MLX5_USER_INDEX_LEN);
225 mlx5_core_dbg(dev, "event %s(%d) arrived on resource 0x%x\n",
226 eqe_type_str(eqe->type), eqe->type, rsn);
227 mlx5_rsc_event(dev, rsn, eqe->type);
230 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
231 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
232 rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
233 mlx5_core_dbg(dev, "SRQ event %s(%d): srqn 0x%x\n",
234 eqe_type_str(eqe->type), eqe->type, rsn);
235 mlx5_srq_event(dev, rsn, eqe->type);
238 case MLX5_EVENT_TYPE_CMD:
239 mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector));
242 case MLX5_EVENT_TYPE_PORT_CHANGE:
243 port = (eqe->data.port.port >> 4) & 0xf;
244 switch (eqe->sub_type) {
245 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
246 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
247 case MLX5_PORT_CHANGE_SUBTYPE_LID:
248 case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
249 case MLX5_PORT_CHANGE_SUBTYPE_GUID:
250 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
251 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
253 dev->event(dev, port_subtype_event(eqe->sub_type),
254 (unsigned long)port);
257 mlx5_core_warn(dev, "Port event with unrecognized subtype: port %d, sub_type %d\n",
258 port, eqe->sub_type);
261 case MLX5_EVENT_TYPE_CQ_ERROR:
262 cqn = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff;
263 mlx5_core_warn(dev, "CQ error on CQN 0x%x, syndrom 0x%x\n",
264 cqn, eqe->data.cq_err.syndrome);
265 mlx5_cq_event(dev, cqn, eqe->type);
268 case MLX5_EVENT_TYPE_PAGE_REQUEST:
270 u16 func_id = be16_to_cpu(eqe->data.req_pages.func_id);
271 s32 npages = be32_to_cpu(eqe->data.req_pages.num_pages);
273 mlx5_core_dbg(dev, "page request for func 0x%x, npages %d\n",
275 mlx5_core_req_pages_handler(dev, func_id, npages);
279 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
280 case MLX5_EVENT_TYPE_PAGE_FAULT:
281 mlx5_eq_pagefault(dev, eqe);
285 #ifdef CONFIG_MLX5_CORE_EN
286 case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE:
287 mlx5_eswitch_vport_event(dev->priv.eswitch, eqe);
291 case MLX5_EVENT_TYPE_PORT_MODULE_EVENT:
292 mlx5_port_module_event(dev, eqe);
296 mlx5_core_warn(dev, "Unhandled event 0x%x on EQ 0x%x\n",
305 /* The HCA will think the queue has overflowed if we
306 * don't tell it we've been processing events. We
307 * create our EQs with MLX5_NUM_SPARE_EQE extra
308 * entries, so we must update our consumer index at
311 if (unlikely(set_ci >= MLX5_NUM_SPARE_EQE)) {
320 tasklet_schedule(&eq->tasklet_ctx.task);
325 static irqreturn_t mlx5_msix_handler(int irq, void *eq_ptr)
327 struct mlx5_eq *eq = eq_ptr;
328 struct mlx5_core_dev *dev = eq->dev;
330 mlx5_eq_int(dev, eq);
332 /* MSI-X vectors always belong to us */
336 static void init_eq_buf(struct mlx5_eq *eq)
338 struct mlx5_eqe *eqe;
341 for (i = 0; i < eq->nent; i++) {
342 eqe = get_eqe(eq, i);
343 eqe->owner = MLX5_EQE_OWNER_INIT_VAL;
347 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
348 int nent, u64 mask, const char *name, struct mlx5_uar *uar)
350 u32 out[MLX5_ST_SZ_DW(create_eq_out)] = {0};
351 struct mlx5_priv *priv = &dev->priv;
358 eq->nent = roundup_pow_of_two(nent + MLX5_NUM_SPARE_EQE);
360 err = mlx5_buf_alloc(dev, eq->nent * MLX5_EQE_SIZE, &eq->buf);
366 inlen = MLX5_ST_SZ_BYTES(create_eq_in) +
367 MLX5_FLD_SZ_BYTES(create_eq_in, pas[0]) * eq->buf.npages;
369 in = mlx5_vzalloc(inlen);
375 pas = (__be64 *)MLX5_ADDR_OF(create_eq_in, in, pas);
376 mlx5_fill_page_array(&eq->buf, pas);
378 MLX5_SET(create_eq_in, in, opcode, MLX5_CMD_OP_CREATE_EQ);
379 MLX5_SET64(create_eq_in, in, event_bitmask, mask);
381 eqc = MLX5_ADDR_OF(create_eq_in, in, eq_context_entry);
382 MLX5_SET(eqc, eqc, log_eq_size, ilog2(eq->nent));
383 MLX5_SET(eqc, eqc, uar_page, uar->index);
384 MLX5_SET(eqc, eqc, intr, vecidx);
385 MLX5_SET(eqc, eqc, log_page_size,
386 eq->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
388 err = mlx5_cmd_exec(dev, in, inlen, out, sizeof(out));
392 snprintf(priv->irq_info[vecidx].name, MLX5_MAX_IRQ_NAME, "%s@pci:%s",
393 name, pci_name(dev->pdev));
395 eq->eqn = MLX5_GET(create_eq_out, out, eq_number);
396 eq->irqn = priv->msix_arr[vecidx].vector;
398 eq->doorbell = uar->map + MLX5_EQ_DOORBEL_OFFSET;
399 err = request_irq(eq->irqn, mlx5_msix_handler, 0,
400 priv->irq_info[vecidx].name, eq);
404 err = mlx5_debug_eq_add(dev, eq);
408 INIT_LIST_HEAD(&eq->tasklet_ctx.list);
409 INIT_LIST_HEAD(&eq->tasklet_ctx.process_list);
410 spin_lock_init(&eq->tasklet_ctx.lock);
411 tasklet_init(&eq->tasklet_ctx.task, mlx5_cq_tasklet_cb,
412 (unsigned long)&eq->tasklet_ctx);
414 /* EQs are created in ARMED state
422 free_irq(priv->msix_arr[vecidx].vector, eq);
425 mlx5_cmd_destroy_eq(dev, eq->eqn);
431 mlx5_buf_free(dev, &eq->buf);
434 EXPORT_SYMBOL_GPL(mlx5_create_map_eq);
436 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
440 mlx5_debug_eq_remove(dev, eq);
441 free_irq(eq->irqn, eq);
442 err = mlx5_cmd_destroy_eq(dev, eq->eqn);
444 mlx5_core_warn(dev, "failed to destroy a previously created eq: eqn %d\n",
446 synchronize_irq(eq->irqn);
447 tasklet_disable(&eq->tasklet_ctx.task);
448 mlx5_buf_free(dev, &eq->buf);
452 EXPORT_SYMBOL_GPL(mlx5_destroy_unmap_eq);
454 u32 mlx5_get_msix_vec(struct mlx5_core_dev *dev, int vecidx)
456 return dev->priv.msix_arr[MLX5_EQ_VEC_ASYNC].vector;
459 int mlx5_eq_init(struct mlx5_core_dev *dev)
463 spin_lock_init(&dev->priv.eq_table.lock);
465 err = mlx5_eq_debugfs_init(dev);
471 void mlx5_eq_cleanup(struct mlx5_core_dev *dev)
473 mlx5_eq_debugfs_cleanup(dev);
476 int mlx5_start_eqs(struct mlx5_core_dev *dev)
478 struct mlx5_eq_table *table = &dev->priv.eq_table;
479 u64 async_event_mask = MLX5_ASYNC_EVENT_MASK;
482 if (MLX5_CAP_GEN(dev, pg))
483 async_event_mask |= (1ull << MLX5_EVENT_TYPE_PAGE_FAULT);
485 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH &&
486 MLX5_CAP_GEN(dev, vport_group_manager) &&
487 mlx5_core_is_pf(dev))
488 async_event_mask |= (1ull << MLX5_EVENT_TYPE_NIC_VPORT_CHANGE);
490 if (MLX5_CAP_GEN(dev, port_module_event))
491 async_event_mask |= (1ull << MLX5_EVENT_TYPE_PORT_MODULE_EVENT);
493 mlx5_core_dbg(dev, "port_module_event is not set\n");
495 err = mlx5_create_map_eq(dev, &table->cmd_eq, MLX5_EQ_VEC_CMD,
496 MLX5_NUM_CMD_EQE, 1ull << MLX5_EVENT_TYPE_CMD,
497 "mlx5_cmd_eq", &dev->priv.uuari.uars[0]);
499 mlx5_core_warn(dev, "failed to create cmd EQ %d\n", err);
503 mlx5_cmd_use_events(dev);
505 err = mlx5_create_map_eq(dev, &table->async_eq, MLX5_EQ_VEC_ASYNC,
506 MLX5_NUM_ASYNC_EQE, async_event_mask,
507 "mlx5_async_eq", &dev->priv.uuari.uars[0]);
509 mlx5_core_warn(dev, "failed to create async EQ %d\n", err);
513 err = mlx5_create_map_eq(dev, &table->pages_eq,
515 /* TODO: sriov max_vf + */ 1,
516 1 << MLX5_EVENT_TYPE_PAGE_REQUEST, "mlx5_pages_eq",
517 &dev->priv.uuari.uars[0]);
519 mlx5_core_warn(dev, "failed to create pages EQ %d\n", err);
526 mlx5_destroy_unmap_eq(dev, &table->async_eq);
529 mlx5_cmd_use_polling(dev);
530 mlx5_destroy_unmap_eq(dev, &table->cmd_eq);
534 int mlx5_stop_eqs(struct mlx5_core_dev *dev)
536 struct mlx5_eq_table *table = &dev->priv.eq_table;
539 err = mlx5_destroy_unmap_eq(dev, &table->pages_eq);
543 mlx5_destroy_unmap_eq(dev, &table->async_eq);
544 mlx5_cmd_use_polling(dev);
546 err = mlx5_destroy_unmap_eq(dev, &table->cmd_eq);
548 mlx5_cmd_use_events(dev);
553 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
554 u32 *out, int outlen)
556 u32 in[MLX5_ST_SZ_DW(query_eq_in)] = {0};
558 MLX5_SET(query_eq_in, in, opcode, MLX5_CMD_OP_QUERY_EQ);
559 MLX5_SET(query_eq_in, in, eq_number, eq->eqn);
560 return mlx5_cmd_exec(dev, in, sizeof(in), out, outlen);
562 EXPORT_SYMBOL_GPL(mlx5_core_eq_query);