net/mlx5: Add a blank line after declarations
[sfrench/cifs-2.6.git] / drivers / net / ethernet / mellanox / mlx5 / core / eq.c
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32
33 #include <linux/interrupt.h>
34 #include <linux/module.h>
35 #include <linux/mlx5/driver.h>
36 #include <linux/mlx5/cmd.h>
37 #include "mlx5_core.h"
38 #include "fpga/core.h"
39 #include "eswitch.h"
40
41 enum {
42         MLX5_EQE_SIZE           = sizeof(struct mlx5_eqe),
43         MLX5_EQE_OWNER_INIT_VAL = 0x1,
44 };
45
46 enum {
47         MLX5_EQ_STATE_ARMED             = 0x9,
48         MLX5_EQ_STATE_FIRED             = 0xa,
49         MLX5_EQ_STATE_ALWAYS_ARMED      = 0xb,
50 };
51
52 enum {
53         MLX5_NUM_SPARE_EQE      = 0x80,
54         MLX5_NUM_ASYNC_EQE      = 0x100,
55         MLX5_NUM_CMD_EQE        = 32,
56         MLX5_NUM_PF_DRAIN       = 64,
57 };
58
59 enum {
60         MLX5_EQ_DOORBEL_OFFSET  = 0x40,
61 };
62
63 #define MLX5_ASYNC_EVENT_MASK ((1ull << MLX5_EVENT_TYPE_PATH_MIG)           | \
64                                (1ull << MLX5_EVENT_TYPE_COMM_EST)           | \
65                                (1ull << MLX5_EVENT_TYPE_SQ_DRAINED)         | \
66                                (1ull << MLX5_EVENT_TYPE_CQ_ERROR)           | \
67                                (1ull << MLX5_EVENT_TYPE_WQ_CATAS_ERROR)     | \
68                                (1ull << MLX5_EVENT_TYPE_PATH_MIG_FAILED)    | \
69                                (1ull << MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
70                                (1ull << MLX5_EVENT_TYPE_WQ_ACCESS_ERROR)    | \
71                                (1ull << MLX5_EVENT_TYPE_PORT_CHANGE)        | \
72                                (1ull << MLX5_EVENT_TYPE_SRQ_CATAS_ERROR)    | \
73                                (1ull << MLX5_EVENT_TYPE_SRQ_LAST_WQE)       | \
74                                (1ull << MLX5_EVENT_TYPE_SRQ_RQ_LIMIT))
75
76 struct map_eq_in {
77         u64     mask;
78         u32     reserved;
79         u32     unmap_eqn;
80 };
81
82 struct cre_des_eq {
83         u8      reserved[15];
84         u8      eqn;
85 };
86
87 static int mlx5_cmd_destroy_eq(struct mlx5_core_dev *dev, u8 eqn)
88 {
89         u32 out[MLX5_ST_SZ_DW(destroy_eq_out)] = {0};
90         u32 in[MLX5_ST_SZ_DW(destroy_eq_in)]   = {0};
91
92         MLX5_SET(destroy_eq_in, in, opcode, MLX5_CMD_OP_DESTROY_EQ);
93         MLX5_SET(destroy_eq_in, in, eq_number, eqn);
94         return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
95 }
96
97 static struct mlx5_eqe *get_eqe(struct mlx5_eq *eq, u32 entry)
98 {
99         return mlx5_buf_offset(&eq->buf, entry * MLX5_EQE_SIZE);
100 }
101
102 static struct mlx5_eqe *next_eqe_sw(struct mlx5_eq *eq)
103 {
104         struct mlx5_eqe *eqe = get_eqe(eq, eq->cons_index & (eq->nent - 1));
105
106         return ((eqe->owner & 1) ^ !!(eq->cons_index & eq->nent)) ? NULL : eqe;
107 }
108
109 static const char *eqe_type_str(u8 type)
110 {
111         switch (type) {
112         case MLX5_EVENT_TYPE_COMP:
113                 return "MLX5_EVENT_TYPE_COMP";
114         case MLX5_EVENT_TYPE_PATH_MIG:
115                 return "MLX5_EVENT_TYPE_PATH_MIG";
116         case MLX5_EVENT_TYPE_COMM_EST:
117                 return "MLX5_EVENT_TYPE_COMM_EST";
118         case MLX5_EVENT_TYPE_SQ_DRAINED:
119                 return "MLX5_EVENT_TYPE_SQ_DRAINED";
120         case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
121                 return "MLX5_EVENT_TYPE_SRQ_LAST_WQE";
122         case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
123                 return "MLX5_EVENT_TYPE_SRQ_RQ_LIMIT";
124         case MLX5_EVENT_TYPE_CQ_ERROR:
125                 return "MLX5_EVENT_TYPE_CQ_ERROR";
126         case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
127                 return "MLX5_EVENT_TYPE_WQ_CATAS_ERROR";
128         case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
129                 return "MLX5_EVENT_TYPE_PATH_MIG_FAILED";
130         case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
131                 return "MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR";
132         case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
133                 return "MLX5_EVENT_TYPE_WQ_ACCESS_ERROR";
134         case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
135                 return "MLX5_EVENT_TYPE_SRQ_CATAS_ERROR";
136         case MLX5_EVENT_TYPE_INTERNAL_ERROR:
137                 return "MLX5_EVENT_TYPE_INTERNAL_ERROR";
138         case MLX5_EVENT_TYPE_PORT_CHANGE:
139                 return "MLX5_EVENT_TYPE_PORT_CHANGE";
140         case MLX5_EVENT_TYPE_GPIO_EVENT:
141                 return "MLX5_EVENT_TYPE_GPIO_EVENT";
142         case MLX5_EVENT_TYPE_PORT_MODULE_EVENT:
143                 return "MLX5_EVENT_TYPE_PORT_MODULE_EVENT";
144         case MLX5_EVENT_TYPE_REMOTE_CONFIG:
145                 return "MLX5_EVENT_TYPE_REMOTE_CONFIG";
146         case MLX5_EVENT_TYPE_DB_BF_CONGESTION:
147                 return "MLX5_EVENT_TYPE_DB_BF_CONGESTION";
148         case MLX5_EVENT_TYPE_STALL_EVENT:
149                 return "MLX5_EVENT_TYPE_STALL_EVENT";
150         case MLX5_EVENT_TYPE_CMD:
151                 return "MLX5_EVENT_TYPE_CMD";
152         case MLX5_EVENT_TYPE_PAGE_REQUEST:
153                 return "MLX5_EVENT_TYPE_PAGE_REQUEST";
154         case MLX5_EVENT_TYPE_PAGE_FAULT:
155                 return "MLX5_EVENT_TYPE_PAGE_FAULT";
156         case MLX5_EVENT_TYPE_PPS_EVENT:
157                 return "MLX5_EVENT_TYPE_PPS_EVENT";
158         case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE:
159                 return "MLX5_EVENT_TYPE_NIC_VPORT_CHANGE";
160         case MLX5_EVENT_TYPE_FPGA_ERROR:
161                 return "MLX5_EVENT_TYPE_FPGA_ERROR";
162         default:
163                 return "Unrecognized event";
164         }
165 }
166
167 static enum mlx5_dev_event port_subtype_event(u8 subtype)
168 {
169         switch (subtype) {
170         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
171                 return MLX5_DEV_EVENT_PORT_DOWN;
172         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
173                 return MLX5_DEV_EVENT_PORT_UP;
174         case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
175                 return MLX5_DEV_EVENT_PORT_INITIALIZED;
176         case MLX5_PORT_CHANGE_SUBTYPE_LID:
177                 return MLX5_DEV_EVENT_LID_CHANGE;
178         case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
179                 return MLX5_DEV_EVENT_PKEY_CHANGE;
180         case MLX5_PORT_CHANGE_SUBTYPE_GUID:
181                 return MLX5_DEV_EVENT_GUID_CHANGE;
182         case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
183                 return MLX5_DEV_EVENT_CLIENT_REREG;
184         }
185         return -1;
186 }
187
188 static void eq_update_ci(struct mlx5_eq *eq, int arm)
189 {
190         __be32 __iomem *addr = eq->doorbell + (arm ? 0 : 2);
191
192         u32 val = (eq->cons_index & 0xffffff) | (eq->eqn << 24);
193         __raw_writel((__force u32)cpu_to_be32(val), addr);
194         /* We still want ordering, just not swabbing, so add a barrier */
195         mb();
196 }
197
198 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
199 static void eqe_pf_action(struct work_struct *work)
200 {
201         struct mlx5_pagefault *pfault = container_of(work,
202                                                      struct mlx5_pagefault,
203                                                      work);
204         struct mlx5_eq *eq = pfault->eq;
205
206         mlx5_core_page_fault(eq->dev, pfault);
207         mempool_free(pfault, eq->pf_ctx.pool);
208 }
209
210 static void eq_pf_process(struct mlx5_eq *eq)
211 {
212         struct mlx5_core_dev *dev = eq->dev;
213         struct mlx5_eqe_page_fault *pf_eqe;
214         struct mlx5_pagefault *pfault;
215         struct mlx5_eqe *eqe;
216         int set_ci = 0;
217
218         while ((eqe = next_eqe_sw(eq))) {
219                 pfault = mempool_alloc(eq->pf_ctx.pool, GFP_ATOMIC);
220                 if (!pfault) {
221                         schedule_work(&eq->pf_ctx.work);
222                         break;
223                 }
224
225                 dma_rmb();
226                 pf_eqe = &eqe->data.page_fault;
227                 pfault->event_subtype = eqe->sub_type;
228                 pfault->bytes_committed = be32_to_cpu(pf_eqe->bytes_committed);
229
230                 mlx5_core_dbg(dev,
231                               "PAGE_FAULT: subtype: 0x%02x, bytes_committed: 0x%06x\n",
232                               eqe->sub_type, pfault->bytes_committed);
233
234                 switch (eqe->sub_type) {
235                 case MLX5_PFAULT_SUBTYPE_RDMA:
236                         /* RDMA based event */
237                         pfault->type =
238                                 be32_to_cpu(pf_eqe->rdma.pftype_token) >> 24;
239                         pfault->token =
240                                 be32_to_cpu(pf_eqe->rdma.pftype_token) &
241                                 MLX5_24BIT_MASK;
242                         pfault->rdma.r_key =
243                                 be32_to_cpu(pf_eqe->rdma.r_key);
244                         pfault->rdma.packet_size =
245                                 be16_to_cpu(pf_eqe->rdma.packet_length);
246                         pfault->rdma.rdma_op_len =
247                                 be32_to_cpu(pf_eqe->rdma.rdma_op_len);
248                         pfault->rdma.rdma_va =
249                                 be64_to_cpu(pf_eqe->rdma.rdma_va);
250                         mlx5_core_dbg(dev,
251                                       "PAGE_FAULT: type:0x%x, token: 0x%06x, r_key: 0x%08x\n",
252                                       pfault->type, pfault->token,
253                                       pfault->rdma.r_key);
254                         mlx5_core_dbg(dev,
255                                       "PAGE_FAULT: rdma_op_len: 0x%08x, rdma_va: 0x%016llx\n",
256                                       pfault->rdma.rdma_op_len,
257                                       pfault->rdma.rdma_va);
258                         break;
259
260                 case MLX5_PFAULT_SUBTYPE_WQE:
261                         /* WQE based event */
262                         pfault->type =
263                                 be32_to_cpu(pf_eqe->wqe.pftype_wq) >> 24;
264                         pfault->token =
265                                 be32_to_cpu(pf_eqe->wqe.token);
266                         pfault->wqe.wq_num =
267                                 be32_to_cpu(pf_eqe->wqe.pftype_wq) &
268                                 MLX5_24BIT_MASK;
269                         pfault->wqe.wqe_index =
270                                 be16_to_cpu(pf_eqe->wqe.wqe_index);
271                         pfault->wqe.packet_size =
272                                 be16_to_cpu(pf_eqe->wqe.packet_length);
273                         mlx5_core_dbg(dev,
274                                       "PAGE_FAULT: type:0x%x, token: 0x%06x, wq_num: 0x%06x, wqe_index: 0x%04x\n",
275                                       pfault->type, pfault->token,
276                                       pfault->wqe.wq_num,
277                                       pfault->wqe.wqe_index);
278                         break;
279
280                 default:
281                         mlx5_core_warn(dev,
282                                        "Unsupported page fault event sub-type: 0x%02hhx\n",
283                                        eqe->sub_type);
284                         /* Unsupported page faults should still be
285                          * resolved by the page fault handler
286                          */
287                 }
288
289                 pfault->eq = eq;
290                 INIT_WORK(&pfault->work, eqe_pf_action);
291                 queue_work(eq->pf_ctx.wq, &pfault->work);
292
293                 ++eq->cons_index;
294                 ++set_ci;
295
296                 if (unlikely(set_ci >= MLX5_NUM_SPARE_EQE)) {
297                         eq_update_ci(eq, 0);
298                         set_ci = 0;
299                 }
300         }
301
302         eq_update_ci(eq, 1);
303 }
304
305 static irqreturn_t mlx5_eq_pf_int(int irq, void *eq_ptr)
306 {
307         struct mlx5_eq *eq = eq_ptr;
308         unsigned long flags;
309
310         if (spin_trylock_irqsave(&eq->pf_ctx.lock, flags)) {
311                 eq_pf_process(eq);
312                 spin_unlock_irqrestore(&eq->pf_ctx.lock, flags);
313         } else {
314                 schedule_work(&eq->pf_ctx.work);
315         }
316
317         return IRQ_HANDLED;
318 }
319
320 /* mempool_refill() was proposed but unfortunately wasn't accepted
321  * http://lkml.iu.edu/hypermail/linux/kernel/1512.1/05073.html
322  * Chip workaround.
323  */
324 static void mempool_refill(mempool_t *pool)
325 {
326         while (pool->curr_nr < pool->min_nr)
327                 mempool_free(mempool_alloc(pool, GFP_KERNEL), pool);
328 }
329
330 static void eq_pf_action(struct work_struct *work)
331 {
332         struct mlx5_eq *eq = container_of(work, struct mlx5_eq, pf_ctx.work);
333
334         mempool_refill(eq->pf_ctx.pool);
335
336         spin_lock_irq(&eq->pf_ctx.lock);
337         eq_pf_process(eq);
338         spin_unlock_irq(&eq->pf_ctx.lock);
339 }
340
341 static int init_pf_ctx(struct mlx5_eq_pagefault *pf_ctx, const char *name)
342 {
343         spin_lock_init(&pf_ctx->lock);
344         INIT_WORK(&pf_ctx->work, eq_pf_action);
345
346         pf_ctx->wq = alloc_ordered_workqueue(name,
347                                              WQ_MEM_RECLAIM);
348         if (!pf_ctx->wq)
349                 return -ENOMEM;
350
351         pf_ctx->pool = mempool_create_kmalloc_pool
352                 (MLX5_NUM_PF_DRAIN, sizeof(struct mlx5_pagefault));
353         if (!pf_ctx->pool)
354                 goto err_wq;
355
356         return 0;
357 err_wq:
358         destroy_workqueue(pf_ctx->wq);
359         return -ENOMEM;
360 }
361
362 int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 token,
363                                 u32 wq_num, u8 type, int error)
364 {
365         u32 out[MLX5_ST_SZ_DW(page_fault_resume_out)] = {0};
366         u32 in[MLX5_ST_SZ_DW(page_fault_resume_in)]   = {0};
367
368         MLX5_SET(page_fault_resume_in, in, opcode,
369                  MLX5_CMD_OP_PAGE_FAULT_RESUME);
370         MLX5_SET(page_fault_resume_in, in, error, !!error);
371         MLX5_SET(page_fault_resume_in, in, page_fault_type, type);
372         MLX5_SET(page_fault_resume_in, in, wq_number, wq_num);
373         MLX5_SET(page_fault_resume_in, in, token, token);
374
375         return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
376 }
377 EXPORT_SYMBOL_GPL(mlx5_core_page_fault_resume);
378 #endif
379
380 static irqreturn_t mlx5_eq_int(int irq, void *eq_ptr)
381 {
382         struct mlx5_eq *eq = eq_ptr;
383         struct mlx5_core_dev *dev = eq->dev;
384         struct mlx5_eqe *eqe;
385         int set_ci = 0;
386         u32 cqn = -1;
387         u32 rsn;
388         u8 port;
389
390         while ((eqe = next_eqe_sw(eq))) {
391                 /*
392                  * Make sure we read EQ entry contents after we've
393                  * checked the ownership bit.
394                  */
395                 dma_rmb();
396
397                 mlx5_core_dbg(eq->dev, "eqn %d, eqe type %s\n",
398                               eq->eqn, eqe_type_str(eqe->type));
399                 switch (eqe->type) {
400                 case MLX5_EVENT_TYPE_COMP:
401                         cqn = be32_to_cpu(eqe->data.comp.cqn) & 0xffffff;
402                         mlx5_cq_completion(dev, cqn);
403                         break;
404
405                 case MLX5_EVENT_TYPE_PATH_MIG:
406                 case MLX5_EVENT_TYPE_COMM_EST:
407                 case MLX5_EVENT_TYPE_SQ_DRAINED:
408                 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
409                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
410                 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
411                 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
412                 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
413                         rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
414                         rsn |= (eqe->data.qp_srq.type << MLX5_USER_INDEX_LEN);
415                         mlx5_core_dbg(dev, "event %s(%d) arrived on resource 0x%x\n",
416                                       eqe_type_str(eqe->type), eqe->type, rsn);
417                         mlx5_rsc_event(dev, rsn, eqe->type);
418                         break;
419
420                 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
421                 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
422                         rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
423                         mlx5_core_dbg(dev, "SRQ event %s(%d): srqn 0x%x\n",
424                                       eqe_type_str(eqe->type), eqe->type, rsn);
425                         mlx5_srq_event(dev, rsn, eqe->type);
426                         break;
427
428                 case MLX5_EVENT_TYPE_CMD:
429                         mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector), false);
430                         break;
431
432                 case MLX5_EVENT_TYPE_PORT_CHANGE:
433                         port = (eqe->data.port.port >> 4) & 0xf;
434                         switch (eqe->sub_type) {
435                         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
436                         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
437                         case MLX5_PORT_CHANGE_SUBTYPE_LID:
438                         case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
439                         case MLX5_PORT_CHANGE_SUBTYPE_GUID:
440                         case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
441                         case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
442                                 if (dev->event)
443                                         dev->event(dev, port_subtype_event(eqe->sub_type),
444                                                    (unsigned long)port);
445                                 break;
446                         default:
447                                 mlx5_core_warn(dev, "Port event with unrecognized subtype: port %d, sub_type %d\n",
448                                                port, eqe->sub_type);
449                         }
450                         break;
451                 case MLX5_EVENT_TYPE_CQ_ERROR:
452                         cqn = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff;
453                         mlx5_core_warn(dev, "CQ error on CQN 0x%x, syndrom 0x%x\n",
454                                        cqn, eqe->data.cq_err.syndrome);
455                         mlx5_cq_event(dev, cqn, eqe->type);
456                         break;
457
458                 case MLX5_EVENT_TYPE_PAGE_REQUEST:
459                         {
460                                 u16 func_id = be16_to_cpu(eqe->data.req_pages.func_id);
461                                 s32 npages = be32_to_cpu(eqe->data.req_pages.num_pages);
462
463                                 mlx5_core_dbg(dev, "page request for func 0x%x, npages %d\n",
464                                               func_id, npages);
465                                 mlx5_core_req_pages_handler(dev, func_id, npages);
466                         }
467                         break;
468
469                 case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE:
470                         mlx5_eswitch_vport_event(dev->priv.eswitch, eqe);
471                         break;
472
473                 case MLX5_EVENT_TYPE_PORT_MODULE_EVENT:
474                         mlx5_port_module_event(dev, eqe);
475                         break;
476
477                 case MLX5_EVENT_TYPE_PPS_EVENT:
478                         if (dev->event)
479                                 dev->event(dev, MLX5_DEV_EVENT_PPS, (unsigned long)eqe);
480                         break;
481
482                 case MLX5_EVENT_TYPE_FPGA_ERROR:
483                         mlx5_fpga_event(dev, eqe->type, &eqe->data.raw);
484                         break;
485
486                 default:
487                         mlx5_core_warn(dev, "Unhandled event 0x%x on EQ 0x%x\n",
488                                        eqe->type, eq->eqn);
489                         break;
490                 }
491
492                 ++eq->cons_index;
493                 ++set_ci;
494
495                 /* The HCA will think the queue has overflowed if we
496                  * don't tell it we've been processing events.  We
497                  * create our EQs with MLX5_NUM_SPARE_EQE extra
498                  * entries, so we must update our consumer index at
499                  * least that often.
500                  */
501                 if (unlikely(set_ci >= MLX5_NUM_SPARE_EQE)) {
502                         eq_update_ci(eq, 0);
503                         set_ci = 0;
504                 }
505         }
506
507         eq_update_ci(eq, 1);
508
509         if (cqn != -1)
510                 tasklet_schedule(&eq->tasklet_ctx.task);
511
512         return IRQ_HANDLED;
513 }
514
515 static void init_eq_buf(struct mlx5_eq *eq)
516 {
517         struct mlx5_eqe *eqe;
518         int i;
519
520         for (i = 0; i < eq->nent; i++) {
521                 eqe = get_eqe(eq, i);
522                 eqe->owner = MLX5_EQE_OWNER_INIT_VAL;
523         }
524 }
525
526 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
527                        int nent, u64 mask, const char *name,
528                        enum mlx5_eq_type type)
529 {
530         u32 out[MLX5_ST_SZ_DW(create_eq_out)] = {0};
531         struct mlx5_priv *priv = &dev->priv;
532         irq_handler_t handler;
533         __be64 *pas;
534         void *eqc;
535         int inlen;
536         u32 *in;
537         int err;
538
539         eq->type = type;
540         eq->nent = roundup_pow_of_two(nent + MLX5_NUM_SPARE_EQE);
541         eq->cons_index = 0;
542         err = mlx5_buf_alloc(dev, eq->nent * MLX5_EQE_SIZE, &eq->buf);
543         if (err)
544                 return err;
545
546 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
547         if (type == MLX5_EQ_TYPE_PF)
548                 handler = mlx5_eq_pf_int;
549         else
550 #endif
551                 handler = mlx5_eq_int;
552
553         init_eq_buf(eq);
554
555         inlen = MLX5_ST_SZ_BYTES(create_eq_in) +
556                 MLX5_FLD_SZ_BYTES(create_eq_in, pas[0]) * eq->buf.npages;
557
558         in = kvzalloc(inlen, GFP_KERNEL);
559         if (!in) {
560                 err = -ENOMEM;
561                 goto err_buf;
562         }
563
564         pas = (__be64 *)MLX5_ADDR_OF(create_eq_in, in, pas);
565         mlx5_fill_page_array(&eq->buf, pas);
566
567         MLX5_SET(create_eq_in, in, opcode, MLX5_CMD_OP_CREATE_EQ);
568         MLX5_SET64(create_eq_in, in, event_bitmask, mask);
569
570         eqc = MLX5_ADDR_OF(create_eq_in, in, eq_context_entry);
571         MLX5_SET(eqc, eqc, log_eq_size, ilog2(eq->nent));
572         MLX5_SET(eqc, eqc, uar_page, priv->uar->index);
573         MLX5_SET(eqc, eqc, intr, vecidx);
574         MLX5_SET(eqc, eqc, log_page_size,
575                  eq->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
576
577         err = mlx5_cmd_exec(dev, in, inlen, out, sizeof(out));
578         if (err)
579                 goto err_in;
580
581         snprintf(priv->irq_info[vecidx].name, MLX5_MAX_IRQ_NAME, "%s@pci:%s",
582                  name, pci_name(dev->pdev));
583
584         eq->eqn = MLX5_GET(create_eq_out, out, eq_number);
585         eq->irqn = priv->msix_arr[vecidx].vector;
586         eq->dev = dev;
587         eq->doorbell = priv->uar->map + MLX5_EQ_DOORBEL_OFFSET;
588         err = request_irq(eq->irqn, handler, 0,
589                           priv->irq_info[vecidx].name, eq);
590         if (err)
591                 goto err_eq;
592
593         err = mlx5_debug_eq_add(dev, eq);
594         if (err)
595                 goto err_irq;
596
597 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
598         if (type == MLX5_EQ_TYPE_PF) {
599                 err = init_pf_ctx(&eq->pf_ctx, name);
600                 if (err)
601                         goto err_irq;
602         } else
603 #endif
604         {
605                 INIT_LIST_HEAD(&eq->tasklet_ctx.list);
606                 INIT_LIST_HEAD(&eq->tasklet_ctx.process_list);
607                 spin_lock_init(&eq->tasklet_ctx.lock);
608                 tasklet_init(&eq->tasklet_ctx.task, mlx5_cq_tasklet_cb,
609                              (unsigned long)&eq->tasklet_ctx);
610         }
611
612         /* EQs are created in ARMED state
613          */
614         eq_update_ci(eq, 1);
615
616         kvfree(in);
617         return 0;
618
619 err_irq:
620         free_irq(priv->msix_arr[vecidx].vector, eq);
621
622 err_eq:
623         mlx5_cmd_destroy_eq(dev, eq->eqn);
624
625 err_in:
626         kvfree(in);
627
628 err_buf:
629         mlx5_buf_free(dev, &eq->buf);
630         return err;
631 }
632 EXPORT_SYMBOL_GPL(mlx5_create_map_eq);
633
634 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
635 {
636         int err;
637
638         mlx5_debug_eq_remove(dev, eq);
639         free_irq(eq->irqn, eq);
640         err = mlx5_cmd_destroy_eq(dev, eq->eqn);
641         if (err)
642                 mlx5_core_warn(dev, "failed to destroy a previously created eq: eqn %d\n",
643                                eq->eqn);
644         synchronize_irq(eq->irqn);
645
646         if (eq->type == MLX5_EQ_TYPE_COMP) {
647                 tasklet_disable(&eq->tasklet_ctx.task);
648 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
649         } else if (eq->type == MLX5_EQ_TYPE_PF) {
650                 cancel_work_sync(&eq->pf_ctx.work);
651                 destroy_workqueue(eq->pf_ctx.wq);
652                 mempool_destroy(eq->pf_ctx.pool);
653 #endif
654         }
655         mlx5_buf_free(dev, &eq->buf);
656
657         return err;
658 }
659 EXPORT_SYMBOL_GPL(mlx5_destroy_unmap_eq);
660
661 u32 mlx5_get_msix_vec(struct mlx5_core_dev *dev, int vecidx)
662 {
663         return dev->priv.msix_arr[MLX5_EQ_VEC_ASYNC].vector;
664 }
665
666 int mlx5_eq_init(struct mlx5_core_dev *dev)
667 {
668         int err;
669
670         spin_lock_init(&dev->priv.eq_table.lock);
671
672         err = mlx5_eq_debugfs_init(dev);
673
674         return err;
675 }
676
677 void mlx5_eq_cleanup(struct mlx5_core_dev *dev)
678 {
679         mlx5_eq_debugfs_cleanup(dev);
680 }
681
682 int mlx5_start_eqs(struct mlx5_core_dev *dev)
683 {
684         struct mlx5_eq_table *table = &dev->priv.eq_table;
685         u64 async_event_mask = MLX5_ASYNC_EVENT_MASK;
686         int err;
687
688         if (MLX5_VPORT_MANAGER(dev))
689                 async_event_mask |= (1ull << MLX5_EVENT_TYPE_NIC_VPORT_CHANGE);
690
691         if (MLX5_CAP_GEN(dev, port_module_event))
692                 async_event_mask |= (1ull << MLX5_EVENT_TYPE_PORT_MODULE_EVENT);
693         else
694                 mlx5_core_dbg(dev, "port_module_event is not set\n");
695
696         if (MLX5_PPS_CAP(dev))
697                 async_event_mask |= (1ull << MLX5_EVENT_TYPE_PPS_EVENT);
698
699         if (MLX5_CAP_GEN(dev, fpga))
700                 async_event_mask |= (1ull << MLX5_EVENT_TYPE_FPGA_ERROR);
701
702         err = mlx5_create_map_eq(dev, &table->cmd_eq, MLX5_EQ_VEC_CMD,
703                                  MLX5_NUM_CMD_EQE, 1ull << MLX5_EVENT_TYPE_CMD,
704                                  "mlx5_cmd_eq", MLX5_EQ_TYPE_ASYNC);
705         if (err) {
706                 mlx5_core_warn(dev, "failed to create cmd EQ %d\n", err);
707                 return err;
708         }
709
710         mlx5_cmd_use_events(dev);
711
712         err = mlx5_create_map_eq(dev, &table->async_eq, MLX5_EQ_VEC_ASYNC,
713                                  MLX5_NUM_ASYNC_EQE, async_event_mask,
714                                  "mlx5_async_eq", MLX5_EQ_TYPE_ASYNC);
715         if (err) {
716                 mlx5_core_warn(dev, "failed to create async EQ %d\n", err);
717                 goto err1;
718         }
719
720         err = mlx5_create_map_eq(dev, &table->pages_eq,
721                                  MLX5_EQ_VEC_PAGES,
722                                  /* TODO: sriov max_vf + */ 1,
723                                  1 << MLX5_EVENT_TYPE_PAGE_REQUEST, "mlx5_pages_eq",
724                                  MLX5_EQ_TYPE_ASYNC);
725         if (err) {
726                 mlx5_core_warn(dev, "failed to create pages EQ %d\n", err);
727                 goto err2;
728         }
729
730 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
731         if (MLX5_CAP_GEN(dev, pg)) {
732                 err = mlx5_create_map_eq(dev, &table->pfault_eq,
733                                          MLX5_EQ_VEC_PFAULT,
734                                          MLX5_NUM_ASYNC_EQE,
735                                          1 << MLX5_EVENT_TYPE_PAGE_FAULT,
736                                          "mlx5_page_fault_eq",
737                                          MLX5_EQ_TYPE_PF);
738                 if (err) {
739                         mlx5_core_warn(dev, "failed to create page fault EQ %d\n",
740                                        err);
741                         goto err3;
742                 }
743         }
744
745         return err;
746 err3:
747         mlx5_destroy_unmap_eq(dev, &table->pages_eq);
748 #else
749         return err;
750 #endif
751
752 err2:
753         mlx5_destroy_unmap_eq(dev, &table->async_eq);
754
755 err1:
756         mlx5_cmd_use_polling(dev);
757         mlx5_destroy_unmap_eq(dev, &table->cmd_eq);
758         return err;
759 }
760
761 int mlx5_stop_eqs(struct mlx5_core_dev *dev)
762 {
763         struct mlx5_eq_table *table = &dev->priv.eq_table;
764         int err;
765
766 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
767         if (MLX5_CAP_GEN(dev, pg)) {
768                 err = mlx5_destroy_unmap_eq(dev, &table->pfault_eq);
769                 if (err)
770                         return err;
771         }
772 #endif
773
774         err = mlx5_destroy_unmap_eq(dev, &table->pages_eq);
775         if (err)
776                 return err;
777
778         mlx5_destroy_unmap_eq(dev, &table->async_eq);
779         mlx5_cmd_use_polling(dev);
780
781         err = mlx5_destroy_unmap_eq(dev, &table->cmd_eq);
782         if (err)
783                 mlx5_cmd_use_events(dev);
784
785         return err;
786 }
787
788 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
789                        u32 *out, int outlen)
790 {
791         u32 in[MLX5_ST_SZ_DW(query_eq_in)] = {0};
792
793         MLX5_SET(query_eq_in, in, opcode, MLX5_CMD_OP_QUERY_EQ);
794         MLX5_SET(query_eq_in, in, eq_number, eq->eqn);
795         return mlx5_cmd_exec(dev, in, sizeof(in), out, outlen);
796 }
797 EXPORT_SYMBOL_GPL(mlx5_core_eq_query);